CPUMAllMsrs.cpp@ 60309

Last change on this file since 60309 was 60307, checked in by vboxsync, 9 years ago
VMM: APIC rewrite. Initial commit, work in progress.
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1	/* $Id: CPUMAllMsrs.cpp 60307 2016-04-04 15:23:11Z vboxsync $ */
2	/** @file
3	* CPUM - CPU MSR Registers.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/pdmapi.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/tm.h>
27	#include <VBox/vmm/gim.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/err.h>
31
32
33	/*********************************************************************************************************************************
34	* Defined Constants And Macros *
35	*********************************************************************************************************************************/
36	/**
37	* Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
38	* pointing to it.
39	*
40	* ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
41	* correctly.
42	*/
43	#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
44	AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
45	&& (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
46	&& !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
47	, ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
48	VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
49	a_Type a_VarName = (a_Type )((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
50
51
52	/*********************************************************************************************************************************
53	* Structures and Typedefs *
54	*********************************************************************************************************************************/
55
56	/**
57	* Implements reading one or more MSRs.
58	*
59	* @returns VBox status code.
60	* @retval VINF_SUCCESS on success.
61	* @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
62	* current context (raw-mode or ring-0).
63	* @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
64	*
65	* @param pVCpu The cross context virtual CPU structure.
66	* @param idMsr The MSR we're reading.
67	* @param pRange The MSR range descriptor.
68	* @param puValue Where to return the value.
69	*/
70	typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
71	/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
72	typedef FNCPUMRDMSR *PFNCPUMRDMSR;
73
74
75	/**
76	* Implements writing one or more MSRs.
77	*
78	* @retval VINF_SUCCESS on success.
79	* @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
80	* current context (raw-mode or ring-0).
81	* @retval VERR_CPUM_RAISE_GP_0 on failure.
82	*
83	* @param pVCpu The cross context virtual CPU structure.
84	* @param idMsr The MSR we're writing.
85	* @param pRange The MSR range descriptor.
86	* @param uValue The value to set, ignored bits masked.
87	* @param uRawValue The raw value with the ignored bits not masked.
88	*/
89	typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
90	/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
91	typedef FNCPUMWRMSR *PFNCPUMWRMSR;
92
93
94
95	/*
96	* Generic functions.
97	* Generic functions.
98	* Generic functions.
99	*/
100
101
102	/** @callback_method_impl{FNCPUMRDMSR} */
103	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
104	{
105	*puValue = pRange->uValue;
106	return VINF_SUCCESS;
107	}
108
109
110	/** @callback_method_impl{FNCPUMWRMSR} */
111	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
112	{
113	Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
114	return VINF_SUCCESS;
115	}
116
117
118	/** @callback_method_impl{FNCPUMRDMSR} */
119	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
120	{
121	return VERR_CPUM_RAISE_GP_0;
122	}
123
124
125	/** @callback_method_impl{FNCPUMWRMSR} */
126	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
127	{
128	Assert(pRange->fWrGpMask == UINT64_MAX);
129	return VERR_CPUM_RAISE_GP_0;
130	}
131
132
133
134
135	/*
136	* IA32
137	* IA32
138	* IA32
139	*/
140
141	/** @callback_method_impl{FNCPUMRDMSR} */
142	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
143	{
144	puValue = 0; /* @todo implement machine check injection. */
145	return VINF_SUCCESS;
146	}
147
148
149	/** @callback_method_impl{FNCPUMWRMSR} */
150	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
151	{
152	/** @todo implement machine check injection. */
153	return VINF_SUCCESS;
154	}
155
156
157	/** @callback_method_impl{FNCPUMRDMSR} */
158	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
159	{
160	puValue = 0; /* @todo implement machine check injection. */
161	return VINF_SUCCESS;
162	}
163
164
165	/** @callback_method_impl{FNCPUMWRMSR} */
166	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
167	{
168	/** @todo implement machine check injection. */
169	return VINF_SUCCESS;
170	}
171
172
173	/** @callback_method_impl{FNCPUMRDMSR} */
174	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
175	{
176	*puValue = TMCpuTickGet(pVCpu);
177	return VINF_SUCCESS;
178	}
179
180
181	/** @callback_method_impl{FNCPUMWRMSR} */
182	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
183	{
184	TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
185	return VINF_SUCCESS;
186	}
187
188
189	/** @callback_method_impl{FNCPUMRDMSR} */
190	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
191	{
192	uint64_t uValue = pRange->uValue;
193	if (uValue & 0x1f00)
194	{
195	/* Max allowed bus ratio present. */
196	/** @todo Implement scaled BUS frequency. */
197	}
198
199	*puValue = uValue;
200	return VINF_SUCCESS;
201	}
202
203
204	/** @callback_method_impl{FNCPUMRDMSR} */
205	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
206	{
207	return PDMApicGetBaseMsr(pVCpu, puValue);
208	}
209
210
211	/** @callback_method_impl{FNCPUMWRMSR} */
212	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
213	{
214	return PDMApicSetBaseMsr(pVCpu, uValue);
215	}
216
217
218	/** @callback_method_impl{FNCPUMRDMSR} */
219	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
220	{
221	puValue = 1; / Locked, no VT-X, no SYSENTER micromanagement. */
222	return VINF_SUCCESS;
223	}
224
225
226	/** @callback_method_impl{FNCPUMWRMSR} */
227	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
228	{
229	return VERR_CPUM_RAISE_GP_0;
230	}
231
232
233	/** @callback_method_impl{FNCPUMRDMSR} */
234	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
235	{
236	/** @todo fake microcode update. */
237	*puValue = pRange->uValue;
238	return VINF_SUCCESS;
239	}
240
241
242	/** @callback_method_impl{FNCPUMWRMSR} */
243	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
244	{
245	/* Normally, zero is written to Ia32BiosSignId before reading it in order
246	to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
247	of the database entry should take care of most illegal writes for now, so
248	just ignore all writes atm. */
249	return VINF_SUCCESS;
250	}
251
252
253	/** @callback_method_impl{FNCPUMWRMSR} */
254	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
255	{
256	/** @todo Fake bios update trigger better. The value is the address to an
257	* update package, I think. We should probably GP if it's invalid. */
258	return VINF_SUCCESS;
259	}
260
261
262	/** @callback_method_impl{FNCPUMRDMSR} */
263	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
264	{
265	/** @todo SMM. */
266	*puValue = 0;
267	return VINF_SUCCESS;
268	}
269
270
271	/** @callback_method_impl{FNCPUMWRMSR} */
272	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
273	{
274	/** @todo SMM. */
275	return VINF_SUCCESS;
276	}
277
278
279	/** @callback_method_impl{FNCPUMRDMSR} */
280	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
281	{
282	/** @todo check CPUID leaf 0ah. */
283	*puValue = 0;
284	return VINF_SUCCESS;
285	}
286
287
288	/** @callback_method_impl{FNCPUMWRMSR} */
289	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
290	{
291	/** @todo check CPUID leaf 0ah. */
292	return VINF_SUCCESS;
293	}
294
295
296	/** @callback_method_impl{FNCPUMRDMSR} */
297	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
298	{
299	/** @todo return 0x1000 if we try emulate mwait 100% correctly. */
300	puValue = 0x40; /* @todo Change to CPU cache line size. */
301	return VINF_SUCCESS;
302	}
303
304
305	/** @callback_method_impl{FNCPUMWRMSR} */
306	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
307	{
308	/** @todo should remember writes, though it's supposedly something only a BIOS
309	* would write so, it's not extremely important. */
310	return VINF_SUCCESS;
311	}
312
313	/** @callback_method_impl{FNCPUMRDMSR} */
314	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
315	{
316	/** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
317	* what we want? */
318	*puValue = TMCpuTickGet(pVCpu);
319	return VINF_SUCCESS;
320	}
321
322
323	/** @callback_method_impl{FNCPUMWRMSR} */
324	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
325	{
326	/** @todo Write MPERF: Calc adjustment. */
327	return VINF_SUCCESS;
328	}
329
330
331	/** @callback_method_impl{FNCPUMRDMSR} */
332	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
333	{
334	/** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
335	* what we want? */
336	*puValue = TMCpuTickGet(pVCpu);
337	return VINF_SUCCESS;
338	}
339
340
341	/** @callback_method_impl{FNCPUMWRMSR} */
342	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
343	{
344	/** @todo Write APERF: Calc adjustment. */
345	return VINF_SUCCESS;
346	}
347
348
349	/** @callback_method_impl{FNCPUMRDMSR} */
350	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
351	{
352	/* This is currently a bit weird. :-) */
353	uint8_t const cVariableRangeRegs = 0;
354	bool const fSystemManagementRangeRegisters = false;
355	bool const fFixedRangeRegisters = false;
356	bool const fWriteCombiningType = false;
357	*puValue = cVariableRangeRegs
358	\| (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
359	\| (fWriteCombiningType ? RT_BIT_64(10) : 0)
360	\| (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
361	return VINF_SUCCESS;
362	}
363
364
365	/** @callback_method_impl{FNCPUMRDMSR} */
366	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
367	{
368	/** @todo Implement variable MTRR storage. */
369	Assert(pRange->uValue == (idMsr - 0x200) / 2);
370	*puValue = 0;
371	return VINF_SUCCESS;
372	}
373
374
375	/** @callback_method_impl{FNCPUMWRMSR} */
376	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
377	{
378	/*
379	* Validate the value.
380	*/
381	Assert(pRange->uValue == (idMsr - 0x200) / 2);
382
383	if ((uValue & 0xff) >= 7)
384	{
385	Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
386	return VERR_CPUM_RAISE_GP_0;
387	}
388
389	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
390	if (fInvPhysMask & uValue)
391	{
392	Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
393	idMsr, uValue, uValue & fInvPhysMask));
394	return VERR_CPUM_RAISE_GP_0;
395	}
396
397	/*
398	* Store it.
399	*/
400	/** @todo Implement variable MTRR storage. */
401	return VINF_SUCCESS;
402	}
403
404
405	/** @callback_method_impl{FNCPUMRDMSR} */
406	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
407	{
408	/** @todo Implement variable MTRR storage. */
409	Assert(pRange->uValue == (idMsr - 0x200) / 2);
410	*puValue = 0;
411	return VINF_SUCCESS;
412	}
413
414
415	/** @callback_method_impl{FNCPUMWRMSR} */
416	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
417	{
418	/*
419	* Validate the value.
420	*/
421	Assert(pRange->uValue == (idMsr - 0x200) / 2);
422
423	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
424	if (fInvPhysMask & uValue)
425	{
426	Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
427	idMsr, uValue, uValue & fInvPhysMask));
428	return VERR_CPUM_RAISE_GP_0;
429	}
430
431	/*
432	* Store it.
433	*/
434	/** @todo Implement variable MTRR storage. */
435	return VINF_SUCCESS;
436	}
437
438
439	/** @callback_method_impl{FNCPUMRDMSR} */
440	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
441	{
442	CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
443	puValue = puFixedMtrr;
444	return VINF_SUCCESS;
445	}
446
447
448	/** @callback_method_impl{FNCPUMWRMSR} */
449	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
450	{
451	CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
452	for (uint32_t cShift = 0; cShift < 63; cShift += 8)
453	{
454	uint8_t uType = (uint8_t)(uValue >> cShift);
455	if (uType >= 7)
456	{
457	Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
458	cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
459	return VERR_CPUM_RAISE_GP_0;
460	}
461	}
462	*puFixedMtrr = uValue;
463	return VINF_SUCCESS;
464	}
465
466
467	/** @callback_method_impl{FNCPUMRDMSR} */
468	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
469	{
470	*puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
471	return VINF_SUCCESS;
472	}
473
474
475	/** @callback_method_impl{FNCPUMWRMSR} */
476	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
477	{
478	if ((uValue & 0xff) >= 7)
479	{
480	Log(("CPUM: Invalid MTRR default type value on %s: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
481	return VERR_CPUM_RAISE_GP_0;
482	}
483
484	pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
485	return VINF_SUCCESS;
486	}
487
488
489	/** @callback_method_impl{FNCPUMRDMSR} */
490	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
491	{
492	*puValue = pVCpu->cpum.s.Guest.msrPAT;
493	return VINF_SUCCESS;
494	}
495
496
497	/** @callback_method_impl{FNCPUMWRMSR} */
498	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
499	{
500	pVCpu->cpum.s.Guest.msrPAT = uValue;
501	return VINF_SUCCESS;
502	}
503
504
505	/** @callback_method_impl{FNCPUMRDMSR} */
506	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
507	{
508	*puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
509	return VINF_SUCCESS;
510	}
511
512
513	/** @callback_method_impl{FNCPUMWRMSR} */
514	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
515	{
516	/* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
517	there are generally 32-bit working bits backing this register. */
518	pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
519	return VINF_SUCCESS;
520	}
521
522
523	/** @callback_method_impl{FNCPUMRDMSR} */
524	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
525	{
526	*puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
527	return VINF_SUCCESS;
528	}
529
530
531	/** @callback_method_impl{FNCPUMWRMSR} */
532	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
533	{
534	if (X86_IS_CANONICAL(uValue))
535	{
536	pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
537	return VINF_SUCCESS;
538	}
539	Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
540	return VERR_CPUM_RAISE_GP_0;
541	}
542
543
544	/** @callback_method_impl{FNCPUMRDMSR} */
545	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
546	{
547	*puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
548	return VINF_SUCCESS;
549	}
550
551
552	/** @callback_method_impl{FNCPUMWRMSR} */
553	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
554	{
555	if (X86_IS_CANONICAL(uValue))
556	{
557	pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
558	return VINF_SUCCESS;
559	}
560	#ifdef IN_RING3
561	LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
562	#else
563	Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
564	#endif
565	return VERR_CPUM_RAISE_GP_0;
566	}
567
568
569	/** @callback_method_impl{FNCPUMRDMSR} */
570	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
571	{
572	#if 0 /** @todo implement machine checks. */
573	*puValue = pRange->uValue & (RT_BIT_64(8) \| 0);
574	#else
575	*puValue = 0;
576	#endif
577	return VINF_SUCCESS;
578	}
579
580
581	/** @callback_method_impl{FNCPUMRDMSR} */
582	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
583	{
584	/** @todo implement machine checks. */
585	*puValue = 0;
586	return VINF_SUCCESS;
587	}
588
589
590	/** @callback_method_impl{FNCPUMWRMSR} */
591	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
592	{
593	/** @todo implement machine checks. */
594	return VINF_SUCCESS;
595	}
596
597
598	/** @callback_method_impl{FNCPUMRDMSR} */
599	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
600	{
601	/** @todo implement machine checks. */
602	*puValue = 0;
603	return VINF_SUCCESS;
604	}
605
606
607	/** @callback_method_impl{FNCPUMWRMSR} */
608	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
609	{
610	/** @todo implement machine checks. */
611	return VINF_SUCCESS;
612	}
613
614
615	/** @callback_method_impl{FNCPUMRDMSR} */
616	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
617	{
618	/** @todo implement IA32_DEBUGCTL. */
619	*puValue = 0;
620	return VINF_SUCCESS;
621	}
622
623
624	/** @callback_method_impl{FNCPUMWRMSR} */
625	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
626	{
627	/** @todo implement IA32_DEBUGCTL. */
628	return VINF_SUCCESS;
629	}
630
631
632	/** @callback_method_impl{FNCPUMRDMSR} */
633	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
634	{
635	/** @todo implement intel SMM. */
636	*puValue = 0;
637	return VINF_SUCCESS;
638	}
639
640
641	/** @callback_method_impl{FNCPUMWRMSR} */
642	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
643	{
644	/** @todo implement intel SMM. */
645	return VERR_CPUM_RAISE_GP_0;
646	}
647
648
649	/** @callback_method_impl{FNCPUMRDMSR} */
650	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
651	{
652	/** @todo implement intel SMM. */
653	*puValue = 0;
654	return VINF_SUCCESS;
655	}
656
657
658	/** @callback_method_impl{FNCPUMWRMSR} */
659	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
660	{
661	/** @todo implement intel SMM. */
662	return VERR_CPUM_RAISE_GP_0;
663	}
664
665
666	/** @callback_method_impl{FNCPUMRDMSR} */
667	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
668	{
669	/** @todo implement intel direct cache access (DCA)?? */
670	*puValue = 0;
671	return VINF_SUCCESS;
672	}
673
674
675	/** @callback_method_impl{FNCPUMWRMSR} */
676	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
677	{
678	/** @todo implement intel direct cache access (DCA)?? */
679	return VINF_SUCCESS;
680	}
681
682
683	/** @callback_method_impl{FNCPUMRDMSR} */
684	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
685	{
686	/** @todo implement intel direct cache access (DCA)?? */
687	*puValue = 0;
688	return VINF_SUCCESS;
689	}
690
691
692	/** @callback_method_impl{FNCPUMRDMSR} */
693	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
694	{
695	/** @todo implement intel direct cache access (DCA)?? */
696	*puValue = 0;
697	return VINF_SUCCESS;
698	}
699
700
701	/** @callback_method_impl{FNCPUMWRMSR} */
702	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
703	{
704	/** @todo implement intel direct cache access (DCA)?? */
705	return VINF_SUCCESS;
706	}
707
708
709	/** @callback_method_impl{FNCPUMRDMSR} */
710	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
711	{
712	/** @todo implement IA32_PERFEVTSEL0+. */
713	*puValue = 0;
714	return VINF_SUCCESS;
715	}
716
717
718	/** @callback_method_impl{FNCPUMWRMSR} */
719	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
720	{
721	/** @todo implement IA32_PERFEVTSEL0+. */
722	return VINF_SUCCESS;
723	}
724
725
726	/** @callback_method_impl{FNCPUMRDMSR} */
727	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
728	{
729	uint64_t uValue = pRange->uValue;
730
731	/* Always provide the max bus ratio for now. XNU expects it. */
732	uValue &= ~((UINT64_C(0x1f) << 40) \| RT_BIT_64(46));
733
734	PVM pVM = pVCpu->CTX_SUFF(pVM);
735	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
736	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
737	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
738	if (uTscRatio > 0x1f)
739	uTscRatio = 0x1f;
740	uValue \|= (uint64_t)uTscRatio << 40;
741
742	*puValue = uValue;
743	return VINF_SUCCESS;
744	}
745
746
747	/** @callback_method_impl{FNCPUMWRMSR} */
748	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
749	{
750	/* Pentium4 allows writing, but all bits are ignored. */
751	return VINF_SUCCESS;
752	}
753
754
755	/** @callback_method_impl{FNCPUMRDMSR} */
756	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
757	{
758	/** @todo implement IA32_PERFCTL. */
759	*puValue = 0;
760	return VINF_SUCCESS;
761	}
762
763
764	/** @callback_method_impl{FNCPUMWRMSR} */
765	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
766	{
767	/** @todo implement IA32_PERFCTL. */
768	return VINF_SUCCESS;
769	}
770
771
772	/** @callback_method_impl{FNCPUMRDMSR} */
773	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
774	{
775	/** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
776	*puValue = 0;
777	return VINF_SUCCESS;
778	}
779
780
781	/** @callback_method_impl{FNCPUMWRMSR} */
782	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
783	{
784	/** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
785	return VINF_SUCCESS;
786	}
787
788
789	/** @callback_method_impl{FNCPUMRDMSR} */
790	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
791	{
792	/** @todo implement performance counters. */
793	*puValue = 0;
794	return VINF_SUCCESS;
795	}
796
797
798	/** @callback_method_impl{FNCPUMWRMSR} */
799	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
800	{
801	/** @todo implement performance counters. */
802	return VINF_SUCCESS;
803	}
804
805
806	/** @callback_method_impl{FNCPUMRDMSR} */
807	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
808	{
809	/** @todo implement performance counters. */
810	*puValue = 0;
811	return VINF_SUCCESS;
812	}
813
814
815	/** @callback_method_impl{FNCPUMWRMSR} */
816	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
817	{
818	/** @todo implement performance counters. */
819	return VINF_SUCCESS;
820	}
821
822
823	/** @callback_method_impl{FNCPUMRDMSR} */
824	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
825	{
826	/** @todo implement performance counters. */
827	*puValue = 0;
828	return VINF_SUCCESS;
829	}
830
831
832	/** @callback_method_impl{FNCPUMWRMSR} */
833	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
834	{
835	/** @todo implement performance counters. */
836	return VINF_SUCCESS;
837	}
838
839
840	/** @callback_method_impl{FNCPUMRDMSR} */
841	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
842	{
843	/** @todo implement performance counters. */
844	*puValue = 0;
845	return VINF_SUCCESS;
846	}
847
848
849	/** @callback_method_impl{FNCPUMWRMSR} */
850	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
851	{
852	/** @todo implement performance counters. */
853	return VINF_SUCCESS;
854	}
855
856
857	/** @callback_method_impl{FNCPUMRDMSR} */
858	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
859	{
860	/** @todo implement performance counters. */
861	*puValue = 0;
862	return VINF_SUCCESS;
863	}
864
865
866	/** @callback_method_impl{FNCPUMWRMSR} */
867	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
868	{
869	/** @todo implement performance counters. */
870	return VINF_SUCCESS;
871	}
872
873
874	/** @callback_method_impl{FNCPUMRDMSR} */
875	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
876	{
877	/** @todo implement performance counters. */
878	*puValue = 0;
879	return VINF_SUCCESS;
880	}
881
882
883	/** @callback_method_impl{FNCPUMWRMSR} */
884	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
885	{
886	/** @todo implement performance counters. */
887	return VINF_SUCCESS;
888	}
889
890
891	/** @callback_method_impl{FNCPUMRDMSR} */
892	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
893	{
894	/** @todo implement IA32_CLOCK_MODULATION. */
895	*puValue = 0;
896	return VINF_SUCCESS;
897	}
898
899
900	/** @callback_method_impl{FNCPUMWRMSR} */
901	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
902	{
903	/** @todo implement IA32_CLOCK_MODULATION. */
904	return VINF_SUCCESS;
905	}
906
907
908	/** @callback_method_impl{FNCPUMRDMSR} */
909	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
910	{
911	/** @todo implement IA32_THERM_INTERRUPT. */
912	*puValue = 0;
913	return VINF_SUCCESS;
914	}
915
916
917	/** @callback_method_impl{FNCPUMWRMSR} */
918	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
919	{
920	/** @todo implement IA32_THERM_STATUS. */
921	return VINF_SUCCESS;
922	}
923
924
925	/** @callback_method_impl{FNCPUMRDMSR} */
926	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
927	{
928	/** @todo implement IA32_THERM_STATUS. */
929	*puValue = 0;
930	return VINF_SUCCESS;
931	}
932
933
934	/** @callback_method_impl{FNCPUMWRMSR} */
935	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
936	{
937	/** @todo implement IA32_THERM_INTERRUPT. */
938	return VINF_SUCCESS;
939	}
940
941
942	/** @callback_method_impl{FNCPUMRDMSR} */
943	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
944	{
945	/** @todo implement IA32_THERM2_CTL. */
946	*puValue = 0;
947	return VINF_SUCCESS;
948	}
949
950
951	/** @callback_method_impl{FNCPUMWRMSR} */
952	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
953	{
954	/** @todo implement IA32_THERM2_CTL. */
955	return VINF_SUCCESS;
956	}
957
958
959	/** @callback_method_impl{FNCPUMRDMSR} */
960	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
961	{
962	*puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
963	return VINF_SUCCESS;
964	}
965
966
967	/** @callback_method_impl{FNCPUMWRMSR} */
968	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
969	{
970	#ifdef LOG_ENABLED
971	uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
972	#endif
973
974	/* Unsupported bits are generally ignored and stripped by the MSR range
975	entry that got us here. So, we just need to preserve fixed bits. */
976	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
977	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
978	\| MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
979
980	Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
981	uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
982
983	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
984	/** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
985	return VINF_SUCCESS;
986	}
987
988
989	/** @callback_method_impl{FNCPUMRDMSR} */
990	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
991	{
992	/** @todo Implement machine check exception injection. */
993	switch (idMsr & 3)
994	{
995	case 0:
996	case 1:
997	*puValue = 0;
998	break;
999
1000	/* The ADDR and MISC registers aren't accessible since the
1001	corresponding STATUS bits are zero. */
1002	case 2:
1003	Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1004	return VERR_CPUM_RAISE_GP_0;
1005	case 3:
1006	Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1007	return VERR_CPUM_RAISE_GP_0;
1008	}
1009	return VINF_SUCCESS;
1010	}
1011
1012
1013	/** @callback_method_impl{FNCPUMWRMSR} */
1014	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1015	{
1016	switch (idMsr & 3)
1017	{
1018	case 0:
1019	/* Ignore writes to the CTL register. */
1020	break;
1021
1022	case 1:
1023	/* According to specs, the STATUS register can only be written to
1024	with the value 0. VBoxCpuReport thinks different for a
1025	Pentium M Dothan, but implementing according to specs now. */
1026	if (uValue != 0)
1027	{
1028	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1029	return VERR_CPUM_RAISE_GP_0;
1030	}
1031	break;
1032
1033	/* Specs states that ADDR and MISC can be cleared by writing zeros.
1034	Writing 1s will GP. Need to figure out how this relates to the
1035	ADDRV and MISCV status flags. If writing is independent of those
1036	bits, we need to know whether the CPU really implements them since
1037	that is exposed by writing 0 to them.
1038	Implementing the solution with the fewer GPs for now. */
1039	case 2:
1040	if (uValue != 0)
1041	{
1042	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1043	return VERR_CPUM_RAISE_GP_0;
1044	}
1045	break;
1046	case 3:
1047	if (uValue != 0)
1048	{
1049	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1050	return VERR_CPUM_RAISE_GP_0;
1051	}
1052	break;
1053	}
1054	return VINF_SUCCESS;
1055	}
1056
1057
1058	/** @callback_method_impl{FNCPUMRDMSR} */
1059	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1060	{
1061	/** @todo Implement machine check exception injection. */
1062	*puValue = 0;
1063	return VINF_SUCCESS;
1064	}
1065
1066
1067	/** @callback_method_impl{FNCPUMWRMSR} */
1068	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1069	{
1070	/** @todo Implement machine check exception injection. */
1071	return VINF_SUCCESS;
1072	}
1073
1074
1075	/** @callback_method_impl{FNCPUMRDMSR} */
1076	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1077	{
1078	/** @todo implement IA32_DS_AREA. */
1079	*puValue = 0;
1080	return VINF_SUCCESS;
1081	}
1082
1083
1084	/** @callback_method_impl{FNCPUMWRMSR} */
1085	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1086	{
1087	return VINF_SUCCESS;
1088	}
1089
1090
1091	/** @callback_method_impl{FNCPUMRDMSR} */
1092	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1093	{
1094	/** @todo implement TSC deadline timer. */
1095	*puValue = 0;
1096	return VINF_SUCCESS;
1097	}
1098
1099
1100	/** @callback_method_impl{FNCPUMWRMSR} */
1101	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1102	{
1103	/** @todo implement TSC deadline timer. */
1104	return VINF_SUCCESS;
1105	}
1106
1107
1108	/** @callback_method_impl{FNCPUMRDMSR} */
1109	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1110	{
1111	return PDMApicReadMsr(pVCpu, idMsr, puValue);
1112	}
1113
1114
1115	/** @callback_method_impl{FNCPUMWRMSR} */
1116	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1117	{
1118	return PDMApicWriteMsr(pVCpu, idMsr, uValue);
1119	}
1120
1121
1122	/** @callback_method_impl{FNCPUMRDMSR} */
1123	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1124	{
1125	/** @todo IA32_DEBUG_INTERFACE (no docs) */
1126	*puValue = 0;
1127	return VINF_SUCCESS;
1128	}
1129
1130
1131	/** @callback_method_impl{FNCPUMWRMSR} */
1132	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1133	{
1134	/** @todo IA32_DEBUG_INTERFACE (no docs) */
1135	return VINF_SUCCESS;
1136	}
1137
1138
1139	/** @callback_method_impl{FNCPUMRDMSR} */
1140	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1141	{
1142	*puValue = 0;
1143	return VINF_SUCCESS;
1144	}
1145
1146
1147	/** @callback_method_impl{FNCPUMRDMSR} */
1148	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1149	{
1150	*puValue = 0;
1151	return VINF_SUCCESS;
1152	}
1153
1154
1155	/** @callback_method_impl{FNCPUMRDMSR} */
1156	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1157	{
1158	*puValue = 0;
1159	return VINF_SUCCESS;
1160	}
1161
1162
1163	/** @callback_method_impl{FNCPUMRDMSR} */
1164	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1165	{
1166	*puValue = 0;
1167	return VINF_SUCCESS;
1168	}
1169
1170
1171	/** @callback_method_impl{FNCPUMRDMSR} */
1172	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1173	{
1174	*puValue = 0;
1175	return VINF_SUCCESS;
1176	}
1177
1178
1179	/** @callback_method_impl{FNCPUMRDMSR} */
1180	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1181	{
1182	*puValue = 0;
1183	return VINF_SUCCESS;
1184	}
1185
1186
1187	/** @callback_method_impl{FNCPUMRDMSR} */
1188	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1189	{
1190	*puValue = 0;
1191	return VINF_SUCCESS;
1192	}
1193
1194
1195	/** @callback_method_impl{FNCPUMRDMSR} */
1196	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1197	{
1198	*puValue = 0;
1199	return VINF_SUCCESS;
1200	}
1201
1202
1203	/** @callback_method_impl{FNCPUMRDMSR} */
1204	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1205	{
1206	*puValue = 0;
1207	return VINF_SUCCESS;
1208	}
1209
1210
1211	/** @callback_method_impl{FNCPUMRDMSR} */
1212	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1213	{
1214	*puValue = 0;
1215	return VINF_SUCCESS;
1216	}
1217
1218
1219	/** @callback_method_impl{FNCPUMRDMSR} */
1220	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1221	{
1222	*puValue = 0;
1223	return VINF_SUCCESS;
1224	}
1225
1226
1227	/** @callback_method_impl{FNCPUMRDMSR} */
1228	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1229	{
1230	*puValue = 0;
1231	return VINF_SUCCESS;
1232	}
1233
1234
1235	/** @callback_method_impl{FNCPUMRDMSR} */
1236	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1237	{
1238	*puValue = 0;
1239	return VINF_SUCCESS;
1240	}
1241
1242
1243	/** @callback_method_impl{FNCPUMRDMSR} */
1244	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1245	{
1246	*puValue = 0;
1247	return VINF_SUCCESS;
1248	}
1249
1250
1251	/** @callback_method_impl{FNCPUMRDMSR} */
1252	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1253	{
1254	*puValue = 0;
1255	return VINF_SUCCESS;
1256	}
1257
1258
1259	/** @callback_method_impl{FNCPUMRDMSR} */
1260	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1261	{
1262	*puValue = 0;
1263	return VINF_SUCCESS;
1264	}
1265
1266
1267	/** @callback_method_impl{FNCPUMRDMSR} */
1268	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1269	{
1270	*puValue = 0;
1271	return VINF_SUCCESS;
1272	}
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283	/*
1284	* AMD64
1285	* AMD64
1286	* AMD64
1287	*/
1288
1289
1290	/** @callback_method_impl{FNCPUMRDMSR} */
1291	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1292	{
1293	*puValue = pVCpu->cpum.s.Guest.msrEFER;
1294	return VINF_SUCCESS;
1295	}
1296
1297
1298	/** @callback_method_impl{FNCPUMWRMSR} */
1299	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1300	{
1301	PVM pVM = pVCpu->CTX_SUFF(pVM);
1302	uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1303	uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax >= 0x80000001
1304	? pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx
1305	: 0;
1306	uint64_t fMask = 0;
1307	uint64_t fIgnoreMask = MSR_K6_EFER_LMA;
1308
1309	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1310	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1311	fMask \|= MSR_K6_EFER_NXE;
1312	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1313	fMask \|= MSR_K6_EFER_LME;
1314	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1315	fMask \|= MSR_K6_EFER_SCE;
1316	if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1317	fMask \|= MSR_K6_EFER_FFXSR;
1318
1319	/* #GP(0) If anything outside the allowed bits is set. */
1320	if (uValue & ~(fIgnoreMask \| fMask))
1321	{
1322	Log(("CPUM: Settings disallowed EFER bit. uValue=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uValue, fMask));
1323	return VERR_CPUM_RAISE_GP_0;
1324	}
1325
1326	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1327	paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1328	if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1329	&& (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1330	{
1331	Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1332	return VERR_CPUM_RAISE_GP_0;
1333	}
1334
1335	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1336	AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE \| MSR_K6_EFER_LME \| MSR_K6_EFER_LMA /* ignored anyway */ \| MSR_K6_EFER_SCE \| MSR_K6_EFER_FFXSR)),
1337	("Unexpected value %RX64\n", uValue));
1338	pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) \| (uValue & fMask);
1339
1340	/* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1341	if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1342	if ( (uOldEfer & (MSR_K6_EFER_NXE \| MSR_K6_EFER_LME \| MSR_K6_EFER_LMA))
1343	!= (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE \| MSR_K6_EFER_LME \| MSR_K6_EFER_LMA)))
1344	{
1345	/// @todo PGMFlushTLB(pVCpu, cr3, true /fGlobal/);
1346	HMFlushTLB(pVCpu);
1347
1348	/* Notify PGM about NXE changes. */
1349	if ( (uOldEfer & MSR_K6_EFER_NXE)
1350	!= (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1351	PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1352	}
1353	return VINF_SUCCESS;
1354	}
1355
1356
1357	/** @callback_method_impl{FNCPUMRDMSR} */
1358	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1359	{
1360	*puValue = pVCpu->cpum.s.Guest.msrSTAR;
1361	return VINF_SUCCESS;
1362	}
1363
1364
1365	/** @callback_method_impl{FNCPUMWRMSR} */
1366	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1367	{
1368	pVCpu->cpum.s.Guest.msrSTAR = uValue;
1369	return VINF_SUCCESS;
1370	}
1371
1372
1373	/** @callback_method_impl{FNCPUMRDMSR} */
1374	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1375	{
1376	*puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1377	return VINF_SUCCESS;
1378	}
1379
1380
1381	/** @callback_method_impl{FNCPUMWRMSR} */
1382	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1383	{
1384	if (!X86_IS_CANONICAL(uValue))
1385	{
1386	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1387	return VERR_CPUM_RAISE_GP_0;
1388	}
1389	pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1390	return VINF_SUCCESS;
1391	}
1392
1393
1394	/** @callback_method_impl{FNCPUMRDMSR} */
1395	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1396	{
1397	*puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1398	return VINF_SUCCESS;
1399	}
1400
1401
1402	/** @callback_method_impl{FNCPUMWRMSR} */
1403	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1404	{
1405	if (!X86_IS_CANONICAL(uValue))
1406	{
1407	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1408	return VERR_CPUM_RAISE_GP_0;
1409	}
1410	pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1411	return VINF_SUCCESS;
1412	}
1413
1414
1415	/** @callback_method_impl{FNCPUMRDMSR} */
1416	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1417	{
1418	*puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1419	return VINF_SUCCESS;
1420	}
1421
1422
1423	/** @callback_method_impl{FNCPUMWRMSR} */
1424	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1425	{
1426	pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1427	return VINF_SUCCESS;
1428	}
1429
1430
1431	/** @callback_method_impl{FNCPUMRDMSR} */
1432	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1433	{
1434	*puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1435	return VINF_SUCCESS;
1436	}
1437
1438
1439	/** @callback_method_impl{FNCPUMWRMSR} */
1440	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1441	{
1442	pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1443	return VINF_SUCCESS;
1444	}
1445
1446
1447	/** @callback_method_impl{FNCPUMRDMSR} */
1448	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1449	{
1450	*puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1451	return VINF_SUCCESS;
1452	}
1453
1454	/** @callback_method_impl{FNCPUMWRMSR} */
1455	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1456	{
1457	pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1458	return VINF_SUCCESS;
1459	}
1460
1461
1462
1463	/** @callback_method_impl{FNCPUMRDMSR} */
1464	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1465	{
1466	*puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1467	return VINF_SUCCESS;
1468	}
1469
1470	/** @callback_method_impl{FNCPUMWRMSR} */
1471	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1472	{
1473	pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1474	return VINF_SUCCESS;
1475	}
1476
1477
1478	/** @callback_method_impl{FNCPUMRDMSR} */
1479	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1480	{
1481	*puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1482	return VINF_SUCCESS;
1483	}
1484
1485	/** @callback_method_impl{FNCPUMWRMSR} */
1486	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1487	{
1488	pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1489	return VINF_SUCCESS;
1490	}
1491
1492
1493	/*
1494	* Intel specific
1495	* Intel specific
1496	* Intel specific
1497	*/
1498
1499	/** @callback_method_impl{FNCPUMRDMSR} */
1500	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1501	{
1502	/** @todo recalc clock frequency ratio? */
1503	*puValue = pRange->uValue;
1504	return VINF_SUCCESS;
1505	}
1506
1507
1508	/** @callback_method_impl{FNCPUMWRMSR} */
1509	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1510	{
1511	/** @todo Write EBL_CR_POWERON: Remember written bits. */
1512	return VINF_SUCCESS;
1513	}
1514
1515
1516	/** @callback_method_impl{FNCPUMRDMSR} */
1517	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1518	{
1519	/* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1520	have a 4-bit core count. */
1521	uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1522	uint16_t cThreads = cCores; /** @todo hyper-threading. */
1523	*puValue = RT_MAKE_U32(cThreads, cCores);
1524	return VINF_SUCCESS;
1525	}
1526
1527
1528	/** @callback_method_impl{FNCPUMRDMSR} */
1529	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1530	{
1531	/** @todo P4 hard power on config */
1532	*puValue = pRange->uValue;
1533	return VINF_SUCCESS;
1534	}
1535
1536
1537	/** @callback_method_impl{FNCPUMWRMSR} */
1538	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1539	{
1540	/** @todo P4 hard power on config */
1541	return VINF_SUCCESS;
1542	}
1543
1544
1545	/** @callback_method_impl{FNCPUMRDMSR} */
1546	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1547	{
1548	/** @todo P4 soft power on config */
1549	*puValue = pRange->uValue;
1550	return VINF_SUCCESS;
1551	}
1552
1553
1554	/** @callback_method_impl{FNCPUMWRMSR} */
1555	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1556	{
1557	/** @todo P4 soft power on config */
1558	return VINF_SUCCESS;
1559	}
1560
1561
1562	/** @callback_method_impl{FNCPUMRDMSR} */
1563	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1564	{
1565	uint64_t uValue;
1566	PVM pVM = pVCpu->CTX_SUFF(pVM);
1567	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1568	if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1569	{
1570	if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1571	{
1572	uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1573	uValue = 0;
1574	}
1575	else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1576	{
1577	uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1578	uValue = 1;
1579	}
1580	else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1581	{
1582	uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1583	uValue = 3;
1584	}
1585	else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1586	{
1587	uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1588	uValue = 2;
1589	}
1590	else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1591	{
1592	uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1593	uValue = 0;
1594	}
1595	else
1596	{
1597	uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1598	uValue = 6;
1599	}
1600	uValue <<= 16;
1601
1602	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1603	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1604	uValue \|= (uint32_t)uTscRatio << 24;
1605
1606	uValue \|= pRange->uValue & ~UINT64_C(0xff0f0000);
1607	}
1608	else
1609	{
1610	/* Probably more stuff here, but intel doesn't want to tell us. */
1611	uValue = pRange->uValue;
1612	uValue &= ~(RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23)); /* 100 MHz is only documented value */
1613	}
1614
1615	*puValue = uValue;
1616	return VINF_SUCCESS;
1617	}
1618
1619
1620	/** @callback_method_impl{FNCPUMWRMSR} */
1621	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1622	{
1623	/** @todo P4 bus frequency config */
1624	return VINF_SUCCESS;
1625	}
1626
1627
1628	/** @callback_method_impl{FNCPUMRDMSR} */
1629	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1630	{
1631	/* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1632	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1633	if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1634	*puValue = 5;
1635	else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1636	*puValue = 1;
1637	else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1638	*puValue = 3;
1639	else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1640	*puValue = 2;
1641	else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1642	*puValue = 0;
1643	else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1644	*puValue = 4;
1645	else /if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)/
1646	*puValue = 6;
1647
1648	*puValue \|= pRange->uValue & ~UINT64_C(0x7);
1649
1650	return VINF_SUCCESS;
1651	}
1652
1653
1654	/** @callback_method_impl{FNCPUMRDMSR} */
1655	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1656	{
1657	/* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1658	PVM pVM = pVCpu->CTX_SUFF(pVM);
1659	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1660	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1661	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1662	uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1663	\| ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1664
1665	/* Ivy bridge has a minimum operating ratio as well. */
1666	if (true) /** @todo detect sandy bridge. */
1667	uValue \|= (uint64_t)uTscRatio << 48;
1668
1669	*puValue = uValue;
1670	return VINF_SUCCESS;
1671	}
1672
1673
1674	/** @callback_method_impl{FNCPUMRDMSR} */
1675	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1676	{
1677	uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1678
1679	PVM pVM = pVCpu->CTX_SUFF(pVM);
1680	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1681	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1682	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1683	uValue \|= (uint32_t)uTscRatio << 8;
1684
1685	*puValue = uValue;
1686	return VINF_SUCCESS;
1687	}
1688
1689
1690	/** @callback_method_impl{FNCPUMWRMSR} */
1691	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1692	{
1693	/** @todo implement writing MSR_FLEX_RATIO. */
1694	return VINF_SUCCESS;
1695	}
1696
1697
1698	/** @callback_method_impl{FNCPUMRDMSR} */
1699	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1700	{
1701	*puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1702	return VINF_SUCCESS;
1703	}
1704
1705
1706	/** @callback_method_impl{FNCPUMWRMSR} */
1707	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1708	{
1709	if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1710	{
1711	Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1712	return VERR_CPUM_RAISE_GP_0;
1713	}
1714	#if 0 /** @todo check what real (old) hardware does. */
1715	if ((uValue & 7) >= 5)
1716	{
1717	Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1718	return VERR_CPUM_RAISE_GP_0;
1719	}
1720	#endif
1721	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1722	return VINF_SUCCESS;
1723	}
1724
1725
1726	/** @callback_method_impl{FNCPUMRDMSR} */
1727	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1728	{
1729	/** @todo implement I/O mwait wakeup. */
1730	*puValue = 0;
1731	return VINF_SUCCESS;
1732	}
1733
1734
1735	/** @callback_method_impl{FNCPUMWRMSR} */
1736	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1737	{
1738	/** @todo implement I/O mwait wakeup. */
1739	return VINF_SUCCESS;
1740	}
1741
1742
1743	/** @callback_method_impl{FNCPUMRDMSR} */
1744	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1745	{
1746	/** @todo implement last branch records. */
1747	*puValue = 0;
1748	return VINF_SUCCESS;
1749	}
1750
1751
1752	/** @callback_method_impl{FNCPUMWRMSR} */
1753	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1754	{
1755	/** @todo implement last branch records. */
1756	return VINF_SUCCESS;
1757	}
1758
1759
1760	/** @callback_method_impl{FNCPUMRDMSR} */
1761	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1762	{
1763	/** @todo implement last branch records. */
1764	*puValue = 0;
1765	return VINF_SUCCESS;
1766	}
1767
1768
1769	/** @callback_method_impl{FNCPUMWRMSR} */
1770	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1771	{
1772	/** @todo implement last branch records. */
1773	/** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1774	* if the rest of the bits are zero. Automatic sign extending?
1775	* Investigate! */
1776	if (!X86_IS_CANONICAL(uValue))
1777	{
1778	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1779	return VERR_CPUM_RAISE_GP_0;
1780	}
1781	return VINF_SUCCESS;
1782	}
1783
1784
1785	/** @callback_method_impl{FNCPUMRDMSR} */
1786	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1787	{
1788	/** @todo implement last branch records. */
1789	*puValue = 0;
1790	return VINF_SUCCESS;
1791	}
1792
1793
1794	/** @callback_method_impl{FNCPUMWRMSR} */
1795	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1796	{
1797	/** @todo implement last branch records. */
1798	/** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1799	* if the rest of the bits are zero. Automatic sign extending?
1800	* Investigate! */
1801	if (!X86_IS_CANONICAL(uValue))
1802	{
1803	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1804	return VERR_CPUM_RAISE_GP_0;
1805	}
1806	return VINF_SUCCESS;
1807	}
1808
1809
1810	/** @callback_method_impl{FNCPUMRDMSR} */
1811	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1812	{
1813	/** @todo implement last branch records. */
1814	*puValue = 0;
1815	return VINF_SUCCESS;
1816	}
1817
1818
1819	/** @callback_method_impl{FNCPUMWRMSR} */
1820	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1821	{
1822	/** @todo implement last branch records. */
1823	return VINF_SUCCESS;
1824	}
1825
1826
1827	/** @callback_method_impl{FNCPUMRDMSR} */
1828	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1829	{
1830	*puValue = pRange->uValue;
1831	return VINF_SUCCESS;
1832	}
1833
1834
1835	/** @callback_method_impl{FNCPUMWRMSR} */
1836	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1837	{
1838	return VINF_SUCCESS;
1839	}
1840
1841
1842	/** @callback_method_impl{FNCPUMRDMSR} */
1843	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1844	{
1845	*puValue = pRange->uValue;
1846	return VINF_SUCCESS;
1847	}
1848
1849
1850	/** @callback_method_impl{FNCPUMWRMSR} */
1851	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1852	{
1853	return VINF_SUCCESS;
1854	}
1855
1856
1857	/** @callback_method_impl{FNCPUMRDMSR} */
1858	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1859	{
1860	*puValue = pRange->uValue;
1861	return VINF_SUCCESS;
1862	}
1863
1864
1865	/** @callback_method_impl{FNCPUMWRMSR} */
1866	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1867	{
1868	return VINF_SUCCESS;
1869	}
1870
1871
1872	/** @callback_method_impl{FNCPUMRDMSR} */
1873	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1874	{
1875	/** @todo machine check. */
1876	*puValue = pRange->uValue;
1877	return VINF_SUCCESS;
1878	}
1879
1880
1881	/** @callback_method_impl{FNCPUMWRMSR} */
1882	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1883	{
1884	/** @todo machine check. */
1885	return VINF_SUCCESS;
1886	}
1887
1888
1889	/** @callback_method_impl{FNCPUMRDMSR} */
1890	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1891	{
1892	*puValue = 0;
1893	return VINF_SUCCESS;
1894	}
1895
1896
1897	/** @callback_method_impl{FNCPUMWRMSR} */
1898	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1899	{
1900	return VINF_SUCCESS;
1901	}
1902
1903
1904	/** @callback_method_impl{FNCPUMRDMSR} */
1905	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1906	{
1907	int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1908	AssertRC(rc);
1909	return VINF_SUCCESS;
1910	}
1911
1912
1913	/** @callback_method_impl{FNCPUMWRMSR} */
1914	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1915	{
1916	/* This CRx interface differs from the MOV CRx, GReg interface in that
1917	#GP(0) isn't raised if unsupported bits are written to. Instead they
1918	are simply ignored and masked off. (Pentium M Dothan) */
1919	/** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1920	* any, gain. */
1921	return VINF_SUCCESS;
1922	}
1923
1924
1925	/** @callback_method_impl{FNCPUMRDMSR} */
1926	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1927	{
1928	/** @todo implement CPUID masking. */
1929	*puValue = UINT64_MAX;
1930	return VINF_SUCCESS;
1931	}
1932
1933
1934	/** @callback_method_impl{FNCPUMWRMSR} */
1935	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1936	{
1937	/** @todo implement CPUID masking. */
1938	return VINF_SUCCESS;
1939	}
1940
1941
1942	/** @callback_method_impl{FNCPUMRDMSR} */
1943	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1944	{
1945	/** @todo implement CPUID masking. */
1946	return VINF_SUCCESS;
1947	}
1948
1949
1950	/** @callback_method_impl{FNCPUMWRMSR} */
1951	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1952	{
1953	/** @todo implement CPUID masking. */
1954	return VINF_SUCCESS;
1955	}
1956
1957
1958
1959	/** @callback_method_impl{FNCPUMRDMSR} */
1960	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1961	{
1962	/** @todo implement CPUID masking. */
1963	*puValue = UINT64_MAX;
1964	return VINF_SUCCESS;
1965	}
1966
1967
1968	/** @callback_method_impl{FNCPUMWRMSR} */
1969	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1970	{
1971	/** @todo implement CPUID masking. */
1972	return VINF_SUCCESS;
1973	}
1974
1975
1976
1977	/** @callback_method_impl{FNCPUMRDMSR} */
1978	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1979	{
1980	/** @todo implement AES-NI. */
1981	puValue = 3; / Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
1982	return VINF_SUCCESS;
1983	}
1984
1985
1986	/** @callback_method_impl{FNCPUMWRMSR} */
1987	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1988	{
1989	/** @todo implement AES-NI. */
1990	return VERR_CPUM_RAISE_GP_0;
1991	}
1992
1993
1994	/** @callback_method_impl{FNCPUMRDMSR} */
1995	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1996	{
1997	/** @todo implement intel C states. */
1998	*puValue = pRange->uValue;
1999	return VINF_SUCCESS;
2000	}
2001
2002
2003	/** @callback_method_impl{FNCPUMWRMSR} */
2004	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2005	{
2006	/** @todo implement intel C states. */
2007	return VINF_SUCCESS;
2008	}
2009
2010
2011	/** @callback_method_impl{FNCPUMRDMSR} */
2012	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2013	{
2014	/** @todo implement last-branch-records. */
2015	*puValue = 0;
2016	return VINF_SUCCESS;
2017	}
2018
2019
2020	/** @callback_method_impl{FNCPUMWRMSR} */
2021	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2022	{
2023	/** @todo implement last-branch-records. */
2024	return VINF_SUCCESS;
2025	}
2026
2027
2028	/** @callback_method_impl{FNCPUMRDMSR} */
2029	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2030	{
2031	/** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2032	*puValue = 0;
2033	return VINF_SUCCESS;
2034	}
2035
2036
2037	/** @callback_method_impl{FNCPUMWRMSR} */
2038	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2039	{
2040	/** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2041	return VINF_SUCCESS;
2042	}
2043
2044
2045	/** @callback_method_impl{FNCPUMRDMSR} */
2046	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2047	{
2048	/** @todo implement memory VLW? */
2049	*puValue = pRange->uValue;
2050	/* Note: A20M is known to be bit 1 as this was disclosed in spec update
2051	AAJ49/AAK51/????, which documents the inversion of this bit. The
2052	Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2053	that correct things. Some guesses at the other bits:
2054	bit 2 = INTR
2055	bit 4 = SMI
2056	bit 5 = INIT
2057	bit 6 = NMI */
2058	return VINF_SUCCESS;
2059	}
2060
2061
2062	/** @callback_method_impl{FNCPUMRDMSR} */
2063	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2064	{
2065	/** @todo intel power management */
2066	*puValue = 0;
2067	return VINF_SUCCESS;
2068	}
2069
2070
2071	/** @callback_method_impl{FNCPUMWRMSR} */
2072	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2073	{
2074	/** @todo intel power management */
2075	return VINF_SUCCESS;
2076	}
2077
2078
2079	/** @callback_method_impl{FNCPUMRDMSR} */
2080	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2081	{
2082	/** @todo intel performance counters. */
2083	*puValue = 0;
2084	return VINF_SUCCESS;
2085	}
2086
2087
2088	/** @callback_method_impl{FNCPUMWRMSR} */
2089	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2090	{
2091	/** @todo intel performance counters. */
2092	return VINF_SUCCESS;
2093	}
2094
2095
2096	/** @callback_method_impl{FNCPUMRDMSR} */
2097	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2098	{
2099	/** @todo intel performance counters. */
2100	*puValue = 0;
2101	return VINF_SUCCESS;
2102	}
2103
2104
2105	/** @callback_method_impl{FNCPUMWRMSR} */
2106	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2107	{
2108	/** @todo intel performance counters. */
2109	return VINF_SUCCESS;
2110	}
2111
2112
2113	/** @callback_method_impl{FNCPUMRDMSR} */
2114	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2115	{
2116	/** @todo intel power management. */
2117	*puValue = 0;
2118	return VINF_SUCCESS;
2119	}
2120
2121
2122	/** @callback_method_impl{FNCPUMRDMSR} */
2123	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2124	{
2125	/** @todo intel power management. */
2126	*puValue = 0;
2127	return VINF_SUCCESS;
2128	}
2129
2130
2131	/** @callback_method_impl{FNCPUMRDMSR} */
2132	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2133	{
2134	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2135	*puValue = 0;
2136	return VINF_SUCCESS;
2137	}
2138
2139
2140	/** @callback_method_impl{FNCPUMWRMSR} */
2141	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2142	{
2143	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2144	return VINF_SUCCESS;
2145	}
2146
2147
2148	/** @callback_method_impl{FNCPUMRDMSR} */
2149	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2150	{
2151	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2152	*puValue = 0;
2153	return VINF_SUCCESS;
2154	}
2155
2156
2157	/** @callback_method_impl{FNCPUMWRMSR} */
2158	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2159	{
2160	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2161	return VINF_SUCCESS;
2162	}
2163
2164
2165	/** @callback_method_impl{FNCPUMRDMSR} */
2166	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2167	{
2168	/** @todo intel RAPL. */
2169	*puValue = pRange->uValue;
2170	return VINF_SUCCESS;
2171	}
2172
2173
2174	/** @callback_method_impl{FNCPUMRDMSR} */
2175	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2176	{
2177	/** @todo intel power management. */
2178	*puValue = 0;
2179	return VINF_SUCCESS;
2180	}
2181
2182
2183	/** @callback_method_impl{FNCPUMWRMSR} */
2184	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2185	{
2186	/** @todo intel power management. */
2187	return VINF_SUCCESS;
2188	}
2189
2190
2191	/** @callback_method_impl{FNCPUMRDMSR} */
2192	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2193	{
2194	/** @todo intel power management. */
2195	*puValue = 0;
2196	return VINF_SUCCESS;
2197	}
2198
2199
2200	/** @callback_method_impl{FNCPUMRDMSR} */
2201	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2202	{
2203	/** @todo intel RAPL. */
2204	*puValue = 0;
2205	return VINF_SUCCESS;
2206	}
2207
2208
2209	/** @callback_method_impl{FNCPUMWRMSR} */
2210	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2211	{
2212	/** @todo intel RAPL. */
2213	return VINF_SUCCESS;
2214	}
2215
2216
2217	/** @callback_method_impl{FNCPUMRDMSR} */
2218	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2219	{
2220	/** @todo intel power management. */
2221	*puValue = 0;
2222	return VINF_SUCCESS;
2223	}
2224
2225
2226	/** @callback_method_impl{FNCPUMRDMSR} */
2227	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2228	{
2229	/** @todo intel power management. */
2230	*puValue = 0;
2231	return VINF_SUCCESS;
2232	}
2233
2234
2235	/** @callback_method_impl{FNCPUMRDMSR} */
2236	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2237	{
2238	/** @todo intel power management. */
2239	*puValue = 0;
2240	return VINF_SUCCESS;
2241	}
2242
2243
2244	/** @callback_method_impl{FNCPUMRDMSR} */
2245	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2246	{
2247	/** @todo intel RAPL. */
2248	*puValue = 0;
2249	return VINF_SUCCESS;
2250	}
2251
2252
2253	/** @callback_method_impl{FNCPUMWRMSR} */
2254	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2255	{
2256	/** @todo intel RAPL. */
2257	return VINF_SUCCESS;
2258	}
2259
2260
2261	/** @callback_method_impl{FNCPUMRDMSR} */
2262	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2263	{
2264	/** @todo intel power management. */
2265	*puValue = 0;
2266	return VINF_SUCCESS;
2267	}
2268
2269
2270	/** @callback_method_impl{FNCPUMRDMSR} */
2271	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2272	{
2273	/** @todo intel power management. */
2274	*puValue = 0;
2275	return VINF_SUCCESS;
2276	}
2277
2278
2279	/** @callback_method_impl{FNCPUMRDMSR} */
2280	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2281	{
2282	/** @todo intel power management. */
2283	*puValue = 0;
2284	return VINF_SUCCESS;
2285	}
2286
2287
2288	/** @callback_method_impl{FNCPUMRDMSR} */
2289	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2290	{
2291	/** @todo intel RAPL. */
2292	*puValue = 0;
2293	return VINF_SUCCESS;
2294	}
2295
2296
2297	/** @callback_method_impl{FNCPUMWRMSR} */
2298	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2299	{
2300	/** @todo intel RAPL. */
2301	return VINF_SUCCESS;
2302	}
2303
2304
2305	/** @callback_method_impl{FNCPUMRDMSR} */
2306	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2307	{
2308	/** @todo intel power management. */
2309	*puValue = 0;
2310	return VINF_SUCCESS;
2311	}
2312
2313
2314	/** @callback_method_impl{FNCPUMRDMSR} */
2315	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2316	{
2317	/** @todo intel RAPL. */
2318	*puValue = 0;
2319	return VINF_SUCCESS;
2320	}
2321
2322
2323	/** @callback_method_impl{FNCPUMWRMSR} */
2324	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2325	{
2326	/** @todo intel RAPL. */
2327	return VINF_SUCCESS;
2328	}
2329
2330
2331	/** @callback_method_impl{FNCPUMRDMSR} */
2332	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2333	{
2334	/** @todo intel power management. */
2335	*puValue = 0;
2336	return VINF_SUCCESS;
2337	}
2338
2339
2340	/** @callback_method_impl{FNCPUMRDMSR} */
2341	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2342	{
2343	/** @todo intel RAPL. */
2344	*puValue = 0;
2345	return VINF_SUCCESS;
2346	}
2347
2348
2349	/** @callback_method_impl{FNCPUMWRMSR} */
2350	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2351	{
2352	/** @todo intel RAPL. */
2353	return VINF_SUCCESS;
2354	}
2355
2356
2357	/** @callback_method_impl{FNCPUMRDMSR} */
2358	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2359	{
2360	/** @todo intel power management. */
2361	*puValue = 0;
2362	return VINF_SUCCESS;
2363	}
2364
2365
2366	/** @callback_method_impl{FNCPUMRDMSR} */
2367	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2368	{
2369	/** @todo intel RAPL. */
2370	*puValue = 0;
2371	return VINF_SUCCESS;
2372	}
2373
2374
2375	/** @callback_method_impl{FNCPUMWRMSR} */
2376	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2377	{
2378	/** @todo intel RAPL. */
2379	return VINF_SUCCESS;
2380	}
2381
2382
2383	/** @callback_method_impl{FNCPUMRDMSR} */
2384	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2385	{
2386	/** @todo intel power management. */
2387	*puValue = pRange->uValue;
2388	return VINF_SUCCESS;
2389	}
2390
2391
2392	/** @callback_method_impl{FNCPUMRDMSR} */
2393	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2394	{
2395	/** @todo intel power management. */
2396	*puValue = pRange->uValue;
2397	return VINF_SUCCESS;
2398	}
2399
2400
2401	/** @callback_method_impl{FNCPUMRDMSR} */
2402	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2403	{
2404	/** @todo intel power management. */
2405	*puValue = pRange->uValue;
2406	return VINF_SUCCESS;
2407	}
2408
2409
2410	/** @callback_method_impl{FNCPUMRDMSR} */
2411	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2412	{
2413	/** @todo intel power management. */
2414	*puValue = 0;
2415	return VINF_SUCCESS;
2416	}
2417
2418
2419	/** @callback_method_impl{FNCPUMWRMSR} */
2420	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2421	{
2422	/** @todo intel power management. */
2423	return VINF_SUCCESS;
2424	}
2425
2426
2427	/** @callback_method_impl{FNCPUMRDMSR} */
2428	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2429	{
2430	/** @todo intel power management. */
2431	*puValue = 0;
2432	return VINF_SUCCESS;
2433	}
2434
2435
2436	/** @callback_method_impl{FNCPUMWRMSR} */
2437	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2438	{
2439	/** @todo intel power management. */
2440	return VINF_SUCCESS;
2441	}
2442
2443
2444	/** @callback_method_impl{FNCPUMRDMSR} */
2445	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2446	{
2447	/** @todo uncore msrs. */
2448	*puValue = 0;
2449	return VINF_SUCCESS;
2450	}
2451
2452
2453	/** @callback_method_impl{FNCPUMWRMSR} */
2454	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2455	{
2456	/** @todo uncore msrs. */
2457	return VINF_SUCCESS;
2458	}
2459
2460
2461	/** @callback_method_impl{FNCPUMRDMSR} */
2462	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2463	{
2464	/** @todo uncore msrs. */
2465	*puValue = 0;
2466	return VINF_SUCCESS;
2467	}
2468
2469
2470	/** @callback_method_impl{FNCPUMWRMSR} */
2471	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2472	{
2473	/** @todo uncore msrs. */
2474	return VINF_SUCCESS;
2475	}
2476
2477
2478	/** @callback_method_impl{FNCPUMRDMSR} */
2479	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2480	{
2481	/** @todo uncore msrs. */
2482	*puValue = 0;
2483	return VINF_SUCCESS;
2484	}
2485
2486
2487	/** @callback_method_impl{FNCPUMWRMSR} */
2488	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2489	{
2490	/** @todo uncore msrs. */
2491	return VINF_SUCCESS;
2492	}
2493
2494
2495	/** @callback_method_impl{FNCPUMRDMSR} */
2496	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2497	{
2498	/** @todo uncore msrs. */
2499	*puValue = 0;
2500	return VINF_SUCCESS;
2501	}
2502
2503
2504	/** @callback_method_impl{FNCPUMWRMSR} */
2505	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2506	{
2507	/** @todo uncore msrs. */
2508	return VINF_SUCCESS;
2509	}
2510
2511
2512	/** @callback_method_impl{FNCPUMRDMSR} */
2513	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2514	{
2515	/** @todo uncore msrs. */
2516	*puValue = 0;
2517	return VINF_SUCCESS;
2518	}
2519
2520
2521	/** @callback_method_impl{FNCPUMWRMSR} */
2522	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2523	{
2524	/** @todo uncore msrs. */
2525	return VINF_SUCCESS;
2526	}
2527
2528
2529	/** @callback_method_impl{FNCPUMRDMSR} */
2530	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2531	{
2532	/** @todo uncore msrs. */
2533	*puValue = 0;
2534	return VINF_SUCCESS;
2535	}
2536
2537
2538	/** @callback_method_impl{FNCPUMRDMSR} */
2539	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2540	{
2541	/** @todo uncore msrs. */
2542	*puValue = 0;
2543	return VINF_SUCCESS;
2544	}
2545
2546
2547	/** @callback_method_impl{FNCPUMWRMSR} */
2548	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2549	{
2550	/** @todo uncore msrs. */
2551	return VINF_SUCCESS;
2552	}
2553
2554
2555	/** @callback_method_impl{FNCPUMRDMSR} */
2556	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2557	{
2558	/** @todo uncore msrs. */
2559	*puValue = 0;
2560	return VINF_SUCCESS;
2561	}
2562
2563
2564	/** @callback_method_impl{FNCPUMWRMSR} */
2565	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2566	{
2567	/** @todo uncore msrs. */
2568	return VINF_SUCCESS;
2569	}
2570
2571
2572	/** @callback_method_impl{FNCPUMRDMSR} */
2573	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2574	{
2575	/** @todo implement enhanced multi thread termal monitoring? */
2576	*puValue = pRange->uValue;
2577	return VINF_SUCCESS;
2578	}
2579
2580
2581	/** @callback_method_impl{FNCPUMWRMSR} */
2582	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2583	{
2584	/** @todo implement enhanced multi thread termal monitoring? */
2585	return VINF_SUCCESS;
2586	}
2587
2588
2589	/** @callback_method_impl{FNCPUMRDMSR} */
2590	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2591	{
2592	/** @todo SMM & C-states? */
2593	*puValue = 0;
2594	return VINF_SUCCESS;
2595	}
2596
2597
2598	/** @callback_method_impl{FNCPUMWRMSR} */
2599	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2600	{
2601	/** @todo SMM & C-states? */
2602	return VINF_SUCCESS;
2603	}
2604
2605
2606	/** @callback_method_impl{FNCPUMRDMSR} */
2607	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2608	{
2609	/** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2610	*puValue = 0;
2611	return VINF_SUCCESS;
2612	}
2613
2614
2615	/** @callback_method_impl{FNCPUMWRMSR} */
2616	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2617	{
2618	/** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2619	return VINF_SUCCESS;
2620	}
2621
2622
2623	/** @callback_method_impl{FNCPUMRDMSR} */
2624	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2625	{
2626	/** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2627	*puValue = 0;
2628	return VINF_SUCCESS;
2629	}
2630
2631
2632	/** @callback_method_impl{FNCPUMWRMSR} */
2633	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2634	{
2635	/** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2636	return VINF_SUCCESS;
2637	}
2638
2639
2640	/** @callback_method_impl{FNCPUMRDMSR} */
2641	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2642	{
2643	/** @todo Core2+ platform environment control interface control register? */
2644	*puValue = 0;
2645	return VINF_SUCCESS;
2646	}
2647
2648
2649	/** @callback_method_impl{FNCPUMWRMSR} */
2650	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2651	{
2652	/** @todo Core2+ platform environment control interface control register? */
2653	return VINF_SUCCESS;
2654	}
2655
2656
2657
2658	/*
2659	* Multiple vendor P6 MSRs.
2660	* Multiple vendor P6 MSRs.
2661	* Multiple vendor P6 MSRs.
2662	*
2663	* These MSRs were introduced with the P6 but not elevated to architectural
2664	* MSRs, despite other vendors implementing them.
2665	*/
2666
2667
2668	/** @callback_method_impl{FNCPUMRDMSR} */
2669	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2670	{
2671	/* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2672	if I read the docs correctly, thus the need for separate functions. */
2673	/** @todo implement last branch records. */
2674	*puValue = 0;
2675	return VINF_SUCCESS;
2676	}
2677
2678
2679	/** @callback_method_impl{FNCPUMRDMSR} */
2680	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2681	{
2682	/** @todo implement last branch records. */
2683	*puValue = 0;
2684	return VINF_SUCCESS;
2685	}
2686
2687
2688	/** @callback_method_impl{FNCPUMRDMSR} */
2689	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2690	{
2691	/** @todo implement last exception records. */
2692	*puValue = 0;
2693	return VINF_SUCCESS;
2694	}
2695
2696
2697	/** @callback_method_impl{FNCPUMWRMSR} */
2698	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2699	{
2700	/** @todo implement last exception records. */
2701	/* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
2702	a non-cannonical address. */
2703	return VINF_SUCCESS;
2704	}
2705
2706
2707	/** @callback_method_impl{FNCPUMRDMSR} */
2708	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2709	{
2710	/** @todo implement last exception records. */
2711	*puValue = 0;
2712	return VINF_SUCCESS;
2713	}
2714
2715
2716	/** @callback_method_impl{FNCPUMWRMSR} */
2717	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2718	{
2719	/** @todo implement last exception records. */
2720	return VINF_SUCCESS;
2721	}
2722
2723
2724
2725	/*
2726	* AMD specific
2727	* AMD specific
2728	* AMD specific
2729	*/
2730
2731
2732	/** @callback_method_impl{FNCPUMRDMSR} */
2733	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2734	{
2735	/** @todo Implement TscRateMsr */
2736	puValue = RT_MAKE_U64(0, 1); / 1.0 = reset value. */
2737	return VINF_SUCCESS;
2738	}
2739
2740
2741	/** @callback_method_impl{FNCPUMWRMSR} */
2742	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2743	{
2744	/** @todo Implement TscRateMsr */
2745	return VINF_SUCCESS;
2746	}
2747
2748
2749	/** @callback_method_impl{FNCPUMRDMSR} */
2750	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2751	{
2752	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2753	/* Note: Only listes in BKDG for Family 15H. */
2754	*puValue = 0;
2755	return VINF_SUCCESS;
2756	}
2757
2758
2759	/** @callback_method_impl{FNCPUMWRMSR} */
2760	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2761	{
2762	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2763	return VINF_SUCCESS;
2764	}
2765
2766
2767	/** @callback_method_impl{FNCPUMRDMSR} */
2768	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2769	{
2770	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2771	/* Note: Only listes in BKDG for Family 15H. */
2772	*puValue = 0;
2773	return VINF_SUCCESS;
2774	}
2775
2776
2777	/** @callback_method_impl{FNCPUMWRMSR} */
2778	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2779	{
2780	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2781	return VINF_SUCCESS;
2782	}
2783
2784
2785	/** @callback_method_impl{FNCPUMRDMSR} */
2786	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2787	{
2788	/** @todo machine check. */
2789	*puValue = 0;
2790	return VINF_SUCCESS;
2791	}
2792
2793
2794	/** @callback_method_impl{FNCPUMWRMSR} */
2795	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2796	{
2797	/** @todo machine check. */
2798	return VINF_SUCCESS;
2799	}
2800
2801
2802	/** @callback_method_impl{FNCPUMRDMSR} */
2803	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2804	{
2805	/** @todo AMD performance events. */
2806	*puValue = 0;
2807	return VINF_SUCCESS;
2808	}
2809
2810
2811	/** @callback_method_impl{FNCPUMWRMSR} */
2812	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2813	{
2814	/** @todo AMD performance events. */
2815	return VINF_SUCCESS;
2816	}
2817
2818
2819	/** @callback_method_impl{FNCPUMRDMSR} */
2820	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2821	{
2822	/** @todo AMD performance events. */
2823	*puValue = 0;
2824	return VINF_SUCCESS;
2825	}
2826
2827
2828	/** @callback_method_impl{FNCPUMWRMSR} */
2829	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2830	{
2831	/** @todo AMD performance events. */
2832	return VINF_SUCCESS;
2833	}
2834
2835
2836	/** @callback_method_impl{FNCPUMRDMSR} */
2837	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2838	{
2839	/** @todo AMD SYS_CFG */
2840	*puValue = pRange->uValue;
2841	return VINF_SUCCESS;
2842	}
2843
2844
2845	/** @callback_method_impl{FNCPUMWRMSR} */
2846	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2847	{
2848	/** @todo AMD SYS_CFG */
2849	return VINF_SUCCESS;
2850	}
2851
2852
2853	/** @callback_method_impl{FNCPUMRDMSR} */
2854	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2855	{
2856	/** @todo AMD HW_CFG */
2857	*puValue = 0;
2858	return VINF_SUCCESS;
2859	}
2860
2861
2862	/** @callback_method_impl{FNCPUMWRMSR} */
2863	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2864	{
2865	/** @todo AMD HW_CFG */
2866	return VINF_SUCCESS;
2867	}
2868
2869
2870	/** @callback_method_impl{FNCPUMRDMSR} */
2871	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2872	{
2873	/** @todo AMD IorrMask/IorrBase */
2874	*puValue = 0;
2875	return VINF_SUCCESS;
2876	}
2877
2878
2879	/** @callback_method_impl{FNCPUMWRMSR} */
2880	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2881	{
2882	/** @todo AMD IorrMask/IorrBase */
2883	return VINF_SUCCESS;
2884	}
2885
2886
2887	/** @callback_method_impl{FNCPUMRDMSR} */
2888	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2889	{
2890	/** @todo AMD IorrMask/IorrBase */
2891	*puValue = 0;
2892	return VINF_SUCCESS;
2893	}
2894
2895
2896	/** @callback_method_impl{FNCPUMWRMSR} */
2897	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2898	{
2899	/** @todo AMD IorrMask/IorrBase */
2900	return VINF_SUCCESS;
2901	}
2902
2903
2904	/** @callback_method_impl{FNCPUMRDMSR} */
2905	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2906	{
2907	*puValue = 0;
2908	/** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2909	* for TOPMEM2. */
2910	//if (pRange->uValue == 0)
2911	// *puValue = _4G - RamHoleSize;
2912	return VINF_SUCCESS;
2913	}
2914
2915
2916	/** @callback_method_impl{FNCPUMWRMSR} */
2917	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2918	{
2919	/** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2920	return VINF_SUCCESS;
2921	}
2922
2923
2924	/** @callback_method_impl{FNCPUMRDMSR} */
2925	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2926	{
2927	/** @todo AMD NB_CFG1 */
2928	*puValue = 0;
2929	return VINF_SUCCESS;
2930	}
2931
2932
2933	/** @callback_method_impl{FNCPUMWRMSR} */
2934	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2935	{
2936	/** @todo AMD NB_CFG1 */
2937	return VINF_SUCCESS;
2938	}
2939
2940
2941	/** @callback_method_impl{FNCPUMRDMSR} */
2942	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2943	{
2944	/** @todo machine check. */
2945	*puValue = 0;
2946	return VINF_SUCCESS;
2947	}
2948
2949
2950	/** @callback_method_impl{FNCPUMWRMSR} */
2951	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2952	{
2953	/** @todo machine check. */
2954	return VINF_SUCCESS;
2955	}
2956
2957
2958	/** @callback_method_impl{FNCPUMRDMSR} */
2959	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2960	{
2961	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001);
2962	if (pLeaf)
2963	{
2964	if (!(pRange->uValue & 1))
2965	*puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2966	else
2967	*puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2968	}
2969	else
2970	*puValue = 0;
2971	return VINF_SUCCESS;
2972	}
2973
2974
2975	/** @callback_method_impl{FNCPUMWRMSR} */
2976	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2977	{
2978	/** @todo Remember guest programmed CPU name. */
2979	return VINF_SUCCESS;
2980	}
2981
2982
2983	/** @callback_method_impl{FNCPUMRDMSR} */
2984	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2985	{
2986	/** @todo AMD HTC. */
2987	*puValue = pRange->uValue;
2988	return VINF_SUCCESS;
2989	}
2990
2991
2992	/** @callback_method_impl{FNCPUMWRMSR} */
2993	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2994	{
2995	/** @todo AMD HTC. */
2996	return VINF_SUCCESS;
2997	}
2998
2999
3000	/** @callback_method_impl{FNCPUMRDMSR} */
3001	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3002	{
3003	/** @todo AMD STC. */
3004	*puValue = 0;
3005	return VINF_SUCCESS;
3006	}
3007
3008
3009	/** @callback_method_impl{FNCPUMWRMSR} */
3010	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3011	{
3012	/** @todo AMD STC. */
3013	return VINF_SUCCESS;
3014	}
3015
3016
3017	/** @callback_method_impl{FNCPUMRDMSR} */
3018	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3019	{
3020	/** @todo AMD FIDVID_CTL. */
3021	*puValue = pRange->uValue;
3022	return VINF_SUCCESS;
3023	}
3024
3025
3026	/** @callback_method_impl{FNCPUMWRMSR} */
3027	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3028	{
3029	/** @todo AMD FIDVID_CTL. */
3030	return VINF_SUCCESS;
3031	}
3032
3033
3034	/** @callback_method_impl{FNCPUMRDMSR} */
3035	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3036	{
3037	/** @todo AMD FIDVID_STATUS. */
3038	*puValue = pRange->uValue;
3039	return VINF_SUCCESS;
3040	}
3041
3042
3043	/** @callback_method_impl{FNCPUMRDMSR} */
3044	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3045	{
3046	/** @todo AMD MC. */
3047	*puValue = 0;
3048	return VINF_SUCCESS;
3049	}
3050
3051
3052	/** @callback_method_impl{FNCPUMWRMSR} */
3053	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3054	{
3055	/** @todo AMD MC. */
3056	return VINF_SUCCESS;
3057	}
3058
3059
3060	/** @callback_method_impl{FNCPUMRDMSR} */
3061	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3062	{
3063	/** @todo AMD SMM/SMI and I/O trap. */
3064	*puValue = 0;
3065	return VINF_SUCCESS;
3066	}
3067
3068
3069	/** @callback_method_impl{FNCPUMWRMSR} */
3070	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3071	{
3072	/** @todo AMD SMM/SMI and I/O trap. */
3073	return VINF_SUCCESS;
3074	}
3075
3076
3077	/** @callback_method_impl{FNCPUMRDMSR} */
3078	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3079	{
3080	/** @todo AMD SMM/SMI and I/O trap. */
3081	*puValue = 0;
3082	return VINF_SUCCESS;
3083	}
3084
3085
3086	/** @callback_method_impl{FNCPUMWRMSR} */
3087	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3088	{
3089	/** @todo AMD SMM/SMI and I/O trap. */
3090	return VINF_SUCCESS;
3091	}
3092
3093
3094	/** @callback_method_impl{FNCPUMRDMSR} */
3095	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3096	{
3097	/** @todo Interrupt pending message. */
3098	*puValue = 0;
3099	return VINF_SUCCESS;
3100	}
3101
3102
3103	/** @callback_method_impl{FNCPUMWRMSR} */
3104	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3105	{
3106	/** @todo Interrupt pending message. */
3107	return VINF_SUCCESS;
3108	}
3109
3110
3111	/** @callback_method_impl{FNCPUMRDMSR} */
3112	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3113	{
3114	/** @todo AMD SMM/SMI and trigger I/O cycle. */
3115	*puValue = 0;
3116	return VINF_SUCCESS;
3117	}
3118
3119
3120	/** @callback_method_impl{FNCPUMWRMSR} */
3121	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3122	{
3123	/** @todo AMD SMM/SMI and trigger I/O cycle. */
3124	return VINF_SUCCESS;
3125	}
3126
3127
3128	/** @callback_method_impl{FNCPUMRDMSR} */
3129	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3130	{
3131	/** @todo AMD MMIO Configuration base address. */
3132	*puValue = 0;
3133	return VINF_SUCCESS;
3134	}
3135
3136
3137	/** @callback_method_impl{FNCPUMWRMSR} */
3138	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3139	{
3140	/** @todo AMD MMIO Configuration base address. */
3141	return VINF_SUCCESS;
3142	}
3143
3144
3145	/** @callback_method_impl{FNCPUMRDMSR} */
3146	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3147	{
3148	/** @todo AMD 0xc0010059. */
3149	*puValue = 0;
3150	return VINF_SUCCESS;
3151	}
3152
3153
3154	/** @callback_method_impl{FNCPUMWRMSR} */
3155	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3156	{
3157	/** @todo AMD 0xc0010059. */
3158	return VINF_SUCCESS;
3159	}
3160
3161
3162	/** @callback_method_impl{FNCPUMRDMSR} */
3163	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3164	{
3165	/** @todo AMD P-states. */
3166	*puValue = pRange->uValue;
3167	return VINF_SUCCESS;
3168	}
3169
3170
3171	/** @callback_method_impl{FNCPUMRDMSR} */
3172	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3173	{
3174	/** @todo AMD P-states. */
3175	*puValue = pRange->uValue;
3176	return VINF_SUCCESS;
3177	}
3178
3179
3180	/** @callback_method_impl{FNCPUMWRMSR} */
3181	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3182	{
3183	/** @todo AMD P-states. */
3184	return VINF_SUCCESS;
3185	}
3186
3187
3188	/** @callback_method_impl{FNCPUMRDMSR} */
3189	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3190	{
3191	/** @todo AMD P-states. */
3192	*puValue = pRange->uValue;
3193	return VINF_SUCCESS;
3194	}
3195
3196
3197	/** @callback_method_impl{FNCPUMWRMSR} */
3198	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3199	{
3200	/** @todo AMD P-states. */
3201	return VINF_SUCCESS;
3202	}
3203
3204
3205	/** @callback_method_impl{FNCPUMRDMSR} */
3206	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3207	{
3208	/** @todo AMD P-states. */
3209	*puValue = pRange->uValue;
3210	return VINF_SUCCESS;
3211	}
3212
3213
3214	/** @callback_method_impl{FNCPUMWRMSR} */
3215	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3216	{
3217	/** @todo AMD P-states. */
3218	return VINF_SUCCESS;
3219	}
3220
3221
3222	/** @callback_method_impl{FNCPUMRDMSR} */
3223	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3224	{
3225	/** @todo AMD P-states. */
3226	*puValue = pRange->uValue;
3227	return VINF_SUCCESS;
3228	}
3229
3230
3231	/** @callback_method_impl{FNCPUMWRMSR} */
3232	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3233	{
3234	/** @todo AMD P-states. */
3235	return VINF_SUCCESS;
3236	}
3237
3238
3239	/** @callback_method_impl{FNCPUMRDMSR} */
3240	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3241	{
3242	/** @todo AMD P-states. */
3243	*puValue = pRange->uValue;
3244	return VINF_SUCCESS;
3245	}
3246
3247
3248	/** @callback_method_impl{FNCPUMWRMSR} */
3249	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3250	{
3251	/* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3252	/** @todo AMD P-states. */
3253	return VINF_SUCCESS;
3254	}
3255
3256
3257	/** @callback_method_impl{FNCPUMRDMSR} */
3258	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3259	{
3260	/** @todo AMD C-states. */
3261	*puValue = 0;
3262	return VINF_SUCCESS;
3263	}
3264
3265
3266	/** @callback_method_impl{FNCPUMWRMSR} */
3267	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3268	{
3269	/** @todo AMD C-states. */
3270	return VINF_SUCCESS;
3271	}
3272
3273
3274	/** @callback_method_impl{FNCPUMRDMSR} */
3275	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3276	{
3277	/** @todo AMD machine checks. */
3278	*puValue = 0;
3279	return VINF_SUCCESS;
3280	}
3281
3282
3283	/** @callback_method_impl{FNCPUMWRMSR} */
3284	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3285	{
3286	/** @todo AMD machine checks. */
3287	return VINF_SUCCESS;
3288	}
3289
3290
3291	/** @callback_method_impl{FNCPUMRDMSR} */
3292	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3293	{
3294	/** @todo AMD SMM. */
3295	*puValue = 0;
3296	return VINF_SUCCESS;
3297	}
3298
3299
3300	/** @callback_method_impl{FNCPUMWRMSR} */
3301	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3302	{
3303	/** @todo AMD SMM. */
3304	return VINF_SUCCESS;
3305	}
3306
3307
3308	/** @callback_method_impl{FNCPUMRDMSR} */
3309	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3310	{
3311	/** @todo AMD SMM. */
3312	*puValue = 0;
3313	return VINF_SUCCESS;
3314	}
3315
3316
3317	/** @callback_method_impl{FNCPUMWRMSR} */
3318	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3319	{
3320	/** @todo AMD SMM. */
3321	return VINF_SUCCESS;
3322	}
3323
3324
3325
3326	/** @callback_method_impl{FNCPUMRDMSR} */
3327	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3328	{
3329	/** @todo AMD SMM. */
3330	*puValue = 0;
3331	return VINF_SUCCESS;
3332	}
3333
3334
3335	/** @callback_method_impl{FNCPUMWRMSR} */
3336	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3337	{
3338	/** @todo AMD SMM. */
3339	return VINF_SUCCESS;
3340	}
3341
3342
3343	/** @callback_method_impl{FNCPUMRDMSR} */
3344	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3345	{
3346	/** @todo AMD SVM. */
3347	*puValue = 0;
3348	return VINF_SUCCESS;
3349	}
3350
3351
3352	/** @callback_method_impl{FNCPUMWRMSR} */
3353	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3354	{
3355	/** @todo AMD SVM. */
3356	return VINF_SUCCESS;
3357	}
3358
3359
3360	/** @callback_method_impl{FNCPUMRDMSR} */
3361	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3362	{
3363	/** @todo AMD IGNNE\# control. */
3364	*puValue = 0;
3365	return VINF_SUCCESS;
3366	}
3367
3368
3369	/** @callback_method_impl{FNCPUMWRMSR} */
3370	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3371	{
3372	/** @todo AMD IGNNE\# control. */
3373	return VINF_SUCCESS;
3374	}
3375
3376
3377	/** @callback_method_impl{FNCPUMRDMSR} */
3378	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3379	{
3380	/** @todo AMD SMM. */
3381	*puValue = 0;
3382	return VINF_SUCCESS;
3383	}
3384
3385
3386	/** @callback_method_impl{FNCPUMWRMSR} */
3387	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3388	{
3389	/** @todo AMD SMM. */
3390	return VINF_SUCCESS;
3391	}
3392
3393
3394	/** @callback_method_impl{FNCPUMRDMSR} */
3395	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3396	{
3397	/** @todo AMD SVM. */
3398	*puValue = 0;
3399	return VINF_SUCCESS;
3400	}
3401
3402
3403	/** @callback_method_impl{FNCPUMWRMSR} */
3404	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3405	{
3406	/** @todo AMD SVM. */
3407	return VINF_SUCCESS;
3408	}
3409
3410
3411	/** @callback_method_impl{FNCPUMRDMSR} */
3412	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3413	{
3414	/** @todo AMD SVM. */
3415	puValue = 0; / RAZ */
3416	return VINF_SUCCESS;
3417	}
3418
3419
3420	/** @callback_method_impl{FNCPUMWRMSR} */
3421	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3422	{
3423	/** @todo AMD SVM. */
3424	return VINF_SUCCESS;
3425	}
3426
3427
3428	/** @callback_method_impl{FNCPUMRDMSR} */
3429	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3430	{
3431	/** @todo AMD SMM. */
3432	puValue = 0; / RAZ */
3433	return VINF_SUCCESS;
3434	}
3435
3436
3437	/** @callback_method_impl{FNCPUMWRMSR} */
3438	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3439	{
3440	/** @todo AMD SMM. */
3441	return VINF_SUCCESS;
3442	}
3443
3444
3445	/** @callback_method_impl{FNCPUMRDMSR} */
3446	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3447	{
3448	/** @todo AMD SMM/SMI. */
3449	*puValue = 0;
3450	return VINF_SUCCESS;
3451	}
3452
3453
3454	/** @callback_method_impl{FNCPUMWRMSR} */
3455	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3456	{
3457	/** @todo AMD SMM/SMI. */
3458	return VINF_SUCCESS;
3459	}
3460
3461
3462	/** @callback_method_impl{FNCPUMRDMSR} */
3463	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3464	{
3465	/** @todo AMD OS visible workaround. */
3466	*puValue = pRange->uValue;
3467	return VINF_SUCCESS;
3468	}
3469
3470
3471	/** @callback_method_impl{FNCPUMWRMSR} */
3472	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3473	{
3474	/** @todo AMD OS visible workaround. */
3475	return VINF_SUCCESS;
3476	}
3477
3478
3479	/** @callback_method_impl{FNCPUMRDMSR} */
3480	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3481	{
3482	/** @todo AMD OS visible workaround. */
3483	*puValue = 0;
3484	return VINF_SUCCESS;
3485	}
3486
3487
3488	/** @callback_method_impl{FNCPUMWRMSR} */
3489	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3490	{
3491	/** @todo AMD OS visible workaround. */
3492	return VINF_SUCCESS;
3493	}
3494
3495
3496	/** @callback_method_impl{FNCPUMRDMSR} */
3497	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3498	{
3499	/** @todo AMD L2I performance counters. */
3500	*puValue = 0;
3501	return VINF_SUCCESS;
3502	}
3503
3504
3505	/** @callback_method_impl{FNCPUMWRMSR} */
3506	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3507	{
3508	/** @todo AMD L2I performance counters. */
3509	return VINF_SUCCESS;
3510	}
3511
3512
3513	/** @callback_method_impl{FNCPUMRDMSR} */
3514	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3515	{
3516	/** @todo AMD L2I performance counters. */
3517	*puValue = 0;
3518	return VINF_SUCCESS;
3519	}
3520
3521
3522	/** @callback_method_impl{FNCPUMWRMSR} */
3523	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3524	{
3525	/** @todo AMD L2I performance counters. */
3526	return VINF_SUCCESS;
3527	}
3528
3529
3530	/** @callback_method_impl{FNCPUMRDMSR} */
3531	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3532	{
3533	/** @todo AMD Northbridge performance counters. */
3534	*puValue = 0;
3535	return VINF_SUCCESS;
3536	}
3537
3538
3539	/** @callback_method_impl{FNCPUMWRMSR} */
3540	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3541	{
3542	/** @todo AMD Northbridge performance counters. */
3543	return VINF_SUCCESS;
3544	}
3545
3546
3547	/** @callback_method_impl{FNCPUMRDMSR} */
3548	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3549	{
3550	/** @todo AMD Northbridge performance counters. */
3551	*puValue = 0;
3552	return VINF_SUCCESS;
3553	}
3554
3555
3556	/** @callback_method_impl{FNCPUMWRMSR} */
3557	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3558	{
3559	/** @todo AMD Northbridge performance counters. */
3560	return VINF_SUCCESS;
3561	}
3562
3563
3564	/** @callback_method_impl{FNCPUMRDMSR} */
3565	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3566	{
3567	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3568	* cpus. Need to be explored and verify K7 presence. */
3569	/** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3570	*puValue = pRange->uValue;
3571	return VINF_SUCCESS;
3572	}
3573
3574
3575	/** @callback_method_impl{FNCPUMWRMSR} */
3576	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3577	{
3578	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3579	* cpus. Need to be explored and verify K7 presence. */
3580	/** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3581	return VINF_SUCCESS;
3582	}
3583
3584
3585	/** @callback_method_impl{FNCPUMRDMSR} */
3586	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3587	{
3588	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3589	* cpus. Need to be explored and verify K7 presence. */
3590	/** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3591	* describing EBL_CR_POWERON. */
3592	*puValue = pRange->uValue;
3593	return VINF_SUCCESS;
3594	}
3595
3596
3597	/** @callback_method_impl{FNCPUMWRMSR} */
3598	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3599	{
3600	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3601	* cpus. Need to be explored and verify K7 presence. */
3602	/** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3603	* describing EBL_CR_POWERON. */
3604	return VINF_SUCCESS;
3605	}
3606
3607
3608	/** @callback_method_impl{FNCPUMRDMSR} */
3609	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3610	{
3611	bool fIgnored;
3612	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVCpu->CTX_SUFF(pVM), 0x00000007, 0, &fIgnored);
3613	if (pLeaf)
3614	*puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3615	else
3616	*puValue = 0;
3617	return VINF_SUCCESS;
3618	}
3619
3620
3621	/** @callback_method_impl{FNCPUMWRMSR} */
3622	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3623	{
3624	/** @todo Changing CPUID leaf 7/0. */
3625	return VINF_SUCCESS;
3626	}
3627
3628
3629	/** @callback_method_impl{FNCPUMRDMSR} */
3630	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3631	{
3632	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006);
3633	if (pLeaf)
3634	*puValue = pLeaf->uEcx;
3635	else
3636	*puValue = 0;
3637	return VINF_SUCCESS;
3638	}
3639
3640
3641	/** @callback_method_impl{FNCPUMWRMSR} */
3642	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3643	{
3644	/** @todo Changing CPUID leaf 6. */
3645	return VINF_SUCCESS;
3646	}
3647
3648
3649	/** @callback_method_impl{FNCPUMRDMSR} */
3650	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3651	{
3652	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001);
3653	if (pLeaf)
3654	*puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3655	else
3656	*puValue = 0;
3657	return VINF_SUCCESS;
3658	}
3659
3660
3661	/** @callback_method_impl{FNCPUMWRMSR} */
3662	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3663	{
3664	/** @todo Changing CPUID leaf 0x80000001. */
3665	return VINF_SUCCESS;
3666	}
3667
3668
3669	/** @callback_method_impl{FNCPUMRDMSR} */
3670	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3671	{
3672	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001);
3673	if (pLeaf)
3674	*puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3675	else
3676	*puValue = 0;
3677	return VINF_SUCCESS;
3678	}
3679
3680
3681	/** @callback_method_impl{FNCPUMWRMSR} */
3682	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3683	{
3684	/** @todo Changing CPUID leaf 0x80000001. */
3685	return VINF_SUCCESS;
3686	}
3687
3688
3689	/** @callback_method_impl{FNCPUMRDMSR} */
3690	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3691	{
3692	/** @todo Fake AMD microcode patching. */
3693	*puValue = pRange->uValue;
3694	return VINF_SUCCESS;
3695	}
3696
3697
3698	/** @callback_method_impl{FNCPUMWRMSR} */
3699	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3700	{
3701	/** @todo Fake AMD microcode patching. */
3702	return VINF_SUCCESS;
3703	}
3704
3705
3706	/** @callback_method_impl{FNCPUMRDMSR} */
3707	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3708	{
3709	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3710	* cpus. Need to be explored and verify K7 presence. */
3711	/** @todo undocumented */
3712	*puValue = 0;
3713	return VINF_SUCCESS;
3714	}
3715
3716
3717	/** @callback_method_impl{FNCPUMWRMSR} */
3718	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3719	{
3720	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3721	* cpus. Need to be explored and verify K7 presence. */
3722	/** @todo undocumented */
3723	return VINF_SUCCESS;
3724	}
3725
3726
3727	/** @callback_method_impl{FNCPUMRDMSR} */
3728	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3729	{
3730	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3731	* cpus. Need to be explored and verify K7 presence. */
3732	/** @todo undocumented */
3733	*puValue = 0;
3734	return VINF_SUCCESS;
3735	}
3736
3737
3738	/** @callback_method_impl{FNCPUMWRMSR} */
3739	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3740	{
3741	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3742	* cpus. Need to be explored and verify K7 presence. */
3743	/** @todo undocumented */
3744	return VINF_SUCCESS;
3745	}
3746
3747
3748	/** @callback_method_impl{FNCPUMRDMSR} */
3749	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3750	{
3751	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3752	* cpus. Need to be explored and verify K7 presence. */
3753	/** @todo undocumented */
3754	*puValue = 0;
3755	return VINF_SUCCESS;
3756	}
3757
3758
3759	/** @callback_method_impl{FNCPUMWRMSR} */
3760	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3761	{
3762	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3763	* cpus. Need to be explored and verify K7 presence. */
3764	/** @todo undocumented */
3765	return VINF_SUCCESS;
3766	}
3767
3768
3769	/** @callback_method_impl{FNCPUMRDMSR} */
3770	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3771	{
3772	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3773	* cpus. Need to be explored and verify K7 presence. */
3774	/** @todo undocumented */
3775	*puValue = 0;
3776	return VINF_SUCCESS;
3777	}
3778
3779
3780	/** @callback_method_impl{FNCPUMWRMSR} */
3781	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3782	{
3783	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3784	* cpus. Need to be explored and verify K7 presence. */
3785	/** @todo undocumented */
3786	return VINF_SUCCESS;
3787	}
3788
3789
3790	/** @callback_method_impl{FNCPUMRDMSR} */
3791	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3792	{
3793	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3794	* cpus. Need to be explored and verify K7 presence. */
3795	/** @todo undocumented */
3796	*puValue = 0;
3797	return VINF_SUCCESS;
3798	}
3799
3800
3801	/** @callback_method_impl{FNCPUMWRMSR} */
3802	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3803	{
3804	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3805	* cpus. Need to be explored and verify K7 presence. */
3806	/** @todo undocumented */
3807	return VINF_SUCCESS;
3808	}
3809
3810
3811	/** @callback_method_impl{FNCPUMRDMSR} */
3812	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3813	{
3814	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3815	* cpus. Need to be explored and verify K7 presence. */
3816	/** @todo undocumented */
3817	*puValue = 0;
3818	return VINF_SUCCESS;
3819	}
3820
3821
3822	/** @callback_method_impl{FNCPUMWRMSR} */
3823	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3824	{
3825	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3826	* cpus. Need to be explored and verify K7 presence. */
3827	/** @todo undocumented */
3828	return VINF_SUCCESS;
3829	}
3830
3831
3832	/** @callback_method_impl{FNCPUMRDMSR} */
3833	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3834	{
3835	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3836	* cpus. Need to be explored and verify K7 presence. */
3837	/** @todo AMD node ID and bios scratch. */
3838	puValue = 0; / nodeid = 0; nodes-per-cpu = 1 */
3839	return VINF_SUCCESS;
3840	}
3841
3842
3843	/** @callback_method_impl{FNCPUMWRMSR} */
3844	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3845	{
3846	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3847	* cpus. Need to be explored and verify K7 presence. */
3848	/** @todo AMD node ID and bios scratch. */
3849	return VINF_SUCCESS;
3850	}
3851
3852
3853	/** @callback_method_impl{FNCPUMRDMSR} */
3854	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3855	{
3856	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3857	* cpus. Need to be explored and verify K7 presence. */
3858	/** @todo AMD DRx address masking (range breakpoints). */
3859	*puValue = 0;
3860	return VINF_SUCCESS;
3861	}
3862
3863
3864	/** @callback_method_impl{FNCPUMWRMSR} */
3865	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3866	{
3867	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3868	* cpus. Need to be explored and verify K7 presence. */
3869	/** @todo AMD DRx address masking (range breakpoints). */
3870	return VINF_SUCCESS;
3871	}
3872
3873
3874	/** @callback_method_impl{FNCPUMRDMSR} */
3875	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3876	{
3877	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3878	* cpus. Need to be explored and verify K7 presence. */
3879	/** @todo AMD undocument debugging features. */
3880	*puValue = 0;
3881	return VINF_SUCCESS;
3882	}
3883
3884
3885	/** @callback_method_impl{FNCPUMWRMSR} */
3886	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3887	{
3888	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3889	* cpus. Need to be explored and verify K7 presence. */
3890	/** @todo AMD undocument debugging features. */
3891	return VINF_SUCCESS;
3892	}
3893
3894
3895	/** @callback_method_impl{FNCPUMRDMSR} */
3896	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3897	{
3898	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3899	* cpus. Need to be explored and verify K7 presence. */
3900	/** @todo AMD undocument debugging features. */
3901	*puValue = 0;
3902	return VINF_SUCCESS;
3903	}
3904
3905
3906	/** @callback_method_impl{FNCPUMWRMSR} */
3907	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3908	{
3909	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3910	* cpus. Need to be explored and verify K7 presence. */
3911	/** @todo AMD undocument debugging features. */
3912	return VINF_SUCCESS;
3913	}
3914
3915
3916	/** @callback_method_impl{FNCPUMRDMSR} */
3917	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3918	{
3919	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3920	* cpus. Need to be explored and verify K7 presence. */
3921	/** @todo AMD load-store config. */
3922	*puValue = 0;
3923	return VINF_SUCCESS;
3924	}
3925
3926
3927	/** @callback_method_impl{FNCPUMWRMSR} */
3928	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3929	{
3930	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3931	* cpus. Need to be explored and verify K7 presence. */
3932	/** @todo AMD load-store config. */
3933	return VINF_SUCCESS;
3934	}
3935
3936
3937	/** @callback_method_impl{FNCPUMRDMSR} */
3938	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3939	{
3940	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3941	* cpus. Need to be explored and verify K7 presence. */
3942	/** @todo AMD instruction cache config. */
3943	*puValue = 0;
3944	return VINF_SUCCESS;
3945	}
3946
3947
3948	/** @callback_method_impl{FNCPUMWRMSR} */
3949	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3950	{
3951	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3952	* cpus. Need to be explored and verify K7 presence. */
3953	/** @todo AMD instruction cache config. */
3954	return VINF_SUCCESS;
3955	}
3956
3957
3958	/** @callback_method_impl{FNCPUMRDMSR} */
3959	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3960	{
3961	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3962	* cpus. Need to be explored and verify K7 presence. */
3963	/** @todo AMD data cache config. */
3964	*puValue = 0;
3965	return VINF_SUCCESS;
3966	}
3967
3968
3969	/** @callback_method_impl{FNCPUMWRMSR} */
3970	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3971	{
3972	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3973	* cpus. Need to be explored and verify K7 presence. */
3974	/** @todo AMD data cache config. */
3975	return VINF_SUCCESS;
3976	}
3977
3978
3979	/** @callback_method_impl{FNCPUMRDMSR} */
3980	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3981	{
3982	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3983	* cpus. Need to be explored and verify K7 presence. */
3984	/** @todo AMD bus unit config. */
3985	*puValue = 0;
3986	return VINF_SUCCESS;
3987	}
3988
3989
3990	/** @callback_method_impl{FNCPUMWRMSR} */
3991	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3992	{
3993	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3994	* cpus. Need to be explored and verify K7 presence. */
3995	/** @todo AMD bus unit config. */
3996	return VINF_SUCCESS;
3997	}
3998
3999
4000	/** @callback_method_impl{FNCPUMRDMSR} */
4001	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4002	{
4003	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4004	* cpus. Need to be explored and verify K7 presence. */
4005	/** @todo Undocument AMD debug control register \#2. */
4006	*puValue = 0;
4007	return VINF_SUCCESS;
4008	}
4009
4010
4011	/** @callback_method_impl{FNCPUMWRMSR} */
4012	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4013	{
4014	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4015	* cpus. Need to be explored and verify K7 presence. */
4016	/** @todo Undocument AMD debug control register \#2. */
4017	return VINF_SUCCESS;
4018	}
4019
4020
4021	/** @callback_method_impl{FNCPUMRDMSR} */
4022	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4023	{
4024	/** @todo AMD FPU config. */
4025	*puValue = 0;
4026	return VINF_SUCCESS;
4027	}
4028
4029
4030	/** @callback_method_impl{FNCPUMWRMSR} */
4031	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4032	{
4033	/** @todo AMD FPU config. */
4034	return VINF_SUCCESS;
4035	}
4036
4037
4038	/** @callback_method_impl{FNCPUMRDMSR} */
4039	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4040	{
4041	/** @todo AMD decoder config. */
4042	*puValue = 0;
4043	return VINF_SUCCESS;
4044	}
4045
4046
4047	/** @callback_method_impl{FNCPUMWRMSR} */
4048	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4049	{
4050	/** @todo AMD decoder config. */
4051	return VINF_SUCCESS;
4052	}
4053
4054
4055	/** @callback_method_impl{FNCPUMRDMSR} */
4056	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4057	{
4058	/* Note! 10h and 16h */
4059	/** @todo AMD bus unit config. */
4060	*puValue = 0;
4061	return VINF_SUCCESS;
4062	}
4063
4064
4065	/** @callback_method_impl{FNCPUMWRMSR} */
4066	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4067	{
4068	/* Note! 10h and 16h */
4069	/** @todo AMD bus unit config. */
4070	return VINF_SUCCESS;
4071	}
4072
4073
4074	/** @callback_method_impl{FNCPUMRDMSR} */
4075	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4076	{
4077	/** @todo AMD unit config. */
4078	*puValue = 0;
4079	return VINF_SUCCESS;
4080	}
4081
4082
4083	/** @callback_method_impl{FNCPUMWRMSR} */
4084	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4085	{
4086	/** @todo AMD unit config. */
4087	return VINF_SUCCESS;
4088	}
4089
4090
4091	/** @callback_method_impl{FNCPUMRDMSR} */
4092	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4093	{
4094	/** @todo AMD unit config 2. */
4095	*puValue = 0;
4096	return VINF_SUCCESS;
4097	}
4098
4099
4100	/** @callback_method_impl{FNCPUMWRMSR} */
4101	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4102	{
4103	/** @todo AMD unit config 2. */
4104	return VINF_SUCCESS;
4105	}
4106
4107
4108	/** @callback_method_impl{FNCPUMRDMSR} */
4109	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4110	{
4111	/** @todo AMD combined unit config 3. */
4112	*puValue = 0;
4113	return VINF_SUCCESS;
4114	}
4115
4116
4117	/** @callback_method_impl{FNCPUMWRMSR} */
4118	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4119	{
4120	/** @todo AMD combined unit config 3. */
4121	return VINF_SUCCESS;
4122	}
4123
4124
4125	/** @callback_method_impl{FNCPUMRDMSR} */
4126	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4127	{
4128	/** @todo AMD execution unit config. */
4129	*puValue = 0;
4130	return VINF_SUCCESS;
4131	}
4132
4133
4134	/** @callback_method_impl{FNCPUMWRMSR} */
4135	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4136	{
4137	/** @todo AMD execution unit config. */
4138	return VINF_SUCCESS;
4139	}
4140
4141
4142	/** @callback_method_impl{FNCPUMRDMSR} */
4143	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4144	{
4145	/** @todo AMD load-store config 2. */
4146	*puValue = 0;
4147	return VINF_SUCCESS;
4148	}
4149
4150
4151	/** @callback_method_impl{FNCPUMWRMSR} */
4152	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4153	{
4154	/** @todo AMD load-store config 2. */
4155	return VINF_SUCCESS;
4156	}
4157
4158
4159	/** @callback_method_impl{FNCPUMRDMSR} */
4160	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4161	{
4162	/** @todo AMD IBS. */
4163	*puValue = 0;
4164	return VINF_SUCCESS;
4165	}
4166
4167
4168	/** @callback_method_impl{FNCPUMWRMSR} */
4169	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4170	{
4171	/** @todo AMD IBS. */
4172	return VINF_SUCCESS;
4173	}
4174
4175
4176	/** @callback_method_impl{FNCPUMRDMSR} */
4177	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4178	{
4179	/** @todo AMD IBS. */
4180	*puValue = 0;
4181	return VINF_SUCCESS;
4182	}
4183
4184
4185	/** @callback_method_impl{FNCPUMWRMSR} */
4186	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4187	{
4188	/** @todo AMD IBS. */
4189	return VINF_SUCCESS;
4190	}
4191
4192
4193	/** @callback_method_impl{FNCPUMRDMSR} */
4194	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4195	{
4196	/** @todo AMD IBS. */
4197	*puValue = 0;
4198	return VINF_SUCCESS;
4199	}
4200
4201
4202	/** @callback_method_impl{FNCPUMWRMSR} */
4203	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4204	{
4205	/** @todo AMD IBS. */
4206	return VINF_SUCCESS;
4207	}
4208
4209
4210	/** @callback_method_impl{FNCPUMRDMSR} */
4211	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4212	{
4213	/** @todo AMD IBS. */
4214	*puValue = 0;
4215	return VINF_SUCCESS;
4216	}
4217
4218
4219	/** @callback_method_impl{FNCPUMWRMSR} */
4220	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4221	{
4222	/** @todo AMD IBS. */
4223	return VINF_SUCCESS;
4224	}
4225
4226
4227	/** @callback_method_impl{FNCPUMRDMSR} */
4228	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4229	{
4230	/** @todo AMD IBS. */
4231	*puValue = 0;
4232	return VINF_SUCCESS;
4233	}
4234
4235
4236	/** @callback_method_impl{FNCPUMWRMSR} */
4237	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4238	{
4239	/** @todo AMD IBS. */
4240	if (!X86_IS_CANONICAL(uValue))
4241	{
4242	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4243	return VERR_CPUM_RAISE_GP_0;
4244	}
4245	return VINF_SUCCESS;
4246	}
4247
4248
4249	/** @callback_method_impl{FNCPUMRDMSR} */
4250	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4251	{
4252	/** @todo AMD IBS. */
4253	*puValue = 0;
4254	return VINF_SUCCESS;
4255	}
4256
4257
4258	/** @callback_method_impl{FNCPUMWRMSR} */
4259	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4260	{
4261	/** @todo AMD IBS. */
4262	return VINF_SUCCESS;
4263	}
4264
4265
4266	/** @callback_method_impl{FNCPUMRDMSR} */
4267	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4268	{
4269	/** @todo AMD IBS. */
4270	*puValue = 0;
4271	return VINF_SUCCESS;
4272	}
4273
4274
4275	/** @callback_method_impl{FNCPUMWRMSR} */
4276	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4277	{
4278	/** @todo AMD IBS. */
4279	return VINF_SUCCESS;
4280	}
4281
4282
4283	/** @callback_method_impl{FNCPUMRDMSR} */
4284	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4285	{
4286	/** @todo AMD IBS. */
4287	*puValue = 0;
4288	return VINF_SUCCESS;
4289	}
4290
4291
4292	/** @callback_method_impl{FNCPUMWRMSR} */
4293	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4294	{
4295	/** @todo AMD IBS. */
4296	return VINF_SUCCESS;
4297	}
4298
4299
4300	/** @callback_method_impl{FNCPUMRDMSR} */
4301	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4302	{
4303	/** @todo AMD IBS. */
4304	*puValue = 0;
4305	return VINF_SUCCESS;
4306	}
4307
4308
4309	/** @callback_method_impl{FNCPUMWRMSR} */
4310	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4311	{
4312	/** @todo AMD IBS. */
4313	if (!X86_IS_CANONICAL(uValue))
4314	{
4315	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4316	return VERR_CPUM_RAISE_GP_0;
4317	}
4318	return VINF_SUCCESS;
4319	}
4320
4321
4322	/** @callback_method_impl{FNCPUMRDMSR} */
4323	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4324	{
4325	/** @todo AMD IBS. */
4326	*puValue = 0;
4327	return VINF_SUCCESS;
4328	}
4329
4330
4331	/** @callback_method_impl{FNCPUMWRMSR} */
4332	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4333	{
4334	/** @todo AMD IBS. */
4335	return VINF_SUCCESS;
4336	}
4337
4338
4339	/** @callback_method_impl{FNCPUMRDMSR} */
4340	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4341	{
4342	/** @todo AMD IBS. */
4343	*puValue = 0;
4344	return VINF_SUCCESS;
4345	}
4346
4347
4348	/** @callback_method_impl{FNCPUMWRMSR} */
4349	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4350	{
4351	/** @todo AMD IBS. */
4352	return VINF_SUCCESS;
4353	}
4354
4355
4356	/** @callback_method_impl{FNCPUMRDMSR} */
4357	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4358	{
4359	/** @todo AMD IBS. */
4360	*puValue = 0;
4361	return VINF_SUCCESS;
4362	}
4363
4364
4365	/** @callback_method_impl{FNCPUMWRMSR} */
4366	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4367	{
4368	/** @todo AMD IBS. */
4369	if (!X86_IS_CANONICAL(uValue))
4370	{
4371	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4372	return VERR_CPUM_RAISE_GP_0;
4373	}
4374	return VINF_SUCCESS;
4375	}
4376
4377
4378
4379	/*
4380	* GIM MSRs.
4381	* GIM MSRs.
4382	* GIM MSRs.
4383	*/
4384
4385
4386	/** @callback_method_impl{FNCPUMRDMSR} */
4387	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4388	{
4389	return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
4390	}
4391
4392
4393	/** @callback_method_impl{FNCPUMWRMSR} */
4394	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4395	{
4396	return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
4397	}
4398
4399
4400	/**
4401	* MSR read function table.
4402	*/
4403	static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4404	{
4405	NULL, /* Invalid */
4406	cpumMsrRd_FixedValue,
4407	NULL, /* Alias */
4408	cpumMsrRd_WriteOnly,
4409	cpumMsrRd_Ia32P5McAddr,
4410	cpumMsrRd_Ia32P5McType,
4411	cpumMsrRd_Ia32TimestampCounter,
4412	cpumMsrRd_Ia32PlatformId,
4413	cpumMsrRd_Ia32ApicBase,
4414	cpumMsrRd_Ia32FeatureControl,
4415	cpumMsrRd_Ia32BiosSignId,
4416	cpumMsrRd_Ia32SmmMonitorCtl,
4417	cpumMsrRd_Ia32PmcN,
4418	cpumMsrRd_Ia32MonitorFilterLineSize,
4419	cpumMsrRd_Ia32MPerf,
4420	cpumMsrRd_Ia32APerf,
4421	cpumMsrRd_Ia32MtrrCap,
4422	cpumMsrRd_Ia32MtrrPhysBaseN,
4423	cpumMsrRd_Ia32MtrrPhysMaskN,
4424	cpumMsrRd_Ia32MtrrFixed,
4425	cpumMsrRd_Ia32MtrrDefType,
4426	cpumMsrRd_Ia32Pat,
4427	cpumMsrRd_Ia32SysEnterCs,
4428	cpumMsrRd_Ia32SysEnterEsp,
4429	cpumMsrRd_Ia32SysEnterEip,
4430	cpumMsrRd_Ia32McgCap,
4431	cpumMsrRd_Ia32McgStatus,
4432	cpumMsrRd_Ia32McgCtl,
4433	cpumMsrRd_Ia32DebugCtl,
4434	cpumMsrRd_Ia32SmrrPhysBase,
4435	cpumMsrRd_Ia32SmrrPhysMask,
4436	cpumMsrRd_Ia32PlatformDcaCap,
4437	cpumMsrRd_Ia32CpuDcaCap,
4438	cpumMsrRd_Ia32Dca0Cap,
4439	cpumMsrRd_Ia32PerfEvtSelN,
4440	cpumMsrRd_Ia32PerfStatus,
4441	cpumMsrRd_Ia32PerfCtl,
4442	cpumMsrRd_Ia32FixedCtrN,
4443	cpumMsrRd_Ia32PerfCapabilities,
4444	cpumMsrRd_Ia32FixedCtrCtrl,
4445	cpumMsrRd_Ia32PerfGlobalStatus,
4446	cpumMsrRd_Ia32PerfGlobalCtrl,
4447	cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4448	cpumMsrRd_Ia32PebsEnable,
4449	cpumMsrRd_Ia32ClockModulation,
4450	cpumMsrRd_Ia32ThermInterrupt,
4451	cpumMsrRd_Ia32ThermStatus,
4452	cpumMsrRd_Ia32Therm2Ctl,
4453	cpumMsrRd_Ia32MiscEnable,
4454	cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4455	cpumMsrRd_Ia32McNCtl2,
4456	cpumMsrRd_Ia32DsArea,
4457	cpumMsrRd_Ia32TscDeadline,
4458	cpumMsrRd_Ia32X2ApicN,
4459	cpumMsrRd_Ia32DebugInterface,
4460	cpumMsrRd_Ia32VmxBase,
4461	cpumMsrRd_Ia32VmxPinbasedCtls,
4462	cpumMsrRd_Ia32VmxProcbasedCtls,
4463	cpumMsrRd_Ia32VmxExitCtls,
4464	cpumMsrRd_Ia32VmxEntryCtls,
4465	cpumMsrRd_Ia32VmxMisc,
4466	cpumMsrRd_Ia32VmxCr0Fixed0,
4467	cpumMsrRd_Ia32VmxCr0Fixed1,
4468	cpumMsrRd_Ia32VmxCr4Fixed0,
4469	cpumMsrRd_Ia32VmxCr4Fixed1,
4470	cpumMsrRd_Ia32VmxVmcsEnum,
4471	cpumMsrRd_Ia32VmxProcBasedCtls2,
4472	cpumMsrRd_Ia32VmxEptVpidCap,
4473	cpumMsrRd_Ia32VmxTruePinbasedCtls,
4474	cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4475	cpumMsrRd_Ia32VmxTrueExitCtls,
4476	cpumMsrRd_Ia32VmxTrueEntryCtls,
4477
4478	cpumMsrRd_Amd64Efer,
4479	cpumMsrRd_Amd64SyscallTarget,
4480	cpumMsrRd_Amd64LongSyscallTarget,
4481	cpumMsrRd_Amd64CompSyscallTarget,
4482	cpumMsrRd_Amd64SyscallFlagMask,
4483	cpumMsrRd_Amd64FsBase,
4484	cpumMsrRd_Amd64GsBase,
4485	cpumMsrRd_Amd64KernelGsBase,
4486	cpumMsrRd_Amd64TscAux,
4487
4488	cpumMsrRd_IntelEblCrPowerOn,
4489	cpumMsrRd_IntelI7CoreThreadCount,
4490	cpumMsrRd_IntelP4EbcHardPowerOn,
4491	cpumMsrRd_IntelP4EbcSoftPowerOn,
4492	cpumMsrRd_IntelP4EbcFrequencyId,
4493	cpumMsrRd_IntelP6FsbFrequency,
4494	cpumMsrRd_IntelPlatformInfo,
4495	cpumMsrRd_IntelFlexRatio,
4496	cpumMsrRd_IntelPkgCStConfigControl,
4497	cpumMsrRd_IntelPmgIoCaptureBase,
4498	cpumMsrRd_IntelLastBranchFromToN,
4499	cpumMsrRd_IntelLastBranchFromN,
4500	cpumMsrRd_IntelLastBranchToN,
4501	cpumMsrRd_IntelLastBranchTos,
4502	cpumMsrRd_IntelBblCrCtl,
4503	cpumMsrRd_IntelBblCrCtl3,
4504	cpumMsrRd_IntelI7TemperatureTarget,
4505	cpumMsrRd_IntelI7MsrOffCoreResponseN,
4506	cpumMsrRd_IntelI7MiscPwrMgmt,
4507	cpumMsrRd_IntelP6CrN,
4508	cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4509	cpumMsrRd_IntelCpuId1FeatureMaskEax,
4510	cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4511	cpumMsrRd_IntelI7SandyAesNiCtl,
4512	cpumMsrRd_IntelI7TurboRatioLimit,
4513	cpumMsrRd_IntelI7LbrSelect,
4514	cpumMsrRd_IntelI7SandyErrorControl,
4515	cpumMsrRd_IntelI7VirtualLegacyWireCap,
4516	cpumMsrRd_IntelI7PowerCtl,
4517	cpumMsrRd_IntelI7SandyPebsNumAlt,
4518	cpumMsrRd_IntelI7PebsLdLat,
4519	cpumMsrRd_IntelI7PkgCnResidencyN,
4520	cpumMsrRd_IntelI7CoreCnResidencyN,
4521	cpumMsrRd_IntelI7SandyVrCurrentConfig,
4522	cpumMsrRd_IntelI7SandyVrMiscConfig,
4523	cpumMsrRd_IntelI7SandyRaplPowerUnit,
4524	cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4525	cpumMsrRd_IntelI7SandyPkgC2Residency,
4526	cpumMsrRd_IntelI7RaplPkgPowerLimit,
4527	cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4528	cpumMsrRd_IntelI7RaplPkgPerfStatus,
4529	cpumMsrRd_IntelI7RaplPkgPowerInfo,
4530	cpumMsrRd_IntelI7RaplDramPowerLimit,
4531	cpumMsrRd_IntelI7RaplDramEnergyStatus,
4532	cpumMsrRd_IntelI7RaplDramPerfStatus,
4533	cpumMsrRd_IntelI7RaplDramPowerInfo,
4534	cpumMsrRd_IntelI7RaplPp0PowerLimit,
4535	cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4536	cpumMsrRd_IntelI7RaplPp0Policy,
4537	cpumMsrRd_IntelI7RaplPp0PerfStatus,
4538	cpumMsrRd_IntelI7RaplPp1PowerLimit,
4539	cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4540	cpumMsrRd_IntelI7RaplPp1Policy,
4541	cpumMsrRd_IntelI7IvyConfigTdpNominal,
4542	cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4543	cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4544	cpumMsrRd_IntelI7IvyConfigTdpControl,
4545	cpumMsrRd_IntelI7IvyTurboActivationRatio,
4546	cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4547	cpumMsrRd_IntelI7UncPerfGlobalStatus,
4548	cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4549	cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4550	cpumMsrRd_IntelI7UncPerfFixedCtr,
4551	cpumMsrRd_IntelI7UncCBoxConfig,
4552	cpumMsrRd_IntelI7UncArbPerfCtrN,
4553	cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4554	cpumMsrRd_IntelCore2EmttmCrTablesN,
4555	cpumMsrRd_IntelCore2SmmCStMiscInfo,
4556	cpumMsrRd_IntelCore1ExtConfig,
4557	cpumMsrRd_IntelCore1DtsCalControl,
4558	cpumMsrRd_IntelCore2PeciControl,
4559
4560	cpumMsrRd_P6LastBranchFromIp,
4561	cpumMsrRd_P6LastBranchToIp,
4562	cpumMsrRd_P6LastIntFromIp,
4563	cpumMsrRd_P6LastIntToIp,
4564
4565	cpumMsrRd_AmdFam15hTscRate,
4566	cpumMsrRd_AmdFam15hLwpCfg,
4567	cpumMsrRd_AmdFam15hLwpCbAddr,
4568	cpumMsrRd_AmdFam10hMc4MiscN,
4569	cpumMsrRd_AmdK8PerfCtlN,
4570	cpumMsrRd_AmdK8PerfCtrN,
4571	cpumMsrRd_AmdK8SysCfg,
4572	cpumMsrRd_AmdK8HwCr,
4573	cpumMsrRd_AmdK8IorrBaseN,
4574	cpumMsrRd_AmdK8IorrMaskN,
4575	cpumMsrRd_AmdK8TopOfMemN,
4576	cpumMsrRd_AmdK8NbCfg1,
4577	cpumMsrRd_AmdK8McXcptRedir,
4578	cpumMsrRd_AmdK8CpuNameN,
4579	cpumMsrRd_AmdK8HwThermalCtrl,
4580	cpumMsrRd_AmdK8SwThermalCtrl,
4581	cpumMsrRd_AmdK8FidVidControl,
4582	cpumMsrRd_AmdK8FidVidStatus,
4583	cpumMsrRd_AmdK8McCtlMaskN,
4584	cpumMsrRd_AmdK8SmiOnIoTrapN,
4585	cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4586	cpumMsrRd_AmdK8IntPendingMessage,
4587	cpumMsrRd_AmdK8SmiTriggerIoCycle,
4588	cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4589	cpumMsrRd_AmdFam10hTrapCtlMaybe,
4590	cpumMsrRd_AmdFam10hPStateCurLimit,
4591	cpumMsrRd_AmdFam10hPStateControl,
4592	cpumMsrRd_AmdFam10hPStateStatus,
4593	cpumMsrRd_AmdFam10hPStateN,
4594	cpumMsrRd_AmdFam10hCofVidControl,
4595	cpumMsrRd_AmdFam10hCofVidStatus,
4596	cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4597	cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4598	cpumMsrRd_AmdK8SmmBase,
4599	cpumMsrRd_AmdK8SmmAddr,
4600	cpumMsrRd_AmdK8SmmMask,
4601	cpumMsrRd_AmdK8VmCr,
4602	cpumMsrRd_AmdK8IgnNe,
4603	cpumMsrRd_AmdK8SmmCtl,
4604	cpumMsrRd_AmdK8VmHSavePa,
4605	cpumMsrRd_AmdFam10hVmLockKey,
4606	cpumMsrRd_AmdFam10hSmmLockKey,
4607	cpumMsrRd_AmdFam10hLocalSmiStatus,
4608	cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4609	cpumMsrRd_AmdFam10hOsVisWrkStatus,
4610	cpumMsrRd_AmdFam16hL2IPerfCtlN,
4611	cpumMsrRd_AmdFam16hL2IPerfCtrN,
4612	cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4613	cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4614	cpumMsrRd_AmdK7MicrocodeCtl,
4615	cpumMsrRd_AmdK7ClusterIdMaybe,
4616	cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4617	cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4618	cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4619	cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4620	cpumMsrRd_AmdK8PatchLevel,
4621	cpumMsrRd_AmdK7DebugStatusMaybe,
4622	cpumMsrRd_AmdK7BHTraceBaseMaybe,
4623	cpumMsrRd_AmdK7BHTracePtrMaybe,
4624	cpumMsrRd_AmdK7BHTraceLimitMaybe,
4625	cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4626	cpumMsrRd_AmdK7FastFlushCountMaybe,
4627	cpumMsrRd_AmdK7NodeId,
4628	cpumMsrRd_AmdK7DrXAddrMaskN,
4629	cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4630	cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4631	cpumMsrRd_AmdK7LoadStoreCfg,
4632	cpumMsrRd_AmdK7InstrCacheCfg,
4633	cpumMsrRd_AmdK7DataCacheCfg,
4634	cpumMsrRd_AmdK7BusUnitCfg,
4635	cpumMsrRd_AmdK7DebugCtl2Maybe,
4636	cpumMsrRd_AmdFam15hFpuCfg,
4637	cpumMsrRd_AmdFam15hDecoderCfg,
4638	cpumMsrRd_AmdFam10hBusUnitCfg2,
4639	cpumMsrRd_AmdFam15hCombUnitCfg,
4640	cpumMsrRd_AmdFam15hCombUnitCfg2,
4641	cpumMsrRd_AmdFam15hCombUnitCfg3,
4642	cpumMsrRd_AmdFam15hExecUnitCfg,
4643	cpumMsrRd_AmdFam15hLoadStoreCfg2,
4644	cpumMsrRd_AmdFam10hIbsFetchCtl,
4645	cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4646	cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4647	cpumMsrRd_AmdFam10hIbsOpExecCtl,
4648	cpumMsrRd_AmdFam10hIbsOpRip,
4649	cpumMsrRd_AmdFam10hIbsOpData,
4650	cpumMsrRd_AmdFam10hIbsOpData2,
4651	cpumMsrRd_AmdFam10hIbsOpData3,
4652	cpumMsrRd_AmdFam10hIbsDcLinAddr,
4653	cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4654	cpumMsrRd_AmdFam10hIbsCtl,
4655	cpumMsrRd_AmdFam14hIbsBrTarget,
4656
4657	cpumMsrRd_Gim
4658	};
4659
4660
4661	/**
4662	* MSR write function table.
4663	*/
4664	static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4665	{
4666	NULL, /* Invalid */
4667	cpumMsrWr_IgnoreWrite,
4668	cpumMsrWr_ReadOnly,
4669	NULL, /* Alias */
4670	cpumMsrWr_Ia32P5McAddr,
4671	cpumMsrWr_Ia32P5McType,
4672	cpumMsrWr_Ia32TimestampCounter,
4673	cpumMsrWr_Ia32ApicBase,
4674	cpumMsrWr_Ia32FeatureControl,
4675	cpumMsrWr_Ia32BiosSignId,
4676	cpumMsrWr_Ia32BiosUpdateTrigger,
4677	cpumMsrWr_Ia32SmmMonitorCtl,
4678	cpumMsrWr_Ia32PmcN,
4679	cpumMsrWr_Ia32MonitorFilterLineSize,
4680	cpumMsrWr_Ia32MPerf,
4681	cpumMsrWr_Ia32APerf,
4682	cpumMsrWr_Ia32MtrrPhysBaseN,
4683	cpumMsrWr_Ia32MtrrPhysMaskN,
4684	cpumMsrWr_Ia32MtrrFixed,
4685	cpumMsrWr_Ia32MtrrDefType,
4686	cpumMsrWr_Ia32Pat,
4687	cpumMsrWr_Ia32SysEnterCs,
4688	cpumMsrWr_Ia32SysEnterEsp,
4689	cpumMsrWr_Ia32SysEnterEip,
4690	cpumMsrWr_Ia32McgStatus,
4691	cpumMsrWr_Ia32McgCtl,
4692	cpumMsrWr_Ia32DebugCtl,
4693	cpumMsrWr_Ia32SmrrPhysBase,
4694	cpumMsrWr_Ia32SmrrPhysMask,
4695	cpumMsrWr_Ia32PlatformDcaCap,
4696	cpumMsrWr_Ia32Dca0Cap,
4697	cpumMsrWr_Ia32PerfEvtSelN,
4698	cpumMsrWr_Ia32PerfStatus,
4699	cpumMsrWr_Ia32PerfCtl,
4700	cpumMsrWr_Ia32FixedCtrN,
4701	cpumMsrWr_Ia32PerfCapabilities,
4702	cpumMsrWr_Ia32FixedCtrCtrl,
4703	cpumMsrWr_Ia32PerfGlobalStatus,
4704	cpumMsrWr_Ia32PerfGlobalCtrl,
4705	cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4706	cpumMsrWr_Ia32PebsEnable,
4707	cpumMsrWr_Ia32ClockModulation,
4708	cpumMsrWr_Ia32ThermInterrupt,
4709	cpumMsrWr_Ia32ThermStatus,
4710	cpumMsrWr_Ia32Therm2Ctl,
4711	cpumMsrWr_Ia32MiscEnable,
4712	cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4713	cpumMsrWr_Ia32McNCtl2,
4714	cpumMsrWr_Ia32DsArea,
4715	cpumMsrWr_Ia32TscDeadline,
4716	cpumMsrWr_Ia32X2ApicN,
4717	cpumMsrWr_Ia32DebugInterface,
4718
4719	cpumMsrWr_Amd64Efer,
4720	cpumMsrWr_Amd64SyscallTarget,
4721	cpumMsrWr_Amd64LongSyscallTarget,
4722	cpumMsrWr_Amd64CompSyscallTarget,
4723	cpumMsrWr_Amd64SyscallFlagMask,
4724	cpumMsrWr_Amd64FsBase,
4725	cpumMsrWr_Amd64GsBase,
4726	cpumMsrWr_Amd64KernelGsBase,
4727	cpumMsrWr_Amd64TscAux,
4728
4729	cpumMsrWr_IntelEblCrPowerOn,
4730	cpumMsrWr_IntelP4EbcHardPowerOn,
4731	cpumMsrWr_IntelP4EbcSoftPowerOn,
4732	cpumMsrWr_IntelP4EbcFrequencyId,
4733	cpumMsrWr_IntelFlexRatio,
4734	cpumMsrWr_IntelPkgCStConfigControl,
4735	cpumMsrWr_IntelPmgIoCaptureBase,
4736	cpumMsrWr_IntelLastBranchFromToN,
4737	cpumMsrWr_IntelLastBranchFromN,
4738	cpumMsrWr_IntelLastBranchToN,
4739	cpumMsrWr_IntelLastBranchTos,
4740	cpumMsrWr_IntelBblCrCtl,
4741	cpumMsrWr_IntelBblCrCtl3,
4742	cpumMsrWr_IntelI7TemperatureTarget,
4743	cpumMsrWr_IntelI7MsrOffCoreResponseN,
4744	cpumMsrWr_IntelI7MiscPwrMgmt,
4745	cpumMsrWr_IntelP6CrN,
4746	cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4747	cpumMsrWr_IntelCpuId1FeatureMaskEax,
4748	cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4749	cpumMsrWr_IntelI7SandyAesNiCtl,
4750	cpumMsrWr_IntelI7TurboRatioLimit,
4751	cpumMsrWr_IntelI7LbrSelect,
4752	cpumMsrWr_IntelI7SandyErrorControl,
4753	cpumMsrWr_IntelI7PowerCtl,
4754	cpumMsrWr_IntelI7SandyPebsNumAlt,
4755	cpumMsrWr_IntelI7PebsLdLat,
4756	cpumMsrWr_IntelI7SandyVrCurrentConfig,
4757	cpumMsrWr_IntelI7SandyVrMiscConfig,
4758	cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4759	cpumMsrWr_IntelI7RaplPkgPowerLimit,
4760	cpumMsrWr_IntelI7RaplDramPowerLimit,
4761	cpumMsrWr_IntelI7RaplPp0PowerLimit,
4762	cpumMsrWr_IntelI7RaplPp0Policy,
4763	cpumMsrWr_IntelI7RaplPp1PowerLimit,
4764	cpumMsrWr_IntelI7RaplPp1Policy,
4765	cpumMsrWr_IntelI7IvyConfigTdpControl,
4766	cpumMsrWr_IntelI7IvyTurboActivationRatio,
4767	cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4768	cpumMsrWr_IntelI7UncPerfGlobalStatus,
4769	cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4770	cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4771	cpumMsrWr_IntelI7UncPerfFixedCtr,
4772	cpumMsrWr_IntelI7UncArbPerfCtrN,
4773	cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4774	cpumMsrWr_IntelCore2EmttmCrTablesN,
4775	cpumMsrWr_IntelCore2SmmCStMiscInfo,
4776	cpumMsrWr_IntelCore1ExtConfig,
4777	cpumMsrWr_IntelCore1DtsCalControl,
4778	cpumMsrWr_IntelCore2PeciControl,
4779
4780	cpumMsrWr_P6LastIntFromIp,
4781	cpumMsrWr_P6LastIntToIp,
4782
4783	cpumMsrWr_AmdFam15hTscRate,
4784	cpumMsrWr_AmdFam15hLwpCfg,
4785	cpumMsrWr_AmdFam15hLwpCbAddr,
4786	cpumMsrWr_AmdFam10hMc4MiscN,
4787	cpumMsrWr_AmdK8PerfCtlN,
4788	cpumMsrWr_AmdK8PerfCtrN,
4789	cpumMsrWr_AmdK8SysCfg,
4790	cpumMsrWr_AmdK8HwCr,
4791	cpumMsrWr_AmdK8IorrBaseN,
4792	cpumMsrWr_AmdK8IorrMaskN,
4793	cpumMsrWr_AmdK8TopOfMemN,
4794	cpumMsrWr_AmdK8NbCfg1,
4795	cpumMsrWr_AmdK8McXcptRedir,
4796	cpumMsrWr_AmdK8CpuNameN,
4797	cpumMsrWr_AmdK8HwThermalCtrl,
4798	cpumMsrWr_AmdK8SwThermalCtrl,
4799	cpumMsrWr_AmdK8FidVidControl,
4800	cpumMsrWr_AmdK8McCtlMaskN,
4801	cpumMsrWr_AmdK8SmiOnIoTrapN,
4802	cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4803	cpumMsrWr_AmdK8IntPendingMessage,
4804	cpumMsrWr_AmdK8SmiTriggerIoCycle,
4805	cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4806	cpumMsrWr_AmdFam10hTrapCtlMaybe,
4807	cpumMsrWr_AmdFam10hPStateControl,
4808	cpumMsrWr_AmdFam10hPStateStatus,
4809	cpumMsrWr_AmdFam10hPStateN,
4810	cpumMsrWr_AmdFam10hCofVidControl,
4811	cpumMsrWr_AmdFam10hCofVidStatus,
4812	cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4813	cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4814	cpumMsrWr_AmdK8SmmBase,
4815	cpumMsrWr_AmdK8SmmAddr,
4816	cpumMsrWr_AmdK8SmmMask,
4817	cpumMsrWr_AmdK8VmCr,
4818	cpumMsrWr_AmdK8IgnNe,
4819	cpumMsrWr_AmdK8SmmCtl,
4820	cpumMsrWr_AmdK8VmHSavePa,
4821	cpumMsrWr_AmdFam10hVmLockKey,
4822	cpumMsrWr_AmdFam10hSmmLockKey,
4823	cpumMsrWr_AmdFam10hLocalSmiStatus,
4824	cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4825	cpumMsrWr_AmdFam10hOsVisWrkStatus,
4826	cpumMsrWr_AmdFam16hL2IPerfCtlN,
4827	cpumMsrWr_AmdFam16hL2IPerfCtrN,
4828	cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4829	cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4830	cpumMsrWr_AmdK7MicrocodeCtl,
4831	cpumMsrWr_AmdK7ClusterIdMaybe,
4832	cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4833	cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4834	cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4835	cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4836	cpumMsrWr_AmdK8PatchLoader,
4837	cpumMsrWr_AmdK7DebugStatusMaybe,
4838	cpumMsrWr_AmdK7BHTraceBaseMaybe,
4839	cpumMsrWr_AmdK7BHTracePtrMaybe,
4840	cpumMsrWr_AmdK7BHTraceLimitMaybe,
4841	cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4842	cpumMsrWr_AmdK7FastFlushCountMaybe,
4843	cpumMsrWr_AmdK7NodeId,
4844	cpumMsrWr_AmdK7DrXAddrMaskN,
4845	cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4846	cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4847	cpumMsrWr_AmdK7LoadStoreCfg,
4848	cpumMsrWr_AmdK7InstrCacheCfg,
4849	cpumMsrWr_AmdK7DataCacheCfg,
4850	cpumMsrWr_AmdK7BusUnitCfg,
4851	cpumMsrWr_AmdK7DebugCtl2Maybe,
4852	cpumMsrWr_AmdFam15hFpuCfg,
4853	cpumMsrWr_AmdFam15hDecoderCfg,
4854	cpumMsrWr_AmdFam10hBusUnitCfg2,
4855	cpumMsrWr_AmdFam15hCombUnitCfg,
4856	cpumMsrWr_AmdFam15hCombUnitCfg2,
4857	cpumMsrWr_AmdFam15hCombUnitCfg3,
4858	cpumMsrWr_AmdFam15hExecUnitCfg,
4859	cpumMsrWr_AmdFam15hLoadStoreCfg2,
4860	cpumMsrWr_AmdFam10hIbsFetchCtl,
4861	cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4862	cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4863	cpumMsrWr_AmdFam10hIbsOpExecCtl,
4864	cpumMsrWr_AmdFam10hIbsOpRip,
4865	cpumMsrWr_AmdFam10hIbsOpData,
4866	cpumMsrWr_AmdFam10hIbsOpData2,
4867	cpumMsrWr_AmdFam10hIbsOpData3,
4868	cpumMsrWr_AmdFam10hIbsDcLinAddr,
4869	cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4870	cpumMsrWr_AmdFam10hIbsCtl,
4871	cpumMsrWr_AmdFam14hIbsBrTarget,
4872
4873	cpumMsrWr_Gim
4874	};
4875
4876
4877	/**
4878	* Looks up the range for the given MSR.
4879	*
4880	* @returns Pointer to the range if found, NULL if not.
4881	* @param pVM The cross context VM structure.
4882	* @param idMsr The MSR to look up.
4883	*/
4884	# ifndef IN_RING3
4885	static
4886	# endif
4887	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4888	{
4889	/*
4890	* Binary lookup.
4891	*/
4892	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4893	if (!cRanges)
4894	return NULL;
4895	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4896	for (;;)
4897	{
4898	uint32_t i = cRanges / 2;
4899	if (idMsr < paRanges[i].uFirst)
4900	{
4901	if (i == 0)
4902	break;
4903	cRanges = i;
4904	}
4905	else if (idMsr > paRanges[i].uLast)
4906	{
4907	i++;
4908	if (i >= cRanges)
4909	break;
4910	cRanges -= i;
4911	paRanges = &paRanges[i];
4912	}
4913	else
4914	{
4915	if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4916	return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4917	return &paRanges[i];
4918	}
4919	}
4920
4921	# ifdef VBOX_STRICT
4922	/*
4923	* Linear lookup to verify the above binary search.
4924	*/
4925	uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4926	PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4927	while (cLeft-- > 0)
4928	{
4929	if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4930	{
4931	AssertFailed();
4932	if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4933	return cpumLookupMsrRange(pVM, pCur->uValue);
4934	return pCur;
4935	}
4936	pCur++;
4937	}
4938	# endif
4939	return NULL;
4940	}
4941
4942
4943	/**
4944	* Query a guest MSR.
4945	*
4946	* The caller is responsible for checking privilege if the call is the result of
4947	* a RDMSR instruction. We'll do the rest.
4948	*
4949	* @retval VINF_SUCCESS on success.
4950	* @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
4951	* current context (raw-mode or ring-0).
4952	* @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4953	* expected to take the appropriate actions. @a *puValue is set to 0.
4954	* @param pVCpu The cross context virtual CPU structure.
4955	* @param idMsr The MSR.
4956	* @param puValue Where to return the value.
4957	*
4958	* @remarks This will always return the right values, even when we're in the
4959	* recompiler.
4960	*/
4961	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4962	{
4963	*puValue = 0;
4964
4965	VBOXSTRICTRC rcStrict;
4966	PVM pVM = pVCpu->CTX_SUFF(pVM);
4967	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4968	if (pRange)
4969	{
4970	CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4971	AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4972
4973	PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
4974	AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
4975
4976	STAM_COUNTER_INC(&pRange->cReads);
4977	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4978
4979	rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
4980	if (rcStrict == VINF_SUCCESS)
4981	Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
4982	else if (rcStrict == VERR_CPUM_RAISE_GP_0)
4983	{
4984	Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
4985	STAM_COUNTER_INC(&pRange->cGps);
4986	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
4987	}
4988	#ifndef IN_RING3
4989	else if (rcStrict == VINF_CPUM_R3_MSR_READ)
4990	Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
4991	#endif
4992	else
4993	{
4994	Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
4995	AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
4996	rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
4997	Assert(rcStrict != VERR_EM_INTERPRETER);
4998	}
4999	}
5000	else
5001	{
5002	Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5003	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5004	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5005	rcStrict = VERR_CPUM_RAISE_GP_0;
5006	}
5007	return rcStrict;
5008	}
5009
5010
5011	/**
5012	* Writes to a guest MSR.
5013	*
5014	* The caller is responsible for checking privilege if the call is the result of
5015	* a WRMSR instruction. We'll do the rest.
5016	*
5017	* @retval VINF_SUCCESS on success.
5018	* @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5019	* current context (raw-mode or ring-0).
5020	* @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5021	* appropriate actions.
5022	*
5023	* @param pVCpu The cross context virtual CPU structure.
5024	* @param idMsr The MSR id.
5025	* @param uValue The value to set.
5026	*
5027	* @remarks Everyone changing MSR values, including the recompiler, shall do it
5028	* by calling this method. This makes sure we have current values and
5029	* that we trigger all the right actions when something changes.
5030	*
5031	* For performance reasons, this actually isn't entirely true for some
5032	* MSRs when in HM mode. The code here and in HM must be aware of
5033	* this.
5034	*/
5035	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5036	{
5037	VBOXSTRICTRC rcStrict;
5038	PVM pVM = pVCpu->CTX_SUFF(pVM);
5039	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5040	if (pRange)
5041	{
5042	STAM_COUNTER_INC(&pRange->cWrites);
5043	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5044
5045	if (!(uValue & pRange->fWrGpMask))
5046	{
5047	CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5048	AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5049
5050	PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5051	AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5052
5053	uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5054	if (uValueAdjusted != uValue)
5055	{
5056	STAM_COUNTER_INC(&pRange->cIgnoredBits);
5057	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5058	}
5059
5060	rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5061	if (rcStrict == VINF_SUCCESS)
5062	Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5063	else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5064	{
5065	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5066	STAM_COUNTER_INC(&pRange->cGps);
5067	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5068	}
5069	#ifndef IN_RING3
5070	else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5071	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5072	#endif
5073	else
5074	{
5075	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5076	idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5077	AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5078	rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5079	Assert(rcStrict != VERR_EM_INTERPRETER);
5080	}
5081	}
5082	else
5083	{
5084	Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5085	idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5086	STAM_COUNTER_INC(&pRange->cGps);
5087	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5088	rcStrict = VERR_CPUM_RAISE_GP_0;
5089	}
5090	}
5091	else
5092	{
5093	Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5094	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5095	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5096	rcStrict = VERR_CPUM_RAISE_GP_0;
5097	}
5098	return rcStrict;
5099	}
5100
5101
5102	#if defined(VBOX_STRICT) && defined(IN_RING3)
5103	/**
5104	* Performs some checks on the static data related to MSRs.
5105	*
5106	* @returns VINF_SUCCESS on success, error on failure.
5107	*/
5108	int cpumR3MsrStrictInitChecks(void)
5109	{
5110	#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5111	AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5112	#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5113	AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5114
5115	AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5116	CPUM_ASSERT_RD_MSR_FN(FixedValue);
5117	CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5118	CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5119	CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5120	CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5121	CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5122	CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5123	CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5124	CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5125	CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5126	CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5127	CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5128	CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5129	CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5130	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5131	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5132	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5133	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5134	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5135	CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5136	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5137	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5138	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5139	CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5140	CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5141	CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5142	CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5143	CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5144	CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5145	CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5146	CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5147	CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5148	CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5149	CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5150	CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5151	CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5152	CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5153	CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5154	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5155	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5156	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5157	CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5158	CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5159	CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5160	CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5161	CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5162	CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5163	CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5164	CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5165	CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5166	CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5167	CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5168	CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5169	CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5170	CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5171	CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5172	CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5173	CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5174	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5175	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5176	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5177	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5178	CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5179	CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5180	CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5181	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5182	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5183	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5184	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5185
5186	CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5187	CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5188	CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5189	CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5190	CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5191	CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5192	CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5193	CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5194	CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5195
5196	CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5197	CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5198	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5199	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5200	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5201	CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5202	CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5203	CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5204	CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5205	CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5206	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5207	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5208	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5209	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5210	CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5211	CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5212	CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5213	CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5214	CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5215	CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5216	CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5217	CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5218	CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5219	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5220	CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5221	CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5222	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5223	CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5224	CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5225	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5226	CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5227	CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5228	CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5229	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5230	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5231	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5232	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5233	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5234	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5235	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5236	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5237	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5238	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5239	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5240	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5241	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5242	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5243	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5244	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5245	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5246	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5247	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5248	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5249	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5250	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5251	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5252	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5253	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5254	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5255	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5256	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5257	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5258	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5259	CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5260	CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5261	CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5262	CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5263	CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5264	CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5265	CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5266	CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5267
5268	CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5269	CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5270	CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5271	CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5272
5273	CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5274	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5275	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5276	CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5277	CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5278	CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5279	CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5280	CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5281	CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5282	CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5283	CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5284	CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5285	CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5286	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5287	CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5288	CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5289	CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5290	CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5291	CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5292	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5293	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5294	CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5295	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5296	CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5297	CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5298	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5299	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5300	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5301	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5302	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5303	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5304	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5305	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5306	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5307	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5308	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5309	CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5310	CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5311	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5312	CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5313	CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5314	CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5315	CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5316	CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5317	CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5318	CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5319	CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5320	CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5321	CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5322	CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5323	CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5324	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5325	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5326	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5327	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5328	CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5329	CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5330	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5331	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5332	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5333	CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5334	CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5335	CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5336	CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5337	CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5338	CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5339	CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5340	CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5341	CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5342	CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5343	CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5344	CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5345	CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5346	CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5347	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5348	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5349	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5350	CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5351	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5352	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5353	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5354	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5355	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5356	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5357	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5358	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5359	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5360	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5361	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5362	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5363	CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5364
5365	CPUM_ASSERT_RD_MSR_FN(Gim)
5366
5367	AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5368	CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5369	CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5370	CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5371	CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5372	CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5373	CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5374	CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5375	CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5376	CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5377	CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5378	CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5379	CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5380	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5381	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5382	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5383	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5384	CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5385	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5386	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5387	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5388	CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5389	CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5390	CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5391	CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5392	CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5393	CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5394	CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5395	CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5396	CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5397	CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5398	CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5399	CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5400	CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5401	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5402	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5403	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5404	CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5405	CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5406	CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5407	CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5408	CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5409	CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5410	CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5411	CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5412	CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5413	CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5414	CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5415
5416	CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5417	CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5418	CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5419	CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5420	CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5421	CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5422	CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5423	CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5424	CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5425
5426	CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5427	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5428	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5429	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5430	CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
5431	CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5432	CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5433	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5434	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5435	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5436	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5437	CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5438	CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5439	CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5440	CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5441	CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5442	CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5443	CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5444	CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5445	CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5446	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5447	CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5448	CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5449	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5450	CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5451	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5452	CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5453	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5454	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5455	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5456	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5457	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5458	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5459	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5460	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5461	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5462	CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5463	CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5464	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5465	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5466	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5467	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5468	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5469	CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5470	CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5471	CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5472	CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5473	CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5474	CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5475	CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5476
5477	CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5478	CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5479
5480	CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5481	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5482	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5483	CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5484	CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5485	CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5486	CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5487	CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5488	CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5489	CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5490	CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5491	CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5492	CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5493	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5494	CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5495	CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5496	CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5497	CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5498	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5499	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5500	CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5501	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5502	CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5503	CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5504	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5505	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5506	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5507	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5508	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5509	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5510	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5511	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5512	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5513	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5514	CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5515	CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5516	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5517	CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5518	CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5519	CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5520	CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5521	CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5522	CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5523	CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5524	CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5525	CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5526	CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5527	CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5528	CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5529	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5530	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5531	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5532	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5533	CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5534	CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5535	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5536	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5537	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5538	CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5539	CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5540	CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5541	CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5542	CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5543	CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5544	CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5545	CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5546	CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5547	CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5548	CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5549	CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5550	CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5551	CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5552	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5553	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5554	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5555	CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5556	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5557	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5558	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5559	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5560	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5561	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5562	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5563	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5564	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5565	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5566	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5567	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5568	CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5569
5570	CPUM_ASSERT_WR_MSR_FN(Gim);
5571
5572	return VINF_SUCCESS;
5573	}
5574	#endif /* VBOX_STRICT && IN_RING3 */
5575
5576
5577	/**
5578	* Gets the scalable bus frequency.
5579	*
5580	* The bus frequency is used as a base in several MSRs that gives the CPU and
5581	* other frequency ratios.
5582	*
5583	* @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
5584	* @param pVM The cross context VM structure.
5585	*/
5586	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
5587	{
5588	uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
5589	if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
5590	uFreq = CPUM_SBUSFREQ_100MHZ;
5591	return uFreq;
5592	}
5593
5594
5595	#ifdef IN_RING0
5596
5597	/**
5598	* Fast way for HM to access the MSR_K8_TSC_AUX register.
5599	*
5600	* @returns The register value.
5601	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
5602	* @thread EMT(pVCpu)
5603	*/
5604	VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5605	{
5606	return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5607	}
5608
5609
5610	/**
5611	* Fast way for HM to access the MSR_K8_TSC_AUX register.
5612	*
5613	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
5614	* @param uValue The new value.
5615	* @thread EMT(pVCpu)
5616	*/
5617	VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5618	{
5619	pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5620	}
5621
5622	#endif /* IN_RING0 */
5623

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source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 60309

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