VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 50590

Last change on this file since 50590 was 50590, checked in by vboxsync, 11 years ago

CPUM,VMM: More work related to bus, cpu and tsc frequency info. Should cover older core and p6 as well as p4 now.
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1/* $Id: CPUMAllMsrs.cpp 50590 2014-02-25 18:51:23Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/pdmapi.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/tm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/err.h>
29
30
31/*******************************************************************************
32* Defined Constants And Macros *
33*******************************************************************************/
34/**
35 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
36 * pointing to it.
37 *
38 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
39 * correctly.
40 */
41#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
42 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
43 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
44 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
45 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
46 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
47 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53
54/**
55 * Implements reading one or more MSRs.
56 *
57 * @returns VBox status code.
58 * @retval VINF_SUCCESS on success.
59 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
60 *
61 * @param pVCpu Pointer to the VMCPU.
62 * @param idMsr The MSR we're reading.
63 * @param pRange The MSR range descriptor.
64 * @param puValue Where to return the value.
65 */
66typedef DECLCALLBACK(int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
67/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
68typedef FNCPUMRDMSR *PFNCPUMRDMSR;
69
70
71/**
72 * Implements writing one or more MSRs.
73 *
74 * @retval VINF_SUCCESS on success.
75 * @retval VERR_CPUM_RAISE_GP_0 on failure.
76 *
77 * @param pVCpu Pointer to the VMCPU.
78 * @param idMsr The MSR we're writing.
79 * @param pRange The MSR range descriptor.
80 * @param uValue The value to set, ignored bits masked.
81 * @param uRawValue The raw value with the ignored bits not masked.
82 */
83typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
84/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
85typedef FNCPUMWRMSR *PFNCPUMWRMSR;
86
87
88
89/*
90 * Generic functions.
91 * Generic functions.
92 * Generic functions.
93 */
94
95
96/** @callback_method_impl{FNCPUMRDMSR} */
97static DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
98{
99 *puValue = pRange->uValue;
100 return VINF_SUCCESS;
101}
102
103
104/** @callback_method_impl{FNCPUMWRMSR} */
105static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
106{
107 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
108 return VINF_SUCCESS;
109}
110
111
112/** @callback_method_impl{FNCPUMRDMSR} */
113static DECLCALLBACK(int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
114{
115 return VERR_CPUM_RAISE_GP_0;
116}
117
118
119/** @callback_method_impl{FNCPUMWRMSR} */
120static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
121{
122 Assert(pRange->fWrGpMask == UINT64_MAX);
123 return VERR_CPUM_RAISE_GP_0;
124}
125
126
127
128
129/*
130 * IA32
131 * IA32
132 * IA32
133 */
134
135/** @callback_method_impl{FNCPUMRDMSR} */
136static DECLCALLBACK(int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
137{
138 *puValue = 0; /** @todo implement machine check injection. */
139 return VINF_SUCCESS;
140}
141
142
143/** @callback_method_impl{FNCPUMWRMSR} */
144static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
145{
146 /** @todo implement machine check injection. */
147 return VINF_SUCCESS;
148}
149
150
151/** @callback_method_impl{FNCPUMRDMSR} */
152static DECLCALLBACK(int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
153{
154 *puValue = 0; /** @todo implement machine check injection. */
155 return VINF_SUCCESS;
156}
157
158
159/** @callback_method_impl{FNCPUMWRMSR} */
160static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
161{
162 /** @todo implement machine check injection. */
163 return VINF_SUCCESS;
164}
165
166
167/** @callback_method_impl{FNCPUMRDMSR} */
168static DECLCALLBACK(int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
169{
170 *puValue = TMCpuTickGet(pVCpu);
171 return VINF_SUCCESS;
172}
173
174
175/** @callback_method_impl{FNCPUMWRMSR} */
176static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
177{
178 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
179 return VINF_SUCCESS;
180}
181
182
183/** @callback_method_impl{FNCPUMRDMSR} */
184static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
185{
186 uint64_t uValue = pRange->uValue;
187 if (uValue & 0x1f00)
188 {
189 /* Max allowed bus ratio present. */
190 /** @todo Implement scaled BUS frequency. */
191 }
192
193 *puValue = uValue;
194 return VINF_SUCCESS;
195}
196
197
198/** @callback_method_impl{FNCPUMRDMSR} */
199static DECLCALLBACK(int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
200{
201 PVM pVM = pVCpu->CTX_SUFF(pVM);
202 if ( !pVM->cpum.s.GuestFeatures.fApic
203 && !pVM->cpum.s.GuestFeatures.fX2Apic)
204 {
205 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
206 return VERR_CPUM_RAISE_GP_0;
207 }
208
209 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
210 return VINF_SUCCESS;
211}
212
213
214/** @callback_method_impl{FNCPUMWRMSR} */
215static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
216{
217 int rc = PDMApicSetBase(pVCpu, uValue);
218 if (rc != VINF_SUCCESS)
219 rc = VERR_CPUM_RAISE_GP_0;
220 return VINF_SUCCESS;
221}
222
223
224/** @callback_method_impl{FNCPUMRDMSR} */
225static DECLCALLBACK(int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
226{
227 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
228 return VINF_SUCCESS;
229}
230
231
232/** @callback_method_impl{FNCPUMWRMSR} */
233static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
234{
235 return VERR_CPUM_RAISE_GP_0;
236}
237
238
239/** @callback_method_impl{FNCPUMRDMSR} */
240static DECLCALLBACK(int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
241{
242 /** @todo fake microcode update. */
243 *puValue = pRange->uValue;
244 return VINF_SUCCESS;
245}
246
247
248/** @callback_method_impl{FNCPUMWRMSR} */
249static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
250{
251 /* Normally, zero is written to Ia32BiosSignId before reading it in order
252 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
253 of the database entry should take care of most illegal writes for now, so
254 just ignore all writes atm. */
255 return VINF_SUCCESS;
256}
257
258
259/** @callback_method_impl{FNCPUMWRMSR} */
260static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
261{
262 /** @todo Fake bios update trigger better. The value is the address to an
263 * update package, I think. We should probably GP if it's invalid. */
264 return VINF_SUCCESS;
265}
266
267
268/** @callback_method_impl{FNCPUMRDMSR} */
269static DECLCALLBACK(int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
270{
271 /** @todo SMM. */
272 *puValue = 0;
273 return VINF_SUCCESS;
274}
275
276
277/** @callback_method_impl{FNCPUMWRMSR} */
278static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
279{
280 /** @todo SMM. */
281 return VINF_SUCCESS;
282}
283
284
285/** @callback_method_impl{FNCPUMRDMSR} */
286static DECLCALLBACK(int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
287{
288 /** @todo check CPUID leaf 0ah. */
289 *puValue = 0;
290 return VINF_SUCCESS;
291}
292
293
294/** @callback_method_impl{FNCPUMWRMSR} */
295static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
296{
297 /** @todo check CPUID leaf 0ah. */
298 return VINF_SUCCESS;
299}
300
301
302/** @callback_method_impl{FNCPUMRDMSR} */
303static DECLCALLBACK(int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
304{
305 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
306 *puValue = 0x40; /** @todo Change to CPU cache line size. */
307 return VINF_SUCCESS;
308}
309
310
311/** @callback_method_impl{FNCPUMWRMSR} */
312static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
313{
314 /** @todo should remember writes, though it's supposedly something only a BIOS
315 * would write so, it's not extremely important. */
316 return VINF_SUCCESS;
317}
318
319/** @callback_method_impl{FNCPUMRDMSR} */
320static DECLCALLBACK(int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
321{
322 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
323 * what we want? */
324 *puValue = TMCpuTickGet(pVCpu);
325 return VINF_SUCCESS;
326}
327
328
329/** @callback_method_impl{FNCPUMWRMSR} */
330static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
331{
332 /** @todo Write MPERF: Calc adjustment. */
333 return VINF_SUCCESS;
334}
335
336
337/** @callback_method_impl{FNCPUMRDMSR} */
338static DECLCALLBACK(int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
339{
340 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
341 * what we want? */
342 *puValue = TMCpuTickGet(pVCpu);
343 return VINF_SUCCESS;
344}
345
346
347/** @callback_method_impl{FNCPUMWRMSR} */
348static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
349{
350 /** @todo Write APERF: Calc adjustment. */
351 return VINF_SUCCESS;
352}
353
354
355/** @callback_method_impl{FNCPUMWRMSR} */
356static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
357{
358 /* This is currently a bit weird. :-) */
359 uint8_t const cVariableRangeRegs = 0;
360 bool const fSystemManagementRangeRegisters = false;
361 bool const fFixedRangeRegisters = false;
362 bool const fWriteCombiningType = false;
363 *puValue = cVariableRangeRegs
364 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
365 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
366 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
367 return VINF_SUCCESS;
368}
369
370
371/** @callback_method_impl{FNCPUMRDMSR} */
372static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
373{
374 /** @todo Implement variable MTRR storage. */
375 Assert(pRange->uValue == (idMsr - 0x200) / 2);
376 *puValue = 0;
377 return VINF_SUCCESS;
378}
379
380
381/** @callback_method_impl{FNCPUMWRMSR} */
382static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
383{
384 /*
385 * Validate the value.
386 */
387 Assert(pRange->uValue == (idMsr - 0x200) / 2);
388
389 if ((uValue & 0xff) >= 7)
390 {
391 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
392 return VERR_CPUM_RAISE_GP_0;
393 }
394
395 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
396 if (fInvPhysMask & uValue)
397 {
398 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
399 idMsr, uValue, uValue & fInvPhysMask));
400 return VERR_CPUM_RAISE_GP_0;
401 }
402
403 /*
404 * Store it.
405 */
406 /** @todo Implement variable MTRR storage. */
407 return VINF_SUCCESS;
408}
409
410
411/** @callback_method_impl{FNCPUMRDMSR} */
412static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
413{
414 /** @todo Implement variable MTRR storage. */
415 Assert(pRange->uValue == (idMsr - 0x200) / 2);
416 *puValue = 0;
417 return VINF_SUCCESS;
418}
419
420
421/** @callback_method_impl{FNCPUMWRMSR} */
422static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
423{
424 /*
425 * Validate the value.
426 */
427 Assert(pRange->uValue == (idMsr - 0x200) / 2);
428
429 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
430 if (fInvPhysMask & uValue)
431 {
432 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
433 idMsr, uValue, uValue & fInvPhysMask));
434 return VERR_CPUM_RAISE_GP_0;
435 }
436
437 /*
438 * Store it.
439 */
440 /** @todo Implement variable MTRR storage. */
441 return VINF_SUCCESS;
442}
443
444
445/** @callback_method_impl{FNCPUMRDMSR} */
446static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
447{
448 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
449 *puValue = *puFixedMtrr;
450 return VINF_SUCCESS;
451}
452
453
454/** @callback_method_impl{FNCPUMWRMSR} */
455static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
456{
457 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
458 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
459 {
460 uint8_t uType = (uint8_t)(uValue >> cShift);
461 if (uType >= 7)
462 {
463 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
464 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
465 return VERR_CPUM_RAISE_GP_0;
466 }
467 }
468 *puFixedMtrr = uValue;
469 return VINF_SUCCESS;
470}
471
472
473/** @callback_method_impl{FNCPUMRDMSR} */
474static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
475{
476 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
477 return VINF_SUCCESS;
478}
479
480
481/** @callback_method_impl{FNCPUMWRMSR} */
482static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
483{
484 if ((uValue & 0xff) >= 7)
485 {
486 Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
487 return VERR_CPUM_RAISE_GP_0;
488 }
489
490 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
491 return VINF_SUCCESS;
492}
493
494
495/** @callback_method_impl{FNCPUMRDMSR} */
496static DECLCALLBACK(int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
497{
498 *puValue = pVCpu->cpum.s.Guest.msrPAT;
499 return VINF_SUCCESS;
500}
501
502
503/** @callback_method_impl{FNCPUMWRMSR} */
504static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
505{
506 pVCpu->cpum.s.Guest.msrPAT = uValue;
507 return VINF_SUCCESS;
508}
509
510
511/** @callback_method_impl{FNCPUMRDMSR} */
512static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
513{
514 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
515 return VINF_SUCCESS;
516}
517
518
519/** @callback_method_impl{FNCPUMWRMSR} */
520static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
521{
522 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
523 there are generally 32-bit working bits backing this register. */
524 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
525 return VINF_SUCCESS;
526}
527
528
529/** @callback_method_impl{FNCPUMRDMSR} */
530static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
531{
532 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
533 return VINF_SUCCESS;
534}
535
536
537/** @callback_method_impl{FNCPUMWRMSR} */
538static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
539{
540 if (X86_IS_CANONICAL(uValue))
541 {
542 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
543 return VINF_SUCCESS;
544 }
545 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
546 return VERR_CPUM_RAISE_GP_0;
547}
548
549
550/** @callback_method_impl{FNCPUMRDMSR} */
551static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
552{
553 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
554 return VINF_SUCCESS;
555}
556
557
558/** @callback_method_impl{FNCPUMWRMSR} */
559static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
560{
561 if (X86_IS_CANONICAL(uValue))
562 {
563 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
564 return VINF_SUCCESS;
565 }
566 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
567 return VERR_CPUM_RAISE_GP_0;
568}
569
570
571/** @callback_method_impl{FNCPUMRDMSR} */
572static DECLCALLBACK(int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
573{
574#if 0 /** @todo implement machine checks. */
575 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
576#else
577 *puValue = 0;
578#endif
579 return VINF_SUCCESS;
580}
581
582
583/** @callback_method_impl{FNCPUMRDMSR} */
584static DECLCALLBACK(int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
585{
586 /** @todo implement machine checks. */
587 *puValue = 0;
588 return VINF_SUCCESS;
589}
590
591
592/** @callback_method_impl{FNCPUMWRMSR} */
593static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
594{
595 /** @todo implement machine checks. */
596 return VINF_SUCCESS;
597}
598
599
600/** @callback_method_impl{FNCPUMRDMSR} */
601static DECLCALLBACK(int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
602{
603 /** @todo implement machine checks. */
604 *puValue = 0;
605 return VINF_SUCCESS;
606}
607
608
609/** @callback_method_impl{FNCPUMWRMSR} */
610static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
611{
612 /** @todo implement machine checks. */
613 return VINF_SUCCESS;
614}
615
616
617/** @callback_method_impl{FNCPUMRDMSR} */
618static DECLCALLBACK(int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
619{
620 /** @todo implement IA32_DEBUGCTL. */
621 *puValue = 0;
622 return VINF_SUCCESS;
623}
624
625
626/** @callback_method_impl{FNCPUMWRMSR} */
627static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
628{
629 /** @todo implement IA32_DEBUGCTL. */
630 return VINF_SUCCESS;
631}
632
633
634/** @callback_method_impl{FNCPUMRDMSR} */
635static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
636{
637 /** @todo implement intel SMM. */
638 *puValue = 0;
639 return VINF_SUCCESS;
640}
641
642
643/** @callback_method_impl{FNCPUMWRMSR} */
644static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
645{
646 /** @todo implement intel SMM. */
647 return VERR_CPUM_RAISE_GP_0;
648}
649
650
651/** @callback_method_impl{FNCPUMRDMSR} */
652static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
653{
654 /** @todo implement intel SMM. */
655 *puValue = 0;
656 return VINF_SUCCESS;
657}
658
659
660/** @callback_method_impl{FNCPUMWRMSR} */
661static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
662{
663 /** @todo implement intel SMM. */
664 return VERR_CPUM_RAISE_GP_0;
665}
666
667
668/** @callback_method_impl{FNCPUMRDMSR} */
669static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
670{
671 /** @todo implement intel direct cache access (DCA)?? */
672 *puValue = 0;
673 return VINF_SUCCESS;
674}
675
676
677/** @callback_method_impl{FNCPUMWRMSR} */
678static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
679{
680 /** @todo implement intel direct cache access (DCA)?? */
681 return VINF_SUCCESS;
682}
683
684
685/** @callback_method_impl{FNCPUMRDMSR} */
686static DECLCALLBACK(int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
687{
688 /** @todo implement intel direct cache access (DCA)?? */
689 *puValue = 0;
690 return VINF_SUCCESS;
691}
692
693
694/** @callback_method_impl{FNCPUMRDMSR} */
695static DECLCALLBACK(int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
696{
697 /** @todo implement intel direct cache access (DCA)?? */
698 *puValue = 0;
699 return VINF_SUCCESS;
700}
701
702
703/** @callback_method_impl{FNCPUMWRMSR} */
704static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
705{
706 /** @todo implement intel direct cache access (DCA)?? */
707 return VINF_SUCCESS;
708}
709
710
711/** @callback_method_impl{FNCPUMRDMSR} */
712static DECLCALLBACK(int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
713{
714 /** @todo implement IA32_PERFEVTSEL0+. */
715 *puValue = 0;
716 return VINF_SUCCESS;
717}
718
719
720/** @callback_method_impl{FNCPUMWRMSR} */
721static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
722{
723 /** @todo implement IA32_PERFEVTSEL0+. */
724 return VINF_SUCCESS;
725}
726
727
728/** @callback_method_impl{FNCPUMRDMSR} */
729static DECLCALLBACK(int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
730{
731 uint64_t uValue = pRange->uValue;
732
733 /* Always provide the max bus ratio for now. XNU expects it. */
734 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
735
736 PVM pVM = pVCpu->CTX_SUFF(pVM);
737 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
738 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
739 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
740 if (uTscRatio > 0x1f)
741 uTscRatio = 0x1f;
742 uValue |= (uint64_t)uTscRatio << 40;
743
744 *puValue = uValue;
745 return VINF_SUCCESS;
746}
747
748
749/** @callback_method_impl{FNCPUMWRMSR} */
750static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
751{
752 /* Pentium4 allows writing, but all bits are ignored. */
753 return VINF_SUCCESS;
754}
755
756
757/** @callback_method_impl{FNCPUMRDMSR} */
758static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
759{
760 /** @todo implement IA32_PERFCTL. */
761 *puValue = 0;
762 return VINF_SUCCESS;
763}
764
765
766/** @callback_method_impl{FNCPUMWRMSR} */
767static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
768{
769 /** @todo implement IA32_PERFCTL. */
770 return VINF_SUCCESS;
771}
772
773
774/** @callback_method_impl{FNCPUMRDMSR} */
775static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
776{
777 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
778 *puValue = 0;
779 return VINF_SUCCESS;
780}
781
782
783/** @callback_method_impl{FNCPUMWRMSR} */
784static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
785{
786 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
787 return VINF_SUCCESS;
788}
789
790
791/** @callback_method_impl{FNCPUMRDMSR} */
792static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
793{
794 /** @todo implement performance counters. */
795 *puValue = 0;
796 return VINF_SUCCESS;
797}
798
799
800/** @callback_method_impl{FNCPUMWRMSR} */
801static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
802{
803 /** @todo implement performance counters. */
804 return VINF_SUCCESS;
805}
806
807
808/** @callback_method_impl{FNCPUMRDMSR} */
809static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
810{
811 /** @todo implement performance counters. */
812 *puValue = 0;
813 return VINF_SUCCESS;
814}
815
816
817/** @callback_method_impl{FNCPUMWRMSR} */
818static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
819{
820 /** @todo implement performance counters. */
821 return VINF_SUCCESS;
822}
823
824
825/** @callback_method_impl{FNCPUMRDMSR} */
826static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
827{
828 /** @todo implement performance counters. */
829 *puValue = 0;
830 return VINF_SUCCESS;
831}
832
833
834/** @callback_method_impl{FNCPUMWRMSR} */
835static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
836{
837 /** @todo implement performance counters. */
838 return VINF_SUCCESS;
839}
840
841
842/** @callback_method_impl{FNCPUMRDMSR} */
843static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
844{
845 /** @todo implement performance counters. */
846 *puValue = 0;
847 return VINF_SUCCESS;
848}
849
850
851/** @callback_method_impl{FNCPUMWRMSR} */
852static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
853{
854 /** @todo implement performance counters. */
855 return VINF_SUCCESS;
856}
857
858
859/** @callback_method_impl{FNCPUMRDMSR} */
860static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
861{
862 /** @todo implement performance counters. */
863 *puValue = 0;
864 return VINF_SUCCESS;
865}
866
867
868/** @callback_method_impl{FNCPUMWRMSR} */
869static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
870{
871 /** @todo implement performance counters. */
872 return VINF_SUCCESS;
873}
874
875
876/** @callback_method_impl{FNCPUMRDMSR} */
877static DECLCALLBACK(int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
878{
879 /** @todo implement performance counters. */
880 *puValue = 0;
881 return VINF_SUCCESS;
882}
883
884
885/** @callback_method_impl{FNCPUMWRMSR} */
886static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
887{
888 /** @todo implement performance counters. */
889 return VINF_SUCCESS;
890}
891
892
893/** @callback_method_impl{FNCPUMRDMSR} */
894static DECLCALLBACK(int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
895{
896 /** @todo implement IA32_CLOCK_MODULATION. */
897 *puValue = 0;
898 return VINF_SUCCESS;
899}
900
901
902/** @callback_method_impl{FNCPUMWRMSR} */
903static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
904{
905 /** @todo implement IA32_CLOCK_MODULATION. */
906 return VINF_SUCCESS;
907}
908
909
910/** @callback_method_impl{FNCPUMRDMSR} */
911static DECLCALLBACK(int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
912{
913 /** @todo implement IA32_THERM_INTERRUPT. */
914 *puValue = 0;
915 return VINF_SUCCESS;
916}
917
918
919/** @callback_method_impl{FNCPUMWRMSR} */
920static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
921{
922 /** @todo implement IA32_THERM_STATUS. */
923 return VINF_SUCCESS;
924}
925
926
927/** @callback_method_impl{FNCPUMRDMSR} */
928static DECLCALLBACK(int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
929{
930 /** @todo implement IA32_THERM_STATUS. */
931 *puValue = 0;
932 return VINF_SUCCESS;
933}
934
935
936/** @callback_method_impl{FNCPUMWRMSR} */
937static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
938{
939 /** @todo implement IA32_THERM_INTERRUPT. */
940 return VINF_SUCCESS;
941}
942
943
944/** @callback_method_impl{FNCPUMRDMSR} */
945static DECLCALLBACK(int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
946{
947 /** @todo implement IA32_THERM2_CTL. */
948 *puValue = 0;
949 return VINF_SUCCESS;
950}
951
952
953/** @callback_method_impl{FNCPUMWRMSR} */
954static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
955{
956 /** @todo implement IA32_THERM2_CTL. */
957 return VINF_SUCCESS;
958}
959
960
961/** @callback_method_impl{FNCPUMRDMSR} */
962static DECLCALLBACK(int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
963{
964 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
965 return VINF_SUCCESS;
966}
967
968
969/** @callback_method_impl{FNCPUMWRMSR} */
970static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
971{
972#ifdef LOG_ENABLED
973 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
974#endif
975
976 /* Unsupported bits are generally ignored and stripped by the MSR range
977 entry that got us here. So, we just need to preserve fixed bits. */
978 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
979 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
980 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
981
982 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
983 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
984
985 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
986 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
987 return VINF_SUCCESS;
988}
989
990
991/** @callback_method_impl{FNCPUMRDMSR} */
992static DECLCALLBACK(int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
993{
994 /** @todo Implement machine check exception injection. */
995 switch (idMsr & 3)
996 {
997 case 0:
998 case 1:
999 *puValue = 0;
1000 break;
1001
1002 /* The ADDR and MISC registers aren't accessible since the
1003 corresponding STATUS bits are zero. */
1004 case 2:
1005 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1006 return VERR_CPUM_RAISE_GP_0;
1007 case 3:
1008 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1009 return VERR_CPUM_RAISE_GP_0;
1010 }
1011 return VINF_SUCCESS;
1012}
1013
1014
1015/** @callback_method_impl{FNCPUMWRMSR} */
1016static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1017{
1018 switch (idMsr & 3)
1019 {
1020 case 0:
1021 /* Ignore writes to the CTL register. */
1022 break;
1023
1024 case 1:
1025 /* According to specs, the STATUS register can only be written to
1026 with the value 0. VBoxCpuReport thinks different for a
1027 Pentium M Dothan, but implementing according to specs now. */
1028 if (uValue != 0)
1029 {
1030 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1031 return VERR_CPUM_RAISE_GP_0;
1032 }
1033 break;
1034
1035 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1036 Writing 1s will GP. Need to figure out how this relates to the
1037 ADDRV and MISCV status flags. If writing is independent of those
1038 bits, we need to know whether the CPU really implements them since
1039 that is exposed by writing 0 to them.
1040 Implementing the solution with the fewer GPs for now. */
1041 case 2:
1042 if (uValue != 0)
1043 {
1044 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1045 return VERR_CPUM_RAISE_GP_0;
1046 }
1047 break;
1048 case 3:
1049 if (uValue != 0)
1050 {
1051 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1052 return VERR_CPUM_RAISE_GP_0;
1053 }
1054 break;
1055 }
1056 return VINF_SUCCESS;
1057}
1058
1059
1060/** @callback_method_impl{FNCPUMRDMSR} */
1061static DECLCALLBACK(int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1062{
1063 /** @todo Implement machine check exception injection. */
1064 *puValue = 0;
1065 return VINF_SUCCESS;
1066}
1067
1068
1069/** @callback_method_impl{FNCPUMWRMSR} */
1070static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1071{
1072 /** @todo Implement machine check exception injection. */
1073 return VINF_SUCCESS;
1074}
1075
1076
1077/** @callback_method_impl{FNCPUMRDMSR} */
1078static DECLCALLBACK(int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1079{
1080 /** @todo implement IA32_DS_AREA. */
1081 *puValue = 0;
1082 return VINF_SUCCESS;
1083}
1084
1085
1086/** @callback_method_impl{FNCPUMWRMSR} */
1087static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1088{
1089 return VINF_SUCCESS;
1090}
1091
1092
1093/** @callback_method_impl{FNCPUMRDMSR} */
1094static DECLCALLBACK(int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1095{
1096 /** @todo implement TSC deadline timer. */
1097 *puValue = 0;
1098 return VINF_SUCCESS;
1099}
1100
1101
1102/** @callback_method_impl{FNCPUMWRMSR} */
1103static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1104{
1105 /** @todo implement TSC deadline timer. */
1106 return VINF_SUCCESS;
1107}
1108
1109
1110/** @callback_method_impl{FNCPUMRDMSR} */
1111static DECLCALLBACK(int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1112{
1113 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1114 if (rc != VINF_SUCCESS)
1115 {
1116 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1117 return VERR_CPUM_RAISE_GP_0;
1118 }
1119 return VINF_SUCCESS;
1120}
1121
1122
1123/** @callback_method_impl{FNCPUMWRMSR} */
1124static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1125{
1126 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1127 if (rc != VINF_SUCCESS)
1128 {
1129 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1130 return VERR_CPUM_RAISE_GP_0;
1131 }
1132 return VINF_SUCCESS;
1133}
1134
1135
1136/** @callback_method_impl{FNCPUMRDMSR} */
1137static DECLCALLBACK(int) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1138{
1139 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1140 *puValue = 0;
1141 return VINF_SUCCESS;
1142}
1143
1144
1145/** @callback_method_impl{FNCPUMWRMSR} */
1146static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1147{
1148 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1149 return VINF_SUCCESS;
1150}
1151
1152
1153/** @callback_method_impl{FNCPUMRDMSR} */
1154static DECLCALLBACK(int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1155{
1156 *puValue = 0;
1157 return VINF_SUCCESS;
1158}
1159
1160
1161/** @callback_method_impl{FNCPUMRDMSR} */
1162static DECLCALLBACK(int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1163{
1164 *puValue = 0;
1165 return VINF_SUCCESS;
1166}
1167
1168
1169/** @callback_method_impl{FNCPUMRDMSR} */
1170static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1171{
1172 *puValue = 0;
1173 return VINF_SUCCESS;
1174}
1175
1176
1177/** @callback_method_impl{FNCPUMRDMSR} */
1178static DECLCALLBACK(int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1179{
1180 *puValue = 0;
1181 return VINF_SUCCESS;
1182}
1183
1184
1185/** @callback_method_impl{FNCPUMRDMSR} */
1186static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1187{
1188 *puValue = 0;
1189 return VINF_SUCCESS;
1190}
1191
1192
1193/** @callback_method_impl{FNCPUMRDMSR} */
1194static DECLCALLBACK(int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1195{
1196 *puValue = 0;
1197 return VINF_SUCCESS;
1198}
1199
1200
1201/** @callback_method_impl{FNCPUMRDMSR} */
1202static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1203{
1204 *puValue = 0;
1205 return VINF_SUCCESS;
1206}
1207
1208
1209/** @callback_method_impl{FNCPUMRDMSR} */
1210static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1211{
1212 *puValue = 0;
1213 return VINF_SUCCESS;
1214}
1215
1216
1217/** @callback_method_impl{FNCPUMRDMSR} */
1218static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1219{
1220 *puValue = 0;
1221 return VINF_SUCCESS;
1222}
1223
1224
1225/** @callback_method_impl{FNCPUMRDMSR} */
1226static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1227{
1228 *puValue = 0;
1229 return VINF_SUCCESS;
1230}
1231
1232
1233/** @callback_method_impl{FNCPUMRDMSR} */
1234static DECLCALLBACK(int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1235{
1236 *puValue = 0;
1237 return VINF_SUCCESS;
1238}
1239
1240
1241/** @callback_method_impl{FNCPUMRDMSR} */
1242static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1243{
1244 *puValue = 0;
1245 return VINF_SUCCESS;
1246}
1247
1248
1249/** @callback_method_impl{FNCPUMRDMSR} */
1250static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1251{
1252 *puValue = 0;
1253 return VINF_SUCCESS;
1254}
1255
1256
1257/** @callback_method_impl{FNCPUMRDMSR} */
1258static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1259{
1260 *puValue = 0;
1261 return VINF_SUCCESS;
1262}
1263
1264
1265/** @callback_method_impl{FNCPUMRDMSR} */
1266static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1267{
1268 *puValue = 0;
1269 return VINF_SUCCESS;
1270}
1271
1272
1273/** @callback_method_impl{FNCPUMRDMSR} */
1274static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1275{
1276 *puValue = 0;
1277 return VINF_SUCCESS;
1278}
1279
1280
1281/** @callback_method_impl{FNCPUMRDMSR} */
1282static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1283{
1284 *puValue = 0;
1285 return VINF_SUCCESS;
1286}
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297/*
1298 * AMD64
1299 * AMD64
1300 * AMD64
1301 */
1302
1303
1304/** @callback_method_impl{FNCPUMRDMSR} */
1305static DECLCALLBACK(int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1306{
1307 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1308 return VINF_SUCCESS;
1309}
1310
1311
1312/** @callback_method_impl{FNCPUMWRMSR} */
1313static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1314{
1315 PVM pVM = pVCpu->CTX_SUFF(pVM);
1316 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1317 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1318 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1319 : 0;
1320 uint64_t fMask = 0;
1321
1322 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1323 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1324 fMask |= MSR_K6_EFER_NXE;
1325 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1326 fMask |= MSR_K6_EFER_LME;
1327 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1328 fMask |= MSR_K6_EFER_SCE;
1329 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1330 fMask |= MSR_K6_EFER_FFXSR;
1331
1332 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1333 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1334 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1335 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1336 {
1337 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1338 return VERR_CPUM_RAISE_GP_0;
1339 }
1340
1341 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1342 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1343 ("Unexpected value %RX64\n", uValue));
1344 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1345
1346 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1347 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1348 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1349 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1350 {
1351 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1352 HMFlushTLB(pVCpu);
1353
1354 /* Notify PGM about NXE changes. */
1355 if ( (uOldEfer & MSR_K6_EFER_NXE)
1356 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1357 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1358 }
1359 return VINF_SUCCESS;
1360}
1361
1362
1363/** @callback_method_impl{FNCPUMRDMSR} */
1364static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1365{
1366 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1367 return VINF_SUCCESS;
1368}
1369
1370
1371/** @callback_method_impl{FNCPUMWRMSR} */
1372static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1373{
1374 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1375 return VINF_SUCCESS;
1376}
1377
1378
1379/** @callback_method_impl{FNCPUMRDMSR} */
1380static DECLCALLBACK(int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1381{
1382 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1383 return VINF_SUCCESS;
1384}
1385
1386
1387/** @callback_method_impl{FNCPUMWRMSR} */
1388static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1389{
1390 if (!X86_IS_CANONICAL(uValue))
1391 {
1392 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1393 return VERR_CPUM_RAISE_GP_0;
1394 }
1395 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1396 return VINF_SUCCESS;
1397}
1398
1399
1400/** @callback_method_impl{FNCPUMRDMSR} */
1401static DECLCALLBACK(int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1402{
1403 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1404 return VINF_SUCCESS;
1405}
1406
1407
1408/** @callback_method_impl{FNCPUMWRMSR} */
1409static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1410{
1411 if (!X86_IS_CANONICAL(uValue))
1412 {
1413 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1414 return VERR_CPUM_RAISE_GP_0;
1415 }
1416 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1417 return VINF_SUCCESS;
1418}
1419
1420
1421/** @callback_method_impl{FNCPUMRDMSR} */
1422static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1423{
1424 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1425 return VINF_SUCCESS;
1426}
1427
1428
1429/** @callback_method_impl{FNCPUMWRMSR} */
1430static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1431{
1432 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1433 return VINF_SUCCESS;
1434}
1435
1436
1437/** @callback_method_impl{FNCPUMRDMSR} */
1438static DECLCALLBACK(int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1439{
1440 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1441 return VINF_SUCCESS;
1442}
1443
1444
1445/** @callback_method_impl{FNCPUMWRMSR} */
1446static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1447{
1448 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1449 return VINF_SUCCESS;
1450}
1451
1452
1453/** @callback_method_impl{FNCPUMRDMSR} */
1454static DECLCALLBACK(int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1455{
1456 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1457 return VINF_SUCCESS;
1458}
1459
1460/** @callback_method_impl{FNCPUMWRMSR} */
1461static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1462{
1463 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1464 return VINF_SUCCESS;
1465}
1466
1467
1468
1469/** @callback_method_impl{FNCPUMRDMSR} */
1470static DECLCALLBACK(int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1471{
1472 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1473 return VINF_SUCCESS;
1474}
1475
1476/** @callback_method_impl{FNCPUMWRMSR} */
1477static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1478{
1479 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1480 return VINF_SUCCESS;
1481}
1482
1483
1484/** @callback_method_impl{FNCPUMRDMSR} */
1485static DECLCALLBACK(int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1486{
1487 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1488 return VINF_SUCCESS;
1489}
1490
1491/** @callback_method_impl{FNCPUMWRMSR} */
1492static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1493{
1494 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1495 return VINF_SUCCESS;
1496}
1497
1498
1499/*
1500 * Intel specific
1501 * Intel specific
1502 * Intel specific
1503 */
1504
1505/** @callback_method_impl{FNCPUMRDMSR} */
1506static DECLCALLBACK(int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1507{
1508 /** @todo recalc clock frequency ratio? */
1509 *puValue = pRange->uValue;
1510 return VINF_SUCCESS;
1511}
1512
1513
1514/** @callback_method_impl{FNCPUMWRMSR} */
1515static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1516{
1517 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1518 return VINF_SUCCESS;
1519}
1520
1521
1522/** @callback_method_impl{FNCPUMRDMSR} */
1523static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1524{
1525 /** @todo P4 hard power on config */
1526 *puValue = pRange->uValue;
1527 return VINF_SUCCESS;
1528}
1529
1530
1531/** @callback_method_impl{FNCPUMWRMSR} */
1532static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1533{
1534 /** @todo P4 hard power on config */
1535 return VINF_SUCCESS;
1536}
1537
1538
1539/** @callback_method_impl{FNCPUMRDMSR} */
1540static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1541{
1542 /** @todo P4 soft power on config */
1543 *puValue = pRange->uValue;
1544 return VINF_SUCCESS;
1545}
1546
1547
1548/** @callback_method_impl{FNCPUMWRMSR} */
1549static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1550{
1551 /** @todo P4 soft power on config */
1552 return VINF_SUCCESS;
1553}
1554
1555
1556/** @callback_method_impl{FNCPUMRDMSR} */
1557static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1558{
1559 uint64_t uValue;
1560 PVM pVM = pVCpu->CTX_SUFF(pVM);
1561 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1562 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1563 {
1564 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1565 {
1566 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1567 uValue = 0;
1568 }
1569 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1570 {
1571 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1572 uValue = 1;
1573 }
1574 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1575 {
1576 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1577 uValue = 3;
1578 }
1579 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1580 {
1581 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1582 uValue = 2;
1583 }
1584 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1585 {
1586 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1587 uValue = 0;
1588 }
1589 else
1590 {
1591 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1592 uValue = 6;
1593 }
1594 uValue <<= 16;
1595
1596 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1597 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1598 uValue |= (uint32_t)uTscRatio << 24;
1599
1600 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1601 }
1602 else
1603 {
1604 /* Probably more stuff here, but intel doesn't want to tell us. */
1605 uValue = pRange->uValue;
1606 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1607 }
1608
1609 *puValue = uValue;
1610 return VINF_SUCCESS;
1611}
1612
1613
1614/** @callback_method_impl{FNCPUMWRMSR} */
1615static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1616{
1617 /** @todo P4 bus frequency config */
1618 return VINF_SUCCESS;
1619}
1620
1621
1622/** @callback_method_impl{FNCPUMRDMSR} */
1623static DECLCALLBACK(int) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1624{
1625 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1626 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1627 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1628 *puValue = 5;
1629 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1630 *puValue = 1;
1631 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1632 *puValue = 3;
1633 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1634 *puValue = 2;
1635 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1636 *puValue = 0;
1637 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1638 *puValue = 4;
1639 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1640 *puValue = 6;
1641
1642 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1643
1644 return VINF_SUCCESS;
1645}
1646
1647
1648/** @callback_method_impl{FNCPUMRDMSR} */
1649static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1650{
1651 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1652 PVM pVM = pVCpu->CTX_SUFF(pVM);
1653 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1654 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1655 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1656 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1657 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1658
1659 /* Ivy bridge has a minimum operating ratio as well. */
1660 if (true) /** @todo detect sandy bridge. */
1661 uValue |= (uint64_t)uTscRatio << 48;
1662
1663 *puValue = uValue;
1664 return VINF_SUCCESS;
1665}
1666
1667
1668/** @callback_method_impl{FNCPUMRDMSR} */
1669static DECLCALLBACK(int) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1670{
1671 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1672
1673 PVM pVM = pVCpu->CTX_SUFF(pVM);
1674 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1675 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1676 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1677 uValue |= (uint32_t)uTscRatio << 8;
1678
1679 *puValue = uValue;
1680 return VINF_SUCCESS;
1681}
1682
1683
1684/** @callback_method_impl{FNCPUMWRMSR} */
1685static DECLCALLBACK(int) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1686{
1687 /** @todo implement writing MSR_FLEX_RATIO. */
1688 return VINF_SUCCESS;
1689}
1690
1691
1692/** @callback_method_impl{FNCPUMRDMSR} */
1693static DECLCALLBACK(int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1694{
1695 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1696 return VINF_SUCCESS;
1697}
1698
1699
1700/** @callback_method_impl{FNCPUMWRMSR} */
1701static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1702{
1703 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1704 {
1705 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1706 return VERR_CPUM_RAISE_GP_0;
1707 }
1708#if 0 /** @todo check what real (old) hardware does. */
1709 if ((uValue & 7) >= 5)
1710 {
1711 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1712 return VERR_CPUM_RAISE_GP_0;
1713 }
1714#endif
1715 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1716 return VINF_SUCCESS;
1717}
1718
1719
1720/** @callback_method_impl{FNCPUMRDMSR} */
1721static DECLCALLBACK(int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1722{
1723 /** @todo implement I/O mwait wakeup. */
1724 *puValue = 0;
1725 return VINF_SUCCESS;
1726}
1727
1728
1729/** @callback_method_impl{FNCPUMWRMSR} */
1730static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1731{
1732 /** @todo implement I/O mwait wakeup. */
1733 return VINF_SUCCESS;
1734}
1735
1736
1737/** @callback_method_impl{FNCPUMRDMSR} */
1738static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1739{
1740 /** @todo implement last branch records. */
1741 *puValue = 0;
1742 return VINF_SUCCESS;
1743}
1744
1745
1746/** @callback_method_impl{FNCPUMWRMSR} */
1747static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1748{
1749 /** @todo implement last branch records. */
1750 return VINF_SUCCESS;
1751}
1752
1753
1754/** @callback_method_impl{FNCPUMRDMSR} */
1755static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1756{
1757 /** @todo implement last branch records. */
1758 *puValue = 0;
1759 return VINF_SUCCESS;
1760}
1761
1762
1763/** @callback_method_impl{FNCPUMWRMSR} */
1764static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1765{
1766 /** @todo implement last branch records. */
1767 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1768 * if the rest of the bits are zero. Automatic sign extending?
1769 * Investigate! */
1770 if (!X86_IS_CANONICAL(uValue))
1771 {
1772 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1773 return VERR_CPUM_RAISE_GP_0;
1774 }
1775 return VINF_SUCCESS;
1776}
1777
1778
1779/** @callback_method_impl{FNCPUMRDMSR} */
1780static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1781{
1782 /** @todo implement last branch records. */
1783 *puValue = 0;
1784 return VINF_SUCCESS;
1785}
1786
1787
1788/** @callback_method_impl{FNCPUMWRMSR} */
1789static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1790{
1791 /** @todo implement last branch records. */
1792 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1793 * if the rest of the bits are zero. Automatic sign extending?
1794 * Investigate! */
1795 if (!X86_IS_CANONICAL(uValue))
1796 {
1797 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1798 return VERR_CPUM_RAISE_GP_0;
1799 }
1800 return VINF_SUCCESS;
1801}
1802
1803
1804/** @callback_method_impl{FNCPUMRDMSR} */
1805static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1806{
1807 /** @todo implement last branch records. */
1808 *puValue = 0;
1809 return VINF_SUCCESS;
1810}
1811
1812
1813/** @callback_method_impl{FNCPUMWRMSR} */
1814static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1815{
1816 /** @todo implement last branch records. */
1817 return VINF_SUCCESS;
1818}
1819
1820
1821/** @callback_method_impl{FNCPUMRDMSR} */
1822static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1823{
1824 *puValue = pRange->uValue;
1825 return VINF_SUCCESS;
1826}
1827
1828
1829/** @callback_method_impl{FNCPUMWRMSR} */
1830static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1831{
1832 return VINF_SUCCESS;
1833}
1834
1835
1836/** @callback_method_impl{FNCPUMRDMSR} */
1837static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1838{
1839 *puValue = pRange->uValue;
1840 return VINF_SUCCESS;
1841}
1842
1843
1844/** @callback_method_impl{FNCPUMWRMSR} */
1845static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1846{
1847 return VINF_SUCCESS;
1848}
1849
1850
1851/** @callback_method_impl{FNCPUMRDMSR} */
1852static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1853{
1854 *puValue = pRange->uValue;
1855 return VINF_SUCCESS;
1856}
1857
1858
1859/** @callback_method_impl{FNCPUMWRMSR} */
1860static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1861{
1862 return VINF_SUCCESS;
1863}
1864
1865
1866/** @callback_method_impl{FNCPUMRDMSR} */
1867static DECLCALLBACK(int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1868{
1869 /** @todo machine check. */
1870 *puValue = pRange->uValue;
1871 return VINF_SUCCESS;
1872}
1873
1874
1875/** @callback_method_impl{FNCPUMWRMSR} */
1876static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1877{
1878 /** @todo machine check. */
1879 return VINF_SUCCESS;
1880}
1881
1882
1883/** @callback_method_impl{FNCPUMRDMSR} */
1884static DECLCALLBACK(int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1885{
1886 *puValue = 0;
1887 return VINF_SUCCESS;
1888}
1889
1890
1891/** @callback_method_impl{FNCPUMWRMSR} */
1892static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1893{
1894 return VINF_SUCCESS;
1895}
1896
1897
1898/** @callback_method_impl{FNCPUMRDMSR} */
1899static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1900{
1901 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1902 AssertRC(rc);
1903 return VINF_SUCCESS;
1904}
1905
1906
1907/** @callback_method_impl{FNCPUMWRMSR} */
1908static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1909{
1910 /* This CRx interface differs from the MOV CRx, GReg interface in that
1911 #GP(0) isn't raised if unsupported bits are written to. Instead they
1912 are simply ignored and masked off. (Pentium M Dothan) */
1913 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1914 * any, gain. */
1915 return VINF_SUCCESS;
1916}
1917
1918
1919/** @callback_method_impl{FNCPUMRDMSR} */
1920static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1921{
1922 /** @todo implement CPUID masking. */
1923 *puValue = UINT64_MAX;
1924 return VINF_SUCCESS;
1925}
1926
1927
1928/** @callback_method_impl{FNCPUMWRMSR} */
1929static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1930{
1931 /** @todo implement CPUID masking. */
1932 return VINF_SUCCESS;
1933}
1934
1935
1936/** @callback_method_impl{FNCPUMRDMSR} */
1937static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1938{
1939 /** @todo implement CPUID masking. */
1940 return VINF_SUCCESS;
1941}
1942
1943
1944/** @callback_method_impl{FNCPUMWRMSR} */
1945static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1946{
1947 /** @todo implement CPUID masking. */
1948 return VINF_SUCCESS;
1949}
1950
1951
1952
1953/** @callback_method_impl{FNCPUMRDMSR} */
1954static DECLCALLBACK(int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1955{
1956 /** @todo implement CPUID masking. */
1957 *puValue = UINT64_MAX;
1958 return VINF_SUCCESS;
1959}
1960
1961
1962/** @callback_method_impl{FNCPUMWRMSR} */
1963static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1964{
1965 /** @todo implement CPUID masking. */
1966 return VINF_SUCCESS;
1967}
1968
1969
1970
1971/** @callback_method_impl{FNCPUMRDMSR} */
1972static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1973{
1974 /** @todo implement AES-NI. */
1975 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
1976 return VINF_SUCCESS;
1977}
1978
1979
1980/** @callback_method_impl{FNCPUMWRMSR} */
1981static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1982{
1983 /** @todo implement AES-NI. */
1984 return VERR_CPUM_RAISE_GP_0;
1985}
1986
1987
1988/** @callback_method_impl{FNCPUMRDMSR} */
1989static DECLCALLBACK(int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1990{
1991 /** @todo implement intel C states. */
1992 *puValue = pRange->uValue;
1993 return VINF_SUCCESS;
1994}
1995
1996
1997/** @callback_method_impl{FNCPUMWRMSR} */
1998static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1999{
2000 /** @todo implement intel C states. */
2001 return VINF_SUCCESS;
2002}
2003
2004
2005/** @callback_method_impl{FNCPUMRDMSR} */
2006static DECLCALLBACK(int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2007{
2008 /** @todo implement last-branch-records. */
2009 *puValue = 0;
2010 return VINF_SUCCESS;
2011}
2012
2013
2014/** @callback_method_impl{FNCPUMWRMSR} */
2015static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2016{
2017 /** @todo implement last-branch-records. */
2018 return VINF_SUCCESS;
2019}
2020
2021
2022/** @callback_method_impl{FNCPUMRDMSR} */
2023static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2024{
2025 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2026 *puValue = 0;
2027 return VINF_SUCCESS;
2028}
2029
2030
2031/** @callback_method_impl{FNCPUMWRMSR} */
2032static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2033{
2034 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2035 return VINF_SUCCESS;
2036}
2037
2038
2039/** @callback_method_impl{FNCPUMRDMSR} */
2040static DECLCALLBACK(int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2041{
2042 /** @todo implement memory VLW? */
2043 *puValue = pRange->uValue;
2044 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2045 AAJ49/AAK51/????, which documents the inversion of this bit. The
2046 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2047 that correct things. Some guesses at the other bits:
2048 bit 2 = INTR
2049 bit 4 = SMI
2050 bit 5 = INIT
2051 bit 6 = NMI */
2052 return VINF_SUCCESS;
2053}
2054
2055
2056/** @callback_method_impl{FNCPUMRDMSR} */
2057static DECLCALLBACK(int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2058{
2059 /** @todo intel power management */
2060 *puValue = 0;
2061 return VINF_SUCCESS;
2062}
2063
2064
2065/** @callback_method_impl{FNCPUMWRMSR} */
2066static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2067{
2068 /** @todo intel power management */
2069 return VINF_SUCCESS;
2070}
2071
2072
2073/** @callback_method_impl{FNCPUMRDMSR} */
2074static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2075{
2076 /** @todo intel performance counters. */
2077 *puValue = 0;
2078 return VINF_SUCCESS;
2079}
2080
2081
2082/** @callback_method_impl{FNCPUMWRMSR} */
2083static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2084{
2085 /** @todo intel performance counters. */
2086 return VINF_SUCCESS;
2087}
2088
2089
2090/** @callback_method_impl{FNCPUMRDMSR} */
2091static DECLCALLBACK(int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2092{
2093 /** @todo intel performance counters. */
2094 *puValue = 0;
2095 return VINF_SUCCESS;
2096}
2097
2098
2099/** @callback_method_impl{FNCPUMWRMSR} */
2100static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2101{
2102 /** @todo intel performance counters. */
2103 return VINF_SUCCESS;
2104}
2105
2106
2107/** @callback_method_impl{FNCPUMRDMSR} */
2108static DECLCALLBACK(int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2109{
2110 /** @todo intel power management. */
2111 *puValue = 0;
2112 return VINF_SUCCESS;
2113}
2114
2115
2116/** @callback_method_impl{FNCPUMRDMSR} */
2117static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2118{
2119 /** @todo intel power management. */
2120 *puValue = 0;
2121 return VINF_SUCCESS;
2122}
2123
2124
2125/** @callback_method_impl{FNCPUMRDMSR} */
2126static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2127{
2128 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2129 *puValue = 0;
2130 return VINF_SUCCESS;
2131}
2132
2133
2134/** @callback_method_impl{FNCPUMWRMSR} */
2135static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2136{
2137 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2138 return VINF_SUCCESS;
2139}
2140
2141
2142/** @callback_method_impl{FNCPUMRDMSR} */
2143static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2144{
2145 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2146 *puValue = 0;
2147 return VINF_SUCCESS;
2148}
2149
2150
2151/** @callback_method_impl{FNCPUMWRMSR} */
2152static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2153{
2154 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2155 return VINF_SUCCESS;
2156}
2157
2158
2159/** @callback_method_impl{FNCPUMRDMSR} */
2160static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2161{
2162 /** @todo intel RAPL. */
2163 *puValue = pRange->uValue;
2164 return VINF_SUCCESS;
2165}
2166
2167
2168/** @callback_method_impl{FNCPUMRDMSR} */
2169static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2170{
2171 /** @todo intel power management. */
2172 *puValue = 0;
2173 return VINF_SUCCESS;
2174}
2175
2176
2177/** @callback_method_impl{FNCPUMWRMSR} */
2178static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2179{
2180 /** @todo intel power management. */
2181 return VINF_SUCCESS;
2182}
2183
2184
2185/** @callback_method_impl{FNCPUMRDMSR} */
2186static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2187{
2188 /** @todo intel power management. */
2189 *puValue = 0;
2190 return VINF_SUCCESS;
2191}
2192
2193
2194/** @callback_method_impl{FNCPUMRDMSR} */
2195static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2196{
2197 /** @todo intel RAPL. */
2198 *puValue = 0;
2199 return VINF_SUCCESS;
2200}
2201
2202
2203/** @callback_method_impl{FNCPUMWRMSR} */
2204static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2205{
2206 /** @todo intel RAPL. */
2207 return VINF_SUCCESS;
2208}
2209
2210
2211/** @callback_method_impl{FNCPUMRDMSR} */
2212static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2213{
2214 /** @todo intel power management. */
2215 *puValue = 0;
2216 return VINF_SUCCESS;
2217}
2218
2219
2220/** @callback_method_impl{FNCPUMRDMSR} */
2221static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2222{
2223 /** @todo intel power management. */
2224 *puValue = 0;
2225 return VINF_SUCCESS;
2226}
2227
2228
2229/** @callback_method_impl{FNCPUMRDMSR} */
2230static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2231{
2232 /** @todo intel power management. */
2233 *puValue = 0;
2234 return VINF_SUCCESS;
2235}
2236
2237
2238/** @callback_method_impl{FNCPUMRDMSR} */
2239static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2240{
2241 /** @todo intel RAPL. */
2242 *puValue = 0;
2243 return VINF_SUCCESS;
2244}
2245
2246
2247/** @callback_method_impl{FNCPUMWRMSR} */
2248static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2249{
2250 /** @todo intel RAPL. */
2251 return VINF_SUCCESS;
2252}
2253
2254
2255/** @callback_method_impl{FNCPUMRDMSR} */
2256static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2257{
2258 /** @todo intel power management. */
2259 *puValue = 0;
2260 return VINF_SUCCESS;
2261}
2262
2263
2264/** @callback_method_impl{FNCPUMRDMSR} */
2265static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2266{
2267 /** @todo intel power management. */
2268 *puValue = 0;
2269 return VINF_SUCCESS;
2270}
2271
2272
2273/** @callback_method_impl{FNCPUMRDMSR} */
2274static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2275{
2276 /** @todo intel power management. */
2277 *puValue = 0;
2278 return VINF_SUCCESS;
2279}
2280
2281
2282/** @callback_method_impl{FNCPUMRDMSR} */
2283static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2284{
2285 /** @todo intel RAPL. */
2286 *puValue = 0;
2287 return VINF_SUCCESS;
2288}
2289
2290
2291/** @callback_method_impl{FNCPUMWRMSR} */
2292static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2293{
2294 /** @todo intel RAPL. */
2295 return VINF_SUCCESS;
2296}
2297
2298
2299/** @callback_method_impl{FNCPUMRDMSR} */
2300static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2301{
2302 /** @todo intel power management. */
2303 *puValue = 0;
2304 return VINF_SUCCESS;
2305}
2306
2307
2308/** @callback_method_impl{FNCPUMRDMSR} */
2309static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2310{
2311 /** @todo intel RAPL. */
2312 *puValue = 0;
2313 return VINF_SUCCESS;
2314}
2315
2316
2317/** @callback_method_impl{FNCPUMWRMSR} */
2318static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2319{
2320 /** @todo intel RAPL. */
2321 return VINF_SUCCESS;
2322}
2323
2324
2325/** @callback_method_impl{FNCPUMRDMSR} */
2326static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2327{
2328 /** @todo intel power management. */
2329 *puValue = 0;
2330 return VINF_SUCCESS;
2331}
2332
2333
2334/** @callback_method_impl{FNCPUMRDMSR} */
2335static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2336{
2337 /** @todo intel RAPL. */
2338 *puValue = 0;
2339 return VINF_SUCCESS;
2340}
2341
2342
2343/** @callback_method_impl{FNCPUMWRMSR} */
2344static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2345{
2346 /** @todo intel RAPL. */
2347 return VINF_SUCCESS;
2348}
2349
2350
2351/** @callback_method_impl{FNCPUMRDMSR} */
2352static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2353{
2354 /** @todo intel power management. */
2355 *puValue = 0;
2356 return VINF_SUCCESS;
2357}
2358
2359
2360/** @callback_method_impl{FNCPUMRDMSR} */
2361static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2362{
2363 /** @todo intel RAPL. */
2364 *puValue = 0;
2365 return VINF_SUCCESS;
2366}
2367
2368
2369/** @callback_method_impl{FNCPUMWRMSR} */
2370static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2371{
2372 /** @todo intel RAPL. */
2373 return VINF_SUCCESS;
2374}
2375
2376
2377/** @callback_method_impl{FNCPUMRDMSR} */
2378static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2379{
2380 /** @todo intel power management. */
2381 *puValue = pRange->uValue;
2382 return VINF_SUCCESS;
2383}
2384
2385
2386/** @callback_method_impl{FNCPUMRDMSR} */
2387static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2388{
2389 /** @todo intel power management. */
2390 *puValue = pRange->uValue;
2391 return VINF_SUCCESS;
2392}
2393
2394
2395/** @callback_method_impl{FNCPUMRDMSR} */
2396static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2397{
2398 /** @todo intel power management. */
2399 *puValue = pRange->uValue;
2400 return VINF_SUCCESS;
2401}
2402
2403
2404/** @callback_method_impl{FNCPUMRDMSR} */
2405static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2406{
2407 /** @todo intel power management. */
2408 *puValue = 0;
2409 return VINF_SUCCESS;
2410}
2411
2412
2413/** @callback_method_impl{FNCPUMWRMSR} */
2414static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2415{
2416 /** @todo intel power management. */
2417 return VINF_SUCCESS;
2418}
2419
2420
2421/** @callback_method_impl{FNCPUMRDMSR} */
2422static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2423{
2424 /** @todo intel power management. */
2425 *puValue = 0;
2426 return VINF_SUCCESS;
2427}
2428
2429
2430/** @callback_method_impl{FNCPUMWRMSR} */
2431static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2432{
2433 /** @todo intel power management. */
2434 return VINF_SUCCESS;
2435}
2436
2437
2438/** @callback_method_impl{FNCPUMRDMSR} */
2439static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2440{
2441 /** @todo uncore msrs. */
2442 *puValue = 0;
2443 return VINF_SUCCESS;
2444}
2445
2446
2447/** @callback_method_impl{FNCPUMWRMSR} */
2448static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2449{
2450 /** @todo uncore msrs. */
2451 return VINF_SUCCESS;
2452}
2453
2454
2455/** @callback_method_impl{FNCPUMRDMSR} */
2456static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2457{
2458 /** @todo uncore msrs. */
2459 *puValue = 0;
2460 return VINF_SUCCESS;
2461}
2462
2463
2464/** @callback_method_impl{FNCPUMWRMSR} */
2465static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2466{
2467 /** @todo uncore msrs. */
2468 return VINF_SUCCESS;
2469}
2470
2471
2472/** @callback_method_impl{FNCPUMRDMSR} */
2473static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2474{
2475 /** @todo uncore msrs. */
2476 *puValue = 0;
2477 return VINF_SUCCESS;
2478}
2479
2480
2481/** @callback_method_impl{FNCPUMWRMSR} */
2482static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2483{
2484 /** @todo uncore msrs. */
2485 return VINF_SUCCESS;
2486}
2487
2488
2489/** @callback_method_impl{FNCPUMRDMSR} */
2490static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2491{
2492 /** @todo uncore msrs. */
2493 *puValue = 0;
2494 return VINF_SUCCESS;
2495}
2496
2497
2498/** @callback_method_impl{FNCPUMWRMSR} */
2499static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2500{
2501 /** @todo uncore msrs. */
2502 return VINF_SUCCESS;
2503}
2504
2505
2506/** @callback_method_impl{FNCPUMRDMSR} */
2507static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2508{
2509 /** @todo uncore msrs. */
2510 *puValue = 0;
2511 return VINF_SUCCESS;
2512}
2513
2514
2515/** @callback_method_impl{FNCPUMWRMSR} */
2516static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2517{
2518 /** @todo uncore msrs. */
2519 return VINF_SUCCESS;
2520}
2521
2522
2523/** @callback_method_impl{FNCPUMRDMSR} */
2524static DECLCALLBACK(int) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2525{
2526 /** @todo uncore msrs. */
2527 *puValue = 0;
2528 return VINF_SUCCESS;
2529}
2530
2531
2532/** @callback_method_impl{FNCPUMRDMSR} */
2533static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2534{
2535 /** @todo uncore msrs. */
2536 *puValue = 0;
2537 return VINF_SUCCESS;
2538}
2539
2540
2541/** @callback_method_impl{FNCPUMWRMSR} */
2542static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2543{
2544 /** @todo uncore msrs. */
2545 return VINF_SUCCESS;
2546}
2547
2548
2549/** @callback_method_impl{FNCPUMRDMSR} */
2550static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2551{
2552 /** @todo uncore msrs. */
2553 *puValue = 0;
2554 return VINF_SUCCESS;
2555}
2556
2557
2558/** @callback_method_impl{FNCPUMWRMSR} */
2559static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2560{
2561 /** @todo uncore msrs. */
2562 return VINF_SUCCESS;
2563}
2564
2565
2566/** @callback_method_impl{FNCPUMRDMSR} */
2567static DECLCALLBACK(int) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2568{
2569 /** @todo implement enhanced multi thread termal monitoring? */
2570 *puValue = pRange->uValue;
2571 return VINF_SUCCESS;
2572}
2573
2574
2575/** @callback_method_impl{FNCPUMWRMSR} */
2576static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2577{
2578 /** @todo implement enhanced multi thread termal monitoring? */
2579 return VINF_SUCCESS;
2580}
2581
2582
2583/** @callback_method_impl{FNCPUMRDMSR} */
2584static DECLCALLBACK(int) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2585{
2586 /** @todo SMM & C-states? */
2587 *puValue = 0;
2588 return VINF_SUCCESS;
2589}
2590
2591
2592/** @callback_method_impl{FNCPUMWRMSR} */
2593static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2594{
2595 /** @todo SMM & C-states? */
2596 return VINF_SUCCESS;
2597}
2598
2599
2600/** @callback_method_impl{FNCPUMRDMSR} */
2601static DECLCALLBACK(int) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2602{
2603 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2604 *puValue = 0;
2605 return VINF_SUCCESS;
2606}
2607
2608
2609/** @callback_method_impl{FNCPUMWRMSR} */
2610static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2611{
2612 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2613 return VINF_SUCCESS;
2614}
2615
2616
2617/** @callback_method_impl{FNCPUMRDMSR} */
2618static DECLCALLBACK(int) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2619{
2620 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2621 *puValue = 0;
2622 return VINF_SUCCESS;
2623}
2624
2625
2626/** @callback_method_impl{FNCPUMWRMSR} */
2627static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2628{
2629 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2630 return VINF_SUCCESS;
2631}
2632
2633
2634/** @callback_method_impl{FNCPUMRDMSR} */
2635static DECLCALLBACK(int) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2636{
2637 /** @todo Core2+ platform environment control interface control register? */
2638 *puValue = 0;
2639 return VINF_SUCCESS;
2640}
2641
2642
2643/** @callback_method_impl{FNCPUMWRMSR} */
2644static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2645{
2646 /** @todo Core2+ platform environment control interface control register? */
2647 return VINF_SUCCESS;
2648}
2649
2650
2651
2652/*
2653 * Multiple vendor P6 MSRs.
2654 * Multiple vendor P6 MSRs.
2655 * Multiple vendor P6 MSRs.
2656 *
2657 * These MSRs were introduced with the P6 but not elevated to architectural
2658 * MSRs, despite other vendors implementing them.
2659 */
2660
2661
2662/** @callback_method_impl{FNCPUMRDMSR} */
2663static DECLCALLBACK(int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2664{
2665 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2666 if I read the docs correctly, thus the need for separate functions. */
2667 /** @todo implement last branch records. */
2668 *puValue = 0;
2669 return VINF_SUCCESS;
2670}
2671
2672
2673/** @callback_method_impl{FNCPUMRDMSR} */
2674static DECLCALLBACK(int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2675{
2676 /** @todo implement last branch records. */
2677 *puValue = 0;
2678 return VINF_SUCCESS;
2679}
2680
2681
2682/** @callback_method_impl{FNCPUMRDMSR} */
2683static DECLCALLBACK(int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2684{
2685 /** @todo implement last exception records. */
2686 *puValue = 0;
2687 return VINF_SUCCESS;
2688}
2689
2690
2691/** @callback_method_impl{FNCPUMWRMSR} */
2692static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2693{
2694 /** @todo implement last exception records. */
2695 return VINF_SUCCESS;
2696}
2697
2698
2699/** @callback_method_impl{FNCPUMRDMSR} */
2700static DECLCALLBACK(int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2701{
2702 /** @todo implement last exception records. */
2703 *puValue = 0;
2704 return VINF_SUCCESS;
2705}
2706
2707
2708/** @callback_method_impl{FNCPUMWRMSR} */
2709static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2710{
2711 /** @todo implement last exception records. */
2712 return VINF_SUCCESS;
2713}
2714
2715
2716
2717/*
2718 * AMD specific
2719 * AMD specific
2720 * AMD specific
2721 */
2722
2723
2724/** @callback_method_impl{FNCPUMRDMSR} */
2725static DECLCALLBACK(int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2726{
2727 /** @todo Implement TscRateMsr */
2728 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2729 return VINF_SUCCESS;
2730}
2731
2732
2733/** @callback_method_impl{FNCPUMWRMSR} */
2734static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2735{
2736 /** @todo Implement TscRateMsr */
2737 return VINF_SUCCESS;
2738}
2739
2740
2741/** @callback_method_impl{FNCPUMRDMSR} */
2742static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2743{
2744 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2745 /* Note: Only listes in BKDG for Family 15H. */
2746 *puValue = 0;
2747 return VINF_SUCCESS;
2748}
2749
2750
2751/** @callback_method_impl{FNCPUMWRMSR} */
2752static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2753{
2754 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2755 return VINF_SUCCESS;
2756}
2757
2758
2759/** @callback_method_impl{FNCPUMRDMSR} */
2760static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2761{
2762 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2763 /* Note: Only listes in BKDG for Family 15H. */
2764 *puValue = 0;
2765 return VINF_SUCCESS;
2766}
2767
2768
2769/** @callback_method_impl{FNCPUMWRMSR} */
2770static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2771{
2772 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2773 return VINF_SUCCESS;
2774}
2775
2776
2777/** @callback_method_impl{FNCPUMRDMSR} */
2778static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2779{
2780 /** @todo machine check. */
2781 *puValue = 0;
2782 return VINF_SUCCESS;
2783}
2784
2785
2786/** @callback_method_impl{FNCPUMWRMSR} */
2787static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2788{
2789 /** @todo machine check. */
2790 return VINF_SUCCESS;
2791}
2792
2793
2794/** @callback_method_impl{FNCPUMRDMSR} */
2795static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2796{
2797 /** @todo AMD performance events. */
2798 *puValue = 0;
2799 return VINF_SUCCESS;
2800}
2801
2802
2803/** @callback_method_impl{FNCPUMWRMSR} */
2804static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2805{
2806 /** @todo AMD performance events. */
2807 return VINF_SUCCESS;
2808}
2809
2810
2811/** @callback_method_impl{FNCPUMRDMSR} */
2812static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2813{
2814 /** @todo AMD performance events. */
2815 *puValue = 0;
2816 return VINF_SUCCESS;
2817}
2818
2819
2820/** @callback_method_impl{FNCPUMWRMSR} */
2821static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2822{
2823 /** @todo AMD performance events. */
2824 return VINF_SUCCESS;
2825}
2826
2827
2828/** @callback_method_impl{FNCPUMRDMSR} */
2829static DECLCALLBACK(int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2830{
2831 /** @todo AMD SYS_CFG */
2832 *puValue = pRange->uValue;
2833 return VINF_SUCCESS;
2834}
2835
2836
2837/** @callback_method_impl{FNCPUMWRMSR} */
2838static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2839{
2840 /** @todo AMD SYS_CFG */
2841 return VINF_SUCCESS;
2842}
2843
2844
2845/** @callback_method_impl{FNCPUMRDMSR} */
2846static DECLCALLBACK(int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2847{
2848 /** @todo AMD HW_CFG */
2849 *puValue = 0;
2850 return VINF_SUCCESS;
2851}
2852
2853
2854/** @callback_method_impl{FNCPUMWRMSR} */
2855static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2856{
2857 /** @todo AMD HW_CFG */
2858 return VINF_SUCCESS;
2859}
2860
2861
2862/** @callback_method_impl{FNCPUMRDMSR} */
2863static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2864{
2865 /** @todo AMD IorrMask/IorrBase */
2866 *puValue = 0;
2867 return VINF_SUCCESS;
2868}
2869
2870
2871/** @callback_method_impl{FNCPUMWRMSR} */
2872static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2873{
2874 /** @todo AMD IorrMask/IorrBase */
2875 return VINF_SUCCESS;
2876}
2877
2878
2879/** @callback_method_impl{FNCPUMRDMSR} */
2880static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2881{
2882 /** @todo AMD IorrMask/IorrBase */
2883 *puValue = 0;
2884 return VINF_SUCCESS;
2885}
2886
2887
2888/** @callback_method_impl{FNCPUMWRMSR} */
2889static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2890{
2891 /** @todo AMD IorrMask/IorrBase */
2892 return VINF_SUCCESS;
2893}
2894
2895
2896/** @callback_method_impl{FNCPUMRDMSR} */
2897static DECLCALLBACK(int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2898{
2899 *puValue = 0;
2900 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2901 * for TOPMEM2. */
2902 //if (pRange->uValue == 0)
2903 // *puValue = _4G - RamHoleSize;
2904 return VINF_SUCCESS;
2905}
2906
2907
2908/** @callback_method_impl{FNCPUMWRMSR} */
2909static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2910{
2911 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2912 return VINF_SUCCESS;
2913}
2914
2915
2916/** @callback_method_impl{FNCPUMRDMSR} */
2917static DECLCALLBACK(int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2918{
2919 /** @todo AMD NB_CFG1 */
2920 *puValue = 0;
2921 return VINF_SUCCESS;
2922}
2923
2924
2925/** @callback_method_impl{FNCPUMWRMSR} */
2926static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2927{
2928 /** @todo AMD NB_CFG1 */
2929 return VINF_SUCCESS;
2930}
2931
2932
2933/** @callback_method_impl{FNCPUMRDMSR} */
2934static DECLCALLBACK(int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2935{
2936 /** @todo machine check. */
2937 *puValue = 0;
2938 return VINF_SUCCESS;
2939}
2940
2941
2942/** @callback_method_impl{FNCPUMWRMSR} */
2943static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2944{
2945 /** @todo machine check. */
2946 return VINF_SUCCESS;
2947}
2948
2949
2950/** @callback_method_impl{FNCPUMRDMSR} */
2951static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2952{
2953 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0);
2954 if (pLeaf)
2955 {
2956 if (!(pRange->uValue & 1))
2957 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2958 else
2959 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2960 }
2961 else
2962 *puValue = 0;
2963 return VINF_SUCCESS;
2964}
2965
2966
2967/** @callback_method_impl{FNCPUMWRMSR} */
2968static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2969{
2970 /** @todo Remember guest programmed CPU name. */
2971 return VINF_SUCCESS;
2972}
2973
2974
2975/** @callback_method_impl{FNCPUMRDMSR} */
2976static DECLCALLBACK(int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2977{
2978 /** @todo AMD HTC. */
2979 *puValue = pRange->uValue;
2980 return VINF_SUCCESS;
2981}
2982
2983
2984/** @callback_method_impl{FNCPUMWRMSR} */
2985static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2986{
2987 /** @todo AMD HTC. */
2988 return VINF_SUCCESS;
2989}
2990
2991
2992/** @callback_method_impl{FNCPUMRDMSR} */
2993static DECLCALLBACK(int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2994{
2995 /** @todo AMD STC. */
2996 *puValue = 0;
2997 return VINF_SUCCESS;
2998}
2999
3000
3001/** @callback_method_impl{FNCPUMWRMSR} */
3002static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3003{
3004 /** @todo AMD STC. */
3005 return VINF_SUCCESS;
3006}
3007
3008
3009/** @callback_method_impl{FNCPUMRDMSR} */
3010static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3011{
3012 /** @todo AMD FIDVID_CTL. */
3013 *puValue = pRange->uValue;
3014 return VINF_SUCCESS;
3015}
3016
3017
3018/** @callback_method_impl{FNCPUMWRMSR} */
3019static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3020{
3021 /** @todo AMD FIDVID_CTL. */
3022 return VINF_SUCCESS;
3023}
3024
3025
3026/** @callback_method_impl{FNCPUMRDMSR} */
3027static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3028{
3029 /** @todo AMD FIDVID_STATUS. */
3030 *puValue = pRange->uValue;
3031 return VINF_SUCCESS;
3032}
3033
3034
3035/** @callback_method_impl{FNCPUMRDMSR} */
3036static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3037{
3038 /** @todo AMD MC. */
3039 *puValue = 0;
3040 return VINF_SUCCESS;
3041}
3042
3043
3044/** @callback_method_impl{FNCPUMWRMSR} */
3045static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3046{
3047 /** @todo AMD MC. */
3048 return VINF_SUCCESS;
3049}
3050
3051
3052/** @callback_method_impl{FNCPUMRDMSR} */
3053static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3054{
3055 /** @todo AMD SMM/SMI and I/O trap. */
3056 *puValue = 0;
3057 return VINF_SUCCESS;
3058}
3059
3060
3061/** @callback_method_impl{FNCPUMWRMSR} */
3062static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3063{
3064 /** @todo AMD SMM/SMI and I/O trap. */
3065 return VINF_SUCCESS;
3066}
3067
3068
3069/** @callback_method_impl{FNCPUMRDMSR} */
3070static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3071{
3072 /** @todo AMD SMM/SMI and I/O trap. */
3073 *puValue = 0;
3074 return VINF_SUCCESS;
3075}
3076
3077
3078/** @callback_method_impl{FNCPUMWRMSR} */
3079static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3080{
3081 /** @todo AMD SMM/SMI and I/O trap. */
3082 return VINF_SUCCESS;
3083}
3084
3085
3086/** @callback_method_impl{FNCPUMRDMSR} */
3087static DECLCALLBACK(int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3088{
3089 /** @todo Interrupt pending message. */
3090 *puValue = 0;
3091 return VINF_SUCCESS;
3092}
3093
3094
3095/** @callback_method_impl{FNCPUMWRMSR} */
3096static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3097{
3098 /** @todo Interrupt pending message. */
3099 return VINF_SUCCESS;
3100}
3101
3102
3103/** @callback_method_impl{FNCPUMRDMSR} */
3104static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3105{
3106 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3107 *puValue = 0;
3108 return VINF_SUCCESS;
3109}
3110
3111
3112/** @callback_method_impl{FNCPUMWRMSR} */
3113static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3114{
3115 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3116 return VINF_SUCCESS;
3117}
3118
3119
3120/** @callback_method_impl{FNCPUMRDMSR} */
3121static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3122{
3123 /** @todo AMD MMIO Configuration base address. */
3124 *puValue = 0;
3125 return VINF_SUCCESS;
3126}
3127
3128
3129/** @callback_method_impl{FNCPUMWRMSR} */
3130static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3131{
3132 /** @todo AMD MMIO Configuration base address. */
3133 return VINF_SUCCESS;
3134}
3135
3136
3137/** @callback_method_impl{FNCPUMRDMSR} */
3138static DECLCALLBACK(int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3139{
3140 /** @todo AMD 0xc0010059. */
3141 *puValue = 0;
3142 return VINF_SUCCESS;
3143}
3144
3145
3146/** @callback_method_impl{FNCPUMWRMSR} */
3147static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3148{
3149 /** @todo AMD 0xc0010059. */
3150 return VINF_SUCCESS;
3151}
3152
3153
3154/** @callback_method_impl{FNCPUMRDMSR} */
3155static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3156{
3157 /** @todo AMD P-states. */
3158 *puValue = pRange->uValue;
3159 return VINF_SUCCESS;
3160}
3161
3162
3163/** @callback_method_impl{FNCPUMRDMSR} */
3164static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3165{
3166 /** @todo AMD P-states. */
3167 *puValue = pRange->uValue;
3168 return VINF_SUCCESS;
3169}
3170
3171
3172/** @callback_method_impl{FNCPUMWRMSR} */
3173static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3174{
3175 /** @todo AMD P-states. */
3176 return VINF_SUCCESS;
3177}
3178
3179
3180/** @callback_method_impl{FNCPUMRDMSR} */
3181static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3182{
3183 /** @todo AMD P-states. */
3184 *puValue = pRange->uValue;
3185 return VINF_SUCCESS;
3186}
3187
3188
3189/** @callback_method_impl{FNCPUMWRMSR} */
3190static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3191{
3192 /** @todo AMD P-states. */
3193 return VINF_SUCCESS;
3194}
3195
3196
3197/** @callback_method_impl{FNCPUMRDMSR} */
3198static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3199{
3200 /** @todo AMD P-states. */
3201 *puValue = pRange->uValue;
3202 return VINF_SUCCESS;
3203}
3204
3205
3206/** @callback_method_impl{FNCPUMWRMSR} */
3207static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3208{
3209 /** @todo AMD P-states. */
3210 return VINF_SUCCESS;
3211}
3212
3213
3214/** @callback_method_impl{FNCPUMRDMSR} */
3215static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3216{
3217 /** @todo AMD P-states. */
3218 *puValue = pRange->uValue;
3219 return VINF_SUCCESS;
3220}
3221
3222
3223/** @callback_method_impl{FNCPUMWRMSR} */
3224static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3225{
3226 /** @todo AMD P-states. */
3227 return VINF_SUCCESS;
3228}
3229
3230
3231/** @callback_method_impl{FNCPUMRDMSR} */
3232static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3233{
3234 /** @todo AMD P-states. */
3235 *puValue = pRange->uValue;
3236 return VINF_SUCCESS;
3237}
3238
3239
3240/** @callback_method_impl{FNCPUMWRMSR} */
3241static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3242{
3243 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3244 /** @todo AMD P-states. */
3245 return VINF_SUCCESS;
3246}
3247
3248
3249/** @callback_method_impl{FNCPUMRDMSR} */
3250static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3251{
3252 /** @todo AMD C-states. */
3253 *puValue = 0;
3254 return VINF_SUCCESS;
3255}
3256
3257
3258/** @callback_method_impl{FNCPUMWRMSR} */
3259static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3260{
3261 /** @todo AMD C-states. */
3262 return VINF_SUCCESS;
3263}
3264
3265
3266/** @callback_method_impl{FNCPUMRDMSR} */
3267static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3268{
3269 /** @todo AMD machine checks. */
3270 *puValue = 0;
3271 return VINF_SUCCESS;
3272}
3273
3274
3275/** @callback_method_impl{FNCPUMWRMSR} */
3276static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3277{
3278 /** @todo AMD machine checks. */
3279 return VINF_SUCCESS;
3280}
3281
3282
3283/** @callback_method_impl{FNCPUMRDMSR} */
3284static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3285{
3286 /** @todo AMD SMM. */
3287 *puValue = 0;
3288 return VINF_SUCCESS;
3289}
3290
3291
3292/** @callback_method_impl{FNCPUMWRMSR} */
3293static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3294{
3295 /** @todo AMD SMM. */
3296 return VINF_SUCCESS;
3297}
3298
3299
3300/** @callback_method_impl{FNCPUMRDMSR} */
3301static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3302{
3303 /** @todo AMD SMM. */
3304 *puValue = 0;
3305 return VINF_SUCCESS;
3306}
3307
3308
3309/** @callback_method_impl{FNCPUMWRMSR} */
3310static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3311{
3312 /** @todo AMD SMM. */
3313 return VINF_SUCCESS;
3314}
3315
3316
3317
3318/** @callback_method_impl{FNCPUMRDMSR} */
3319static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3320{
3321 /** @todo AMD SMM. */
3322 *puValue = 0;
3323 return VINF_SUCCESS;
3324}
3325
3326
3327/** @callback_method_impl{FNCPUMWRMSR} */
3328static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3329{
3330 /** @todo AMD SMM. */
3331 return VINF_SUCCESS;
3332}
3333
3334
3335/** @callback_method_impl{FNCPUMRDMSR} */
3336static DECLCALLBACK(int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3337{
3338 /** @todo AMD SVM. */
3339 *puValue = 0;
3340 return VINF_SUCCESS;
3341}
3342
3343
3344/** @callback_method_impl{FNCPUMWRMSR} */
3345static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3346{
3347 /** @todo AMD SVM. */
3348 return VINF_SUCCESS;
3349}
3350
3351
3352/** @callback_method_impl{FNCPUMRDMSR} */
3353static DECLCALLBACK(int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3354{
3355 /** @todo AMD IGNNE\# control. */
3356 *puValue = 0;
3357 return VINF_SUCCESS;
3358}
3359
3360
3361/** @callback_method_impl{FNCPUMWRMSR} */
3362static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3363{
3364 /** @todo AMD IGNNE\# control. */
3365 return VINF_SUCCESS;
3366}
3367
3368
3369/** @callback_method_impl{FNCPUMRDMSR} */
3370static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3371{
3372 /** @todo AMD SMM. */
3373 *puValue = 0;
3374 return VINF_SUCCESS;
3375}
3376
3377
3378/** @callback_method_impl{FNCPUMWRMSR} */
3379static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3380{
3381 /** @todo AMD SMM. */
3382 return VINF_SUCCESS;
3383}
3384
3385
3386/** @callback_method_impl{FNCPUMRDMSR} */
3387static DECLCALLBACK(int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3388{
3389 /** @todo AMD SVM. */
3390 *puValue = 0;
3391 return VINF_SUCCESS;
3392}
3393
3394
3395/** @callback_method_impl{FNCPUMWRMSR} */
3396static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3397{
3398 /** @todo AMD SVM. */
3399 return VINF_SUCCESS;
3400}
3401
3402
3403/** @callback_method_impl{FNCPUMRDMSR} */
3404static DECLCALLBACK(int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3405{
3406 /** @todo AMD SVM. */
3407 *puValue = 0; /* RAZ */
3408 return VINF_SUCCESS;
3409}
3410
3411
3412/** @callback_method_impl{FNCPUMWRMSR} */
3413static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3414{
3415 /** @todo AMD SVM. */
3416 return VINF_SUCCESS;
3417}
3418
3419
3420/** @callback_method_impl{FNCPUMRDMSR} */
3421static DECLCALLBACK(int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3422{
3423 /** @todo AMD SMM. */
3424 *puValue = 0; /* RAZ */
3425 return VINF_SUCCESS;
3426}
3427
3428
3429/** @callback_method_impl{FNCPUMWRMSR} */
3430static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3431{
3432 /** @todo AMD SMM. */
3433 return VINF_SUCCESS;
3434}
3435
3436
3437/** @callback_method_impl{FNCPUMRDMSR} */
3438static DECLCALLBACK(int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3439{
3440 /** @todo AMD SMM/SMI. */
3441 *puValue = 0;
3442 return VINF_SUCCESS;
3443}
3444
3445
3446/** @callback_method_impl{FNCPUMWRMSR} */
3447static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3448{
3449 /** @todo AMD SMM/SMI. */
3450 return VINF_SUCCESS;
3451}
3452
3453
3454/** @callback_method_impl{FNCPUMRDMSR} */
3455static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3456{
3457 /** @todo AMD OS visible workaround. */
3458 *puValue = pRange->uValue;
3459 return VINF_SUCCESS;
3460}
3461
3462
3463/** @callback_method_impl{FNCPUMWRMSR} */
3464static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3465{
3466 /** @todo AMD OS visible workaround. */
3467 return VINF_SUCCESS;
3468}
3469
3470
3471/** @callback_method_impl{FNCPUMRDMSR} */
3472static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3473{
3474 /** @todo AMD OS visible workaround. */
3475 *puValue = 0;
3476 return VINF_SUCCESS;
3477}
3478
3479
3480/** @callback_method_impl{FNCPUMWRMSR} */
3481static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3482{
3483 /** @todo AMD OS visible workaround. */
3484 return VINF_SUCCESS;
3485}
3486
3487
3488/** @callback_method_impl{FNCPUMRDMSR} */
3489static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3490{
3491 /** @todo AMD L2I performance counters. */
3492 *puValue = 0;
3493 return VINF_SUCCESS;
3494}
3495
3496
3497/** @callback_method_impl{FNCPUMWRMSR} */
3498static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3499{
3500 /** @todo AMD L2I performance counters. */
3501 return VINF_SUCCESS;
3502}
3503
3504
3505/** @callback_method_impl{FNCPUMRDMSR} */
3506static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3507{
3508 /** @todo AMD L2I performance counters. */
3509 *puValue = 0;
3510 return VINF_SUCCESS;
3511}
3512
3513
3514/** @callback_method_impl{FNCPUMWRMSR} */
3515static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3516{
3517 /** @todo AMD L2I performance counters. */
3518 return VINF_SUCCESS;
3519}
3520
3521
3522/** @callback_method_impl{FNCPUMRDMSR} */
3523static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3524{
3525 /** @todo AMD Northbridge performance counters. */
3526 *puValue = 0;
3527 return VINF_SUCCESS;
3528}
3529
3530
3531/** @callback_method_impl{FNCPUMWRMSR} */
3532static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3533{
3534 /** @todo AMD Northbridge performance counters. */
3535 return VINF_SUCCESS;
3536}
3537
3538
3539/** @callback_method_impl{FNCPUMRDMSR} */
3540static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3541{
3542 /** @todo AMD Northbridge performance counters. */
3543 *puValue = 0;
3544 return VINF_SUCCESS;
3545}
3546
3547
3548/** @callback_method_impl{FNCPUMWRMSR} */
3549static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3550{
3551 /** @todo AMD Northbridge performance counters. */
3552 return VINF_SUCCESS;
3553}
3554
3555
3556/** @callback_method_impl{FNCPUMRDMSR} */
3557static DECLCALLBACK(int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3558{
3559 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3560 * cpus. Need to be explored and verify K7 presence. */
3561 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3562 *puValue = pRange->uValue;
3563 return VINF_SUCCESS;
3564}
3565
3566
3567/** @callback_method_impl{FNCPUMWRMSR} */
3568static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3569{
3570 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3571 * cpus. Need to be explored and verify K7 presence. */
3572 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3573 return VINF_SUCCESS;
3574}
3575
3576
3577/** @callback_method_impl{FNCPUMRDMSR} */
3578static DECLCALLBACK(int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3579{
3580 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3581 * cpus. Need to be explored and verify K7 presence. */
3582 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3583 * describing EBL_CR_POWERON. */
3584 *puValue = pRange->uValue;
3585 return VINF_SUCCESS;
3586}
3587
3588
3589/** @callback_method_impl{FNCPUMWRMSR} */
3590static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3591{
3592 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3593 * cpus. Need to be explored and verify K7 presence. */
3594 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3595 * describing EBL_CR_POWERON. */
3596 return VINF_SUCCESS;
3597}
3598
3599
3600/** @callback_method_impl{FNCPUMRDMSR} */
3601static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3602{
3603 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0);
3604 if (pLeaf)
3605 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3606 else
3607 *puValue = 0;
3608 return VINF_SUCCESS;
3609}
3610
3611
3612/** @callback_method_impl{FNCPUMWRMSR} */
3613static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3614{
3615 /** @todo Changing CPUID leaf 7/0. */
3616 return VINF_SUCCESS;
3617}
3618
3619
3620/** @callback_method_impl{FNCPUMRDMSR} */
3621static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3622{
3623 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0);
3624 if (pLeaf)
3625 *puValue = pLeaf->uEcx;
3626 else
3627 *puValue = 0;
3628 return VINF_SUCCESS;
3629}
3630
3631
3632/** @callback_method_impl{FNCPUMWRMSR} */
3633static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3634{
3635 /** @todo Changing CPUID leaf 6. */
3636 return VINF_SUCCESS;
3637}
3638
3639
3640/** @callback_method_impl{FNCPUMRDMSR} */
3641static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3642{
3643 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0);
3644 if (pLeaf)
3645 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3646 else
3647 *puValue = 0;
3648 return VINF_SUCCESS;
3649}
3650
3651
3652/** @callback_method_impl{FNCPUMWRMSR} */
3653static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3654{
3655 /** @todo Changing CPUID leaf 0x80000001. */
3656 return VINF_SUCCESS;
3657}
3658
3659
3660/** @callback_method_impl{FNCPUMRDMSR} */
3661static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3662{
3663 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0);
3664 if (pLeaf)
3665 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3666 else
3667 *puValue = 0;
3668 return VINF_SUCCESS;
3669}
3670
3671
3672/** @callback_method_impl{FNCPUMWRMSR} */
3673static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3674{
3675 /** @todo Changing CPUID leaf 0x80000001. */
3676 return VINF_SUCCESS;
3677}
3678
3679
3680/** @callback_method_impl{FNCPUMRDMSR} */
3681static DECLCALLBACK(int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3682{
3683 /** @todo Fake AMD microcode patching. */
3684 *puValue = pRange->uValue;
3685 return VINF_SUCCESS;
3686}
3687
3688
3689/** @callback_method_impl{FNCPUMWRMSR} */
3690static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3691{
3692 /** @todo Fake AMD microcode patching. */
3693 return VINF_SUCCESS;
3694}
3695
3696
3697/** @callback_method_impl{FNCPUMRDMSR} */
3698static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3699{
3700 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3701 * cpus. Need to be explored and verify K7 presence. */
3702 /** @todo undocumented */
3703 *puValue = 0;
3704 return VINF_SUCCESS;
3705}
3706
3707
3708/** @callback_method_impl{FNCPUMWRMSR} */
3709static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3710{
3711 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3712 * cpus. Need to be explored and verify K7 presence. */
3713 /** @todo undocumented */
3714 return VINF_SUCCESS;
3715}
3716
3717
3718/** @callback_method_impl{FNCPUMRDMSR} */
3719static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3720{
3721 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3722 * cpus. Need to be explored and verify K7 presence. */
3723 /** @todo undocumented */
3724 *puValue = 0;
3725 return VINF_SUCCESS;
3726}
3727
3728
3729/** @callback_method_impl{FNCPUMWRMSR} */
3730static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3731{
3732 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3733 * cpus. Need to be explored and verify K7 presence. */
3734 /** @todo undocumented */
3735 return VINF_SUCCESS;
3736}
3737
3738
3739/** @callback_method_impl{FNCPUMRDMSR} */
3740static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3741{
3742 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3743 * cpus. Need to be explored and verify K7 presence. */
3744 /** @todo undocumented */
3745 *puValue = 0;
3746 return VINF_SUCCESS;
3747}
3748
3749
3750/** @callback_method_impl{FNCPUMWRMSR} */
3751static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3752{
3753 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3754 * cpus. Need to be explored and verify K7 presence. */
3755 /** @todo undocumented */
3756 return VINF_SUCCESS;
3757}
3758
3759
3760/** @callback_method_impl{FNCPUMRDMSR} */
3761static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3762{
3763 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3764 * cpus. Need to be explored and verify K7 presence. */
3765 /** @todo undocumented */
3766 *puValue = 0;
3767 return VINF_SUCCESS;
3768}
3769
3770
3771/** @callback_method_impl{FNCPUMWRMSR} */
3772static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3773{
3774 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3775 * cpus. Need to be explored and verify K7 presence. */
3776 /** @todo undocumented */
3777 return VINF_SUCCESS;
3778}
3779
3780
3781/** @callback_method_impl{FNCPUMRDMSR} */
3782static DECLCALLBACK(int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3783{
3784 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3785 * cpus. Need to be explored and verify K7 presence. */
3786 /** @todo undocumented */
3787 *puValue = 0;
3788 return VINF_SUCCESS;
3789}
3790
3791
3792/** @callback_method_impl{FNCPUMWRMSR} */
3793static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3794{
3795 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3796 * cpus. Need to be explored and verify K7 presence. */
3797 /** @todo undocumented */
3798 return VINF_SUCCESS;
3799}
3800
3801
3802/** @callback_method_impl{FNCPUMRDMSR} */
3803static DECLCALLBACK(int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3804{
3805 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3806 * cpus. Need to be explored and verify K7 presence. */
3807 /** @todo undocumented */
3808 *puValue = 0;
3809 return VINF_SUCCESS;
3810}
3811
3812
3813/** @callback_method_impl{FNCPUMWRMSR} */
3814static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3815{
3816 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3817 * cpus. Need to be explored and verify K7 presence. */
3818 /** @todo undocumented */
3819 return VINF_SUCCESS;
3820}
3821
3822
3823/** @callback_method_impl{FNCPUMRDMSR} */
3824static DECLCALLBACK(int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3825{
3826 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3827 * cpus. Need to be explored and verify K7 presence. */
3828 /** @todo AMD node ID and bios scratch. */
3829 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3830 return VINF_SUCCESS;
3831}
3832
3833
3834/** @callback_method_impl{FNCPUMWRMSR} */
3835static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3836{
3837 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3838 * cpus. Need to be explored and verify K7 presence. */
3839 /** @todo AMD node ID and bios scratch. */
3840 return VINF_SUCCESS;
3841}
3842
3843
3844/** @callback_method_impl{FNCPUMRDMSR} */
3845static DECLCALLBACK(int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3846{
3847 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3848 * cpus. Need to be explored and verify K7 presence. */
3849 /** @todo AMD DRx address masking (range breakpoints). */
3850 *puValue = 0;
3851 return VINF_SUCCESS;
3852}
3853
3854
3855/** @callback_method_impl{FNCPUMWRMSR} */
3856static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3857{
3858 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3859 * cpus. Need to be explored and verify K7 presence. */
3860 /** @todo AMD DRx address masking (range breakpoints). */
3861 return VINF_SUCCESS;
3862}
3863
3864
3865/** @callback_method_impl{FNCPUMRDMSR} */
3866static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3867{
3868 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3869 * cpus. Need to be explored and verify K7 presence. */
3870 /** @todo AMD undocument debugging features. */
3871 *puValue = 0;
3872 return VINF_SUCCESS;
3873}
3874
3875
3876/** @callback_method_impl{FNCPUMWRMSR} */
3877static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3878{
3879 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3880 * cpus. Need to be explored and verify K7 presence. */
3881 /** @todo AMD undocument debugging features. */
3882 return VINF_SUCCESS;
3883}
3884
3885
3886/** @callback_method_impl{FNCPUMRDMSR} */
3887static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3888{
3889 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3890 * cpus. Need to be explored and verify K7 presence. */
3891 /** @todo AMD undocument debugging features. */
3892 *puValue = 0;
3893 return VINF_SUCCESS;
3894}
3895
3896
3897/** @callback_method_impl{FNCPUMWRMSR} */
3898static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3899{
3900 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3901 * cpus. Need to be explored and verify K7 presence. */
3902 /** @todo AMD undocument debugging features. */
3903 return VINF_SUCCESS;
3904}
3905
3906
3907/** @callback_method_impl{FNCPUMRDMSR} */
3908static DECLCALLBACK(int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3909{
3910 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3911 * cpus. Need to be explored and verify K7 presence. */
3912 /** @todo AMD load-store config. */
3913 *puValue = 0;
3914 return VINF_SUCCESS;
3915}
3916
3917
3918/** @callback_method_impl{FNCPUMWRMSR} */
3919static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3920{
3921 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3922 * cpus. Need to be explored and verify K7 presence. */
3923 /** @todo AMD load-store config. */
3924 return VINF_SUCCESS;
3925}
3926
3927
3928/** @callback_method_impl{FNCPUMRDMSR} */
3929static DECLCALLBACK(int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3930{
3931 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3932 * cpus. Need to be explored and verify K7 presence. */
3933 /** @todo AMD instruction cache config. */
3934 *puValue = 0;
3935 return VINF_SUCCESS;
3936}
3937
3938
3939/** @callback_method_impl{FNCPUMWRMSR} */
3940static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3941{
3942 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3943 * cpus. Need to be explored and verify K7 presence. */
3944 /** @todo AMD instruction cache config. */
3945 return VINF_SUCCESS;
3946}
3947
3948
3949/** @callback_method_impl{FNCPUMRDMSR} */
3950static DECLCALLBACK(int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3951{
3952 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3953 * cpus. Need to be explored and verify K7 presence. */
3954 /** @todo AMD data cache config. */
3955 *puValue = 0;
3956 return VINF_SUCCESS;
3957}
3958
3959
3960/** @callback_method_impl{FNCPUMWRMSR} */
3961static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3962{
3963 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3964 * cpus. Need to be explored and verify K7 presence. */
3965 /** @todo AMD data cache config. */
3966 return VINF_SUCCESS;
3967}
3968
3969
3970/** @callback_method_impl{FNCPUMRDMSR} */
3971static DECLCALLBACK(int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3972{
3973 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3974 * cpus. Need to be explored and verify K7 presence. */
3975 /** @todo AMD bus unit config. */
3976 *puValue = 0;
3977 return VINF_SUCCESS;
3978}
3979
3980
3981/** @callback_method_impl{FNCPUMWRMSR} */
3982static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3983{
3984 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3985 * cpus. Need to be explored and verify K7 presence. */
3986 /** @todo AMD bus unit config. */
3987 return VINF_SUCCESS;
3988}
3989
3990
3991/** @callback_method_impl{FNCPUMRDMSR} */
3992static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3993{
3994 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3995 * cpus. Need to be explored and verify K7 presence. */
3996 /** @todo Undocument AMD debug control register \#2. */
3997 *puValue = 0;
3998 return VINF_SUCCESS;
3999}
4000
4001
4002/** @callback_method_impl{FNCPUMWRMSR} */
4003static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4004{
4005 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4006 * cpus. Need to be explored and verify K7 presence. */
4007 /** @todo Undocument AMD debug control register \#2. */
4008 return VINF_SUCCESS;
4009}
4010
4011
4012/** @callback_method_impl{FNCPUMRDMSR} */
4013static DECLCALLBACK(int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4014{
4015 /** @todo AMD FPU config. */
4016 *puValue = 0;
4017 return VINF_SUCCESS;
4018}
4019
4020
4021/** @callback_method_impl{FNCPUMWRMSR} */
4022static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4023{
4024 /** @todo AMD FPU config. */
4025 return VINF_SUCCESS;
4026}
4027
4028
4029/** @callback_method_impl{FNCPUMRDMSR} */
4030static DECLCALLBACK(int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4031{
4032 /** @todo AMD decoder config. */
4033 *puValue = 0;
4034 return VINF_SUCCESS;
4035}
4036
4037
4038/** @callback_method_impl{FNCPUMWRMSR} */
4039static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4040{
4041 /** @todo AMD decoder config. */
4042 return VINF_SUCCESS;
4043}
4044
4045
4046/** @callback_method_impl{FNCPUMRDMSR} */
4047static DECLCALLBACK(int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4048{
4049 /* Note! 10h and 16h */
4050 /** @todo AMD bus unit config. */
4051 *puValue = 0;
4052 return VINF_SUCCESS;
4053}
4054
4055
4056/** @callback_method_impl{FNCPUMWRMSR} */
4057static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4058{
4059 /* Note! 10h and 16h */
4060 /** @todo AMD bus unit config. */
4061 return VINF_SUCCESS;
4062}
4063
4064
4065/** @callback_method_impl{FNCPUMRDMSR} */
4066static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4067{
4068 /** @todo AMD unit config. */
4069 *puValue = 0;
4070 return VINF_SUCCESS;
4071}
4072
4073
4074/** @callback_method_impl{FNCPUMWRMSR} */
4075static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4076{
4077 /** @todo AMD unit config. */
4078 return VINF_SUCCESS;
4079}
4080
4081
4082/** @callback_method_impl{FNCPUMRDMSR} */
4083static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4084{
4085 /** @todo AMD unit config 2. */
4086 *puValue = 0;
4087 return VINF_SUCCESS;
4088}
4089
4090
4091/** @callback_method_impl{FNCPUMWRMSR} */
4092static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4093{
4094 /** @todo AMD unit config 2. */
4095 return VINF_SUCCESS;
4096}
4097
4098
4099/** @callback_method_impl{FNCPUMRDMSR} */
4100static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4101{
4102 /** @todo AMD combined unit config 3. */
4103 *puValue = 0;
4104 return VINF_SUCCESS;
4105}
4106
4107
4108/** @callback_method_impl{FNCPUMWRMSR} */
4109static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4110{
4111 /** @todo AMD combined unit config 3. */
4112 return VINF_SUCCESS;
4113}
4114
4115
4116/** @callback_method_impl{FNCPUMRDMSR} */
4117static DECLCALLBACK(int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4118{
4119 /** @todo AMD execution unit config. */
4120 *puValue = 0;
4121 return VINF_SUCCESS;
4122}
4123
4124
4125/** @callback_method_impl{FNCPUMWRMSR} */
4126static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4127{
4128 /** @todo AMD execution unit config. */
4129 return VINF_SUCCESS;
4130}
4131
4132
4133/** @callback_method_impl{FNCPUMRDMSR} */
4134static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4135{
4136 /** @todo AMD load-store config 2. */
4137 *puValue = 0;
4138 return VINF_SUCCESS;
4139}
4140
4141
4142/** @callback_method_impl{FNCPUMWRMSR} */
4143static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4144{
4145 /** @todo AMD load-store config 2. */
4146 return VINF_SUCCESS;
4147}
4148
4149
4150/** @callback_method_impl{FNCPUMRDMSR} */
4151static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4152{
4153 /** @todo AMD IBS. */
4154 *puValue = 0;
4155 return VINF_SUCCESS;
4156}
4157
4158
4159/** @callback_method_impl{FNCPUMWRMSR} */
4160static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4161{
4162 /** @todo AMD IBS. */
4163 return VINF_SUCCESS;
4164}
4165
4166
4167/** @callback_method_impl{FNCPUMRDMSR} */
4168static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4169{
4170 /** @todo AMD IBS. */
4171 *puValue = 0;
4172 return VINF_SUCCESS;
4173}
4174
4175
4176/** @callback_method_impl{FNCPUMWRMSR} */
4177static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4178{
4179 /** @todo AMD IBS. */
4180 return VINF_SUCCESS;
4181}
4182
4183
4184/** @callback_method_impl{FNCPUMRDMSR} */
4185static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4186{
4187 /** @todo AMD IBS. */
4188 *puValue = 0;
4189 return VINF_SUCCESS;
4190}
4191
4192
4193/** @callback_method_impl{FNCPUMWRMSR} */
4194static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4195{
4196 /** @todo AMD IBS. */
4197 return VINF_SUCCESS;
4198}
4199
4200
4201/** @callback_method_impl{FNCPUMRDMSR} */
4202static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4203{
4204 /** @todo AMD IBS. */
4205 *puValue = 0;
4206 return VINF_SUCCESS;
4207}
4208
4209
4210/** @callback_method_impl{FNCPUMWRMSR} */
4211static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4212{
4213 /** @todo AMD IBS. */
4214 return VINF_SUCCESS;
4215}
4216
4217
4218/** @callback_method_impl{FNCPUMRDMSR} */
4219static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4220{
4221 /** @todo AMD IBS. */
4222 *puValue = 0;
4223 return VINF_SUCCESS;
4224}
4225
4226
4227/** @callback_method_impl{FNCPUMWRMSR} */
4228static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4229{
4230 /** @todo AMD IBS. */
4231 if (!X86_IS_CANONICAL(uValue))
4232 {
4233 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4234 return VERR_CPUM_RAISE_GP_0;
4235 }
4236 return VINF_SUCCESS;
4237}
4238
4239
4240/** @callback_method_impl{FNCPUMRDMSR} */
4241static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4242{
4243 /** @todo AMD IBS. */
4244 *puValue = 0;
4245 return VINF_SUCCESS;
4246}
4247
4248
4249/** @callback_method_impl{FNCPUMWRMSR} */
4250static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4251{
4252 /** @todo AMD IBS. */
4253 return VINF_SUCCESS;
4254}
4255
4256
4257/** @callback_method_impl{FNCPUMRDMSR} */
4258static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4259{
4260 /** @todo AMD IBS. */
4261 *puValue = 0;
4262 return VINF_SUCCESS;
4263}
4264
4265
4266/** @callback_method_impl{FNCPUMWRMSR} */
4267static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4268{
4269 /** @todo AMD IBS. */
4270 return VINF_SUCCESS;
4271}
4272
4273
4274/** @callback_method_impl{FNCPUMRDMSR} */
4275static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4276{
4277 /** @todo AMD IBS. */
4278 *puValue = 0;
4279 return VINF_SUCCESS;
4280}
4281
4282
4283/** @callback_method_impl{FNCPUMWRMSR} */
4284static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4285{
4286 /** @todo AMD IBS. */
4287 return VINF_SUCCESS;
4288}
4289
4290
4291/** @callback_method_impl{FNCPUMRDMSR} */
4292static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4293{
4294 /** @todo AMD IBS. */
4295 *puValue = 0;
4296 return VINF_SUCCESS;
4297}
4298
4299
4300/** @callback_method_impl{FNCPUMWRMSR} */
4301static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4302{
4303 /** @todo AMD IBS. */
4304 if (!X86_IS_CANONICAL(uValue))
4305 {
4306 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4307 return VERR_CPUM_RAISE_GP_0;
4308 }
4309 return VINF_SUCCESS;
4310}
4311
4312
4313/** @callback_method_impl{FNCPUMRDMSR} */
4314static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4315{
4316 /** @todo AMD IBS. */
4317 *puValue = 0;
4318 return VINF_SUCCESS;
4319}
4320
4321
4322/** @callback_method_impl{FNCPUMWRMSR} */
4323static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4324{
4325 /** @todo AMD IBS. */
4326 return VINF_SUCCESS;
4327}
4328
4329
4330/** @callback_method_impl{FNCPUMRDMSR} */
4331static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4332{
4333 /** @todo AMD IBS. */
4334 *puValue = 0;
4335 return VINF_SUCCESS;
4336}
4337
4338
4339/** @callback_method_impl{FNCPUMWRMSR} */
4340static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4341{
4342 /** @todo AMD IBS. */
4343 return VINF_SUCCESS;
4344}
4345
4346
4347/** @callback_method_impl{FNCPUMRDMSR} */
4348static DECLCALLBACK(int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4349{
4350 /** @todo AMD IBS. */
4351 *puValue = 0;
4352 return VINF_SUCCESS;
4353}
4354
4355
4356/** @callback_method_impl{FNCPUMWRMSR} */
4357static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4358{
4359 /** @todo AMD IBS. */
4360 if (!X86_IS_CANONICAL(uValue))
4361 {
4362 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4363 return VERR_CPUM_RAISE_GP_0;
4364 }
4365 return VINF_SUCCESS;
4366}
4367
4368
4369
4370/**
4371 * MSR read function table.
4372 */
4373static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4374{
4375 NULL, /* Invalid */
4376 cpumMsrRd_FixedValue,
4377 NULL, /* Alias */
4378 cpumMsrRd_WriteOnly,
4379 cpumMsrRd_Ia32P5McAddr,
4380 cpumMsrRd_Ia32P5McType,
4381 cpumMsrRd_Ia32TimestampCounter,
4382 cpumMsrRd_Ia32PlatformId,
4383 cpumMsrRd_Ia32ApicBase,
4384 cpumMsrRd_Ia32FeatureControl,
4385 cpumMsrRd_Ia32BiosSignId,
4386 cpumMsrRd_Ia32SmmMonitorCtl,
4387 cpumMsrRd_Ia32PmcN,
4388 cpumMsrRd_Ia32MonitorFilterLineSize,
4389 cpumMsrRd_Ia32MPerf,
4390 cpumMsrRd_Ia32APerf,
4391 cpumMsrRd_Ia32MtrrCap,
4392 cpumMsrRd_Ia32MtrrPhysBaseN,
4393 cpumMsrRd_Ia32MtrrPhysMaskN,
4394 cpumMsrRd_Ia32MtrrFixed,
4395 cpumMsrRd_Ia32MtrrDefType,
4396 cpumMsrRd_Ia32Pat,
4397 cpumMsrRd_Ia32SysEnterCs,
4398 cpumMsrRd_Ia32SysEnterEsp,
4399 cpumMsrRd_Ia32SysEnterEip,
4400 cpumMsrRd_Ia32McgCap,
4401 cpumMsrRd_Ia32McgStatus,
4402 cpumMsrRd_Ia32McgCtl,
4403 cpumMsrRd_Ia32DebugCtl,
4404 cpumMsrRd_Ia32SmrrPhysBase,
4405 cpumMsrRd_Ia32SmrrPhysMask,
4406 cpumMsrRd_Ia32PlatformDcaCap,
4407 cpumMsrRd_Ia32CpuDcaCap,
4408 cpumMsrRd_Ia32Dca0Cap,
4409 cpumMsrRd_Ia32PerfEvtSelN,
4410 cpumMsrRd_Ia32PerfStatus,
4411 cpumMsrRd_Ia32PerfCtl,
4412 cpumMsrRd_Ia32FixedCtrN,
4413 cpumMsrRd_Ia32PerfCapabilities,
4414 cpumMsrRd_Ia32FixedCtrCtrl,
4415 cpumMsrRd_Ia32PerfGlobalStatus,
4416 cpumMsrRd_Ia32PerfGlobalCtrl,
4417 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4418 cpumMsrRd_Ia32PebsEnable,
4419 cpumMsrRd_Ia32ClockModulation,
4420 cpumMsrRd_Ia32ThermInterrupt,
4421 cpumMsrRd_Ia32ThermStatus,
4422 cpumMsrRd_Ia32Therm2Ctl,
4423 cpumMsrRd_Ia32MiscEnable,
4424 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4425 cpumMsrRd_Ia32McNCtl2,
4426 cpumMsrRd_Ia32DsArea,
4427 cpumMsrRd_Ia32TscDeadline,
4428 cpumMsrRd_Ia32X2ApicN,
4429 cpumMsrRd_Ia32DebugInterface,
4430 cpumMsrRd_Ia32VmxBase,
4431 cpumMsrRd_Ia32VmxPinbasedCtls,
4432 cpumMsrRd_Ia32VmxProcbasedCtls,
4433 cpumMsrRd_Ia32VmxExitCtls,
4434 cpumMsrRd_Ia32VmxEntryCtls,
4435 cpumMsrRd_Ia32VmxMisc,
4436 cpumMsrRd_Ia32VmxCr0Fixed0,
4437 cpumMsrRd_Ia32VmxCr0Fixed1,
4438 cpumMsrRd_Ia32VmxCr4Fixed0,
4439 cpumMsrRd_Ia32VmxCr4Fixed1,
4440 cpumMsrRd_Ia32VmxVmcsEnum,
4441 cpumMsrRd_Ia32VmxProcBasedCtls2,
4442 cpumMsrRd_Ia32VmxEptVpidCap,
4443 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4444 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4445 cpumMsrRd_Ia32VmxTrueExitCtls,
4446 cpumMsrRd_Ia32VmxTrueEntryCtls,
4447
4448 cpumMsrRd_Amd64Efer,
4449 cpumMsrRd_Amd64SyscallTarget,
4450 cpumMsrRd_Amd64LongSyscallTarget,
4451 cpumMsrRd_Amd64CompSyscallTarget,
4452 cpumMsrRd_Amd64SyscallFlagMask,
4453 cpumMsrRd_Amd64FsBase,
4454 cpumMsrRd_Amd64GsBase,
4455 cpumMsrRd_Amd64KernelGsBase,
4456 cpumMsrRd_Amd64TscAux,
4457
4458 cpumMsrRd_IntelEblCrPowerOn,
4459 cpumMsrRd_IntelP4EbcHardPowerOn,
4460 cpumMsrRd_IntelP4EbcSoftPowerOn,
4461 cpumMsrRd_IntelP4EbcFrequencyId,
4462 cpumMsrRd_IntelP6FsbFrequency,
4463 cpumMsrRd_IntelPlatformInfo,
4464 cpumMsrRd_IntelFlexRatio,
4465 cpumMsrRd_IntelPkgCStConfigControl,
4466 cpumMsrRd_IntelPmgIoCaptureBase,
4467 cpumMsrRd_IntelLastBranchFromToN,
4468 cpumMsrRd_IntelLastBranchFromN,
4469 cpumMsrRd_IntelLastBranchToN,
4470 cpumMsrRd_IntelLastBranchTos,
4471 cpumMsrRd_IntelBblCrCtl,
4472 cpumMsrRd_IntelBblCrCtl3,
4473 cpumMsrRd_IntelI7TemperatureTarget,
4474 cpumMsrRd_IntelI7MsrOffCoreResponseN,
4475 cpumMsrRd_IntelI7MiscPwrMgmt,
4476 cpumMsrRd_IntelP6CrN,
4477 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4478 cpumMsrRd_IntelCpuId1FeatureMaskEax,
4479 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4480 cpumMsrRd_IntelI7SandyAesNiCtl,
4481 cpumMsrRd_IntelI7TurboRatioLimit,
4482 cpumMsrRd_IntelI7LbrSelect,
4483 cpumMsrRd_IntelI7SandyErrorControl,
4484 cpumMsrRd_IntelI7VirtualLegacyWireCap,
4485 cpumMsrRd_IntelI7PowerCtl,
4486 cpumMsrRd_IntelI7SandyPebsNumAlt,
4487 cpumMsrRd_IntelI7PebsLdLat,
4488 cpumMsrRd_IntelI7PkgCnResidencyN,
4489 cpumMsrRd_IntelI7CoreCnResidencyN,
4490 cpumMsrRd_IntelI7SandyVrCurrentConfig,
4491 cpumMsrRd_IntelI7SandyVrMiscConfig,
4492 cpumMsrRd_IntelI7SandyRaplPowerUnit,
4493 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4494 cpumMsrRd_IntelI7SandyPkgC2Residency,
4495 cpumMsrRd_IntelI7RaplPkgPowerLimit,
4496 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4497 cpumMsrRd_IntelI7RaplPkgPerfStatus,
4498 cpumMsrRd_IntelI7RaplPkgPowerInfo,
4499 cpumMsrRd_IntelI7RaplDramPowerLimit,
4500 cpumMsrRd_IntelI7RaplDramEnergyStatus,
4501 cpumMsrRd_IntelI7RaplDramPerfStatus,
4502 cpumMsrRd_IntelI7RaplDramPowerInfo,
4503 cpumMsrRd_IntelI7RaplPp0PowerLimit,
4504 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4505 cpumMsrRd_IntelI7RaplPp0Policy,
4506 cpumMsrRd_IntelI7RaplPp0PerfStatus,
4507 cpumMsrRd_IntelI7RaplPp1PowerLimit,
4508 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4509 cpumMsrRd_IntelI7RaplPp1Policy,
4510 cpumMsrRd_IntelI7IvyConfigTdpNominal,
4511 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4512 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4513 cpumMsrRd_IntelI7IvyConfigTdpControl,
4514 cpumMsrRd_IntelI7IvyTurboActivationRatio,
4515 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4516 cpumMsrRd_IntelI7UncPerfGlobalStatus,
4517 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4518 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4519 cpumMsrRd_IntelI7UncPerfFixedCtr,
4520 cpumMsrRd_IntelI7UncCBoxConfig,
4521 cpumMsrRd_IntelI7UncArbPerfCtrN,
4522 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4523 cpumMsrRd_IntelCore2EmttmCrTablesN,
4524 cpumMsrRd_IntelCore2SmmCStMiscInfo,
4525 cpumMsrRd_IntelCore1ExtConfig,
4526 cpumMsrRd_IntelCore1DtsCalControl,
4527 cpumMsrRd_IntelCore2PeciControl,
4528
4529 cpumMsrRd_P6LastBranchFromIp,
4530 cpumMsrRd_P6LastBranchToIp,
4531 cpumMsrRd_P6LastIntFromIp,
4532 cpumMsrRd_P6LastIntToIp,
4533
4534 cpumMsrRd_AmdFam15hTscRate,
4535 cpumMsrRd_AmdFam15hLwpCfg,
4536 cpumMsrRd_AmdFam15hLwpCbAddr,
4537 cpumMsrRd_AmdFam10hMc4MiscN,
4538 cpumMsrRd_AmdK8PerfCtlN,
4539 cpumMsrRd_AmdK8PerfCtrN,
4540 cpumMsrRd_AmdK8SysCfg,
4541 cpumMsrRd_AmdK8HwCr,
4542 cpumMsrRd_AmdK8IorrBaseN,
4543 cpumMsrRd_AmdK8IorrMaskN,
4544 cpumMsrRd_AmdK8TopOfMemN,
4545 cpumMsrRd_AmdK8NbCfg1,
4546 cpumMsrRd_AmdK8McXcptRedir,
4547 cpumMsrRd_AmdK8CpuNameN,
4548 cpumMsrRd_AmdK8HwThermalCtrl,
4549 cpumMsrRd_AmdK8SwThermalCtrl,
4550 cpumMsrRd_AmdK8FidVidControl,
4551 cpumMsrRd_AmdK8FidVidStatus,
4552 cpumMsrRd_AmdK8McCtlMaskN,
4553 cpumMsrRd_AmdK8SmiOnIoTrapN,
4554 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4555 cpumMsrRd_AmdK8IntPendingMessage,
4556 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4557 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4558 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4559 cpumMsrRd_AmdFam10hPStateCurLimit,
4560 cpumMsrRd_AmdFam10hPStateControl,
4561 cpumMsrRd_AmdFam10hPStateStatus,
4562 cpumMsrRd_AmdFam10hPStateN,
4563 cpumMsrRd_AmdFam10hCofVidControl,
4564 cpumMsrRd_AmdFam10hCofVidStatus,
4565 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4566 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4567 cpumMsrRd_AmdK8SmmBase,
4568 cpumMsrRd_AmdK8SmmAddr,
4569 cpumMsrRd_AmdK8SmmMask,
4570 cpumMsrRd_AmdK8VmCr,
4571 cpumMsrRd_AmdK8IgnNe,
4572 cpumMsrRd_AmdK8SmmCtl,
4573 cpumMsrRd_AmdK8VmHSavePa,
4574 cpumMsrRd_AmdFam10hVmLockKey,
4575 cpumMsrRd_AmdFam10hSmmLockKey,
4576 cpumMsrRd_AmdFam10hLocalSmiStatus,
4577 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4578 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4579 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4580 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4581 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4582 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4583 cpumMsrRd_AmdK7MicrocodeCtl,
4584 cpumMsrRd_AmdK7ClusterIdMaybe,
4585 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4586 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4587 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4588 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4589 cpumMsrRd_AmdK8PatchLevel,
4590 cpumMsrRd_AmdK7DebugStatusMaybe,
4591 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4592 cpumMsrRd_AmdK7BHTracePtrMaybe,
4593 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4594 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4595 cpumMsrRd_AmdK7FastFlushCountMaybe,
4596 cpumMsrRd_AmdK7NodeId,
4597 cpumMsrRd_AmdK7DrXAddrMaskN,
4598 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4599 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4600 cpumMsrRd_AmdK7LoadStoreCfg,
4601 cpumMsrRd_AmdK7InstrCacheCfg,
4602 cpumMsrRd_AmdK7DataCacheCfg,
4603 cpumMsrRd_AmdK7BusUnitCfg,
4604 cpumMsrRd_AmdK7DebugCtl2Maybe,
4605 cpumMsrRd_AmdFam15hFpuCfg,
4606 cpumMsrRd_AmdFam15hDecoderCfg,
4607 cpumMsrRd_AmdFam10hBusUnitCfg2,
4608 cpumMsrRd_AmdFam15hCombUnitCfg,
4609 cpumMsrRd_AmdFam15hCombUnitCfg2,
4610 cpumMsrRd_AmdFam15hCombUnitCfg3,
4611 cpumMsrRd_AmdFam15hExecUnitCfg,
4612 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4613 cpumMsrRd_AmdFam10hIbsFetchCtl,
4614 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4615 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4616 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4617 cpumMsrRd_AmdFam10hIbsOpRip,
4618 cpumMsrRd_AmdFam10hIbsOpData,
4619 cpumMsrRd_AmdFam10hIbsOpData2,
4620 cpumMsrRd_AmdFam10hIbsOpData3,
4621 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4622 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4623 cpumMsrRd_AmdFam10hIbsCtl,
4624 cpumMsrRd_AmdFam14hIbsBrTarget,
4625};
4626
4627
4628/**
4629 * MSR write function table.
4630 */
4631static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4632{
4633 NULL, /* Invalid */
4634 cpumMsrWr_IgnoreWrite,
4635 cpumMsrWr_ReadOnly,
4636 NULL, /* Alias */
4637 cpumMsrWr_Ia32P5McAddr,
4638 cpumMsrWr_Ia32P5McType,
4639 cpumMsrWr_Ia32TimestampCounter,
4640 cpumMsrWr_Ia32ApicBase,
4641 cpumMsrWr_Ia32FeatureControl,
4642 cpumMsrWr_Ia32BiosSignId,
4643 cpumMsrWr_Ia32BiosUpdateTrigger,
4644 cpumMsrWr_Ia32SmmMonitorCtl,
4645 cpumMsrWr_Ia32PmcN,
4646 cpumMsrWr_Ia32MonitorFilterLineSize,
4647 cpumMsrWr_Ia32MPerf,
4648 cpumMsrWr_Ia32APerf,
4649 cpumMsrWr_Ia32MtrrPhysBaseN,
4650 cpumMsrWr_Ia32MtrrPhysMaskN,
4651 cpumMsrWr_Ia32MtrrFixed,
4652 cpumMsrWr_Ia32MtrrDefType,
4653 cpumMsrWr_Ia32Pat,
4654 cpumMsrWr_Ia32SysEnterCs,
4655 cpumMsrWr_Ia32SysEnterEsp,
4656 cpumMsrWr_Ia32SysEnterEip,
4657 cpumMsrWr_Ia32McgStatus,
4658 cpumMsrWr_Ia32McgCtl,
4659 cpumMsrWr_Ia32DebugCtl,
4660 cpumMsrWr_Ia32SmrrPhysBase,
4661 cpumMsrWr_Ia32SmrrPhysMask,
4662 cpumMsrWr_Ia32PlatformDcaCap,
4663 cpumMsrWr_Ia32Dca0Cap,
4664 cpumMsrWr_Ia32PerfEvtSelN,
4665 cpumMsrWr_Ia32PerfStatus,
4666 cpumMsrWr_Ia32PerfCtl,
4667 cpumMsrWr_Ia32FixedCtrN,
4668 cpumMsrWr_Ia32PerfCapabilities,
4669 cpumMsrWr_Ia32FixedCtrCtrl,
4670 cpumMsrWr_Ia32PerfGlobalStatus,
4671 cpumMsrWr_Ia32PerfGlobalCtrl,
4672 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4673 cpumMsrWr_Ia32PebsEnable,
4674 cpumMsrWr_Ia32ClockModulation,
4675 cpumMsrWr_Ia32ThermInterrupt,
4676 cpumMsrWr_Ia32ThermStatus,
4677 cpumMsrWr_Ia32Therm2Ctl,
4678 cpumMsrWr_Ia32MiscEnable,
4679 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4680 cpumMsrWr_Ia32McNCtl2,
4681 cpumMsrWr_Ia32DsArea,
4682 cpumMsrWr_Ia32TscDeadline,
4683 cpumMsrWr_Ia32X2ApicN,
4684 cpumMsrWr_Ia32DebugInterface,
4685
4686 cpumMsrWr_Amd64Efer,
4687 cpumMsrWr_Amd64SyscallTarget,
4688 cpumMsrWr_Amd64LongSyscallTarget,
4689 cpumMsrWr_Amd64CompSyscallTarget,
4690 cpumMsrWr_Amd64SyscallFlagMask,
4691 cpumMsrWr_Amd64FsBase,
4692 cpumMsrWr_Amd64GsBase,
4693 cpumMsrWr_Amd64KernelGsBase,
4694 cpumMsrWr_Amd64TscAux,
4695
4696 cpumMsrWr_IntelEblCrPowerOn,
4697 cpumMsrWr_IntelP4EbcHardPowerOn,
4698 cpumMsrWr_IntelP4EbcSoftPowerOn,
4699 cpumMsrWr_IntelP4EbcFrequencyId,
4700 cpumMsrWr_IntelFlexRatio,
4701 cpumMsrWr_IntelPkgCStConfigControl,
4702 cpumMsrWr_IntelPmgIoCaptureBase,
4703 cpumMsrWr_IntelLastBranchFromToN,
4704 cpumMsrWr_IntelLastBranchFromN,
4705 cpumMsrWr_IntelLastBranchToN,
4706 cpumMsrWr_IntelLastBranchTos,
4707 cpumMsrWr_IntelBblCrCtl,
4708 cpumMsrWr_IntelBblCrCtl3,
4709 cpumMsrWr_IntelI7TemperatureTarget,
4710 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4711 cpumMsrWr_IntelI7MiscPwrMgmt,
4712 cpumMsrWr_IntelP6CrN,
4713 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4714 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4715 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4716 cpumMsrWr_IntelI7SandyAesNiCtl,
4717 cpumMsrWr_IntelI7TurboRatioLimit,
4718 cpumMsrWr_IntelI7LbrSelect,
4719 cpumMsrWr_IntelI7SandyErrorControl,
4720 cpumMsrWr_IntelI7PowerCtl,
4721 cpumMsrWr_IntelI7SandyPebsNumAlt,
4722 cpumMsrWr_IntelI7PebsLdLat,
4723 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4724 cpumMsrWr_IntelI7SandyVrMiscConfig,
4725 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4726 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4727 cpumMsrWr_IntelI7RaplDramPowerLimit,
4728 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4729 cpumMsrWr_IntelI7RaplPp0Policy,
4730 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4731 cpumMsrWr_IntelI7RaplPp1Policy,
4732 cpumMsrWr_IntelI7IvyConfigTdpControl,
4733 cpumMsrWr_IntelI7IvyTurboActivationRatio,
4734 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4735 cpumMsrWr_IntelI7UncPerfGlobalStatus,
4736 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4737 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4738 cpumMsrWr_IntelI7UncPerfFixedCtr,
4739 cpumMsrWr_IntelI7UncArbPerfCtrN,
4740 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4741 cpumMsrWr_IntelCore2EmttmCrTablesN,
4742 cpumMsrWr_IntelCore2SmmCStMiscInfo,
4743 cpumMsrWr_IntelCore1ExtConfig,
4744 cpumMsrWr_IntelCore1DtsCalControl,
4745 cpumMsrWr_IntelCore2PeciControl,
4746
4747 cpumMsrWr_P6LastIntFromIp,
4748 cpumMsrWr_P6LastIntToIp,
4749
4750 cpumMsrWr_AmdFam15hTscRate,
4751 cpumMsrWr_AmdFam15hLwpCfg,
4752 cpumMsrWr_AmdFam15hLwpCbAddr,
4753 cpumMsrWr_AmdFam10hMc4MiscN,
4754 cpumMsrWr_AmdK8PerfCtlN,
4755 cpumMsrWr_AmdK8PerfCtrN,
4756 cpumMsrWr_AmdK8SysCfg,
4757 cpumMsrWr_AmdK8HwCr,
4758 cpumMsrWr_AmdK8IorrBaseN,
4759 cpumMsrWr_AmdK8IorrMaskN,
4760 cpumMsrWr_AmdK8TopOfMemN,
4761 cpumMsrWr_AmdK8NbCfg1,
4762 cpumMsrWr_AmdK8McXcptRedir,
4763 cpumMsrWr_AmdK8CpuNameN,
4764 cpumMsrWr_AmdK8HwThermalCtrl,
4765 cpumMsrWr_AmdK8SwThermalCtrl,
4766 cpumMsrWr_AmdK8FidVidControl,
4767 cpumMsrWr_AmdK8McCtlMaskN,
4768 cpumMsrWr_AmdK8SmiOnIoTrapN,
4769 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4770 cpumMsrWr_AmdK8IntPendingMessage,
4771 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4772 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4773 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4774 cpumMsrWr_AmdFam10hPStateControl,
4775 cpumMsrWr_AmdFam10hPStateStatus,
4776 cpumMsrWr_AmdFam10hPStateN,
4777 cpumMsrWr_AmdFam10hCofVidControl,
4778 cpumMsrWr_AmdFam10hCofVidStatus,
4779 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4780 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4781 cpumMsrWr_AmdK8SmmBase,
4782 cpumMsrWr_AmdK8SmmAddr,
4783 cpumMsrWr_AmdK8SmmMask,
4784 cpumMsrWr_AmdK8VmCr,
4785 cpumMsrWr_AmdK8IgnNe,
4786 cpumMsrWr_AmdK8SmmCtl,
4787 cpumMsrWr_AmdK8VmHSavePa,
4788 cpumMsrWr_AmdFam10hVmLockKey,
4789 cpumMsrWr_AmdFam10hSmmLockKey,
4790 cpumMsrWr_AmdFam10hLocalSmiStatus,
4791 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4792 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4793 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4794 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4795 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4796 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4797 cpumMsrWr_AmdK7MicrocodeCtl,
4798 cpumMsrWr_AmdK7ClusterIdMaybe,
4799 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4800 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4801 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4802 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4803 cpumMsrWr_AmdK8PatchLoader,
4804 cpumMsrWr_AmdK7DebugStatusMaybe,
4805 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4806 cpumMsrWr_AmdK7BHTracePtrMaybe,
4807 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4808 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4809 cpumMsrWr_AmdK7FastFlushCountMaybe,
4810 cpumMsrWr_AmdK7NodeId,
4811 cpumMsrWr_AmdK7DrXAddrMaskN,
4812 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4813 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4814 cpumMsrWr_AmdK7LoadStoreCfg,
4815 cpumMsrWr_AmdK7InstrCacheCfg,
4816 cpumMsrWr_AmdK7DataCacheCfg,
4817 cpumMsrWr_AmdK7BusUnitCfg,
4818 cpumMsrWr_AmdK7DebugCtl2Maybe,
4819 cpumMsrWr_AmdFam15hFpuCfg,
4820 cpumMsrWr_AmdFam15hDecoderCfg,
4821 cpumMsrWr_AmdFam10hBusUnitCfg2,
4822 cpumMsrWr_AmdFam15hCombUnitCfg,
4823 cpumMsrWr_AmdFam15hCombUnitCfg2,
4824 cpumMsrWr_AmdFam15hCombUnitCfg3,
4825 cpumMsrWr_AmdFam15hExecUnitCfg,
4826 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4827 cpumMsrWr_AmdFam10hIbsFetchCtl,
4828 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4829 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4830 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4831 cpumMsrWr_AmdFam10hIbsOpRip,
4832 cpumMsrWr_AmdFam10hIbsOpData,
4833 cpumMsrWr_AmdFam10hIbsOpData2,
4834 cpumMsrWr_AmdFam10hIbsOpData3,
4835 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4836 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4837 cpumMsrWr_AmdFam10hIbsCtl,
4838 cpumMsrWr_AmdFam14hIbsBrTarget,
4839};
4840
4841
4842/**
4843 * Looks up the range for the given MSR.
4844 *
4845 * @returns Pointer to the range if found, NULL if not.
4846 * @param pVM The cross context VM structure.
4847 * @param idMsr The MSR to look up.
4848 */
4849# ifndef IN_RING3
4850static
4851# endif
4852PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4853{
4854 /*
4855 * Binary lookup.
4856 */
4857 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4858 if (!cRanges)
4859 return NULL;
4860 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4861 for (;;)
4862 {
4863 uint32_t i = cRanges / 2;
4864 if (idMsr < paRanges[i].uFirst)
4865 {
4866 if (i == 0)
4867 break;
4868 cRanges = i;
4869 }
4870 else if (idMsr > paRanges[i].uLast)
4871 {
4872 i++;
4873 if (i >= cRanges)
4874 break;
4875 cRanges -= i;
4876 paRanges = &paRanges[i];
4877 }
4878 else
4879 {
4880 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4881 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4882 return &paRanges[i];
4883 }
4884 }
4885
4886# ifdef VBOX_STRICT
4887 /*
4888 * Linear lookup to verify the above binary search.
4889 */
4890 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4891 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4892 while (cLeft-- > 0)
4893 {
4894 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4895 {
4896 AssertFailed();
4897 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4898 return cpumLookupMsrRange(pVM, pCur->uValue);
4899 return pCur;
4900 }
4901 pCur++;
4902 }
4903# endif
4904 return NULL;
4905}
4906
4907#ifdef VBOX_WITH_NEW_MSR_CODE
4908
4909/**
4910 * Query a guest MSR.
4911 *
4912 * The caller is responsible for checking privilege if the call is the result of
4913 * a RDMSR instruction. We'll do the rest.
4914 *
4915 * @retval VINF_SUCCESS on success.
4916 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4917 * expected to take the appropriate actions. @a *puValue is set to 0.
4918 * @param pVCpu Pointer to the VMCPU.
4919 * @param idMsr The MSR.
4920 * @param puValue Where to return the value.
4921 *
4922 * @remarks This will always return the right values, even when we're in the
4923 * recompiler.
4924 */
4925VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4926{
4927 *puValue = 0;
4928
4929 int rc;
4930 PVM pVM = pVCpu->CTX_SUFF(pVM);
4931 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4932 if (pRange)
4933 {
4934 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4935 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4936
4937 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
4938 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
4939
4940 STAM_COUNTER_INC(&pRange->cReads);
4941 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4942
4943 rc = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
4944 if (RT_SUCCESS(rc))
4945 {
4946 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
4947 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4948 }
4949 else if (rc == VERR_CPUM_RAISE_GP_0)
4950 {
4951 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
4952 STAM_COUNTER_INC(&pRange->cGps);
4953 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
4954 }
4955 else
4956 Log(("CPUM: RDMSR %#x (%s) -> rc=%Rrc\n", idMsr, pRange->szName, rc));
4957 }
4958 else
4959 {
4960 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
4961 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4962 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
4963 rc = VERR_CPUM_RAISE_GP_0;
4964 }
4965 return rc;
4966}
4967
4968
4969/**
4970 * Writes to a guest MSR.
4971 *
4972 * The caller is responsible for checking privilege if the call is the result of
4973 * a WRMSR instruction. We'll do the rest.
4974 *
4975 * @retval VINF_SUCCESS on success.
4976 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
4977 * appropriate actions.
4978 *
4979 * @param pVCpu Pointer to the VMCPU.
4980 * @param idMsr The MSR id.
4981 * @param uValue The value to set.
4982 *
4983 * @remarks Everyone changing MSR values, including the recompiler, shall do it
4984 * by calling this method. This makes sure we have current values and
4985 * that we trigger all the right actions when something changes.
4986 *
4987 * For performance reasons, this actually isn't entirely true for some
4988 * MSRs when in HM mode. The code here and in HM must be aware of
4989 * this.
4990 */
4991VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
4992{
4993 int rc;
4994 PVM pVM = pVCpu->CTX_SUFF(pVM);
4995 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4996 if (pRange)
4997 {
4998 STAM_COUNTER_INC(&pRange->cWrites);
4999 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5000
5001 if (!(uValue & pRange->fWrGpMask))
5002 {
5003 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5004 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5005
5006 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5007 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5008
5009 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5010 if (uValueAdjusted != uValue)
5011 {
5012 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5013 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5014 }
5015
5016 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5017 if (RT_SUCCESS(rc))
5018 {
5019 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5020 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
5021 }
5022 else if (rc == VERR_CPUM_RAISE_GP_0)
5023 {
5024 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5025 STAM_COUNTER_INC(&pRange->cGps);
5026 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5027 }
5028 else
5029 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc));
5030 }
5031 else
5032 {
5033 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5034 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5035 STAM_COUNTER_INC(&pRange->cGps);
5036 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5037 rc = VERR_CPUM_RAISE_GP_0;
5038 }
5039 }
5040 else
5041 {
5042 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5043 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5044 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5045 rc = VERR_CPUM_RAISE_GP_0;
5046 }
5047 return rc;
5048}
5049
5050#endif /* VBOX_WITH_NEW_MSR_CODE */
5051
5052
5053#if defined(VBOX_STRICT) && defined(IN_RING3)
5054/**
5055 * Performs some checks on the static data related to MSRs.
5056 *
5057 * @returns VINF_SUCCESS on success, error on failure.
5058 */
5059int cpumR3MsrStrictInitChecks(void)
5060{
5061#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5062 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5063#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5064 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5065
5066 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5067 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5068 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5069 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5070 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5071 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5072 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5073 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5074 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5075 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5076 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5077 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5078 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5079 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5080 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5081 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5082 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5083 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5084 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5085 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5086 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5087 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5088 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5089 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5090 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5091 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5092 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5093 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5094 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5095 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5096 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5097 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5098 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5099 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5100 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5101 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5102 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5103 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5104 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5105 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5106 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5107 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5108 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5109 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5110 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5111 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5112 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5113 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5114 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5115 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5116 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5117 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5118 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5119 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5120 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5121 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5122 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5123 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5124 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5125 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5126 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5127 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5128 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5129 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5130 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5131 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5132 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5133 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5134 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5135 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5136
5137 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5138 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5139 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5140 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5141 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5142 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5143 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5144 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5145 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5146
5147 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5148 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5149 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5150 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5151 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5152 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5153 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5154 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5155 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5156 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5157 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5158 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5159 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5160 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5161 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5162 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5163 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5164 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5165 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5166 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5167 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5168 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5169 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5170 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5171 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5172 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5173 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5174 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5175 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5176 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5177 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5178 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5179 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5180 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5181 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5182 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5183 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5184 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5185 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5186 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5187 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5188 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5189 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5190 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5191 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5192 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5193 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5194 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5195 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5196 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5197 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5198 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5199 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5200 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5201 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5202 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5203 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5204 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5205 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5206 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5207 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5208 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5209 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5210 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5211 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5212 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5213 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5214 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5215 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5216 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5217
5218 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5219 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5220 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5221 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5222
5223 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5224 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5225 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5226 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5227 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5228 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5229 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5230 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5231 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5232 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5233 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5234 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5235 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5236 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5237 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5238 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5239 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5240 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5241 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5242 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5243 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5244 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5245 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5246 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5247 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5248 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5249 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5250 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5251 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5252 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5253 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5254 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5255 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5256 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5257 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5258 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5259 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5260 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5261 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5262 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5263 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5264 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5265 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5266 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5267 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5268 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5269 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5270 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5271 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5272 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5273 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5274 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5275 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5276 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5277 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5278 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5279 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5280 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5281 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5282 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5283 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5284 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5285 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5286 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5287 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5288 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5289 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5290 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5291 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5292 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5293 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5294 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5295 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5296 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5297 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5298 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5299 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5300 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5301 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5302 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5303 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5304 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5305 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5306 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5307 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5308 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5309 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5310 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5311 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5312 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5313 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5314
5315 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5316 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5317 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5318 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5319 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5320 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5321 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5322 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5323 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5324 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5325 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5326 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5327 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5328 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5329 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5330 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5331 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5332 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5333 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5334 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5335 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5336 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5337 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5338 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5339 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5340 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5341 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5342 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5343 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5344 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5345 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5346 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5347 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5348 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5349 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5350 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5351 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5352 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5353 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5354 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5355 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5356 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5357 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5358 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5359 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5360 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5361 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5362 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5363
5364 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5365 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5366 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5367 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5368 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5369 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5370 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5371 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5372 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5373
5374 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5375 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5376 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5377 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5378 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
5379 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5380 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5381 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5382 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5383 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5384 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5385 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5386 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5387 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5388 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5389 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5390 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5391 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5392 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5393 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5394 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5395 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5396 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5397 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5398 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5399 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5400 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5401 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5402 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5403 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5404 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5405 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5406 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5407 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5408 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5409 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5410 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5411 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5412 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5413 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5414 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5415 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5416 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5417 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5418 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5419 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5420 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5421 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5422 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5423 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5424
5425 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5426 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5427
5428 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5429 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5430 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5431 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5432 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5433 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5434 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5435 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5436 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5437 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5438 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5439 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5440 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5441 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5442 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5443 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5444 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5445 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5446 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5447 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5448 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5449 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5450 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5451 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5452 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5453 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5454 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5455 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5456 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5457 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5458 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5459 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5460 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5461 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5462 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5463 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5464 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5465 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5466 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5467 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5468 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5469 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5470 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5471 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5472 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5473 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5474 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5475 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5476 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5477 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5478 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5479 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5480 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5481 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5482 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5483 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5484 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5485 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5486 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5487 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5488 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5489 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5490 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5491 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5492 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5493 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5494 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5495 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5496 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5497 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5498 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5499 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5500 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5501 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5502 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5503 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5504 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5505 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5506 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5507 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5508 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5509 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5510 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5511 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5512 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5513 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5514 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5515 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5516 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5517
5518 return VINF_SUCCESS;
5519}
5520#endif /* VBOX_STRICT && IN_RING3 */
5521
5522
5523/**
5524 * Gets the scalable bus frequency.
5525 *
5526 * The bus frequency is used as a base in several MSRs that gives the CPU and
5527 * other frequency ratios.
5528 *
5529 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
5530 * @param pVM Pointer to the shared VM structure.
5531 */
5532VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
5533{
5534 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
5535 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
5536 uFreq = CPUM_SBUSFREQ_100MHZ;
5537 return uFreq;
5538}
5539
5540
5541#ifdef IN_RING0
5542
5543/**
5544 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5545 *
5546 * @returns The register value.
5547 * @param pVCpu Pointer to the cross context CPU structure for
5548 * the calling EMT.
5549 * @thread EMT(pVCpu)
5550 */
5551VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5552{
5553 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5554}
5555
5556
5557/**
5558 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5559 *
5560 * @param pVCpu Pointer to the cross context CPU structure for
5561 * the calling EMT.
5562 * @param uValue The new value.
5563 * @thread EMT(pVCpu)
5564 */
5565VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5566{
5567 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5568}
5569
5570#endif /* IN_RING0 */
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