VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 50141

Last change on this file since 50141 was 49981, checked in by vboxsync, 11 years ago

CPUMAllMsrs.cpp: Fixed cpumLookupMsrRange to resolved aliases. Also reimplemented it as a binary search.
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1/* $Id: CPUMAllMsrs.cpp 49981 2013-12-19 10:59:28Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/pdmapi.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/tm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/err.h>
29
30
31/*******************************************************************************
32* Defined Constants And Macros *
33*******************************************************************************/
34/**
35 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
36 * pointing to it.
37 *
38 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
39 * correctly.
40 */
41#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
42 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
43 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
44 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
45 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
46 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
47 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53
54/**
55 * Implements reading one or more MSRs.
56 *
57 * @returns VBox status code.
58 * @retval VINF_SUCCESS on success.
59 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
60 *
61 * @param pVCpu Pointer to the VMCPU.
62 * @param idMsr The MSR we're reading.
63 * @param pRange The MSR range descriptor.
64 * @param puValue Where to return the value.
65 */
66typedef DECLCALLBACK(int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
67/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
68typedef FNCPUMRDMSR *PFNCPUMRDMSR;
69
70
71/**
72 * Implements writing one or more MSRs.
73 *
74 * @retval VINF_SUCCESS on success.
75 * @retval VERR_CPUM_RAISE_GP_0 on failure.
76 *
77 * @param pVCpu Pointer to the VMCPU.
78 * @param idMsr The MSR we're writing.
79 * @param pRange The MSR range descriptor.
80 * @param uValue The value to set, ignored bits masked.
81 * @param uRawValue The raw value with the ignored bits not masked.
82 */
83typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
84/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
85typedef FNCPUMWRMSR *PFNCPUMWRMSR;
86
87
88
89/*
90 * Generic functions.
91 * Generic functions.
92 * Generic functions.
93 */
94
95
96/** @callback_method_impl{FNCPUMRDMSR} */
97static DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
98{
99 *puValue = pRange->uValue;
100 return VINF_SUCCESS;
101}
102
103
104/** @callback_method_impl{FNCPUMWRMSR} */
105static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
106{
107 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
108 return VINF_SUCCESS;
109}
110
111
112/** @callback_method_impl{FNCPUMRDMSR} */
113static DECLCALLBACK(int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
114{
115 return VERR_CPUM_RAISE_GP_0;
116}
117
118
119/** @callback_method_impl{FNCPUMWRMSR} */
120static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
121{
122 Assert(pRange->fWrGpMask == UINT64_MAX);
123 return VERR_CPUM_RAISE_GP_0;
124}
125
126
127
128
129/*
130 * IA32
131 * IA32
132 * IA32
133 */
134
135/** @callback_method_impl{FNCPUMRDMSR} */
136static DECLCALLBACK(int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
137{
138 *puValue = 0; /** @todo implement machine check injection. */
139 return VINF_SUCCESS;
140}
141
142
143/** @callback_method_impl{FNCPUMWRMSR} */
144static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
145{
146 /** @todo implement machine check injection. */
147 return VINF_SUCCESS;
148}
149
150
151/** @callback_method_impl{FNCPUMRDMSR} */
152static DECLCALLBACK(int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
153{
154 *puValue = 0; /** @todo implement machine check injection. */
155 return VINF_SUCCESS;
156}
157
158
159/** @callback_method_impl{FNCPUMWRMSR} */
160static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
161{
162 /** @todo implement machine check injection. */
163 return VINF_SUCCESS;
164}
165
166
167/** @callback_method_impl{FNCPUMRDMSR} */
168static DECLCALLBACK(int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
169{
170 *puValue = TMCpuTickGet(pVCpu);
171 return VINF_SUCCESS;
172}
173
174
175/** @callback_method_impl{FNCPUMWRMSR} */
176static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
177{
178 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
179 return VINF_SUCCESS;
180}
181
182
183/** @callback_method_impl{FNCPUMRDMSR} */
184static DECLCALLBACK(int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
185{
186 PVM pVM = pVCpu->CTX_SUFF(pVM);
187 if ( !pVM->cpum.s.GuestFeatures.fApic
188 && !pVM->cpum.s.GuestFeatures.fX2Apic)
189 {
190 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
191 return VERR_CPUM_RAISE_GP_0;
192 }
193
194 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
195 return VINF_SUCCESS;
196}
197
198
199/** @callback_method_impl{FNCPUMWRMSR} */
200static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
201{
202 int rc = PDMApicSetBase(pVCpu, uValue);
203 if (rc != VINF_SUCCESS)
204 rc = VERR_CPUM_RAISE_GP_0;
205 return VINF_SUCCESS;
206}
207
208
209/** @callback_method_impl{FNCPUMRDMSR} */
210static DECLCALLBACK(int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
211{
212 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
213 return VINF_SUCCESS;
214}
215
216
217/** @callback_method_impl{FNCPUMWRMSR} */
218static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
219{
220 return VERR_CPUM_RAISE_GP_0;
221}
222
223
224/** @callback_method_impl{FNCPUMRDMSR} */
225static DECLCALLBACK(int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
226{
227 /** @todo fake microcode update. */
228 *puValue = pRange->uValue;
229 return VINF_SUCCESS;
230}
231
232
233/** @callback_method_impl{FNCPUMWRMSR} */
234static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
235{
236 return VERR_CPUM_RAISE_GP_0;
237}
238
239
240/** @callback_method_impl{FNCPUMWRMSR} */
241static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
242{
243 /** @todo Fake bios update trigger better. The value is the address to an
244 * update package, I think. We should probably GP if it's invalid. */
245 return VINF_SUCCESS;
246}
247
248
249/** @callback_method_impl{FNCPUMRDMSR} */
250static DECLCALLBACK(int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
251{
252 /** @todo SMM. */
253 *puValue = 0;
254 return VINF_SUCCESS;
255}
256
257
258/** @callback_method_impl{FNCPUMWRMSR} */
259static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
260{
261 /** @todo SMM. */
262 return VINF_SUCCESS;
263}
264
265
266/** @callback_method_impl{FNCPUMRDMSR} */
267static DECLCALLBACK(int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
268{
269 /** @todo check CPUID leaf 0ah. */
270 *puValue = 0;
271 return VINF_SUCCESS;
272}
273
274
275/** @callback_method_impl{FNCPUMWRMSR} */
276static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
277{
278 /** @todo check CPUID leaf 0ah. */
279 return VINF_SUCCESS;
280}
281
282
283/** @callback_method_impl{FNCPUMRDMSR} */
284static DECLCALLBACK(int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
285{
286 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
287 *puValue = 0x40; /** @todo Change to CPU cache line size. */
288 return VINF_SUCCESS;
289}
290
291
292/** @callback_method_impl{FNCPUMWRMSR} */
293static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
294{
295 /** @todo should remember writes, though it's supposedly something only a BIOS
296 * would write so, it's not extremely important. */
297 return VINF_SUCCESS;
298}
299
300/** @callback_method_impl{FNCPUMRDMSR} */
301static DECLCALLBACK(int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
302{
303 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
304 * what we want? */
305 *puValue = TMCpuTickGet(pVCpu);
306 return VINF_SUCCESS;
307}
308
309
310/** @callback_method_impl{FNCPUMWRMSR} */
311static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
312{
313 /** @todo Write MPERF: Calc adjustment. */
314 return VINF_SUCCESS;
315}
316
317
318/** @callback_method_impl{FNCPUMRDMSR} */
319static DECLCALLBACK(int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
320{
321 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
322 * what we want? */
323 *puValue = TMCpuTickGet(pVCpu);
324 return VINF_SUCCESS;
325}
326
327
328/** @callback_method_impl{FNCPUMWRMSR} */
329static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
330{
331 /** @todo Write APERF: Calc adjustment. */
332 return VINF_SUCCESS;
333}
334
335
336/** @callback_method_impl{FNCPUMWRMSR} */
337static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
338{
339 /* This is currently a bit weird. :-) */
340 uint8_t const cVariableRangeRegs = 0;
341 bool const fSystemManagementRangeRegisters = false;
342 bool const fFixedRangeRegisters = false;
343 bool const fWriteCombiningType = false;
344 *puValue = cVariableRangeRegs
345 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
346 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
347 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
348 return VINF_SUCCESS;
349}
350
351
352/** @callback_method_impl{FNCPUMRDMSR} */
353static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
354{
355 /** @todo Implement variable MTRR storage. */
356 Assert(pRange->uValue == (idMsr - 0x200) / 2);
357 *puValue = 0;
358 return VINF_SUCCESS;
359}
360
361
362/** @callback_method_impl{FNCPUMWRMSR} */
363static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
364{
365 /*
366 * Validate the value.
367 */
368 Assert(pRange->uValue == (idMsr - 0x200) / 2);
369
370 if ((uValue & 0xff) >= 7)
371 {
372 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
373 return VERR_CPUM_RAISE_GP_0;
374 }
375
376 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
377 if (fInvPhysMask & uValue)
378 {
379 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
380 idMsr, uValue, uValue & fInvPhysMask));
381 return VERR_CPUM_RAISE_GP_0;
382 }
383
384 /*
385 * Store it.
386 */
387 /** @todo Implement variable MTRR storage. */
388 return VINF_SUCCESS;
389}
390
391
392/** @callback_method_impl{FNCPUMRDMSR} */
393static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
394{
395 /** @todo Implement variable MTRR storage. */
396 Assert(pRange->uValue == (idMsr - 0x200) / 2);
397 *puValue = 0;
398 return VINF_SUCCESS;
399}
400
401
402/** @callback_method_impl{FNCPUMWRMSR} */
403static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
404{
405 /*
406 * Validate the value.
407 */
408 Assert(pRange->uValue == (idMsr - 0x200) / 2);
409
410 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
411 if (fInvPhysMask & uValue)
412 {
413 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
414 idMsr, uValue, uValue & fInvPhysMask));
415 return VERR_CPUM_RAISE_GP_0;
416 }
417
418 /*
419 * Store it.
420 */
421 /** @todo Implement variable MTRR storage. */
422 return VINF_SUCCESS;
423}
424
425
426/** @callback_method_impl{FNCPUMRDMSR} */
427static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
428{
429 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
430 *puValue = *puFixedMtrr;
431 return VINF_SUCCESS;
432}
433
434
435/** @callback_method_impl{FNCPUMWRMSR} */
436static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
437{
438 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
439 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
440 {
441 uint8_t uType = (uint8_t)(uValue >> cShift);
442 if (uType >= 7)
443 {
444 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
445 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
446 return VERR_CPUM_RAISE_GP_0;
447 }
448 }
449 *puFixedMtrr = uValue;
450 return VINF_SUCCESS;
451}
452
453
454/** @callback_method_impl{FNCPUMRDMSR} */
455static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
456{
457 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
458 return VINF_SUCCESS;
459}
460
461
462/** @callback_method_impl{FNCPUMWRMSR} */
463static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
464{
465 if ((uValue & 0xff) >= 7)
466 {
467 Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
468 return VERR_CPUM_RAISE_GP_0;
469 }
470
471 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
472 return VINF_SUCCESS;
473}
474
475
476/** @callback_method_impl{FNCPUMRDMSR} */
477static DECLCALLBACK(int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
478{
479 *puValue = pVCpu->cpum.s.Guest.msrPAT;
480 return VINF_SUCCESS;
481}
482
483
484/** @callback_method_impl{FNCPUMWRMSR} */
485static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
486{
487 pVCpu->cpum.s.Guest.msrPAT = uValue;
488 return VINF_SUCCESS;
489}
490
491
492/** @callback_method_impl{FNCPUMRDMSR} */
493static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
494{
495 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
496 return VINF_SUCCESS;
497}
498
499
500/** @callback_method_impl{FNCPUMWRMSR} */
501static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
502{
503 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
504 there are generally 32-bit working bits backing this register. */
505 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
506 return VINF_SUCCESS;
507}
508
509
510/** @callback_method_impl{FNCPUMRDMSR} */
511static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
512{
513 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
514 return VINF_SUCCESS;
515}
516
517
518/** @callback_method_impl{FNCPUMWRMSR} */
519static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
520{
521 if (X86_IS_CANONICAL(uValue))
522 {
523 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
524 return VINF_SUCCESS;
525 }
526 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
527 return VERR_CPUM_RAISE_GP_0;
528}
529
530
531/** @callback_method_impl{FNCPUMRDMSR} */
532static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
533{
534 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
535 return VINF_SUCCESS;
536}
537
538
539/** @callback_method_impl{FNCPUMWRMSR} */
540static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
541{
542 if (X86_IS_CANONICAL(uValue))
543 {
544 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
545 return VINF_SUCCESS;
546 }
547 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
548 return VERR_CPUM_RAISE_GP_0;
549}
550
551
552/** @callback_method_impl{FNCPUMRDMSR} */
553static DECLCALLBACK(int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
554{
555#if 0 /** @todo implement machine checks. */
556 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
557#else
558 *puValue = 0;
559#endif
560 return VINF_SUCCESS;
561}
562
563
564/** @callback_method_impl{FNCPUMRDMSR} */
565static DECLCALLBACK(int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
566{
567 /** @todo implement machine checks. */
568 *puValue = 0;
569 return VINF_SUCCESS;
570}
571
572
573/** @callback_method_impl{FNCPUMWRMSR} */
574static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
575{
576 /** @todo implement machine checks. */
577 return VINF_SUCCESS;
578}
579
580
581/** @callback_method_impl{FNCPUMRDMSR} */
582static DECLCALLBACK(int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
583{
584 /** @todo implement machine checks. */
585 *puValue = 0;
586 return VINF_SUCCESS;
587}
588
589
590/** @callback_method_impl{FNCPUMWRMSR} */
591static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
592{
593 /** @todo implement machine checks. */
594 return VINF_SUCCESS;
595}
596
597
598/** @callback_method_impl{FNCPUMRDMSR} */
599static DECLCALLBACK(int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
600{
601 /** @todo implement IA32_DEBUGCTL. */
602 *puValue = 0;
603 return VINF_SUCCESS;
604}
605
606
607/** @callback_method_impl{FNCPUMWRMSR} */
608static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
609{
610 /** @todo implement IA32_DEBUGCTL. */
611 return VINF_SUCCESS;
612}
613
614
615/** @callback_method_impl{FNCPUMRDMSR} */
616static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
617{
618 /** @todo implement intel SMM. */
619 *puValue = 0;
620 return VINF_SUCCESS;
621}
622
623
624/** @callback_method_impl{FNCPUMWRMSR} */
625static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
626{
627 /** @todo implement intel SMM. */
628 return VERR_CPUM_RAISE_GP_0;
629}
630
631
632/** @callback_method_impl{FNCPUMRDMSR} */
633static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
634{
635 /** @todo implement intel SMM. */
636 *puValue = 0;
637 return VINF_SUCCESS;
638}
639
640
641/** @callback_method_impl{FNCPUMWRMSR} */
642static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
643{
644 /** @todo implement intel SMM. */
645 return VERR_CPUM_RAISE_GP_0;
646}
647
648
649/** @callback_method_impl{FNCPUMRDMSR} */
650static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
651{
652 /** @todo implement intel direct cache access (DCA)?? */
653 *puValue = 0;
654 return VINF_SUCCESS;
655}
656
657
658/** @callback_method_impl{FNCPUMWRMSR} */
659static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
660{
661 /** @todo implement intel direct cache access (DCA)?? */
662 return VINF_SUCCESS;
663}
664
665
666/** @callback_method_impl{FNCPUMRDMSR} */
667static DECLCALLBACK(int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
668{
669 /** @todo implement intel direct cache access (DCA)?? */
670 *puValue = 0;
671 return VINF_SUCCESS;
672}
673
674
675/** @callback_method_impl{FNCPUMRDMSR} */
676static DECLCALLBACK(int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
677{
678 /** @todo implement intel direct cache access (DCA)?? */
679 *puValue = 0;
680 return VINF_SUCCESS;
681}
682
683
684/** @callback_method_impl{FNCPUMWRMSR} */
685static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
686{
687 /** @todo implement intel direct cache access (DCA)?? */
688 return VINF_SUCCESS;
689}
690
691
692/** @callback_method_impl{FNCPUMRDMSR} */
693static DECLCALLBACK(int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
694{
695 /** @todo implement IA32_PERFEVTSEL0+. */
696 *puValue = 0;
697 return VINF_SUCCESS;
698}
699
700
701/** @callback_method_impl{FNCPUMWRMSR} */
702static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
703{
704 /** @todo implement IA32_PERFEVTSEL0+. */
705 return VINF_SUCCESS;
706}
707
708
709/** @callback_method_impl{FNCPUMRDMSR} */
710static DECLCALLBACK(int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
711{
712 /** @todo implement IA32_PERFSTATUS. */
713 *puValue = pRange->uValue;
714 return VINF_SUCCESS;
715}
716
717
718/** @callback_method_impl{FNCPUMWRMSR} */
719static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
720{
721 /* Pentium4 allows writing, but all bits are ignored. */
722 return VINF_SUCCESS;
723}
724
725
726/** @callback_method_impl{FNCPUMRDMSR} */
727static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
728{
729 /** @todo implement IA32_PERFCTL. */
730 *puValue = 0;
731 return VINF_SUCCESS;
732}
733
734
735/** @callback_method_impl{FNCPUMWRMSR} */
736static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
737{
738 /** @todo implement IA32_PERFCTL. */
739 return VINF_SUCCESS;
740}
741
742
743/** @callback_method_impl{FNCPUMRDMSR} */
744static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
745{
746 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
747 *puValue = 0;
748 return VINF_SUCCESS;
749}
750
751
752/** @callback_method_impl{FNCPUMWRMSR} */
753static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
754{
755 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
756 return VINF_SUCCESS;
757}
758
759
760/** @callback_method_impl{FNCPUMRDMSR} */
761static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
762{
763 /** @todo implement performance counters. */
764 *puValue = 0;
765 return VINF_SUCCESS;
766}
767
768
769/** @callback_method_impl{FNCPUMWRMSR} */
770static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
771{
772 /** @todo implement performance counters. */
773 return VINF_SUCCESS;
774}
775
776
777/** @callback_method_impl{FNCPUMRDMSR} */
778static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
779{
780 /** @todo implement performance counters. */
781 *puValue = 0;
782 return VINF_SUCCESS;
783}
784
785
786/** @callback_method_impl{FNCPUMWRMSR} */
787static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
788{
789 /** @todo implement performance counters. */
790 return VINF_SUCCESS;
791}
792
793
794/** @callback_method_impl{FNCPUMRDMSR} */
795static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
796{
797 /** @todo implement performance counters. */
798 *puValue = 0;
799 return VINF_SUCCESS;
800}
801
802
803/** @callback_method_impl{FNCPUMWRMSR} */
804static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
805{
806 /** @todo implement performance counters. */
807 return VINF_SUCCESS;
808}
809
810
811/** @callback_method_impl{FNCPUMRDMSR} */
812static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
813{
814 /** @todo implement performance counters. */
815 *puValue = 0;
816 return VINF_SUCCESS;
817}
818
819
820/** @callback_method_impl{FNCPUMWRMSR} */
821static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
822{
823 /** @todo implement performance counters. */
824 return VINF_SUCCESS;
825}
826
827
828/** @callback_method_impl{FNCPUMRDMSR} */
829static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
830{
831 /** @todo implement performance counters. */
832 *puValue = 0;
833 return VINF_SUCCESS;
834}
835
836
837/** @callback_method_impl{FNCPUMWRMSR} */
838static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
839{
840 /** @todo implement performance counters. */
841 return VINF_SUCCESS;
842}
843
844
845/** @callback_method_impl{FNCPUMRDMSR} */
846static DECLCALLBACK(int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
847{
848 /** @todo implement performance counters. */
849 *puValue = 0;
850 return VINF_SUCCESS;
851}
852
853
854/** @callback_method_impl{FNCPUMWRMSR} */
855static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
856{
857 /** @todo implement performance counters. */
858 return VINF_SUCCESS;
859}
860
861
862/** @callback_method_impl{FNCPUMRDMSR} */
863static DECLCALLBACK(int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
864{
865 /** @todo implement IA32_CLOCK_MODULATION. */
866 *puValue = 0;
867 return VINF_SUCCESS;
868}
869
870
871/** @callback_method_impl{FNCPUMWRMSR} */
872static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
873{
874 /** @todo implement IA32_CLOCK_MODULATION. */
875 return VINF_SUCCESS;
876}
877
878
879/** @callback_method_impl{FNCPUMRDMSR} */
880static DECLCALLBACK(int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
881{
882 /** @todo implement IA32_THERM_INTERRUPT. */
883 *puValue = 0;
884 return VINF_SUCCESS;
885}
886
887
888/** @callback_method_impl{FNCPUMWRMSR} */
889static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
890{
891 /** @todo implement IA32_THERM_STATUS. */
892 return VINF_SUCCESS;
893}
894
895
896/** @callback_method_impl{FNCPUMRDMSR} */
897static DECLCALLBACK(int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
898{
899 /** @todo implement IA32_THERM_STATUS. */
900 *puValue = 0;
901 return VINF_SUCCESS;
902}
903
904
905/** @callback_method_impl{FNCPUMWRMSR} */
906static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
907{
908 /** @todo implement IA32_THERM_INTERRUPT. */
909 return VINF_SUCCESS;
910}
911
912
913/** @callback_method_impl{FNCPUMRDMSR} */
914static DECLCALLBACK(int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
915{
916 /** @todo implement IA32_THERM2_CTL. */
917 *puValue = 0;
918 return VINF_SUCCESS;
919}
920
921
922/** @callback_method_impl{FNCPUMWRMSR} */
923static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
924{
925 /** @todo implement IA32_THERM2_CTL. */
926 return VINF_SUCCESS;
927}
928
929
930/** @callback_method_impl{FNCPUMRDMSR} */
931static DECLCALLBACK(int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
932{
933 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
934 return VINF_SUCCESS;
935}
936
937
938/** @callback_method_impl{FNCPUMWRMSR} */
939static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
940{
941#ifdef LOG_ENABLED
942 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
943#endif
944
945 /* Unsupported bits are generally ignored and stripped by the MSR range
946 entry that got us here. So, we just need to preserve fixed bits. */
947 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
948 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
949 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
950
951 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
952 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
953
954 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
955 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
956 return VINF_SUCCESS;
957}
958
959
960/** @callback_method_impl{FNCPUMRDMSR} */
961static DECLCALLBACK(int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
962{
963 /** @todo Implement machine check exception injection. */
964 switch (idMsr & 3)
965 {
966 case 0:
967 case 1:
968 *puValue = 0;
969 break;
970
971 /* The ADDR and MISC registers aren't accessible since the
972 corresponding STATUS bits are zero. */
973 case 2:
974 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
975 return VERR_CPUM_RAISE_GP_0;
976 case 3:
977 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
978 return VERR_CPUM_RAISE_GP_0;
979 }
980 return VINF_SUCCESS;
981}
982
983
984/** @callback_method_impl{FNCPUMWRMSR} */
985static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
986{
987 switch (idMsr & 3)
988 {
989 case 0:
990 /* Ignore writes to the CTL register. */
991 break;
992
993 case 1:
994 /* According to specs, the STATUS register can only be written to
995 with the value 0. VBoxCpuReport thinks different for a
996 Pentium M Dothan, but implementing according to specs now. */
997 if (uValue != 0)
998 {
999 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1000 return VERR_CPUM_RAISE_GP_0;
1001 }
1002 break;
1003
1004 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1005 Writing 1s will GP. Need to figure out how this relates to the
1006 ADDRV and MISCV status flags. If writing is independent of those
1007 bits, we need to know whether the CPU really implements them since
1008 that is exposed by writing 0 to them.
1009 Implementing the solution with the fewer GPs for now. */
1010 case 2:
1011 if (uValue != 0)
1012 {
1013 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1014 return VERR_CPUM_RAISE_GP_0;
1015 }
1016 break;
1017 case 3:
1018 if (uValue != 0)
1019 {
1020 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1021 return VERR_CPUM_RAISE_GP_0;
1022 }
1023 break;
1024 }
1025 return VINF_SUCCESS;
1026}
1027
1028
1029/** @callback_method_impl{FNCPUMRDMSR} */
1030static DECLCALLBACK(int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1031{
1032 /** @todo Implement machine check exception injection. */
1033 *puValue = 0;
1034 return VINF_SUCCESS;
1035}
1036
1037
1038/** @callback_method_impl{FNCPUMWRMSR} */
1039static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1040{
1041 /** @todo Implement machine check exception injection. */
1042 return VINF_SUCCESS;
1043}
1044
1045
1046/** @callback_method_impl{FNCPUMRDMSR} */
1047static DECLCALLBACK(int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1048{
1049 /** @todo implement IA32_DS_AREA. */
1050 *puValue = 0;
1051 return VINF_SUCCESS;
1052}
1053
1054
1055/** @callback_method_impl{FNCPUMWRMSR} */
1056static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1057{
1058 return VINF_SUCCESS;
1059}
1060
1061
1062/** @callback_method_impl{FNCPUMRDMSR} */
1063static DECLCALLBACK(int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1064{
1065 /** @todo implement TSC deadline timer. */
1066 *puValue = 0;
1067 return VINF_SUCCESS;
1068}
1069
1070
1071/** @callback_method_impl{FNCPUMWRMSR} */
1072static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1073{
1074 /** @todo implement TSC deadline timer. */
1075 return VINF_SUCCESS;
1076}
1077
1078
1079/** @callback_method_impl{FNCPUMRDMSR} */
1080static DECLCALLBACK(int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1081{
1082 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1083 if (rc != VINF_SUCCESS)
1084 {
1085 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1086 return VERR_CPUM_RAISE_GP_0;
1087 }
1088 return VINF_SUCCESS;
1089}
1090
1091
1092/** @callback_method_impl{FNCPUMWRMSR} */
1093static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1094{
1095 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1096 if (rc != VINF_SUCCESS)
1097 {
1098 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1099 return VERR_CPUM_RAISE_GP_0;
1100 }
1101 return VINF_SUCCESS;
1102}
1103
1104
1105/** @callback_method_impl{FNCPUMRDMSR} */
1106static DECLCALLBACK(int) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1107{
1108 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1109 *puValue = 0;
1110 return VINF_SUCCESS;
1111}
1112
1113
1114/** @callback_method_impl{FNCPUMWRMSR} */
1115static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1116{
1117 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1118 return VINF_SUCCESS;
1119}
1120
1121
1122/** @callback_method_impl{FNCPUMRDMSR} */
1123static DECLCALLBACK(int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1124{
1125 *puValue = 0;
1126 return VINF_SUCCESS;
1127}
1128
1129
1130/** @callback_method_impl{FNCPUMRDMSR} */
1131static DECLCALLBACK(int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1132{
1133 *puValue = 0;
1134 return VINF_SUCCESS;
1135}
1136
1137
1138/** @callback_method_impl{FNCPUMRDMSR} */
1139static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1140{
1141 *puValue = 0;
1142 return VINF_SUCCESS;
1143}
1144
1145
1146/** @callback_method_impl{FNCPUMRDMSR} */
1147static DECLCALLBACK(int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1148{
1149 *puValue = 0;
1150 return VINF_SUCCESS;
1151}
1152
1153
1154/** @callback_method_impl{FNCPUMRDMSR} */
1155static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1156{
1157 *puValue = 0;
1158 return VINF_SUCCESS;
1159}
1160
1161
1162/** @callback_method_impl{FNCPUMRDMSR} */
1163static DECLCALLBACK(int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1164{
1165 *puValue = 0;
1166 return VINF_SUCCESS;
1167}
1168
1169
1170/** @callback_method_impl{FNCPUMRDMSR} */
1171static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1172{
1173 *puValue = 0;
1174 return VINF_SUCCESS;
1175}
1176
1177
1178/** @callback_method_impl{FNCPUMRDMSR} */
1179static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1180{
1181 *puValue = 0;
1182 return VINF_SUCCESS;
1183}
1184
1185
1186/** @callback_method_impl{FNCPUMRDMSR} */
1187static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1188{
1189 *puValue = 0;
1190 return VINF_SUCCESS;
1191}
1192
1193
1194/** @callback_method_impl{FNCPUMRDMSR} */
1195static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1196{
1197 *puValue = 0;
1198 return VINF_SUCCESS;
1199}
1200
1201
1202/** @callback_method_impl{FNCPUMRDMSR} */
1203static DECLCALLBACK(int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1204{
1205 *puValue = 0;
1206 return VINF_SUCCESS;
1207}
1208
1209
1210/** @callback_method_impl{FNCPUMRDMSR} */
1211static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1212{
1213 *puValue = 0;
1214 return VINF_SUCCESS;
1215}
1216
1217
1218/** @callback_method_impl{FNCPUMRDMSR} */
1219static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1220{
1221 *puValue = 0;
1222 return VINF_SUCCESS;
1223}
1224
1225
1226/** @callback_method_impl{FNCPUMRDMSR} */
1227static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1228{
1229 *puValue = 0;
1230 return VINF_SUCCESS;
1231}
1232
1233
1234/** @callback_method_impl{FNCPUMRDMSR} */
1235static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1236{
1237 *puValue = 0;
1238 return VINF_SUCCESS;
1239}
1240
1241
1242/** @callback_method_impl{FNCPUMRDMSR} */
1243static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1244{
1245 *puValue = 0;
1246 return VINF_SUCCESS;
1247}
1248
1249
1250/** @callback_method_impl{FNCPUMRDMSR} */
1251static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1252{
1253 *puValue = 0;
1254 return VINF_SUCCESS;
1255}
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266/*
1267 * AMD64
1268 * AMD64
1269 * AMD64
1270 */
1271
1272
1273/** @callback_method_impl{FNCPUMRDMSR} */
1274static DECLCALLBACK(int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1275{
1276 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1277 return VINF_SUCCESS;
1278}
1279
1280
1281/** @callback_method_impl{FNCPUMWRMSR} */
1282static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1283{
1284 PVM pVM = pVCpu->CTX_SUFF(pVM);
1285 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1286 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1287 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1288 : 0;
1289 uint64_t fMask = 0;
1290
1291 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1292 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1293 fMask |= MSR_K6_EFER_NXE;
1294 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1295 fMask |= MSR_K6_EFER_LME;
1296 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1297 fMask |= MSR_K6_EFER_SCE;
1298 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1299 fMask |= MSR_K6_EFER_FFXSR;
1300
1301 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1302 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1303 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1304 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1305 {
1306 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1307 return VERR_CPUM_RAISE_GP_0;
1308 }
1309
1310 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1311 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1312 ("Unexpected value %RX64\n", uValue));
1313 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1314
1315 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1316 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1317 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1318 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1319 {
1320 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1321 HMFlushTLB(pVCpu);
1322
1323 /* Notify PGM about NXE changes. */
1324 if ( (uOldEfer & MSR_K6_EFER_NXE)
1325 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1326 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1327 }
1328 return VINF_SUCCESS;
1329}
1330
1331
1332/** @callback_method_impl{FNCPUMRDMSR} */
1333static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1334{
1335 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1336 return VINF_SUCCESS;
1337}
1338
1339
1340/** @callback_method_impl{FNCPUMWRMSR} */
1341static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1342{
1343 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1344 return VINF_SUCCESS;
1345}
1346
1347
1348/** @callback_method_impl{FNCPUMRDMSR} */
1349static DECLCALLBACK(int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1350{
1351 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1352 return VINF_SUCCESS;
1353}
1354
1355
1356/** @callback_method_impl{FNCPUMWRMSR} */
1357static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1358{
1359 if (!X86_IS_CANONICAL(uValue))
1360 {
1361 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1362 return VERR_CPUM_RAISE_GP_0;
1363 }
1364 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1365 return VINF_SUCCESS;
1366}
1367
1368
1369/** @callback_method_impl{FNCPUMRDMSR} */
1370static DECLCALLBACK(int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1371{
1372 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1373 return VINF_SUCCESS;
1374}
1375
1376
1377/** @callback_method_impl{FNCPUMWRMSR} */
1378static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1379{
1380 if (!X86_IS_CANONICAL(uValue))
1381 {
1382 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1383 return VERR_CPUM_RAISE_GP_0;
1384 }
1385 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1386 return VINF_SUCCESS;
1387}
1388
1389
1390/** @callback_method_impl{FNCPUMRDMSR} */
1391static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1392{
1393 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1394 return VINF_SUCCESS;
1395}
1396
1397
1398/** @callback_method_impl{FNCPUMWRMSR} */
1399static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1400{
1401 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1402 return VINF_SUCCESS;
1403}
1404
1405
1406/** @callback_method_impl{FNCPUMRDMSR} */
1407static DECLCALLBACK(int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1408{
1409 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1410 return VINF_SUCCESS;
1411}
1412
1413
1414/** @callback_method_impl{FNCPUMWRMSR} */
1415static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1416{
1417 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1418 return VINF_SUCCESS;
1419}
1420
1421
1422/** @callback_method_impl{FNCPUMRDMSR} */
1423static DECLCALLBACK(int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1424{
1425 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1426 return VINF_SUCCESS;
1427}
1428
1429/** @callback_method_impl{FNCPUMWRMSR} */
1430static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1431{
1432 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1433 return VINF_SUCCESS;
1434}
1435
1436
1437
1438/** @callback_method_impl{FNCPUMRDMSR} */
1439static DECLCALLBACK(int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1440{
1441 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1442 return VINF_SUCCESS;
1443}
1444
1445/** @callback_method_impl{FNCPUMWRMSR} */
1446static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1447{
1448 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1449 return VINF_SUCCESS;
1450}
1451
1452
1453/** @callback_method_impl{FNCPUMRDMSR} */
1454static DECLCALLBACK(int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1455{
1456 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1457 return VINF_SUCCESS;
1458}
1459
1460/** @callback_method_impl{FNCPUMWRMSR} */
1461static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1462{
1463 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1464 return VINF_SUCCESS;
1465}
1466
1467
1468/*
1469 * Intel specific
1470 * Intel specific
1471 * Intel specific
1472 */
1473
1474/** @callback_method_impl{FNCPUMRDMSR} */
1475static DECLCALLBACK(int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1476{
1477 /** @todo recalc clock frequency ratio? */
1478 *puValue = pRange->uValue;
1479 return VINF_SUCCESS;
1480}
1481
1482
1483/** @callback_method_impl{FNCPUMWRMSR} */
1484static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1485{
1486 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1487 return VINF_SUCCESS;
1488}
1489
1490
1491/** @callback_method_impl{FNCPUMRDMSR} */
1492static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1493{
1494 /** @todo P4 hard power on config */
1495 *puValue = pRange->uValue;
1496 return VINF_SUCCESS;
1497}
1498
1499
1500/** @callback_method_impl{FNCPUMWRMSR} */
1501static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1502{
1503 /** @todo P4 hard power on config */
1504 return VINF_SUCCESS;
1505}
1506
1507
1508/** @callback_method_impl{FNCPUMRDMSR} */
1509static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1510{
1511 /** @todo P4 soft power on config */
1512 *puValue = pRange->uValue;
1513 return VINF_SUCCESS;
1514}
1515
1516
1517/** @callback_method_impl{FNCPUMWRMSR} */
1518static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1519{
1520 /** @todo P4 soft power on config */
1521 return VINF_SUCCESS;
1522}
1523
1524
1525/** @callback_method_impl{FNCPUMRDMSR} */
1526static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1527{
1528 /** @todo P4 bus frequency config */
1529 *puValue = pRange->uValue;
1530 return VINF_SUCCESS;
1531}
1532
1533
1534/** @callback_method_impl{FNCPUMWRMSR} */
1535static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1536{
1537 /** @todo P4 bus frequency config */
1538 return VINF_SUCCESS;
1539}
1540
1541
1542/** @callback_method_impl{FNCPUMRDMSR} */
1543static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo100MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1544{
1545 PVM pVM = pVCpu->CTX_SUFF(pVM);
1546
1547 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1548 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1549 uint8_t uTsc100MHz = (uint8_t)(uTscHz / UINT32_C(100000000));
1550 *puValue = ((uint32_t)uTsc100MHz << 8) /* TSC invariant frequency. */
1551 | ((uint64_t)uTsc100MHz << 40); /* The max turbo frequency. */
1552
1553 /* Ivy bridge has a minimum operating ratio as well. */
1554 if (true) /** @todo detect sandy bridge. */
1555 *puValue |= (uint64_t)uTsc100MHz << 48;
1556
1557 return VINF_SUCCESS;
1558}
1559
1560
1561/** @callback_method_impl{FNCPUMRDMSR} */
1562static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo133MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1563{
1564 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1565 uint64_t uTscHz = TMCpuTicksPerSecond(pVCpu->CTX_SUFF(pVM));
1566 uint8_t uTsc133MHz = (uint8_t)(uTscHz / UINT32_C(133333333));
1567 *puValue = ((uint32_t)uTsc133MHz << 8) /* TSC invariant frequency. */
1568 | ((uint64_t)uTsc133MHz << 40); /* The max turbo frequency. */
1569 return VINF_SUCCESS;
1570}
1571
1572
1573/** @callback_method_impl{FNCPUMRDMSR} */
1574static DECLCALLBACK(int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1575{
1576 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1577 return VINF_SUCCESS;
1578}
1579
1580
1581/** @callback_method_impl{FNCPUMWRMSR} */
1582static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1583{
1584 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1585 {
1586 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1587 return VERR_CPUM_RAISE_GP_0;
1588 }
1589#if 0 /** @todo check what real (old) hardware does. */
1590 if ((uValue & 7) >= 5)
1591 {
1592 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1593 return VERR_CPUM_RAISE_GP_0;
1594 }
1595#endif
1596 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1597 return VINF_SUCCESS;
1598}
1599
1600
1601/** @callback_method_impl{FNCPUMRDMSR} */
1602static DECLCALLBACK(int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1603{
1604 /** @todo implement I/O mwait wakeup. */
1605 *puValue = 0;
1606 return VINF_SUCCESS;
1607}
1608
1609
1610/** @callback_method_impl{FNCPUMWRMSR} */
1611static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1612{
1613 /** @todo implement I/O mwait wakeup. */
1614 return VINF_SUCCESS;
1615}
1616
1617
1618/** @callback_method_impl{FNCPUMRDMSR} */
1619static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1620{
1621 /** @todo implement last branch records. */
1622 *puValue = 0;
1623 return VINF_SUCCESS;
1624}
1625
1626
1627/** @callback_method_impl{FNCPUMWRMSR} */
1628static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1629{
1630 /** @todo implement last branch records. */
1631 return VINF_SUCCESS;
1632}
1633
1634
1635/** @callback_method_impl{FNCPUMRDMSR} */
1636static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1637{
1638 /** @todo implement last branch records. */
1639 *puValue = 0;
1640 return VINF_SUCCESS;
1641}
1642
1643
1644/** @callback_method_impl{FNCPUMWRMSR} */
1645static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1646{
1647 /** @todo implement last branch records. */
1648 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1649 * if the rest of the bits are zero. Automatic sign extending?
1650 * Investigate! */
1651 if (!X86_IS_CANONICAL(uValue))
1652 {
1653 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1654 return VERR_CPUM_RAISE_GP_0;
1655 }
1656 return VINF_SUCCESS;
1657}
1658
1659
1660/** @callback_method_impl{FNCPUMRDMSR} */
1661static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1662{
1663 /** @todo implement last branch records. */
1664 *puValue = 0;
1665 return VINF_SUCCESS;
1666}
1667
1668
1669/** @callback_method_impl{FNCPUMWRMSR} */
1670static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1671{
1672 /** @todo implement last branch records. */
1673 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1674 * if the rest of the bits are zero. Automatic sign extending?
1675 * Investigate! */
1676 if (!X86_IS_CANONICAL(uValue))
1677 {
1678 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1679 return VERR_CPUM_RAISE_GP_0;
1680 }
1681 return VINF_SUCCESS;
1682}
1683
1684
1685/** @callback_method_impl{FNCPUMRDMSR} */
1686static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1687{
1688 /** @todo implement last branch records. */
1689 *puValue = 0;
1690 return VINF_SUCCESS;
1691}
1692
1693
1694/** @callback_method_impl{FNCPUMWRMSR} */
1695static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1696{
1697 /** @todo implement last branch records. */
1698 return VINF_SUCCESS;
1699}
1700
1701
1702/** @callback_method_impl{FNCPUMRDMSR} */
1703static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1704{
1705 *puValue = pRange->uValue;
1706 return VINF_SUCCESS;
1707}
1708
1709
1710/** @callback_method_impl{FNCPUMWRMSR} */
1711static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1712{
1713 return VINF_SUCCESS;
1714}
1715
1716
1717/** @callback_method_impl{FNCPUMRDMSR} */
1718static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1719{
1720 *puValue = pRange->uValue;
1721 return VINF_SUCCESS;
1722}
1723
1724
1725/** @callback_method_impl{FNCPUMWRMSR} */
1726static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1727{
1728 return VINF_SUCCESS;
1729}
1730
1731
1732/** @callback_method_impl{FNCPUMRDMSR} */
1733static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1734{
1735 *puValue = pRange->uValue;
1736 return VINF_SUCCESS;
1737}
1738
1739
1740/** @callback_method_impl{FNCPUMWRMSR} */
1741static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1742{
1743 return VINF_SUCCESS;
1744}
1745
1746
1747/** @callback_method_impl{FNCPUMRDMSR} */
1748static DECLCALLBACK(int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1749{
1750 /** @todo machine check. */
1751 *puValue = pRange->uValue;
1752 return VINF_SUCCESS;
1753}
1754
1755
1756/** @callback_method_impl{FNCPUMWRMSR} */
1757static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1758{
1759 /** @todo machine check. */
1760 return VINF_SUCCESS;
1761}
1762
1763
1764/** @callback_method_impl{FNCPUMRDMSR} */
1765static DECLCALLBACK(int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1766{
1767 *puValue = 0;
1768 return VINF_SUCCESS;
1769}
1770
1771
1772/** @callback_method_impl{FNCPUMWRMSR} */
1773static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1774{
1775 return VINF_SUCCESS;
1776}
1777
1778
1779/** @callback_method_impl{FNCPUMRDMSR} */
1780static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1781{
1782 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1783 AssertRC(rc);
1784 return VINF_SUCCESS;
1785}
1786
1787
1788/** @callback_method_impl{FNCPUMWRMSR} */
1789static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1790{
1791 /* This CRx interface differs from the MOV CRx, GReg interface in that
1792 #GP(0) isn't raised if unsupported bits are written to. Instead they
1793 are simply ignored and masked off. (Pentium M Dothan) */
1794 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1795 * any, gain. */
1796 return VINF_SUCCESS;
1797}
1798
1799
1800/** @callback_method_impl{FNCPUMRDMSR} */
1801static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1802{
1803 /** @todo implement CPUID masking. */
1804 *puValue = UINT64_MAX;
1805 return VINF_SUCCESS;
1806}
1807
1808
1809/** @callback_method_impl{FNCPUMWRMSR} */
1810static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1811{
1812 /** @todo implement CPUID masking. */
1813 return VINF_SUCCESS;
1814}
1815
1816
1817/** @callback_method_impl{FNCPUMRDMSR} */
1818static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1819{
1820 /** @todo implement CPUID masking. */
1821 return VINF_SUCCESS;
1822}
1823
1824
1825/** @callback_method_impl{FNCPUMWRMSR} */
1826static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1827{
1828 /** @todo implement CPUID masking. */
1829 return VINF_SUCCESS;
1830}
1831
1832
1833
1834/** @callback_method_impl{FNCPUMRDMSR} */
1835static DECLCALLBACK(int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1836{
1837 /** @todo implement CPUID masking. */
1838 *puValue = UINT64_MAX;
1839 return VINF_SUCCESS;
1840}
1841
1842
1843/** @callback_method_impl{FNCPUMWRMSR} */
1844static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1845{
1846 /** @todo implement CPUID masking. */
1847 return VINF_SUCCESS;
1848}
1849
1850
1851
1852/** @callback_method_impl{FNCPUMRDMSR} */
1853static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1854{
1855 /** @todo implement AES-NI. */
1856 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
1857 return VINF_SUCCESS;
1858}
1859
1860
1861/** @callback_method_impl{FNCPUMWRMSR} */
1862static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1863{
1864 /** @todo implement AES-NI. */
1865 return VERR_CPUM_RAISE_GP_0;
1866}
1867
1868
1869/** @callback_method_impl{FNCPUMRDMSR} */
1870static DECLCALLBACK(int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1871{
1872 /** @todo implement intel C states. */
1873 *puValue = pRange->uValue;
1874 return VINF_SUCCESS;
1875}
1876
1877
1878/** @callback_method_impl{FNCPUMWRMSR} */
1879static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1880{
1881 /** @todo implement intel C states. */
1882 return VINF_SUCCESS;
1883}
1884
1885
1886/** @callback_method_impl{FNCPUMRDMSR} */
1887static DECLCALLBACK(int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1888{
1889 /** @todo implement last-branch-records. */
1890 *puValue = 0;
1891 return VINF_SUCCESS;
1892}
1893
1894
1895/** @callback_method_impl{FNCPUMWRMSR} */
1896static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1897{
1898 /** @todo implement last-branch-records. */
1899 return VINF_SUCCESS;
1900}
1901
1902
1903/** @callback_method_impl{FNCPUMRDMSR} */
1904static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1905{
1906 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
1907 *puValue = 0;
1908 return VINF_SUCCESS;
1909}
1910
1911
1912/** @callback_method_impl{FNCPUMWRMSR} */
1913static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1914{
1915 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
1916 return VINF_SUCCESS;
1917}
1918
1919
1920/** @callback_method_impl{FNCPUMRDMSR} */
1921static DECLCALLBACK(int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1922{
1923 /** @todo implement memory VLW? */
1924 *puValue = pRange->uValue;
1925 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
1926 AAJ49/AAK51/????, which documents the inversion of this bit. The
1927 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
1928 that correct things. Some guesses at the other bits:
1929 bit 2 = INTR
1930 bit 4 = SMI
1931 bit 5 = INIT
1932 bit 6 = NMI */
1933 return VINF_SUCCESS;
1934}
1935
1936
1937/** @callback_method_impl{FNCPUMRDMSR} */
1938static DECLCALLBACK(int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1939{
1940 /** @todo intel power management */
1941 *puValue = 0;
1942 return VINF_SUCCESS;
1943}
1944
1945
1946/** @callback_method_impl{FNCPUMWRMSR} */
1947static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1948{
1949 /** @todo intel power management */
1950 return VINF_SUCCESS;
1951}
1952
1953
1954/** @callback_method_impl{FNCPUMRDMSR} */
1955static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1956{
1957 /** @todo intel performance counters. */
1958 *puValue = 0;
1959 return VINF_SUCCESS;
1960}
1961
1962
1963/** @callback_method_impl{FNCPUMWRMSR} */
1964static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1965{
1966 /** @todo intel performance counters. */
1967 return VINF_SUCCESS;
1968}
1969
1970
1971/** @callback_method_impl{FNCPUMRDMSR} */
1972static DECLCALLBACK(int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1973{
1974 /** @todo intel performance counters. */
1975 *puValue = 0;
1976 return VINF_SUCCESS;
1977}
1978
1979
1980/** @callback_method_impl{FNCPUMWRMSR} */
1981static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1982{
1983 /** @todo intel performance counters. */
1984 return VINF_SUCCESS;
1985}
1986
1987
1988/** @callback_method_impl{FNCPUMRDMSR} */
1989static DECLCALLBACK(int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1990{
1991 /** @todo intel power management. */
1992 *puValue = 0;
1993 return VINF_SUCCESS;
1994}
1995
1996
1997/** @callback_method_impl{FNCPUMRDMSR} */
1998static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1999{
2000 /** @todo intel power management. */
2001 *puValue = 0;
2002 return VINF_SUCCESS;
2003}
2004
2005
2006/** @callback_method_impl{FNCPUMRDMSR} */
2007static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2008{
2009 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2010 *puValue = 0;
2011 return VINF_SUCCESS;
2012}
2013
2014
2015/** @callback_method_impl{FNCPUMWRMSR} */
2016static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2017{
2018 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2019 return VINF_SUCCESS;
2020}
2021
2022
2023/** @callback_method_impl{FNCPUMRDMSR} */
2024static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2025{
2026 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2027 *puValue = 0;
2028 return VINF_SUCCESS;
2029}
2030
2031
2032/** @callback_method_impl{FNCPUMWRMSR} */
2033static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2034{
2035 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2036 return VINF_SUCCESS;
2037}
2038
2039
2040/** @callback_method_impl{FNCPUMRDMSR} */
2041static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2042{
2043 /** @todo intel RAPL. */
2044 *puValue = pRange->uValue;
2045 return VINF_SUCCESS;
2046}
2047
2048
2049/** @callback_method_impl{FNCPUMRDMSR} */
2050static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2051{
2052 /** @todo intel power management. */
2053 *puValue = 0;
2054 return VINF_SUCCESS;
2055}
2056
2057
2058/** @callback_method_impl{FNCPUMWRMSR} */
2059static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2060{
2061 /** @todo intel power management. */
2062 return VINF_SUCCESS;
2063}
2064
2065
2066/** @callback_method_impl{FNCPUMRDMSR} */
2067static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2068{
2069 /** @todo intel power management. */
2070 *puValue = 0;
2071 return VINF_SUCCESS;
2072}
2073
2074
2075/** @callback_method_impl{FNCPUMRDMSR} */
2076static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2077{
2078 /** @todo intel RAPL. */
2079 *puValue = 0;
2080 return VINF_SUCCESS;
2081}
2082
2083
2084/** @callback_method_impl{FNCPUMWRMSR} */
2085static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2086{
2087 /** @todo intel RAPL. */
2088 return VINF_SUCCESS;
2089}
2090
2091
2092/** @callback_method_impl{FNCPUMRDMSR} */
2093static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2094{
2095 /** @todo intel power management. */
2096 *puValue = 0;
2097 return VINF_SUCCESS;
2098}
2099
2100
2101/** @callback_method_impl{FNCPUMRDMSR} */
2102static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2103{
2104 /** @todo intel power management. */
2105 *puValue = 0;
2106 return VINF_SUCCESS;
2107}
2108
2109
2110/** @callback_method_impl{FNCPUMRDMSR} */
2111static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2112{
2113 /** @todo intel power management. */
2114 *puValue = 0;
2115 return VINF_SUCCESS;
2116}
2117
2118
2119/** @callback_method_impl{FNCPUMRDMSR} */
2120static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2121{
2122 /** @todo intel RAPL. */
2123 *puValue = 0;
2124 return VINF_SUCCESS;
2125}
2126
2127
2128/** @callback_method_impl{FNCPUMWRMSR} */
2129static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2130{
2131 /** @todo intel RAPL. */
2132 return VINF_SUCCESS;
2133}
2134
2135
2136/** @callback_method_impl{FNCPUMRDMSR} */
2137static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2138{
2139 /** @todo intel power management. */
2140 *puValue = 0;
2141 return VINF_SUCCESS;
2142}
2143
2144
2145/** @callback_method_impl{FNCPUMRDMSR} */
2146static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2147{
2148 /** @todo intel power management. */
2149 *puValue = 0;
2150 return VINF_SUCCESS;
2151}
2152
2153
2154/** @callback_method_impl{FNCPUMRDMSR} */
2155static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2156{
2157 /** @todo intel power management. */
2158 *puValue = 0;
2159 return VINF_SUCCESS;
2160}
2161
2162
2163/** @callback_method_impl{FNCPUMRDMSR} */
2164static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2165{
2166 /** @todo intel RAPL. */
2167 *puValue = 0;
2168 return VINF_SUCCESS;
2169}
2170
2171
2172/** @callback_method_impl{FNCPUMWRMSR} */
2173static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2174{
2175 /** @todo intel RAPL. */
2176 return VINF_SUCCESS;
2177}
2178
2179
2180/** @callback_method_impl{FNCPUMRDMSR} */
2181static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2182{
2183 /** @todo intel power management. */
2184 *puValue = 0;
2185 return VINF_SUCCESS;
2186}
2187
2188
2189/** @callback_method_impl{FNCPUMRDMSR} */
2190static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2191{
2192 /** @todo intel RAPL. */
2193 *puValue = 0;
2194 return VINF_SUCCESS;
2195}
2196
2197
2198/** @callback_method_impl{FNCPUMWRMSR} */
2199static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2200{
2201 /** @todo intel RAPL. */
2202 return VINF_SUCCESS;
2203}
2204
2205
2206/** @callback_method_impl{FNCPUMRDMSR} */
2207static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2208{
2209 /** @todo intel power management. */
2210 *puValue = 0;
2211 return VINF_SUCCESS;
2212}
2213
2214
2215/** @callback_method_impl{FNCPUMRDMSR} */
2216static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2217{
2218 /** @todo intel RAPL. */
2219 *puValue = 0;
2220 return VINF_SUCCESS;
2221}
2222
2223
2224/** @callback_method_impl{FNCPUMWRMSR} */
2225static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2226{
2227 /** @todo intel RAPL. */
2228 return VINF_SUCCESS;
2229}
2230
2231
2232/** @callback_method_impl{FNCPUMRDMSR} */
2233static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2234{
2235 /** @todo intel power management. */
2236 *puValue = 0;
2237 return VINF_SUCCESS;
2238}
2239
2240
2241/** @callback_method_impl{FNCPUMRDMSR} */
2242static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2243{
2244 /** @todo intel RAPL. */
2245 *puValue = 0;
2246 return VINF_SUCCESS;
2247}
2248
2249
2250/** @callback_method_impl{FNCPUMWRMSR} */
2251static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2252{
2253 /** @todo intel RAPL. */
2254 return VINF_SUCCESS;
2255}
2256
2257
2258/** @callback_method_impl{FNCPUMRDMSR} */
2259static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2260{
2261 /** @todo intel power management. */
2262 *puValue = pRange->uValue;
2263 return VINF_SUCCESS;
2264}
2265
2266
2267/** @callback_method_impl{FNCPUMRDMSR} */
2268static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2269{
2270 /** @todo intel power management. */
2271 *puValue = pRange->uValue;
2272 return VINF_SUCCESS;
2273}
2274
2275
2276/** @callback_method_impl{FNCPUMRDMSR} */
2277static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2278{
2279 /** @todo intel power management. */
2280 *puValue = pRange->uValue;
2281 return VINF_SUCCESS;
2282}
2283
2284
2285/** @callback_method_impl{FNCPUMRDMSR} */
2286static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2287{
2288 /** @todo intel power management. */
2289 *puValue = 0;
2290 return VINF_SUCCESS;
2291}
2292
2293
2294/** @callback_method_impl{FNCPUMWRMSR} */
2295static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2296{
2297 /** @todo intel power management. */
2298 return VINF_SUCCESS;
2299}
2300
2301
2302/** @callback_method_impl{FNCPUMRDMSR} */
2303static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2304{
2305 /** @todo intel power management. */
2306 *puValue = 0;
2307 return VINF_SUCCESS;
2308}
2309
2310
2311/** @callback_method_impl{FNCPUMWRMSR} */
2312static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2313{
2314 /** @todo intel power management. */
2315 return VINF_SUCCESS;
2316}
2317
2318
2319/** @callback_method_impl{FNCPUMRDMSR} */
2320static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2321{
2322 /** @todo uncore msrs. */
2323 *puValue = 0;
2324 return VINF_SUCCESS;
2325}
2326
2327
2328/** @callback_method_impl{FNCPUMWRMSR} */
2329static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2330{
2331 /** @todo uncore msrs. */
2332 return VINF_SUCCESS;
2333}
2334
2335
2336/** @callback_method_impl{FNCPUMRDMSR} */
2337static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2338{
2339 /** @todo uncore msrs. */
2340 *puValue = 0;
2341 return VINF_SUCCESS;
2342}
2343
2344
2345/** @callback_method_impl{FNCPUMWRMSR} */
2346static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2347{
2348 /** @todo uncore msrs. */
2349 return VINF_SUCCESS;
2350}
2351
2352
2353/** @callback_method_impl{FNCPUMRDMSR} */
2354static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2355{
2356 /** @todo uncore msrs. */
2357 *puValue = 0;
2358 return VINF_SUCCESS;
2359}
2360
2361
2362/** @callback_method_impl{FNCPUMWRMSR} */
2363static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2364{
2365 /** @todo uncore msrs. */
2366 return VINF_SUCCESS;
2367}
2368
2369
2370/** @callback_method_impl{FNCPUMRDMSR} */
2371static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2372{
2373 /** @todo uncore msrs. */
2374 *puValue = 0;
2375 return VINF_SUCCESS;
2376}
2377
2378
2379/** @callback_method_impl{FNCPUMWRMSR} */
2380static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2381{
2382 /** @todo uncore msrs. */
2383 return VINF_SUCCESS;
2384}
2385
2386
2387/** @callback_method_impl{FNCPUMRDMSR} */
2388static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2389{
2390 /** @todo uncore msrs. */
2391 *puValue = 0;
2392 return VINF_SUCCESS;
2393}
2394
2395
2396/** @callback_method_impl{FNCPUMWRMSR} */
2397static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2398{
2399 /** @todo uncore msrs. */
2400 return VINF_SUCCESS;
2401}
2402
2403
2404/** @callback_method_impl{FNCPUMRDMSR} */
2405static DECLCALLBACK(int) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2406{
2407 /** @todo uncore msrs. */
2408 *puValue = 0;
2409 return VINF_SUCCESS;
2410}
2411
2412
2413/** @callback_method_impl{FNCPUMRDMSR} */
2414static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2415{
2416 /** @todo uncore msrs. */
2417 *puValue = 0;
2418 return VINF_SUCCESS;
2419}
2420
2421
2422/** @callback_method_impl{FNCPUMWRMSR} */
2423static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2424{
2425 /** @todo uncore msrs. */
2426 return VINF_SUCCESS;
2427}
2428
2429
2430/** @callback_method_impl{FNCPUMRDMSR} */
2431static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2432{
2433 /** @todo uncore msrs. */
2434 *puValue = 0;
2435 return VINF_SUCCESS;
2436}
2437
2438
2439/** @callback_method_impl{FNCPUMWRMSR} */
2440static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2441{
2442 /** @todo uncore msrs. */
2443 return VINF_SUCCESS;
2444}
2445
2446
2447/** @callback_method_impl{FNCPUMRDMSR} */
2448static DECLCALLBACK(int) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2449{
2450 /** @todo implement enhanced multi thread termal monitoring? */
2451 *puValue = pRange->uValue;
2452 return VINF_SUCCESS;
2453}
2454
2455
2456/** @callback_method_impl{FNCPUMWRMSR} */
2457static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2458{
2459 /** @todo implement enhanced multi thread termal monitoring? */
2460 return VINF_SUCCESS;
2461}
2462
2463
2464/** @callback_method_impl{FNCPUMRDMSR} */
2465static DECLCALLBACK(int) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2466{
2467 /** @todo SMM & C-states? */
2468 *puValue = 0;
2469 return VINF_SUCCESS;
2470}
2471
2472
2473/** @callback_method_impl{FNCPUMWRMSR} */
2474static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2475{
2476 /** @todo SMM & C-states? */
2477 return VINF_SUCCESS;
2478}
2479
2480
2481/** @callback_method_impl{FNCPUMRDMSR} */
2482static DECLCALLBACK(int) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2483{
2484 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2485 *puValue = 0;
2486 return VINF_SUCCESS;
2487}
2488
2489
2490/** @callback_method_impl{FNCPUMWRMSR} */
2491static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2492{
2493 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2494 return VINF_SUCCESS;
2495}
2496
2497
2498/** @callback_method_impl{FNCPUMRDMSR} */
2499static DECLCALLBACK(int) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2500{
2501 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2502 *puValue = 0;
2503 return VINF_SUCCESS;
2504}
2505
2506
2507/** @callback_method_impl{FNCPUMWRMSR} */
2508static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2509{
2510 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2511 return VINF_SUCCESS;
2512}
2513
2514
2515/** @callback_method_impl{FNCPUMRDMSR} */
2516static DECLCALLBACK(int) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2517{
2518 /** @todo Core2+ platform environment control interface control register? */
2519 *puValue = 0;
2520 return VINF_SUCCESS;
2521}
2522
2523
2524/** @callback_method_impl{FNCPUMWRMSR} */
2525static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2526{
2527 /** @todo Core2+ platform environment control interface control register? */
2528 return VINF_SUCCESS;
2529}
2530
2531
2532
2533/*
2534 * Multiple vendor P6 MSRs.
2535 * Multiple vendor P6 MSRs.
2536 * Multiple vendor P6 MSRs.
2537 *
2538 * These MSRs were introduced with the P6 but not elevated to architectural
2539 * MSRs, despite other vendors implementing them.
2540 */
2541
2542
2543/** @callback_method_impl{FNCPUMRDMSR} */
2544static DECLCALLBACK(int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2545{
2546 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2547 if I read the docs correctly, thus the need for separate functions. */
2548 /** @todo implement last branch records. */
2549 *puValue = 0;
2550 return VINF_SUCCESS;
2551}
2552
2553
2554/** @callback_method_impl{FNCPUMRDMSR} */
2555static DECLCALLBACK(int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2556{
2557 /** @todo implement last branch records. */
2558 *puValue = 0;
2559 return VINF_SUCCESS;
2560}
2561
2562
2563/** @callback_method_impl{FNCPUMRDMSR} */
2564static DECLCALLBACK(int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2565{
2566 /** @todo implement last exception records. */
2567 *puValue = 0;
2568 return VINF_SUCCESS;
2569}
2570
2571
2572/** @callback_method_impl{FNCPUMWRMSR} */
2573static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2574{
2575 /** @todo implement last exception records. */
2576 return VINF_SUCCESS;
2577}
2578
2579
2580/** @callback_method_impl{FNCPUMRDMSR} */
2581static DECLCALLBACK(int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2582{
2583 /** @todo implement last exception records. */
2584 *puValue = 0;
2585 return VINF_SUCCESS;
2586}
2587
2588
2589/** @callback_method_impl{FNCPUMWRMSR} */
2590static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2591{
2592 /** @todo implement last exception records. */
2593 return VINF_SUCCESS;
2594}
2595
2596
2597
2598/*
2599 * AMD specific
2600 * AMD specific
2601 * AMD specific
2602 */
2603
2604
2605/** @callback_method_impl{FNCPUMRDMSR} */
2606static DECLCALLBACK(int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2607{
2608 /** @todo Implement TscRateMsr */
2609 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2610 return VINF_SUCCESS;
2611}
2612
2613
2614/** @callback_method_impl{FNCPUMWRMSR} */
2615static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2616{
2617 /** @todo Implement TscRateMsr */
2618 return VINF_SUCCESS;
2619}
2620
2621
2622/** @callback_method_impl{FNCPUMRDMSR} */
2623static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2624{
2625 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2626 /* Note: Only listes in BKDG for Family 15H. */
2627 *puValue = 0;
2628 return VINF_SUCCESS;
2629}
2630
2631
2632/** @callback_method_impl{FNCPUMWRMSR} */
2633static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2634{
2635 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2636 return VINF_SUCCESS;
2637}
2638
2639
2640/** @callback_method_impl{FNCPUMRDMSR} */
2641static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2642{
2643 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2644 /* Note: Only listes in BKDG for Family 15H. */
2645 *puValue = 0;
2646 return VINF_SUCCESS;
2647}
2648
2649
2650/** @callback_method_impl{FNCPUMWRMSR} */
2651static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2652{
2653 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2654 return VINF_SUCCESS;
2655}
2656
2657
2658/** @callback_method_impl{FNCPUMRDMSR} */
2659static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2660{
2661 /** @todo machine check. */
2662 *puValue = 0;
2663 return VINF_SUCCESS;
2664}
2665
2666
2667/** @callback_method_impl{FNCPUMWRMSR} */
2668static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2669{
2670 /** @todo machine check. */
2671 return VINF_SUCCESS;
2672}
2673
2674
2675/** @callback_method_impl{FNCPUMRDMSR} */
2676static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2677{
2678 /** @todo AMD performance events. */
2679 *puValue = 0;
2680 return VINF_SUCCESS;
2681}
2682
2683
2684/** @callback_method_impl{FNCPUMWRMSR} */
2685static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2686{
2687 /** @todo AMD performance events. */
2688 return VINF_SUCCESS;
2689}
2690
2691
2692/** @callback_method_impl{FNCPUMRDMSR} */
2693static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2694{
2695 /** @todo AMD performance events. */
2696 *puValue = 0;
2697 return VINF_SUCCESS;
2698}
2699
2700
2701/** @callback_method_impl{FNCPUMWRMSR} */
2702static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2703{
2704 /** @todo AMD performance events. */
2705 return VINF_SUCCESS;
2706}
2707
2708
2709/** @callback_method_impl{FNCPUMRDMSR} */
2710static DECLCALLBACK(int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2711{
2712 /** @todo AMD SYS_CFG */
2713 *puValue = pRange->uValue;
2714 return VINF_SUCCESS;
2715}
2716
2717
2718/** @callback_method_impl{FNCPUMWRMSR} */
2719static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2720{
2721 /** @todo AMD SYS_CFG */
2722 return VINF_SUCCESS;
2723}
2724
2725
2726/** @callback_method_impl{FNCPUMRDMSR} */
2727static DECLCALLBACK(int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2728{
2729 /** @todo AMD HW_CFG */
2730 *puValue = 0;
2731 return VINF_SUCCESS;
2732}
2733
2734
2735/** @callback_method_impl{FNCPUMWRMSR} */
2736static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2737{
2738 /** @todo AMD HW_CFG */
2739 return VINF_SUCCESS;
2740}
2741
2742
2743/** @callback_method_impl{FNCPUMRDMSR} */
2744static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2745{
2746 /** @todo AMD IorrMask/IorrBase */
2747 *puValue = 0;
2748 return VINF_SUCCESS;
2749}
2750
2751
2752/** @callback_method_impl{FNCPUMWRMSR} */
2753static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2754{
2755 /** @todo AMD IorrMask/IorrBase */
2756 return VINF_SUCCESS;
2757}
2758
2759
2760/** @callback_method_impl{FNCPUMRDMSR} */
2761static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2762{
2763 /** @todo AMD IorrMask/IorrBase */
2764 *puValue = 0;
2765 return VINF_SUCCESS;
2766}
2767
2768
2769/** @callback_method_impl{FNCPUMWRMSR} */
2770static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2771{
2772 /** @todo AMD IorrMask/IorrBase */
2773 return VINF_SUCCESS;
2774}
2775
2776
2777/** @callback_method_impl{FNCPUMRDMSR} */
2778static DECLCALLBACK(int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2779{
2780 *puValue = 0;
2781 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2782 * for TOPMEM2. */
2783 //if (pRange->uValue == 0)
2784 // *puValue = _4G - RamHoleSize;
2785 return VINF_SUCCESS;
2786}
2787
2788
2789/** @callback_method_impl{FNCPUMWRMSR} */
2790static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2791{
2792 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2793 return VINF_SUCCESS;
2794}
2795
2796
2797/** @callback_method_impl{FNCPUMRDMSR} */
2798static DECLCALLBACK(int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2799{
2800 /** @todo AMD NB_CFG1 */
2801 *puValue = 0;
2802 return VINF_SUCCESS;
2803}
2804
2805
2806/** @callback_method_impl{FNCPUMWRMSR} */
2807static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2808{
2809 /** @todo AMD NB_CFG1 */
2810 return VINF_SUCCESS;
2811}
2812
2813
2814/** @callback_method_impl{FNCPUMRDMSR} */
2815static DECLCALLBACK(int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2816{
2817 /** @todo machine check. */
2818 *puValue = 0;
2819 return VINF_SUCCESS;
2820}
2821
2822
2823/** @callback_method_impl{FNCPUMWRMSR} */
2824static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2825{
2826 /** @todo machine check. */
2827 return VINF_SUCCESS;
2828}
2829
2830
2831/** @callback_method_impl{FNCPUMRDMSR} */
2832static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2833{
2834 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0);
2835 if (pLeaf)
2836 {
2837 if (!(pRange->uValue & 1))
2838 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2839 else
2840 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2841 }
2842 else
2843 *puValue = 0;
2844 return VINF_SUCCESS;
2845}
2846
2847
2848/** @callback_method_impl{FNCPUMWRMSR} */
2849static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2850{
2851 /** @todo Remember guest programmed CPU name. */
2852 return VINF_SUCCESS;
2853}
2854
2855
2856/** @callback_method_impl{FNCPUMRDMSR} */
2857static DECLCALLBACK(int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2858{
2859 /** @todo AMD HTC. */
2860 *puValue = pRange->uValue;
2861 return VINF_SUCCESS;
2862}
2863
2864
2865/** @callback_method_impl{FNCPUMWRMSR} */
2866static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2867{
2868 /** @todo AMD HTC. */
2869 return VINF_SUCCESS;
2870}
2871
2872
2873/** @callback_method_impl{FNCPUMRDMSR} */
2874static DECLCALLBACK(int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2875{
2876 /** @todo AMD STC. */
2877 *puValue = 0;
2878 return VINF_SUCCESS;
2879}
2880
2881
2882/** @callback_method_impl{FNCPUMWRMSR} */
2883static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2884{
2885 /** @todo AMD STC. */
2886 return VINF_SUCCESS;
2887}
2888
2889
2890/** @callback_method_impl{FNCPUMRDMSR} */
2891static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2892{
2893 /** @todo AMD FIDVID_CTL. */
2894 *puValue = pRange->uValue;
2895 return VINF_SUCCESS;
2896}
2897
2898
2899/** @callback_method_impl{FNCPUMWRMSR} */
2900static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2901{
2902 /** @todo AMD FIDVID_CTL. */
2903 return VINF_SUCCESS;
2904}
2905
2906
2907/** @callback_method_impl{FNCPUMRDMSR} */
2908static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2909{
2910 /** @todo AMD FIDVID_STATUS. */
2911 *puValue = pRange->uValue;
2912 return VINF_SUCCESS;
2913}
2914
2915
2916/** @callback_method_impl{FNCPUMRDMSR} */
2917static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2918{
2919 /** @todo AMD MC. */
2920 *puValue = 0;
2921 return VINF_SUCCESS;
2922}
2923
2924
2925/** @callback_method_impl{FNCPUMWRMSR} */
2926static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2927{
2928 /** @todo AMD MC. */
2929 return VINF_SUCCESS;
2930}
2931
2932
2933/** @callback_method_impl{FNCPUMRDMSR} */
2934static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2935{
2936 /** @todo AMD SMM/SMI and I/O trap. */
2937 *puValue = 0;
2938 return VINF_SUCCESS;
2939}
2940
2941
2942/** @callback_method_impl{FNCPUMWRMSR} */
2943static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2944{
2945 /** @todo AMD SMM/SMI and I/O trap. */
2946 return VINF_SUCCESS;
2947}
2948
2949
2950/** @callback_method_impl{FNCPUMRDMSR} */
2951static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2952{
2953 /** @todo AMD SMM/SMI and I/O trap. */
2954 *puValue = 0;
2955 return VINF_SUCCESS;
2956}
2957
2958
2959/** @callback_method_impl{FNCPUMWRMSR} */
2960static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2961{
2962 /** @todo AMD SMM/SMI and I/O trap. */
2963 return VINF_SUCCESS;
2964}
2965
2966
2967/** @callback_method_impl{FNCPUMRDMSR} */
2968static DECLCALLBACK(int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2969{
2970 /** @todo Interrupt pending message. */
2971 *puValue = 0;
2972 return VINF_SUCCESS;
2973}
2974
2975
2976/** @callback_method_impl{FNCPUMWRMSR} */
2977static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2978{
2979 /** @todo Interrupt pending message. */
2980 return VINF_SUCCESS;
2981}
2982
2983
2984/** @callback_method_impl{FNCPUMRDMSR} */
2985static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2986{
2987 /** @todo AMD SMM/SMI and trigger I/O cycle. */
2988 *puValue = 0;
2989 return VINF_SUCCESS;
2990}
2991
2992
2993/** @callback_method_impl{FNCPUMWRMSR} */
2994static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2995{
2996 /** @todo AMD SMM/SMI and trigger I/O cycle. */
2997 return VINF_SUCCESS;
2998}
2999
3000
3001/** @callback_method_impl{FNCPUMRDMSR} */
3002static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3003{
3004 /** @todo AMD MMIO Configuration base address. */
3005 *puValue = 0;
3006 return VINF_SUCCESS;
3007}
3008
3009
3010/** @callback_method_impl{FNCPUMWRMSR} */
3011static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3012{
3013 /** @todo AMD MMIO Configuration base address. */
3014 return VINF_SUCCESS;
3015}
3016
3017
3018/** @callback_method_impl{FNCPUMRDMSR} */
3019static DECLCALLBACK(int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3020{
3021 /** @todo AMD 0xc0010059. */
3022 *puValue = 0;
3023 return VINF_SUCCESS;
3024}
3025
3026
3027/** @callback_method_impl{FNCPUMWRMSR} */
3028static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3029{
3030 /** @todo AMD 0xc0010059. */
3031 return VINF_SUCCESS;
3032}
3033
3034
3035/** @callback_method_impl{FNCPUMRDMSR} */
3036static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3037{
3038 /** @todo AMD P-states. */
3039 *puValue = pRange->uValue;
3040 return VINF_SUCCESS;
3041}
3042
3043
3044/** @callback_method_impl{FNCPUMRDMSR} */
3045static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3046{
3047 /** @todo AMD P-states. */
3048 *puValue = pRange->uValue;
3049 return VINF_SUCCESS;
3050}
3051
3052
3053/** @callback_method_impl{FNCPUMWRMSR} */
3054static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3055{
3056 /** @todo AMD P-states. */
3057 return VINF_SUCCESS;
3058}
3059
3060
3061/** @callback_method_impl{FNCPUMRDMSR} */
3062static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3063{
3064 /** @todo AMD P-states. */
3065 *puValue = pRange->uValue;
3066 return VINF_SUCCESS;
3067}
3068
3069
3070/** @callback_method_impl{FNCPUMWRMSR} */
3071static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3072{
3073 /** @todo AMD P-states. */
3074 return VINF_SUCCESS;
3075}
3076
3077
3078/** @callback_method_impl{FNCPUMRDMSR} */
3079static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3080{
3081 /** @todo AMD P-states. */
3082 *puValue = pRange->uValue;
3083 return VINF_SUCCESS;
3084}
3085
3086
3087/** @callback_method_impl{FNCPUMWRMSR} */
3088static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3089{
3090 /** @todo AMD P-states. */
3091 return VINF_SUCCESS;
3092}
3093
3094
3095/** @callback_method_impl{FNCPUMRDMSR} */
3096static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3097{
3098 /** @todo AMD P-states. */
3099 *puValue = pRange->uValue;
3100 return VINF_SUCCESS;
3101}
3102
3103
3104/** @callback_method_impl{FNCPUMWRMSR} */
3105static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3106{
3107 /** @todo AMD P-states. */
3108 return VINF_SUCCESS;
3109}
3110
3111
3112/** @callback_method_impl{FNCPUMRDMSR} */
3113static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3114{
3115 /** @todo AMD P-states. */
3116 *puValue = pRange->uValue;
3117 return VINF_SUCCESS;
3118}
3119
3120
3121/** @callback_method_impl{FNCPUMWRMSR} */
3122static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3123{
3124 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3125 /** @todo AMD P-states. */
3126 return VINF_SUCCESS;
3127}
3128
3129
3130/** @callback_method_impl{FNCPUMRDMSR} */
3131static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3132{
3133 /** @todo AMD C-states. */
3134 *puValue = 0;
3135 return VINF_SUCCESS;
3136}
3137
3138
3139/** @callback_method_impl{FNCPUMWRMSR} */
3140static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3141{
3142 /** @todo AMD C-states. */
3143 return VINF_SUCCESS;
3144}
3145
3146
3147/** @callback_method_impl{FNCPUMRDMSR} */
3148static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3149{
3150 /** @todo AMD machine checks. */
3151 *puValue = 0;
3152 return VINF_SUCCESS;
3153}
3154
3155
3156/** @callback_method_impl{FNCPUMWRMSR} */
3157static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3158{
3159 /** @todo AMD machine checks. */
3160 return VINF_SUCCESS;
3161}
3162
3163
3164/** @callback_method_impl{FNCPUMRDMSR} */
3165static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3166{
3167 /** @todo AMD SMM. */
3168 *puValue = 0;
3169 return VINF_SUCCESS;
3170}
3171
3172
3173/** @callback_method_impl{FNCPUMWRMSR} */
3174static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3175{
3176 /** @todo AMD SMM. */
3177 return VINF_SUCCESS;
3178}
3179
3180
3181/** @callback_method_impl{FNCPUMRDMSR} */
3182static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3183{
3184 /** @todo AMD SMM. */
3185 *puValue = 0;
3186 return VINF_SUCCESS;
3187}
3188
3189
3190/** @callback_method_impl{FNCPUMWRMSR} */
3191static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3192{
3193 /** @todo AMD SMM. */
3194 return VINF_SUCCESS;
3195}
3196
3197
3198
3199/** @callback_method_impl{FNCPUMRDMSR} */
3200static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3201{
3202 /** @todo AMD SMM. */
3203 *puValue = 0;
3204 return VINF_SUCCESS;
3205}
3206
3207
3208/** @callback_method_impl{FNCPUMWRMSR} */
3209static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3210{
3211 /** @todo AMD SMM. */
3212 return VINF_SUCCESS;
3213}
3214
3215
3216/** @callback_method_impl{FNCPUMRDMSR} */
3217static DECLCALLBACK(int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3218{
3219 /** @todo AMD SVM. */
3220 *puValue = 0;
3221 return VINF_SUCCESS;
3222}
3223
3224
3225/** @callback_method_impl{FNCPUMWRMSR} */
3226static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3227{
3228 /** @todo AMD SVM. */
3229 return VINF_SUCCESS;
3230}
3231
3232
3233/** @callback_method_impl{FNCPUMRDMSR} */
3234static DECLCALLBACK(int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3235{
3236 /** @todo AMD IGNNE\# control. */
3237 *puValue = 0;
3238 return VINF_SUCCESS;
3239}
3240
3241
3242/** @callback_method_impl{FNCPUMWRMSR} */
3243static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3244{
3245 /** @todo AMD IGNNE\# control. */
3246 return VINF_SUCCESS;
3247}
3248
3249
3250/** @callback_method_impl{FNCPUMRDMSR} */
3251static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3252{
3253 /** @todo AMD SMM. */
3254 *puValue = 0;
3255 return VINF_SUCCESS;
3256}
3257
3258
3259/** @callback_method_impl{FNCPUMWRMSR} */
3260static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3261{
3262 /** @todo AMD SMM. */
3263 return VINF_SUCCESS;
3264}
3265
3266
3267/** @callback_method_impl{FNCPUMRDMSR} */
3268static DECLCALLBACK(int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3269{
3270 /** @todo AMD SVM. */
3271 *puValue = 0;
3272 return VINF_SUCCESS;
3273}
3274
3275
3276/** @callback_method_impl{FNCPUMWRMSR} */
3277static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3278{
3279 /** @todo AMD SVM. */
3280 return VINF_SUCCESS;
3281}
3282
3283
3284/** @callback_method_impl{FNCPUMRDMSR} */
3285static DECLCALLBACK(int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3286{
3287 /** @todo AMD SVM. */
3288 *puValue = 0; /* RAZ */
3289 return VINF_SUCCESS;
3290}
3291
3292
3293/** @callback_method_impl{FNCPUMWRMSR} */
3294static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3295{
3296 /** @todo AMD SVM. */
3297 return VINF_SUCCESS;
3298}
3299
3300
3301/** @callback_method_impl{FNCPUMRDMSR} */
3302static DECLCALLBACK(int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3303{
3304 /** @todo AMD SMM. */
3305 *puValue = 0; /* RAZ */
3306 return VINF_SUCCESS;
3307}
3308
3309
3310/** @callback_method_impl{FNCPUMWRMSR} */
3311static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3312{
3313 /** @todo AMD SMM. */
3314 return VINF_SUCCESS;
3315}
3316
3317
3318/** @callback_method_impl{FNCPUMRDMSR} */
3319static DECLCALLBACK(int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3320{
3321 /** @todo AMD SMM/SMI. */
3322 *puValue = 0;
3323 return VINF_SUCCESS;
3324}
3325
3326
3327/** @callback_method_impl{FNCPUMWRMSR} */
3328static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3329{
3330 /** @todo AMD SMM/SMI. */
3331 return VINF_SUCCESS;
3332}
3333
3334
3335/** @callback_method_impl{FNCPUMRDMSR} */
3336static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3337{
3338 /** @todo AMD OS visible workaround. */
3339 *puValue = pRange->uValue;
3340 return VINF_SUCCESS;
3341}
3342
3343
3344/** @callback_method_impl{FNCPUMWRMSR} */
3345static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3346{
3347 /** @todo AMD OS visible workaround. */
3348 return VINF_SUCCESS;
3349}
3350
3351
3352/** @callback_method_impl{FNCPUMRDMSR} */
3353static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3354{
3355 /** @todo AMD OS visible workaround. */
3356 *puValue = 0;
3357 return VINF_SUCCESS;
3358}
3359
3360
3361/** @callback_method_impl{FNCPUMWRMSR} */
3362static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3363{
3364 /** @todo AMD OS visible workaround. */
3365 return VINF_SUCCESS;
3366}
3367
3368
3369/** @callback_method_impl{FNCPUMRDMSR} */
3370static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3371{
3372 /** @todo AMD L2I performance counters. */
3373 *puValue = 0;
3374 return VINF_SUCCESS;
3375}
3376
3377
3378/** @callback_method_impl{FNCPUMWRMSR} */
3379static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3380{
3381 /** @todo AMD L2I performance counters. */
3382 return VINF_SUCCESS;
3383}
3384
3385
3386/** @callback_method_impl{FNCPUMRDMSR} */
3387static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3388{
3389 /** @todo AMD L2I performance counters. */
3390 *puValue = 0;
3391 return VINF_SUCCESS;
3392}
3393
3394
3395/** @callback_method_impl{FNCPUMWRMSR} */
3396static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3397{
3398 /** @todo AMD L2I performance counters. */
3399 return VINF_SUCCESS;
3400}
3401
3402
3403/** @callback_method_impl{FNCPUMRDMSR} */
3404static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3405{
3406 /** @todo AMD Northbridge performance counters. */
3407 *puValue = 0;
3408 return VINF_SUCCESS;
3409}
3410
3411
3412/** @callback_method_impl{FNCPUMWRMSR} */
3413static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3414{
3415 /** @todo AMD Northbridge performance counters. */
3416 return VINF_SUCCESS;
3417}
3418
3419
3420/** @callback_method_impl{FNCPUMRDMSR} */
3421static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3422{
3423 /** @todo AMD Northbridge performance counters. */
3424 *puValue = 0;
3425 return VINF_SUCCESS;
3426}
3427
3428
3429/** @callback_method_impl{FNCPUMWRMSR} */
3430static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3431{
3432 /** @todo AMD Northbridge performance counters. */
3433 return VINF_SUCCESS;
3434}
3435
3436
3437/** @callback_method_impl{FNCPUMRDMSR} */
3438static DECLCALLBACK(int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3439{
3440 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3441 * cpus. Need to be explored and verify K7 presence. */
3442 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3443 *puValue = pRange->uValue;
3444 return VINF_SUCCESS;
3445}
3446
3447
3448/** @callback_method_impl{FNCPUMWRMSR} */
3449static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3450{
3451 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3452 * cpus. Need to be explored and verify K7 presence. */
3453 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3454 return VINF_SUCCESS;
3455}
3456
3457
3458/** @callback_method_impl{FNCPUMRDMSR} */
3459static DECLCALLBACK(int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3460{
3461 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3462 * cpus. Need to be explored and verify K7 presence. */
3463 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3464 * describing EBL_CR_POWERON. */
3465 *puValue = pRange->uValue;
3466 return VINF_SUCCESS;
3467}
3468
3469
3470/** @callback_method_impl{FNCPUMWRMSR} */
3471static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3472{
3473 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3474 * cpus. Need to be explored and verify K7 presence. */
3475 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3476 * describing EBL_CR_POWERON. */
3477 return VINF_SUCCESS;
3478}
3479
3480
3481/** @callback_method_impl{FNCPUMRDMSR} */
3482static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3483{
3484 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0);
3485 if (pLeaf)
3486 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3487 else
3488 *puValue = 0;
3489 return VINF_SUCCESS;
3490}
3491
3492
3493/** @callback_method_impl{FNCPUMWRMSR} */
3494static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3495{
3496 /** @todo Changing CPUID leaf 7/0. */
3497 return VINF_SUCCESS;
3498}
3499
3500
3501/** @callback_method_impl{FNCPUMRDMSR} */
3502static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3503{
3504 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0);
3505 if (pLeaf)
3506 *puValue = pLeaf->uEcx;
3507 else
3508 *puValue = 0;
3509 return VINF_SUCCESS;
3510}
3511
3512
3513/** @callback_method_impl{FNCPUMWRMSR} */
3514static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3515{
3516 /** @todo Changing CPUID leaf 6. */
3517 return VINF_SUCCESS;
3518}
3519
3520
3521/** @callback_method_impl{FNCPUMRDMSR} */
3522static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3523{
3524 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0);
3525 if (pLeaf)
3526 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3527 else
3528 *puValue = 0;
3529 return VINF_SUCCESS;
3530}
3531
3532
3533/** @callback_method_impl{FNCPUMWRMSR} */
3534static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3535{
3536 /** @todo Changing CPUID leaf 0x80000001. */
3537 return VINF_SUCCESS;
3538}
3539
3540
3541/** @callback_method_impl{FNCPUMRDMSR} */
3542static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3543{
3544 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0);
3545 if (pLeaf)
3546 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3547 else
3548 *puValue = 0;
3549 return VINF_SUCCESS;
3550}
3551
3552
3553/** @callback_method_impl{FNCPUMWRMSR} */
3554static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3555{
3556 /** @todo Changing CPUID leaf 0x80000001. */
3557 return VINF_SUCCESS;
3558}
3559
3560
3561/** @callback_method_impl{FNCPUMRDMSR} */
3562static DECLCALLBACK(int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3563{
3564 /** @todo Fake AMD microcode patching. */
3565 *puValue = pRange->uValue;
3566 return VINF_SUCCESS;
3567}
3568
3569
3570/** @callback_method_impl{FNCPUMWRMSR} */
3571static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3572{
3573 /** @todo Fake AMD microcode patching. */
3574 return VINF_SUCCESS;
3575}
3576
3577
3578/** @callback_method_impl{FNCPUMRDMSR} */
3579static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3580{
3581 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3582 * cpus. Need to be explored and verify K7 presence. */
3583 /** @todo undocumented */
3584 *puValue = 0;
3585 return VINF_SUCCESS;
3586}
3587
3588
3589/** @callback_method_impl{FNCPUMWRMSR} */
3590static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3591{
3592 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3593 * cpus. Need to be explored and verify K7 presence. */
3594 /** @todo undocumented */
3595 return VINF_SUCCESS;
3596}
3597
3598
3599/** @callback_method_impl{FNCPUMRDMSR} */
3600static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3601{
3602 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3603 * cpus. Need to be explored and verify K7 presence. */
3604 /** @todo undocumented */
3605 *puValue = 0;
3606 return VINF_SUCCESS;
3607}
3608
3609
3610/** @callback_method_impl{FNCPUMWRMSR} */
3611static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3612{
3613 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3614 * cpus. Need to be explored and verify K7 presence. */
3615 /** @todo undocumented */
3616 return VINF_SUCCESS;
3617}
3618
3619
3620/** @callback_method_impl{FNCPUMRDMSR} */
3621static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3622{
3623 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3624 * cpus. Need to be explored and verify K7 presence. */
3625 /** @todo undocumented */
3626 *puValue = 0;
3627 return VINF_SUCCESS;
3628}
3629
3630
3631/** @callback_method_impl{FNCPUMWRMSR} */
3632static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3633{
3634 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3635 * cpus. Need to be explored and verify K7 presence. */
3636 /** @todo undocumented */
3637 return VINF_SUCCESS;
3638}
3639
3640
3641/** @callback_method_impl{FNCPUMRDMSR} */
3642static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3643{
3644 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3645 * cpus. Need to be explored and verify K7 presence. */
3646 /** @todo undocumented */
3647 *puValue = 0;
3648 return VINF_SUCCESS;
3649}
3650
3651
3652/** @callback_method_impl{FNCPUMWRMSR} */
3653static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3654{
3655 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3656 * cpus. Need to be explored and verify K7 presence. */
3657 /** @todo undocumented */
3658 return VINF_SUCCESS;
3659}
3660
3661
3662/** @callback_method_impl{FNCPUMRDMSR} */
3663static DECLCALLBACK(int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3664{
3665 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3666 * cpus. Need to be explored and verify K7 presence. */
3667 /** @todo undocumented */
3668 *puValue = 0;
3669 return VINF_SUCCESS;
3670}
3671
3672
3673/** @callback_method_impl{FNCPUMWRMSR} */
3674static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3675{
3676 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3677 * cpus. Need to be explored and verify K7 presence. */
3678 /** @todo undocumented */
3679 return VINF_SUCCESS;
3680}
3681
3682
3683/** @callback_method_impl{FNCPUMRDMSR} */
3684static DECLCALLBACK(int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3685{
3686 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3687 * cpus. Need to be explored and verify K7 presence. */
3688 /** @todo undocumented */
3689 *puValue = 0;
3690 return VINF_SUCCESS;
3691}
3692
3693
3694/** @callback_method_impl{FNCPUMWRMSR} */
3695static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3696{
3697 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3698 * cpus. Need to be explored and verify K7 presence. */
3699 /** @todo undocumented */
3700 return VINF_SUCCESS;
3701}
3702
3703
3704/** @callback_method_impl{FNCPUMRDMSR} */
3705static DECLCALLBACK(int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3706{
3707 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3708 * cpus. Need to be explored and verify K7 presence. */
3709 /** @todo AMD node ID and bios scratch. */
3710 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3711 return VINF_SUCCESS;
3712}
3713
3714
3715/** @callback_method_impl{FNCPUMWRMSR} */
3716static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3717{
3718 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3719 * cpus. Need to be explored and verify K7 presence. */
3720 /** @todo AMD node ID and bios scratch. */
3721 return VINF_SUCCESS;
3722}
3723
3724
3725/** @callback_method_impl{FNCPUMRDMSR} */
3726static DECLCALLBACK(int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3727{
3728 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3729 * cpus. Need to be explored and verify K7 presence. */
3730 /** @todo AMD DRx address masking (range breakpoints). */
3731 *puValue = 0;
3732 return VINF_SUCCESS;
3733}
3734
3735
3736/** @callback_method_impl{FNCPUMWRMSR} */
3737static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3738{
3739 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3740 * cpus. Need to be explored and verify K7 presence. */
3741 /** @todo AMD DRx address masking (range breakpoints). */
3742 return VINF_SUCCESS;
3743}
3744
3745
3746/** @callback_method_impl{FNCPUMRDMSR} */
3747static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3748{
3749 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3750 * cpus. Need to be explored and verify K7 presence. */
3751 /** @todo AMD undocument debugging features. */
3752 *puValue = 0;
3753 return VINF_SUCCESS;
3754}
3755
3756
3757/** @callback_method_impl{FNCPUMWRMSR} */
3758static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3759{
3760 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3761 * cpus. Need to be explored and verify K7 presence. */
3762 /** @todo AMD undocument debugging features. */
3763 return VINF_SUCCESS;
3764}
3765
3766
3767/** @callback_method_impl{FNCPUMRDMSR} */
3768static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3769{
3770 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3771 * cpus. Need to be explored and verify K7 presence. */
3772 /** @todo AMD undocument debugging features. */
3773 *puValue = 0;
3774 return VINF_SUCCESS;
3775}
3776
3777
3778/** @callback_method_impl{FNCPUMWRMSR} */
3779static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3780{
3781 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3782 * cpus. Need to be explored and verify K7 presence. */
3783 /** @todo AMD undocument debugging features. */
3784 return VINF_SUCCESS;
3785}
3786
3787
3788/** @callback_method_impl{FNCPUMRDMSR} */
3789static DECLCALLBACK(int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3790{
3791 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3792 * cpus. Need to be explored and verify K7 presence. */
3793 /** @todo AMD load-store config. */
3794 *puValue = 0;
3795 return VINF_SUCCESS;
3796}
3797
3798
3799/** @callback_method_impl{FNCPUMWRMSR} */
3800static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3801{
3802 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3803 * cpus. Need to be explored and verify K7 presence. */
3804 /** @todo AMD load-store config. */
3805 return VINF_SUCCESS;
3806}
3807
3808
3809/** @callback_method_impl{FNCPUMRDMSR} */
3810static DECLCALLBACK(int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3811{
3812 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3813 * cpus. Need to be explored and verify K7 presence. */
3814 /** @todo AMD instruction cache config. */
3815 *puValue = 0;
3816 return VINF_SUCCESS;
3817}
3818
3819
3820/** @callback_method_impl{FNCPUMWRMSR} */
3821static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3822{
3823 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3824 * cpus. Need to be explored and verify K7 presence. */
3825 /** @todo AMD instruction cache config. */
3826 return VINF_SUCCESS;
3827}
3828
3829
3830/** @callback_method_impl{FNCPUMRDMSR} */
3831static DECLCALLBACK(int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3832{
3833 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3834 * cpus. Need to be explored and verify K7 presence. */
3835 /** @todo AMD data cache config. */
3836 *puValue = 0;
3837 return VINF_SUCCESS;
3838}
3839
3840
3841/** @callback_method_impl{FNCPUMWRMSR} */
3842static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3843{
3844 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3845 * cpus. Need to be explored and verify K7 presence. */
3846 /** @todo AMD data cache config. */
3847 return VINF_SUCCESS;
3848}
3849
3850
3851/** @callback_method_impl{FNCPUMRDMSR} */
3852static DECLCALLBACK(int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3853{
3854 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3855 * cpus. Need to be explored and verify K7 presence. */
3856 /** @todo AMD bus unit config. */
3857 *puValue = 0;
3858 return VINF_SUCCESS;
3859}
3860
3861
3862/** @callback_method_impl{FNCPUMWRMSR} */
3863static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3864{
3865 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3866 * cpus. Need to be explored and verify K7 presence. */
3867 /** @todo AMD bus unit config. */
3868 return VINF_SUCCESS;
3869}
3870
3871
3872/** @callback_method_impl{FNCPUMRDMSR} */
3873static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3874{
3875 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3876 * cpus. Need to be explored and verify K7 presence. */
3877 /** @todo Undocument AMD debug control register \#2. */
3878 *puValue = 0;
3879 return VINF_SUCCESS;
3880}
3881
3882
3883/** @callback_method_impl{FNCPUMWRMSR} */
3884static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3885{
3886 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3887 * cpus. Need to be explored and verify K7 presence. */
3888 /** @todo Undocument AMD debug control register \#2. */
3889 return VINF_SUCCESS;
3890}
3891
3892
3893/** @callback_method_impl{FNCPUMRDMSR} */
3894static DECLCALLBACK(int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3895{
3896 /** @todo AMD FPU config. */
3897 *puValue = 0;
3898 return VINF_SUCCESS;
3899}
3900
3901
3902/** @callback_method_impl{FNCPUMWRMSR} */
3903static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3904{
3905 /** @todo AMD FPU config. */
3906 return VINF_SUCCESS;
3907}
3908
3909
3910/** @callback_method_impl{FNCPUMRDMSR} */
3911static DECLCALLBACK(int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3912{
3913 /** @todo AMD decoder config. */
3914 *puValue = 0;
3915 return VINF_SUCCESS;
3916}
3917
3918
3919/** @callback_method_impl{FNCPUMWRMSR} */
3920static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3921{
3922 /** @todo AMD decoder config. */
3923 return VINF_SUCCESS;
3924}
3925
3926
3927/** @callback_method_impl{FNCPUMRDMSR} */
3928static DECLCALLBACK(int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3929{
3930 /* Note! 10h and 16h */
3931 /** @todo AMD bus unit config. */
3932 *puValue = 0;
3933 return VINF_SUCCESS;
3934}
3935
3936
3937/** @callback_method_impl{FNCPUMWRMSR} */
3938static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3939{
3940 /* Note! 10h and 16h */
3941 /** @todo AMD bus unit config. */
3942 return VINF_SUCCESS;
3943}
3944
3945
3946/** @callback_method_impl{FNCPUMRDMSR} */
3947static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3948{
3949 /** @todo AMD unit config. */
3950 *puValue = 0;
3951 return VINF_SUCCESS;
3952}
3953
3954
3955/** @callback_method_impl{FNCPUMWRMSR} */
3956static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3957{
3958 /** @todo AMD unit config. */
3959 return VINF_SUCCESS;
3960}
3961
3962
3963/** @callback_method_impl{FNCPUMRDMSR} */
3964static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3965{
3966 /** @todo AMD unit config 2. */
3967 *puValue = 0;
3968 return VINF_SUCCESS;
3969}
3970
3971
3972/** @callback_method_impl{FNCPUMWRMSR} */
3973static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3974{
3975 /** @todo AMD unit config 2. */
3976 return VINF_SUCCESS;
3977}
3978
3979
3980/** @callback_method_impl{FNCPUMRDMSR} */
3981static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3982{
3983 /** @todo AMD combined unit config 3. */
3984 *puValue = 0;
3985 return VINF_SUCCESS;
3986}
3987
3988
3989/** @callback_method_impl{FNCPUMWRMSR} */
3990static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3991{
3992 /** @todo AMD combined unit config 3. */
3993 return VINF_SUCCESS;
3994}
3995
3996
3997/** @callback_method_impl{FNCPUMRDMSR} */
3998static DECLCALLBACK(int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3999{
4000 /** @todo AMD execution unit config. */
4001 *puValue = 0;
4002 return VINF_SUCCESS;
4003}
4004
4005
4006/** @callback_method_impl{FNCPUMWRMSR} */
4007static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4008{
4009 /** @todo AMD execution unit config. */
4010 return VINF_SUCCESS;
4011}
4012
4013
4014/** @callback_method_impl{FNCPUMRDMSR} */
4015static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4016{
4017 /** @todo AMD load-store config 2. */
4018 *puValue = 0;
4019 return VINF_SUCCESS;
4020}
4021
4022
4023/** @callback_method_impl{FNCPUMWRMSR} */
4024static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4025{
4026 /** @todo AMD load-store config 2. */
4027 return VINF_SUCCESS;
4028}
4029
4030
4031/** @callback_method_impl{FNCPUMRDMSR} */
4032static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4033{
4034 /** @todo AMD IBS. */
4035 *puValue = 0;
4036 return VINF_SUCCESS;
4037}
4038
4039
4040/** @callback_method_impl{FNCPUMWRMSR} */
4041static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4042{
4043 /** @todo AMD IBS. */
4044 return VINF_SUCCESS;
4045}
4046
4047
4048/** @callback_method_impl{FNCPUMRDMSR} */
4049static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4050{
4051 /** @todo AMD IBS. */
4052 *puValue = 0;
4053 return VINF_SUCCESS;
4054}
4055
4056
4057/** @callback_method_impl{FNCPUMWRMSR} */
4058static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4059{
4060 /** @todo AMD IBS. */
4061 return VINF_SUCCESS;
4062}
4063
4064
4065/** @callback_method_impl{FNCPUMRDMSR} */
4066static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4067{
4068 /** @todo AMD IBS. */
4069 *puValue = 0;
4070 return VINF_SUCCESS;
4071}
4072
4073
4074/** @callback_method_impl{FNCPUMWRMSR} */
4075static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4076{
4077 /** @todo AMD IBS. */
4078 return VINF_SUCCESS;
4079}
4080
4081
4082/** @callback_method_impl{FNCPUMRDMSR} */
4083static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4084{
4085 /** @todo AMD IBS. */
4086 *puValue = 0;
4087 return VINF_SUCCESS;
4088}
4089
4090
4091/** @callback_method_impl{FNCPUMWRMSR} */
4092static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4093{
4094 /** @todo AMD IBS. */
4095 return VINF_SUCCESS;
4096}
4097
4098
4099/** @callback_method_impl{FNCPUMRDMSR} */
4100static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4101{
4102 /** @todo AMD IBS. */
4103 *puValue = 0;
4104 return VINF_SUCCESS;
4105}
4106
4107
4108/** @callback_method_impl{FNCPUMWRMSR} */
4109static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4110{
4111 /** @todo AMD IBS. */
4112 if (!X86_IS_CANONICAL(uValue))
4113 {
4114 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4115 return VERR_CPUM_RAISE_GP_0;
4116 }
4117 return VINF_SUCCESS;
4118}
4119
4120
4121/** @callback_method_impl{FNCPUMRDMSR} */
4122static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4123{
4124 /** @todo AMD IBS. */
4125 *puValue = 0;
4126 return VINF_SUCCESS;
4127}
4128
4129
4130/** @callback_method_impl{FNCPUMWRMSR} */
4131static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4132{
4133 /** @todo AMD IBS. */
4134 return VINF_SUCCESS;
4135}
4136
4137
4138/** @callback_method_impl{FNCPUMRDMSR} */
4139static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4140{
4141 /** @todo AMD IBS. */
4142 *puValue = 0;
4143 return VINF_SUCCESS;
4144}
4145
4146
4147/** @callback_method_impl{FNCPUMWRMSR} */
4148static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4149{
4150 /** @todo AMD IBS. */
4151 return VINF_SUCCESS;
4152}
4153
4154
4155/** @callback_method_impl{FNCPUMRDMSR} */
4156static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4157{
4158 /** @todo AMD IBS. */
4159 *puValue = 0;
4160 return VINF_SUCCESS;
4161}
4162
4163
4164/** @callback_method_impl{FNCPUMWRMSR} */
4165static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4166{
4167 /** @todo AMD IBS. */
4168 return VINF_SUCCESS;
4169}
4170
4171
4172/** @callback_method_impl{FNCPUMRDMSR} */
4173static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4174{
4175 /** @todo AMD IBS. */
4176 *puValue = 0;
4177 return VINF_SUCCESS;
4178}
4179
4180
4181/** @callback_method_impl{FNCPUMWRMSR} */
4182static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4183{
4184 /** @todo AMD IBS. */
4185 if (!X86_IS_CANONICAL(uValue))
4186 {
4187 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4188 return VERR_CPUM_RAISE_GP_0;
4189 }
4190 return VINF_SUCCESS;
4191}
4192
4193
4194/** @callback_method_impl{FNCPUMRDMSR} */
4195static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4196{
4197 /** @todo AMD IBS. */
4198 *puValue = 0;
4199 return VINF_SUCCESS;
4200}
4201
4202
4203/** @callback_method_impl{FNCPUMWRMSR} */
4204static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4205{
4206 /** @todo AMD IBS. */
4207 return VINF_SUCCESS;
4208}
4209
4210
4211/** @callback_method_impl{FNCPUMRDMSR} */
4212static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4213{
4214 /** @todo AMD IBS. */
4215 *puValue = 0;
4216 return VINF_SUCCESS;
4217}
4218
4219
4220/** @callback_method_impl{FNCPUMWRMSR} */
4221static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4222{
4223 /** @todo AMD IBS. */
4224 return VINF_SUCCESS;
4225}
4226
4227
4228/** @callback_method_impl{FNCPUMRDMSR} */
4229static DECLCALLBACK(int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4230{
4231 /** @todo AMD IBS. */
4232 *puValue = 0;
4233 return VINF_SUCCESS;
4234}
4235
4236
4237/** @callback_method_impl{FNCPUMWRMSR} */
4238static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4239{
4240 /** @todo AMD IBS. */
4241 if (!X86_IS_CANONICAL(uValue))
4242 {
4243 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4244 return VERR_CPUM_RAISE_GP_0;
4245 }
4246 return VINF_SUCCESS;
4247}
4248
4249
4250
4251/**
4252 * MSR read function table.
4253 */
4254static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4255{
4256 NULL, /* Invalid */
4257 cpumMsrRd_FixedValue,
4258 NULL, /* Alias */
4259 cpumMsrRd_WriteOnly,
4260 cpumMsrRd_Ia32P5McAddr,
4261 cpumMsrRd_Ia32P5McType,
4262 cpumMsrRd_Ia32TimestampCounter,
4263 cpumMsrRd_Ia32ApicBase,
4264 cpumMsrRd_Ia32FeatureControl,
4265 cpumMsrRd_Ia32BiosSignId,
4266 cpumMsrRd_Ia32SmmMonitorCtl,
4267 cpumMsrRd_Ia32PmcN,
4268 cpumMsrRd_Ia32MonitorFilterLineSize,
4269 cpumMsrRd_Ia32MPerf,
4270 cpumMsrRd_Ia32APerf,
4271 cpumMsrRd_Ia32MtrrCap,
4272 cpumMsrRd_Ia32MtrrPhysBaseN,
4273 cpumMsrRd_Ia32MtrrPhysMaskN,
4274 cpumMsrRd_Ia32MtrrFixed,
4275 cpumMsrRd_Ia32MtrrDefType,
4276 cpumMsrRd_Ia32Pat,
4277 cpumMsrRd_Ia32SysEnterCs,
4278 cpumMsrRd_Ia32SysEnterEsp,
4279 cpumMsrRd_Ia32SysEnterEip,
4280 cpumMsrRd_Ia32McgCap,
4281 cpumMsrRd_Ia32McgStatus,
4282 cpumMsrRd_Ia32McgCtl,
4283 cpumMsrRd_Ia32DebugCtl,
4284 cpumMsrRd_Ia32SmrrPhysBase,
4285 cpumMsrRd_Ia32SmrrPhysMask,
4286 cpumMsrRd_Ia32PlatformDcaCap,
4287 cpumMsrRd_Ia32CpuDcaCap,
4288 cpumMsrRd_Ia32Dca0Cap,
4289 cpumMsrRd_Ia32PerfEvtSelN,
4290 cpumMsrRd_Ia32PerfStatus,
4291 cpumMsrRd_Ia32PerfCtl,
4292 cpumMsrRd_Ia32FixedCtrN,
4293 cpumMsrRd_Ia32PerfCapabilities,
4294 cpumMsrRd_Ia32FixedCtrCtrl,
4295 cpumMsrRd_Ia32PerfGlobalStatus,
4296 cpumMsrRd_Ia32PerfGlobalCtrl,
4297 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4298 cpumMsrRd_Ia32PebsEnable,
4299 cpumMsrRd_Ia32ClockModulation,
4300 cpumMsrRd_Ia32ThermInterrupt,
4301 cpumMsrRd_Ia32ThermStatus,
4302 cpumMsrRd_Ia32Therm2Ctl,
4303 cpumMsrRd_Ia32MiscEnable,
4304 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4305 cpumMsrRd_Ia32McNCtl2,
4306 cpumMsrRd_Ia32DsArea,
4307 cpumMsrRd_Ia32TscDeadline,
4308 cpumMsrRd_Ia32X2ApicN,
4309 cpumMsrRd_Ia32DebugInterface,
4310 cpumMsrRd_Ia32VmxBase,
4311 cpumMsrRd_Ia32VmxPinbasedCtls,
4312 cpumMsrRd_Ia32VmxProcbasedCtls,
4313 cpumMsrRd_Ia32VmxExitCtls,
4314 cpumMsrRd_Ia32VmxEntryCtls,
4315 cpumMsrRd_Ia32VmxMisc,
4316 cpumMsrRd_Ia32VmxCr0Fixed0,
4317 cpumMsrRd_Ia32VmxCr0Fixed1,
4318 cpumMsrRd_Ia32VmxCr4Fixed0,
4319 cpumMsrRd_Ia32VmxCr4Fixed1,
4320 cpumMsrRd_Ia32VmxVmcsEnum,
4321 cpumMsrRd_Ia32VmxProcBasedCtls2,
4322 cpumMsrRd_Ia32VmxEptVpidCap,
4323 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4324 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4325 cpumMsrRd_Ia32VmxTrueExitCtls,
4326 cpumMsrRd_Ia32VmxTrueEntryCtls,
4327
4328 cpumMsrRd_Amd64Efer,
4329 cpumMsrRd_Amd64SyscallTarget,
4330 cpumMsrRd_Amd64LongSyscallTarget,
4331 cpumMsrRd_Amd64CompSyscallTarget,
4332 cpumMsrRd_Amd64SyscallFlagMask,
4333 cpumMsrRd_Amd64FsBase,
4334 cpumMsrRd_Amd64GsBase,
4335 cpumMsrRd_Amd64KernelGsBase,
4336 cpumMsrRd_Amd64TscAux,
4337
4338 cpumMsrRd_IntelEblCrPowerOn,
4339 cpumMsrRd_IntelP4EbcHardPowerOn,
4340 cpumMsrRd_IntelP4EbcSoftPowerOn,
4341 cpumMsrRd_IntelP4EbcFrequencyId,
4342 cpumMsrRd_IntelPlatformInfo100MHz,
4343 cpumMsrRd_IntelPlatformInfo133MHz,
4344 cpumMsrRd_IntelPkgCStConfigControl,
4345 cpumMsrRd_IntelPmgIoCaptureBase,
4346 cpumMsrRd_IntelLastBranchFromToN,
4347 cpumMsrRd_IntelLastBranchFromN,
4348 cpumMsrRd_IntelLastBranchToN,
4349 cpumMsrRd_IntelLastBranchTos,
4350 cpumMsrRd_IntelBblCrCtl,
4351 cpumMsrRd_IntelBblCrCtl3,
4352 cpumMsrRd_IntelI7TemperatureTarget,
4353 cpumMsrRd_IntelI7MsrOffCoreResponseN,
4354 cpumMsrRd_IntelI7MiscPwrMgmt,
4355 cpumMsrRd_IntelP6CrN,
4356 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4357 cpumMsrRd_IntelCpuId1FeatureMaskEax,
4358 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4359 cpumMsrRd_IntelI7SandyAesNiCtl,
4360 cpumMsrRd_IntelI7TurboRatioLimit,
4361 cpumMsrRd_IntelI7LbrSelect,
4362 cpumMsrRd_IntelI7SandyErrorControl,
4363 cpumMsrRd_IntelI7VirtualLegacyWireCap,
4364 cpumMsrRd_IntelI7PowerCtl,
4365 cpumMsrRd_IntelI7SandyPebsNumAlt,
4366 cpumMsrRd_IntelI7PebsLdLat,
4367 cpumMsrRd_IntelI7PkgCnResidencyN,
4368 cpumMsrRd_IntelI7CoreCnResidencyN,
4369 cpumMsrRd_IntelI7SandyVrCurrentConfig,
4370 cpumMsrRd_IntelI7SandyVrMiscConfig,
4371 cpumMsrRd_IntelI7SandyRaplPowerUnit,
4372 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4373 cpumMsrRd_IntelI7SandyPkgC2Residency,
4374 cpumMsrRd_IntelI7RaplPkgPowerLimit,
4375 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4376 cpumMsrRd_IntelI7RaplPkgPerfStatus,
4377 cpumMsrRd_IntelI7RaplPkgPowerInfo,
4378 cpumMsrRd_IntelI7RaplDramPowerLimit,
4379 cpumMsrRd_IntelI7RaplDramEnergyStatus,
4380 cpumMsrRd_IntelI7RaplDramPerfStatus,
4381 cpumMsrRd_IntelI7RaplDramPowerInfo,
4382 cpumMsrRd_IntelI7RaplPp0PowerLimit,
4383 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4384 cpumMsrRd_IntelI7RaplPp0Policy,
4385 cpumMsrRd_IntelI7RaplPp0PerfStatus,
4386 cpumMsrRd_IntelI7RaplPp1PowerLimit,
4387 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4388 cpumMsrRd_IntelI7RaplPp1Policy,
4389 cpumMsrRd_IntelI7IvyConfigTdpNominal,
4390 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4391 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4392 cpumMsrRd_IntelI7IvyConfigTdpControl,
4393 cpumMsrRd_IntelI7IvyTurboActivationRatio,
4394 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4395 cpumMsrRd_IntelI7UncPerfGlobalStatus,
4396 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4397 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4398 cpumMsrRd_IntelI7UncPerfFixedCtr,
4399 cpumMsrRd_IntelI7UncCBoxConfig,
4400 cpumMsrRd_IntelI7UncArbPerfCtrN,
4401 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4402 cpumMsrRd_IntelCore2EmttmCrTablesN,
4403 cpumMsrRd_IntelCore2SmmCStMiscInfo,
4404 cpumMsrRd_IntelCore1ExtConfig,
4405 cpumMsrRd_IntelCore1DtsCalControl,
4406 cpumMsrRd_IntelCore2PeciControl,
4407
4408 cpumMsrRd_P6LastBranchFromIp,
4409 cpumMsrRd_P6LastBranchToIp,
4410 cpumMsrRd_P6LastIntFromIp,
4411 cpumMsrRd_P6LastIntToIp,
4412
4413 cpumMsrRd_AmdFam15hTscRate,
4414 cpumMsrRd_AmdFam15hLwpCfg,
4415 cpumMsrRd_AmdFam15hLwpCbAddr,
4416 cpumMsrRd_AmdFam10hMc4MiscN,
4417 cpumMsrRd_AmdK8PerfCtlN,
4418 cpumMsrRd_AmdK8PerfCtrN,
4419 cpumMsrRd_AmdK8SysCfg,
4420 cpumMsrRd_AmdK8HwCr,
4421 cpumMsrRd_AmdK8IorrBaseN,
4422 cpumMsrRd_AmdK8IorrMaskN,
4423 cpumMsrRd_AmdK8TopOfMemN,
4424 cpumMsrRd_AmdK8NbCfg1,
4425 cpumMsrRd_AmdK8McXcptRedir,
4426 cpumMsrRd_AmdK8CpuNameN,
4427 cpumMsrRd_AmdK8HwThermalCtrl,
4428 cpumMsrRd_AmdK8SwThermalCtrl,
4429 cpumMsrRd_AmdK8FidVidControl,
4430 cpumMsrRd_AmdK8FidVidStatus,
4431 cpumMsrRd_AmdK8McCtlMaskN,
4432 cpumMsrRd_AmdK8SmiOnIoTrapN,
4433 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4434 cpumMsrRd_AmdK8IntPendingMessage,
4435 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4436 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4437 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4438 cpumMsrRd_AmdFam10hPStateCurLimit,
4439 cpumMsrRd_AmdFam10hPStateControl,
4440 cpumMsrRd_AmdFam10hPStateStatus,
4441 cpumMsrRd_AmdFam10hPStateN,
4442 cpumMsrRd_AmdFam10hCofVidControl,
4443 cpumMsrRd_AmdFam10hCofVidStatus,
4444 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4445 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4446 cpumMsrRd_AmdK8SmmBase,
4447 cpumMsrRd_AmdK8SmmAddr,
4448 cpumMsrRd_AmdK8SmmMask,
4449 cpumMsrRd_AmdK8VmCr,
4450 cpumMsrRd_AmdK8IgnNe,
4451 cpumMsrRd_AmdK8SmmCtl,
4452 cpumMsrRd_AmdK8VmHSavePa,
4453 cpumMsrRd_AmdFam10hVmLockKey,
4454 cpumMsrRd_AmdFam10hSmmLockKey,
4455 cpumMsrRd_AmdFam10hLocalSmiStatus,
4456 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4457 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4458 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4459 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4460 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4461 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4462 cpumMsrRd_AmdK7MicrocodeCtl,
4463 cpumMsrRd_AmdK7ClusterIdMaybe,
4464 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4465 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4466 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4467 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4468 cpumMsrRd_AmdK8PatchLevel,
4469 cpumMsrRd_AmdK7DebugStatusMaybe,
4470 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4471 cpumMsrRd_AmdK7BHTracePtrMaybe,
4472 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4473 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4474 cpumMsrRd_AmdK7FastFlushCountMaybe,
4475 cpumMsrRd_AmdK7NodeId,
4476 cpumMsrRd_AmdK7DrXAddrMaskN,
4477 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4478 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4479 cpumMsrRd_AmdK7LoadStoreCfg,
4480 cpumMsrRd_AmdK7InstrCacheCfg,
4481 cpumMsrRd_AmdK7DataCacheCfg,
4482 cpumMsrRd_AmdK7BusUnitCfg,
4483 cpumMsrRd_AmdK7DebugCtl2Maybe,
4484 cpumMsrRd_AmdFam15hFpuCfg,
4485 cpumMsrRd_AmdFam15hDecoderCfg,
4486 cpumMsrRd_AmdFam10hBusUnitCfg2,
4487 cpumMsrRd_AmdFam15hCombUnitCfg,
4488 cpumMsrRd_AmdFam15hCombUnitCfg2,
4489 cpumMsrRd_AmdFam15hCombUnitCfg3,
4490 cpumMsrRd_AmdFam15hExecUnitCfg,
4491 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4492 cpumMsrRd_AmdFam10hIbsFetchCtl,
4493 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4494 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4495 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4496 cpumMsrRd_AmdFam10hIbsOpRip,
4497 cpumMsrRd_AmdFam10hIbsOpData,
4498 cpumMsrRd_AmdFam10hIbsOpData2,
4499 cpumMsrRd_AmdFam10hIbsOpData3,
4500 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4501 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4502 cpumMsrRd_AmdFam10hIbsCtl,
4503 cpumMsrRd_AmdFam14hIbsBrTarget,
4504};
4505
4506
4507/**
4508 * MSR write function table.
4509 */
4510static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4511{
4512 NULL, /* Invalid */
4513 cpumMsrWr_IgnoreWrite,
4514 cpumMsrWr_ReadOnly,
4515 NULL, /* Alias */
4516 cpumMsrWr_Ia32P5McAddr,
4517 cpumMsrWr_Ia32P5McType,
4518 cpumMsrWr_Ia32TimestampCounter,
4519 cpumMsrWr_Ia32ApicBase,
4520 cpumMsrWr_Ia32FeatureControl,
4521 cpumMsrWr_Ia32BiosSignId,
4522 cpumMsrWr_Ia32BiosUpdateTrigger,
4523 cpumMsrWr_Ia32SmmMonitorCtl,
4524 cpumMsrWr_Ia32PmcN,
4525 cpumMsrWr_Ia32MonitorFilterLineSize,
4526 cpumMsrWr_Ia32MPerf,
4527 cpumMsrWr_Ia32APerf,
4528 cpumMsrWr_Ia32MtrrPhysBaseN,
4529 cpumMsrWr_Ia32MtrrPhysMaskN,
4530 cpumMsrWr_Ia32MtrrFixed,
4531 cpumMsrWr_Ia32MtrrDefType,
4532 cpumMsrWr_Ia32Pat,
4533 cpumMsrWr_Ia32SysEnterCs,
4534 cpumMsrWr_Ia32SysEnterEsp,
4535 cpumMsrWr_Ia32SysEnterEip,
4536 cpumMsrWr_Ia32McgStatus,
4537 cpumMsrWr_Ia32McgCtl,
4538 cpumMsrWr_Ia32DebugCtl,
4539 cpumMsrWr_Ia32SmrrPhysBase,
4540 cpumMsrWr_Ia32SmrrPhysMask,
4541 cpumMsrWr_Ia32PlatformDcaCap,
4542 cpumMsrWr_Ia32Dca0Cap,
4543 cpumMsrWr_Ia32PerfEvtSelN,
4544 cpumMsrWr_Ia32PerfStatus,
4545 cpumMsrWr_Ia32PerfCtl,
4546 cpumMsrWr_Ia32FixedCtrN,
4547 cpumMsrWr_Ia32PerfCapabilities,
4548 cpumMsrWr_Ia32FixedCtrCtrl,
4549 cpumMsrWr_Ia32PerfGlobalStatus,
4550 cpumMsrWr_Ia32PerfGlobalCtrl,
4551 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4552 cpumMsrWr_Ia32PebsEnable,
4553 cpumMsrWr_Ia32ClockModulation,
4554 cpumMsrWr_Ia32ThermInterrupt,
4555 cpumMsrWr_Ia32ThermStatus,
4556 cpumMsrWr_Ia32Therm2Ctl,
4557 cpumMsrWr_Ia32MiscEnable,
4558 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4559 cpumMsrWr_Ia32McNCtl2,
4560 cpumMsrWr_Ia32DsArea,
4561 cpumMsrWr_Ia32TscDeadline,
4562 cpumMsrWr_Ia32X2ApicN,
4563 cpumMsrWr_Ia32DebugInterface,
4564
4565 cpumMsrWr_Amd64Efer,
4566 cpumMsrWr_Amd64SyscallTarget,
4567 cpumMsrWr_Amd64LongSyscallTarget,
4568 cpumMsrWr_Amd64CompSyscallTarget,
4569 cpumMsrWr_Amd64SyscallFlagMask,
4570 cpumMsrWr_Amd64FsBase,
4571 cpumMsrWr_Amd64GsBase,
4572 cpumMsrWr_Amd64KernelGsBase,
4573 cpumMsrWr_Amd64TscAux,
4574
4575 cpumMsrWr_IntelEblCrPowerOn,
4576 cpumMsrWr_IntelP4EbcHardPowerOn,
4577 cpumMsrWr_IntelP4EbcSoftPowerOn,
4578 cpumMsrWr_IntelP4EbcFrequencyId,
4579 cpumMsrWr_IntelPkgCStConfigControl,
4580 cpumMsrWr_IntelPmgIoCaptureBase,
4581 cpumMsrWr_IntelLastBranchFromToN,
4582 cpumMsrWr_IntelLastBranchFromN,
4583 cpumMsrWr_IntelLastBranchToN,
4584 cpumMsrWr_IntelLastBranchTos,
4585 cpumMsrWr_IntelBblCrCtl,
4586 cpumMsrWr_IntelBblCrCtl3,
4587 cpumMsrWr_IntelI7TemperatureTarget,
4588 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4589 cpumMsrWr_IntelI7MiscPwrMgmt,
4590 cpumMsrWr_IntelP6CrN,
4591 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4592 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4593 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4594 cpumMsrWr_IntelI7SandyAesNiCtl,
4595 cpumMsrWr_IntelI7TurboRatioLimit,
4596 cpumMsrWr_IntelI7LbrSelect,
4597 cpumMsrWr_IntelI7SandyErrorControl,
4598 cpumMsrWr_IntelI7PowerCtl,
4599 cpumMsrWr_IntelI7SandyPebsNumAlt,
4600 cpumMsrWr_IntelI7PebsLdLat,
4601 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4602 cpumMsrWr_IntelI7SandyVrMiscConfig,
4603 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4604 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4605 cpumMsrWr_IntelI7RaplDramPowerLimit,
4606 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4607 cpumMsrWr_IntelI7RaplPp0Policy,
4608 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4609 cpumMsrWr_IntelI7RaplPp1Policy,
4610 cpumMsrWr_IntelI7IvyConfigTdpControl,
4611 cpumMsrWr_IntelI7IvyTurboActivationRatio,
4612 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4613 cpumMsrWr_IntelI7UncPerfGlobalStatus,
4614 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4615 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4616 cpumMsrWr_IntelI7UncPerfFixedCtr,
4617 cpumMsrWr_IntelI7UncArbPerfCtrN,
4618 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4619 cpumMsrWr_IntelCore2EmttmCrTablesN,
4620 cpumMsrWr_IntelCore2SmmCStMiscInfo,
4621 cpumMsrWr_IntelCore1ExtConfig,
4622 cpumMsrWr_IntelCore1DtsCalControl,
4623 cpumMsrWr_IntelCore2PeciControl,
4624
4625 cpumMsrWr_P6LastIntFromIp,
4626 cpumMsrWr_P6LastIntToIp,
4627
4628 cpumMsrWr_AmdFam15hTscRate,
4629 cpumMsrWr_AmdFam15hLwpCfg,
4630 cpumMsrWr_AmdFam15hLwpCbAddr,
4631 cpumMsrWr_AmdFam10hMc4MiscN,
4632 cpumMsrWr_AmdK8PerfCtlN,
4633 cpumMsrWr_AmdK8PerfCtrN,
4634 cpumMsrWr_AmdK8SysCfg,
4635 cpumMsrWr_AmdK8HwCr,
4636 cpumMsrWr_AmdK8IorrBaseN,
4637 cpumMsrWr_AmdK8IorrMaskN,
4638 cpumMsrWr_AmdK8TopOfMemN,
4639 cpumMsrWr_AmdK8NbCfg1,
4640 cpumMsrWr_AmdK8McXcptRedir,
4641 cpumMsrWr_AmdK8CpuNameN,
4642 cpumMsrWr_AmdK8HwThermalCtrl,
4643 cpumMsrWr_AmdK8SwThermalCtrl,
4644 cpumMsrWr_AmdK8FidVidControl,
4645 cpumMsrWr_AmdK8McCtlMaskN,
4646 cpumMsrWr_AmdK8SmiOnIoTrapN,
4647 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4648 cpumMsrWr_AmdK8IntPendingMessage,
4649 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4650 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4651 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4652 cpumMsrWr_AmdFam10hPStateControl,
4653 cpumMsrWr_AmdFam10hPStateStatus,
4654 cpumMsrWr_AmdFam10hPStateN,
4655 cpumMsrWr_AmdFam10hCofVidControl,
4656 cpumMsrWr_AmdFam10hCofVidStatus,
4657 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4658 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4659 cpumMsrWr_AmdK8SmmBase,
4660 cpumMsrWr_AmdK8SmmAddr,
4661 cpumMsrWr_AmdK8SmmMask,
4662 cpumMsrWr_AmdK8VmCr,
4663 cpumMsrWr_AmdK8IgnNe,
4664 cpumMsrWr_AmdK8SmmCtl,
4665 cpumMsrWr_AmdK8VmHSavePa,
4666 cpumMsrWr_AmdFam10hVmLockKey,
4667 cpumMsrWr_AmdFam10hSmmLockKey,
4668 cpumMsrWr_AmdFam10hLocalSmiStatus,
4669 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4670 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4671 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4672 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4673 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4674 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4675 cpumMsrWr_AmdK7MicrocodeCtl,
4676 cpumMsrWr_AmdK7ClusterIdMaybe,
4677 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4678 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4679 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4680 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4681 cpumMsrWr_AmdK8PatchLoader,
4682 cpumMsrWr_AmdK7DebugStatusMaybe,
4683 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4684 cpumMsrWr_AmdK7BHTracePtrMaybe,
4685 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4686 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4687 cpumMsrWr_AmdK7FastFlushCountMaybe,
4688 cpumMsrWr_AmdK7NodeId,
4689 cpumMsrWr_AmdK7DrXAddrMaskN,
4690 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4691 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4692 cpumMsrWr_AmdK7LoadStoreCfg,
4693 cpumMsrWr_AmdK7InstrCacheCfg,
4694 cpumMsrWr_AmdK7DataCacheCfg,
4695 cpumMsrWr_AmdK7BusUnitCfg,
4696 cpumMsrWr_AmdK7DebugCtl2Maybe,
4697 cpumMsrWr_AmdFam15hFpuCfg,
4698 cpumMsrWr_AmdFam15hDecoderCfg,
4699 cpumMsrWr_AmdFam10hBusUnitCfg2,
4700 cpumMsrWr_AmdFam15hCombUnitCfg,
4701 cpumMsrWr_AmdFam15hCombUnitCfg2,
4702 cpumMsrWr_AmdFam15hCombUnitCfg3,
4703 cpumMsrWr_AmdFam15hExecUnitCfg,
4704 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4705 cpumMsrWr_AmdFam10hIbsFetchCtl,
4706 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4707 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4708 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4709 cpumMsrWr_AmdFam10hIbsOpRip,
4710 cpumMsrWr_AmdFam10hIbsOpData,
4711 cpumMsrWr_AmdFam10hIbsOpData2,
4712 cpumMsrWr_AmdFam10hIbsOpData3,
4713 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4714 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4715 cpumMsrWr_AmdFam10hIbsCtl,
4716 cpumMsrWr_AmdFam14hIbsBrTarget,
4717};
4718
4719
4720/**
4721 * Looks up the range for the given MSR.
4722 *
4723 * @returns Pointer to the range if found, NULL if not.
4724 * @param pVM The cross context VM structure.
4725 * @param idMsr The MSR to look up.
4726 */
4727# ifndef IN_RING3
4728static
4729# endif
4730PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4731{
4732 /*
4733 * Binary lookup.
4734 */
4735 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4736 if (!cRanges)
4737 return NULL;
4738 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4739 for (;;)
4740 {
4741 uint32_t i = cRanges / 2;
4742 if (idMsr < paRanges[i].uFirst)
4743 {
4744 if (i == 0)
4745 break;
4746 cRanges = i;
4747 }
4748 else if (idMsr > paRanges[i].uLast)
4749 {
4750 i++;
4751 if (i >= cRanges)
4752 break;
4753 cRanges -= i;
4754 paRanges = &paRanges[i];
4755 }
4756 else
4757 {
4758 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4759 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4760 return &paRanges[i];
4761 }
4762 }
4763
4764# ifdef VBOX_STRICT
4765 /*
4766 * Linear lookup to verify the above binary search.
4767 */
4768 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4769 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4770 while (cLeft-- > 0)
4771 {
4772 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4773 {
4774 AssertFailed();
4775 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4776 return cpumLookupMsrRange(pVM, pCur->uValue);
4777 return pCur;
4778 }
4779 pCur++;
4780 }
4781# endif
4782 return NULL;
4783}
4784
4785#ifdef VBOX_WITH_NEW_MSR_CODE
4786
4787/**
4788 * Query a guest MSR.
4789 *
4790 * The caller is responsible for checking privilege if the call is the result of
4791 * a RDMSR instruction. We'll do the rest.
4792 *
4793 * @retval VINF_SUCCESS on success.
4794 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4795 * expected to take the appropriate actions. @a *puValue is set to 0.
4796 * @param pVCpu Pointer to the VMCPU.
4797 * @param idMsr The MSR.
4798 * @param puValue Where to return the value.
4799 *
4800 * @remarks This will always return the right values, even when we're in the
4801 * recompiler.
4802 */
4803VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4804{
4805 *puValue = 0;
4806
4807 int rc;
4808 PVM pVM = pVCpu->CTX_SUFF(pVM);
4809 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4810 if (pRange)
4811 {
4812 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4813 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4814
4815 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
4816 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
4817
4818 STAM_COUNTER_INC(&pRange->cReads);
4819 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4820
4821 rc = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
4822 if (RT_SUCCESS(rc))
4823 {
4824 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
4825 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4826 }
4827 else if (rc == VERR_CPUM_RAISE_GP_0)
4828 {
4829 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
4830 STAM_COUNTER_INC(&pRange->cGps);
4831 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
4832 }
4833 else
4834 Log(("CPUM: RDMSR %#x (%s) -> rc=%Rrc\n", idMsr, pRange->szName, rc));
4835 }
4836 else
4837 {
4838 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
4839 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4840 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
4841 rc = VERR_CPUM_RAISE_GP_0;
4842 }
4843 return rc;
4844}
4845
4846
4847/**
4848 * Writes to a guest MSR.
4849 *
4850 * The caller is responsible for checking privilege if the call is the result of
4851 * a WRMSR instruction. We'll do the rest.
4852 *
4853 * @retval VINF_SUCCESS on success.
4854 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
4855 * appropriate actions.
4856 *
4857 * @param pVCpu Pointer to the VMCPU.
4858 * @param idMsr The MSR id.
4859 * @param uValue The value to set.
4860 *
4861 * @remarks Everyone changing MSR values, including the recompiler, shall do it
4862 * by calling this method. This makes sure we have current values and
4863 * that we trigger all the right actions when something changes.
4864 *
4865 * For performance reasons, this actually isn't entirely true for some
4866 * MSRs when in HM mode. The code here and in HM must be aware of
4867 * this.
4868 */
4869VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
4870{
4871 int rc;
4872 PVM pVM = pVCpu->CTX_SUFF(pVM);
4873 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4874 if (pRange)
4875 {
4876 STAM_COUNTER_INC(&pRange->cWrites);
4877 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
4878
4879 if (!(uValue & pRange->fWrGpMask))
4880 {
4881 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
4882 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
4883
4884 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
4885 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
4886
4887 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
4888 if (uValueAdjusted != uValue)
4889 {
4890 STAM_COUNTER_INC(&pRange->cIgnoredBits);
4891 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
4892 }
4893
4894 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
4895 if (RT_SUCCESS(rc))
4896 {
4897 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
4898 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4899 }
4900 else if (rc == VERR_CPUM_RAISE_GP_0)
4901 {
4902 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
4903 STAM_COUNTER_INC(&pRange->cGps);
4904 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
4905 }
4906 else
4907 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc));
4908 }
4909 else
4910 {
4911 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
4912 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
4913 STAM_COUNTER_INC(&pRange->cGps);
4914 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
4915 rc = VERR_CPUM_RAISE_GP_0;
4916 }
4917 }
4918 else
4919 {
4920 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
4921 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
4922 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
4923 rc = VERR_CPUM_RAISE_GP_0;
4924 }
4925 return rc;
4926}
4927
4928#endif /* VBOX_WITH_NEW_MSR_CODE */
4929
4930
4931#if defined(VBOX_STRICT) && defined(IN_RING3)
4932/**
4933 * Performs some checks on the static data related to MSRs.
4934 *
4935 * @returns VINF_SUCCESS on success, error on failure.
4936 */
4937int cpumR3MsrStrictInitChecks(void)
4938{
4939#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
4940 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
4941#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
4942 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
4943
4944 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
4945 CPUM_ASSERT_RD_MSR_FN(FixedValue);
4946 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
4947 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
4948 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
4949 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
4950 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
4951 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
4952 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
4953 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
4954 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
4955 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
4956 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
4957 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
4958 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
4959 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
4960 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
4961 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
4962 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
4963 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
4964 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
4965 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
4966 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
4967 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
4968 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
4969 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
4970 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
4971 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
4972 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
4973 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
4974 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
4975 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
4976 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
4977 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
4978 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
4979 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
4980 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
4981 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
4982 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
4983 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
4984 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
4985 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
4986 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
4987 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
4988 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
4989 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
4990 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
4991 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
4992 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
4993 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
4994 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
4995 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
4996 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
4997 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
4998 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
4999 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5000 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5001 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5002 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5003 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5004 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5005 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5006 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5007 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5008 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5009 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5010 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5011 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5012 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5013
5014 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5015 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5016 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5017 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5018 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5019 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5020 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5021 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5022 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5023
5024 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5025 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5026 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5027 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5028 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo100MHz);
5029 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo133MHz);
5030 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5031 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5032 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5033 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5034 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5035 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5036 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5037 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5038 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5039 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5040 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5041 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5042 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5043 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5044 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5045 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5046 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5047 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5048 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5049 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5050 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5051 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5052 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5053 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5054 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5055 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5056 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5057 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5058 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5059 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5060 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5061 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5062 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5063 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5064 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5065 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5066 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5067 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5068 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5069 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5070 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5071 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5072 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5073 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5074 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5075 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5076 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5077 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5078 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5079 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5080 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5081 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5082 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5083 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5084 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5085 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5086 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5087 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5088 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5089 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5090 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5091 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5092 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5093
5094 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5095 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5096 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5097 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5098
5099 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5100 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5101 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5102 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5103 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5104 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5105 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5106 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5107 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5108 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5109 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5110 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5111 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5112 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5113 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5114 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5115 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5116 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5117 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5118 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5119 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5120 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5121 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5122 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5123 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5124 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5125 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5126 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5127 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5128 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5129 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5130 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5131 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5132 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5133 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5134 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5135 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5136 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5137 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5138 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5139 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5140 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5141 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5142 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5143 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5144 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5145 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5146 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5147 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5148 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5149 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5150 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5151 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5152 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5153 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5154 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5155 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5156 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5157 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5158 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5159 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5160 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5161 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5162 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5163 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5164 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5165 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5166 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5167 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5168 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5169 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5170 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5171 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5172 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5173 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5174 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5175 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5176 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5177 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5178 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5179 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5180 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5181 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5182 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5183 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5184 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5185 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5186 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5187 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5188 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5189 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5190
5191 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5192 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5193 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5194 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5195 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5196 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5197 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5198 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5199 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5200 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5201 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5202 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5203 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5204 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5205 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5206 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5207 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5208 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5209 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5210 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5211 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5212 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5213 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5214 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5215 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5216 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5217 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5218 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5219 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5220 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5221 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5222 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5223 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5224 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5225 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5226 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5227 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5228 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5229 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5230 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5231 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5232 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5233 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5234 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5235 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5236 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5237 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5238 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5239
5240 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5241 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5242 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5243 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5244 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5245 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5246 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5247 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5248 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5249
5250 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5251 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5252 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5253 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5254 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5255 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5256 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5257 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5258 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5259 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5260 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5261 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5262 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5263 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5264 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5265 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5266 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5267 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5268 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5269 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5270 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5271 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5272 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5273 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5274 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5275 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5276 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5277 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5278 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5279 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5280 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5281 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5282 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5283 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5284 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5285 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5286 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5287 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5288 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5289 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5290 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5291 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5292 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5293 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5294 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5295 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5296 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5297 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5298 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5299
5300 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5301 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5302
5303 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5304 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5305 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5306 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5307 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5308 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5309 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5310 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5311 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5312 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5313 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5314 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5315 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5316 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5317 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5318 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5319 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5320 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5321 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5322 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5323 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5324 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5325 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5326 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5327 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5328 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5329 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5330 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5331 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5332 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5333 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5334 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5335 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5336 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5337 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5338 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5339 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5340 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5341 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5342 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5343 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5344 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5345 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5346 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5347 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5348 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5349 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5350 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5351 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5352 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5353 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5354 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5355 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5356 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5357 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5358 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5359 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5360 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5361 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5362 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5363 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5364 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5365 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5366 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5367 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5368 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5369 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5370 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5371 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5372 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5373 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5374 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5375 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5376 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5377 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5378 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5379 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5380 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5381 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5382 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5383 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5384 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5385 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5386 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5387 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5388 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5389 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5390 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5391 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5392
5393 return VINF_SUCCESS;
5394}
5395#endif /* VBOX_STRICT && IN_RING3 */
5396
5397
5398#ifdef IN_RING0
5399
5400/**
5401 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5402 *
5403 * @returns The register value.
5404 * @param pVCpu Pointer to the cross context CPU structure for
5405 * the calling EMT.
5406 * @thread EMT(pVCpu)
5407 */
5408VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5409{
5410 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5411}
5412
5413
5414/**
5415 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5416 *
5417 * @param pVCpu Pointer to the cross context CPU structure for
5418 * the calling EMT.
5419 * @param uValue The new value.
5420 * @thread EMT(pVCpu)
5421 */
5422VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5423{
5424 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5425}
5426
5427#endif /* IN_RING0 */
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