VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp@ 94991

Last change on this file since 94991 was 94931, checked in by vboxsync, 3 years ago

VMM/CPUM: Introduced a global variable g_CpumHostFeatures for keeping the host CPU features. This is safer than keeping this info in the shared part of the VM structure. bugref:10093
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 74.7 KB
Line 
1/* $Id: CPUMAllCpuId.cpp 94931 2022-05-09 08:24:47Z vboxsync $ */
2/** @file
3 * CPUM - CPU ID part, common bits.
4 */
5
6/*
7 * Copyright (C) 2013-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/ssm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vmcc.h>
28#include <VBox/sup.h>
29
30#include <VBox/err.h>
31#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
32# include <iprt/asm-amd64-x86.h>
33#endif
34#include <iprt/ctype.h>
35#include <iprt/mem.h>
36#include <iprt/string.h>
37#include <iprt/x86-helpers.h>
38
39
40/*********************************************************************************************************************************
41* Global Variables *
42*********************************************************************************************************************************/
43/**
44 * The intel pentium family.
45 */
46static const CPUMMICROARCH g_aenmIntelFamily06[] =
47{
48 /* [ 0(0x00)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro A-step (says sandpile.org). */
49 /* [ 1(0x01)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro */
50 /* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
51 /* [ 3(0x03)] = */ kCpumMicroarch_Intel_P6_II, /* PII Klamath */
52 /* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
53 /* [ 5(0x05)] = */ kCpumMicroarch_Intel_P6_II, /* PII Deschutes */
54 /* [ 6(0x06)] = */ kCpumMicroarch_Intel_P6_II, /* Celeron Mendocino. */
55 /* [ 7(0x07)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Katmai. */
56 /* [ 8(0x08)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Coppermine (includes Celeron). */
57 /* [ 9(0x09)] = */ kCpumMicroarch_Intel_P6_M_Banias, /* Pentium/Celeron M Banias. */
58 /* [10(0x0a)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Xeon */
59 /* [11(0x0b)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Tualatin (includes Celeron). */
60 /* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
61 /* [13(0x0d)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Pentium/Celeron M Dothan. */
62 /* [14(0x0e)] = */ kCpumMicroarch_Intel_Core_Yonah, /* Core Yonah (Enhanced Pentium M). */
63 /* [15(0x0f)] = */ kCpumMicroarch_Intel_Core2_Merom, /* Merom */
64 /* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
65 /* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
66 /* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
67 /* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
68 /* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
69 /* [21(0x15)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Tolapai - System-on-a-chip. */
70 /* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
71 /* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
72 /* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
73 /* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
74 /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Nehalem-EP */
75 /* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
76 /* [28(0x1c)] = */ kCpumMicroarch_Intel_Atom_Bonnell, /* Diamonville, Pineview, */
77 /* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
78 /* [30(0x1e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Clarksfield, Lynnfield, Jasper Forest. */
79 /* [31(0x1f)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
80 /* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
81 /* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
82 /* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
83 /* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
84 /* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
85 /* [37(0x25)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Arrandale, Clarksdale. */
86 /* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
87 /* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
88 /* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
89 /* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
90 /* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
91 /* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
92 /* [44(0x2c)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Gulftown, Westmere-EP. */
93 /* [45(0x2d)] = */ kCpumMicroarch_Intel_Core7_SandyBridge, /* SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
94 /* [46(0x2e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Beckton (Xeon). */
95 /* [47(0x2f)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Westmere-EX. */
96 /* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
97 /* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
98 /* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
99 /* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
100 /* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
101 /* [53(0x35)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* ?? */
102 /* [54(0x36)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* Cedarview, ++ */
103 /* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
104 /* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
105 /* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
106 /* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
107 /* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
108 /* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
109 /* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
110 /* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
111 /* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
112 /* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
113 /* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
114 /* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
115 /* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
116 /* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
117 /* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
118 /* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
119 /* [71(0x47)] = */ kCpumMicroarch_Intel_Core7_Broadwell, /* i7-5775C */
120 /* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
121 /* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
122 /* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
123 /* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
124 /* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
125 /* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
126 /* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
127 /* [79(0x4f)] = */ kCpumMicroarch_Intel_Core7_Broadwell, /* Broadwell-E */
128 /* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
129 /* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
130 /* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
131 /* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
132 /* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
133 /* [85(0x55)] = */ kCpumMicroarch_Intel_Core7_Skylake, /* server cpu; skylake <= 4, cascade lake > 5 */
134 /* [86(0x56)] = */ kCpumMicroarch_Intel_Core7_Broadwell, /* Xeon D-1540, Broadwell-DE */
135 /* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
136 /* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
137 /* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
138 /* [90(0x5a)] = */ kCpumMicroarch_Intel_Atom_Silvermont, /* Moorefield */
139 /* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
140 /* [92(0x5c)] = */ kCpumMicroarch_Intel_Atom_Goldmont, /* Apollo Lake */
141 /* [93(0x5d)] = */ kCpumMicroarch_Intel_Atom_Silvermont, /* x3-C3230 */
142 /* [94(0x5e)] = */ kCpumMicroarch_Intel_Core7_Skylake, /* i7-6700K */
143 /* [95(0x5f)] = */ kCpumMicroarch_Intel_Atom_Goldmont, /* Denverton */
144 /* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
145 /* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
146 /* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
147 /* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
148 /*[100(0x64)] = */ kCpumMicroarch_Intel_Unknown,
149 /*[101(0x65)] = */ kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
150 /*[102(0x66)] = */ kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
151 /*[103(0x67)] = */ kCpumMicroarch_Intel_Unknown,
152 /*[104(0x68)] = */ kCpumMicroarch_Intel_Unknown,
153 /*[105(0x69)] = */ kCpumMicroarch_Intel_Unknown,
154 /*[106(0x6a)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
155 /*[107(0x6b)] = */ kCpumMicroarch_Intel_Unknown,
156 /*[108(0x6c)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
157 /*[109(0x6d)] = */ kCpumMicroarch_Intel_Unknown,
158 /*[110(0x6e)] = */ kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
159 /*[111(0x6f)] = */ kCpumMicroarch_Intel_Unknown,
160 /*[112(0x70)] = */ kCpumMicroarch_Intel_Unknown,
161 /*[113(0x71)] = */ kCpumMicroarch_Intel_Unknown,
162 /*[114(0x72)] = */ kCpumMicroarch_Intel_Unknown,
163 /*[115(0x73)] = */ kCpumMicroarch_Intel_Unknown,
164 /*[116(0x74)] = */ kCpumMicroarch_Intel_Unknown,
165 /*[117(0x75)] = */ kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
166 /*[118(0x76)] = */ kCpumMicroarch_Intel_Unknown,
167 /*[119(0x77)] = */ kCpumMicroarch_Intel_Unknown,
168 /*[120(0x78)] = */ kCpumMicroarch_Intel_Unknown,
169 /*[121(0x79)] = */ kCpumMicroarch_Intel_Unknown,
170 /*[122(0x7a)] = */ kCpumMicroarch_Intel_Atom_GoldmontPlus,
171 /*[123(0x7b)] = */ kCpumMicroarch_Intel_Unknown,
172 /*[124(0x7c)] = */ kCpumMicroarch_Intel_Unknown,
173 /*[125(0x7d)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
174 /*[126(0x7e)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
175 /*[127(0x7f)] = */ kCpumMicroarch_Intel_Unknown,
176 /*[128(0x80)] = */ kCpumMicroarch_Intel_Unknown,
177 /*[129(0x81)] = */ kCpumMicroarch_Intel_Unknown,
178 /*[130(0x82)] = */ kCpumMicroarch_Intel_Unknown,
179 /*[131(0x83)] = */ kCpumMicroarch_Intel_Unknown,
180 /*[132(0x84)] = */ kCpumMicroarch_Intel_Unknown,
181 /*[133(0x85)] = */ kCpumMicroarch_Intel_Phi_KnightsMill,
182 /*[134(0x86)] = */ kCpumMicroarch_Intel_Unknown,
183 /*[135(0x87)] = */ kCpumMicroarch_Intel_Unknown,
184 /*[136(0x88)] = */ kCpumMicroarch_Intel_Unknown,
185 /*[137(0x89)] = */ kCpumMicroarch_Intel_Unknown,
186 /*[138(0x8a)] = */ kCpumMicroarch_Intel_Unknown,
187 /*[139(0x8b)] = */ kCpumMicroarch_Intel_Unknown,
188 /*[140(0x8c)] = */ kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
189 /*[141(0x8d)] = */ kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
190 /*[142(0x8e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
191 /*[143(0x8f)] = */ kCpumMicroarch_Intel_Core7_SapphireRapids,
192 /*[144(0x90)] = */ kCpumMicroarch_Intel_Unknown,
193 /*[145(0x91)] = */ kCpumMicroarch_Intel_Unknown,
194 /*[146(0x92)] = */ kCpumMicroarch_Intel_Unknown,
195 /*[147(0x93)] = */ kCpumMicroarch_Intel_Unknown,
196 /*[148(0x94)] = */ kCpumMicroarch_Intel_Unknown,
197 /*[149(0x95)] = */ kCpumMicroarch_Intel_Unknown,
198 /*[150(0x96)] = */ kCpumMicroarch_Intel_Unknown,
199 /*[151(0x97)] = */ kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
200 /*[152(0x98)] = */ kCpumMicroarch_Intel_Unknown,
201 /*[153(0x99)] = */ kCpumMicroarch_Intel_Unknown,
202 /*[154(0x9a)] = */ kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
203 /*[155(0x9b)] = */ kCpumMicroarch_Intel_Unknown,
204 /*[156(0x9c)] = */ kCpumMicroarch_Intel_Unknown,
205 /*[157(0x9d)] = */ kCpumMicroarch_Intel_Unknown,
206 /*[158(0x9e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
207 /*[159(0x9f)] = */ kCpumMicroarch_Intel_Unknown,
208 /*[160(0xa0)] = */ kCpumMicroarch_Intel_Unknown,
209 /*[161(0xa1)] = */ kCpumMicroarch_Intel_Unknown,
210 /*[162(0xa2)] = */ kCpumMicroarch_Intel_Unknown,
211 /*[163(0xa3)] = */ kCpumMicroarch_Intel_Unknown,
212 /*[164(0xa4)] = */ kCpumMicroarch_Intel_Unknown,
213 /*[165(0xa5)] = */ kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
214 /*[166(0xa6)] = */ kCpumMicroarch_Intel_Unknown,
215 /*[167(0xa7)] = */ kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
216};
217AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
218
219
220/**
221 * Figures out the (sub-)micro architecture given a bit of CPUID info.
222 *
223 * @returns Micro architecture.
224 * @param enmVendor The CPU vendor.
225 * @param bFamily The CPU family.
226 * @param bModel The CPU model.
227 * @param bStepping The CPU stepping.
228 */
229VMMDECL(CPUMMICROARCH) CPUMCpuIdDetermineX86MicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
230 uint8_t bModel, uint8_t bStepping)
231{
232 if (enmVendor == CPUMCPUVENDOR_AMD)
233 {
234 switch (bFamily)
235 {
236 case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
237 case 0x03: return kCpumMicroarch_AMD_Am386;
238 case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
239 case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
240 case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
241 case 0x06:
242 switch (bModel)
243 {
244 case 0: return kCpumMicroarch_AMD_K7_Palomino;
245 case 1: return kCpumMicroarch_AMD_K7_Palomino;
246 case 2: return kCpumMicroarch_AMD_K7_Palomino;
247 case 3: return kCpumMicroarch_AMD_K7_Spitfire;
248 case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
249 case 6: return kCpumMicroarch_AMD_K7_Palomino;
250 case 7: return kCpumMicroarch_AMD_K7_Morgan;
251 case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
252 case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
253 }
254 return kCpumMicroarch_AMD_K7_Unknown;
255 case 0x0f:
256 /*
257 * This family is a friggin mess. Trying my best to make some
258 * sense out of it. Too much happened in the 0x0f family to
259 * lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
260 *
261 * Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
262 * cpu-world.com, and other places:
263 * - 130nm:
264 * - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
265 * - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
266 * - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
267 * - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
268 * - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
269 * - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
270 * - 90nm:
271 * - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
272 * - Oakville: 10FC0/DH-D0.
273 * - Georgetown: 10FC0/DH-D0.
274 * - Sonora: 10FC0/DH-D0.
275 * - Venus: 20F71/SH-E4
276 * - Troy: 20F51/SH-E4
277 * - Athens: 20F51/SH-E4
278 * - San Diego: 20F71/SH-E4.
279 * - Lancaster: 20F42/SH-E5
280 * - Newark: 20F42/SH-E5.
281 * - Albany: 20FC2/DH-E6.
282 * - Roma: 20FC2/DH-E6.
283 * - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
284 * - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
285 * - 90nm introducing Dual core:
286 * - Denmark: 20F30/JH-E1, 20F32/JH-E6
287 * - Italy: 20F10/JH-E1, 20F12/JH-E6
288 * - Egypt: 20F10/JH-E1, 20F12/JH-E6
289 * - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
290 * - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
291 * - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
292 * - Santa Ana: 40F32/JH-F2, /-F3
293 * - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
294 * - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
295 * - Manila: 50FF2/DH-F2, 40FF2/DH-F2
296 * - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
297 * - Keene: 40FC2/DH-F2.
298 * - Richmond: 40FC2/DH-F2
299 * - Taylor: 40F82/BH-F2
300 * - Trinidad: 40F82/BH-F2
301 *
302 * - 65nm:
303 * - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
304 * - Tyler: 60F81/BH-G1, 60F82/BH-G2.
305 * - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
306 * - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
307 * - Sherman: /-G1, 70FC2/DH-G2.
308 * - Huron: 70FF2/DH-G2.
309 */
310 if (bModel < 0x10)
311 return kCpumMicroarch_AMD_K8_130nm;
312 if (bModel >= 0x60 && bModel < 0x80)
313 return kCpumMicroarch_AMD_K8_65nm;
314 if (bModel >= 0x40)
315 return kCpumMicroarch_AMD_K8_90nm_AMDV;
316 switch (bModel)
317 {
318 case 0x21:
319 case 0x23:
320 case 0x2b:
321 case 0x2f:
322 case 0x37:
323 case 0x3f:
324 return kCpumMicroarch_AMD_K8_90nm_DualCore;
325 }
326 return kCpumMicroarch_AMD_K8_90nm;
327 case 0x10:
328 return kCpumMicroarch_AMD_K10;
329 case 0x11:
330 return kCpumMicroarch_AMD_K10_Lion;
331 case 0x12:
332 return kCpumMicroarch_AMD_K10_Llano;
333 case 0x14:
334 return kCpumMicroarch_AMD_Bobcat;
335 case 0x15:
336 switch (bModel)
337 {
338 case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
339 case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
340 case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
341 case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
342 case 0x11: /* ?? */
343 case 0x12: /* ?? */
344 case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
345 }
346 return kCpumMicroarch_AMD_15h_Unknown;
347 case 0x16:
348 return kCpumMicroarch_AMD_Jaguar;
349 case 0x17:
350 return kCpumMicroarch_AMD_Zen_Ryzen;
351 }
352 return kCpumMicroarch_AMD_Unknown;
353 }
354
355 if (enmVendor == CPUMCPUVENDOR_INTEL)
356 {
357 switch (bFamily)
358 {
359 case 3:
360 return kCpumMicroarch_Intel_80386;
361 case 4:
362 return kCpumMicroarch_Intel_80486;
363 case 5:
364 return kCpumMicroarch_Intel_P5;
365 case 6:
366 if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
367 {
368 CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
369 if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
370 {
371 if (bStepping >= 0xa && bStepping <= 0xc)
372 enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
373 else if (bStepping >= 0xc)
374 enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
375 }
376 else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
377 && bModel == 0x55
378 && bStepping >= 5)
379 enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
380 return enmMicroArch;
381 }
382 return kCpumMicroarch_Intel_Atom_Unknown;
383 case 15:
384 switch (bModel)
385 {
386 case 0: return kCpumMicroarch_Intel_NB_Willamette;
387 case 1: return kCpumMicroarch_Intel_NB_Willamette;
388 case 2: return kCpumMicroarch_Intel_NB_Northwood;
389 case 3: return kCpumMicroarch_Intel_NB_Prescott;
390 case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
391 case 5: return kCpumMicroarch_Intel_NB_Unknown; /*??*/
392 case 6: return kCpumMicroarch_Intel_NB_CedarMill;
393 case 7: return kCpumMicroarch_Intel_NB_Gallatin;
394 default: return kCpumMicroarch_Intel_NB_Unknown;
395 }
396 break;
397 /* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
398 case 0:
399 return kCpumMicroarch_Intel_8086;
400 case 1:
401 return kCpumMicroarch_Intel_80186;
402 case 2:
403 return kCpumMicroarch_Intel_80286;
404 }
405 return kCpumMicroarch_Intel_Unknown;
406 }
407
408 if (enmVendor == CPUMCPUVENDOR_VIA)
409 {
410 switch (bFamily)
411 {
412 case 5:
413 switch (bModel)
414 {
415 case 1: return kCpumMicroarch_Centaur_C6;
416 case 4: return kCpumMicroarch_Centaur_C6;
417 case 8: return kCpumMicroarch_Centaur_C2;
418 case 9: return kCpumMicroarch_Centaur_C3;
419 }
420 break;
421
422 case 6:
423 switch (bModel)
424 {
425 case 5: return kCpumMicroarch_VIA_C3_M2;
426 case 6: return kCpumMicroarch_VIA_C3_C5A;
427 case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
428 case 8: return kCpumMicroarch_VIA_C3_C5N;
429 case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
430 case 10: return kCpumMicroarch_VIA_C7_C5J;
431 case 15: return kCpumMicroarch_VIA_Isaiah;
432 }
433 break;
434 }
435 return kCpumMicroarch_VIA_Unknown;
436 }
437
438 if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
439 {
440 switch (bFamily)
441 {
442 case 6:
443 case 7:
444 return kCpumMicroarch_Shanghai_Wudaokou;
445 default:
446 break;
447 }
448 return kCpumMicroarch_Shanghai_Unknown;
449 }
450
451 if (enmVendor == CPUMCPUVENDOR_CYRIX)
452 {
453 switch (bFamily)
454 {
455 case 4:
456 switch (bModel)
457 {
458 case 9: return kCpumMicroarch_Cyrix_5x86;
459 }
460 break;
461
462 case 5:
463 switch (bModel)
464 {
465 case 2: return kCpumMicroarch_Cyrix_M1;
466 case 4: return kCpumMicroarch_Cyrix_MediaGX;
467 case 5: return kCpumMicroarch_Cyrix_MediaGXm;
468 }
469 break;
470
471 case 6:
472 switch (bModel)
473 {
474 case 0: return kCpumMicroarch_Cyrix_M2;
475 }
476 break;
477
478 }
479 return kCpumMicroarch_Cyrix_Unknown;
480 }
481
482 if (enmVendor == CPUMCPUVENDOR_HYGON)
483 {
484 switch (bFamily)
485 {
486 case 0x18:
487 return kCpumMicroarch_Hygon_Dhyana;
488 default:
489 break;
490 }
491 return kCpumMicroarch_Hygon_Unknown;
492 }
493
494 return kCpumMicroarch_Unknown;
495}
496
497
498/**
499 * Translates a microarchitecture enum value to the corresponding string
500 * constant.
501 *
502 * @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
503 * NULL if the value is invalid.
504 *
505 * @param enmMicroarch The enum value to convert.
506 */
507VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch)
508{
509 switch (enmMicroarch)
510 {
511#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
512 CASE_RET_STR(kCpumMicroarch_Intel_8086);
513 CASE_RET_STR(kCpumMicroarch_Intel_80186);
514 CASE_RET_STR(kCpumMicroarch_Intel_80286);
515 CASE_RET_STR(kCpumMicroarch_Intel_80386);
516 CASE_RET_STR(kCpumMicroarch_Intel_80486);
517 CASE_RET_STR(kCpumMicroarch_Intel_P5);
518
519 CASE_RET_STR(kCpumMicroarch_Intel_P6);
520 CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
521 CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
522
523 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
524 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
525 CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
526
527 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
528 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
529
530 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
531 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
532 CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
533 CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
534 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
535 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
536 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
537 CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
538 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
539 CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
540 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
541 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
542 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
543 CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
544 CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
545 CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
546 CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
547 CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
548
549 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
550 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
551 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
552 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
553 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
554 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
555 CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
556 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
557
558 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
559 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
560 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
561 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
562 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
563
564 CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
565 CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
566 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
567 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
568 CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
569 CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
570 CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
571
572 CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
573
574 CASE_RET_STR(kCpumMicroarch_AMD_Am286);
575 CASE_RET_STR(kCpumMicroarch_AMD_Am386);
576 CASE_RET_STR(kCpumMicroarch_AMD_Am486);
577 CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
578 CASE_RET_STR(kCpumMicroarch_AMD_K5);
579 CASE_RET_STR(kCpumMicroarch_AMD_K6);
580
581 CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
582 CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
583 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
584 CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
585 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
586 CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
587 CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
588
589 CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
590 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
591 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
592 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
593 CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
594
595 CASE_RET_STR(kCpumMicroarch_AMD_K10);
596 CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
597 CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
598 CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
599 CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
600
601 CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
602 CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
603 CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
604 CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
605 CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
606
607 CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
608
609 CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
610
611 CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
612
613 CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
614 CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
615
616 CASE_RET_STR(kCpumMicroarch_Centaur_C6);
617 CASE_RET_STR(kCpumMicroarch_Centaur_C2);
618 CASE_RET_STR(kCpumMicroarch_Centaur_C3);
619 CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
620 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
621 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
622 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
623 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
624 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
625 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
626 CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
627 CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
628 CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
629
630 CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
631 CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
632
633 CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
634 CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
635 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
636 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
637 CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
638 CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
639
640 CASE_RET_STR(kCpumMicroarch_NEC_V20);
641 CASE_RET_STR(kCpumMicroarch_NEC_V30);
642
643 CASE_RET_STR(kCpumMicroarch_Unknown);
644
645#undef CASE_RET_STR
646 case kCpumMicroarch_Invalid:
647 case kCpumMicroarch_Intel_End:
648 case kCpumMicroarch_Intel_Core2_End:
649 case kCpumMicroarch_Intel_Core7_End:
650 case kCpumMicroarch_Intel_Atom_End:
651 case kCpumMicroarch_Intel_P6_Core_Atom_End:
652 case kCpumMicroarch_Intel_Phi_End:
653 case kCpumMicroarch_Intel_NB_End:
654 case kCpumMicroarch_AMD_K7_End:
655 case kCpumMicroarch_AMD_K8_End:
656 case kCpumMicroarch_AMD_15h_End:
657 case kCpumMicroarch_AMD_16h_End:
658 case kCpumMicroarch_AMD_Zen_End:
659 case kCpumMicroarch_AMD_End:
660 case kCpumMicroarch_Hygon_End:
661 case kCpumMicroarch_VIA_End:
662 case kCpumMicroarch_Shanghai_End:
663 case kCpumMicroarch_Cyrix_End:
664 case kCpumMicroarch_NEC_End:
665 case kCpumMicroarch_32BitHack:
666 break;
667 /* no default! */
668 }
669
670 return NULL;
671}
672
673
674/**
675 * Gets a matching leaf in the CPUID leaf array.
676 *
677 * @returns Pointer to the matching leaf, or NULL if not found.
678 * @param paLeaves The CPUID leaves to search. This is sorted.
679 * @param cLeaves The number of leaves in the array.
680 * @param uLeaf The leaf to locate.
681 * @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
682 */
683PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
684{
685 /* Lazy bird does linear lookup here since this is only used for the
686 occational CPUID overrides. */
687 for (uint32_t i = 0; i < cLeaves; i++)
688 if ( paLeaves[i].uLeaf == uLeaf
689 && paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
690 return &paLeaves[i];
691 return NULL;
692}
693
694
695/**
696 * Ensures that the CPUID leaf array can hold one more leaf.
697 *
698 * @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
699 * failure.
700 * @param pVM The cross context VM structure. If NULL, use
701 * the process heap, otherwise the VM's hyper heap.
702 * @param ppaLeaves Pointer to the variable holding the array pointer
703 * (input/output).
704 * @param cLeaves The current array size.
705 *
706 * @remarks This function will automatically update the R0 and RC pointers when
707 * using the hyper heap, which means @a ppaLeaves and @a cLeaves must
708 * be the corresponding VM's CPUID arrays (which is asserted).
709 */
710PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
711{
712 /*
713 * If pVM is not specified, we're on the regular heap and can waste a
714 * little space to speed things up.
715 */
716 uint32_t cAllocated;
717 if (!pVM)
718 {
719 cAllocated = RT_ALIGN(cLeaves, 16);
720 if (cLeaves + 1 > cAllocated)
721 {
722 void *pvNew = RTMemRealloc(*ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
723 if (pvNew)
724 *ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
725 else
726 {
727 RTMemFree(*ppaLeaves);
728 *ppaLeaves = NULL;
729 }
730 }
731 }
732 /*
733 * Otherwise, we're on the hyper heap and are probably just inserting
734 * one or two leaves and should conserve space.
735 */
736 else
737 {
738#ifdef IN_VBOX_CPU_REPORT
739 AssertReleaseFailed();
740#else
741# ifdef IN_RING3
742 Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
743 Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves);
744 Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
745
746 if (cLeaves + 1 <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves))
747 { }
748 else
749# endif
750 {
751 *ppaLeaves = NULL;
752 LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n"));
753 }
754#endif
755 }
756 return *ppaLeaves;
757}
758
759
760#ifdef VBOX_STRICT
761/**
762 * Checks that we've updated the CPUID leaves array correctly.
763 *
764 * This is a no-op in non-strict builds.
765 *
766 * @param paLeaves The leaves array.
767 * @param cLeaves The number of leaves.
768 */
769void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
770{
771 for (uint32_t i = 1; i < cLeaves; i++)
772 if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
773 AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
774 else
775 {
776 AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
777 ("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
778 AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
779 ("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
780 AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
781 ("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
782 }
783}
784#endif
785
786#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
787
788/**
789 * Append a CPUID leaf or sub-leaf.
790 *
791 * ASSUMES linear insertion order, so we'll won't need to do any searching or
792 * replace anything. Use cpumR3CpuIdInsert() for those cases.
793 *
794 * @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
795 * the caller need do no more work.
796 * @param ppaLeaves Pointer to the pointer to the array of sorted
797 * CPUID leaves and sub-leaves.
798 * @param pcLeaves Where we keep the leaf count for *ppaLeaves.
799 * @param uLeaf The leaf we're adding.
800 * @param uSubLeaf The sub-leaf number.
801 * @param fSubLeafMask The sub-leaf mask.
802 * @param uEax The EAX value.
803 * @param uEbx The EBX value.
804 * @param uEcx The ECX value.
805 * @param uEdx The EDX value.
806 * @param fFlags The flags.
807 */
808static int cpumCollectCpuIdInfoAddOne(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves,
809 uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
810 uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
811{
812 if (!cpumCpuIdEnsureSpace(NULL /* pVM */, ppaLeaves, *pcLeaves))
813 return VERR_NO_MEMORY;
814
815 PCPUMCPUIDLEAF pNew = &(*ppaLeaves)[*pcLeaves];
816 Assert( *pcLeaves == 0
817 || pNew[-1].uLeaf < uLeaf
818 || (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
819
820 pNew->uLeaf = uLeaf;
821 pNew->uSubLeaf = uSubLeaf;
822 pNew->fSubLeafMask = fSubLeafMask;
823 pNew->uEax = uEax;
824 pNew->uEbx = uEbx;
825 pNew->uEcx = uEcx;
826 pNew->uEdx = uEdx;
827 pNew->fFlags = fFlags;
828
829 *pcLeaves += 1;
830 return VINF_SUCCESS;
831}
832
833
834/**
835 * Checks if ECX make a difference when reading a given CPUID leaf.
836 *
837 * @returns @c true if it does, @c false if it doesn't.
838 * @param uLeaf The leaf we're reading.
839 * @param pcSubLeaves Number of sub-leaves accessible via ECX.
840 * @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
841 * final sub-leaf (for leaf 0xb only).
842 */
843static bool cpumIsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t *pcSubLeaves, bool *pfFinalEcxUnchanged)
844{
845 *pfFinalEcxUnchanged = false;
846
847 uint32_t auCur[4];
848 uint32_t auPrev[4];
849 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
850
851 /* Look for sub-leaves. */
852 uint32_t uSubLeaf = 1;
853 for (;;)
854 {
855 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
856 if (memcmp(auCur, auPrev, sizeof(auCur)))
857 break;
858
859 /* Advance / give up. */
860 uSubLeaf++;
861 if (uSubLeaf >= 64)
862 {
863 *pcSubLeaves = 1;
864 return false;
865 }
866 }
867
868 /* Count sub-leaves. */
869 uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
870 uint32_t cRepeats = 0;
871 uSubLeaf = 0;
872 for (;;)
873 {
874 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
875
876 /* Figuring out when to stop isn't entirely straight forward as we need
877 to cover undocumented behavior up to a point and implementation shortcuts. */
878
879 /* 1. Look for more than 4 repeating value sets. */
880 if ( auCur[0] == auPrev[0]
881 && auCur[1] == auPrev[1]
882 && ( auCur[2] == auPrev[2]
883 || ( auCur[2] == uSubLeaf
884 && auPrev[2] == uSubLeaf - 1) )
885 && auCur[3] == auPrev[3])
886 {
887 if ( uLeaf != 0xd
888 || uSubLeaf >= 64
889 || ( auCur[0] == 0
890 && auCur[1] == 0
891 && auCur[2] == 0
892 && auCur[3] == 0
893 && auPrev[2] == 0) )
894 cRepeats++;
895 if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
896 break;
897 }
898 else
899 cRepeats = 0;
900
901 /* 2. Look for zero values. */
902 if ( auCur[0] == 0
903 && auCur[1] == 0
904 && (auCur[2] == 0 || auCur[2] == uSubLeaf)
905 && (auCur[3] == 0 || uLeaf == 0xb /* edx is fixed */)
906 && uSubLeaf >= cMinLeaves)
907 {
908 cRepeats = 0;
909 break;
910 }
911
912 /* 3. Leaf 0xb level type 0 check. */
913 if ( uLeaf == 0xb
914 && (auCur[2] & 0xff00) == 0
915 && (auPrev[2] & 0xff00) == 0)
916 {
917 cRepeats = 0;
918 break;
919 }
920
921 /* 99. Give up. */
922 if (uSubLeaf >= 128)
923 {
924# ifndef IN_VBOX_CPU_REPORT
925 /* Ok, limit it according to the documentation if possible just to
926 avoid annoying users with these detection issues. */
927 uint32_t cDocLimit = UINT32_MAX;
928 if (uLeaf == 0x4)
929 cDocLimit = 4;
930 else if (uLeaf == 0x7)
931 cDocLimit = 1;
932 else if (uLeaf == 0xd)
933 cDocLimit = 63;
934 else if (uLeaf == 0xf)
935 cDocLimit = 2;
936 if (cDocLimit != UINT32_MAX)
937 {
938 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
939 *pcSubLeaves = cDocLimit + 3;
940 return true;
941 }
942# endif
943 *pcSubLeaves = UINT32_MAX;
944 return true;
945 }
946
947 /* Advance. */
948 uSubLeaf++;
949 memcpy(auPrev, auCur, sizeof(auCur));
950 }
951
952 /* Standard exit. */
953 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
954 *pcSubLeaves = uSubLeaf + 1 - cRepeats;
955 if (*pcSubLeaves == 0)
956 *pcSubLeaves = 1;
957 return true;
958}
959
960
961/**
962 * Collects CPUID leaves and sub-leaves, returning a sorted array of them.
963 *
964 * @returns VBox status code.
965 * @param ppaLeaves Where to return the array pointer on success.
966 * Use RTMemFree to release.
967 * @param pcLeaves Where to return the size of the array on
968 * success.
969 */
970VMMDECL(int) CPUMCpuIdCollectLeavesX86(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
971{
972 *ppaLeaves = NULL;
973 *pcLeaves = 0;
974
975 /*
976 * Try out various candidates. This must be sorted!
977 */
978 static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
979 {
980 { UINT32_C(0x00000000), false },
981 { UINT32_C(0x10000000), false },
982 { UINT32_C(0x20000000), false },
983 { UINT32_C(0x30000000), false },
984 { UINT32_C(0x40000000), false },
985 { UINT32_C(0x50000000), false },
986 { UINT32_C(0x60000000), false },
987 { UINT32_C(0x70000000), false },
988 { UINT32_C(0x80000000), false },
989 { UINT32_C(0x80860000), false },
990 { UINT32_C(0x8ffffffe), true },
991 { UINT32_C(0x8fffffff), true },
992 { UINT32_C(0x90000000), false },
993 { UINT32_C(0xa0000000), false },
994 { UINT32_C(0xb0000000), false },
995 { UINT32_C(0xc0000000), false },
996 { UINT32_C(0xd0000000), false },
997 { UINT32_C(0xe0000000), false },
998 { UINT32_C(0xf0000000), false },
999 };
1000
1001 for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1002 {
1003 uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1004 uint32_t uEax, uEbx, uEcx, uEdx;
1005 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1006
1007 /*
1008 * Does EAX look like a typical leaf count value?
1009 */
1010 if ( uEax > uLeaf
1011 && uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1012 {
1013 /* Yes, dump them. */
1014 uint32_t cLeaves = uEax - uLeaf + 1;
1015 while (cLeaves-- > 0)
1016 {
1017 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1018
1019 uint32_t fFlags = 0;
1020
1021 /* There are currently three known leaves containing an APIC ID
1022 that needs EMT specific attention */
1023 if (uLeaf == 1)
1024 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1025 else if (uLeaf == 0xb && uEcx != 0)
1026 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1027 else if ( uLeaf == UINT32_C(0x8000001e)
1028 && ( uEax
1029 || uEbx
1030 || uEdx
1031 || RTX86IsAmdCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1032 || RTX86IsHygonCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1033 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1034
1035 /* The APIC bit is per-VCpu and needs flagging. */
1036 if (uLeaf == 1)
1037 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1038 else if ( uLeaf == UINT32_C(0x80000001)
1039 && ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1040 || RTX86IsAmdCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1041 || RTX86IsHygonCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1042 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1043
1044 /* Check three times here to reduce the chance of CPU migration
1045 resulting in false positives with things like the APIC ID. */
1046 uint32_t cSubLeaves;
1047 bool fFinalEcxUnchanged;
1048 if ( cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1049 && cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1050 && cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1051 {
1052 if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1053 {
1054 /* This shouldn't happen. But in case it does, file all
1055 relevant details in the release log. */
1056 LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1057 LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1058 for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1059 {
1060 uint32_t auTmp[4];
1061 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1062 LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1063 uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1064 }
1065 LogRel(("----------------- dump of what we've found so far -----------------\n"));
1066 for (uint32_t i = 0 ; i < *pcLeaves; i++)
1067 LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1068 (*ppaLeaves)[i].uLeaf, (*ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1069 (*ppaLeaves)[i].uEax, (*ppaLeaves)[i].uEbx, (*ppaLeaves)[i].uEcx, (*ppaLeaves)[i].uEdx));
1070 LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1071 return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1072 }
1073
1074 if (fFinalEcxUnchanged)
1075 fFlags |= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1076
1077 for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1078 {
1079 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1080 int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1081 uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1082 if (RT_FAILURE(rc))
1083 return rc;
1084 }
1085 }
1086 else
1087 {
1088 int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves, uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1089 if (RT_FAILURE(rc))
1090 return rc;
1091 }
1092
1093 /* next */
1094 uLeaf++;
1095 }
1096 }
1097 /*
1098 * Special CPUIDs needs special handling as they don't follow the
1099 * leaf count principle used above.
1100 */
1101 else if (s_aCandidates[iOuter].fSpecial)
1102 {
1103 bool fKeep = false;
1104 if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1105 fKeep = true;
1106 else if ( uLeaf == 0x8fffffff
1107 && RT_C_IS_PRINT(RT_BYTE1(uEax))
1108 && RT_C_IS_PRINT(RT_BYTE2(uEax))
1109 && RT_C_IS_PRINT(RT_BYTE3(uEax))
1110 && RT_C_IS_PRINT(RT_BYTE4(uEax))
1111 && RT_C_IS_PRINT(RT_BYTE1(uEbx))
1112 && RT_C_IS_PRINT(RT_BYTE2(uEbx))
1113 && RT_C_IS_PRINT(RT_BYTE3(uEbx))
1114 && RT_C_IS_PRINT(RT_BYTE4(uEbx))
1115 && RT_C_IS_PRINT(RT_BYTE1(uEcx))
1116 && RT_C_IS_PRINT(RT_BYTE2(uEcx))
1117 && RT_C_IS_PRINT(RT_BYTE3(uEcx))
1118 && RT_C_IS_PRINT(RT_BYTE4(uEcx))
1119 && RT_C_IS_PRINT(RT_BYTE1(uEdx))
1120 && RT_C_IS_PRINT(RT_BYTE2(uEdx))
1121 && RT_C_IS_PRINT(RT_BYTE3(uEdx))
1122 && RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1123 fKeep = true;
1124 if (fKeep)
1125 {
1126 int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves, uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1127 if (RT_FAILURE(rc))
1128 return rc;
1129 }
1130 }
1131 }
1132
1133# ifdef VBOX_STRICT
1134 cpumCpuIdAssertOrder(*ppaLeaves, *pcLeaves);
1135# endif
1136 return VINF_SUCCESS;
1137}
1138#endif /* RT_ARCH_X86 || RT_ARCH_AMD64 */
1139
1140
1141/**
1142 * Detect the CPU vendor give n the
1143 *
1144 * @returns The vendor.
1145 * @param uEAX EAX from CPUID(0).
1146 * @param uEBX EBX from CPUID(0).
1147 * @param uECX ECX from CPUID(0).
1148 * @param uEDX EDX from CPUID(0).
1149 */
1150VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1151{
1152 if (RTX86IsValidStdRange(uEAX))
1153 {
1154 if (RTX86IsAmdCpu(uEBX, uECX, uEDX))
1155 return CPUMCPUVENDOR_AMD;
1156
1157 if (RTX86IsIntelCpu(uEBX, uECX, uEDX))
1158 return CPUMCPUVENDOR_INTEL;
1159
1160 if (RTX86IsViaCentaurCpu(uEBX, uECX, uEDX))
1161 return CPUMCPUVENDOR_VIA;
1162
1163 if (RTX86IsShanghaiCpu(uEBX, uECX, uEDX))
1164 return CPUMCPUVENDOR_SHANGHAI;
1165
1166 if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1167 && uECX == UINT32_C(0x64616574)
1168 && uEDX == UINT32_C(0x736E4978))
1169 return CPUMCPUVENDOR_CYRIX;
1170
1171 if (RTX86IsHygonCpu(uEBX, uECX, uEDX))
1172 return CPUMCPUVENDOR_HYGON;
1173
1174 /* "Geode by NSC", example: family 5, model 9. */
1175
1176 /** @todo detect the other buggers... */
1177 }
1178
1179 return CPUMCPUVENDOR_UNKNOWN;
1180}
1181
1182
1183/**
1184 * Translates a CPU vendor enum value into the corresponding string constant.
1185 *
1186 * The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1187 * value name. This can be useful when generating code.
1188 *
1189 * @returns Read only name string.
1190 * @param enmVendor The CPU vendor value.
1191 */
1192VMMDECL(const char *) CPUMCpuVendorName(CPUMCPUVENDOR enmVendor)
1193{
1194 switch (enmVendor)
1195 {
1196 case CPUMCPUVENDOR_INTEL: return "INTEL";
1197 case CPUMCPUVENDOR_AMD: return "AMD";
1198 case CPUMCPUVENDOR_VIA: return "VIA";
1199 case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1200 case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1201 case CPUMCPUVENDOR_HYGON: return "HYGON";
1202 case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1203
1204 case CPUMCPUVENDOR_INVALID:
1205 case CPUMCPUVENDOR_32BIT_HACK:
1206 break;
1207 }
1208 return "Invalid-cpu-vendor";
1209}
1210
1211
1212static PCCPUMCPUIDLEAF cpumCpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1213{
1214 /* Could do binary search, doing linear now because I'm lazy. */
1215 PCCPUMCPUIDLEAF pLeaf = paLeaves;
1216 while (cLeaves-- > 0)
1217 {
1218 if (pLeaf->uLeaf == uLeaf)
1219 return pLeaf;
1220 pLeaf++;
1221 }
1222 return NULL;
1223}
1224
1225
1226static PCCPUMCPUIDLEAF cpumCpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1227{
1228 PCCPUMCPUIDLEAF pLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1229 if ( !pLeaf
1230 || pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1231 return pLeaf;
1232
1233 /* Linear sub-leaf search. Lazy as usual. */
1234 cLeaves -= pLeaf - paLeaves;
1235 while ( cLeaves-- > 0
1236 && pLeaf->uLeaf == uLeaf)
1237 {
1238 if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1239 return pLeaf;
1240 pLeaf++;
1241 }
1242
1243 return NULL;
1244}
1245
1246
1247static void cpumExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1248{
1249 Assert(pVmxMsrs);
1250 Assert(pFeatures);
1251 Assert(pFeatures->fVmx);
1252
1253 /* Basic information. */
1254 bool const fVmxTrueMsrs = RT_BOOL(pVmxMsrs->u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
1255 {
1256 uint64_t const u64Basic = pVmxMsrs->u64Basic;
1257 pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1258 }
1259
1260 /* Pin-based VM-execution controls. */
1261 {
1262 uint32_t const fPinCtls = fVmxTrueMsrs ? pVmxMsrs->TruePinCtls.n.allowed1 : pVmxMsrs->PinCtls.n.allowed1;
1263 pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1264 pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1265 pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1266 pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1267 pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1268 }
1269
1270 /* Processor-based VM-execution controls. */
1271 {
1272 uint32_t const fProcCtls = fVmxTrueMsrs ? pVmxMsrs->TrueProcCtls.n.allowed1 : pVmxMsrs->ProcCtls.n.allowed1;
1273 pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1274 pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1275 pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1276 pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1277 pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1278 pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1279 pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1280 pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1281 pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1282 pFeatures->fVmxTertiaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1283 pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1284 pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1285 pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1286 pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1287 pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1288 pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1289 pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1290 pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1291 pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1292 pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1293 pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1294 pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1295 }
1296
1297 /* Secondary processor-based VM-execution controls. */
1298 {
1299 uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1300 pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1301 pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1302 pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1303 pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1304 pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1305 pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1306 pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1307 pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1308 pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1309 pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1310 pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1311 pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1312 pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1313 pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1314 pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1315 pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1316 pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1317 pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE);
1318 pFeatures->fVmxConcealVmxFromPt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1319 pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1320 pFeatures->fVmxModeBasedExecuteEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1321 pFeatures->fVmxSppEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_SPP_EPT);
1322 pFeatures->fVmxPtEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PT_EPT);
1323 pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1324 pFeatures->fVmxUserWaitPause = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1325 pFeatures->fVmxEnclvExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_ENCLV_EXIT);
1326 }
1327
1328 /* Tertiary processor-based VM-execution controls. */
1329 {
1330 uint64_t const fProcCtls3 = pFeatures->fVmxTertiaryExecCtls ? pVmxMsrs->u64ProcCtls3 : 0;
1331 pFeatures->fVmxLoadIwKeyExit = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT);
1332 }
1333
1334 /* VM-exit controls. */
1335 {
1336 uint32_t const fExitCtls = fVmxTrueMsrs ? pVmxMsrs->TrueExitCtls.n.allowed1 : pVmxMsrs->ExitCtls.n.allowed1;
1337 pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1338 pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1339 pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1340 pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1341 pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1342 pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1343 pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1344 pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1345 }
1346
1347 /* VM-entry controls. */
1348 {
1349 uint32_t const fEntryCtls = fVmxTrueMsrs ? pVmxMsrs->TrueEntryCtls.n.allowed1 : pVmxMsrs->EntryCtls.n.allowed1;
1350 pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1351 pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1352 pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1353 pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1354 }
1355
1356 /* Miscellaneous data. */
1357 {
1358 uint32_t const fMiscData = pVmxMsrs->u64Misc;
1359 pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1360 pFeatures->fVmxPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1361 pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1362 pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1363 }
1364}
1365
1366
1367int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1368{
1369 Assert(pMsrs);
1370 RT_ZERO(*pFeatures);
1371 if (cLeaves >= 2)
1372 {
1373 AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1374 AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1375 PCCPUMCPUIDLEAF const pStd0Leaf = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1376 AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1377 PCCPUMCPUIDLEAF const pStd1Leaf = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1378 AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1379
1380 pFeatures->enmCpuVendor = CPUMCpuIdDetectX86VendorEx(pStd0Leaf->uEax,
1381 pStd0Leaf->uEbx,
1382 pStd0Leaf->uEcx,
1383 pStd0Leaf->uEdx);
1384 pFeatures->uFamily = RTX86GetCpuFamily(pStd1Leaf->uEax);
1385 pFeatures->uModel = RTX86GetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1386 pFeatures->uStepping = RTX86GetCpuStepping(pStd1Leaf->uEax);
1387 pFeatures->enmMicroarch = CPUMCpuIdDetermineX86MicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1388 pFeatures->uFamily,
1389 pFeatures->uModel,
1390 pFeatures->uStepping);
1391
1392 PCCPUMCPUIDLEAF const pExtLeaf8 = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1393 if (pExtLeaf8)
1394 {
1395 pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1396 pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1397 }
1398 else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1399 {
1400 pFeatures->cMaxPhysAddrWidth = 36;
1401 pFeatures->cMaxLinearAddrWidth = 36;
1402 }
1403 else
1404 {
1405 pFeatures->cMaxPhysAddrWidth = 32;
1406 pFeatures->cMaxLinearAddrWidth = 32;
1407 }
1408
1409 /* Standard features. */
1410 pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1411 pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1412 pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1413 pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1414 pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1415 pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1416 pFeatures->fPge = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PGE);
1417 pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1418 pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1419 pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1420 pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1421 pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1422 pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1423 pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1424 pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1425 pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1426 pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1427 pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1428 pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1429 pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1430 pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1431 pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1432 pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1433 pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1434 pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1435 pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1436 pFeatures->fRdRand = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_RDRAND);
1437 pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1438 if (pFeatures->fVmx)
1439 cpumExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1440
1441 /* Structured extended features. */
1442 PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1443 if (pSxfLeaf0)
1444 {
1445 pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1446 pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1447 pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1448 pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1449 pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1450 pFeatures->fBmi1 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI1);
1451 pFeatures->fBmi2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1452 pFeatures->fRdSeed = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_RDSEED);
1453
1454 pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1455 pFeatures->fIbrs = pFeatures->fIbpb;
1456 pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1457 pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1458 pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1459 pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1460 }
1461
1462 /* MWAIT/MONITOR leaf. */
1463 PCCPUMCPUIDLEAF const pMWaitLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 5);
1464 if (pMWaitLeaf)
1465 pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1466 == (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1467
1468 /* Extended features. */
1469 PCCPUMCPUIDLEAF const pExtLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1470 if (pExtLeaf)
1471 {
1472 pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1473 pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1474 pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1475 pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1476 pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1477 pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1478 pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1479 pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1480 || (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1481 | X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1482 }
1483
1484 /* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1485 pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1486
1487 if ( pExtLeaf
1488 && ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1489 || pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
1490 {
1491 /* AMD features. */
1492 pFeatures->fMsr |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1493 pFeatures->fApic |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1494 pFeatures->fPse |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1495 pFeatures->fPse36 |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1496 pFeatures->fPae |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1497 pFeatures->fPge |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PGE);
1498 pFeatures->fPat |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1499 pFeatures->fFxSaveRstor |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1500 pFeatures->fMmx |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1501 pFeatures->fTsc |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1502 pFeatures->fIbpb |= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1503 pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1504 pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1505 pFeatures->fAbm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_ABM);
1506 pFeatures->fTbm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_TBM);
1507 pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1508 if (pFeatures->fSvm)
1509 {
1510 PCCPUMCPUIDLEAF pSvmLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1511 AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1512 pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1513 pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1514 pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1515 pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1516 pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1517 pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1518 pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1519 pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1520 pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1521 pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1522 pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1523 pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1524 pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1525 pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
1526 pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1527 }
1528 }
1529
1530 /*
1531 * Quirks.
1532 */
1533 pFeatures->fLeakyFxSR = pExtLeaf
1534 && (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1535 && ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1536 && pFeatures->uFamily >= 6 /* K7 and up */)
1537 || pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
1538
1539 /*
1540 * Max extended (/FPU) state.
1541 */
1542 pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1543 if (pFeatures->fXSaveRstor)
1544 {
1545 PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1546 if (pXStateLeaf0)
1547 {
1548 if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1549 && pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1550 && RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1551 && pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1552 && pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1553 && RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1554 {
1555 pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1556
1557 /* (paranoia:) */
1558 PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1559 if ( pXStateLeaf1
1560 && pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1561 && pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1562 && (pXStateLeaf1->uEcx || pXStateLeaf1->uEdx) )
1563 pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1564 }
1565 else
1566 AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1567 pFeatures->fXSaveRstor = 0);
1568 }
1569 else
1570 AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1571 pFeatures->fXSaveRstor = 0);
1572 }
1573 }
1574 else
1575 AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1576 return VINF_SUCCESS;
1577}
1578
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