VMM.cpp@ 4050

Last change on this file since 4050 was 4013, checked in by vboxsync, 17 years ago
pdm.h = include pdm*.h; pdmapi.h = only the 'core' pdm APIs.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 96.6 KB

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1	/* $Id: VMM.cpp 4013 2007-08-03 00:11:38Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor Core.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	//#define NO_SUPCALLR0VMM
23
24	/** @page pg_vmm VMM - The Virtual Machine Monitor
25	*
26	* !Revise this! It's already incorrect!
27	*
28	* The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
29	* manages the alternate reality; controlling the virtualization, managing
30	* resources, tracking CPU state, it's resources and so on...
31	*
32	* We will split the VMM into smaller entities:
33	*
34	* - Virtual Machine Core Monitor (VMCM), which purpose it is to
35	* provide ring and world switching, that including routing
36	* interrupts to the host OS and traps to the appropriate trap
37	* handlers. It will implement an external interface for
38	* managing trap handlers.
39	*
40	* - CPU Monitor (CM), tracking the state of the CPU (in the alternate
41	* reality) and implementing external interfaces to read and change
42	* the state.
43	*
44	* - Memory Monitor (MM), which purpose it is to virtualize physical
45	* pages, segment descriptor tables, interrupt descriptor tables, task
46	* segments, and keep track of all memory providing external interfaces
47	* to access content and map pages. (Internally splitt into smaller entities!)
48	*
49	* - IO Monitor (IOM), which virtualizes in and out I/O operations. It
50	* interacts with the MM to implement memory mapped I/O. External
51	* interfaces for adding and removing I/O ranges are implemented.
52	*
53	* - External Interrupt Monitor (EIM), which purpose it is to manage
54	* interrupts generated by virtual devices. This monitor provides
55	* an interfaces for raising interrupts which is accessible at any
56	* time and from all thread.
57	* <p>
58	* A subentity of the EIM is the vitual Programmable Interrupt
59	* Controller Device (VPICD), and perhaps a virtual I/O Advanced
60	* Programmable Interrupt Controller Device (VAPICD).
61	*
62	* - Direct Memory Access Monitor (DMAM), which purpose it is to support
63	* virtual device using the DMA controller. Interfaces must be as the
64	* EIM interfaces independent and threadable.
65	* <p>
66	* A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
67	*
68	*
69	* Entities working on a higher level:
70	*
71	* - Device Manager (DM), which is a support facility for virtualized
72	* hardware. This provides generic facilities for efficient device
73	* virtualization. It will manage device attaching and detaching
74	* conversing with EIM and IOM.
75	*
76	* - Debugger Facility (DBGF) provides the basic features for
77	* debugging the alternate reality execution.
78	*
79	*
80	*
81	* @section pg_vmm_s_use_cases Use Cases
82	*
83	* @subsection pg_vmm_s_use_case_boot Bootstrap
84	*
85	* - Basic Init:
86	* - Init SUPDRV.
87	*
88	* - Init Virtual Machine Instance:
89	* - Load settings.
90	* - Check resource requirements (memory, com, stuff).
91	*
92	* - Init Host Ring 3 part:
93	* - Init Core code.
94	* - Load Pluggable Components.
95	* - Init Pluggable Components.
96	*
97	* - Init Host Ring 0 part:
98	* - Load Core (core = core components like VMM, RMI, CA, and so on) code.
99	* - Init Core code.
100	* - Load Pluggable Component code.
101	* - Init Pluggable Component code.
102	*
103	* - Allocate first chunk of memory and pin it down. This block of memory
104	* will fit the following pieces:
105	* - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
106	* (This is available from everywhere (at different addresses though)).
107	* - VMM Guest Context code.
108	* - Pluggable devices Guest Context code.
109	* - Page tables (directory and everything) for the VMM Guest
110	*
111	* - Setup Guest (Ring 0) part:
112	* - Setup initial page tables (i.e. directory all the stuff).
113	* - Load Core Guest Context code.
114	* - Load Pluggable Devices Guest Context code.
115	*
116	*
117	*/
118
119
120	/*******************************************************************************
121	* Header Files *
122	*******************************************************************************/
123	#define LOG_GROUP LOG_GROUP_VMM
124	#include <VBox/vmm.h>
125	#include <VBox/vmapi.h>
126	#include <VBox/pgm.h>
127	#include <VBox/cfgm.h>
128	#include <VBox/pdmqueue.h>
129	#include <VBox/pdmapi.h>
130	#include <VBox/cpum.h>
131	#include <VBox/mm.h>
132	#include <VBox/iom.h>
133	#include <VBox/trpm.h>
134	#include <VBox/selm.h>
135	#include <VBox/em.h>
136	#include <VBox/sup.h>
137	#include <VBox/dbgf.h>
138	#include <VBox/csam.h>
139	#include <VBox/patm.h>
140	#include <VBox/rem.h>
141	#include <VBox/ssm.h>
142	#include <VBox/tm.h>
143	#include "VMMInternal.h"
144	#include "VMMSwitcher/VMMSwitcher.h"
145	#include <VBox/vm.h>
146	#include <VBox/err.h>
147	#include <VBox/param.h>
148	#include <VBox/version.h>
149	#include <VBox/x86.h>
150	#include <VBox/hwaccm.h>
151	#include <iprt/assert.h>
152	#include <iprt/alloc.h>
153	#include <iprt/asm.h>
154	#include <iprt/time.h>
155	#include <iprt/stream.h>
156	#include <iprt/string.h>
157	#include <iprt/stdarg.h>
158	#include <iprt/ctype.h>
159
160
161
162	/** The saved state version. */
163	#define VMM_SAVED_STATE_VERSION 3
164
165
166	/*******************************************************************************
167	* Internal Functions *
168	*******************************************************************************/
169	static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
170	static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
171	static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
172	static int vmmR3ServiceCallHostRequest(PVM pVM);
173	static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
174
175
176	/*******************************************************************************
177	* Global Variables *
178	*******************************************************************************/
179	/** Array of switcher defininitions.
180	* The type and index shall match!
181	*/
182	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
183	{
184	NULL, /* invalid entry */
185	#ifndef RT_ARCH_AMD64
186	&vmmR3Switcher32BitTo32Bit_Def,
187	&vmmR3Switcher32BitToPAE_Def,
188	NULL, //&vmmR3Switcher32BitToAMD64_Def,
189	&vmmR3SwitcherPAETo32Bit_Def,
190	&vmmR3SwitcherPAEToPAE_Def,
191	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
192	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
193	&vmmR3SwitcherAMD64ToPAE_Def,
194	# else
195	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
196	# endif
197	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
198	#else
199	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
200	NULL, //&vmmR3Switcher32BitToPAE_Def,
201	NULL, //&vmmR3Switcher32BitToAMD64_Def,
202	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
203	NULL, //&vmmR3SwitcherPAEToPAE_Def,
204	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
205	&vmmR3SwitcherAMD64ToPAE_Def,
206	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
207	#endif
208	};
209
210
211
212	/**
213	* Initiates the core code.
214	*
215	* This is core per VM code which might need fixups and/or for ease of use
216	* are put on linear contiguous backing.
217	*
218	* @returns VBox status code.
219	* @param pVM Pointer to VM structure.
220	*/
221	static int vmmR3InitCoreCode(PVM pVM)
222	{
223	/*
224	* Calc the size.
225	*/
226	unsigned cbCoreCode = 0;
227	for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
228	{
229	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
230	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
231	if (pSwitcher)
232	{
233	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
234	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
235	}
236	}
237
238	/*
239	* Allocate continguous pages for switchers and deal with
240	* conflicts in the intermediate mapping of the code.
241	*/
242	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
243	pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
244	int rc = VERR_NO_MEMORY;
245	if (pVM->vmm.s.pvHCCoreCodeR3)
246	{
247	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
248	if (rc == VERR_PGM_MAPPINGS_FIX_CONFLICT)
249	{
250	/* try more allocations. */
251	struct
252	{
253	RTR0PTR pvR0;
254	void *pvR3;
255	RTHCPHYS HCPhys;
256	RTUINT cb;
257	} aBadTries[16];
258	unsigned i = 0;
259	do
260	{
261	aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
262	aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
263	aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
264	i++;
265	pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
266	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
267	pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
268	if (!pVM->vmm.s.pvHCCoreCodeR3)
269	break;
270	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
271	} while ( rc == VERR_PGM_MAPPINGS_FIX_CONFLICT
272	&& i < ELEMENTS(aBadTries) - 1);
273
274	/* cleanup */
275	if (VBOX_FAILURE(rc))
276	{
277	aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
278	aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
279	aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
280	aBadTries[i].cb = pVM->vmm.s.cbCoreCode;
281	i++;
282	LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
283	}
284	while (i-- > 0)
285	{
286	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
287	i, aBadTries[i].pvR3, aBadTries[i].pvR0, aBadTries[i].HCPhys));
288	SUPContFree(aBadTries[i].pvR3, aBadTries[i].cb >> PAGE_SHIFT);
289	}
290	}
291	}
292	if (VBOX_SUCCESS(rc))
293	{
294	/*
295	* copy the code.
296	*/
297	for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
298	{
299	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
300	if (pSwitcher)
301	memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
302	pSwitcher->pvCode, pSwitcher->cbCode);
303	}
304
305	/*
306	* Map the code into the GC address space.
307	*/
308	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &pVM->vmm.s.pvGCCoreCode);
309	if (VBOX_SUCCESS(rc))
310	{
311	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
312	LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VGv Phys=%VHp cb=%#x\n",
313	pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
314
315	/*
316	* Finally, PGM probably have selected a switcher already but we need
317	* to do get the addresses so we'll reselect it.
318	* This may legally fail so, we're ignoring the rc.
319	*/
320	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
321	return rc;
322	}
323
324	/* shit */
325	AssertMsgFailed(("PGMR3Map(,%VGv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
326	SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
327	}
328	else
329	VMSetError(pVM, rc, RT_SRC_POS,
330	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code."),
331	cbCoreCode);
332
333	pVM->vmm.s.pvHCCoreCodeR3 = NULL;
334	pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
335	pVM->vmm.s.pvGCCoreCode = 0;
336	return rc;
337	}
338
339
340	/**
341	* Initializes the VMM.
342	*
343	* @returns VBox status code.
344	* @param pVM The VM to operate on.
345	*/
346	VMMR3DECL(int) VMMR3Init(PVM pVM)
347	{
348	LogFlow(("VMMR3Init\n"));
349
350	/*
351	* Assert alignment, sizes and order.
352	*/
353	AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
354	AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
355	("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
356	sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
357
358	/*
359	* Init basic VM VMM members.
360	*/
361	pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
362	int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
363	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
364	pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
365	//pVM->vmm.s.cYieldEveryMillies = 8; //debugging
366	else
367	AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
368
369	/* GC switchers are enabled by default. Turned off by HWACCM. */
370	pVM->vmm.s.fSwitcherDisabled = false;
371
372	/*
373	* Register the saved state data unit.
374	*/
375	rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
376	NULL, vmmR3Save, NULL,
377	NULL, vmmR3Load, NULL);
378	if (VBOX_FAILURE(rc))
379	return rc;
380
381	#ifdef VBOX_WITHOUT_IDT_PATCHING
382	/*
383	* Register the Ring-0 VM handle with the session for fast ioctl calls.
384	*/
385	rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
386	if (VBOX_FAILURE(rc))
387	return rc;
388	#endif
389
390	/*
391	* Init core code.
392	*/
393	rc = vmmR3InitCoreCode(pVM);
394	if (VBOX_SUCCESS(rc))
395	{
396	/*
397	* Allocate & init VMM GC stack.
398	* The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
399	* (The page protection is modifed during R3 init completion.)
400	*/
401	#ifdef VBOX_STRICT_VMM_STACK
402	rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
403	#else
404	rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
405	#endif
406	if (VBOX_SUCCESS(rc))
407	{
408	/* Set HC and GC stack pointers to top of stack. */
409	pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
410	pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
411	pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
412	AssertRelease(pVM->vmm.s.pbGCStack);
413
414	/* Set hypervisor eip. */
415	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
416
417	/*
418	* Allocate GC & R0 Logger instances (they are finalized in the relocator).
419	*/
420	#ifdef LOG_ENABLED
421	PRTLOGGER pLogger = RTLogDefaultInstance();
422	if (pLogger)
423	{
424	pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pLogger->cGroups]);
425	rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
426	if (VBOX_SUCCESS(rc))
427	{
428	pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
429
430	/*
431	* Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
432	* you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
433	*
434	* If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
435	* to not stub all the log functions.
436	*
437	* You might also wish to enable the AssertMsg1/2 overrides in VMMR0.cpp when enabling this.
438	*/
439	# if defined(DEBUG_sandervl) \|\| defined(DEBUG_frank)
440	rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
441	0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
442	if (VBOX_SUCCESS(rc))
443	{
444	pVM->vmm.s.pR0Logger->pVM = pVM;
445	//pVM->vmm.s.pR0Logger->fCreated = false;
446	pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
447	}
448	# endif
449	}
450	}
451	#endif /* LOG_ENABLED */
452
453	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
454	/*
455	* Allocate GC Release Logger instances (finalized in the relocator).
456	*/
457	if (VBOX_SUCCESS(rc))
458	{
459	PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
460	if (pRelLogger)
461	{
462	pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pRelLogger->cGroups]);
463	rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
464	if (VBOX_SUCCESS(rc))
465	pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
466	}
467	}
468	#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
469
470	#ifdef VBOX_WITH_NMI
471	/*
472	* Allocate mapping for the host APIC.
473	*/
474	if (VBOX_SUCCESS(rc))
475	{
476	rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
477	AssertRC(rc);
478	}
479	#endif
480	if (VBOX_SUCCESS(rc))
481	{
482	rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
483	if (VBOX_SUCCESS(rc))
484	{
485	/*
486	* Debug info.
487	*/
488	DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
489
490	/*
491	* Statistics.
492	*/
493	STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
494	STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
495	STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
496	STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
497	STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
498	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
499	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
500	STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
501	STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
502	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
503	STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
504	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
505	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
506	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
507	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
508	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
509	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
510	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
511	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
512	STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
513	STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
514	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
515	STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
516	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
517	STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
518	STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
519	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
520	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
521	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
522	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
523	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
524	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
525	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
526	STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
527	STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
528	STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
529	STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
530	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
531	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
532	STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
533	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
534	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
535	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
536	STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
537	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
538	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
539	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
540	STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
541	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
542
543	return VINF_SUCCESS;
544	}
545	AssertRC(rc);
546	}
547	}
548	/** @todo: Need failure cleanup. */
549
550	//more todo in here?
551	//if (VBOX_SUCCESS(rc))
552	//{
553	//}
554	//int rc2 = vmmR3TermCoreCode(pVM);
555	//AssertRC(rc2));
556	}
557
558	return rc;
559	}
560
561
562	/**
563	* Ring-3 init finalizing.
564	*
565	* @returns VBox status code.
566	* @param pVM The VM handle.
567	*/
568	VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
569	{
570	#ifdef VBOX_STRICT_VMM_STACK
571	/*
572	* Two inaccessible pages at each sides of the stack to catch over/under-flows.
573	*/
574	memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
575	PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
576	RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
577
578	memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
579	PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
580	RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
581	#endif
582
583	/*
584	* Set page attributes to r/w for stack pages.
585	*/
586	int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D \| X86_PTE_RW);
587	AssertRC(rc);
588	if (VBOX_SUCCESS(rc))
589	{
590	/*
591	* Create the EMT yield timer.
592	*/
593	rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
594	if (VBOX_SUCCESS(rc))
595	rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
596	}
597	#ifdef VBOX_WITH_NMI
598	/*
599	* Map the host APIC into GC - This may be host os specific!
600	*/
601	if (VBOX_SUCCESS(rc))
602	rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
603	X86_PTE_P \| X86_PTE_RW \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A \| X86_PTE_D);
604	#endif
605	return rc;
606	}
607
608
609	/**
610	* Initializes the R0 VMM.
611	*
612	* @returns VBox status code.
613	* @param pVM The VM to operate on.
614	*/
615	VMMR3DECL(int) VMMR3InitR0(PVM pVM)
616	{
617	int rc;
618
619	/*
620	* Initialize the ring-0 logger if we haven't done so yet.
621	*/
622	if ( pVM->vmm.s.pR0Logger
623	&& !pVM->vmm.s.pR0Logger->fCreated)
624	{
625	rc = VMMR3UpdateLoggers(pVM);
626	if (VBOX_FAILURE(rc))
627	return rc;
628	}
629
630	/*
631	* Call Ring-0 entry with init code.
632	*/
633	for (;;)
634	{
635	#ifdef NO_SUPCALLR0VMM
636	//rc = VERR_GENERAL_FAILURE;
637	rc = VINF_SUCCESS;
638	#else
639	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, (void *)VBOX_VERSION);
640	#endif
641	if ( pVM->vmm.s.pR0Logger
642	&& pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
643	RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
644	if (rc != VINF_VMM_CALL_HOST)
645	break;
646	rc = vmmR3ServiceCallHostRequest(pVM);
647	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
648	break;
649	break; // remove this when we do setjmp for all ring-0 stuff.
650	}
651
652	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
653	{
654	LogRel(("R0 init failed, rc=%Vra\n", rc));
655	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
656	rc = VERR_INTERNAL_ERROR;
657	}
658	return rc;
659	}
660
661
662	/**
663	* Initializes the GC VMM.
664	*
665	* @returns VBox status code.
666	* @param pVM The VM to operate on.
667	*/
668	VMMR3DECL(int) VMMR3InitGC(PVM pVM)
669	{
670	/* In VMX mode, there's no need to init GC. */
671	if (pVM->vmm.s.fSwitcherDisabled)
672	return VINF_SUCCESS;
673
674	/*
675	* Call VMMGCInit():
676	* -# resolve the address.
677	* -# setup stackframe and EIP to use the trampoline.
678	* -# do a generic hypervisor call.
679	*/
680	RTGCPTR GCPtrEP;
681	int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
682	if (VBOX_SUCCESS(rc))
683	{
684	CPUMHyperSetCtxCore(pVM, NULL);
685	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
686	uint64_t u64TS = RTTimeProgramStartNanoTS();
687	#if GC_ARCH_BITS == 32
688	CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
689	CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
690	#else /* 64-bit GC */
691	CPUMPushHyper(pVM, u64TS); /* Param 3: The program startup TS. */
692	#endif
693	CPUMPushHyper(pVM, VBOX_VERSION); /* Param 2: Version argument. */
694	CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
695	CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
696	CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* trampoline param: stacksize. */
697	CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
698	CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
699
700	for (;;)
701	{
702	#ifdef NO_SUPCALLR0VMM
703	//rc = VERR_GENERAL_FAILURE;
704	rc = VINF_SUCCESS;
705	#else
706	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
707	#endif
708	#ifdef LOG_ENABLED
709	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
710	if ( pLogger
711	&& pLogger->offScratch > 0)
712	RTLogFlushGC(NULL, pLogger);
713	#endif
714	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
715	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
716	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
717	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
718	#endif
719	if (rc != VINF_VMM_CALL_HOST)
720	break;
721	rc = vmmR3ServiceCallHostRequest(pVM);
722	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
723	break;
724	}
725
726	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
727	{
728	VMMR3FatalDump(pVM, rc);
729	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
730	rc = VERR_INTERNAL_ERROR;
731	}
732	AssertRC(rc);
733	}
734	return rc;
735	}
736
737
738	/**
739	* Terminate the VMM bits.
740	*
741	* @returns VINF_SUCCESS.
742	* @param pVM The VM handle.
743	*/
744	VMMR3DECL(int) VMMR3Term(PVM pVM)
745	{
746	/** @todo must call ring-0 so the logger thread instance can be properly removed. */
747
748	#ifdef VBOX_STRICT_VMM_STACK
749	/*
750	* Make the two stack guard pages present again.
751	*/
752	RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
753	RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
754	#endif
755	return VINF_SUCCESS;
756	}
757
758
759	/**
760	* Applies relocations to data and code managed by this
761	* component. This function will be called at init and
762	* whenever the VMM need to relocate it self inside the GC.
763	*
764	* The VMM will need to apply relocations to the core code.
765	*
766	* @param pVM The VM handle.
767	* @param offDelta The relocation delta.
768	*/
769	VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
770	{
771	LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
772
773	/*
774	* Recalc the GC address.
775	*/
776	pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
777
778	/*
779	* The stack.
780	*/
781	CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
782	pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
783	pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
784
785	/*
786	* All the switchers.
787	*/
788	for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
789	{
790	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
791	if (pSwitcher && pSwitcher->pfnRelocate)
792	{
793	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
794	pSwitcher->pfnRelocate(pVM,
795	pSwitcher,
796	(uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
797	(uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
798	pVM->vmm.s.pvGCCoreCode + off,
799	pVM->vmm.s.HCPhysCoreCode + off);
800	}
801	}
802
803	/*
804	* Recalc the GC address for the current switcher.
805	*/
806	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
807	RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
808	pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
809	pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
810	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
811	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
812	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
813
814	/*
815	* Get other GC entry points.
816	*/
817	int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
818	AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
819
820	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
821	AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
822
823	/*
824	* Update the logger.
825	*/
826	VMMR3UpdateLoggers(pVM);
827	}
828
829
830	/**
831	* Updates the settings for the GC and R0 loggers.
832	*
833	* @returns VBox status code.
834	* @param pVM The VM handle.
835	*/
836	VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
837	{
838	/*
839	* Simply clone the logger instance (for GC).
840	*/
841	int rc = VINF_SUCCESS;
842	RTGCPTR GCPtrLoggerFlush = 0;
843
844	if (pVM->vmm.s.pLoggerHC
845	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
846	\|\| pVM->vmm.s.pRelLoggerHC
847	#endif
848	)
849	{
850	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
851	AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
852	}
853
854	if (pVM->vmm.s.pLoggerHC)
855	{
856	RTGCPTR GCPtrLoggerWrapper = 0;
857	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
858	AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
859	pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
860	rc = RTLogCloneGC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
861	GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
862	AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
863	}
864
865	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
866	if (pVM->vmm.s.pRelLoggerHC)
867	{
868	RTGCPTR GCPtrLoggerWrapper = 0;
869	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
870	AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
871	pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
872	rc = RTLogCloneGC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
873	GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
874	AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
875	}
876	#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
877
878	/*
879	* For the ring-0 EMT logger, we use a per-thread logger
880	* instance in ring-0. Only initialize it once.
881	*/
882	PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
883	if (pR0Logger)
884	{
885	if (!pR0Logger->fCreated)
886	{
887	RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
888	rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
889	AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
890
891	RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
892	rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
893	AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
894
895	rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
896	(PFNRTLOGGER )&pfnLoggerWrapper, (PFNRTLOGFLUSH )&pfnLoggerFlush,
897	RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
898	AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
899	pR0Logger->fCreated = true;
900	}
901
902	rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, RTLOGFLAGS_BUFFERED, 0);
903	AssertRC(rc);
904	}
905
906	return rc;
907	}
908
909
910	/**
911	* Generic switch code relocator.
912	*
913	* @param pVM The VM handle.
914	* @param pSwitcher The switcher definition.
915	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
916	* @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
917	* @param GCPtrCode The guest context address corresponding to pu8Code.
918	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
919	* @param SelCS The hypervisor CS selector.
920	* @param SelDS The hypervisor DS selector.
921	* @param SelTSS The hypervisor TSS selector.
922	* @param GCPtrGDT The GC address of the hypervisor GDT.
923	* @param SelCS64 The 64-bit mode hypervisor CS selector.
924	*/
925	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
926	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
927	{
928	union
929	{
930	const uint8_t *pu8;
931	const uint16_t *pu16;
932	const uint32_t *pu32;
933	const uint64_t *pu64;
934	const void *pv;
935	uintptr_t u;
936	} u;
937	u.pv = pSwitcher->pvFixups;
938
939	/*
940	* Process fixups.
941	*/
942	uint8_t u8;
943	while ((u8 = *u.pu8++) != FIX_THE_END)
944	{
945	/*
946	* Get the source (where to write the fixup).
947	*/
948	uint32_t offSrc = *u.pu32++;
949	Assert(offSrc < pSwitcher->cbCode);
950	union
951	{
952	uint8_t *pu8;
953	uint16_t *pu16;
954	uint32_t *pu32;
955	uint64_t *pu64;
956	uintptr_t u;
957	} uSrc;
958	uSrc.pu8 = pu8CodeR3 + offSrc;
959
960	/* The fixup target and method depends on the type. */
961	switch (u8)
962	{
963	/*
964	* 32-bit relative, source in HC and target in GC.
965	*/
966	case FIX_HC_2_GC_NEAR_REL:
967	{
968	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
969	uint32_t offTrg = *u.pu32++;
970	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
971	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
972	break;
973	}
974
975	/*
976	* 32-bit relative, source in HC and target in ID.
977	*/
978	case FIX_HC_2_ID_NEAR_REL:
979	{
980	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
981	uint32_t offTrg = *u.pu32++;
982	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
983	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (uSrc.u + 4));
984	break;
985	}
986
987	/*
988	* 32-bit relative, source in GC and target in HC.
989	*/
990	case FIX_GC_2_HC_NEAR_REL:
991	{
992	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
993	uint32_t offTrg = *u.pu32++;
994	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
995	*uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
996	break;
997	}
998
999	/*
1000	* 32-bit relative, source in GC and target in ID.
1001	*/
1002	case FIX_GC_2_ID_NEAR_REL:
1003	{
1004	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1005	uint32_t offTrg = *u.pu32++;
1006	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1007	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1008	break;
1009	}
1010
1011	/*
1012	* 32-bit relative, source in ID and target in HC.
1013	*/
1014	case FIX_ID_2_HC_NEAR_REL:
1015	{
1016	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1017	uint32_t offTrg = *u.pu32++;
1018	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1019	*uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1020	break;
1021	}
1022
1023	/*
1024	* 32-bit relative, source in ID and target in HC.
1025	*/
1026	case FIX_ID_2_GC_NEAR_REL:
1027	{
1028	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1029	uint32_t offTrg = *u.pu32++;
1030	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1031	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1032	break;
1033	}
1034
1035	/*
1036	* 16:32 far jump, target in GC.
1037	*/
1038	case FIX_GC_FAR32:
1039	{
1040	uint32_t offTrg = *u.pu32++;
1041	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1042	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1043	*uSrc.pu16++ = SelCS;
1044	break;
1045	}
1046
1047	/*
1048	* Make 32-bit GC pointer given CPUM offset.
1049	*/
1050	case FIX_GC_CPUM_OFF:
1051	{
1052	uint32_t offCPUM = *u.pu32++;
1053	Assert(offCPUM < sizeof(pVM->cpum));
1054	*uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1055	break;
1056	}
1057
1058	/*
1059	* Make 32-bit GC pointer given VM offset.
1060	*/
1061	case FIX_GC_VM_OFF:
1062	{
1063	uint32_t offVM = *u.pu32++;
1064	Assert(offVM < sizeof(VM));
1065	*uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1066	break;
1067	}
1068
1069	/*
1070	* Make 32-bit HC pointer given CPUM offset.
1071	*/
1072	case FIX_HC_CPUM_OFF:
1073	{
1074	uint32_t offCPUM = *u.pu32++;
1075	Assert(offCPUM < sizeof(pVM->cpum));
1076	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1077	break;
1078	}
1079
1080	/*
1081	* Make 32-bit R0 pointer given VM offset.
1082	*/
1083	case FIX_HC_VM_OFF:
1084	{
1085	uint32_t offVM = *u.pu32++;
1086	Assert(offVM < sizeof(VM));
1087	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1088	break;
1089	}
1090
1091	/*
1092	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1093	*/
1094	case FIX_INTER_32BIT_CR3:
1095	{
1096
1097	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1098	break;
1099	}
1100
1101	/*
1102	* Store the PAE CR3 (32-bit) for the intermediate memory context.
1103	*/
1104	case FIX_INTER_PAE_CR3:
1105	{
1106
1107	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1108	break;
1109	}
1110
1111	/*
1112	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1113	*/
1114	case FIX_INTER_AMD64_CR3:
1115	{
1116
1117	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1118	break;
1119	}
1120
1121	/*
1122	* Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1123	*/
1124	case FIX_HYPER_32BIT_CR3:
1125	{
1126
1127	*uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1128	break;
1129	}
1130
1131	/*
1132	* Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1133	*/
1134	case FIX_HYPER_PAE_CR3:
1135	{
1136
1137	*uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1138	break;
1139	}
1140
1141	/*
1142	* Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1143	*/
1144	case FIX_HYPER_AMD64_CR3:
1145	{
1146
1147	*uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1148	break;
1149	}
1150
1151	/*
1152	* Store Hypervisor CS (16-bit).
1153	*/
1154	case FIX_HYPER_CS:
1155	{
1156	*uSrc.pu16 = SelCS;
1157	break;
1158	}
1159
1160	/*
1161	* Store Hypervisor DS (16-bit).
1162	*/
1163	case FIX_HYPER_DS:
1164	{
1165	*uSrc.pu16 = SelDS;
1166	break;
1167	}
1168
1169	/*
1170	* Store Hypervisor TSS (16-bit).
1171	*/
1172	case FIX_HYPER_TSS:
1173	{
1174	*uSrc.pu16 = SelTSS;
1175	break;
1176	}
1177
1178	/*
1179	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1180	*/
1181	case FIX_GC_TSS_GDTE_DW2:
1182	{
1183	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1184	*uSrc.pu32 = (uint32_t)GCPtr;
1185	break;
1186	}
1187
1188
1189	///@todo case FIX_CR4_MASK:
1190	///@todo case FIX_CR4_OSFSXR:
1191
1192	/*
1193	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1194	*/
1195	case FIX_NO_FXSAVE_JMP:
1196	{
1197	uint32_t offTrg = *u.pu32++;
1198	Assert(offTrg < pSwitcher->cbCode);
1199	if (!CPUMSupportsFXSR(pVM))
1200	{
1201	uSrc.pu8++ = 0xe9; / jmp rel32 */
1202	*uSrc.pu32++ = offTrg - (offSrc + 5);
1203	}
1204	else
1205	{
1206	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1207	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1208	}
1209	break;
1210	}
1211
1212	/*
1213	* Insert relative jump to specified target it SYSENTER isn't used by the host.
1214	*/
1215	case FIX_NO_SYSENTER_JMP:
1216	{
1217	uint32_t offTrg = *u.pu32++;
1218	Assert(offTrg < pSwitcher->cbCode);
1219	if (!CPUMIsHostUsingSysEnter(pVM))
1220	{
1221	uSrc.pu8++ = 0xe9; / jmp rel32 */
1222	*uSrc.pu32++ = offTrg - (offSrc + 5);
1223	}
1224	else
1225	{
1226	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1227	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1228	}
1229	break;
1230	}
1231
1232	/*
1233	* Insert relative jump to specified target it SYSENTER isn't used by the host.
1234	*/
1235	case FIX_NO_SYSCALL_JMP:
1236	{
1237	uint32_t offTrg = *u.pu32++;
1238	Assert(offTrg < pSwitcher->cbCode);
1239	if (!CPUMIsHostUsingSysEnter(pVM))
1240	{
1241	uSrc.pu8++ = 0xe9; / jmp rel32 */
1242	*uSrc.pu32++ = offTrg - (offSrc + 5);
1243	}
1244	else
1245	{
1246	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1247	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1248	}
1249	break;
1250	}
1251
1252	/*
1253	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1254	*/
1255	case FIX_HC_32BIT:
1256	{
1257	uint32_t offTrg = *u.pu32++;
1258	Assert(offSrc < pSwitcher->cbCode);
1259	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1260	*uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1261	break;
1262	}
1263
1264	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1265	/*
1266	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1267	*/
1268	case FIX_HC_64BIT:
1269	{
1270	uint32_t offTrg = *u.pu32++;
1271	Assert(offSrc < pSwitcher->cbCode);
1272	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1273	*uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1274	break;
1275	}
1276
1277	/*
1278	* 64-bit HC Code Selector (no argument).
1279	*/
1280	case FIX_HC_64BIT_CS:
1281	{
1282	Assert(offSrc < pSwitcher->cbCode);
1283	#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1284	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
1285	#else
1286	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1287	#endif
1288	break;
1289	}
1290
1291	/*
1292	* 64-bit HC pointer to the CPUM instance data (no argument).
1293	*/
1294	case FIX_HC_64BIT_CPUM:
1295	{
1296	Assert(offSrc < pSwitcher->cbCode);
1297	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1298	break;
1299	}
1300	#endif
1301
1302	/*
1303	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
1304	*/
1305	case FIX_ID_32BIT:
1306	{
1307	uint32_t offTrg = *u.pu32++;
1308	Assert(offSrc < pSwitcher->cbCode);
1309	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1310	*uSrc.pu32 = u32IDCode + offTrg;
1311	break;
1312	}
1313
1314	/*
1315	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
1316	*/
1317	case FIX_ID_64BIT:
1318	{
1319	uint32_t offTrg = *u.pu32++;
1320	Assert(offSrc < pSwitcher->cbCode);
1321	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1322	*uSrc.pu64 = u32IDCode + offTrg;
1323	break;
1324	}
1325
1326	/*
1327	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1328	*/
1329	case FIX_ID_FAR32_TO_64BIT_MODE:
1330	{
1331	uint32_t offTrg = *u.pu32++;
1332	Assert(offSrc < pSwitcher->cbCode);
1333	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1334	*uSrc.pu32++ = u32IDCode + offTrg;
1335	*uSrc.pu16 = SelCS64;
1336	AssertRelease(SelCS64);
1337	break;
1338	}
1339
1340	#ifdef VBOX_WITH_NMI
1341	/*
1342	* 32-bit address to the APIC base.
1343	*/
1344	case FIX_GC_APIC_BASE_32BIT:
1345	{
1346	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1347	break;
1348	}
1349	#endif
1350
1351	default:
1352	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1353	break;
1354	}
1355	}
1356
1357	#ifdef LOG_ENABLED
1358	/*
1359	* If Log2 is enabled disassemble the switcher code.
1360	*
1361	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1362	*/
1363	if (LogIs2Enabled())
1364	{
1365	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
1366	" pu8CodeR0 = %p\n"
1367	" pu8CodeR3 = %p\n"
1368	" GCPtrCode = %VGv\n"
1369	" u32IDCode = %08x\n"
1370	" pVMGC = %VGv\n"
1371	" pCPUMGC = %VGv\n"
1372	" pVMHC = %p\n"
1373	" pCPUMHC = %p\n"
1374	" GCPtrGDT = %VGv\n"
1375	" InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1376	" HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1377	" SelCS = %04x\n"
1378	" SelDS = %04x\n"
1379	" SelCS64 = %04x\n"
1380	" SelTSS = %04x\n",
1381	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1382	pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1383	VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1384	GCPtrGDT,
1385	PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1386	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1387	SelCS, SelDS, SelCS64, SelTSS);
1388
1389	uint32_t offCode = 0;
1390	while (offCode < pSwitcher->cbCode)
1391	{
1392	/*
1393	* Figure out where this is.
1394	*/
1395	const char *pszDesc = NULL;
1396	RTUINTPTR uBase;
1397	uint32_t cbCode;
1398	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1399	{
1400	pszDesc = "HCCode0";
1401	uBase = (RTUINTPTR)pu8CodeR0;
1402	offCode = pSwitcher->offHCCode0;
1403	cbCode = pSwitcher->cbHCCode0;
1404	}
1405	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1406	{
1407	pszDesc = "HCCode1";
1408	uBase = (RTUINTPTR)pu8CodeR0;
1409	offCode = pSwitcher->offHCCode1;
1410	cbCode = pSwitcher->cbHCCode1;
1411	}
1412	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1413	{
1414	pszDesc = "GCCode";
1415	uBase = GCPtrCode;
1416	offCode = pSwitcher->offGCCode;
1417	cbCode = pSwitcher->cbGCCode;
1418	}
1419	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1420	{
1421	pszDesc = "IDCode0";
1422	uBase = u32IDCode;
1423	offCode = pSwitcher->offIDCode0;
1424	cbCode = pSwitcher->cbIDCode0;
1425	}
1426	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1427	{
1428	pszDesc = "IDCode1";
1429	uBase = u32IDCode;
1430	offCode = pSwitcher->offIDCode1;
1431	cbCode = pSwitcher->cbIDCode1;
1432	}
1433	else
1434	{
1435	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1436	offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1437	offCode++;
1438	continue;
1439	}
1440
1441	/*
1442	* Disassemble it.
1443	*/
1444	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1445	DISCPUSTATE Cpu = {0};
1446	Cpu.mode = CPUMODE_32BIT;
1447	while (cbCode > 0)
1448	{
1449	/* try label it */
1450	if (pSwitcher->offR0HostToGuest == offCode)
1451	RTLogPrintf(" *R0HostToGuest:\n");
1452	if (pSwitcher->offGCGuestToHost == offCode)
1453	RTLogPrintf(" *GCGuestToHost:\n");
1454	if (pSwitcher->offGCCallTrampoline == offCode)
1455	RTLogPrintf(" *GCCallTrampoline:\n");
1456	if (pSwitcher->offGCGuestToHostAsm == offCode)
1457	RTLogPrintf(" *GCGuestToHostAsm:\n");
1458	if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1459	RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1460	if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1461	RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1462
1463	/* disas */
1464	uint32_t cbInstr = 0;
1465	char szDisas[256];
1466	if (DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas))
1467	RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1468	else
1469	{
1470	RTLogPrintf(" %04x: %02x '%c'\n",
1471	offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1472	cbInstr = 1;
1473	}
1474	offCode += cbInstr;
1475	cbCode -= RT_MIN(cbInstr, cbCode);
1476	}
1477	}
1478	}
1479	#endif
1480	}
1481
1482
1483	/**
1484	* Relocator for the 32-Bit to 32-Bit world switcher.
1485	*/
1486	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1487	{
1488	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1489	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1490	}
1491
1492
1493	/**
1494	* Relocator for the 32-Bit to PAE world switcher.
1495	*/
1496	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1497	{
1498	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1499	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1500	}
1501
1502
1503	/**
1504	* Relocator for the PAE to 32-Bit world switcher.
1505	*/
1506	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1507	{
1508	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1509	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1510	}
1511
1512
1513	/**
1514	* Relocator for the PAE to PAE world switcher.
1515	*/
1516	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1517	{
1518	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1519	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1520	}
1521
1522
1523	/**
1524	* Relocator for the AMD64 to PAE world switcher.
1525	*/
1526	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1527	{
1528	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1529	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1530	}
1531
1532
1533	/**
1534	* Gets the pointer to g_szRTAssertMsg1 in GC.
1535	* @returns Pointer to VMMGC::g_szRTAssertMsg1.
1536	* Returns NULL if not present.
1537	* @param pVM The VM handle.
1538	*/
1539	VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1540	{
1541	RTGCPTR GCPtr;
1542	int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1543	if (VBOX_SUCCESS(rc))
1544	return (const char *)MMHyperGC2HC(pVM, GCPtr);
1545	return NULL;
1546	}
1547
1548
1549	/**
1550	* Gets the pointer to g_szRTAssertMsg2 in GC.
1551	* @returns Pointer to VMMGC::g_szRTAssertMsg2.
1552	* Returns NULL if not present.
1553	* @param pVM The VM handle.
1554	*/
1555	VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1556	{
1557	RTGCPTR GCPtr;
1558	int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1559	if (VBOX_SUCCESS(rc))
1560	return (const char *)MMHyperGC2HC(pVM, GCPtr);
1561	return NULL;
1562	}
1563
1564
1565	/**
1566	* Execute state save operation.
1567	*
1568	* @returns VBox status code.
1569	* @param pVM VM Handle.
1570	* @param pSSM SSM operation handle.
1571	*/
1572	static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1573	{
1574	LogFlow(("vmmR3Save:\n"));
1575
1576	/*
1577	* The hypervisor stack.
1578	*/
1579	SSMR3PutGCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1580	RTGCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1581	Assert(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE);
1582	SSMR3PutGCPtr(pSSM, GCPtrESP);
1583	SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1584	return SSMR3PutU32(pSSM, ~0); /* terminator */
1585	}
1586
1587
1588	/**
1589	* Execute state load operation.
1590	*
1591	* @returns VBox status code.
1592	* @param pVM VM Handle.
1593	* @param pSSM SSM operation handle.
1594	* @param u32Version Data layout version.
1595	*/
1596	static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1597	{
1598	LogFlow(("vmmR3Load:\n"));
1599
1600	/*
1601	* Validate version.
1602	*/
1603	if (u32Version != VMM_SAVED_STATE_VERSION)
1604	{
1605	Log(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1606	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1607	}
1608
1609	/*
1610	* Check that the stack is in the same place, or that it's fearly empty.
1611	*/
1612	RTGCPTR GCPtrStackBottom;
1613	SSMR3GetGCPtr(pSSM, &GCPtrStackBottom);
1614	RTGCPTR GCPtrESP;
1615	int rc = SSMR3GetGCPtr(pSSM, &GCPtrESP);
1616	if (VBOX_FAILURE(rc))
1617	return rc;
1618	if ( GCPtrStackBottom == pVM->vmm.s.pbGCStackBottom
1619	\|\| (GCPtrStackBottom - GCPtrESP < 32)) /** @todo This will break if we start preemting the hypervisor. */
1620	{
1621	/*
1622	* We must set the ESP because the CPUM load + PGM load relocations will render
1623	* the ESP in CPUM fatally invalid.
1624	*/
1625	CPUMSetHyperESP(pVM, GCPtrESP);
1626
1627	/* restore the stack. */
1628	SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1629
1630	/* terminator */
1631	uint32_t u32;
1632	rc = SSMR3GetU32(pSSM, &u32);
1633	if (VBOX_FAILURE(rc))
1634	return rc;
1635	if (u32 != ~0U)
1636	{
1637	AssertMsgFailed(("u32=%#x\n", u32));
1638	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1639	}
1640	return VINF_SUCCESS;
1641	}
1642
1643	LogRel(("The stack is not in the same place and it's not empty! GCPtrStackBottom=%VGv pbGCStackBottom=%VGv ESP=%VGv\n",
1644	GCPtrStackBottom, pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1645	AssertFailed();
1646	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1647	}
1648
1649
1650	/**
1651	* Selects the switcher to be used for switching to GC.
1652	*
1653	* @returns VBox status code.
1654	* @param pVM VM handle.
1655	* @param enmSwitcher The new switcher.
1656	* @remark This function may be called before the VMM is initialized.
1657	*/
1658	VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1659	{
1660	/*
1661	* Validate input.
1662	*/
1663	if ( enmSwitcher < VMMSWITCHER_INVALID
1664	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1665	{
1666	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1667	return VERR_INVALID_PARAMETER;
1668	}
1669
1670	/*
1671	* Select the new switcher.
1672	*/
1673	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1674	if (pSwitcher)
1675	{
1676	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1677	pVM->vmm.s.enmSwitcher = enmSwitcher;
1678
1679	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1680	pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1681
1682	RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1683	pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1684	pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1685	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1686	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1687	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1688	return VINF_SUCCESS;
1689	}
1690	return VERR_NOT_IMPLEMENTED;
1691	}
1692
1693	/**
1694	* Disable the switcher logic permanently.
1695	*
1696	* @returns VBox status code.
1697	* @param pVM VM handle.
1698	*/
1699	VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1700	{
1701	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1702	* @code
1703	* mov eax, VERR_INTERNAL_ERROR
1704	* ret
1705	* @endcode
1706	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1707	*/
1708	pVM->vmm.s.fSwitcherDisabled = true;
1709	return VINF_SUCCESS;
1710	}
1711
1712
1713	/**
1714	* Resolve a builtin GC symbol.
1715	* Called by PDM when loading or relocating GC modules.
1716	*
1717	* @returns VBox status
1718	* @param pVM VM Handle.
1719	* @param pszSymbol Symbol to resolv
1720	* @param pGCPtrValue Where to store the symbol value.
1721	* @remark This has to work before VMMR3Relocate() is called.
1722	*/
1723	VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1724	{
1725	if (!strcmp(pszSymbol, "g_Logger"))
1726	{
1727	if (pVM->vmm.s.pLoggerHC)
1728	pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1729	*pGCPtrValue = pVM->vmm.s.pLoggerGC;
1730	}
1731	else if (!strcmp(pszSymbol, "g_RelLogger"))
1732	{
1733	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1734	if (pVM->vmm.s.pRelLoggerHC)
1735	pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1736	*pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1737	#else
1738	*pGCPtrValue = NIL_RTGCPTR;
1739	#endif
1740	}
1741	else
1742	return VERR_SYMBOL_NOT_FOUND;
1743	return VINF_SUCCESS;
1744	}
1745
1746
1747	/**
1748	* Suspends the the CPU yielder.
1749	*
1750	* @param pVM The VM handle.
1751	*/
1752	VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1753	{
1754	if (!pVM->vmm.s.cYieldResumeMillies)
1755	{
1756	uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1757	uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1758	if (u64Now >= u64Expire \|\| u64Expire == ~(uint64_t)0)
1759	pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1760	else
1761	pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1762	TMTimerStop(pVM->vmm.s.pYieldTimer);
1763	}
1764	pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1765	}
1766
1767
1768	/**
1769	* Stops the the CPU yielder.
1770	*
1771	* @param pVM The VM handle.
1772	*/
1773	VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1774	{
1775	if (!pVM->vmm.s.cYieldResumeMillies)
1776	TMTimerStop(pVM->vmm.s.pYieldTimer);
1777	pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1778	pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1779	}
1780
1781
1782	/**
1783	* Resumes the CPU yielder when it has been a suspended or stopped.
1784	*
1785	* @param pVM The VM handle.
1786	*/
1787	VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1788	{
1789	if (pVM->vmm.s.cYieldResumeMillies)
1790	{
1791	TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1792	pVM->vmm.s.cYieldResumeMillies = 0;
1793	}
1794	}
1795
1796
1797	/**
1798	* Internal timer callback function.
1799	*
1800	* @param pVM The VM.
1801	* @param pTimer The timer handle.
1802	* @param pvUser User argument specified upon timer creation.
1803	*/
1804	static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1805	{
1806	/*
1807	* This really needs some careful tuning. While we shouldn't be too gready since
1808	* that'll cause the rest of the system to stop up, we shouldn't be too nice either
1809	* because that'll cause us to stop up.
1810	*
1811	* The current logic is to use the default interval when there is no lag worth
1812	* mentioning, but when we start accumulating lag we don't bother yielding at all.
1813	*
1814	* (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1815	* so the lag is up to date.)
1816	*/
1817	const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1818	if ( u64Lag < 50000000 /* 50ms */
1819	\|\| ( u64Lag < 1000000000 /* 1s */
1820	&& RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1821	)
1822	{
1823	uint64_t u64Elapsed = RTTimeNanoTS();
1824	pVM->vmm.s.u64LastYield = u64Elapsed;
1825
1826	RTThreadYield();
1827
1828	#ifdef LOG_ENABLED
1829	u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1830	Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1831	#endif
1832	}
1833	TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1834	}
1835
1836
1837	/**
1838	* Acquire global VM lock.
1839	*
1840	* @returns VBox status code
1841	* @param pVM The VM to operate on.
1842	*/
1843	VMMR3DECL(int) VMMR3Lock(PVM pVM)
1844	{
1845	return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1846	}
1847
1848
1849	/**
1850	* Release global VM lock.
1851	*
1852	* @returns VBox status code
1853	* @param pVM The VM to operate on.
1854	*/
1855	VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1856	{
1857	return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1858	}
1859
1860
1861	/**
1862	* Return global VM lock owner.
1863	*
1864	* @returns Thread id of owner.
1865	* @returns NIL_RTTHREAD if no owner.
1866	* @param pVM The VM to operate on.
1867	*/
1868	VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1869	{
1870	return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1871	}
1872
1873
1874	/**
1875	* Checks if the current thread is the owner of the global VM lock.
1876	*
1877	* @returns true if owner.
1878	* @returns false if not owner.
1879	* @param pVM The VM to operate on.
1880	*/
1881	VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1882	{
1883	return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1884	}
1885
1886
1887	/**
1888	* Executes guest code.
1889	*
1890	* @param pVM VM handle.
1891	*/
1892	VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1893	{
1894	Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1895
1896	/*
1897	* Set the EIP and ESP.
1898	*/
1899	CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1900	? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1901	: pVM->vmm.s.pfnCPUMGCResumeGuest);
1902	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1903
1904	/*
1905	* We hide log flushes (outer) and hypervisor interrupts (inner).
1906	*/
1907	for (;;)
1908	{
1909	int rc;
1910	do
1911	{
1912	#ifdef NO_SUPCALLR0VMM
1913	rc = VERR_GENERAL_FAILURE;
1914	#else
1915	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
1916	#endif
1917	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1918
1919	/*
1920	* Flush the logs.
1921	*/
1922	#ifdef LOG_ENABLED
1923	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1924	if ( pLogger
1925	&& pLogger->offScratch > 0)
1926	RTLogFlushGC(NULL, pLogger);
1927	#endif
1928	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1929	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1930	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1931	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1932	#endif
1933	if (rc != VINF_VMM_CALL_HOST)
1934	{
1935	Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1936	return rc;
1937	}
1938	rc = vmmR3ServiceCallHostRequest(pVM);
1939	if (VBOX_FAILURE(rc))
1940	return rc;
1941	/* Resume GC */
1942	}
1943	}
1944
1945
1946	/**
1947	* Executes guest code (Intel VMX and AMD SVM).
1948	*
1949	* @param pVM VM handle.
1950	*/
1951	VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1952	{
1953	Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1954
1955	for (;;)
1956	{
1957	int rc;
1958	do
1959	{
1960	#ifdef NO_SUPCALLR0VMM
1961	rc = VERR_GENERAL_FAILURE;
1962	#else
1963	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_RUN, NULL);
1964	#endif
1965	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1966
1967	#ifdef LOG_ENABLED
1968	/*
1969	* Flush the log
1970	*/
1971	PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
1972	if ( pR0Logger
1973	&& pR0Logger->Logger.offScratch > 0)
1974	RTLogFlushToLogger(&pR0Logger->Logger, NULL);
1975	#endif /* !LOG_ENABLED */
1976	if (rc != VINF_VMM_CALL_HOST)
1977	{
1978	Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1979	return rc;
1980	}
1981	rc = vmmR3ServiceCallHostRequest(pVM);
1982	if (VBOX_FAILURE(rc))
1983	return rc;
1984	/* Resume R0 */
1985	}
1986	}
1987
1988	/**
1989	* Calls GC a function.
1990	*
1991	* @param pVM The VM handle.
1992	* @param GCPtrEntry The GC function address.
1993	* @param cArgs The number of arguments in the ....
1994	* @param ... Arguments to the function.
1995	*/
1996	VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, ...)
1997	{
1998	va_list args;
1999	va_start(args, cArgs);
2000	int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2001	va_end(args);
2002	return rc;
2003	}
2004
2005
2006	/**
2007	* Calls GC a function.
2008	*
2009	* @param pVM The VM handle.
2010	* @param GCPtrEntry The GC function address.
2011	* @param cArgs The number of arguments in the ....
2012	* @param args Arguments to the function.
2013	*/
2014	VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, va_list args)
2015	{
2016	Log2(("VMMR3CallGCV: GCPtrEntry=%VGv cArgs=%d\n", GCPtrEntry, cArgs));
2017
2018	/*
2019	* Setup the call frame using the trampoline.
2020	*/
2021	CPUMHyperSetCtxCore(pVM, NULL);
2022	memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2023	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR));
2024	PRTGCUINTPTR pFrame = (PRTGCUINTPTR)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2025	int i = cArgs;
2026	while (i-- > 0)
2027	*pFrame++ = va_arg(args, RTGCUINTPTR);
2028
2029	CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR)); /* stack frame size */
2030	CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2031	CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2032
2033	/*
2034	* We hide log flushes (outer) and hypervisor interrupts (inner).
2035	*/
2036	for (;;)
2037	{
2038	int rc;
2039	do
2040	{
2041	#ifdef NO_SUPCALLR0VMM
2042	rc = VERR_GENERAL_FAILURE;
2043	#else
2044	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2045	#endif
2046	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2047
2048	/*
2049	* Flush the logs.
2050	*/
2051	#ifdef LOG_ENABLED
2052	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2053	if ( pLogger
2054	&& pLogger->offScratch > 0)
2055	RTLogFlushGC(NULL, pLogger);
2056	#endif
2057	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2058	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2059	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2060	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2061	#endif
2062	if (rc == VERR_TRPM_PANIC \|\| rc == VERR_TRPM_DONT_PANIC)
2063	VMMR3FatalDump(pVM, rc);
2064	if (rc != VINF_VMM_CALL_HOST)
2065	{
2066	Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2067	return rc;
2068	}
2069	rc = vmmR3ServiceCallHostRequest(pVM);
2070	if (VBOX_FAILURE(rc))
2071	return rc;
2072	}
2073	}
2074
2075
2076	/**
2077	* Resumes executing hypervisor code when interrupted
2078	* by a queue flush or a debug event.
2079	*
2080	* @returns VBox status code.
2081	* @param pVM VM handle.
2082	*/
2083	VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2084	{
2085	Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2086
2087	/*
2088	* We hide log flushes (outer) and hypervisor interrupts (inner).
2089	*/
2090	for (;;)
2091	{
2092	int rc;
2093	do
2094	{
2095	#ifdef NO_SUPCALLR0VMM
2096	rc = VERR_GENERAL_FAILURE;
2097	#else
2098	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2099	#endif
2100	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2101
2102	/*
2103	* Flush the loggers,
2104	*/
2105	#ifdef LOG_ENABLED
2106	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2107	if ( pLogger
2108	&& pLogger->offScratch > 0)
2109	RTLogFlushGC(NULL, pLogger);
2110	#endif
2111	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2112	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2113	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2114	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2115	#endif
2116	if (rc == VERR_TRPM_PANIC \|\| rc == VERR_TRPM_DONT_PANIC)
2117	VMMR3FatalDump(pVM, rc);
2118	if (rc != VINF_VMM_CALL_HOST)
2119	{
2120	Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2121	return rc;
2122	}
2123	rc = vmmR3ServiceCallHostRequest(pVM);
2124	if (VBOX_FAILURE(rc))
2125	return rc;
2126	}
2127	}
2128
2129
2130	/**
2131	* Service a call to the ring-3 host code.
2132	*
2133	* @returns VBox status code.
2134	* @param pVM VM handle.
2135	* @remark Careful with critsects.
2136	*/
2137	static int vmmR3ServiceCallHostRequest(PVM pVM)
2138	{
2139	switch (pVM->vmm.s.enmCallHostOperation)
2140	{
2141	/*
2142	* Acquire the PDM lock.
2143	*/
2144	case VMMCALLHOST_PDM_LOCK:
2145	{
2146	pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2147	break;
2148	}
2149
2150	/*
2151	* Flush a PDM queue.
2152	*/
2153	case VMMCALLHOST_PDM_QUEUE_FLUSH:
2154	{
2155	PDMR3QueueFlushWorker(pVM, NULL);
2156	pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2157	break;
2158	}
2159
2160	/*
2161	* Grow the PGM pool.
2162	*/
2163	case VMMCALLHOST_PGM_POOL_GROW:
2164	{
2165	pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2166	break;
2167	}
2168
2169	/*
2170	* Acquire the PGM lock.
2171	*/
2172	case VMMCALLHOST_PGM_LOCK:
2173	{
2174	pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2175	break;
2176	}
2177
2178	/*
2179	* Flush REM handler notifications.
2180	*/
2181	case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2182	{
2183	REMR3ReplayHandlerNotifications(pVM);
2184	break;
2185	}
2186
2187	case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2188	{
2189	pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, pVM->vmm.s.u64CallHostArg);
2190	break;
2191	}
2192
2193	/*
2194	* This is a noop. We just take this route to avoid unnecessary
2195	* tests in the loops.
2196	*/
2197	case VMMCALLHOST_VMM_LOGGER_FLUSH:
2198	break;
2199
2200	/*
2201	* Set the VM error message.
2202	*/
2203	case VMMCALLHOST_VM_SET_ERROR:
2204	VMR3SetErrorWorker(pVM);
2205	break;
2206
2207	/*
2208	* Set the VM runtime error message.
2209	*/
2210	case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2211	VMR3SetRuntimeErrorWorker(pVM);
2212	break;
2213
2214	default:
2215	AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2216	return VERR_INTERNAL_ERROR;
2217	}
2218
2219	pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2220	return VINF_SUCCESS;
2221	}
2222
2223
2224
2225	/**
2226	* Structure to pass to DBGFR3Info() and for doing all other
2227	* output during fatal dump.
2228	*/
2229	typedef struct VMMR3FATALDUMPINFOHLP
2230	{
2231	/** The helper core. */
2232	DBGFINFOHLP Core;
2233	/** The release logger instance. */
2234	PRTLOGGER pRelLogger;
2235	/** The saved release logger flags. */
2236	RTUINT fRelLoggerFlags;
2237	/** The logger instance. */
2238	PRTLOGGER pLogger;
2239	/** The saved logger flags. */
2240	RTUINT fLoggerFlags;
2241	/** The saved logger destination flags. */
2242	RTUINT fLoggerDestFlags;
2243	/** Whether to output to stderr or not. */
2244	bool fStdErr;
2245	} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2246	typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2247
2248
2249	/**
2250	* Print formatted string.
2251	*
2252	* @param pHlp Pointer to this structure.
2253	* @param pszFormat The format string.
2254	* @param ... Arguments.
2255	*/
2256	static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2257	{
2258	va_list args;
2259	va_start(args, pszFormat);
2260	pHlp->pfnPrintfV(pHlp, pszFormat, args);
2261	va_end(args);
2262	}
2263
2264
2265	/**
2266	* Print formatted string.
2267	*
2268	* @param pHlp Pointer to this structure.
2269	* @param pszFormat The format string.
2270	* @param args Argument list.
2271	*/
2272	static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2273	{
2274	PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2275
2276	if (pMyHlp->pRelLogger)
2277	{
2278	va_list args2;
2279	va_copy(args2, args);
2280	RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2281	va_end(args2);
2282	}
2283	if (pMyHlp->pLogger)
2284	{
2285	va_list args2;
2286	va_copy(args2, args);
2287	RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2288	va_end(args2);
2289	}
2290	if (pMyHlp->fStdErr)
2291	{
2292	va_list args2;
2293	va_copy(args2, args);
2294	RTStrmPrintfV(g_pStdErr, pszFormat, args);
2295	va_end(args2);
2296	}
2297	}
2298
2299
2300	/**
2301	* Initializes the fatal dump output helper.
2302	*
2303	* @param pHlp The structure to initialize.
2304	*/
2305	static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2306	{
2307	memset(pHlp, 0, sizeof(*pHlp));
2308
2309	pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2310	pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2311
2312	/*
2313	* The loggers.
2314	*/
2315	pHlp->pRelLogger = RTLogRelDefaultInstance();
2316	#ifndef LOG_ENABLED
2317	if (!pHlp->pRelLogger)
2318	#endif
2319	pHlp->pLogger = RTLogDefaultInstance();
2320
2321	if (pHlp->pRelLogger)
2322	{
2323	pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2324	pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED \| RTLOGFLAGS_DISABLED);
2325	}
2326
2327	if (pHlp->pLogger)
2328	{
2329	pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2330	pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2331	pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED \| RTLOGFLAGS_DISABLED);
2332	#ifndef DEBUG_sandervl
2333	pHlp->pLogger->fDestFlags \|= RTLOGDEST_DEBUGGER;
2334	#endif
2335	}
2336
2337	/*
2338	* Check if we need write to stderr.
2339	*/
2340	pHlp->fStdErr = (!pHlp->pRelLogger \|\| !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT \| RTLOGDEST_STDERR)))
2341	&& (!pHlp->pLogger \|\| !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT \| RTLOGDEST_STDERR)));
2342	}
2343
2344
2345	/**
2346	* Deletes the fatal dump output helper.
2347	*
2348	* @param pHlp The structure to delete.
2349	*/
2350	static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2351	{
2352	if (pHlp->pRelLogger)
2353	{
2354	RTLogFlush(pHlp->pRelLogger);
2355	pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2356	}
2357
2358	if (pHlp->pLogger)
2359	{
2360	RTLogFlush(pHlp->pLogger);
2361	pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2362	pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2363	}
2364	}
2365
2366
2367	/**
2368	* Dumps the VM state on a fatal error.
2369	*
2370	* @param pVM VM Handle.
2371	* @param rcErr VBox status code.
2372	*/
2373	VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2374	{
2375	/*
2376	* Create our output helper and sync it with the log settings.
2377	* This helper will be used for all the output.
2378	*/
2379	VMMR3FATALDUMPINFOHLP Hlp;
2380	PCDBGFINFOHLP pHlp = &Hlp.Core;
2381	vmmR3FatalDumpInfoHlpInit(&Hlp);
2382
2383	/*
2384	* Header.
2385	*/
2386	pHlp->pfnPrintf(pHlp,
2387	"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2388	"!!\n"
2389	"!! Guru Meditation %d (%Vrc)\n"
2390	"!!\n",
2391	rcErr, rcErr);
2392
2393	/*
2394	* Continue according to context.
2395	*/
2396	bool fDoneHyper = false;
2397	switch (rcErr)
2398	{
2399	/*
2400	* Hyper visor errors.
2401	*/
2402	case VINF_EM_DBG_HYPER_ASSERTION:
2403	pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2404	/* fall thru */
2405	case VERR_TRPM_DONT_PANIC:
2406	case VERR_TRPM_PANIC:
2407	case VINF_EM_RAW_STALE_SELECTOR:
2408	case VINF_EM_RAW_IRET_TRAP:
2409	case VINF_EM_DBG_HYPER_BREAKPOINT:
2410	case VINF_EM_DBG_HYPER_STEPPED:
2411	{
2412	/* Trap? */
2413	uint32_t uEIP = CPUMGetHyperEIP(pVM);
2414	TRPMEVENT enmType;
2415	uint8_t u8TrapNo = 0xce;
2416	RTGCUINT uErrorCode = 0xdeadface;
2417	RTGCUINTPTR uCR2 = 0xdeadface;
2418	int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2419	if (VBOX_SUCCESS(rc2))
2420	pHlp->pfnPrintf(pHlp,
2421	"!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv Type=%d\n",
2422	u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2423	else
2424	pHlp->pfnPrintf(pHlp,
2425	"!! EIP=%VGv NOTRAP\n",
2426	uEIP);
2427
2428	/*
2429	* Try figure out where eip is.
2430	*/
2431	/** @todo make query call for core code or move this function to VMM. */
2432	/* core code? */
2433	//if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2434	// pHlp->pfnPrintf(pHlp,
2435	// "!! EIP is in CoreCode, offset %#x\n",
2436	// uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2437	//else
2438	{ /* ask PDM */
2439	/** @todo ask DBGFR3Sym later. */
2440	char szModName[64];
2441	RTGCPTR GCPtrMod;
2442	char szNearSym1[260];
2443	RTGCPTR GCPtrNearSym1;
2444	char szNearSym2[260];
2445	RTGCPTR GCPtrNearSym2;
2446	int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2447	&szModName[0], sizeof(szModName), &GCPtrMod,
2448	&szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2449	&szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2450	if (VBOX_SUCCESS(rc))
2451	{
2452	pHlp->pfnPrintf(pHlp,
2453	"!! EIP in %s (%p) at rva %x near symbols:\n"
2454	"!! %VGv rva %VGv off %08x %s\n"
2455	"!! %VGv rva %VGv off -%08x %s\n",
2456	szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2457	GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2458	GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2459	}
2460	else
2461	pHlp->pfnPrintf(pHlp,
2462	"!! EIP is not in any code known to VMM!\n");
2463	}
2464
2465	/* Disassemble the instruction. */
2466	char szInstr[256];
2467	rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2468	if (VBOX_SUCCESS(rc2))
2469	pHlp->pfnPrintf(pHlp,
2470	"!! %s\n", szInstr);
2471
2472	/* Dump the hypervisor cpu state. */
2473	pHlp->pfnPrintf(pHlp,
2474	"!!\n"
2475	"!!\n"
2476	"!!\n");
2477	rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2478	fDoneHyper = true;
2479
2480	/* Callstack. */
2481	DBGFSTACKFRAME Frame = {0};
2482	rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2483	if (VBOX_SUCCESS(rc2))
2484	{
2485	pHlp->pfnPrintf(pHlp,
2486	"!!\n"
2487	"!! Call Stack:\n"
2488	"!!\n"
2489	"EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2490	do
2491	{
2492	pHlp->pfnPrintf(pHlp,
2493	"%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2494	(uint32_t)Frame.AddrFrame.off,
2495	(uint32_t)Frame.AddrReturnFrame.off,
2496	(uint32_t)Frame.AddrReturnPC.Sel,
2497	(uint32_t)Frame.AddrReturnPC.off,
2498	Frame.Args.au32[0],
2499	Frame.Args.au32[1],
2500	Frame.Args.au32[2],
2501	Frame.Args.au32[3]);
2502	pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2503	if (Frame.pSymPC)
2504	{
2505	RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2506	if (offDisp > 0)
2507	pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2508	else if (offDisp < 0)
2509	pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2510	else
2511	pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2512	}
2513	if (Frame.pLinePC)
2514	pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2515	pHlp->pfnPrintf(pHlp, "\n");
2516
2517	/* next */
2518	rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2519	} while (VBOX_SUCCESS(rc2));
2520	DBGFR3StackWalkEnd(pVM, &Frame);
2521	}
2522
2523	/* raw stack */
2524	pHlp->pfnPrintf(pHlp,
2525	"!!\n"
2526	"!! Raw stack (mind the direction).\n"
2527	"!!\n"
2528	"%.*Vhxd\n",
2529	VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2530	break;
2531	}
2532
2533	default:
2534	{
2535	break;
2536	}
2537
2538	} /* switch (rcErr) */
2539
2540
2541	/*
2542	* Dump useful state information.
2543	*/
2544	/** @todo convert these dumpers to DBGFR3Info() handlers!!! */
2545	pHlp->pfnPrintf(pHlp,
2546	"!!\n"
2547	"!! PGM Access Handlers & Stuff:\n"
2548	"!!\n");
2549	PGMR3DumpMappings(pVM);
2550
2551
2552	/*
2553	* Generic info dumper loop.
2554	*/
2555	static struct
2556	{
2557	const char *pszInfo;
2558	const char *pszArgs;
2559	} const aInfo[] =
2560	{
2561	{ "hma", NULL },
2562	{ "cpumguest", "verbose" },
2563	{ "cpumhyper", "verbose" },
2564	{ "cpumhost", "verbose" },
2565	{ "mode", "all" },
2566	{ "cpuid", "verbose" },
2567	{ "gdt", NULL },
2568	{ "ldt", NULL },
2569	//{ "tss", NULL },
2570	{ "ioport", NULL },
2571	{ "mmio", NULL },
2572	{ "phys", NULL },
2573	//{ "pgmpd", NULL }, - doesn't always work at init time...
2574	{ "timers", NULL },
2575	{ "activetimers", NULL },
2576	{ "handlers", "phys virt stats" },
2577	{ "cfgm", NULL },
2578	};
2579	for (unsigned i = 0; i < ELEMENTS(aInfo); i++)
2580	{
2581	if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2582	continue;
2583	pHlp->pfnPrintf(pHlp,
2584	"!!\n"
2585	"!! {%s, %s}\n"
2586	"!!\n",
2587	aInfo[i].pszInfo, aInfo[i].pszArgs);
2588	DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2589	}
2590
2591	/* done */
2592	pHlp->pfnPrintf(pHlp,
2593	"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2594
2595
2596	/*
2597	* Delete the output instance (flushing and restoring of flags).
2598	*/
2599	vmmR3FatalDumpInfoHlpDelete(&Hlp);
2600	}
2601
2602
2603
2604	/**
2605	* Displays the Force action Flags.
2606	*
2607	* @param pVM The VM handle.
2608	* @param pHlp The output helpers.
2609	* @param pszArgs The additional arguments (ignored).
2610	*/
2611	static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2612	{
2613	const uint32_t fForcedActions = pVM->fForcedActions;
2614
2615	pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2616
2617	/* show the flag mnemonics */
2618	int c = 0;
2619	uint32_t f = fForcedActions;
2620	#define PRINT_FLAG(flag) do { \
2621	if (f & (flag)) \
2622	{ \
2623	static const char *s_psz = #flag; \
2624	if (!(c % 6)) \
2625	pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2626	else \
2627	pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2628	c++; \
2629	f &= ~(flag); \
2630	} \
2631	} while (0)
2632	PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2633	PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2634	PRINT_FLAG(VM_FF_TIMER);
2635	PRINT_FLAG(VM_FF_PDM_QUEUES);
2636	PRINT_FLAG(VM_FF_PDM_DMA);
2637	PRINT_FLAG(VM_FF_PDM_CRITSECT);
2638	PRINT_FLAG(VM_FF_DBGF);
2639	PRINT_FLAG(VM_FF_REQUEST);
2640	PRINT_FLAG(VM_FF_TERMINATE);
2641	PRINT_FLAG(VM_FF_RESET);
2642	PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2643	PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2644	PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2645	PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2646	PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2647	PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2648	PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2649	PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2650	PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2651	PRINT_FLAG(VM_FF_TO_R3);
2652	PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2653	if (f)
2654	pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2655	else
2656	pHlp->pfnPrintf(pHlp, "\n");
2657	#undef PRINT_FLAG
2658
2659	/* the groups */
2660	c = 0;
2661	#define PRINT_GROUP(grp) do { \
2662	if (fForcedActions & (grp)) \
2663	{ \
2664	static const char *s_psz = #grp; \
2665	if (!(c % 5)) \
2666	pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2667	else \
2668	pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2669	c++; \
2670	} \
2671	} while (0)
2672	PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2673	PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2674	PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2675	PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2676	PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2677	PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2678	PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2679	PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2680	PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2681	if (c)
2682	pHlp->pfnPrintf(pHlp, "\n");
2683	#undef PRINT_GROUP
2684	}
2685

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source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 4050

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