VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 3753

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1/* $Id: VMM.cpp 3753 2007-07-20 17:40:59Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/** @page pg_vmm VMM - The Virtual Machine Monitor
25 *
26 * !Revise this! It's already incorrect!
27 *
28 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
29 * manages the alternate reality; controlling the virtualization, managing
30 * resources, tracking CPU state, it's resources and so on...
31 *
32 * We will split the VMM into smaller entities:
33 *
34 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
35 * provide ring and world switching, that including routing
36 * interrupts to the host OS and traps to the appropriate trap
37 * handlers. It will implement an external interface for
38 * managing trap handlers.
39 *
40 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
41 * reality) and implementing external interfaces to read and change
42 * the state.
43 *
44 * - Memory Monitor (MM), which purpose it is to virtualize physical
45 * pages, segment descriptor tables, interrupt descriptor tables, task
46 * segments, and keep track of all memory providing external interfaces
47 * to access content and map pages. (Internally splitt into smaller entities!)
48 *
49 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
50 * interacts with the MM to implement memory mapped I/O. External
51 * interfaces for adding and removing I/O ranges are implemented.
52 *
53 * - External Interrupt Monitor (EIM), which purpose it is to manage
54 * interrupts generated by virtual devices. This monitor provides
55 * an interfaces for raising interrupts which is accessible at any
56 * time and from all thread.
57 * <p>
58 * A subentity of the EIM is the vitual Programmable Interrupt
59 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
60 * Programmable Interrupt Controller Device (VAPICD).
61 *
62 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
63 * virtual device using the DMA controller. Interfaces must be as the
64 * EIM interfaces independent and threadable.
65 * <p>
66 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
67 *
68 *
69 * Entities working on a higher level:
70 *
71 * - Device Manager (DM), which is a support facility for virtualized
72 * hardware. This provides generic facilities for efficient device
73 * virtualization. It will manage device attaching and detaching
74 * conversing with EIM and IOM.
75 *
76 * - Debugger Facility (DBGF) provides the basic features for
77 * debugging the alternate reality execution.
78 *
79 *
80 *
81 * @section pg_vmm_s_use_cases Use Cases
82 *
83 * @subsection pg_vmm_s_use_case_boot Bootstrap
84 *
85 * - Basic Init:
86 * - Init SUPDRV.
87 *
88 * - Init Virtual Machine Instance:
89 * - Load settings.
90 * - Check resource requirements (memory, com, stuff).
91 *
92 * - Init Host Ring 3 part:
93 * - Init Core code.
94 * - Load Pluggable Components.
95 * - Init Pluggable Components.
96 *
97 * - Init Host Ring 0 part:
98 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
99 * - Init Core code.
100 * - Load Pluggable Component code.
101 * - Init Pluggable Component code.
102 *
103 * - Allocate first chunk of memory and pin it down. This block of memory
104 * will fit the following pieces:
105 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
106 * (This is available from everywhere (at different addresses though)).
107 * - VMM Guest Context code.
108 * - Pluggable devices Guest Context code.
109 * - Page tables (directory and everything) for the VMM Guest
110 *
111 * - Setup Guest (Ring 0) part:
112 * - Setup initial page tables (i.e. directory all the stuff).
113 * - Load Core Guest Context code.
114 * - Load Pluggable Devices Guest Context code.
115 *
116 *
117 */
118
119
120/*******************************************************************************
121* Header Files *
122*******************************************************************************/
123#define LOG_GROUP LOG_GROUP_VMM
124#include <VBox/vmm.h>
125#include <VBox/vmapi.h>
126#include <VBox/pgm.h>
127#include <VBox/cfgm.h>
128#include <VBox/pdm.h>
129#include <VBox/cpum.h>
130#include <VBox/mm.h>
131#include <VBox/iom.h>
132#include <VBox/trpm.h>
133#include <VBox/selm.h>
134#include <VBox/em.h>
135#include <VBox/sup.h>
136#include <VBox/dbgf.h>
137#include <VBox/csam.h>
138#include <VBox/patm.h>
139#include <VBox/rem.h>
140#include <VBox/ssm.h>
141#include <VBox/tm.h>
142#include "VMMInternal.h"
143#include "VMMSwitcher/VMMSwitcher.h"
144#include <VBox/vm.h>
145#include <VBox/err.h>
146#include <VBox/param.h>
147#include <VBox/version.h>
148#include <VBox/x86.h>
149#include <VBox/hwaccm.h>
150#include <iprt/assert.h>
151#include <iprt/alloc.h>
152#include <iprt/asm.h>
153#include <iprt/time.h>
154#include <iprt/stream.h>
155#include <iprt/string.h>
156#include <iprt/stdarg.h>
157#include <iprt/ctype.h>
158
159
160
161/** The saved state version. */
162#define VMM_SAVED_STATE_VERSION 3
163
164
165/*******************************************************************************
166* Internal Functions *
167*******************************************************************************/
168static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
169static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
170static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
171static int vmmR3ServiceCallHostRequest(PVM pVM);
172static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
173
174
175/*******************************************************************************
176* Global Variables *
177*******************************************************************************/
178/** Array of switcher defininitions.
179 * The type and index shall match!
180 */
181static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
182{
183 NULL, /* invalid entry */
184#ifndef RT_ARCH_AMD64
185 &vmmR3Switcher32BitTo32Bit_Def,
186 &vmmR3Switcher32BitToPAE_Def,
187 NULL, //&vmmR3Switcher32BitToAMD64_Def,
188 &vmmR3SwitcherPAETo32Bit_Def,
189 &vmmR3SwitcherPAEToPAE_Def,
190 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
191# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
192 &vmmR3SwitcherAMD64ToPAE_Def,
193# else
194 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
195# endif
196 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
197#else
198 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
199 NULL, //&vmmR3Switcher32BitToPAE_Def,
200 NULL, //&vmmR3Switcher32BitToAMD64_Def,
201 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
202 NULL, //&vmmR3SwitcherPAEToPAE_Def,
203 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
204 &vmmR3SwitcherAMD64ToPAE_Def,
205 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
206#endif
207};
208
209
210
211/**
212 * Initiates the core code.
213 *
214 * This is core per VM code which might need fixups and/or for ease of use
215 * are put on linear contiguous backing.
216 *
217 * @returns VBox status code.
218 * @param pVM Pointer to VM structure.
219 */
220static int vmmR3InitCoreCode(PVM pVM)
221{
222 /*
223 * Calc the size.
224 */
225 unsigned cbCoreCode = 0;
226 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
227 {
228 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
229 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
230 if (pSwitcher)
231 {
232 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
233 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
234 }
235 }
236
237 /*
238 * Allocate continguous pages for switchers and deal with
239 * conflicts in the intermediate mapping of the code.
240 */
241 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
242 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
243 int rc = VERR_NO_MEMORY;
244 if (pVM->vmm.s.pvHCCoreCodeR3)
245 {
246 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
247 if (rc == VERR_PGM_MAPPINGS_FIX_CONFLICT)
248 {
249 /* try more allocations. */
250 struct
251 {
252 RTR0PTR pvR0;
253 void *pvR3;
254 RTHCPHYS HCPhys;
255 RTUINT cb;
256 } aBadTries[16];
257 unsigned i = 0;
258 do
259 {
260 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
261 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
262 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
263 i++;
264 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
265 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
266 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
267 if (!pVM->vmm.s.pvHCCoreCodeR3)
268 break;
269 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
270 } while ( rc == VERR_PGM_MAPPINGS_FIX_CONFLICT
271 && i < ELEMENTS(aBadTries) - 1);
272
273 /* cleanup */
274 if (VBOX_FAILURE(rc))
275 {
276 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
277 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
278 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
279 aBadTries[i].cb = pVM->vmm.s.cbCoreCode;
280 i++;
281 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
282 }
283 while (i-- > 0)
284 {
285 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
286 i, aBadTries[i].pvR3, aBadTries[i].pvR0, aBadTries[i].HCPhys));
287 SUPContFree(aBadTries[i].pvR3, aBadTries[i].cb >> PAGE_SHIFT);
288 }
289 }
290 }
291 if (VBOX_SUCCESS(rc))
292 {
293 /*
294 * copy the code.
295 */
296 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
297 {
298 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
299 if (pSwitcher)
300 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
301 pSwitcher->pvCode, pSwitcher->cbCode);
302 }
303
304 /*
305 * Map the code into the GC address space.
306 */
307 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &pVM->vmm.s.pvGCCoreCode);
308 if (VBOX_SUCCESS(rc))
309 {
310 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
311 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VGv Phys=%VHp cb=%#x\n",
312 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
313
314 /*
315 * Finally, PGM probably have selected a switcher already but we need
316 * to do get the addresses so we'll reselect it.
317 * This may legally fail so, we're ignoring the rc.
318 */
319 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
320 return rc;
321 }
322
323 /* shit */
324 AssertMsgFailed(("PGMR3Map(,%VGv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
325 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
326 }
327 else
328 VMSetError(pVM, rc, RT_SRC_POS,
329 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code."),
330 cbCoreCode);
331
332 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
333 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
334 pVM->vmm.s.pvGCCoreCode = 0;
335 return rc;
336}
337
338
339/**
340 * Initializes the VMM.
341 *
342 * @returns VBox status code.
343 * @param pVM The VM to operate on.
344 */
345VMMR3DECL(int) VMMR3Init(PVM pVM)
346{
347 LogFlow(("VMMR3Init\n"));
348
349 /*
350 * Assert alignment, sizes and order.
351 */
352 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
353 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
354 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
355 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
356
357 /*
358 * Init basic VM VMM members.
359 */
360 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
361 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
362 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
363 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
364 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
365 else
366 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
367
368 /* GC switchers are enabled by default. Turned off by HWACCM. */
369 pVM->vmm.s.fSwitcherDisabled = false;
370
371 /*
372 * Register the saved state data unit.
373 */
374 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
375 NULL, vmmR3Save, NULL,
376 NULL, vmmR3Load, NULL);
377 if (VBOX_FAILURE(rc))
378 return rc;
379
380#ifdef VBOX_WITHOUT_IDT_PATCHING
381 /*
382 * Register the Ring-0 VM handle with the session for fast ioctl calls.
383 */
384 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
385 if (VBOX_FAILURE(rc))
386 return rc;
387#endif
388
389 /*
390 * Init core code.
391 */
392 rc = vmmR3InitCoreCode(pVM);
393 if (VBOX_SUCCESS(rc))
394 {
395 /*
396 * Allocate & init VMM GC stack.
397 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
398 * (The page protection is modifed during R3 init completion.)
399 */
400#ifdef VBOX_STRICT_VMM_STACK
401 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
402#else
403 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
404#endif
405 if (VBOX_SUCCESS(rc))
406 {
407 /* Set HC and GC stack pointers to top of stack. */
408 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
409 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
410 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
411 AssertRelease(pVM->vmm.s.pbGCStack);
412
413 /* Set hypervisor eip. */
414 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
415
416 /*
417 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
418 */
419#ifdef LOG_ENABLED
420 PRTLOGGER pLogger = RTLogDefaultInstance();
421 if (pLogger)
422 {
423 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pLogger->cGroups]);
424 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
425 if (VBOX_SUCCESS(rc))
426 {
427 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
428
429/*
430 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
431 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
432 *
433 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
434 * to not stub all the log functions.
435 *
436 * You might also wish to enable the AssertMsg1/2 overrides in VMMR0.cpp when enabling this.
437 */
438# if defined(DEBUG_sandervl) || defined(DEBUG_frank)
439 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
440 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
441 if (VBOX_SUCCESS(rc))
442 {
443 pVM->vmm.s.pR0Logger->pVM = pVM;
444 //pVM->vmm.s.pR0Logger->fCreated = false;
445 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
446 }
447# endif
448 }
449 }
450#endif /* LOG_ENABLED */
451
452#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
453 /*
454 * Allocate GC Release Logger instances (finalized in the relocator).
455 */
456 if (VBOX_SUCCESS(rc))
457 {
458 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
459 if (pRelLogger)
460 {
461 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pRelLogger->cGroups]);
462 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
463 if (VBOX_SUCCESS(rc))
464 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
465 }
466 }
467#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
468
469#ifdef VBOX_WITH_NMI
470 /*
471 * Allocate mapping for the host APIC.
472 */
473 if (VBOX_SUCCESS(rc))
474 {
475 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
476 AssertRC(rc);
477 }
478#endif
479 if (VBOX_SUCCESS(rc))
480 {
481 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
482 if (VBOX_SUCCESS(rc))
483 {
484 /*
485 * Debug info.
486 */
487 DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
488
489 /*
490 * Statistics.
491 */
492 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
493 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
494 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
495 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
496 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
497 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
498 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
499 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
500 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
501 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
502 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
503 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
504 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
505 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
506 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
507 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
508 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
509 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
510 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
511 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
512 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
520 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
521 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
522 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
523 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
524 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
525 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
526 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
527 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
528 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
529 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
530 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
531 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
532 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
533 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
534 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
535 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
536 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
537 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
538 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
539 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
540 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
541
542 return VINF_SUCCESS;
543 }
544 AssertRC(rc);
545 }
546 }
547 /** @todo: Need failure cleanup. */
548
549 //more todo in here?
550 //if (VBOX_SUCCESS(rc))
551 //{
552 //}
553 //int rc2 = vmmR3TermCoreCode(pVM);
554 //AssertRC(rc2));
555 }
556
557 return rc;
558}
559
560
561/**
562 * Ring-3 init finalizing.
563 *
564 * @returns VBox status code.
565 * @param pVM The VM handle.
566 */
567VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
568{
569#ifdef VBOX_STRICT_VMM_STACK
570 /*
571 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
572 */
573 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
574 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
575 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
576
577 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
578 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
579 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
580#endif
581
582 /*
583 * Set page attributes to r/w for stack pages.
584 */
585 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
586 AssertRC(rc);
587 if (VBOX_SUCCESS(rc))
588 {
589 /*
590 * Create the EMT yield timer.
591 */
592 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
593 if (VBOX_SUCCESS(rc))
594 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
595 }
596#ifdef VBOX_WITH_NMI
597 /*
598 * Map the host APIC into GC - This may be host os specific!
599 */
600 if (VBOX_SUCCESS(rc))
601 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
602 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
603#endif
604 return rc;
605}
606
607
608/**
609 * Initializes the R0 VMM.
610 *
611 * @returns VBox status code.
612 * @param pVM The VM to operate on.
613 */
614VMMR3DECL(int) VMMR3InitR0(PVM pVM)
615{
616 int rc;
617
618 /*
619 * Initialize the ring-0 logger if we haven't done so yet.
620 */
621 if ( pVM->vmm.s.pR0Logger
622 && !pVM->vmm.s.pR0Logger->fCreated)
623 {
624 rc = VMMR3UpdateLoggers(pVM);
625 if (VBOX_FAILURE(rc))
626 return rc;
627 }
628
629 /*
630 * Call Ring-0 entry with init code.
631 */
632 for (;;)
633 {
634#ifdef NO_SUPCALLR0VMM
635 //rc = VERR_GENERAL_FAILURE;
636 rc = VINF_SUCCESS;
637#else
638 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, (void *)VBOX_VERSION);
639#endif
640 if ( pVM->vmm.s.pR0Logger
641 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
642 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
643 if (rc != VINF_VMM_CALL_HOST)
644 break;
645 rc = vmmR3ServiceCallHostRequest(pVM);
646 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
647 break;
648 break; // remove this when we do setjmp for all ring-0 stuff.
649 }
650
651 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
652 {
653 LogRel(("R0 init failed, rc=%Vra\n", rc));
654 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
655 rc = VERR_INTERNAL_ERROR;
656 }
657 return rc;
658}
659
660
661/**
662 * Initializes the GC VMM.
663 *
664 * @returns VBox status code.
665 * @param pVM The VM to operate on.
666 */
667VMMR3DECL(int) VMMR3InitGC(PVM pVM)
668{
669 /* In VMX mode, there's no need to init GC. */
670 if (pVM->vmm.s.fSwitcherDisabled)
671 return VINF_SUCCESS;
672
673 /*
674 * Call VMMGCInit():
675 * -# resolve the address.
676 * -# setup stackframe and EIP to use the trampoline.
677 * -# do a generic hypervisor call.
678 */
679 RTGCPTR GCPtrEP;
680 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
681 if (VBOX_SUCCESS(rc))
682 {
683 CPUMHyperSetCtxCore(pVM, NULL);
684 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
685 uint64_t u64TS = RTTimeProgramStartNanoTS();
686#if GC_ARCH_BITS == 32
687 CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
688 CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
689#else /* 64-bit GC */
690 CPUMPushHyper(pVM, u64TS); /* Param 3: The program startup TS. */
691#endif
692 CPUMPushHyper(pVM, VBOX_VERSION); /* Param 2: Version argument. */
693 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
694 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
695 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* trampoline param: stacksize. */
696 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
697 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
698
699 for (;;)
700 {
701#ifdef NO_SUPCALLR0VMM
702 //rc = VERR_GENERAL_FAILURE;
703 rc = VINF_SUCCESS;
704#else
705 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
706#endif
707#ifdef LOG_ENABLED
708 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
709 if ( pLogger
710 && pLogger->offScratch > 0)
711 RTLogFlushGC(NULL, pLogger);
712#endif
713#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
714 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
715 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
716 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
717#endif
718 if (rc != VINF_VMM_CALL_HOST)
719 break;
720 rc = vmmR3ServiceCallHostRequest(pVM);
721 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
722 break;
723 }
724
725 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
726 {
727 VMMR3FatalDump(pVM, rc);
728 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
729 rc = VERR_INTERNAL_ERROR;
730 }
731 AssertRC(rc);
732 }
733 return rc;
734}
735
736
737/**
738 * Terminate the VMM bits.
739 *
740 * @returns VINF_SUCCESS.
741 * @param pVM The VM handle.
742 */
743VMMR3DECL(int) VMMR3Term(PVM pVM)
744{
745 /** @todo must call ring-0 so the logger thread instance can be properly removed. */
746
747#ifdef VBOX_STRICT_VMM_STACK
748 /*
749 * Make the two stack guard pages present again.
750 */
751 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
752 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
753#endif
754 return VINF_SUCCESS;
755}
756
757
758/**
759 * Applies relocations to data and code managed by this
760 * component. This function will be called at init and
761 * whenever the VMM need to relocate it self inside the GC.
762 *
763 * The VMM will need to apply relocations to the core code.
764 *
765 * @param pVM The VM handle.
766 * @param offDelta The relocation delta.
767 */
768VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
769{
770 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
771
772 /*
773 * Recalc the GC address.
774 */
775 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
776
777 /*
778 * The stack.
779 */
780 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
781 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
782 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
783
784 /*
785 * All the switchers.
786 */
787 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
788 {
789 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
790 if (pSwitcher && pSwitcher->pfnRelocate)
791 {
792 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
793 pSwitcher->pfnRelocate(pVM,
794 pSwitcher,
795 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
796 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
797 pVM->vmm.s.pvGCCoreCode + off,
798 pVM->vmm.s.HCPhysCoreCode + off);
799 }
800 }
801
802 /*
803 * Recalc the GC address for the current switcher.
804 */
805 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
806 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
807 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
808 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
809 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
810 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
811 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
812
813 /*
814 * Get other GC entry points.
815 */
816 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
817 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
818
819 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
820 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
821
822 /*
823 * Update the logger.
824 */
825 VMMR3UpdateLoggers(pVM);
826}
827
828
829/**
830 * Updates the settings for the GC and R0 loggers.
831 *
832 * @returns VBox status code.
833 * @param pVM The VM handle.
834 */
835VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
836{
837 /*
838 * Simply clone the logger instance (for GC).
839 */
840 int rc = VINF_SUCCESS;
841 RTGCPTR GCPtrLoggerFlush = 0;
842
843 if (pVM->vmm.s.pLoggerHC
844#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
845 || pVM->vmm.s.pRelLoggerHC
846#endif
847 )
848 {
849 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
850 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
851 }
852
853 if (pVM->vmm.s.pLoggerHC)
854 {
855 RTGCPTR GCPtrLoggerWrapper = 0;
856 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
857 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
858 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
859 rc = RTLogCloneGC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
860 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
861 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
862 }
863
864#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
865 if (pVM->vmm.s.pRelLoggerHC)
866 {
867 RTGCPTR GCPtrLoggerWrapper = 0;
868 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
869 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
870 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
871 rc = RTLogCloneGC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
872 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
873 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
874 }
875#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
876
877 /*
878 * For the ring-0 EMT logger, we use a per-thread logger
879 * instance in ring-0. Only initialize it once.
880 */
881 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
882 if (pR0Logger)
883 {
884 if (!pR0Logger->fCreated)
885 {
886 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
887 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
888 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
889
890 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
891 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
892 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
893
894 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
895 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
896 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
897 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
898 pR0Logger->fCreated = true;
899 }
900
901 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, RTLOGFLAGS_BUFFERED, 0);
902 AssertRC(rc);
903 }
904
905 return rc;
906}
907
908
909/**
910 * Generic switch code relocator.
911 *
912 * @param pVM The VM handle.
913 * @param pSwitcher The switcher definition.
914 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
915 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
916 * @param GCPtrCode The guest context address corresponding to pu8Code.
917 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
918 * @param SelCS The hypervisor CS selector.
919 * @param SelDS The hypervisor DS selector.
920 * @param SelTSS The hypervisor TSS selector.
921 * @param GCPtrGDT The GC address of the hypervisor GDT.
922 * @param SelCS64 The 64-bit mode hypervisor CS selector.
923 */
924static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
925 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
926{
927 union
928 {
929 const uint8_t *pu8;
930 const uint16_t *pu16;
931 const uint32_t *pu32;
932 const uint64_t *pu64;
933 const void *pv;
934 uintptr_t u;
935 } u;
936 u.pv = pSwitcher->pvFixups;
937
938 /*
939 * Process fixups.
940 */
941 uint8_t u8;
942 while ((u8 = *u.pu8++) != FIX_THE_END)
943 {
944 /*
945 * Get the source (where to write the fixup).
946 */
947 uint32_t offSrc = *u.pu32++;
948 Assert(offSrc < pSwitcher->cbCode);
949 union
950 {
951 uint8_t *pu8;
952 uint16_t *pu16;
953 uint32_t *pu32;
954 uint64_t *pu64;
955 uintptr_t u;
956 } uSrc;
957 uSrc.pu8 = pu8CodeR3 + offSrc;
958
959 /* The fixup target and method depends on the type. */
960 switch (u8)
961 {
962 /*
963 * 32-bit relative, source in HC and target in GC.
964 */
965 case FIX_HC_2_GC_NEAR_REL:
966 {
967 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
968 uint32_t offTrg = *u.pu32++;
969 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
970 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
971 break;
972 }
973
974 /*
975 * 32-bit relative, source in HC and target in ID.
976 */
977 case FIX_HC_2_ID_NEAR_REL:
978 {
979 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
980 uint32_t offTrg = *u.pu32++;
981 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
982 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (uSrc.u + 4));
983 break;
984 }
985
986 /*
987 * 32-bit relative, source in GC and target in HC.
988 */
989 case FIX_GC_2_HC_NEAR_REL:
990 {
991 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
992 uint32_t offTrg = *u.pu32++;
993 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
994 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
995 break;
996 }
997
998 /*
999 * 32-bit relative, source in GC and target in ID.
1000 */
1001 case FIX_GC_2_ID_NEAR_REL:
1002 {
1003 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1004 uint32_t offTrg = *u.pu32++;
1005 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1006 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1007 break;
1008 }
1009
1010 /*
1011 * 32-bit relative, source in ID and target in HC.
1012 */
1013 case FIX_ID_2_HC_NEAR_REL:
1014 {
1015 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1016 uint32_t offTrg = *u.pu32++;
1017 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1018 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1019 break;
1020 }
1021
1022 /*
1023 * 32-bit relative, source in ID and target in HC.
1024 */
1025 case FIX_ID_2_GC_NEAR_REL:
1026 {
1027 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1028 uint32_t offTrg = *u.pu32++;
1029 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1030 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1031 break;
1032 }
1033
1034 /*
1035 * 16:32 far jump, target in GC.
1036 */
1037 case FIX_GC_FAR32:
1038 {
1039 uint32_t offTrg = *u.pu32++;
1040 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1041 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1042 *uSrc.pu16++ = SelCS;
1043 break;
1044 }
1045
1046 /*
1047 * Make 32-bit GC pointer given CPUM offset.
1048 */
1049 case FIX_GC_CPUM_OFF:
1050 {
1051 uint32_t offCPUM = *u.pu32++;
1052 Assert(offCPUM < sizeof(pVM->cpum));
1053 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1054 break;
1055 }
1056
1057 /*
1058 * Make 32-bit GC pointer given VM offset.
1059 */
1060 case FIX_GC_VM_OFF:
1061 {
1062 uint32_t offVM = *u.pu32++;
1063 Assert(offVM < sizeof(VM));
1064 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1065 break;
1066 }
1067
1068 /*
1069 * Make 32-bit HC pointer given CPUM offset.
1070 */
1071 case FIX_HC_CPUM_OFF:
1072 {
1073 uint32_t offCPUM = *u.pu32++;
1074 Assert(offCPUM < sizeof(pVM->cpum));
1075 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1076 break;
1077 }
1078
1079 /*
1080 * Make 32-bit R0 pointer given VM offset.
1081 */
1082 case FIX_HC_VM_OFF:
1083 {
1084 uint32_t offVM = *u.pu32++;
1085 Assert(offVM < sizeof(VM));
1086 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1087 break;
1088 }
1089
1090 /*
1091 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1092 */
1093 case FIX_INTER_32BIT_CR3:
1094 {
1095
1096 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1097 break;
1098 }
1099
1100 /*
1101 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1102 */
1103 case FIX_INTER_PAE_CR3:
1104 {
1105
1106 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1107 break;
1108 }
1109
1110 /*
1111 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1112 */
1113 case FIX_INTER_AMD64_CR3:
1114 {
1115
1116 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1117 break;
1118 }
1119
1120 /*
1121 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1122 */
1123 case FIX_HYPER_32BIT_CR3:
1124 {
1125
1126 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1127 break;
1128 }
1129
1130 /*
1131 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1132 */
1133 case FIX_HYPER_PAE_CR3:
1134 {
1135
1136 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1137 break;
1138 }
1139
1140 /*
1141 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1142 */
1143 case FIX_HYPER_AMD64_CR3:
1144 {
1145
1146 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1147 break;
1148 }
1149
1150 /*
1151 * Store Hypervisor CS (16-bit).
1152 */
1153 case FIX_HYPER_CS:
1154 {
1155 *uSrc.pu16 = SelCS;
1156 break;
1157 }
1158
1159 /*
1160 * Store Hypervisor DS (16-bit).
1161 */
1162 case FIX_HYPER_DS:
1163 {
1164 *uSrc.pu16 = SelDS;
1165 break;
1166 }
1167
1168 /*
1169 * Store Hypervisor TSS (16-bit).
1170 */
1171 case FIX_HYPER_TSS:
1172 {
1173 *uSrc.pu16 = SelTSS;
1174 break;
1175 }
1176
1177 /*
1178 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1179 */
1180 case FIX_GC_TSS_GDTE_DW2:
1181 {
1182 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1183 *uSrc.pu32 = (uint32_t)GCPtr;
1184 break;
1185 }
1186
1187
1188 ///@todo case FIX_CR4_MASK:
1189 ///@todo case FIX_CR4_OSFSXR:
1190
1191 /*
1192 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1193 */
1194 case FIX_NO_FXSAVE_JMP:
1195 {
1196 uint32_t offTrg = *u.pu32++;
1197 Assert(offTrg < pSwitcher->cbCode);
1198 if (!CPUMSupportsFXSR(pVM))
1199 {
1200 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1201 *uSrc.pu32++ = offTrg - (offSrc + 5);
1202 }
1203 else
1204 {
1205 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1206 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1207 }
1208 break;
1209 }
1210
1211 /*
1212 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1213 */
1214 case FIX_NO_SYSENTER_JMP:
1215 {
1216 uint32_t offTrg = *u.pu32++;
1217 Assert(offTrg < pSwitcher->cbCode);
1218 if (!CPUMIsHostUsingSysEnter(pVM))
1219 {
1220 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1221 *uSrc.pu32++ = offTrg - (offSrc + 5);
1222 }
1223 else
1224 {
1225 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1226 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1227 }
1228 break;
1229 }
1230
1231 /*
1232 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1233 */
1234 case FIX_NO_SYSCALL_JMP:
1235 {
1236 uint32_t offTrg = *u.pu32++;
1237 Assert(offTrg < pSwitcher->cbCode);
1238 if (!CPUMIsHostUsingSysEnter(pVM))
1239 {
1240 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1241 *uSrc.pu32++ = offTrg - (offSrc + 5);
1242 }
1243 else
1244 {
1245 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1246 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1247 }
1248 break;
1249 }
1250
1251 /*
1252 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1253 */
1254 case FIX_HC_32BIT:
1255 {
1256 uint32_t offTrg = *u.pu32++;
1257 Assert(offSrc < pSwitcher->cbCode);
1258 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1259 *uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1260 break;
1261 }
1262
1263#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1264 /*
1265 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1266 */
1267 case FIX_HC_64BIT:
1268 {
1269 uint32_t offTrg = *u.pu32++;
1270 Assert(offSrc < pSwitcher->cbCode);
1271 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1272 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1273 break;
1274 }
1275
1276 /*
1277 * 64-bit HC Code Selector (no argument).
1278 */
1279 case FIX_HC_64BIT_CS:
1280 {
1281 Assert(offSrc < pSwitcher->cbCode);
1282#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1283 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1284#else
1285 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1286#endif
1287 break;
1288 }
1289
1290 /*
1291 * 64-bit HC pointer to the CPUM instance data (no argument).
1292 */
1293 case FIX_HC_64BIT_CPUM:
1294 {
1295 Assert(offSrc < pSwitcher->cbCode);
1296 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1297 break;
1298 }
1299#endif
1300
1301 /*
1302 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1303 */
1304 case FIX_ID_32BIT:
1305 {
1306 uint32_t offTrg = *u.pu32++;
1307 Assert(offSrc < pSwitcher->cbCode);
1308 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1309 *uSrc.pu32 = u32IDCode + offTrg;
1310 break;
1311 }
1312
1313 /*
1314 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1315 */
1316 case FIX_ID_64BIT:
1317 {
1318 uint32_t offTrg = *u.pu32++;
1319 Assert(offSrc < pSwitcher->cbCode);
1320 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1321 *uSrc.pu64 = u32IDCode + offTrg;
1322 break;
1323 }
1324
1325 /*
1326 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1327 */
1328 case FIX_ID_FAR32_TO_64BIT_MODE:
1329 {
1330 uint32_t offTrg = *u.pu32++;
1331 Assert(offSrc < pSwitcher->cbCode);
1332 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1333 *uSrc.pu32++ = u32IDCode + offTrg;
1334 *uSrc.pu16 = SelCS64;
1335 AssertRelease(SelCS64);
1336 break;
1337 }
1338
1339#ifdef VBOX_WITH_NMI
1340 /*
1341 * 32-bit address to the APIC base.
1342 */
1343 case FIX_GC_APIC_BASE_32BIT:
1344 {
1345 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1346 break;
1347 }
1348#endif
1349
1350 default:
1351 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1352 break;
1353 }
1354 }
1355
1356#ifdef LOG_ENABLED
1357 /*
1358 * If Log2 is enabled disassemble the switcher code.
1359 *
1360 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1361 */
1362 if (LogIs2Enabled())
1363 {
1364 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1365 " pu8CodeR0 = %p\n"
1366 " pu8CodeR3 = %p\n"
1367 " GCPtrCode = %VGv\n"
1368 " u32IDCode = %08x\n"
1369 " pVMGC = %VGv\n"
1370 " pCPUMGC = %VGv\n"
1371 " pVMHC = %p\n"
1372 " pCPUMHC = %p\n"
1373 " GCPtrGDT = %VGv\n"
1374 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1375 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1376 " SelCS = %04x\n"
1377 " SelDS = %04x\n"
1378 " SelCS64 = %04x\n"
1379 " SelTSS = %04x\n",
1380 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1381 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1382 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1383 GCPtrGDT,
1384 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1385 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1386 SelCS, SelDS, SelCS64, SelTSS);
1387
1388 uint32_t offCode = 0;
1389 while (offCode < pSwitcher->cbCode)
1390 {
1391 /*
1392 * Figure out where this is.
1393 */
1394 const char *pszDesc = NULL;
1395 RTUINTPTR uBase;
1396 uint32_t cbCode;
1397 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1398 {
1399 pszDesc = "HCCode0";
1400 uBase = (RTUINTPTR)pu8CodeR0;
1401 offCode = pSwitcher->offHCCode0;
1402 cbCode = pSwitcher->cbHCCode0;
1403 }
1404 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1405 {
1406 pszDesc = "HCCode1";
1407 uBase = (RTUINTPTR)pu8CodeR0;
1408 offCode = pSwitcher->offHCCode1;
1409 cbCode = pSwitcher->cbHCCode1;
1410 }
1411 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1412 {
1413 pszDesc = "GCCode";
1414 uBase = GCPtrCode;
1415 offCode = pSwitcher->offGCCode;
1416 cbCode = pSwitcher->cbGCCode;
1417 }
1418 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1419 {
1420 pszDesc = "IDCode0";
1421 uBase = u32IDCode;
1422 offCode = pSwitcher->offIDCode0;
1423 cbCode = pSwitcher->cbIDCode0;
1424 }
1425 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1426 {
1427 pszDesc = "IDCode1";
1428 uBase = u32IDCode;
1429 offCode = pSwitcher->offIDCode1;
1430 cbCode = pSwitcher->cbIDCode1;
1431 }
1432 else
1433 {
1434 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1435 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1436 offCode++;
1437 continue;
1438 }
1439
1440 /*
1441 * Disassemble it.
1442 */
1443 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1444 DISCPUSTATE Cpu = {0};
1445 Cpu.mode = CPUMODE_32BIT;
1446 while (cbCode > 0)
1447 {
1448 /* try label it */
1449 if (pSwitcher->offR0HostToGuest == offCode)
1450 RTLogPrintf(" *R0HostToGuest:\n");
1451 if (pSwitcher->offGCGuestToHost == offCode)
1452 RTLogPrintf(" *GCGuestToHost:\n");
1453 if (pSwitcher->offGCCallTrampoline == offCode)
1454 RTLogPrintf(" *GCCallTrampoline:\n");
1455 if (pSwitcher->offGCGuestToHostAsm == offCode)
1456 RTLogPrintf(" *GCGuestToHostAsm:\n");
1457 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1458 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1459 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1460 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1461
1462 /* disas */
1463 uint32_t cbInstr = 0;
1464 char szDisas[256];
1465 if (DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas))
1466 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1467 else
1468 {
1469 RTLogPrintf(" %04x: %02x '%c'\n",
1470 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1471 cbInstr = 1;
1472 }
1473 offCode += cbInstr;
1474 cbCode -= RT_MIN(cbInstr, cbCode);
1475 }
1476 }
1477 }
1478#endif
1479}
1480
1481
1482/**
1483 * Relocator for the 32-Bit to 32-Bit world switcher.
1484 */
1485DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1486{
1487 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1488 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1489}
1490
1491
1492/**
1493 * Relocator for the 32-Bit to PAE world switcher.
1494 */
1495DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1496{
1497 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1498 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1499}
1500
1501
1502/**
1503 * Relocator for the PAE to 32-Bit world switcher.
1504 */
1505DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1506{
1507 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1508 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1509}
1510
1511
1512/**
1513 * Relocator for the PAE to PAE world switcher.
1514 */
1515DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1516{
1517 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1518 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1519}
1520
1521
1522/**
1523 * Relocator for the AMD64 to PAE world switcher.
1524 */
1525DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1526{
1527 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1528 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1529}
1530
1531
1532/**
1533 * Gets the pointer to g_szRTAssertMsg1 in GC.
1534 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1535 * Returns NULL if not present.
1536 * @param pVM The VM handle.
1537 */
1538VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1539{
1540 RTGCPTR GCPtr;
1541 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1542 if (VBOX_SUCCESS(rc))
1543 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1544 return NULL;
1545}
1546
1547
1548/**
1549 * Gets the pointer to g_szRTAssertMsg2 in GC.
1550 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1551 * Returns NULL if not present.
1552 * @param pVM The VM handle.
1553 */
1554VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1555{
1556 RTGCPTR GCPtr;
1557 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1558 if (VBOX_SUCCESS(rc))
1559 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1560 return NULL;
1561}
1562
1563
1564/**
1565 * Execute state save operation.
1566 *
1567 * @returns VBox status code.
1568 * @param pVM VM Handle.
1569 * @param pSSM SSM operation handle.
1570 */
1571static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1572{
1573 LogFlow(("vmmR3Save:\n"));
1574
1575 /*
1576 * The hypervisor stack.
1577 */
1578 SSMR3PutGCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1579 RTGCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1580 Assert(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE);
1581 SSMR3PutGCPtr(pSSM, GCPtrESP);
1582 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1583 return SSMR3PutU32(pSSM, ~0); /* terminator */
1584}
1585
1586
1587/**
1588 * Execute state load operation.
1589 *
1590 * @returns VBox status code.
1591 * @param pVM VM Handle.
1592 * @param pSSM SSM operation handle.
1593 * @param u32Version Data layout version.
1594 */
1595static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1596{
1597 LogFlow(("vmmR3Load:\n"));
1598
1599 /*
1600 * Validate version.
1601 */
1602 if (u32Version != VMM_SAVED_STATE_VERSION)
1603 {
1604 Log(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1605 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1606 }
1607
1608 /*
1609 * Check that the stack is in the same place, or that it's fearly empty.
1610 */
1611 RTGCPTR GCPtrStackBottom;
1612 SSMR3GetGCPtr(pSSM, &GCPtrStackBottom);
1613 RTGCPTR GCPtrESP;
1614 int rc = SSMR3GetGCPtr(pSSM, &GCPtrESP);
1615 if (VBOX_FAILURE(rc))
1616 return rc;
1617 if ( GCPtrStackBottom == pVM->vmm.s.pbGCStackBottom
1618 || (GCPtrStackBottom - GCPtrESP < 32)) /** @todo This will break if we start preemting the hypervisor. */
1619 {
1620 /*
1621 * We *must* set the ESP because the CPUM load + PGM load relocations will render
1622 * the ESP in CPUM fatally invalid.
1623 */
1624 CPUMSetHyperESP(pVM, GCPtrESP);
1625
1626 /* restore the stack. */
1627 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1628
1629 /* terminator */
1630 uint32_t u32;
1631 rc = SSMR3GetU32(pSSM, &u32);
1632 if (VBOX_FAILURE(rc))
1633 return rc;
1634 if (u32 != ~0U)
1635 {
1636 AssertMsgFailed(("u32=%#x\n", u32));
1637 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1638 }
1639 return VINF_SUCCESS;
1640 }
1641
1642 LogRel(("The stack is not in the same place and it's not empty! GCPtrStackBottom=%VGv pbGCStackBottom=%VGv ESP=%VGv\n",
1643 GCPtrStackBottom, pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1644 AssertFailed();
1645 return VERR_SSM_LOAD_CONFIG_MISMATCH;
1646}
1647
1648
1649/**
1650 * Selects the switcher to be used for switching to GC.
1651 *
1652 * @returns VBox status code.
1653 * @param pVM VM handle.
1654 * @param enmSwitcher The new switcher.
1655 * @remark This function may be called before the VMM is initialized.
1656 */
1657VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1658{
1659 /*
1660 * Validate input.
1661 */
1662 if ( enmSwitcher < VMMSWITCHER_INVALID
1663 || enmSwitcher >= VMMSWITCHER_MAX)
1664 {
1665 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1666 return VERR_INVALID_PARAMETER;
1667 }
1668
1669 /*
1670 * Select the new switcher.
1671 */
1672 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1673 if (pSwitcher)
1674 {
1675 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1676 pVM->vmm.s.enmSwitcher = enmSwitcher;
1677
1678 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1679 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1680
1681 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1682 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1683 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1684 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1685 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1686 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1687 return VINF_SUCCESS;
1688 }
1689 return VERR_NOT_IMPLEMENTED;
1690}
1691
1692/**
1693 * Disable the switcher logic permanently.
1694 *
1695 * @returns VBox status code.
1696 * @param pVM VM handle.
1697 */
1698VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1699{
1700/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1701 * @code
1702 * mov eax, VERR_INTERNAL_ERROR
1703 * ret
1704 * @endcode
1705 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1706 */
1707 pVM->vmm.s.fSwitcherDisabled = true;
1708 return VINF_SUCCESS;
1709}
1710
1711
1712/**
1713 * Resolve a builtin GC symbol.
1714 * Called by PDM when loading or relocating GC modules.
1715 *
1716 * @returns VBox status
1717 * @param pVM VM Handle.
1718 * @param pszSymbol Symbol to resolv
1719 * @param pGCPtrValue Where to store the symbol value.
1720 * @remark This has to work before VMMR3Relocate() is called.
1721 */
1722VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1723{
1724 if (!strcmp(pszSymbol, "g_Logger"))
1725 {
1726 if (pVM->vmm.s.pLoggerHC)
1727 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1728 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1729 }
1730 else if (!strcmp(pszSymbol, "g_RelLogger"))
1731 {
1732#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1733 if (pVM->vmm.s.pRelLoggerHC)
1734 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1735 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1736#else
1737 *pGCPtrValue = NIL_RTGCPTR;
1738#endif
1739 }
1740 else
1741 return VERR_SYMBOL_NOT_FOUND;
1742 return VINF_SUCCESS;
1743}
1744
1745
1746/**
1747 * Suspends the the CPU yielder.
1748 *
1749 * @param pVM The VM handle.
1750 */
1751VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1752{
1753 if (!pVM->vmm.s.cYieldResumeMillies)
1754 {
1755 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1756 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1757 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1758 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1759 else
1760 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1761 TMTimerStop(pVM->vmm.s.pYieldTimer);
1762 }
1763 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1764}
1765
1766
1767/**
1768 * Stops the the CPU yielder.
1769 *
1770 * @param pVM The VM handle.
1771 */
1772VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1773{
1774 if (!pVM->vmm.s.cYieldResumeMillies)
1775 TMTimerStop(pVM->vmm.s.pYieldTimer);
1776 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1777 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1778}
1779
1780
1781/**
1782 * Resumes the CPU yielder when it has been a suspended or stopped.
1783 *
1784 * @param pVM The VM handle.
1785 */
1786VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1787{
1788 if (pVM->vmm.s.cYieldResumeMillies)
1789 {
1790 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1791 pVM->vmm.s.cYieldResumeMillies = 0;
1792 }
1793}
1794
1795
1796/**
1797 * Internal timer callback function.
1798 *
1799 * @param pVM The VM.
1800 * @param pTimer The timer handle.
1801 * @param pvUser User argument specified upon timer creation.
1802 */
1803static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1804{
1805 /*
1806 * This really needs some careful tuning. While we shouldn't be too gready since
1807 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1808 * because that'll cause us to stop up.
1809 *
1810 * The current logic is to use the default interval when there is no lag worth
1811 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1812 *
1813 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1814 * so the lag is up to date.)
1815 */
1816 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1817 if ( u64Lag < 50000000 /* 50ms */
1818 || ( u64Lag < 1000000000 /* 1s */
1819 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1820 )
1821 {
1822 uint64_t u64Elapsed = RTTimeNanoTS();
1823 pVM->vmm.s.u64LastYield = u64Elapsed;
1824
1825 RTThreadYield();
1826
1827#ifdef LOG_ENABLED
1828 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1829 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1830#endif
1831 }
1832 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1833}
1834
1835
1836/**
1837 * Acquire global VM lock.
1838 *
1839 * @returns VBox status code
1840 * @param pVM The VM to operate on.
1841 */
1842VMMR3DECL(int) VMMR3Lock(PVM pVM)
1843{
1844 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1845}
1846
1847
1848/**
1849 * Release global VM lock.
1850 *
1851 * @returns VBox status code
1852 * @param pVM The VM to operate on.
1853 */
1854VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1855{
1856 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1857}
1858
1859
1860/**
1861 * Return global VM lock owner.
1862 *
1863 * @returns Thread id of owner.
1864 * @returns NIL_RTTHREAD if no owner.
1865 * @param pVM The VM to operate on.
1866 */
1867VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1868{
1869 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1870}
1871
1872
1873/**
1874 * Checks if the current thread is the owner of the global VM lock.
1875 *
1876 * @returns true if owner.
1877 * @returns false if not owner.
1878 * @param pVM The VM to operate on.
1879 */
1880VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1881{
1882 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1883}
1884
1885
1886/**
1887 * Executes guest code.
1888 *
1889 * @param pVM VM handle.
1890 */
1891VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1892{
1893 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1894
1895 /*
1896 * Set the EIP and ESP.
1897 */
1898 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1899 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1900 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1901 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1902
1903 /*
1904 * We hide log flushes (outer) and hypervisor interrupts (inner).
1905 */
1906 for (;;)
1907 {
1908 int rc;
1909 do
1910 {
1911#ifdef NO_SUPCALLR0VMM
1912 rc = VERR_GENERAL_FAILURE;
1913#else
1914 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
1915#endif
1916 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1917
1918 /*
1919 * Flush the logs.
1920 */
1921#ifdef LOG_ENABLED
1922 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1923 if ( pLogger
1924 && pLogger->offScratch > 0)
1925 RTLogFlushGC(NULL, pLogger);
1926#endif
1927#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1928 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1929 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1930 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1931#endif
1932 if (rc != VINF_VMM_CALL_HOST)
1933 {
1934 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1935 return rc;
1936 }
1937 rc = vmmR3ServiceCallHostRequest(pVM);
1938 if (VBOX_FAILURE(rc))
1939 return rc;
1940 /* Resume GC */
1941 }
1942}
1943
1944
1945/**
1946 * Executes guest code (Intel VMX and AMD SVM).
1947 *
1948 * @param pVM VM handle.
1949 */
1950VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1951{
1952 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1953
1954 for (;;)
1955 {
1956 int rc;
1957 do
1958 {
1959#ifdef NO_SUPCALLR0VMM
1960 rc = VERR_GENERAL_FAILURE;
1961#else
1962 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_RUN, NULL);
1963#endif
1964 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1965
1966#ifdef LOG_ENABLED
1967 /*
1968 * Flush the log
1969 */
1970 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
1971 if ( pR0Logger
1972 && pR0Logger->Logger.offScratch > 0)
1973 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
1974#endif /* !LOG_ENABLED */
1975 if (rc != VINF_VMM_CALL_HOST)
1976 {
1977 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1978 return rc;
1979 }
1980 rc = vmmR3ServiceCallHostRequest(pVM);
1981 if (VBOX_FAILURE(rc))
1982 return rc;
1983 /* Resume R0 */
1984 }
1985}
1986
1987/**
1988 * Calls GC a function.
1989 *
1990 * @param pVM The VM handle.
1991 * @param GCPtrEntry The GC function address.
1992 * @param cArgs The number of arguments in the ....
1993 * @param ... Arguments to the function.
1994 */
1995VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, ...)
1996{
1997 va_list args;
1998 va_start(args, cArgs);
1999 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2000 va_end(args);
2001 return rc;
2002}
2003
2004
2005/**
2006 * Calls GC a function.
2007 *
2008 * @param pVM The VM handle.
2009 * @param GCPtrEntry The GC function address.
2010 * @param cArgs The number of arguments in the ....
2011 * @param args Arguments to the function.
2012 */
2013VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, va_list args)
2014{
2015 Log2(("VMMR3CallGCV: GCPtrEntry=%VGv cArgs=%d\n", GCPtrEntry, cArgs));
2016
2017 /*
2018 * Setup the call frame using the trampoline.
2019 */
2020 CPUMHyperSetCtxCore(pVM, NULL);
2021 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2022 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR));
2023 PRTGCUINTPTR pFrame = (PRTGCUINTPTR)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2024 int i = cArgs;
2025 while (i-- > 0)
2026 *pFrame++ = va_arg(args, RTGCUINTPTR);
2027
2028 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR)); /* stack frame size */
2029 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2030 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2031
2032 /*
2033 * We hide log flushes (outer) and hypervisor interrupts (inner).
2034 */
2035 for (;;)
2036 {
2037 int rc;
2038 do
2039 {
2040#ifdef NO_SUPCALLR0VMM
2041 rc = VERR_GENERAL_FAILURE;
2042#else
2043 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2044#endif
2045 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2046
2047 /*
2048 * Flush the logs.
2049 */
2050#ifdef LOG_ENABLED
2051 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2052 if ( pLogger
2053 && pLogger->offScratch > 0)
2054 RTLogFlushGC(NULL, pLogger);
2055#endif
2056#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2057 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2058 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2059 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2060#endif
2061 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2062 VMMR3FatalDump(pVM, rc);
2063 if (rc != VINF_VMM_CALL_HOST)
2064 {
2065 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2066 return rc;
2067 }
2068 rc = vmmR3ServiceCallHostRequest(pVM);
2069 if (VBOX_FAILURE(rc))
2070 return rc;
2071 }
2072}
2073
2074
2075/**
2076 * Resumes executing hypervisor code when interrupted
2077 * by a queue flush or a debug event.
2078 *
2079 * @returns VBox status code.
2080 * @param pVM VM handle.
2081 */
2082VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2083{
2084 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2085
2086 /*
2087 * We hide log flushes (outer) and hypervisor interrupts (inner).
2088 */
2089 for (;;)
2090 {
2091 int rc;
2092 do
2093 {
2094#ifdef NO_SUPCALLR0VMM
2095 rc = VERR_GENERAL_FAILURE;
2096#else
2097 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2098#endif
2099 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2100
2101 /*
2102 * Flush the loggers,
2103 */
2104#ifdef LOG_ENABLED
2105 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2106 if ( pLogger
2107 && pLogger->offScratch > 0)
2108 RTLogFlushGC(NULL, pLogger);
2109#endif
2110#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2111 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2112 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2113 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2114#endif
2115 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2116 VMMR3FatalDump(pVM, rc);
2117 if (rc != VINF_VMM_CALL_HOST)
2118 {
2119 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2120 return rc;
2121 }
2122 rc = vmmR3ServiceCallHostRequest(pVM);
2123 if (VBOX_FAILURE(rc))
2124 return rc;
2125 }
2126}
2127
2128
2129/**
2130 * Service a call to the ring-3 host code.
2131 *
2132 * @returns VBox status code.
2133 * @param pVM VM handle.
2134 * @remark Careful with critsects.
2135 */
2136static int vmmR3ServiceCallHostRequest(PVM pVM)
2137{
2138 switch (pVM->vmm.s.enmCallHostOperation)
2139 {
2140 /*
2141 * Acquire the PDM lock.
2142 */
2143 case VMMCALLHOST_PDM_LOCK:
2144 {
2145 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2146 break;
2147 }
2148
2149 /*
2150 * Flush a PDM queue.
2151 */
2152 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2153 {
2154 PDMR3QueueFlushWorker(pVM, NULL);
2155 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2156 break;
2157 }
2158
2159 /*
2160 * Grow the PGM pool.
2161 */
2162 case VMMCALLHOST_PGM_POOL_GROW:
2163 {
2164 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2165 break;
2166 }
2167
2168 /*
2169 * Acquire the PGM lock.
2170 */
2171 case VMMCALLHOST_PGM_LOCK:
2172 {
2173 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2174 break;
2175 }
2176
2177 /*
2178 * Flush REM handler notifications.
2179 */
2180 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2181 {
2182 REMR3ReplayHandlerNotifications(pVM);
2183 break;
2184 }
2185
2186 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2187 {
2188 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, pVM->vmm.s.u64CallHostArg);
2189 break;
2190 }
2191
2192 /*
2193 * This is a noop. We just take this route to avoid unnecessary
2194 * tests in the loops.
2195 */
2196 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2197 break;
2198
2199 /*
2200 * Set the VM error message.
2201 */
2202 case VMMCALLHOST_VM_SET_ERROR:
2203 VMR3SetErrorWorker(pVM);
2204 break;
2205
2206 /*
2207 * Set the VM runtime error message.
2208 */
2209 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2210 VMR3SetRuntimeErrorWorker(pVM);
2211 break;
2212
2213 default:
2214 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2215 return VERR_INTERNAL_ERROR;
2216 }
2217
2218 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2219 return VINF_SUCCESS;
2220}
2221
2222
2223
2224/**
2225 * Structure to pass to DBGFR3Info() and for doing all other
2226 * output during fatal dump.
2227 */
2228typedef struct VMMR3FATALDUMPINFOHLP
2229{
2230 /** The helper core. */
2231 DBGFINFOHLP Core;
2232 /** The release logger instance. */
2233 PRTLOGGER pRelLogger;
2234 /** The saved release logger flags. */
2235 RTUINT fRelLoggerFlags;
2236 /** The logger instance. */
2237 PRTLOGGER pLogger;
2238 /** The saved logger flags. */
2239 RTUINT fLoggerFlags;
2240 /** The saved logger destination flags. */
2241 RTUINT fLoggerDestFlags;
2242 /** Whether to output to stderr or not. */
2243 bool fStdErr;
2244} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2245typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2246
2247
2248/**
2249 * Print formatted string.
2250 *
2251 * @param pHlp Pointer to this structure.
2252 * @param pszFormat The format string.
2253 * @param ... Arguments.
2254 */
2255static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2256{
2257 va_list args;
2258 va_start(args, pszFormat);
2259 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2260 va_end(args);
2261}
2262
2263
2264/**
2265 * Print formatted string.
2266 *
2267 * @param pHlp Pointer to this structure.
2268 * @param pszFormat The format string.
2269 * @param args Argument list.
2270 */
2271static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2272{
2273 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2274
2275 if (pMyHlp->pRelLogger)
2276 {
2277 va_list args2;
2278 va_copy(args2, args);
2279 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2280 va_end(args2);
2281 }
2282 if (pMyHlp->pLogger)
2283 {
2284 va_list args2;
2285 va_copy(args2, args);
2286 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2287 va_end(args2);
2288 }
2289 if (pMyHlp->fStdErr)
2290 {
2291 va_list args2;
2292 va_copy(args2, args);
2293 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2294 va_end(args2);
2295 }
2296}
2297
2298
2299/**
2300 * Initializes the fatal dump output helper.
2301 *
2302 * @param pHlp The structure to initialize.
2303 */
2304static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2305{
2306 memset(pHlp, 0, sizeof(*pHlp));
2307
2308 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2309 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2310
2311 /*
2312 * The loggers.
2313 */
2314 pHlp->pRelLogger = RTLogRelDefaultInstance();
2315#ifndef LOG_ENABLED
2316 if (!pHlp->pRelLogger)
2317#endif
2318 pHlp->pLogger = RTLogDefaultInstance();
2319
2320 if (pHlp->pRelLogger)
2321 {
2322 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2323 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2324 }
2325
2326 if (pHlp->pLogger)
2327 {
2328 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2329 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2330 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2331#ifndef DEBUG_sandervl
2332 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2333#endif
2334 }
2335
2336 /*
2337 * Check if we need write to stderr.
2338 */
2339 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2340 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2341}
2342
2343
2344/**
2345 * Deletes the fatal dump output helper.
2346 *
2347 * @param pHlp The structure to delete.
2348 */
2349static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2350{
2351 if (pHlp->pRelLogger)
2352 {
2353 RTLogFlush(pHlp->pRelLogger);
2354 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2355 }
2356
2357 if (pHlp->pLogger)
2358 {
2359 RTLogFlush(pHlp->pLogger);
2360 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2361 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2362 }
2363}
2364
2365
2366/**
2367 * Dumps the VM state on a fatal error.
2368 *
2369 * @param pVM VM Handle.
2370 * @param rcErr VBox status code.
2371 */
2372VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2373{
2374 /*
2375 * Create our output helper and sync it with the log settings.
2376 * This helper will be used for all the output.
2377 */
2378 VMMR3FATALDUMPINFOHLP Hlp;
2379 PCDBGFINFOHLP pHlp = &Hlp.Core;
2380 vmmR3FatalDumpInfoHlpInit(&Hlp);
2381
2382 /*
2383 * Header.
2384 */
2385 pHlp->pfnPrintf(pHlp,
2386 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2387 "!!\n"
2388 "!! Guru Meditation %d (%Vrc)\n"
2389 "!!\n",
2390 rcErr, rcErr);
2391
2392 /*
2393 * Continue according to context.
2394 */
2395 bool fDoneHyper = false;
2396 switch (rcErr)
2397 {
2398 /*
2399 * Hyper visor errors.
2400 */
2401 case VINF_EM_DBG_HYPER_ASSERTION:
2402 pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2403 /* fall thru */
2404 case VERR_TRPM_DONT_PANIC:
2405 case VERR_TRPM_PANIC:
2406 case VINF_EM_RAW_STALE_SELECTOR:
2407 case VINF_EM_RAW_IRET_TRAP:
2408 case VINF_EM_DBG_HYPER_BREAKPOINT:
2409 case VINF_EM_DBG_HYPER_STEPPED:
2410 {
2411 /* Trap? */
2412 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2413 TRPMEVENT enmType;
2414 uint8_t u8TrapNo = 0xce;
2415 RTGCUINT uErrorCode = 0xdeadface;
2416 RTGCUINTPTR uCR2 = 0xdeadface;
2417 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2418 if (VBOX_SUCCESS(rc2))
2419 pHlp->pfnPrintf(pHlp,
2420 "!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv Type=%d\n",
2421 u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2422 else
2423 pHlp->pfnPrintf(pHlp,
2424 "!! EIP=%VGv NOTRAP\n",
2425 uEIP);
2426
2427 /*
2428 * Try figure out where eip is.
2429 */
2430 /** @todo make query call for core code or move this function to VMM. */
2431 /* core code? */
2432 //if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2433 // pHlp->pfnPrintf(pHlp,
2434 // "!! EIP is in CoreCode, offset %#x\n",
2435 // uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2436 //else
2437 { /* ask PDM */
2438 /** @todo ask DBGFR3Sym later. */
2439 char szModName[64];
2440 RTGCPTR GCPtrMod;
2441 char szNearSym1[260];
2442 RTGCPTR GCPtrNearSym1;
2443 char szNearSym2[260];
2444 RTGCPTR GCPtrNearSym2;
2445 int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2446 &szModName[0], sizeof(szModName), &GCPtrMod,
2447 &szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2448 &szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2449 if (VBOX_SUCCESS(rc))
2450 {
2451 pHlp->pfnPrintf(pHlp,
2452 "!! EIP in %s (%p) at rva %x near symbols:\n"
2453 "!! %VGv rva %VGv off %08x %s\n"
2454 "!! %VGv rva %VGv off -%08x %s\n",
2455 szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2456 GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2457 GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2458 }
2459 else
2460 pHlp->pfnPrintf(pHlp,
2461 "!! EIP is not in any code known to VMM!\n");
2462 }
2463
2464 /* Disassemble the instruction. */
2465 char szInstr[256];
2466 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2467 if (VBOX_SUCCESS(rc2))
2468 pHlp->pfnPrintf(pHlp,
2469 "!! %s\n", szInstr);
2470
2471 /* Dump the hypervisor cpu state. */
2472 pHlp->pfnPrintf(pHlp,
2473 "!!\n"
2474 "!!\n"
2475 "!!\n");
2476 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2477 fDoneHyper = true;
2478
2479 /* Callstack. */
2480 DBGFSTACKFRAME Frame = {0};
2481 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2482 if (VBOX_SUCCESS(rc2))
2483 {
2484 pHlp->pfnPrintf(pHlp,
2485 "!!\n"
2486 "!! Call Stack:\n"
2487 "!!\n"
2488 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2489 do
2490 {
2491 pHlp->pfnPrintf(pHlp,
2492 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2493 (uint32_t)Frame.AddrFrame.off,
2494 (uint32_t)Frame.AddrReturnFrame.off,
2495 (uint32_t)Frame.AddrReturnPC.Sel,
2496 (uint32_t)Frame.AddrReturnPC.off,
2497 Frame.Args.au32[0],
2498 Frame.Args.au32[1],
2499 Frame.Args.au32[2],
2500 Frame.Args.au32[3]);
2501 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2502 if (Frame.pSymPC)
2503 {
2504 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2505 if (offDisp > 0)
2506 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2507 else if (offDisp < 0)
2508 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2509 else
2510 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2511 }
2512 if (Frame.pLinePC)
2513 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2514 pHlp->pfnPrintf(pHlp, "\n");
2515
2516 /* next */
2517 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2518 } while (VBOX_SUCCESS(rc2));
2519 DBGFR3StackWalkEnd(pVM, &Frame);
2520 }
2521
2522 /* raw stack */
2523 pHlp->pfnPrintf(pHlp,
2524 "!!\n"
2525 "!! Raw stack (mind the direction).\n"
2526 "!!\n"
2527 "%.*Vhxd\n",
2528 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2529 break;
2530 }
2531
2532 default:
2533 {
2534 break;
2535 }
2536
2537 } /* switch (rcErr) */
2538
2539
2540 /*
2541 * Dump useful state information.
2542 */
2543 /** @todo convert these dumpers to DBGFR3Info() handlers!!! */
2544 pHlp->pfnPrintf(pHlp,
2545 "!!\n"
2546 "!! PGM Access Handlers & Stuff:\n"
2547 "!!\n");
2548 PGMR3DumpMappings(pVM);
2549
2550
2551 /*
2552 * Generic info dumper loop.
2553 */
2554 static struct
2555 {
2556 const char *pszInfo;
2557 const char *pszArgs;
2558 } const aInfo[] =
2559 {
2560 { "hma", NULL },
2561 { "cpumguest", "verbose" },
2562 { "cpumhyper", "verbose" },
2563 { "cpumhost", "verbose" },
2564 { "mode", "all" },
2565 { "cpuid", "verbose" },
2566 { "gdt", NULL },
2567 { "ldt", NULL },
2568 //{ "tss", NULL },
2569 { "ioport", NULL },
2570 { "mmio", NULL },
2571 { "phys", NULL },
2572 //{ "pgmpd", NULL }, - doesn't always work at init time...
2573 { "timers", NULL },
2574 { "activetimers", NULL },
2575 { "handlers", "phys virt stats" },
2576 { "cfgm", NULL },
2577 };
2578 for (unsigned i = 0; i < ELEMENTS(aInfo); i++)
2579 {
2580 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2581 continue;
2582 pHlp->pfnPrintf(pHlp,
2583 "!!\n"
2584 "!! {%s, %s}\n"
2585 "!!\n",
2586 aInfo[i].pszInfo, aInfo[i].pszArgs);
2587 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2588 }
2589
2590 /* done */
2591 pHlp->pfnPrintf(pHlp,
2592 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2593
2594
2595 /*
2596 * Delete the output instance (flushing and restoring of flags).
2597 */
2598 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2599}
2600
2601
2602
2603/**
2604 * Displays the Force action Flags.
2605 *
2606 * @param pVM The VM handle.
2607 * @param pHlp The output helpers.
2608 * @param pszArgs The additional arguments (ignored).
2609 */
2610static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2611{
2612 const uint32_t fForcedActions = pVM->fForcedActions;
2613
2614 pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2615
2616 /* show the flag mnemonics */
2617 int c = 0;
2618 uint32_t f = fForcedActions;
2619#define PRINT_FLAG(flag) do { \
2620 if (f & (flag)) \
2621 { \
2622 static const char *s_psz = #flag; \
2623 if (!(c % 6)) \
2624 pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2625 else \
2626 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2627 c++; \
2628 f &= ~(flag); \
2629 } \
2630 } while (0)
2631 PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2632 PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2633 PRINT_FLAG(VM_FF_TIMER);
2634 PRINT_FLAG(VM_FF_PDM_QUEUES);
2635 PRINT_FLAG(VM_FF_PDM_DMA);
2636 PRINT_FLAG(VM_FF_PDM_CRITSECT);
2637 PRINT_FLAG(VM_FF_DBGF);
2638 PRINT_FLAG(VM_FF_REQUEST);
2639 PRINT_FLAG(VM_FF_TERMINATE);
2640 PRINT_FLAG(VM_FF_RESET);
2641 PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2642 PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2643 PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2644 PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2645 PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2646 PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2647 PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2648 PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2649 PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2650 PRINT_FLAG(VM_FF_TO_R3);
2651 PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2652 if (f)
2653 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2654 else
2655 pHlp->pfnPrintf(pHlp, "\n");
2656#undef PRINT_FLAG
2657
2658 /* the groups */
2659 c = 0;
2660#define PRINT_GROUP(grp) do { \
2661 if (fForcedActions & (grp)) \
2662 { \
2663 static const char *s_psz = #grp; \
2664 if (!(c % 5)) \
2665 pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2666 else \
2667 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2668 c++; \
2669 } \
2670 } while (0)
2671 PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2672 PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2673 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2674 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2675 PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2676 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2677 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2678 PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2679 PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2680 if (c)
2681 pHlp->pfnPrintf(pHlp, "\n");
2682#undef PRINT_GROUP
2683}
2684
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