VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 3700

Last change on this file since 3700 was 3700, checked in by vboxsync, 17 years ago

r0 logging for me
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 93.6 KB
Line 
1/* $Id: VMM.cpp 3700 2007-07-18 19:26:10Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/** @page pg_vmm VMM - The Virtual Machine Monitor
25 *
26 * !Revise this! It's already incorrect!
27 *
28 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
29 * manages the alternate reality; controlling the virtualization, managing
30 * resources, tracking CPU state, it's resources and so on...
31 *
32 * We will split the VMM into smaller entities:
33 *
34 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
35 * provide ring and world switching, that including routing
36 * interrupts to the host OS and traps to the appropriate trap
37 * handlers. It will implement an external interface for
38 * managing trap handlers.
39 *
40 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
41 * reality) and implementing external interfaces to read and change
42 * the state.
43 *
44 * - Memory Monitor (MM), which purpose it is to virtualize physical
45 * pages, segment descriptor tables, interrupt descriptor tables, task
46 * segments, and keep track of all memory providing external interfaces
47 * to access content and map pages. (Internally splitt into smaller entities!)
48 *
49 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
50 * interacts with the MM to implement memory mapped I/O. External
51 * interfaces for adding and removing I/O ranges are implemented.
52 *
53 * - External Interrupt Monitor (EIM), which purpose it is to manage
54 * interrupts generated by virtual devices. This monitor provides
55 * an interfaces for raising interrupts which is accessible at any
56 * time and from all thread.
57 * <p>
58 * A subentity of the EIM is the vitual Programmable Interrupt
59 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
60 * Programmable Interrupt Controller Device (VAPICD).
61 *
62 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
63 * virtual device using the DMA controller. Interfaces must be as the
64 * EIM interfaces independent and threadable.
65 * <p>
66 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
67 *
68 *
69 * Entities working on a higher level:
70 *
71 * - Device Manager (DM), which is a support facility for virtualized
72 * hardware. This provides generic facilities for efficient device
73 * virtualization. It will manage device attaching and detaching
74 * conversing with EIM and IOM.
75 *
76 * - Debugger Facility (DBGF) provides the basic features for
77 * debugging the alternate reality execution.
78 *
79 *
80 *
81 * @section pg_vmm_s_use_cases Use Cases
82 *
83 * @subsection pg_vmm_s_use_case_boot Bootstrap
84 *
85 * - Basic Init:
86 * - Init SUPDRV.
87 *
88 * - Init Virtual Machine Instance:
89 * - Load settings.
90 * - Check resource requirements (memory, com, stuff).
91 *
92 * - Init Host Ring 3 part:
93 * - Init Core code.
94 * - Load Pluggable Components.
95 * - Init Pluggable Components.
96 *
97 * - Init Host Ring 0 part:
98 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
99 * - Init Core code.
100 * - Load Pluggable Component code.
101 * - Init Pluggable Component code.
102 *
103 * - Allocate first chunk of memory and pin it down. This block of memory
104 * will fit the following pieces:
105 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
106 * (This is available from everywhere (at different addresses though)).
107 * - VMM Guest Context code.
108 * - Pluggable devices Guest Context code.
109 * - Page tables (directory and everything) for the VMM Guest
110 *
111 * - Setup Guest (Ring 0) part:
112 * - Setup initial page tables (i.e. directory all the stuff).
113 * - Load Core Guest Context code.
114 * - Load Pluggable Devices Guest Context code.
115 *
116 *
117 */
118
119
120/*******************************************************************************
121* Header Files *
122*******************************************************************************/
123#define LOG_GROUP LOG_GROUP_VMM
124#include <VBox/vmm.h>
125#include <VBox/vmapi.h>
126#include <VBox/pgm.h>
127#include <VBox/cfgm.h>
128#include <VBox/pdm.h>
129#include <VBox/cpum.h>
130#include <VBox/mm.h>
131#include <VBox/iom.h>
132#include <VBox/trpm.h>
133#include <VBox/selm.h>
134#include <VBox/em.h>
135#include <VBox/sup.h>
136#include <VBox/dbgf.h>
137#include <VBox/csam.h>
138#include <VBox/patm.h>
139#include <VBox/rem.h>
140#include <VBox/ssm.h>
141#include <VBox/tm.h>
142#include "VMMInternal.h"
143#include "VMMSwitcher/VMMSwitcher.h"
144#include <VBox/vm.h>
145#include <VBox/err.h>
146#include <VBox/param.h>
147#include <VBox/version.h>
148#include <VBox/x86.h>
149#include <VBox/hwaccm.h>
150#include <iprt/assert.h>
151#include <iprt/alloc.h>
152#include <iprt/asm.h>
153#include <iprt/time.h>
154#include <iprt/stream.h>
155#include <iprt/string.h>
156#include <iprt/stdarg.h>
157#include <iprt/ctype.h>
158
159
160
161/** The saved state version. */
162#define VMM_SAVED_STATE_VERSION 3
163
164
165/*******************************************************************************
166* Internal Functions *
167*******************************************************************************/
168static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
169static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
170static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
171static int vmmR3ServiceCallHostRequest(PVM pVM);
172
173
174/*******************************************************************************
175* Global Variables *
176*******************************************************************************/
177/** Array of switcher defininitions.
178 * The type and index shall match!
179 */
180static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
181{
182 NULL, /* invalid entry */
183#ifndef RT_ARCH_AMD64
184 &vmmR3Switcher32BitTo32Bit_Def,
185 &vmmR3Switcher32BitToPAE_Def,
186 NULL, //&vmmR3Switcher32BitToAMD64_Def,
187 &vmmR3SwitcherPAETo32Bit_Def,
188 &vmmR3SwitcherPAEToPAE_Def,
189 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
190# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
191 &vmmR3SwitcherAMD64ToPAE_Def,
192# else
193 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
194# endif
195 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
196#else
197 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
198 NULL, //&vmmR3Switcher32BitToPAE_Def,
199 NULL, //&vmmR3Switcher32BitToAMD64_Def,
200 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
201 NULL, //&vmmR3SwitcherPAEToPAE_Def,
202 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
203 &vmmR3SwitcherAMD64ToPAE_Def,
204 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
205#endif
206};
207
208
209
210/**
211 * Initiates the core code.
212 *
213 * This is core per VM code which might need fixups and/or for ease of use
214 * are put on linear contiguous backing.
215 *
216 * @returns VBox status code.
217 * @param pVM Pointer to VM structure.
218 */
219static int vmmR3InitCoreCode(PVM pVM)
220{
221 /*
222 * Calc the size.
223 */
224 unsigned cbCoreCode = 0;
225 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
226 {
227 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
228 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
229 if (pSwitcher)
230 {
231 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
232 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
233 }
234 }
235
236 /*
237 * Allocate continguous pages for switchers and deal with
238 * conflicts in the intermediate mapping of the code.
239 */
240 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
241 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
242 int rc = VERR_NO_MEMORY;
243 if (pVM->vmm.s.pvHCCoreCodeR3)
244 {
245 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
246 if (rc == VERR_PGM_MAPPINGS_FIX_CONFLICT)
247 {
248 /* try more allocations. */
249 struct
250 {
251 RTR0PTR pvR0;
252 void *pvR3;
253 RTHCPHYS HCPhys;
254 RTUINT cb;
255 } aBadTries[16];
256 unsigned i = 0;
257 do
258 {
259 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
260 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
261 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
262 i++;
263 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
264 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
265 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
266 if (!pVM->vmm.s.pvHCCoreCodeR3)
267 break;
268 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
269 } while ( rc == VERR_PGM_MAPPINGS_FIX_CONFLICT
270 && i < ELEMENTS(aBadTries) - 1);
271
272 /* cleanup */
273 if (VBOX_FAILURE(rc))
274 {
275 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
276 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
277 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
278 aBadTries[i].cb = pVM->vmm.s.cbCoreCode;
279 i++;
280 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
281 }
282 while (i-- > 0)
283 {
284 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
285 i, aBadTries[i].pvR3, aBadTries[i].pvR0, aBadTries[i].HCPhys));
286 SUPContFree(aBadTries[i].pvR3, aBadTries[i].cb >> PAGE_SHIFT);
287 }
288 }
289 }
290 if (VBOX_SUCCESS(rc))
291 {
292 /*
293 * copy the code.
294 */
295 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
296 {
297 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
298 if (pSwitcher)
299 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
300 pSwitcher->pvCode, pSwitcher->cbCode);
301 }
302
303 /*
304 * Map the code into the GC address space.
305 */
306 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &pVM->vmm.s.pvGCCoreCode);
307 if (VBOX_SUCCESS(rc))
308 {
309 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
310 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VGv Phys=%VHp cb=%#x\n",
311 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
312
313 /*
314 * Finally, PGM probably have selected a switcher already but we need
315 * to do get the addresses so we'll reselect it.
316 * This may legally fail so, we're ignoring the rc.
317 */
318 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
319 return rc;
320 }
321
322 /* shit */
323 AssertMsgFailed(("PGMR3Map(,%VGv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
324 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
325 }
326 else
327 VMSetError(pVM, rc, RT_SRC_POS,
328 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code."),
329 cbCoreCode);
330
331 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
332 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
333 pVM->vmm.s.pvGCCoreCode = 0;
334 return rc;
335}
336
337
338/**
339 * Initializes the VMM.
340 *
341 * @returns VBox status code.
342 * @param pVM The VM to operate on.
343 */
344VMMR3DECL(int) VMMR3Init(PVM pVM)
345{
346 LogFlow(("VMMR3Init\n"));
347
348 /*
349 * Assert alignment, sizes and order.
350 */
351 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
352 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
353 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
354 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
355
356 /*
357 * Init basic VM VMM members.
358 */
359 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
360 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
361 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
362 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
363 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
364 else
365 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
366
367 /* GC switchers are enabled by default. Turned off by HWACCM. */
368 pVM->vmm.s.fSwitcherDisabled = false;
369
370 /*
371 * Register the saved state data unit.
372 */
373 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
374 NULL, vmmR3Save, NULL,
375 NULL, vmmR3Load, NULL);
376 if (VBOX_FAILURE(rc))
377 return rc;
378
379#ifdef VBOX_WITHOUT_IDT_PATCHING
380 /*
381 * Register the Ring-0 VM handle with the session for fast ioctl calls.
382 */
383 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
384 if (VBOX_FAILURE(rc))
385 return rc;
386#endif
387
388 /*
389 * Init core code.
390 */
391 rc = vmmR3InitCoreCode(pVM);
392 if (VBOX_SUCCESS(rc))
393 {
394 /*
395 * Allocate & init VMM GC stack.
396 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
397 * (The page protection is modifed during R3 init completion.)
398 */
399#ifdef VBOX_STRICT_VMM_STACK
400 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
401#else
402 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
403#endif
404 if (VBOX_SUCCESS(rc))
405 {
406 /* Set HC and GC stack pointers to top of stack. */
407 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
408 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
409 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
410 AssertRelease(pVM->vmm.s.pbGCStack);
411
412 /* Set hypervisor eip. */
413 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
414
415 /*
416 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
417 */
418#ifdef LOG_ENABLED
419 PRTLOGGER pLogger = RTLogDefaultInstance();
420 if (pLogger)
421 {
422 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pLogger->cGroups]);
423 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
424 if (VBOX_SUCCESS(rc))
425 {
426 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
427
428/*
429 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
430 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
431 *
432 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
433 * to not stub all the log functions.
434 *
435 * You might also wish to enable the AssertMsg1/2 overrides in VMMR0.cpp when enabling this.
436 */
437# if defined(DEBUG_sandervl) || defined(DEBUG_frank)
438 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
439 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
440 if (VBOX_SUCCESS(rc))
441 {
442 pVM->vmm.s.pR0Logger->pVM = pVM;
443 //pVM->vmm.s.pR0Logger->fCreated = false;
444 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
445 }
446# endif
447 }
448 }
449#endif /* LOG_ENABLED */
450
451#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
452 /*
453 * Allocate GC Release Logger instances (finalized in the relocator).
454 */
455 if (VBOX_SUCCESS(rc))
456 {
457 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
458 if (pRelLogger)
459 {
460 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pRelLogger->cGroups]);
461 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
462 if (VBOX_SUCCESS(rc))
463 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
464 }
465 }
466#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
467
468#ifdef VBOX_WITH_NMI
469 /*
470 * Allocate mapping for the host APIC.
471 */
472 if (VBOX_SUCCESS(rc))
473 {
474 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
475 AssertRC(rc);
476 }
477#endif
478 if (VBOX_SUCCESS(rc))
479 {
480 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
481 if (VBOX_SUCCESS(rc))
482 {
483 /*
484 * Statistics.
485 */
486 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
487 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
488 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
489 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
490 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
491 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
492 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
493 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
494 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
495 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
496 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
497 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
498 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
499 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
500 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
501 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
502 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
503 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
504 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
505 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
506 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
507 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
508 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
509 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
510 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
511 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
512 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
520 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
521 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
522 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
523 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
524 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
525 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
526 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
527 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
528 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
529 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
530 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
531 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
532 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
533 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
534 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
535
536 return VINF_SUCCESS;
537 }
538 AssertRC(rc);
539 }
540 }
541 /** @todo: Need failure cleanup. */
542
543 //more todo in here?
544 //if (VBOX_SUCCESS(rc))
545 //{
546 //}
547 //int rc2 = vmmR3TermCoreCode(pVM);
548 //AssertRC(rc2));
549 }
550
551 return rc;
552}
553
554
555/**
556 * Ring-3 init finalizing.
557 *
558 * @returns VBox status code.
559 * @param pVM The VM handle.
560 */
561VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
562{
563#ifdef VBOX_STRICT_VMM_STACK
564 /*
565 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
566 */
567 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
568 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
569 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
570
571 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
572 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
573 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
574#endif
575
576 /*
577 * Set page attributes to r/w for stack pages.
578 */
579 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
580 AssertRC(rc);
581 if (VBOX_SUCCESS(rc))
582 {
583 /*
584 * Create the EMT yield timer.
585 */
586 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
587 if (VBOX_SUCCESS(rc))
588 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
589 }
590#ifdef VBOX_WITH_NMI
591 /*
592 * Map the host APIC into GC - This may be host os specific!
593 */
594 if (VBOX_SUCCESS(rc))
595 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
596 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
597#endif
598 return rc;
599}
600
601
602/**
603 * Initializes the R0 VMM.
604 *
605 * @returns VBox status code.
606 * @param pVM The VM to operate on.
607 */
608VMMR3DECL(int) VMMR3InitR0(PVM pVM)
609{
610 int rc;
611
612 /*
613 * Initialize the ring-0 logger if we haven't done so yet.
614 */
615 if ( pVM->vmm.s.pR0Logger
616 && !pVM->vmm.s.pR0Logger->fCreated)
617 {
618 rc = VMMR3UpdateLoggers(pVM);
619 if (VBOX_FAILURE(rc))
620 return rc;
621 }
622
623 /*
624 * Call Ring-0 entry with init code.
625 */
626 for (;;)
627 {
628#ifdef NO_SUPCALLR0VMM
629 //rc = VERR_GENERAL_FAILURE;
630 rc = VINF_SUCCESS;
631#else
632 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, (void *)VBOX_VERSION);
633#endif
634 if ( pVM->vmm.s.pR0Logger
635 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
636 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
637 if (rc != VINF_VMM_CALL_HOST)
638 break;
639 rc = vmmR3ServiceCallHostRequest(pVM);
640 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
641 break;
642 break; // remove this when we do setjmp for all ring-0 stuff.
643 }
644
645 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
646 {
647 LogRel(("R0 init failed, rc=%Vra\n", rc));
648 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
649 rc = VERR_INTERNAL_ERROR;
650 }
651 return rc;
652}
653
654
655/**
656 * Initializes the GC VMM.
657 *
658 * @returns VBox status code.
659 * @param pVM The VM to operate on.
660 */
661VMMR3DECL(int) VMMR3InitGC(PVM pVM)
662{
663 /* In VMX mode, there's no need to init GC. */
664 if (pVM->vmm.s.fSwitcherDisabled)
665 return VINF_SUCCESS;
666
667 /*
668 * Call VMMGCInit():
669 * -# resolve the address.
670 * -# setup stackframe and EIP to use the trampoline.
671 * -# do a generic hypervisor call.
672 */
673 RTGCPTR GCPtrEP;
674 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
675 if (VBOX_SUCCESS(rc))
676 {
677 CPUMHyperSetCtxCore(pVM, NULL);
678 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
679 uint64_t u64TS = RTTimeProgramStartNanoTS();
680#if GC_ARCH_BITS == 32
681 CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
682 CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
683#else /* 64-bit GC */
684 CPUMPushHyper(pVM, u64TS); /* Param 3: The program startup TS. */
685#endif
686 CPUMPushHyper(pVM, VBOX_VERSION); /* Param 2: Version argument. */
687 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
688 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
689 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* trampoline param: stacksize. */
690 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
691 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
692
693 for (;;)
694 {
695#ifdef NO_SUPCALLR0VMM
696 //rc = VERR_GENERAL_FAILURE;
697 rc = VINF_SUCCESS;
698#else
699 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
700#endif
701#ifdef LOG_ENABLED
702 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
703 if ( pLogger
704 && pLogger->offScratch > 0)
705 RTLogFlushGC(NULL, pLogger);
706#endif
707#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
708 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
709 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
710 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
711#endif
712 if (rc != VINF_VMM_CALL_HOST)
713 break;
714 rc = vmmR3ServiceCallHostRequest(pVM);
715 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
716 break;
717 }
718
719 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
720 {
721 VMMR3FatalDump(pVM, rc);
722 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
723 rc = VERR_INTERNAL_ERROR;
724 }
725 AssertRC(rc);
726 }
727 return rc;
728}
729
730
731/**
732 * Terminate the VMM bits.
733 *
734 * @returns VINF_SUCCESS.
735 * @param pVM The VM handle.
736 */
737VMMR3DECL(int) VMMR3Term(PVM pVM)
738{
739 /** @todo must call ring-0 so the logger thread instance can be properly removed. */
740
741#ifdef VBOX_STRICT_VMM_STACK
742 /*
743 * Make the two stack guard pages present again.
744 */
745 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
746 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
747#endif
748 return VINF_SUCCESS;
749}
750
751
752/**
753 * Applies relocations to data and code managed by this
754 * component. This function will be called at init and
755 * whenever the VMM need to relocate it self inside the GC.
756 *
757 * The VMM will need to apply relocations to the core code.
758 *
759 * @param pVM The VM handle.
760 * @param offDelta The relocation delta.
761 */
762VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
763{
764 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
765
766 /*
767 * Recalc the GC address.
768 */
769 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
770
771 /*
772 * The stack.
773 */
774 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
775 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
776 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
777
778 /*
779 * All the switchers.
780 */
781 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
782 {
783 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
784 if (pSwitcher && pSwitcher->pfnRelocate)
785 {
786 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
787 pSwitcher->pfnRelocate(pVM,
788 pSwitcher,
789 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
790 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
791 pVM->vmm.s.pvGCCoreCode + off,
792 pVM->vmm.s.HCPhysCoreCode + off);
793 }
794 }
795
796 /*
797 * Recalc the GC address for the current switcher.
798 */
799 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
800 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
801 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
802 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
803 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
804 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
805 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
806
807 /*
808 * Get other GC entry points.
809 */
810 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
811 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
812
813 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
814 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
815
816 /*
817 * Update the logger.
818 */
819 VMMR3UpdateLoggers(pVM);
820}
821
822
823/**
824 * Updates the settings for the GC and R0 loggers.
825 *
826 * @returns VBox status code.
827 * @param pVM The VM handle.
828 */
829VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
830{
831 /*
832 * Simply clone the logger instance (for GC).
833 */
834 int rc = VINF_SUCCESS;
835 RTGCPTR GCPtrLoggerFlush = 0;
836
837 if (pVM->vmm.s.pLoggerHC
838#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
839 || pVM->vmm.s.pRelLoggerHC
840#endif
841 )
842 {
843 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
844 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
845 }
846
847 if (pVM->vmm.s.pLoggerHC)
848 {
849 RTGCPTR GCPtrLoggerWrapper = 0;
850 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
851 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
852 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
853 rc = RTLogCloneGC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
854 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
855 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
856 }
857
858#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
859 if (pVM->vmm.s.pRelLoggerHC)
860 {
861 RTGCPTR GCPtrLoggerWrapper = 0;
862 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
863 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
864 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
865 rc = RTLogCloneGC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
866 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
867 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
868 }
869#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
870
871 /*
872 * For the ring-0 EMT logger, we use a per-thread logger
873 * instance in ring-0. Only initialize it once.
874 */
875 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
876 if (pR0Logger)
877 {
878 if (!pR0Logger->fCreated)
879 {
880 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
881 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
882 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
883
884 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
885 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
886 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
887
888 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
889 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
890 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
891 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
892 pR0Logger->fCreated = true;
893 }
894
895 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, RTLOGFLAGS_BUFFERED, 0);
896 AssertRC(rc);
897 }
898
899 return rc;
900}
901
902
903/**
904 * Generic switch code relocator.
905 *
906 * @param pVM The VM handle.
907 * @param pSwitcher The switcher definition.
908 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
909 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
910 * @param GCPtrCode The guest context address corresponding to pu8Code.
911 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
912 * @param SelCS The hypervisor CS selector.
913 * @param SelDS The hypervisor DS selector.
914 * @param SelTSS The hypervisor TSS selector.
915 * @param GCPtrGDT The GC address of the hypervisor GDT.
916 * @param SelCS64 The 64-bit mode hypervisor CS selector.
917 */
918static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
919 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
920{
921 union
922 {
923 const uint8_t *pu8;
924 const uint16_t *pu16;
925 const uint32_t *pu32;
926 const uint64_t *pu64;
927 const void *pv;
928 uintptr_t u;
929 } u;
930 u.pv = pSwitcher->pvFixups;
931
932 /*
933 * Process fixups.
934 */
935 uint8_t u8;
936 while ((u8 = *u.pu8++) != FIX_THE_END)
937 {
938 /*
939 * Get the source (where to write the fixup).
940 */
941 uint32_t offSrc = *u.pu32++;
942 Assert(offSrc < pSwitcher->cbCode);
943 union
944 {
945 uint8_t *pu8;
946 uint16_t *pu16;
947 uint32_t *pu32;
948 uint64_t *pu64;
949 uintptr_t u;
950 } uSrc;
951 uSrc.pu8 = pu8CodeR3 + offSrc;
952
953 /* The fixup target and method depends on the type. */
954 switch (u8)
955 {
956 /*
957 * 32-bit relative, source in HC and target in GC.
958 */
959 case FIX_HC_2_GC_NEAR_REL:
960 {
961 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
962 uint32_t offTrg = *u.pu32++;
963 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
964 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
965 break;
966 }
967
968 /*
969 * 32-bit relative, source in HC and target in ID.
970 */
971 case FIX_HC_2_ID_NEAR_REL:
972 {
973 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
974 uint32_t offTrg = *u.pu32++;
975 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
976 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (uSrc.u + 4));
977 break;
978 }
979
980 /*
981 * 32-bit relative, source in GC and target in HC.
982 */
983 case FIX_GC_2_HC_NEAR_REL:
984 {
985 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
986 uint32_t offTrg = *u.pu32++;
987 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
988 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
989 break;
990 }
991
992 /*
993 * 32-bit relative, source in GC and target in ID.
994 */
995 case FIX_GC_2_ID_NEAR_REL:
996 {
997 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
998 uint32_t offTrg = *u.pu32++;
999 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1000 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1001 break;
1002 }
1003
1004 /*
1005 * 32-bit relative, source in ID and target in HC.
1006 */
1007 case FIX_ID_2_HC_NEAR_REL:
1008 {
1009 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1010 uint32_t offTrg = *u.pu32++;
1011 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1012 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1013 break;
1014 }
1015
1016 /*
1017 * 32-bit relative, source in ID and target in HC.
1018 */
1019 case FIX_ID_2_GC_NEAR_REL:
1020 {
1021 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1022 uint32_t offTrg = *u.pu32++;
1023 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1024 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1025 break;
1026 }
1027
1028 /*
1029 * 16:32 far jump, target in GC.
1030 */
1031 case FIX_GC_FAR32:
1032 {
1033 uint32_t offTrg = *u.pu32++;
1034 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1035 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1036 *uSrc.pu16++ = SelCS;
1037 break;
1038 }
1039
1040 /*
1041 * Make 32-bit GC pointer given CPUM offset.
1042 */
1043 case FIX_GC_CPUM_OFF:
1044 {
1045 uint32_t offCPUM = *u.pu32++;
1046 Assert(offCPUM < sizeof(pVM->cpum));
1047 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1048 break;
1049 }
1050
1051 /*
1052 * Make 32-bit GC pointer given VM offset.
1053 */
1054 case FIX_GC_VM_OFF:
1055 {
1056 uint32_t offVM = *u.pu32++;
1057 Assert(offVM < sizeof(VM));
1058 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1059 break;
1060 }
1061
1062 /*
1063 * Make 32-bit HC pointer given CPUM offset.
1064 */
1065 case FIX_HC_CPUM_OFF:
1066 {
1067 uint32_t offCPUM = *u.pu32++;
1068 Assert(offCPUM < sizeof(pVM->cpum));
1069 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1070 break;
1071 }
1072
1073 /*
1074 * Make 32-bit R0 pointer given VM offset.
1075 */
1076 case FIX_HC_VM_OFF:
1077 {
1078 uint32_t offVM = *u.pu32++;
1079 Assert(offVM < sizeof(VM));
1080 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1081 break;
1082 }
1083
1084 /*
1085 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1086 */
1087 case FIX_INTER_32BIT_CR3:
1088 {
1089
1090 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1091 break;
1092 }
1093
1094 /*
1095 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1096 */
1097 case FIX_INTER_PAE_CR3:
1098 {
1099
1100 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1101 break;
1102 }
1103
1104 /*
1105 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1106 */
1107 case FIX_INTER_AMD64_CR3:
1108 {
1109
1110 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1111 break;
1112 }
1113
1114 /*
1115 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1116 */
1117 case FIX_HYPER_32BIT_CR3:
1118 {
1119
1120 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1121 break;
1122 }
1123
1124 /*
1125 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1126 */
1127 case FIX_HYPER_PAE_CR3:
1128 {
1129
1130 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1131 break;
1132 }
1133
1134 /*
1135 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1136 */
1137 case FIX_HYPER_AMD64_CR3:
1138 {
1139
1140 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1141 break;
1142 }
1143
1144 /*
1145 * Store Hypervisor CS (16-bit).
1146 */
1147 case FIX_HYPER_CS:
1148 {
1149 *uSrc.pu16 = SelCS;
1150 break;
1151 }
1152
1153 /*
1154 * Store Hypervisor DS (16-bit).
1155 */
1156 case FIX_HYPER_DS:
1157 {
1158 *uSrc.pu16 = SelDS;
1159 break;
1160 }
1161
1162 /*
1163 * Store Hypervisor TSS (16-bit).
1164 */
1165 case FIX_HYPER_TSS:
1166 {
1167 *uSrc.pu16 = SelTSS;
1168 break;
1169 }
1170
1171 /*
1172 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1173 */
1174 case FIX_GC_TSS_GDTE_DW2:
1175 {
1176 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1177 *uSrc.pu32 = (uint32_t)GCPtr;
1178 break;
1179 }
1180
1181
1182 ///@todo case FIX_CR4_MASK:
1183 ///@todo case FIX_CR4_OSFSXR:
1184
1185 /*
1186 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1187 */
1188 case FIX_NO_FXSAVE_JMP:
1189 {
1190 uint32_t offTrg = *u.pu32++;
1191 Assert(offTrg < pSwitcher->cbCode);
1192 if (!CPUMSupportsFXSR(pVM))
1193 {
1194 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1195 *uSrc.pu32++ = offTrg - (offSrc + 5);
1196 }
1197 else
1198 {
1199 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1200 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1201 }
1202 break;
1203 }
1204
1205 /*
1206 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1207 */
1208 case FIX_NO_SYSENTER_JMP:
1209 {
1210 uint32_t offTrg = *u.pu32++;
1211 Assert(offTrg < pSwitcher->cbCode);
1212 if (!CPUMIsHostUsingSysEnter(pVM))
1213 {
1214 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1215 *uSrc.pu32++ = offTrg - (offSrc + 5);
1216 }
1217 else
1218 {
1219 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1220 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1221 }
1222 break;
1223 }
1224
1225 /*
1226 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1227 */
1228 case FIX_NO_SYSCALL_JMP:
1229 {
1230 uint32_t offTrg = *u.pu32++;
1231 Assert(offTrg < pSwitcher->cbCode);
1232 if (!CPUMIsHostUsingSysEnter(pVM))
1233 {
1234 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1235 *uSrc.pu32++ = offTrg - (offSrc + 5);
1236 }
1237 else
1238 {
1239 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1240 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1241 }
1242 break;
1243 }
1244
1245 /*
1246 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1247 */
1248 case FIX_HC_32BIT:
1249 {
1250 uint32_t offTrg = *u.pu32++;
1251 Assert(offSrc < pSwitcher->cbCode);
1252 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1253 *uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1254 break;
1255 }
1256
1257#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1258 /*
1259 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1260 */
1261 case FIX_HC_64BIT:
1262 {
1263 uint32_t offTrg = *u.pu32++;
1264 Assert(offSrc < pSwitcher->cbCode);
1265 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1266 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1267 break;
1268 }
1269
1270 /*
1271 * 64-bit HC Code Selector (no argument).
1272 */
1273 case FIX_HC_64BIT_CS:
1274 {
1275 Assert(offSrc < pSwitcher->cbCode);
1276#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1277 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1278#else
1279 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1280#endif
1281 break;
1282 }
1283
1284 /*
1285 * 64-bit HC pointer to the CPUM instance data (no argument).
1286 */
1287 case FIX_HC_64BIT_CPUM:
1288 {
1289 Assert(offSrc < pSwitcher->cbCode);
1290 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1291 break;
1292 }
1293#endif
1294
1295 /*
1296 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1297 */
1298 case FIX_ID_32BIT:
1299 {
1300 uint32_t offTrg = *u.pu32++;
1301 Assert(offSrc < pSwitcher->cbCode);
1302 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1303 *uSrc.pu32 = u32IDCode + offTrg;
1304 break;
1305 }
1306
1307 /*
1308 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1309 */
1310 case FIX_ID_64BIT:
1311 {
1312 uint32_t offTrg = *u.pu32++;
1313 Assert(offSrc < pSwitcher->cbCode);
1314 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1315 *uSrc.pu64 = u32IDCode + offTrg;
1316 break;
1317 }
1318
1319 /*
1320 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1321 */
1322 case FIX_ID_FAR32_TO_64BIT_MODE:
1323 {
1324 uint32_t offTrg = *u.pu32++;
1325 Assert(offSrc < pSwitcher->cbCode);
1326 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1327 *uSrc.pu32++ = u32IDCode + offTrg;
1328 *uSrc.pu16 = SelCS64;
1329 AssertRelease(SelCS64);
1330 break;
1331 }
1332
1333#ifdef VBOX_WITH_NMI
1334 /*
1335 * 32-bit address to the APIC base.
1336 */
1337 case FIX_GC_APIC_BASE_32BIT:
1338 {
1339 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1340 break;
1341 }
1342#endif
1343
1344 default:
1345 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1346 break;
1347 }
1348 }
1349
1350#ifdef LOG_ENABLED
1351 /*
1352 * If Log2 is enabled disassemble the switcher code.
1353 *
1354 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1355 */
1356 if (LogIs2Enabled())
1357 {
1358 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1359 " pu8CodeR0 = %p\n"
1360 " pu8CodeR3 = %p\n"
1361 " GCPtrCode = %VGv\n"
1362 " u32IDCode = %08x\n"
1363 " pVMGC = %VGv\n"
1364 " pCPUMGC = %VGv\n"
1365 " pVMHC = %p\n"
1366 " pCPUMHC = %p\n"
1367 " GCPtrGDT = %VGv\n"
1368 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1369 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1370 " SelCS = %04x\n"
1371 " SelDS = %04x\n"
1372 " SelCS64 = %04x\n"
1373 " SelTSS = %04x\n",
1374 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1375 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1376 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1377 GCPtrGDT,
1378 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1379 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1380 SelCS, SelDS, SelCS64, SelTSS);
1381
1382 uint32_t offCode = 0;
1383 while (offCode < pSwitcher->cbCode)
1384 {
1385 /*
1386 * Figure out where this is.
1387 */
1388 const char *pszDesc = NULL;
1389 RTUINTPTR uBase;
1390 uint32_t cbCode;
1391 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1392 {
1393 pszDesc = "HCCode0";
1394 uBase = (RTUINTPTR)pu8CodeR0;
1395 offCode = pSwitcher->offHCCode0;
1396 cbCode = pSwitcher->cbHCCode0;
1397 }
1398 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1399 {
1400 pszDesc = "HCCode1";
1401 uBase = (RTUINTPTR)pu8CodeR0;
1402 offCode = pSwitcher->offHCCode1;
1403 cbCode = pSwitcher->cbHCCode1;
1404 }
1405 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1406 {
1407 pszDesc = "GCCode";
1408 uBase = GCPtrCode;
1409 offCode = pSwitcher->offGCCode;
1410 cbCode = pSwitcher->cbGCCode;
1411 }
1412 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1413 {
1414 pszDesc = "IDCode0";
1415 uBase = u32IDCode;
1416 offCode = pSwitcher->offIDCode0;
1417 cbCode = pSwitcher->cbIDCode0;
1418 }
1419 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1420 {
1421 pszDesc = "IDCode1";
1422 uBase = u32IDCode;
1423 offCode = pSwitcher->offIDCode1;
1424 cbCode = pSwitcher->cbIDCode1;
1425 }
1426 else
1427 {
1428 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1429 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1430 offCode++;
1431 continue;
1432 }
1433
1434 /*
1435 * Disassemble it.
1436 */
1437 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1438 DISCPUSTATE Cpu = {0};
1439 Cpu.mode = CPUMODE_32BIT;
1440 while (cbCode > 0)
1441 {
1442 /* try label it */
1443 if (pSwitcher->offR0HostToGuest == offCode)
1444 RTLogPrintf(" *R0HostToGuest:\n");
1445 if (pSwitcher->offGCGuestToHost == offCode)
1446 RTLogPrintf(" *GCGuestToHost:\n");
1447 if (pSwitcher->offGCCallTrampoline == offCode)
1448 RTLogPrintf(" *GCCallTrampoline:\n");
1449 if (pSwitcher->offGCGuestToHostAsm == offCode)
1450 RTLogPrintf(" *GCGuestToHostAsm:\n");
1451 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1452 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1453 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1454 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1455
1456 /* disas */
1457 uint32_t cbInstr = 0;
1458 char szDisas[256];
1459 if (DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas))
1460 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1461 else
1462 {
1463 RTLogPrintf(" %04x: %02x '%c'\n",
1464 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1465 cbInstr = 1;
1466 }
1467 offCode += cbInstr;
1468 cbCode -= RT_MIN(cbInstr, cbCode);
1469 }
1470 }
1471 }
1472#endif
1473}
1474
1475
1476/**
1477 * Relocator for the 32-Bit to 32-Bit world switcher.
1478 */
1479DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1480{
1481 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1482 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1483}
1484
1485
1486/**
1487 * Relocator for the 32-Bit to PAE world switcher.
1488 */
1489DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1490{
1491 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1492 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1493}
1494
1495
1496/**
1497 * Relocator for the PAE to 32-Bit world switcher.
1498 */
1499DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1500{
1501 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1502 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1503}
1504
1505
1506/**
1507 * Relocator for the PAE to PAE world switcher.
1508 */
1509DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1510{
1511 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1512 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1513}
1514
1515
1516/**
1517 * Relocator for the AMD64 to PAE world switcher.
1518 */
1519DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1520{
1521 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1522 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1523}
1524
1525
1526/**
1527 * Gets the pointer to g_szRTAssertMsg1 in GC.
1528 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1529 * Returns NULL if not present.
1530 * @param pVM The VM handle.
1531 */
1532VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1533{
1534 RTGCPTR GCPtr;
1535 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1536 if (VBOX_SUCCESS(rc))
1537 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1538 return NULL;
1539}
1540
1541
1542/**
1543 * Gets the pointer to g_szRTAssertMsg2 in GC.
1544 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1545 * Returns NULL if not present.
1546 * @param pVM The VM handle.
1547 */
1548VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1549{
1550 RTGCPTR GCPtr;
1551 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1552 if (VBOX_SUCCESS(rc))
1553 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1554 return NULL;
1555}
1556
1557
1558/**
1559 * Execute state save operation.
1560 *
1561 * @returns VBox status code.
1562 * @param pVM VM Handle.
1563 * @param pSSM SSM operation handle.
1564 */
1565static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1566{
1567 LogFlow(("vmmR3Save:\n"));
1568
1569 /*
1570 * The hypervisor stack.
1571 */
1572 SSMR3PutGCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1573 RTGCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1574 Assert(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE);
1575 SSMR3PutGCPtr(pSSM, GCPtrESP);
1576 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1577 return SSMR3PutU32(pSSM, ~0); /* terminator */
1578}
1579
1580
1581/**
1582 * Execute state load operation.
1583 *
1584 * @returns VBox status code.
1585 * @param pVM VM Handle.
1586 * @param pSSM SSM operation handle.
1587 * @param u32Version Data layout version.
1588 */
1589static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1590{
1591 LogFlow(("vmmR3Load:\n"));
1592
1593 /*
1594 * Validate version.
1595 */
1596 if (u32Version != VMM_SAVED_STATE_VERSION)
1597 {
1598 Log(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1599 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1600 }
1601
1602 /*
1603 * Check that the stack is in the same place, or that it's fearly empty.
1604 */
1605 RTGCPTR GCPtrStackBottom;
1606 SSMR3GetGCPtr(pSSM, &GCPtrStackBottom);
1607 RTGCPTR GCPtrESP;
1608 int rc = SSMR3GetGCPtr(pSSM, &GCPtrESP);
1609 if (VBOX_FAILURE(rc))
1610 return rc;
1611 if ( GCPtrStackBottom == pVM->vmm.s.pbGCStackBottom
1612 || (GCPtrStackBottom - GCPtrESP < 32)) /** @todo This will break if we start preemting the hypervisor. */
1613 {
1614 /*
1615 * We *must* set the ESP because the CPUM load + PGM load relocations will render
1616 * the ESP in CPUM fatally invalid.
1617 */
1618 CPUMSetHyperESP(pVM, GCPtrESP);
1619
1620 /* restore the stack. */
1621 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1622
1623 /* terminator */
1624 uint32_t u32;
1625 rc = SSMR3GetU32(pSSM, &u32);
1626 if (VBOX_FAILURE(rc))
1627 return rc;
1628 if (u32 != ~0U)
1629 {
1630 AssertMsgFailed(("u32=%#x\n", u32));
1631 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1632 }
1633 return VINF_SUCCESS;
1634 }
1635
1636 LogRel(("The stack is not in the same place and it's not empty! GCPtrStackBottom=%VGv pbGCStackBottom=%VGv ESP=%VGv\n",
1637 GCPtrStackBottom, pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1638 AssertFailed();
1639 return VERR_SSM_LOAD_CONFIG_MISMATCH;
1640}
1641
1642
1643/**
1644 * Selects the switcher to be used for switching to GC.
1645 *
1646 * @returns VBox status code.
1647 * @param pVM VM handle.
1648 * @param enmSwitcher The new switcher.
1649 * @remark This function may be called before the VMM is initialized.
1650 */
1651VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1652{
1653 /*
1654 * Validate input.
1655 */
1656 if ( enmSwitcher < VMMSWITCHER_INVALID
1657 || enmSwitcher >= VMMSWITCHER_MAX)
1658 {
1659 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1660 return VERR_INVALID_PARAMETER;
1661 }
1662
1663 /*
1664 * Select the new switcher.
1665 */
1666 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1667 if (pSwitcher)
1668 {
1669 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1670 pVM->vmm.s.enmSwitcher = enmSwitcher;
1671
1672 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1673 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1674
1675 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1676 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1677 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1678 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1679 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1680 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1681 return VINF_SUCCESS;
1682 }
1683 return VERR_NOT_IMPLEMENTED;
1684}
1685
1686/**
1687 * Disable the switcher logic permanently.
1688 *
1689 * @returns VBox status code.
1690 * @param pVM VM handle.
1691 */
1692VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1693{
1694/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1695 * @code
1696 * mov eax, VERR_INTERNAL_ERROR
1697 * ret
1698 * @endcode
1699 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1700 */
1701 pVM->vmm.s.fSwitcherDisabled = true;
1702 return VINF_SUCCESS;
1703}
1704
1705
1706/**
1707 * Resolve a builtin GC symbol.
1708 * Called by PDM when loading or relocating GC modules.
1709 *
1710 * @returns VBox status
1711 * @param pVM VM Handle.
1712 * @param pszSymbol Symbol to resolv
1713 * @param pGCPtrValue Where to store the symbol value.
1714 * @remark This has to work before VMMR3Relocate() is called.
1715 */
1716VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1717{
1718 if (!strcmp(pszSymbol, "g_Logger"))
1719 {
1720 if (pVM->vmm.s.pLoggerHC)
1721 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1722 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1723 }
1724 else if (!strcmp(pszSymbol, "g_RelLogger"))
1725 {
1726#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1727 if (pVM->vmm.s.pRelLoggerHC)
1728 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1729 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1730#else
1731 *pGCPtrValue = NIL_RTGCPTR;
1732#endif
1733 }
1734 else
1735 return VERR_SYMBOL_NOT_FOUND;
1736 return VINF_SUCCESS;
1737}
1738
1739
1740/**
1741 * Suspends the the CPU yielder.
1742 *
1743 * @param pVM The VM handle.
1744 */
1745VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1746{
1747 if (!pVM->vmm.s.cYieldResumeMillies)
1748 {
1749 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1750 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1751 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1752 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1753 else
1754 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1755 TMTimerStop(pVM->vmm.s.pYieldTimer);
1756 }
1757 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1758}
1759
1760
1761/**
1762 * Stops the the CPU yielder.
1763 *
1764 * @param pVM The VM handle.
1765 */
1766VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1767{
1768 if (!pVM->vmm.s.cYieldResumeMillies)
1769 TMTimerStop(pVM->vmm.s.pYieldTimer);
1770 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1771 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1772}
1773
1774
1775/**
1776 * Resumes the CPU yielder when it has been a suspended or stopped.
1777 *
1778 * @param pVM The VM handle.
1779 */
1780VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1781{
1782 if (pVM->vmm.s.cYieldResumeMillies)
1783 {
1784 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1785 pVM->vmm.s.cYieldResumeMillies = 0;
1786 }
1787}
1788
1789
1790/**
1791 * Internal timer callback function.
1792 *
1793 * @param pVM The VM.
1794 * @param pTimer The timer handle.
1795 * @param pvUser User argument specified upon timer creation.
1796 */
1797static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1798{
1799 /*
1800 * This really needs some careful tuning. While we shouldn't be too gready since
1801 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1802 * because that'll cause us to stop up.
1803 *
1804 * The current logic is to use the default interval when there is no lag worth
1805 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1806 *
1807 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1808 * so the lag is up to date.)
1809 */
1810 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1811 if ( u64Lag < 50000000 /* 50ms */
1812 || ( u64Lag < 1000000000 /* 1s */
1813 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1814 )
1815 {
1816 uint64_t u64Elapsed = RTTimeNanoTS();
1817 pVM->vmm.s.u64LastYield = u64Elapsed;
1818
1819 RTThreadYield();
1820
1821#ifdef LOG_ENABLED
1822 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1823 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1824#endif
1825 }
1826 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1827}
1828
1829
1830/**
1831 * Acquire global VM lock.
1832 *
1833 * @returns VBox status code
1834 * @param pVM The VM to operate on.
1835 */
1836VMMR3DECL(int) VMMR3Lock(PVM pVM)
1837{
1838 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1839}
1840
1841
1842/**
1843 * Release global VM lock.
1844 *
1845 * @returns VBox status code
1846 * @param pVM The VM to operate on.
1847 */
1848VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1849{
1850 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1851}
1852
1853
1854/**
1855 * Return global VM lock owner.
1856 *
1857 * @returns Thread id of owner.
1858 * @returns NIL_RTTHREAD if no owner.
1859 * @param pVM The VM to operate on.
1860 */
1861VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1862{
1863 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1864}
1865
1866
1867/**
1868 * Checks if the current thread is the owner of the global VM lock.
1869 *
1870 * @returns true if owner.
1871 * @returns false if not owner.
1872 * @param pVM The VM to operate on.
1873 */
1874VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1875{
1876 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1877}
1878
1879
1880/**
1881 * Executes guest code.
1882 *
1883 * @param pVM VM handle.
1884 */
1885VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1886{
1887 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1888
1889 /*
1890 * Set the EIP and ESP.
1891 */
1892 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1893 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1894 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1895 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1896
1897 /*
1898 * We hide log flushes (outer) and hypervisor interrupts (inner).
1899 */
1900 for (;;)
1901 {
1902 int rc;
1903 do
1904 {
1905#ifdef NO_SUPCALLR0VMM
1906 rc = VERR_GENERAL_FAILURE;
1907#else
1908 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
1909#endif
1910 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1911
1912 /*
1913 * Flush the logs.
1914 */
1915#ifdef LOG_ENABLED
1916 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1917 if ( pLogger
1918 && pLogger->offScratch > 0)
1919 RTLogFlushGC(NULL, pLogger);
1920#endif
1921#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1922 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1923 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1924 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1925#endif
1926 if (rc != VINF_VMM_CALL_HOST)
1927 {
1928 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1929 return rc;
1930 }
1931 rc = vmmR3ServiceCallHostRequest(pVM);
1932 if (VBOX_FAILURE(rc))
1933 return rc;
1934 /* Resume GC */
1935 }
1936}
1937
1938
1939/**
1940 * Executes guest code (Intel VMX and AMD SVM).
1941 *
1942 * @param pVM VM handle.
1943 */
1944VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1945{
1946 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1947
1948 for (;;)
1949 {
1950 int rc;
1951 do
1952 {
1953#ifdef NO_SUPCALLR0VMM
1954 rc = VERR_GENERAL_FAILURE;
1955#else
1956 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_RUN, NULL);
1957#endif
1958 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1959
1960#ifdef LOG_ENABLED
1961 /*
1962 * Flush the log
1963 */
1964 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
1965 if ( pR0Logger
1966 && pR0Logger->Logger.offScratch > 0)
1967 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
1968#endif /* !LOG_ENABLED */
1969 if (rc != VINF_VMM_CALL_HOST)
1970 {
1971 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1972 return rc;
1973 }
1974 rc = vmmR3ServiceCallHostRequest(pVM);
1975 if (VBOX_FAILURE(rc))
1976 return rc;
1977 /* Resume R0 */
1978 }
1979}
1980
1981/**
1982 * Calls GC a function.
1983 *
1984 * @param pVM The VM handle.
1985 * @param GCPtrEntry The GC function address.
1986 * @param cArgs The number of arguments in the ....
1987 * @param ... Arguments to the function.
1988 */
1989VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, ...)
1990{
1991 va_list args;
1992 va_start(args, cArgs);
1993 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
1994 va_end(args);
1995 return rc;
1996}
1997
1998
1999/**
2000 * Calls GC a function.
2001 *
2002 * @param pVM The VM handle.
2003 * @param GCPtrEntry The GC function address.
2004 * @param cArgs The number of arguments in the ....
2005 * @param args Arguments to the function.
2006 */
2007VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, va_list args)
2008{
2009 Log2(("VMMR3CallGCV: GCPtrEntry=%VGv cArgs=%d\n", GCPtrEntry, cArgs));
2010
2011 /*
2012 * Setup the call frame using the trampoline.
2013 */
2014 CPUMHyperSetCtxCore(pVM, NULL);
2015 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2016 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR));
2017 PRTGCUINTPTR pFrame = (PRTGCUINTPTR)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2018 int i = cArgs;
2019 while (i-- > 0)
2020 *pFrame++ = va_arg(args, RTGCUINTPTR);
2021
2022 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR)); /* stack frame size */
2023 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2024 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2025
2026 /*
2027 * We hide log flushes (outer) and hypervisor interrupts (inner).
2028 */
2029 for (;;)
2030 {
2031 int rc;
2032 do
2033 {
2034#ifdef NO_SUPCALLR0VMM
2035 rc = VERR_GENERAL_FAILURE;
2036#else
2037 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2038#endif
2039 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2040
2041 /*
2042 * Flush the logs.
2043 */
2044#ifdef LOG_ENABLED
2045 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2046 if ( pLogger
2047 && pLogger->offScratch > 0)
2048 RTLogFlushGC(NULL, pLogger);
2049#endif
2050#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2051 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2052 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2053 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2054#endif
2055 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2056 VMMR3FatalDump(pVM, rc);
2057 if (rc != VINF_VMM_CALL_HOST)
2058 {
2059 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2060 return rc;
2061 }
2062 rc = vmmR3ServiceCallHostRequest(pVM);
2063 if (VBOX_FAILURE(rc))
2064 return rc;
2065 }
2066}
2067
2068
2069/**
2070 * Resumes executing hypervisor code when interrupted
2071 * by a queue flush or a debug event.
2072 *
2073 * @returns VBox status code.
2074 * @param pVM VM handle.
2075 */
2076VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2077{
2078 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2079
2080 /*
2081 * We hide log flushes (outer) and hypervisor interrupts (inner).
2082 */
2083 for (;;)
2084 {
2085 int rc;
2086 do
2087 {
2088#ifdef NO_SUPCALLR0VMM
2089 rc = VERR_GENERAL_FAILURE;
2090#else
2091 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2092#endif
2093 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2094
2095 /*
2096 * Flush the loggers,
2097 */
2098#ifdef LOG_ENABLED
2099 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2100 if ( pLogger
2101 && pLogger->offScratch > 0)
2102 RTLogFlushGC(NULL, pLogger);
2103#endif
2104#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2105 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2106 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2107 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2108#endif
2109 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2110 VMMR3FatalDump(pVM, rc);
2111 if (rc != VINF_VMM_CALL_HOST)
2112 {
2113 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2114 return rc;
2115 }
2116 rc = vmmR3ServiceCallHostRequest(pVM);
2117 if (VBOX_FAILURE(rc))
2118 return rc;
2119 }
2120}
2121
2122
2123/**
2124 * Service a call to the ring-3 host code.
2125 *
2126 * @returns VBox status code.
2127 * @param pVM VM handle.
2128 * @remark Careful with critsects.
2129 */
2130static int vmmR3ServiceCallHostRequest(PVM pVM)
2131{
2132 switch (pVM->vmm.s.enmCallHostOperation)
2133 {
2134 /*
2135 * Acquire the PDM lock.
2136 */
2137 case VMMCALLHOST_PDM_LOCK:
2138 {
2139 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2140 break;
2141 }
2142
2143 /*
2144 * Flush a PDM queue.
2145 */
2146 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2147 {
2148 PDMR3QueueFlushWorker(pVM, NULL);
2149 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2150 break;
2151 }
2152
2153 /*
2154 * Grow the PGM pool.
2155 */
2156 case VMMCALLHOST_PGM_POOL_GROW:
2157 {
2158 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2159 break;
2160 }
2161
2162 /*
2163 * Acquire the PGM lock.
2164 */
2165 case VMMCALLHOST_PGM_LOCK:
2166 {
2167 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2168 break;
2169 }
2170
2171 /*
2172 * Flush REM handler notifications.
2173 */
2174 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2175 {
2176 REMR3ReplayHandlerNotifications(pVM);
2177 break;
2178 }
2179
2180 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2181 {
2182 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, pVM->vmm.s.u64CallHostArg);
2183 break;
2184 }
2185
2186 /*
2187 * This is a noop. We just take this route to avoid unnecessary
2188 * tests in the loops.
2189 */
2190 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2191 break;
2192
2193 /*
2194 * Set the VM error message.
2195 */
2196 case VMMCALLHOST_VM_SET_ERROR:
2197 VMR3SetErrorWorker(pVM);
2198 break;
2199
2200 /*
2201 * Set the VM runtime error message.
2202 */
2203 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2204 VMR3SetRuntimeErrorWorker(pVM);
2205 break;
2206
2207 default:
2208 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2209 return VERR_INTERNAL_ERROR;
2210 }
2211
2212 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2213 return VINF_SUCCESS;
2214}
2215
2216
2217
2218/**
2219 * Structure to pass to DBGFR3Info() and for doing all other
2220 * output during fatal dump.
2221 */
2222typedef struct VMMR3FATALDUMPINFOHLP
2223{
2224 /** The helper core. */
2225 DBGFINFOHLP Core;
2226 /** The release logger instance. */
2227 PRTLOGGER pRelLogger;
2228 /** The saved release logger flags. */
2229 RTUINT fRelLoggerFlags;
2230 /** The logger instance. */
2231 PRTLOGGER pLogger;
2232 /** The saved logger flags. */
2233 RTUINT fLoggerFlags;
2234 /** The saved logger destination flags. */
2235 RTUINT fLoggerDestFlags;
2236 /** Whether to output to stderr or not. */
2237 bool fStdErr;
2238} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2239typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2240
2241
2242/**
2243 * Print formatted string.
2244 *
2245 * @param pHlp Pointer to this structure.
2246 * @param pszFormat The format string.
2247 * @param ... Arguments.
2248 */
2249static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2250{
2251 va_list args;
2252 va_start(args, pszFormat);
2253 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2254 va_end(args);
2255}
2256
2257
2258/**
2259 * Print formatted string.
2260 *
2261 * @param pHlp Pointer to this structure.
2262 * @param pszFormat The format string.
2263 * @param args Argument list.
2264 */
2265static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2266{
2267 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2268
2269 if (pMyHlp->pRelLogger)
2270 {
2271 va_list args2;
2272 va_copy(args2, args);
2273 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2274 va_end(args2);
2275 }
2276 if (pMyHlp->pLogger)
2277 {
2278 va_list args2;
2279 va_copy(args2, args);
2280 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2281 va_end(args2);
2282 }
2283 if (pMyHlp->fStdErr)
2284 {
2285 va_list args2;
2286 va_copy(args2, args);
2287 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2288 va_end(args2);
2289 }
2290}
2291
2292
2293/**
2294 * Initializes the fatal dump output helper.
2295 *
2296 * @param pHlp The structure to initialize.
2297 */
2298static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2299{
2300 memset(pHlp, 0, sizeof(*pHlp));
2301
2302 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2303 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2304
2305 /*
2306 * The loggers.
2307 */
2308 pHlp->pRelLogger = RTLogRelDefaultInstance();
2309#ifndef LOG_ENABLED
2310 if (!pHlp->pRelLogger)
2311#endif
2312 pHlp->pLogger = RTLogDefaultInstance();
2313
2314 if (pHlp->pRelLogger)
2315 {
2316 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2317 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2318 }
2319
2320 if (pHlp->pLogger)
2321 {
2322 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2323 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2324 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2325#ifndef DEBUG_sandervl
2326 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2327#endif
2328 }
2329
2330 /*
2331 * Check if we need write to stderr.
2332 */
2333 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2334 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2335}
2336
2337
2338/**
2339 * Deletes the fatal dump output helper.
2340 *
2341 * @param pHlp The structure to delete.
2342 */
2343static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2344{
2345 if (pHlp->pRelLogger)
2346 {
2347 RTLogFlush(pHlp->pRelLogger);
2348 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2349 }
2350
2351 if (pHlp->pLogger)
2352 {
2353 RTLogFlush(pHlp->pLogger);
2354 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2355 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2356 }
2357}
2358
2359
2360/**
2361 * Dumps the VM state on a fatal error.
2362 *
2363 * @param pVM VM Handle.
2364 * @param rcErr VBox status code.
2365 */
2366VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2367{
2368 /*
2369 * Create our output helper and sync it with the log settings.
2370 * This helper will be used for all the output.
2371 */
2372 VMMR3FATALDUMPINFOHLP Hlp;
2373 PCDBGFINFOHLP pHlp = &Hlp.Core;
2374 vmmR3FatalDumpInfoHlpInit(&Hlp);
2375
2376 /*
2377 * Header.
2378 */
2379 pHlp->pfnPrintf(pHlp,
2380 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2381 "!!\n"
2382 "!! Guru Meditation %d (%Vrc)\n"
2383 "!!\n",
2384 rcErr, rcErr);
2385
2386 /*
2387 * Continue according to context.
2388 */
2389 bool fDoneHyper = false;
2390 switch (rcErr)
2391 {
2392 /*
2393 * Hyper visor errors.
2394 */
2395 case VINF_EM_DBG_HYPER_ASSERTION:
2396 pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2397 /* fall thru */
2398 case VERR_TRPM_DONT_PANIC:
2399 case VERR_TRPM_PANIC:
2400 case VINF_EM_RAW_STALE_SELECTOR:
2401 case VINF_EM_RAW_IRET_TRAP:
2402 case VINF_EM_DBG_HYPER_BREAKPOINT:
2403 case VINF_EM_DBG_HYPER_STEPPED:
2404 {
2405 /* Trap? */
2406 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2407 TRPMEVENT enmType;
2408 uint8_t u8TrapNo = 0xce;
2409 RTGCUINT uErrorCode = 0xdeadface;
2410 RTGCUINTPTR uCR2 = 0xdeadface;
2411 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2412 if (VBOX_SUCCESS(rc2))
2413 pHlp->pfnPrintf(pHlp,
2414 "!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv Type=%d\n",
2415 u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2416 else
2417 pHlp->pfnPrintf(pHlp,
2418 "!! EIP=%VGv NOTRAP\n",
2419 uEIP);
2420
2421 /*
2422 * Try figure out where eip is.
2423 */
2424 /** @todo make query call for core code or move this function to VMM. */
2425 /* core code? */
2426 //if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2427 // pHlp->pfnPrintf(pHlp,
2428 // "!! EIP is in CoreCode, offset %#x\n",
2429 // uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2430 //else
2431 { /* ask PDM */
2432 /** @todo ask DBGFR3Sym later. */
2433 char szModName[64];
2434 RTGCPTR GCPtrMod;
2435 char szNearSym1[260];
2436 RTGCPTR GCPtrNearSym1;
2437 char szNearSym2[260];
2438 RTGCPTR GCPtrNearSym2;
2439 int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2440 &szModName[0], sizeof(szModName), &GCPtrMod,
2441 &szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2442 &szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2443 if (VBOX_SUCCESS(rc))
2444 {
2445 pHlp->pfnPrintf(pHlp,
2446 "!! EIP in %s (%p) at rva %x near symbols:\n"
2447 "!! %VGv rva %VGv off %08x %s\n"
2448 "!! %VGv rva %VGv off -%08x %s\n",
2449 szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2450 GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2451 GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2452 }
2453 else
2454 pHlp->pfnPrintf(pHlp,
2455 "!! EIP is not in any code known to VMM!\n");
2456 }
2457
2458 /* Disassemble the instruction. */
2459 char szInstr[256];
2460 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2461 if (VBOX_SUCCESS(rc2))
2462 pHlp->pfnPrintf(pHlp,
2463 "!! %s\n", szInstr);
2464
2465 /* Dump the hypervisor cpu state. */
2466 pHlp->pfnPrintf(pHlp,
2467 "!!\n"
2468 "!!\n"
2469 "!!\n");
2470 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2471 fDoneHyper = true;
2472
2473 /* Callstack. */
2474 DBGFSTACKFRAME Frame = {0};
2475 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2476 if (VBOX_SUCCESS(rc2))
2477 {
2478 pHlp->pfnPrintf(pHlp,
2479 "!!\n"
2480 "!! Call Stack:\n"
2481 "!!\n"
2482 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2483 do
2484 {
2485 pHlp->pfnPrintf(pHlp,
2486 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2487 (uint32_t)Frame.AddrFrame.off,
2488 (uint32_t)Frame.AddrReturnFrame.off,
2489 (uint32_t)Frame.AddrReturnPC.Sel,
2490 (uint32_t)Frame.AddrReturnPC.off,
2491 Frame.Args.au32[0],
2492 Frame.Args.au32[1],
2493 Frame.Args.au32[2],
2494 Frame.Args.au32[3]);
2495 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2496 if (Frame.pSymPC)
2497 {
2498 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2499 if (offDisp > 0)
2500 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2501 else if (offDisp < 0)
2502 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2503 else
2504 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2505 }
2506 if (Frame.pLinePC)
2507 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2508 pHlp->pfnPrintf(pHlp, "\n");
2509
2510 /* next */
2511 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2512 } while (VBOX_SUCCESS(rc2));
2513 DBGFR3StackWalkEnd(pVM, &Frame);
2514 }
2515
2516 /* raw stack */
2517 pHlp->pfnPrintf(pHlp,
2518 "!!\n"
2519 "!! Raw stack (mind the direction).\n"
2520 "!!\n"
2521 "%.*Vhxd\n",
2522 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2523 break;
2524 }
2525
2526 default:
2527 {
2528 break;
2529 }
2530
2531 } /* switch (rcErr) */
2532
2533
2534 /*
2535 * Dump useful state information.
2536 */
2537 /** @todo convert these dumpers to DBGFR3Info() handlers!!! */
2538 pHlp->pfnPrintf(pHlp,
2539 "!!\n"
2540 "!! PGM Access Handlers & Stuff:\n"
2541 "!!\n");
2542 PGMR3DumpMappings(pVM);
2543
2544
2545 /*
2546 * Generic info dumper loop.
2547 */
2548 static struct
2549 {
2550 const char *pszInfo;
2551 const char *pszArgs;
2552 } const aInfo[] =
2553 {
2554 { "hma", NULL },
2555 { "cpumguest", "verbose" },
2556 { "cpumhyper", "verbose" },
2557 { "cpumhost", "verbose" },
2558 { "mode", "all" },
2559 { "cpuid", "verbose" },
2560 { "gdt", NULL },
2561 { "ldt", NULL },
2562 //{ "tss", NULL },
2563 { "ioport", NULL },
2564 { "mmio", NULL },
2565 { "phys", NULL },
2566 //{ "pgmpd", NULL }, - doesn't always work at init time...
2567 { "timers", NULL },
2568 { "activetimers", NULL },
2569 { "handlers", "phys virt stats" },
2570 { "cfgm", NULL },
2571 };
2572 for (unsigned i = 0; i < ELEMENTS(aInfo); i++)
2573 {
2574 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2575 continue;
2576 pHlp->pfnPrintf(pHlp,
2577 "!!\n"
2578 "!! {%s, %s}\n"
2579 "!!\n",
2580 aInfo[i].pszInfo, aInfo[i].pszArgs);
2581 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2582 }
2583
2584 /* done */
2585 pHlp->pfnPrintf(pHlp,
2586 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2587
2588
2589 /*
2590 * Delete the output instance (flushing and restoring of flags).
2591 */
2592 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2593}
2594
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette