VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 12932

Last change on this file since 12932 was 12837, checked in by vboxsync, 16 years ago

VMM: more VT-x/AMD-V guru meditation fixes.
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1/* $Id: VMM.cpp 12837 2008-09-30 15:34:05Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/** @page pg_vmm VMM - The Virtual Machine Monitor
25 *
26 * !Revise this! It's already incorrect!
27 *
28 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
29 * manages the alternate reality; controlling the virtualization, managing
30 * resources, tracking CPU state, it's resources and so on...
31 *
32 * We will split the VMM into smaller entities:
33 *
34 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
35 * provide ring and world switching, that including routing
36 * interrupts to the host OS and traps to the appropriate trap
37 * handlers. It will implement an external interface for
38 * managing trap handlers.
39 *
40 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
41 * reality) and implementing external interfaces to read and change
42 * the state.
43 *
44 * - Memory Monitor (MM), which purpose it is to virtualize physical
45 * pages, segment descriptor tables, interrupt descriptor tables, task
46 * segments, and keep track of all memory providing external interfaces
47 * to access content and map pages. (Internally splitt into smaller entities!)
48 *
49 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
50 * interacts with the MM to implement memory mapped I/O. External
51 * interfaces for adding and removing I/O ranges are implemented.
52 *
53 * - External Interrupt Monitor (EIM), which purpose it is to manage
54 * interrupts generated by virtual devices. This monitor provides
55 * an interfaces for raising interrupts which is accessible at any
56 * time and from all thread.
57 * <p>
58 * A subentity of the EIM is the vitual Programmable Interrupt
59 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
60 * Programmable Interrupt Controller Device (VAPICD).
61 *
62 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
63 * virtual device using the DMA controller. Interfaces must be as the
64 * EIM interfaces independent and threadable.
65 * <p>
66 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
67 *
68 *
69 * Entities working on a higher level:
70 *
71 * - Device Manager (DM), which is a support facility for virtualized
72 * hardware. This provides generic facilities for efficient device
73 * virtualization. It will manage device attaching and detaching
74 * conversing with EIM and IOM.
75 *
76 * - Debugger Facility (DBGF) provides the basic features for
77 * debugging the alternate reality execution.
78 *
79 *
80 *
81 * @section pg_vmm_s_use_cases Use Cases
82 *
83 * @subsection pg_vmm_s_use_case_boot Bootstrap
84 *
85 * - Basic Init:
86 * - Init SUPDRV.
87 *
88 * - Init Virtual Machine Instance:
89 * - Load settings.
90 * - Check resource requirements (memory, com, stuff).
91 *
92 * - Init Host Ring 3 part:
93 * - Init Core code.
94 * - Load Pluggable Components.
95 * - Init Pluggable Components.
96 *
97 * - Init Host Ring 0 part:
98 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
99 * - Init Core code.
100 * - Load Pluggable Component code.
101 * - Init Pluggable Component code.
102 *
103 * - Allocate first chunk of memory and pin it down. This block of memory
104 * will fit the following pieces:
105 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
106 * (This is available from everywhere (at different addresses though)).
107 * - VMM Guest Context code.
108 * - Pluggable devices Guest Context code.
109 * - Page tables (directory and everything) for the VMM Guest
110 *
111 * - Setup Guest (Ring 0) part:
112 * - Setup initial page tables (i.e. directory all the stuff).
113 * - Load Core Guest Context code.
114 * - Load Pluggable Devices Guest Context code.
115 *
116 *
117 */
118
119
120/*******************************************************************************
121* Header Files *
122*******************************************************************************/
123#define LOG_GROUP LOG_GROUP_VMM
124#include <VBox/vmm.h>
125#include <VBox/vmapi.h>
126#include <VBox/pgm.h>
127#include <VBox/cfgm.h>
128#include <VBox/pdmqueue.h>
129#include <VBox/pdmapi.h>
130#include <VBox/cpum.h>
131#include <VBox/mm.h>
132#include <VBox/iom.h>
133#include <VBox/trpm.h>
134#include <VBox/selm.h>
135#include <VBox/em.h>
136#include <VBox/sup.h>
137#include <VBox/dbgf.h>
138#include <VBox/csam.h>
139#include <VBox/patm.h>
140#include <VBox/rem.h>
141#include <VBox/ssm.h>
142#include <VBox/tm.h>
143#include "VMMInternal.h"
144#include "VMMSwitcher/VMMSwitcher.h"
145#include <VBox/vm.h>
146#include <VBox/err.h>
147#include <VBox/param.h>
148#include <VBox/version.h>
149#include <VBox/x86.h>
150#include <VBox/hwaccm.h>
151#include <iprt/assert.h>
152#include <iprt/alloc.h>
153#include <iprt/asm.h>
154#include <iprt/time.h>
155#include <iprt/stream.h>
156#include <iprt/string.h>
157#include <iprt/stdarg.h>
158#include <iprt/ctype.h>
159
160
161
162/** The saved state version. */
163#define VMM_SAVED_STATE_VERSION 3
164
165
166/*******************************************************************************
167* Internal Functions *
168*******************************************************************************/
169static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
170static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
171static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
172static int vmmR3ServiceCallHostRequest(PVM pVM);
173static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
174
175
176/*******************************************************************************
177* Global Variables *
178*******************************************************************************/
179/** Array of switcher defininitions.
180 * The type and index shall match!
181 */
182static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
183{
184 NULL, /* invalid entry */
185#ifndef RT_ARCH_AMD64
186 &vmmR3Switcher32BitTo32Bit_Def,
187 &vmmR3Switcher32BitToPAE_Def,
188 NULL, //&vmmR3Switcher32BitToAMD64_Def,
189 &vmmR3SwitcherPAETo32Bit_Def,
190 &vmmR3SwitcherPAEToPAE_Def,
191 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
192# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
193 &vmmR3SwitcherAMD64ToPAE_Def,
194# else
195 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
196# endif
197 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
198#else
199 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
200 NULL, //&vmmR3Switcher32BitToPAE_Def,
201 NULL, //&vmmR3Switcher32BitToAMD64_Def,
202 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
203 NULL, //&vmmR3SwitcherPAEToPAE_Def,
204 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
205 &vmmR3SwitcherAMD64ToPAE_Def,
206 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
207#endif
208};
209
210
211
212/**
213 * Initiates the core code.
214 *
215 * This is core per VM code which might need fixups and/or for ease of use
216 * are put on linear contiguous backing.
217 *
218 * @returns VBox status code.
219 * @param pVM Pointer to VM structure.
220 */
221static int vmmR3InitCoreCode(PVM pVM)
222{
223 /*
224 * Calc the size.
225 */
226 unsigned cbCoreCode = 0;
227 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
228 {
229 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
230 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
231 if (pSwitcher)
232 {
233 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
234 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
235 }
236 }
237
238 /*
239 * Allocate continguous pages for switchers and deal with
240 * conflicts in the intermediate mapping of the code.
241 */
242 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
243 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
244 int rc = VERR_NO_MEMORY;
245 if (pVM->vmm.s.pvHCCoreCodeR3)
246 {
247 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
248 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
249 {
250 /* try more allocations - Solaris */
251 const unsigned cTries = 4112;
252 struct VMMInitBadTry
253 {
254 RTR0PTR pvR0;
255 void *pvR3;
256 RTHCPHYS HCPhys;
257 RTUINT cb;
258 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
259 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
260 unsigned i = 0;
261 do
262 {
263 paBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
264 paBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
265 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
266 i++;
267 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
268 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
269 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
270 if (!pVM->vmm.s.pvHCCoreCodeR3)
271 break;
272 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
273 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
274 && i < cTries - 1);
275
276 /* cleanup */
277 if (VBOX_FAILURE(rc))
278 {
279 paBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
280 paBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
281 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
282 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
283 i++;
284 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
285 }
286 while (i-- > 0)
287 {
288 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
289 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
290 SUPContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
291 }
292 RTMemTmpFree(paBadTries);
293 }
294 }
295 if (VBOX_SUCCESS(rc))
296 {
297 /*
298 * copy the code.
299 */
300 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
301 {
302 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
303 if (pSwitcher)
304 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
305 pSwitcher->pvCode, pSwitcher->cbCode);
306 }
307
308 /*
309 * Map the code into the GC address space.
310 */
311 RTGCPTR GCPtr;
312 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &GCPtr);
313 if (VBOX_SUCCESS(rc))
314 {
315 pVM->vmm.s.pvGCCoreCode = GCPtr;
316 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
317 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VRv Phys=%VHp cb=%#x\n",
318 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
319
320 /*
321 * Finally, PGM probably have selected a switcher already but we need
322 * to do get the addresses so we'll reselect it.
323 * This may legally fail so, we're ignoring the rc.
324 */
325 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
326 return rc;
327 }
328
329 /* shit */
330 AssertMsgFailed(("PGMR3Map(,%VRv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
331 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
332 }
333 else
334 VMSetError(pVM, rc, RT_SRC_POS,
335 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
336 cbCoreCode);
337
338 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
339 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
340 pVM->vmm.s.pvGCCoreCode = 0;
341 return rc;
342}
343
344
345/**
346 * Initializes the VMM.
347 *
348 * @returns VBox status code.
349 * @param pVM The VM to operate on.
350 */
351VMMR3DECL(int) VMMR3Init(PVM pVM)
352{
353 LogFlow(("VMMR3Init\n"));
354
355 /*
356 * Assert alignment, sizes and order.
357 */
358 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
359 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
360 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
361 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
362
363 /*
364 * Init basic VM VMM members.
365 */
366 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
367 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
368 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
369 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
370 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
371 else
372 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
373
374 /* GC switchers are enabled by default. Turned off by HWACCM. */
375 pVM->vmm.s.fSwitcherDisabled = false;
376
377 /* Get the CPU count.*/
378 rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "NumCPUs", &pVM->cCPUs, 1);
379 AssertLogRelMsgRCReturn(rc, ("Configuration error: Querying \"NumCPUs\" as integer failed, rc=%Vrc\n", rc), rc);
380#ifdef VBOX_WITH_SMP_GUESTS
381 AssertLogRelMsgReturn(pVM->cCPUs > 0 && pVM->cCPUs <= 256,
382 ("Configuration error: \"NumCPUs\"=%RU32 is out of range [1..256]\n", pVM->cCPUs), VERR_INVALID_PARAMETER);
383#else
384 AssertLogRelMsgReturn(pVM->cCPUs != 0,
385 ("Configuration error: \"NumCPUs\"=%RU32, expected 1\n", pVM->cCPUs), VERR_INVALID_PARAMETER);
386#endif
387
388#ifdef VBOX_WITH_SMP_GUESTS
389 LogRel(("[SMP] VMM with %RU32 CPUs\n", pVM->cCPUs));
390#endif
391
392 /*
393 * Register the saved state data unit.
394 */
395 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
396 NULL, vmmR3Save, NULL,
397 NULL, vmmR3Load, NULL);
398 if (VBOX_FAILURE(rc))
399 return rc;
400
401 /*
402 * Register the Ring-0 VM handle with the session for fast ioctl calls.
403 */
404 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
405 if (VBOX_FAILURE(rc))
406 return rc;
407
408 /*
409 * Init core code.
410 */
411 rc = vmmR3InitCoreCode(pVM);
412 if (VBOX_SUCCESS(rc))
413 {
414 /*
415 * Allocate & init VMM GC stack.
416 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
417 * (The page protection is modifed during R3 init completion.)
418 */
419#ifdef VBOX_STRICT_VMM_STACK
420 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
421#else
422 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
423#endif
424 if (VBOX_SUCCESS(rc))
425 {
426 /* Set HC and GC stack pointers to top of stack. */
427 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
428 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
429 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
430 AssertRelease(pVM->vmm.s.pbGCStack);
431
432 /* Set hypervisor eip. */
433 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
434
435 /*
436 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
437 */
438#ifdef LOG_ENABLED
439 PRTLOGGER pLogger = RTLogDefaultInstance();
440 if (pLogger)
441 {
442 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERRC, afGroups[pLogger->cGroups]);
443 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
444 if (VBOX_SUCCESS(rc))
445 {
446 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
447
448/*
449 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
450 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
451 *
452 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
453 * to not stub all the log functions.
454 *
455 * You might also wish to enable the AssertMsg1/2 overrides in VMMR0.cpp when enabling this.
456 */
457# if defined(DEBUG_sandervl) || defined(DEBUG_frank)
458 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
459 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
460 if (VBOX_SUCCESS(rc))
461 {
462 pVM->vmm.s.pR0Logger->pVM = pVM->pVMR0;
463 //pVM->vmm.s.pR0Logger->fCreated = false;
464 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
465 }
466# endif
467 }
468 }
469#endif /* LOG_ENABLED */
470
471#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
472 /*
473 * Allocate GC Release Logger instances (finalized in the relocator).
474 */
475 if (VBOX_SUCCESS(rc))
476 {
477 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
478 if (pRelLogger)
479 {
480 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERRC, afGroups[pRelLogger->cGroups]);
481 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
482 if (VBOX_SUCCESS(rc))
483 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
484 }
485 }
486#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
487
488#ifdef VBOX_WITH_NMI
489 /*
490 * Allocate mapping for the host APIC.
491 */
492 if (VBOX_SUCCESS(rc))
493 {
494 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
495 AssertRC(rc);
496 }
497#endif
498 if (VBOX_SUCCESS(rc))
499 {
500 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
501 if (VBOX_SUCCESS(rc))
502 {
503 /*
504 * Debug info.
505 */
506 DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
507
508 /*
509 * Statistics.
510 */
511 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
512 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
520 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
521 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
522 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
523 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
524 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
525 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
526 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
527 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
528 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
529 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
530 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
531 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
532 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
533 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
534 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
535 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
536 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
537 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
538 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
539 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
540 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
541 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
542 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
543 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
544 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
545 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
546 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
547 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
548 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
549 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
550 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
551 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
552 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
553 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
554 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
555 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
556 STAM_REG(pVM, &pVM->vmm.s.StatGCRetHyperAssertion, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/HyperAssert", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
557 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
558 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
559 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
560 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
561
562 return VINF_SUCCESS;
563 }
564 AssertRC(rc);
565 }
566 }
567 /** @todo: Need failure cleanup. */
568
569 //more todo in here?
570 //if (VBOX_SUCCESS(rc))
571 //{
572 //}
573 //int rc2 = vmmR3TermCoreCode(pVM);
574 //AssertRC(rc2));
575 }
576
577 return rc;
578}
579
580
581/**
582 * Ring-3 init finalizing.
583 *
584 * @returns VBox status code.
585 * @param pVM The VM handle.
586 */
587VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
588{
589#ifdef VBOX_STRICT_VMM_STACK
590 /*
591 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
592 */
593 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
594 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
595 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
596
597 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
598 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
599 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
600#endif
601
602 /*
603 * Set page attributes to r/w for stack pages.
604 */
605 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
606 AssertRC(rc);
607 if (VBOX_SUCCESS(rc))
608 {
609 /*
610 * Create the EMT yield timer.
611 */
612 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
613 if (VBOX_SUCCESS(rc))
614 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
615 }
616#ifdef VBOX_WITH_NMI
617 /*
618 * Map the host APIC into GC - This may be host os specific!
619 */
620 if (VBOX_SUCCESS(rc))
621 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
622 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
623#endif
624 return rc;
625}
626
627
628/**
629 * Initializes the R0 VMM.
630 *
631 * @returns VBox status code.
632 * @param pVM The VM to operate on.
633 */
634VMMR3DECL(int) VMMR3InitR0(PVM pVM)
635{
636 int rc;
637
638 /*
639 * Initialize the ring-0 logger if we haven't done so yet.
640 */
641 if ( pVM->vmm.s.pR0Logger
642 && !pVM->vmm.s.pR0Logger->fCreated)
643 {
644 rc = VMMR3UpdateLoggers(pVM);
645 if (VBOX_FAILURE(rc))
646 return rc;
647 }
648
649 /*
650 * Call Ring-0 entry with init code.
651 */
652 for (;;)
653 {
654#ifdef NO_SUPCALLR0VMM
655 //rc = VERR_GENERAL_FAILURE;
656 rc = VINF_SUCCESS;
657#else
658 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, VMMGetSvnRev(), NULL);
659#endif
660 if ( pVM->vmm.s.pR0Logger
661 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
662 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
663 if (rc != VINF_VMM_CALL_HOST)
664 break;
665 rc = vmmR3ServiceCallHostRequest(pVM);
666 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
667 break;
668 /* Resume R0 */
669 }
670
671 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
672 {
673 LogRel(("R0 init failed, rc=%Vra\n", rc));
674 if (VBOX_SUCCESS(rc))
675 rc = VERR_INTERNAL_ERROR;
676 }
677 return rc;
678}
679
680
681/**
682 * Initializes the GC VMM.
683 *
684 * @returns VBox status code.
685 * @param pVM The VM to operate on.
686 */
687VMMR3DECL(int) VMMR3InitGC(PVM pVM)
688{
689 /* In VMX mode, there's no need to init GC. */
690 if (pVM->vmm.s.fSwitcherDisabled)
691 return VINF_SUCCESS;
692
693 /*
694 * Call VMMGCInit():
695 * -# resolve the address.
696 * -# setup stackframe and EIP to use the trampoline.
697 * -# do a generic hypervisor call.
698 */
699 RTGCPTR32 GCPtrEP;
700 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
701 if (VBOX_SUCCESS(rc))
702 {
703 CPUMHyperSetCtxCore(pVM, NULL);
704 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
705 uint64_t u64TS = RTTimeProgramStartNanoTS();
706 CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
707 CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
708 CPUMPushHyper(pVM, VMMGetSvnRev()); /* Param 2: Version argument. */
709 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
710 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
711 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR32)); /* trampoline param: stacksize. */
712 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
713 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
714
715 for (;;)
716 {
717#ifdef NO_SUPCALLR0VMM
718 //rc = VERR_GENERAL_FAILURE;
719 rc = VINF_SUCCESS;
720#else
721 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
722#endif
723#ifdef LOG_ENABLED
724 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
725 if ( pLogger
726 && pLogger->offScratch > 0)
727 RTLogFlushGC(NULL, pLogger);
728#endif
729#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
730 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
731 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
732 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
733#endif
734 if (rc != VINF_VMM_CALL_HOST)
735 break;
736 rc = vmmR3ServiceCallHostRequest(pVM);
737 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
738 break;
739 }
740
741 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
742 {
743 VMMR3FatalDump(pVM, rc);
744 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
745 rc = VERR_INTERNAL_ERROR;
746 }
747 AssertRC(rc);
748 }
749 return rc;
750}
751
752
753/**
754 * Terminate the VMM bits.
755 *
756 * @returns VINF_SUCCESS.
757 * @param pVM The VM handle.
758 */
759VMMR3DECL(int) VMMR3Term(PVM pVM)
760{
761 /*
762 * Call Ring-0 entry with termination code.
763 */
764 int rc;
765 for (;;)
766 {
767#ifdef NO_SUPCALLR0VMM
768 //rc = VERR_GENERAL_FAILURE;
769 rc = VINF_SUCCESS;
770#else
771 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_TERM, 0, NULL);
772#endif
773 if ( pVM->vmm.s.pR0Logger
774 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
775 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
776 if (rc != VINF_VMM_CALL_HOST)
777 break;
778 rc = vmmR3ServiceCallHostRequest(pVM);
779 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
780 break;
781 /* Resume R0 */
782 }
783 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
784 {
785 LogRel(("VMMR3Term: R0 term failed, rc=%Vra. (warning)\n", rc));
786 if (VBOX_SUCCESS(rc))
787 rc = VERR_INTERNAL_ERROR;
788 }
789
790#ifdef VBOX_STRICT_VMM_STACK
791 /*
792 * Make the two stack guard pages present again.
793 */
794 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
795 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
796#endif
797 return rc;
798}
799
800
801/**
802 * Applies relocations to data and code managed by this
803 * component. This function will be called at init and
804 * whenever the VMM need to relocate it self inside the GC.
805 *
806 * The VMM will need to apply relocations to the core code.
807 *
808 * @param pVM The VM handle.
809 * @param offDelta The relocation delta.
810 */
811VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
812{
813 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
814
815 /*
816 * Recalc the GC address.
817 */
818 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
819
820 /*
821 * The stack.
822 */
823 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
824 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
825 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
826
827 /*
828 * All the switchers.
829 */
830 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
831 {
832 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
833 if (pSwitcher && pSwitcher->pfnRelocate)
834 {
835 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
836 pSwitcher->pfnRelocate(pVM,
837 pSwitcher,
838 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
839 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
840 pVM->vmm.s.pvGCCoreCode + off,
841 pVM->vmm.s.HCPhysCoreCode + off);
842 }
843 }
844
845 /*
846 * Recalc the GC address for the current switcher.
847 */
848 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
849 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
850 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
851 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
852 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
853 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
854 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
855
856 /*
857 * Get other GC entry points.
858 */
859 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
860 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
861
862 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
863 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
864
865 /*
866 * Update the logger.
867 */
868 VMMR3UpdateLoggers(pVM);
869}
870
871
872/**
873 * Updates the settings for the GC and R0 loggers.
874 *
875 * @returns VBox status code.
876 * @param pVM The VM handle.
877 */
878VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
879{
880 /*
881 * Simply clone the logger instance (for GC).
882 */
883 int rc = VINF_SUCCESS;
884 RTGCPTR32 GCPtrLoggerFlush = 0;
885
886 if (pVM->vmm.s.pLoggerHC
887#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
888 || pVM->vmm.s.pRelLoggerHC
889#endif
890 )
891 {
892 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
893 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
894 }
895
896 if (pVM->vmm.s.pLoggerHC)
897 {
898 RTGCPTR32 GCPtrLoggerWrapper = 0;
899 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
900 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
901 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
902 rc = RTLogCloneRC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
903 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
904 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
905 }
906
907#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
908 if (pVM->vmm.s.pRelLoggerHC)
909 {
910 RTGCPTR32 GCPtrLoggerWrapper = 0;
911 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
912 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
913 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
914 rc = RTLogCloneRC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
915 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
916 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
917 }
918#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
919
920 /*
921 * For the ring-0 EMT logger, we use a per-thread logger
922 * instance in ring-0. Only initialize it once.
923 */
924 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
925 if (pR0Logger)
926 {
927 if (!pR0Logger->fCreated)
928 {
929 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
930 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
931 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
932
933 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
934 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
935 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
936
937 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
938 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
939 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
940 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
941 pR0Logger->fCreated = true;
942 }
943
944 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, pVM->vmm.s.pLoggerHC->fFlags, RTLOGFLAGS_BUFFERED);
945 AssertRC(rc);
946 }
947
948 return rc;
949}
950
951
952/**
953 * Generic switch code relocator.
954 *
955 * @param pVM The VM handle.
956 * @param pSwitcher The switcher definition.
957 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
958 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
959 * @param GCPtrCode The guest context address corresponding to pu8Code.
960 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
961 * @param SelCS The hypervisor CS selector.
962 * @param SelDS The hypervisor DS selector.
963 * @param SelTSS The hypervisor TSS selector.
964 * @param GCPtrGDT The GC address of the hypervisor GDT.
965 * @param SelCS64 The 64-bit mode hypervisor CS selector.
966 */
967static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
968 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
969{
970 union
971 {
972 const uint8_t *pu8;
973 const uint16_t *pu16;
974 const uint32_t *pu32;
975 const uint64_t *pu64;
976 const void *pv;
977 uintptr_t u;
978 } u;
979 u.pv = pSwitcher->pvFixups;
980
981 /*
982 * Process fixups.
983 */
984 uint8_t u8;
985 while ((u8 = *u.pu8++) != FIX_THE_END)
986 {
987 /*
988 * Get the source (where to write the fixup).
989 */
990 uint32_t offSrc = *u.pu32++;
991 Assert(offSrc < pSwitcher->cbCode);
992 union
993 {
994 uint8_t *pu8;
995 uint16_t *pu16;
996 uint32_t *pu32;
997 uint64_t *pu64;
998 uintptr_t u;
999 } uSrc;
1000 uSrc.pu8 = pu8CodeR3 + offSrc;
1001
1002 /* The fixup target and method depends on the type. */
1003 switch (u8)
1004 {
1005 /*
1006 * 32-bit relative, source in HC and target in GC.
1007 */
1008 case FIX_HC_2_GC_NEAR_REL:
1009 {
1010 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1011 uint32_t offTrg = *u.pu32++;
1012 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1013 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
1014 break;
1015 }
1016
1017 /*
1018 * 32-bit relative, source in HC and target in ID.
1019 */
1020 case FIX_HC_2_ID_NEAR_REL:
1021 {
1022 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1023 uint32_t offTrg = *u.pu32++;
1024 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1025 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - ((uintptr_t)pu8CodeR0 + offSrc + 4));
1026 break;
1027 }
1028
1029 /*
1030 * 32-bit relative, source in GC and target in HC.
1031 */
1032 case FIX_GC_2_HC_NEAR_REL:
1033 {
1034 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1035 uint32_t offTrg = *u.pu32++;
1036 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1037 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
1038 break;
1039 }
1040
1041 /*
1042 * 32-bit relative, source in GC and target in ID.
1043 */
1044 case FIX_GC_2_ID_NEAR_REL:
1045 {
1046 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1047 uint32_t offTrg = *u.pu32++;
1048 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1049 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1050 break;
1051 }
1052
1053 /*
1054 * 32-bit relative, source in ID and target in HC.
1055 */
1056 case FIX_ID_2_HC_NEAR_REL:
1057 {
1058 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1059 uint32_t offTrg = *u.pu32++;
1060 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1061 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1062 break;
1063 }
1064
1065 /*
1066 * 32-bit relative, source in ID and target in HC.
1067 */
1068 case FIX_ID_2_GC_NEAR_REL:
1069 {
1070 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1071 uint32_t offTrg = *u.pu32++;
1072 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1073 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1074 break;
1075 }
1076
1077 /*
1078 * 16:32 far jump, target in GC.
1079 */
1080 case FIX_GC_FAR32:
1081 {
1082 uint32_t offTrg = *u.pu32++;
1083 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1084 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1085 *uSrc.pu16++ = SelCS;
1086 break;
1087 }
1088
1089 /*
1090 * Make 32-bit GC pointer given CPUM offset.
1091 */
1092 case FIX_GC_CPUM_OFF:
1093 {
1094 uint32_t offCPUM = *u.pu32++;
1095 Assert(offCPUM < sizeof(pVM->cpum));
1096 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1097 break;
1098 }
1099
1100 /*
1101 * Make 32-bit GC pointer given VM offset.
1102 */
1103 case FIX_GC_VM_OFF:
1104 {
1105 uint32_t offVM = *u.pu32++;
1106 Assert(offVM < sizeof(VM));
1107 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1108 break;
1109 }
1110
1111 /*
1112 * Make 32-bit HC pointer given CPUM offset.
1113 */
1114 case FIX_HC_CPUM_OFF:
1115 {
1116 uint32_t offCPUM = *u.pu32++;
1117 Assert(offCPUM < sizeof(pVM->cpum));
1118 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1119 break;
1120 }
1121
1122 /*
1123 * Make 32-bit R0 pointer given VM offset.
1124 */
1125 case FIX_HC_VM_OFF:
1126 {
1127 uint32_t offVM = *u.pu32++;
1128 Assert(offVM < sizeof(VM));
1129 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1130 break;
1131 }
1132
1133 /*
1134 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1135 */
1136 case FIX_INTER_32BIT_CR3:
1137 {
1138
1139 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1140 break;
1141 }
1142
1143 /*
1144 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1145 */
1146 case FIX_INTER_PAE_CR3:
1147 {
1148
1149 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1150 break;
1151 }
1152
1153 /*
1154 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1155 */
1156 case FIX_INTER_AMD64_CR3:
1157 {
1158
1159 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1160 break;
1161 }
1162
1163 /*
1164 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1165 */
1166 case FIX_HYPER_32BIT_CR3:
1167 {
1168
1169 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1170 break;
1171 }
1172
1173 /*
1174 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1175 */
1176 case FIX_HYPER_PAE_CR3:
1177 {
1178
1179 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1180 break;
1181 }
1182
1183 /*
1184 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1185 */
1186 case FIX_HYPER_AMD64_CR3:
1187 {
1188
1189 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1190 break;
1191 }
1192
1193 /*
1194 * Store Hypervisor CS (16-bit).
1195 */
1196 case FIX_HYPER_CS:
1197 {
1198 *uSrc.pu16 = SelCS;
1199 break;
1200 }
1201
1202 /*
1203 * Store Hypervisor DS (16-bit).
1204 */
1205 case FIX_HYPER_DS:
1206 {
1207 *uSrc.pu16 = SelDS;
1208 break;
1209 }
1210
1211 /*
1212 * Store Hypervisor TSS (16-bit).
1213 */
1214 case FIX_HYPER_TSS:
1215 {
1216 *uSrc.pu16 = SelTSS;
1217 break;
1218 }
1219
1220 /*
1221 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1222 */
1223 case FIX_GC_TSS_GDTE_DW2:
1224 {
1225 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1226 *uSrc.pu32 = (uint32_t)GCPtr;
1227 break;
1228 }
1229
1230
1231 ///@todo case FIX_CR4_MASK:
1232 ///@todo case FIX_CR4_OSFSXR:
1233
1234 /*
1235 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1236 */
1237 case FIX_NO_FXSAVE_JMP:
1238 {
1239 uint32_t offTrg = *u.pu32++;
1240 Assert(offTrg < pSwitcher->cbCode);
1241 if (!CPUMSupportsFXSR(pVM))
1242 {
1243 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1244 *uSrc.pu32++ = offTrg - (offSrc + 5);
1245 }
1246 else
1247 {
1248 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1249 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1250 }
1251 break;
1252 }
1253
1254 /*
1255 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1256 */
1257 case FIX_NO_SYSENTER_JMP:
1258 {
1259 uint32_t offTrg = *u.pu32++;
1260 Assert(offTrg < pSwitcher->cbCode);
1261 if (!CPUMIsHostUsingSysEnter(pVM))
1262 {
1263 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1264 *uSrc.pu32++ = offTrg - (offSrc + 5);
1265 }
1266 else
1267 {
1268 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1269 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1270 }
1271 break;
1272 }
1273
1274 /*
1275 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1276 */
1277 case FIX_NO_SYSCALL_JMP:
1278 {
1279 uint32_t offTrg = *u.pu32++;
1280 Assert(offTrg < pSwitcher->cbCode);
1281 if (!CPUMIsHostUsingSysEnter(pVM))
1282 {
1283 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1284 *uSrc.pu32++ = offTrg - (offSrc + 5);
1285 }
1286 else
1287 {
1288 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1289 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1290 }
1291 break;
1292 }
1293
1294 /*
1295 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1296 */
1297 case FIX_HC_32BIT:
1298 {
1299 uint32_t offTrg = *u.pu32++;
1300 Assert(offSrc < pSwitcher->cbCode);
1301 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1302 *uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1303 break;
1304 }
1305
1306#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1307 /*
1308 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1309 */
1310 case FIX_HC_64BIT:
1311 {
1312 uint32_t offTrg = *u.pu32++;
1313 Assert(offSrc < pSwitcher->cbCode);
1314 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1315 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1316 break;
1317 }
1318
1319 /*
1320 * 64-bit HC Code Selector (no argument).
1321 */
1322 case FIX_HC_64BIT_CS:
1323 {
1324 Assert(offSrc < pSwitcher->cbCode);
1325#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1326 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1327#else
1328 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1329#endif
1330 break;
1331 }
1332
1333 /*
1334 * 64-bit HC pointer to the CPUM instance data (no argument).
1335 */
1336 case FIX_HC_64BIT_CPUM:
1337 {
1338 Assert(offSrc < pSwitcher->cbCode);
1339 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1340 break;
1341 }
1342#endif
1343
1344 /*
1345 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1346 */
1347 case FIX_ID_32BIT:
1348 {
1349 uint32_t offTrg = *u.pu32++;
1350 Assert(offSrc < pSwitcher->cbCode);
1351 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1352 *uSrc.pu32 = u32IDCode + offTrg;
1353 break;
1354 }
1355
1356 /*
1357 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1358 */
1359 case FIX_ID_64BIT:
1360 {
1361 uint32_t offTrg = *u.pu32++;
1362 Assert(offSrc < pSwitcher->cbCode);
1363 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1364 *uSrc.pu64 = u32IDCode + offTrg;
1365 break;
1366 }
1367
1368 /*
1369 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1370 */
1371 case FIX_ID_FAR32_TO_64BIT_MODE:
1372 {
1373 uint32_t offTrg = *u.pu32++;
1374 Assert(offSrc < pSwitcher->cbCode);
1375 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1376 *uSrc.pu32++ = u32IDCode + offTrg;
1377 *uSrc.pu16 = SelCS64;
1378 AssertRelease(SelCS64);
1379 break;
1380 }
1381
1382#ifdef VBOX_WITH_NMI
1383 /*
1384 * 32-bit address to the APIC base.
1385 */
1386 case FIX_GC_APIC_BASE_32BIT:
1387 {
1388 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1389 break;
1390 }
1391#endif
1392
1393 default:
1394 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1395 break;
1396 }
1397 }
1398
1399#ifdef LOG_ENABLED
1400 /*
1401 * If Log2 is enabled disassemble the switcher code.
1402 *
1403 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1404 */
1405 if (LogIs2Enabled())
1406 {
1407 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1408 " pu8CodeR0 = %p\n"
1409 " pu8CodeR3 = %p\n"
1410 " GCPtrCode = %VGv\n"
1411 " u32IDCode = %08x\n"
1412 " pVMGC = %VGv\n"
1413 " pCPUMGC = %VGv\n"
1414 " pVMHC = %p\n"
1415 " pCPUMHC = %p\n"
1416 " GCPtrGDT = %VGv\n"
1417 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1418 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1419 " SelCS = %04x\n"
1420 " SelDS = %04x\n"
1421 " SelCS64 = %04x\n"
1422 " SelTSS = %04x\n",
1423 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1424 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1425 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1426 GCPtrGDT,
1427 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1428 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1429 SelCS, SelDS, SelCS64, SelTSS);
1430
1431 uint32_t offCode = 0;
1432 while (offCode < pSwitcher->cbCode)
1433 {
1434 /*
1435 * Figure out where this is.
1436 */
1437 const char *pszDesc = NULL;
1438 RTUINTPTR uBase;
1439 uint32_t cbCode;
1440 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1441 {
1442 pszDesc = "HCCode0";
1443 uBase = (RTUINTPTR)pu8CodeR0;
1444 offCode = pSwitcher->offHCCode0;
1445 cbCode = pSwitcher->cbHCCode0;
1446 }
1447 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1448 {
1449 pszDesc = "HCCode1";
1450 uBase = (RTUINTPTR)pu8CodeR0;
1451 offCode = pSwitcher->offHCCode1;
1452 cbCode = pSwitcher->cbHCCode1;
1453 }
1454 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1455 {
1456 pszDesc = "GCCode";
1457 uBase = GCPtrCode;
1458 offCode = pSwitcher->offGCCode;
1459 cbCode = pSwitcher->cbGCCode;
1460 }
1461 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1462 {
1463 pszDesc = "IDCode0";
1464 uBase = u32IDCode;
1465 offCode = pSwitcher->offIDCode0;
1466 cbCode = pSwitcher->cbIDCode0;
1467 }
1468 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1469 {
1470 pszDesc = "IDCode1";
1471 uBase = u32IDCode;
1472 offCode = pSwitcher->offIDCode1;
1473 cbCode = pSwitcher->cbIDCode1;
1474 }
1475 else
1476 {
1477 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1478 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1479 offCode++;
1480 continue;
1481 }
1482
1483 /*
1484 * Disassemble it.
1485 */
1486 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1487 DISCPUSTATE Cpu;
1488
1489 memset(&Cpu, 0, sizeof(Cpu));
1490 Cpu.mode = CPUMODE_32BIT;
1491 while (cbCode > 0)
1492 {
1493 /* try label it */
1494 if (pSwitcher->offR0HostToGuest == offCode)
1495 RTLogPrintf(" *R0HostToGuest:\n");
1496 if (pSwitcher->offGCGuestToHost == offCode)
1497 RTLogPrintf(" *GCGuestToHost:\n");
1498 if (pSwitcher->offGCCallTrampoline == offCode)
1499 RTLogPrintf(" *GCCallTrampoline:\n");
1500 if (pSwitcher->offGCGuestToHostAsm == offCode)
1501 RTLogPrintf(" *GCGuestToHostAsm:\n");
1502 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1503 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1504 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1505 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1506
1507 /* disas */
1508 uint32_t cbInstr = 0;
1509 char szDisas[256];
1510 if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
1511 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1512 else
1513 {
1514 RTLogPrintf(" %04x: %02x '%c'\n",
1515 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1516 cbInstr = 1;
1517 }
1518 offCode += cbInstr;
1519 cbCode -= RT_MIN(cbInstr, cbCode);
1520 }
1521 }
1522 }
1523#endif
1524}
1525
1526
1527/**
1528 * Relocator for the 32-Bit to 32-Bit world switcher.
1529 */
1530DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1531{
1532 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1533 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1534}
1535
1536
1537/**
1538 * Relocator for the 32-Bit to PAE world switcher.
1539 */
1540DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1541{
1542 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1543 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1544}
1545
1546
1547/**
1548 * Relocator for the PAE to 32-Bit world switcher.
1549 */
1550DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1551{
1552 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1553 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1554}
1555
1556
1557/**
1558 * Relocator for the PAE to PAE world switcher.
1559 */
1560DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1561{
1562 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1563 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1564}
1565
1566
1567/**
1568 * Relocator for the AMD64 to PAE world switcher.
1569 */
1570DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1571{
1572 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1573 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1574}
1575
1576
1577/**
1578 * Gets the pointer to g_szRTAssertMsg1 in GC.
1579 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1580 * Returns NULL if not present.
1581 * @param pVM The VM handle.
1582 */
1583VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1584{
1585 RTGCPTR32 GCPtr;
1586 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1587 if (VBOX_SUCCESS(rc))
1588 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1589 return NULL;
1590}
1591
1592
1593/**
1594 * Gets the pointer to g_szRTAssertMsg2 in GC.
1595 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1596 * Returns NULL if not present.
1597 * @param pVM The VM handle.
1598 */
1599VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1600{
1601 RTGCPTR32 GCPtr;
1602 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1603 if (VBOX_SUCCESS(rc))
1604 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1605 return NULL;
1606}
1607
1608
1609/**
1610 * Execute state save operation.
1611 *
1612 * @returns VBox status code.
1613 * @param pVM VM Handle.
1614 * @param pSSM SSM operation handle.
1615 */
1616static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1617{
1618 LogFlow(("vmmR3Save:\n"));
1619
1620 /*
1621 * The hypervisor stack.
1622 */
1623 SSMR3PutRCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1624 RTRCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1625 AssertMsg(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE, ("Bottom %VGv ESP=%VGv\n", pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1626 SSMR3PutRCPtr(pSSM, GCPtrESP);
1627 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1628 return SSMR3PutU32(pSSM, ~0); /* terminator */
1629}
1630
1631
1632/**
1633 * Execute state load operation.
1634 *
1635 * @returns VBox status code.
1636 * @param pVM VM Handle.
1637 * @param pSSM SSM operation handle.
1638 * @param u32Version Data layout version.
1639 */
1640static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1641{
1642 LogFlow(("vmmR3Load:\n"));
1643
1644 /*
1645 * Validate version.
1646 */
1647 if (u32Version != VMM_SAVED_STATE_VERSION)
1648 {
1649 AssertMsgFailed(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1650 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1651 }
1652
1653 /*
1654 * Check that the stack is in the same place, or that it's fearly empty.
1655 */
1656 RTRCPTR GCPtrStackBottom;
1657 SSMR3GetRCPtr(pSSM, &GCPtrStackBottom);
1658 RTRCPTR GCPtrESP;
1659 int rc = SSMR3GetRCPtr(pSSM, &GCPtrESP);
1660 if (VBOX_FAILURE(rc))
1661 return rc;
1662
1663 /* Previously we checked if the location of the stack was identical or that the stack was empty.
1664 * This is not required as we can never initiate a save when GC context code performs a ring 3 call.
1665 */
1666 /* restore the stack. (not necessary; just consistency checking) */
1667 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1668
1669 /* terminator */
1670 uint32_t u32;
1671 rc = SSMR3GetU32(pSSM, &u32);
1672 if (VBOX_FAILURE(rc))
1673 return rc;
1674 if (u32 != ~0U)
1675 {
1676 AssertMsgFailed(("u32=%#x\n", u32));
1677 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1678 }
1679 return VINF_SUCCESS;
1680}
1681
1682
1683/**
1684 * Selects the switcher to be used for switching to GC.
1685 *
1686 * @returns VBox status code.
1687 * @param pVM VM handle.
1688 * @param enmSwitcher The new switcher.
1689 * @remark This function may be called before the VMM is initialized.
1690 */
1691VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1692{
1693 /*
1694 * Validate input.
1695 */
1696 if ( enmSwitcher < VMMSWITCHER_INVALID
1697 || enmSwitcher >= VMMSWITCHER_MAX)
1698 {
1699 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1700 return VERR_INVALID_PARAMETER;
1701 }
1702
1703 /* Do nothing if the switcher is disabled. */
1704 if (pVM->vmm.s.fSwitcherDisabled)
1705 return VINF_SUCCESS;
1706
1707 /*
1708 * Select the new switcher.
1709 */
1710 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1711 if (pSwitcher)
1712 {
1713 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1714 pVM->vmm.s.enmSwitcher = enmSwitcher;
1715
1716 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1717 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1718
1719 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1720 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1721 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1722 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1723 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1724 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1725 return VINF_SUCCESS;
1726 }
1727 return VERR_NOT_IMPLEMENTED;
1728}
1729
1730/**
1731 * Disable the switcher logic permanently.
1732 *
1733 * @returns VBox status code.
1734 * @param pVM VM handle.
1735 */
1736VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1737{
1738/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1739 * @code
1740 * mov eax, VERR_INTERNAL_ERROR
1741 * ret
1742 * @endcode
1743 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1744 */
1745 pVM->vmm.s.fSwitcherDisabled = true;
1746 return VINF_SUCCESS;
1747}
1748
1749
1750/**
1751 * Resolve a builtin GC symbol.
1752 * Called by PDM when loading or relocating GC modules.
1753 *
1754 * @returns VBox status
1755 * @param pVM VM Handle.
1756 * @param pszSymbol Symbol to resolv
1757 * @param pGCPtrValue Where to store the symbol value.
1758 * @remark This has to work before VMMR3Relocate() is called.
1759 */
1760VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1761{
1762 if (!strcmp(pszSymbol, "g_Logger"))
1763 {
1764 if (pVM->vmm.s.pLoggerHC)
1765 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1766 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1767 }
1768 else if (!strcmp(pszSymbol, "g_RelLogger"))
1769 {
1770#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1771 if (pVM->vmm.s.pRelLoggerHC)
1772 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1773 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1774#else
1775 *pGCPtrValue = NIL_RTGCPTR;
1776#endif
1777 }
1778 else
1779 return VERR_SYMBOL_NOT_FOUND;
1780 return VINF_SUCCESS;
1781}
1782
1783
1784/**
1785 * Suspends the the CPU yielder.
1786 *
1787 * @param pVM The VM handle.
1788 */
1789VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1790{
1791 if (!pVM->vmm.s.cYieldResumeMillies)
1792 {
1793 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1794 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1795 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1796 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1797 else
1798 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1799 TMTimerStop(pVM->vmm.s.pYieldTimer);
1800 }
1801 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1802}
1803
1804
1805/**
1806 * Stops the the CPU yielder.
1807 *
1808 * @param pVM The VM handle.
1809 */
1810VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1811{
1812 if (!pVM->vmm.s.cYieldResumeMillies)
1813 TMTimerStop(pVM->vmm.s.pYieldTimer);
1814 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1815 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1816}
1817
1818
1819/**
1820 * Resumes the CPU yielder when it has been a suspended or stopped.
1821 *
1822 * @param pVM The VM handle.
1823 */
1824VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1825{
1826 if (pVM->vmm.s.cYieldResumeMillies)
1827 {
1828 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1829 pVM->vmm.s.cYieldResumeMillies = 0;
1830 }
1831}
1832
1833
1834/**
1835 * Internal timer callback function.
1836 *
1837 * @param pVM The VM.
1838 * @param pTimer The timer handle.
1839 * @param pvUser User argument specified upon timer creation.
1840 */
1841static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1842{
1843 /*
1844 * This really needs some careful tuning. While we shouldn't be too gready since
1845 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1846 * because that'll cause us to stop up.
1847 *
1848 * The current logic is to use the default interval when there is no lag worth
1849 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1850 *
1851 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1852 * so the lag is up to date.)
1853 */
1854 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1855 if ( u64Lag < 50000000 /* 50ms */
1856 || ( u64Lag < 1000000000 /* 1s */
1857 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1858 )
1859 {
1860 uint64_t u64Elapsed = RTTimeNanoTS();
1861 pVM->vmm.s.u64LastYield = u64Elapsed;
1862
1863 RTThreadYield();
1864
1865#ifdef LOG_ENABLED
1866 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1867 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1868#endif
1869 }
1870 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1871}
1872
1873
1874/**
1875 * Acquire global VM lock.
1876 *
1877 * @returns VBox status code
1878 * @param pVM The VM to operate on.
1879 */
1880VMMR3DECL(int) VMMR3Lock(PVM pVM)
1881{
1882 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1883}
1884
1885
1886/**
1887 * Release global VM lock.
1888 *
1889 * @returns VBox status code
1890 * @param pVM The VM to operate on.
1891 */
1892VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1893{
1894 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1895}
1896
1897
1898/**
1899 * Return global VM lock owner.
1900 *
1901 * @returns Thread id of owner.
1902 * @returns NIL_RTTHREAD if no owner.
1903 * @param pVM The VM to operate on.
1904 */
1905VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1906{
1907 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1908}
1909
1910
1911/**
1912 * Checks if the current thread is the owner of the global VM lock.
1913 *
1914 * @returns true if owner.
1915 * @returns false if not owner.
1916 * @param pVM The VM to operate on.
1917 */
1918VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1919{
1920 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1921}
1922
1923
1924/**
1925 * Executes guest code.
1926 *
1927 * @param pVM VM handle.
1928 */
1929VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1930{
1931 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1932
1933 /*
1934 * Set the EIP and ESP.
1935 */
1936 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1937 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1938 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1939 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1940
1941 /*
1942 * We hide log flushes (outer) and hypervisor interrupts (inner).
1943 */
1944 for (;;)
1945 {
1946 int rc;
1947 do
1948 {
1949#ifdef NO_SUPCALLR0VMM
1950 rc = VERR_GENERAL_FAILURE;
1951#else
1952 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
1953 if (RT_LIKELY(rc == VINF_SUCCESS))
1954 rc = pVM->vmm.s.iLastGCRc;
1955#endif
1956 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1957
1958 /*
1959 * Flush the logs.
1960 */
1961#ifdef LOG_ENABLED
1962 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
1963 if ( pLogger
1964 && pLogger->offScratch > 0)
1965 RTLogFlushGC(NULL, pLogger);
1966#endif
1967#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1968 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1969 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1970 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1971#endif
1972 if (rc != VINF_VMM_CALL_HOST)
1973 {
1974 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1975 return rc;
1976 }
1977 rc = vmmR3ServiceCallHostRequest(pVM);
1978 if (VBOX_FAILURE(rc))
1979 return rc;
1980 /* Resume GC */
1981 }
1982}
1983
1984
1985/**
1986 * Executes guest code (Intel VT-x and AMD-V).
1987 *
1988 * @param pVM VM handle.
1989 */
1990VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1991{
1992 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1993
1994 for (;;)
1995 {
1996 int rc;
1997 do
1998 {
1999#ifdef NO_SUPCALLR0VMM
2000 rc = VERR_GENERAL_FAILURE;
2001#else
2002 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN);
2003 if (RT_LIKELY(rc == VINF_SUCCESS))
2004 rc = pVM->vmm.s.iLastGCRc;
2005#endif
2006 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2007
2008#ifdef LOG_ENABLED
2009 /*
2010 * Flush the log
2011 */
2012 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
2013 if ( pR0Logger
2014 && pR0Logger->Logger.offScratch > 0)
2015 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
2016#endif /* !LOG_ENABLED */
2017 if (rc != VINF_VMM_CALL_HOST)
2018 {
2019 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2020 return rc;
2021 }
2022 rc = vmmR3ServiceCallHostRequest(pVM);
2023 if (VBOX_FAILURE(rc) || rc == VINF_EM_DBG_HYPER_ASSERTION)
2024 return rc;
2025 /* Resume R0 */
2026 }
2027}
2028
2029/**
2030 * Calls GC a function.
2031 *
2032 * @param pVM The VM handle.
2033 * @param GCPtrEntry The GC function address.
2034 * @param cArgs The number of arguments in the ....
2035 * @param ... Arguments to the function.
2036 */
2037VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, ...)
2038{
2039 va_list args;
2040 va_start(args, cArgs);
2041 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2042 va_end(args);
2043 return rc;
2044}
2045
2046
2047/**
2048 * Calls GC a function.
2049 *
2050 * @param pVM The VM handle.
2051 * @param GCPtrEntry The GC function address.
2052 * @param cArgs The number of arguments in the ....
2053 * @param args Arguments to the function.
2054 */
2055VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, va_list args)
2056{
2057 Log2(("VMMR3CallGCV: GCPtrEntry=%VRv cArgs=%d\n", GCPtrEntry, cArgs));
2058
2059 /*
2060 * Setup the call frame using the trampoline.
2061 */
2062 CPUMHyperSetCtxCore(pVM, NULL);
2063 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2064 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR32));
2065 PRTGCUINTPTR32 pFrame = (PRTGCUINTPTR32)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2066 int i = cArgs;
2067 while (i-- > 0)
2068 *pFrame++ = va_arg(args, RTGCUINTPTR32);
2069
2070 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR32)); /* stack frame size */
2071 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2072 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2073
2074 /*
2075 * We hide log flushes (outer) and hypervisor interrupts (inner).
2076 */
2077 for (;;)
2078 {
2079 int rc;
2080 do
2081 {
2082#ifdef NO_SUPCALLR0VMM
2083 rc = VERR_GENERAL_FAILURE;
2084#else
2085 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2086 if (RT_LIKELY(rc == VINF_SUCCESS))
2087 rc = pVM->vmm.s.iLastGCRc;
2088#endif
2089 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2090
2091 /*
2092 * Flush the logs.
2093 */
2094#ifdef LOG_ENABLED
2095 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
2096 if ( pLogger
2097 && pLogger->offScratch > 0)
2098 RTLogFlushGC(NULL, pLogger);
2099#endif
2100#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2101 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2102 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2103 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2104#endif
2105 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2106 VMMR3FatalDump(pVM, rc);
2107 if (rc != VINF_VMM_CALL_HOST)
2108 {
2109 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2110 return rc;
2111 }
2112 rc = vmmR3ServiceCallHostRequest(pVM);
2113 if (VBOX_FAILURE(rc))
2114 return rc;
2115 }
2116}
2117
2118
2119/**
2120 * Resumes executing hypervisor code when interrupted
2121 * by a queue flush or a debug event.
2122 *
2123 * @returns VBox status code.
2124 * @param pVM VM handle.
2125 */
2126VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2127{
2128 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2129
2130 /*
2131 * We hide log flushes (outer) and hypervisor interrupts (inner).
2132 */
2133 for (;;)
2134 {
2135 int rc;
2136 do
2137 {
2138#ifdef NO_SUPCALLR0VMM
2139 rc = VERR_GENERAL_FAILURE;
2140#else
2141 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2142 if (RT_LIKELY(rc == VINF_SUCCESS))
2143 rc = pVM->vmm.s.iLastGCRc;
2144#endif
2145 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2146
2147 /*
2148 * Flush the loggers,
2149 */
2150#ifdef LOG_ENABLED
2151 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
2152 if ( pLogger
2153 && pLogger->offScratch > 0)
2154 RTLogFlushGC(NULL, pLogger);
2155#endif
2156#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2157 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2158 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2159 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2160#endif
2161 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2162 VMMR3FatalDump(pVM, rc);
2163 if (rc != VINF_VMM_CALL_HOST)
2164 {
2165 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2166 return rc;
2167 }
2168 rc = vmmR3ServiceCallHostRequest(pVM);
2169 if (VBOX_FAILURE(rc))
2170 return rc;
2171 }
2172}
2173
2174
2175/**
2176 * Service a call to the ring-3 host code.
2177 *
2178 * @returns VBox status code.
2179 * @param pVM VM handle.
2180 * @remark Careful with critsects.
2181 */
2182static int vmmR3ServiceCallHostRequest(PVM pVM)
2183{
2184 switch (pVM->vmm.s.enmCallHostOperation)
2185 {
2186 /*
2187 * Acquire the PDM lock.
2188 */
2189 case VMMCALLHOST_PDM_LOCK:
2190 {
2191 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2192 break;
2193 }
2194
2195 /*
2196 * Flush a PDM queue.
2197 */
2198 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2199 {
2200 PDMR3QueueFlushWorker(pVM, NULL);
2201 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2202 break;
2203 }
2204
2205 /*
2206 * Grow the PGM pool.
2207 */
2208 case VMMCALLHOST_PGM_POOL_GROW:
2209 {
2210 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2211 break;
2212 }
2213
2214 /*
2215 * Maps an page allocation chunk into ring-3 so ring-0 can use it.
2216 */
2217 case VMMCALLHOST_PGM_MAP_CHUNK:
2218 {
2219 pVM->vmm.s.rcCallHost = PGMR3PhysChunkMap(pVM, pVM->vmm.s.u64CallHostArg);
2220 break;
2221 }
2222
2223 /*
2224 * Allocates more handy pages.
2225 */
2226 case VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES:
2227 {
2228 pVM->vmm.s.rcCallHost = PGMR3PhysAllocateHandyPages(pVM);
2229 break;
2230 }
2231#ifndef VBOX_WITH_NEW_PHYS_CODE
2232
2233 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2234 {
2235 const RTGCPHYS GCPhys = pVM->vmm.s.u64CallHostArg;
2236 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, &GCPhys);
2237 break;
2238 }
2239#endif
2240
2241 /*
2242 * Acquire the PGM lock.
2243 */
2244 case VMMCALLHOST_PGM_LOCK:
2245 {
2246 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2247 break;
2248 }
2249
2250 /*
2251 * Flush REM handler notifications.
2252 */
2253 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2254 {
2255 REMR3ReplayHandlerNotifications(pVM);
2256 break;
2257 }
2258
2259 /*
2260 * This is a noop. We just take this route to avoid unnecessary
2261 * tests in the loops.
2262 */
2263 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2264 break;
2265
2266 /*
2267 * Set the VM error message.
2268 */
2269 case VMMCALLHOST_VM_SET_ERROR:
2270 VMR3SetErrorWorker(pVM);
2271 break;
2272
2273 /*
2274 * Set the VM runtime error message.
2275 */
2276 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2277 VMR3SetRuntimeErrorWorker(pVM);
2278 break;
2279
2280 /*
2281 * Signal a ring 0 hypervisor assertion.
2282 * Cancel the longjmp operation that's in progress.
2283 */
2284 case VMMCALLHOST_VM_R0_HYPER_ASSERTION:
2285 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2286 pVM->vmm.s.CallHostR0JmpBuf.fInRing3Call = false;
2287#ifdef RT_ARCH_X86
2288 pVM->vmm.s.CallHostR0JmpBuf.eip = 0;
2289#else
2290 pVM->vmm.s.CallHostR0JmpBuf.rip = 0;
2291#endif
2292 LogRel((pVM->vmm.s.szRing0AssertMsg1));
2293 LogRel((pVM->vmm.s.szRing0AssertMsg2));
2294 return VINF_EM_DBG_HYPER_ASSERTION;
2295
2296 default:
2297 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2298 return VERR_INTERNAL_ERROR;
2299 }
2300
2301 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2302 return VINF_SUCCESS;
2303}
2304
2305
2306
2307/**
2308 * Structure to pass to DBGFR3Info() and for doing all other
2309 * output during fatal dump.
2310 */
2311typedef struct VMMR3FATALDUMPINFOHLP
2312{
2313 /** The helper core. */
2314 DBGFINFOHLP Core;
2315 /** The release logger instance. */
2316 PRTLOGGER pRelLogger;
2317 /** The saved release logger flags. */
2318 RTUINT fRelLoggerFlags;
2319 /** The logger instance. */
2320 PRTLOGGER pLogger;
2321 /** The saved logger flags. */
2322 RTUINT fLoggerFlags;
2323 /** The saved logger destination flags. */
2324 RTUINT fLoggerDestFlags;
2325 /** Whether to output to stderr or not. */
2326 bool fStdErr;
2327} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2328typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2329
2330
2331/**
2332 * Print formatted string.
2333 *
2334 * @param pHlp Pointer to this structure.
2335 * @param pszFormat The format string.
2336 * @param ... Arguments.
2337 */
2338static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2339{
2340 va_list args;
2341 va_start(args, pszFormat);
2342 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2343 va_end(args);
2344}
2345
2346
2347/**
2348 * Print formatted string.
2349 *
2350 * @param pHlp Pointer to this structure.
2351 * @param pszFormat The format string.
2352 * @param args Argument list.
2353 */
2354static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2355{
2356 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2357
2358 if (pMyHlp->pRelLogger)
2359 {
2360 va_list args2;
2361 va_copy(args2, args);
2362 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2363 va_end(args2);
2364 }
2365 if (pMyHlp->pLogger)
2366 {
2367 va_list args2;
2368 va_copy(args2, args);
2369 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2370 va_end(args2);
2371 }
2372 if (pMyHlp->fStdErr)
2373 {
2374 va_list args2;
2375 va_copy(args2, args);
2376 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2377 va_end(args2);
2378 }
2379}
2380
2381
2382/**
2383 * Initializes the fatal dump output helper.
2384 *
2385 * @param pHlp The structure to initialize.
2386 */
2387static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2388{
2389 memset(pHlp, 0, sizeof(*pHlp));
2390
2391 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2392 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2393
2394 /*
2395 * The loggers.
2396 */
2397 pHlp->pRelLogger = RTLogRelDefaultInstance();
2398#ifndef LOG_ENABLED
2399 if (!pHlp->pRelLogger)
2400#endif
2401 pHlp->pLogger = RTLogDefaultInstance();
2402
2403 if (pHlp->pRelLogger)
2404 {
2405 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2406 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2407 }
2408
2409 if (pHlp->pLogger)
2410 {
2411 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2412 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2413 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2414#ifndef DEBUG_sandervl
2415 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2416#endif
2417 }
2418
2419 /*
2420 * Check if we need write to stderr.
2421 */
2422#ifdef DEBUG_sandervl
2423 pHlp->fStdErr = false; /* takes too long to display here */
2424#else
2425 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2426 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2427#endif
2428}
2429
2430
2431/**
2432 * Deletes the fatal dump output helper.
2433 *
2434 * @param pHlp The structure to delete.
2435 */
2436static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2437{
2438 if (pHlp->pRelLogger)
2439 {
2440 RTLogFlush(pHlp->pRelLogger);
2441 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2442 }
2443
2444 if (pHlp->pLogger)
2445 {
2446 RTLogFlush(pHlp->pLogger);
2447 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2448 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2449 }
2450}
2451
2452
2453/**
2454 * Dumps the VM state on a fatal error.
2455 *
2456 * @param pVM VM Handle.
2457 * @param rcErr VBox status code.
2458 */
2459VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2460{
2461 /*
2462 * Create our output helper and sync it with the log settings.
2463 * This helper will be used for all the output.
2464 */
2465 VMMR3FATALDUMPINFOHLP Hlp;
2466 PCDBGFINFOHLP pHlp = &Hlp.Core;
2467 vmmR3FatalDumpInfoHlpInit(&Hlp);
2468
2469 /*
2470 * Header.
2471 */
2472 pHlp->pfnPrintf(pHlp,
2473 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2474 "!!\n"
2475 "!! Guru Meditation %d (%Vrc)\n"
2476 "!!\n",
2477 rcErr, rcErr);
2478
2479 /*
2480 * Continue according to context.
2481 */
2482 bool fDoneHyper = false;
2483 switch (rcErr)
2484 {
2485 /*
2486 * Hypervisor errors.
2487 */
2488 case VINF_EM_DBG_HYPER_ASSERTION:
2489 {
2490 const char *pszMsg1 = HWACCMR3IsActive(pVM) ? pVM->vmm.s.szRing0AssertMsg1 : VMMR3GetGCAssertMsg1(pVM);
2491 while (pszMsg1 && *pszMsg1 == '\n')
2492 pszMsg1++;
2493 const char *pszMsg2 = HWACCMR3IsActive(pVM) ? pVM->vmm.s.szRing0AssertMsg2 : VMMR3GetGCAssertMsg2(pVM);
2494 while (pszMsg2 && *pszMsg2 == '\n')
2495 pszMsg2++;
2496 pHlp->pfnPrintf(pHlp,
2497 "%s"
2498 "%s",
2499 pszMsg1,
2500 pszMsg2);
2501 if ( !pszMsg2
2502 || !*pszMsg2
2503 || strchr(pszMsg2, '\0')[-1] != '\n')
2504 pHlp->pfnPrintf(pHlp, "\n");
2505 pHlp->pfnPrintf(pHlp, "!!\n");
2506 /* fall thru */
2507 }
2508 case VERR_TRPM_DONT_PANIC:
2509 case VERR_TRPM_PANIC:
2510 case VINF_EM_RAW_STALE_SELECTOR:
2511 case VINF_EM_RAW_IRET_TRAP:
2512 case VINF_EM_DBG_HYPER_BREAKPOINT:
2513 case VINF_EM_DBG_HYPER_STEPPED:
2514 {
2515 /*
2516 * Active trap? This is only of partial interest when in hardware
2517 * assisted virtualization mode, thus the different messages.
2518 */
2519 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2520 TRPMEVENT enmType;
2521 uint8_t u8TrapNo = 0xce;
2522 RTGCUINT uErrorCode = 0xdeadface;
2523 RTGCUINTPTR uCR2 = 0xdeadface;
2524 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2525 if (!HWACCMR3IsActive(pVM))
2526 {
2527 if (RT_SUCCESS(rc2))
2528 pHlp->pfnPrintf(pHlp,
2529 "!! TRAP=%02x ERRCD=%RGv CR2=%RGv EIP=%RX32 Type=%d\n",
2530 u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2531 else
2532 pHlp->pfnPrintf(pHlp,
2533 "!! EIP=%RX32 NOTRAP\n",
2534 uEIP);
2535 }
2536 else if (RT_SUCCESS(rc2))
2537 pHlp->pfnPrintf(pHlp,
2538 "!! ACTIVE TRAP=%02x ERRCD=%RGv CR2=%RGv PC=%RGr Type=%d (Guest!)\n",
2539 u8TrapNo, uErrorCode, uCR2, CPUMGetGuestRIP(pVM), enmType);
2540
2541 /*
2542 * The hypervisor dump is not relevant when we're in VT-x/AMD-V mode.
2543 */
2544 if (HWACCMR3IsActive(pVM))
2545 pHlp->pfnPrintf(pHlp, "\n");
2546 else
2547 {
2548 /*
2549 * Try figure out where eip is.
2550 */
2551 /* core code? */
2552 if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2553 pHlp->pfnPrintf(pHlp,
2554 "!! EIP is in CoreCode, offset %#x\n",
2555 uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2556 else
2557 { /* ask PDM */ /** @todo ask DBGFR3Sym later? */
2558 char szModName[64];
2559 RTGCPTR GCPtrMod;
2560 char szNearSym1[260];
2561 RTGCPTR GCPtrNearSym1;
2562 char szNearSym2[260];
2563 RTGCPTR GCPtrNearSym2;
2564 int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2565 &szModName[0], sizeof(szModName), &GCPtrMod,
2566 &szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2567 &szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2568 if (VBOX_SUCCESS(rc))
2569 pHlp->pfnPrintf(pHlp,
2570 "!! EIP in %s (%RGv) at rva %x near symbols:\n"
2571 "!! %RGv rva %RGv off %08x %s\n"
2572 "!! %RGv rva %RGv off -%08x %s\n",
2573 szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2574 GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2575 GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2576 else
2577 pHlp->pfnPrintf(pHlp,
2578 "!! EIP is not in any code known to VMM!\n");
2579 }
2580
2581 /* Disassemble the instruction. */
2582 char szInstr[256];
2583 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2584 if (VBOX_SUCCESS(rc2))
2585 pHlp->pfnPrintf(pHlp,
2586 "!! %s\n", szInstr);
2587
2588 /* Dump the hypervisor cpu state. */
2589 pHlp->pfnPrintf(pHlp,
2590 "!!\n"
2591 "!!\n"
2592 "!!\n");
2593 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2594 fDoneHyper = true;
2595
2596 /* Callstack. */
2597 DBGFSTACKFRAME Frame = {0};
2598 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2599 if (VBOX_SUCCESS(rc2))
2600 {
2601 pHlp->pfnPrintf(pHlp,
2602 "!!\n"
2603 "!! Call Stack:\n"
2604 "!!\n"
2605 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2606 do
2607 {
2608 pHlp->pfnPrintf(pHlp,
2609 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2610 (uint32_t)Frame.AddrFrame.off,
2611 (uint32_t)Frame.AddrReturnFrame.off,
2612 (uint32_t)Frame.AddrReturnPC.Sel,
2613 (uint32_t)Frame.AddrReturnPC.off,
2614 Frame.Args.au32[0],
2615 Frame.Args.au32[1],
2616 Frame.Args.au32[2],
2617 Frame.Args.au32[3]);
2618 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2619 if (Frame.pSymPC)
2620 {
2621 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2622 if (offDisp > 0)
2623 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2624 else if (offDisp < 0)
2625 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2626 else
2627 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2628 }
2629 if (Frame.pLinePC)
2630 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2631 pHlp->pfnPrintf(pHlp, "\n");
2632
2633 /* next */
2634 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2635 } while (VBOX_SUCCESS(rc2));
2636 DBGFR3StackWalkEnd(pVM, &Frame);
2637 }
2638
2639 /* raw stack */
2640 pHlp->pfnPrintf(pHlp,
2641 "!!\n"
2642 "!! Raw stack (mind the direction).\n"
2643 "!!\n"
2644 "%.*Vhxd\n",
2645 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2646 } /* !HWACCMR3IsActive */
2647 break;
2648 }
2649
2650 default:
2651 {
2652 break;
2653 }
2654
2655 } /* switch (rcErr) */
2656
2657
2658 /*
2659 * Generic info dumper loop.
2660 */
2661 static struct
2662 {
2663 const char *pszInfo;
2664 const char *pszArgs;
2665 } const aInfo[] =
2666 {
2667 { "mappings", NULL },
2668 { "hma", NULL },
2669 { "cpumguest", "verbose" },
2670 { "cpumguestinstr", "verbose" },
2671 { "cpumhyper", "verbose" },
2672 { "cpumhost", "verbose" },
2673 { "mode", "all" },
2674 { "cpuid", "verbose" },
2675 { "gdt", NULL },
2676 { "ldt", NULL },
2677 //{ "tss", NULL },
2678 { "ioport", NULL },
2679 { "mmio", NULL },
2680 { "phys", NULL },
2681 //{ "pgmpd", NULL }, - doesn't always work at init time...
2682 { "timers", NULL },
2683 { "activetimers", NULL },
2684 { "handlers", "phys virt hyper stats" },
2685 { "cfgm", NULL },
2686 };
2687 for (unsigned i = 0; i < RT_ELEMENTS(aInfo); i++)
2688 {
2689 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2690 continue;
2691 pHlp->pfnPrintf(pHlp,
2692 "!!\n"
2693 "!! {%s, %s}\n"
2694 "!!\n",
2695 aInfo[i].pszInfo, aInfo[i].pszArgs);
2696 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2697 }
2698
2699 /* done */
2700 pHlp->pfnPrintf(pHlp,
2701 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2702
2703
2704 /*
2705 * Delete the output instance (flushing and restoring of flags).
2706 */
2707 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2708}
2709
2710
2711
2712/**
2713 * Displays the Force action Flags.
2714 *
2715 * @param pVM The VM handle.
2716 * @param pHlp The output helpers.
2717 * @param pszArgs The additional arguments (ignored).
2718 */
2719static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2720{
2721 const uint32_t fForcedActions = pVM->fForcedActions;
2722
2723 pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2724
2725 /* show the flag mnemonics */
2726 int c = 0;
2727 uint32_t f = fForcedActions;
2728#define PRINT_FLAG(flag) do { \
2729 if (f & (flag)) \
2730 { \
2731 static const char *s_psz = #flag; \
2732 if (!(c % 6)) \
2733 pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2734 else \
2735 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2736 c++; \
2737 f &= ~(flag); \
2738 } \
2739 } while (0)
2740 PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2741 PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2742 PRINT_FLAG(VM_FF_TIMER);
2743 PRINT_FLAG(VM_FF_PDM_QUEUES);
2744 PRINT_FLAG(VM_FF_PDM_DMA);
2745 PRINT_FLAG(VM_FF_PDM_CRITSECT);
2746 PRINT_FLAG(VM_FF_DBGF);
2747 PRINT_FLAG(VM_FF_REQUEST);
2748 PRINT_FLAG(VM_FF_TERMINATE);
2749 PRINT_FLAG(VM_FF_RESET);
2750 PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2751 PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2752 PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2753 PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2754 PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2755 PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2756 PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2757 PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2758 PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2759 PRINT_FLAG(VM_FF_TO_R3);
2760 PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2761 if (f)
2762 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2763 else
2764 pHlp->pfnPrintf(pHlp, "\n");
2765#undef PRINT_FLAG
2766
2767 /* the groups */
2768 c = 0;
2769#define PRINT_GROUP(grp) do { \
2770 if (fForcedActions & (grp)) \
2771 { \
2772 static const char *s_psz = #grp; \
2773 if (!(c % 5)) \
2774 pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2775 else \
2776 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2777 c++; \
2778 } \
2779 } while (0)
2780 PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2781 PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2782 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2783 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2784 PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2785 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2786 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2787 PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2788 PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2789 if (c)
2790 pHlp->pfnPrintf(pHlp, "\n");
2791#undef PRINT_GROUP
2792}
2793
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