VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 12623

Last change on this file since 12623 was 12564, checked in by vboxsync, 16 years ago

VMM: Don't need to make complicated 16-bit CFGM read here, but you must check that the value is sane afterwards!
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1/* $Id: VMM.cpp 12564 2008-09-18 12:13:15Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/** @page pg_vmm VMM - The Virtual Machine Monitor
25 *
26 * !Revise this! It's already incorrect!
27 *
28 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
29 * manages the alternate reality; controlling the virtualization, managing
30 * resources, tracking CPU state, it's resources and so on...
31 *
32 * We will split the VMM into smaller entities:
33 *
34 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
35 * provide ring and world switching, that including routing
36 * interrupts to the host OS and traps to the appropriate trap
37 * handlers. It will implement an external interface for
38 * managing trap handlers.
39 *
40 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
41 * reality) and implementing external interfaces to read and change
42 * the state.
43 *
44 * - Memory Monitor (MM), which purpose it is to virtualize physical
45 * pages, segment descriptor tables, interrupt descriptor tables, task
46 * segments, and keep track of all memory providing external interfaces
47 * to access content and map pages. (Internally splitt into smaller entities!)
48 *
49 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
50 * interacts with the MM to implement memory mapped I/O. External
51 * interfaces for adding and removing I/O ranges are implemented.
52 *
53 * - External Interrupt Monitor (EIM), which purpose it is to manage
54 * interrupts generated by virtual devices. This monitor provides
55 * an interfaces for raising interrupts which is accessible at any
56 * time and from all thread.
57 * <p>
58 * A subentity of the EIM is the vitual Programmable Interrupt
59 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
60 * Programmable Interrupt Controller Device (VAPICD).
61 *
62 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
63 * virtual device using the DMA controller. Interfaces must be as the
64 * EIM interfaces independent and threadable.
65 * <p>
66 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
67 *
68 *
69 * Entities working on a higher level:
70 *
71 * - Device Manager (DM), which is a support facility for virtualized
72 * hardware. This provides generic facilities for efficient device
73 * virtualization. It will manage device attaching and detaching
74 * conversing with EIM and IOM.
75 *
76 * - Debugger Facility (DBGF) provides the basic features for
77 * debugging the alternate reality execution.
78 *
79 *
80 *
81 * @section pg_vmm_s_use_cases Use Cases
82 *
83 * @subsection pg_vmm_s_use_case_boot Bootstrap
84 *
85 * - Basic Init:
86 * - Init SUPDRV.
87 *
88 * - Init Virtual Machine Instance:
89 * - Load settings.
90 * - Check resource requirements (memory, com, stuff).
91 *
92 * - Init Host Ring 3 part:
93 * - Init Core code.
94 * - Load Pluggable Components.
95 * - Init Pluggable Components.
96 *
97 * - Init Host Ring 0 part:
98 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
99 * - Init Core code.
100 * - Load Pluggable Component code.
101 * - Init Pluggable Component code.
102 *
103 * - Allocate first chunk of memory and pin it down. This block of memory
104 * will fit the following pieces:
105 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
106 * (This is available from everywhere (at different addresses though)).
107 * - VMM Guest Context code.
108 * - Pluggable devices Guest Context code.
109 * - Page tables (directory and everything) for the VMM Guest
110 *
111 * - Setup Guest (Ring 0) part:
112 * - Setup initial page tables (i.e. directory all the stuff).
113 * - Load Core Guest Context code.
114 * - Load Pluggable Devices Guest Context code.
115 *
116 *
117 */
118
119
120/*******************************************************************************
121* Header Files *
122*******************************************************************************/
123#define LOG_GROUP LOG_GROUP_VMM
124#include <VBox/vmm.h>
125#include <VBox/vmapi.h>
126#include <VBox/pgm.h>
127#include <VBox/cfgm.h>
128#include <VBox/pdmqueue.h>
129#include <VBox/pdmapi.h>
130#include <VBox/cpum.h>
131#include <VBox/mm.h>
132#include <VBox/iom.h>
133#include <VBox/trpm.h>
134#include <VBox/selm.h>
135#include <VBox/em.h>
136#include <VBox/sup.h>
137#include <VBox/dbgf.h>
138#include <VBox/csam.h>
139#include <VBox/patm.h>
140#include <VBox/rem.h>
141#include <VBox/ssm.h>
142#include <VBox/tm.h>
143#include "VMMInternal.h"
144#include "VMMSwitcher/VMMSwitcher.h"
145#include <VBox/vm.h>
146#include <VBox/err.h>
147#include <VBox/param.h>
148#include <VBox/version.h>
149#include <VBox/x86.h>
150#include <VBox/hwaccm.h>
151#include <iprt/assert.h>
152#include <iprt/alloc.h>
153#include <iprt/asm.h>
154#include <iprt/time.h>
155#include <iprt/stream.h>
156#include <iprt/string.h>
157#include <iprt/stdarg.h>
158#include <iprt/ctype.h>
159
160
161
162/** The saved state version. */
163#define VMM_SAVED_STATE_VERSION 3
164
165
166/*******************************************************************************
167* Internal Functions *
168*******************************************************************************/
169static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
170static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
171static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
172static int vmmR3ServiceCallHostRequest(PVM pVM);
173static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
174
175
176/*******************************************************************************
177* Global Variables *
178*******************************************************************************/
179/** Array of switcher defininitions.
180 * The type and index shall match!
181 */
182static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
183{
184 NULL, /* invalid entry */
185#ifndef RT_ARCH_AMD64
186 &vmmR3Switcher32BitTo32Bit_Def,
187 &vmmR3Switcher32BitToPAE_Def,
188 NULL, //&vmmR3Switcher32BitToAMD64_Def,
189 &vmmR3SwitcherPAETo32Bit_Def,
190 &vmmR3SwitcherPAEToPAE_Def,
191 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
192# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
193 &vmmR3SwitcherAMD64ToPAE_Def,
194# else
195 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
196# endif
197 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
198#else
199 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
200 NULL, //&vmmR3Switcher32BitToPAE_Def,
201 NULL, //&vmmR3Switcher32BitToAMD64_Def,
202 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
203 NULL, //&vmmR3SwitcherPAEToPAE_Def,
204 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
205 &vmmR3SwitcherAMD64ToPAE_Def,
206 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
207#endif
208};
209
210
211
212/**
213 * Initiates the core code.
214 *
215 * This is core per VM code which might need fixups and/or for ease of use
216 * are put on linear contiguous backing.
217 *
218 * @returns VBox status code.
219 * @param pVM Pointer to VM structure.
220 */
221static int vmmR3InitCoreCode(PVM pVM)
222{
223 /*
224 * Calc the size.
225 */
226 unsigned cbCoreCode = 0;
227 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
228 {
229 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
230 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
231 if (pSwitcher)
232 {
233 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
234 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
235 }
236 }
237
238 /*
239 * Allocate continguous pages for switchers and deal with
240 * conflicts in the intermediate mapping of the code.
241 */
242 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
243 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
244 int rc = VERR_NO_MEMORY;
245 if (pVM->vmm.s.pvHCCoreCodeR3)
246 {
247 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
248 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
249 {
250 /* try more allocations - Solaris */
251 const unsigned cTries = 4112;
252 struct VMMInitBadTry
253 {
254 RTR0PTR pvR0;
255 void *pvR3;
256 RTHCPHYS HCPhys;
257 RTUINT cb;
258 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
259 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
260 unsigned i = 0;
261 do
262 {
263 paBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
264 paBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
265 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
266 i++;
267 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
268 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
269 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
270 if (!pVM->vmm.s.pvHCCoreCodeR3)
271 break;
272 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
273 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
274 && i < cTries - 1);
275
276 /* cleanup */
277 if (VBOX_FAILURE(rc))
278 {
279 paBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
280 paBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
281 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
282 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
283 i++;
284 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
285 }
286 while (i-- > 0)
287 {
288 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
289 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
290 SUPContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
291 }
292 RTMemTmpFree(paBadTries);
293 }
294 }
295 if (VBOX_SUCCESS(rc))
296 {
297 /*
298 * copy the code.
299 */
300 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
301 {
302 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
303 if (pSwitcher)
304 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
305 pSwitcher->pvCode, pSwitcher->cbCode);
306 }
307
308 /*
309 * Map the code into the GC address space.
310 */
311 RTGCPTR GCPtr;
312 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &GCPtr);
313 if (VBOX_SUCCESS(rc))
314 {
315 pVM->vmm.s.pvGCCoreCode = GCPtr;
316 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
317 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VRv Phys=%VHp cb=%#x\n",
318 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
319
320 /*
321 * Finally, PGM probably have selected a switcher already but we need
322 * to do get the addresses so we'll reselect it.
323 * This may legally fail so, we're ignoring the rc.
324 */
325 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
326 return rc;
327 }
328
329 /* shit */
330 AssertMsgFailed(("PGMR3Map(,%VRv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
331 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
332 }
333 else
334 VMSetError(pVM, rc, RT_SRC_POS,
335 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
336 cbCoreCode);
337
338 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
339 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
340 pVM->vmm.s.pvGCCoreCode = 0;
341 return rc;
342}
343
344
345/**
346 * Initializes the VMM.
347 *
348 * @returns VBox status code.
349 * @param pVM The VM to operate on.
350 */
351VMMR3DECL(int) VMMR3Init(PVM pVM)
352{
353 LogFlow(("VMMR3Init\n"));
354
355 /*
356 * Assert alignment, sizes and order.
357 */
358 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
359 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
360 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
361 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
362
363 /*
364 * Init basic VM VMM members.
365 */
366 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
367 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
368 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
369 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
370 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
371 else
372 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
373
374 /* GC switchers are enabled by default. Turned off by HWACCM. */
375 pVM->vmm.s.fSwitcherDisabled = false;
376
377 /* Get the CPU count.*/
378 rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "NumCPUs", &pVM->cCPUs, 1);
379 AssertLogRelMsgRCReturn(rc, ("Configuration error: Querying \"NumCPUs\" as integer failed, rc=%Vrc\n", rc), rc);
380#ifdef VBOX_WITH_SMP_GUESTS
381 AssertLogRelMsgReturn(pVM->cCPUs > 0 && pVM->cCPUs <= 256,
382 ("Configuration error: \"NumCPUs\"=%RU32 is out of range [1..256]\n", pVM->cCPUs), VERR_INVALID_PARAMETER);
383#else
384 AssertLogRelMsgReturn(pVM->cCPUs != 0,
385 ("Configuration error: \"NumCPUs\"=%RU32, expected 1\n", pVM->cCPUs), VERR_INVALID_PARAMETER);
386#endif
387
388#ifdef VBOX_WITH_SMP_GUESTS
389 LogRel(("[SMP] VMM with %RU32 CPUs\n", pVM->cCPUs));
390#endif
391
392 /* Current CPU id */ /** @todo move to per CPU structure. */
393 pVM->idCPU = 0;
394
395 /*
396 * Register the saved state data unit.
397 */
398 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
399 NULL, vmmR3Save, NULL,
400 NULL, vmmR3Load, NULL);
401 if (VBOX_FAILURE(rc))
402 return rc;
403
404 /*
405 * Register the Ring-0 VM handle with the session for fast ioctl calls.
406 */
407 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
408 if (VBOX_FAILURE(rc))
409 return rc;
410
411 /*
412 * Init core code.
413 */
414 rc = vmmR3InitCoreCode(pVM);
415 if (VBOX_SUCCESS(rc))
416 {
417 /*
418 * Allocate & init VMM GC stack.
419 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
420 * (The page protection is modifed during R3 init completion.)
421 */
422#ifdef VBOX_STRICT_VMM_STACK
423 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
424#else
425 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
426#endif
427 if (VBOX_SUCCESS(rc))
428 {
429 /* Set HC and GC stack pointers to top of stack. */
430 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
431 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
432 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
433 AssertRelease(pVM->vmm.s.pbGCStack);
434
435 /* Set hypervisor eip. */
436 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
437
438 /*
439 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
440 */
441#ifdef LOG_ENABLED
442 PRTLOGGER pLogger = RTLogDefaultInstance();
443 if (pLogger)
444 {
445 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERRC, afGroups[pLogger->cGroups]);
446 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
447 if (VBOX_SUCCESS(rc))
448 {
449 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
450
451/*
452 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
453 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
454 *
455 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
456 * to not stub all the log functions.
457 *
458 * You might also wish to enable the AssertMsg1/2 overrides in VMMR0.cpp when enabling this.
459 */
460# if defined(DEBUG_sandervl) || defined(DEBUG_frank)
461 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
462 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
463 if (VBOX_SUCCESS(rc))
464 {
465 pVM->vmm.s.pR0Logger->pVM = pVM->pVMR0;
466 //pVM->vmm.s.pR0Logger->fCreated = false;
467 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
468 }
469# endif
470 }
471 }
472#endif /* LOG_ENABLED */
473
474#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
475 /*
476 * Allocate GC Release Logger instances (finalized in the relocator).
477 */
478 if (VBOX_SUCCESS(rc))
479 {
480 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
481 if (pRelLogger)
482 {
483 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERRC, afGroups[pRelLogger->cGroups]);
484 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
485 if (VBOX_SUCCESS(rc))
486 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
487 }
488 }
489#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
490
491#ifdef VBOX_WITH_NMI
492 /*
493 * Allocate mapping for the host APIC.
494 */
495 if (VBOX_SUCCESS(rc))
496 {
497 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
498 AssertRC(rc);
499 }
500#endif
501 if (VBOX_SUCCESS(rc))
502 {
503 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
504 if (VBOX_SUCCESS(rc))
505 {
506 /*
507 * Debug info.
508 */
509 DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
510
511 /*
512 * Statistics.
513 */
514 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
520 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
521 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
522 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
523 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
524 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
525 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
526 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
527 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
528 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
529 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
530 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
531 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
532 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
533 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
534 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
535 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
536 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
537 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
538 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
539 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
540 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
541 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
542 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
543 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
544 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
545 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
546 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
547 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
548 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
549 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
550 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
551 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
552 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
553 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
554 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
555 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
556 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
557 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
558 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
559 STAM_REG(pVM, &pVM->vmm.s.StatGCRetHyperAssertion, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/HyperAssert", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
560 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
561 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
562 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
563 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
564
565 return VINF_SUCCESS;
566 }
567 AssertRC(rc);
568 }
569 }
570 /** @todo: Need failure cleanup. */
571
572 //more todo in here?
573 //if (VBOX_SUCCESS(rc))
574 //{
575 //}
576 //int rc2 = vmmR3TermCoreCode(pVM);
577 //AssertRC(rc2));
578 }
579
580 return rc;
581}
582
583
584/**
585 * Ring-3 init finalizing.
586 *
587 * @returns VBox status code.
588 * @param pVM The VM handle.
589 */
590VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
591{
592#ifdef VBOX_STRICT_VMM_STACK
593 /*
594 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
595 */
596 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
597 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
598 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
599
600 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
601 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
602 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
603#endif
604
605 /*
606 * Set page attributes to r/w for stack pages.
607 */
608 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
609 AssertRC(rc);
610 if (VBOX_SUCCESS(rc))
611 {
612 /*
613 * Create the EMT yield timer.
614 */
615 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
616 if (VBOX_SUCCESS(rc))
617 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
618 }
619#ifdef VBOX_WITH_NMI
620 /*
621 * Map the host APIC into GC - This may be host os specific!
622 */
623 if (VBOX_SUCCESS(rc))
624 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
625 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
626#endif
627 return rc;
628}
629
630
631/**
632 * Initializes the R0 VMM.
633 *
634 * @returns VBox status code.
635 * @param pVM The VM to operate on.
636 */
637VMMR3DECL(int) VMMR3InitR0(PVM pVM)
638{
639 int rc;
640
641 /*
642 * Initialize the ring-0 logger if we haven't done so yet.
643 */
644 if ( pVM->vmm.s.pR0Logger
645 && !pVM->vmm.s.pR0Logger->fCreated)
646 {
647 rc = VMMR3UpdateLoggers(pVM);
648 if (VBOX_FAILURE(rc))
649 return rc;
650 }
651
652 /*
653 * Call Ring-0 entry with init code.
654 */
655 for (;;)
656 {
657#ifdef NO_SUPCALLR0VMM
658 //rc = VERR_GENERAL_FAILURE;
659 rc = VINF_SUCCESS;
660#else
661 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, VMMGetSvnRev(), NULL);
662#endif
663 if ( pVM->vmm.s.pR0Logger
664 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
665 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
666 if (rc != VINF_VMM_CALL_HOST)
667 break;
668 rc = vmmR3ServiceCallHostRequest(pVM);
669 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
670 break;
671 /* Resume R0 */
672 }
673
674 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
675 {
676 LogRel(("R0 init failed, rc=%Vra\n", rc));
677 if (VBOX_SUCCESS(rc))
678 rc = VERR_INTERNAL_ERROR;
679 }
680 return rc;
681}
682
683
684/**
685 * Initializes the GC VMM.
686 *
687 * @returns VBox status code.
688 * @param pVM The VM to operate on.
689 */
690VMMR3DECL(int) VMMR3InitGC(PVM pVM)
691{
692 /* In VMX mode, there's no need to init GC. */
693 if (pVM->vmm.s.fSwitcherDisabled)
694 return VINF_SUCCESS;
695
696 /*
697 * Call VMMGCInit():
698 * -# resolve the address.
699 * -# setup stackframe and EIP to use the trampoline.
700 * -# do a generic hypervisor call.
701 */
702 RTGCPTR32 GCPtrEP;
703 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
704 if (VBOX_SUCCESS(rc))
705 {
706 CPUMHyperSetCtxCore(pVM, NULL);
707 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
708 uint64_t u64TS = RTTimeProgramStartNanoTS();
709 CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
710 CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
711 CPUMPushHyper(pVM, VMMGetSvnRev()); /* Param 2: Version argument. */
712 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
713 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
714 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR32)); /* trampoline param: stacksize. */
715 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
716 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
717
718 for (;;)
719 {
720#ifdef NO_SUPCALLR0VMM
721 //rc = VERR_GENERAL_FAILURE;
722 rc = VINF_SUCCESS;
723#else
724 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
725#endif
726#ifdef LOG_ENABLED
727 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
728 if ( pLogger
729 && pLogger->offScratch > 0)
730 RTLogFlushGC(NULL, pLogger);
731#endif
732#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
733 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
734 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
735 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
736#endif
737 if (rc != VINF_VMM_CALL_HOST)
738 break;
739 rc = vmmR3ServiceCallHostRequest(pVM);
740 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
741 break;
742 }
743
744 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
745 {
746 VMMR3FatalDump(pVM, rc);
747 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
748 rc = VERR_INTERNAL_ERROR;
749 }
750 AssertRC(rc);
751 }
752 return rc;
753}
754
755
756/**
757 * Terminate the VMM bits.
758 *
759 * @returns VINF_SUCCESS.
760 * @param pVM The VM handle.
761 */
762VMMR3DECL(int) VMMR3Term(PVM pVM)
763{
764 /*
765 * Call Ring-0 entry with termination code.
766 */
767 int rc;
768 for (;;)
769 {
770#ifdef NO_SUPCALLR0VMM
771 //rc = VERR_GENERAL_FAILURE;
772 rc = VINF_SUCCESS;
773#else
774 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_TERM, 0, NULL);
775#endif
776 if ( pVM->vmm.s.pR0Logger
777 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
778 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
779 if (rc != VINF_VMM_CALL_HOST)
780 break;
781 rc = vmmR3ServiceCallHostRequest(pVM);
782 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
783 break;
784 /* Resume R0 */
785 }
786 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
787 {
788 LogRel(("VMMR3Term: R0 term failed, rc=%Vra. (warning)\n", rc));
789 if (VBOX_SUCCESS(rc))
790 rc = VERR_INTERNAL_ERROR;
791 }
792
793#ifdef VBOX_STRICT_VMM_STACK
794 /*
795 * Make the two stack guard pages present again.
796 */
797 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
798 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
799#endif
800 return rc;
801}
802
803
804/**
805 * Applies relocations to data and code managed by this
806 * component. This function will be called at init and
807 * whenever the VMM need to relocate it self inside the GC.
808 *
809 * The VMM will need to apply relocations to the core code.
810 *
811 * @param pVM The VM handle.
812 * @param offDelta The relocation delta.
813 */
814VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
815{
816 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
817
818 /*
819 * Recalc the GC address.
820 */
821 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
822
823 /*
824 * The stack.
825 */
826 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
827 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
828 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
829
830 /*
831 * All the switchers.
832 */
833 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
834 {
835 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
836 if (pSwitcher && pSwitcher->pfnRelocate)
837 {
838 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
839 pSwitcher->pfnRelocate(pVM,
840 pSwitcher,
841 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
842 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
843 pVM->vmm.s.pvGCCoreCode + off,
844 pVM->vmm.s.HCPhysCoreCode + off);
845 }
846 }
847
848 /*
849 * Recalc the GC address for the current switcher.
850 */
851 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
852 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
853 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
854 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
855 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
856 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
857 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
858
859 /*
860 * Get other GC entry points.
861 */
862 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
863 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
864
865 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
866 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
867
868 /*
869 * Update the logger.
870 */
871 VMMR3UpdateLoggers(pVM);
872}
873
874
875/**
876 * Updates the settings for the GC and R0 loggers.
877 *
878 * @returns VBox status code.
879 * @param pVM The VM handle.
880 */
881VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
882{
883 /*
884 * Simply clone the logger instance (for GC).
885 */
886 int rc = VINF_SUCCESS;
887 RTGCPTR32 GCPtrLoggerFlush = 0;
888
889 if (pVM->vmm.s.pLoggerHC
890#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
891 || pVM->vmm.s.pRelLoggerHC
892#endif
893 )
894 {
895 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
896 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
897 }
898
899 if (pVM->vmm.s.pLoggerHC)
900 {
901 RTGCPTR32 GCPtrLoggerWrapper = 0;
902 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
903 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
904 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
905 rc = RTLogCloneRC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
906 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
907 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
908 }
909
910#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
911 if (pVM->vmm.s.pRelLoggerHC)
912 {
913 RTGCPTR32 GCPtrLoggerWrapper = 0;
914 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
915 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
916 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
917 rc = RTLogCloneRC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
918 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
919 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
920 }
921#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
922
923 /*
924 * For the ring-0 EMT logger, we use a per-thread logger
925 * instance in ring-0. Only initialize it once.
926 */
927 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
928 if (pR0Logger)
929 {
930 if (!pR0Logger->fCreated)
931 {
932 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
933 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
934 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
935
936 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
937 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
938 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
939
940 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
941 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
942 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
943 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
944 pR0Logger->fCreated = true;
945 }
946
947 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, pVM->vmm.s.pLoggerHC->fFlags, RTLOGFLAGS_BUFFERED);
948 AssertRC(rc);
949 }
950
951 return rc;
952}
953
954
955/**
956 * Generic switch code relocator.
957 *
958 * @param pVM The VM handle.
959 * @param pSwitcher The switcher definition.
960 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
961 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
962 * @param GCPtrCode The guest context address corresponding to pu8Code.
963 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
964 * @param SelCS The hypervisor CS selector.
965 * @param SelDS The hypervisor DS selector.
966 * @param SelTSS The hypervisor TSS selector.
967 * @param GCPtrGDT The GC address of the hypervisor GDT.
968 * @param SelCS64 The 64-bit mode hypervisor CS selector.
969 */
970static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
971 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
972{
973 union
974 {
975 const uint8_t *pu8;
976 const uint16_t *pu16;
977 const uint32_t *pu32;
978 const uint64_t *pu64;
979 const void *pv;
980 uintptr_t u;
981 } u;
982 u.pv = pSwitcher->pvFixups;
983
984 /*
985 * Process fixups.
986 */
987 uint8_t u8;
988 while ((u8 = *u.pu8++) != FIX_THE_END)
989 {
990 /*
991 * Get the source (where to write the fixup).
992 */
993 uint32_t offSrc = *u.pu32++;
994 Assert(offSrc < pSwitcher->cbCode);
995 union
996 {
997 uint8_t *pu8;
998 uint16_t *pu16;
999 uint32_t *pu32;
1000 uint64_t *pu64;
1001 uintptr_t u;
1002 } uSrc;
1003 uSrc.pu8 = pu8CodeR3 + offSrc;
1004
1005 /* The fixup target and method depends on the type. */
1006 switch (u8)
1007 {
1008 /*
1009 * 32-bit relative, source in HC and target in GC.
1010 */
1011 case FIX_HC_2_GC_NEAR_REL:
1012 {
1013 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1014 uint32_t offTrg = *u.pu32++;
1015 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1016 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
1017 break;
1018 }
1019
1020 /*
1021 * 32-bit relative, source in HC and target in ID.
1022 */
1023 case FIX_HC_2_ID_NEAR_REL:
1024 {
1025 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1026 uint32_t offTrg = *u.pu32++;
1027 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1028 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - ((uintptr_t)pu8CodeR0 + offSrc + 4));
1029 break;
1030 }
1031
1032 /*
1033 * 32-bit relative, source in GC and target in HC.
1034 */
1035 case FIX_GC_2_HC_NEAR_REL:
1036 {
1037 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1038 uint32_t offTrg = *u.pu32++;
1039 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1040 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
1041 break;
1042 }
1043
1044 /*
1045 * 32-bit relative, source in GC and target in ID.
1046 */
1047 case FIX_GC_2_ID_NEAR_REL:
1048 {
1049 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1050 uint32_t offTrg = *u.pu32++;
1051 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1052 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1053 break;
1054 }
1055
1056 /*
1057 * 32-bit relative, source in ID and target in HC.
1058 */
1059 case FIX_ID_2_HC_NEAR_REL:
1060 {
1061 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1062 uint32_t offTrg = *u.pu32++;
1063 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1064 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1065 break;
1066 }
1067
1068 /*
1069 * 32-bit relative, source in ID and target in HC.
1070 */
1071 case FIX_ID_2_GC_NEAR_REL:
1072 {
1073 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1074 uint32_t offTrg = *u.pu32++;
1075 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1076 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1077 break;
1078 }
1079
1080 /*
1081 * 16:32 far jump, target in GC.
1082 */
1083 case FIX_GC_FAR32:
1084 {
1085 uint32_t offTrg = *u.pu32++;
1086 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1087 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1088 *uSrc.pu16++ = SelCS;
1089 break;
1090 }
1091
1092 /*
1093 * Make 32-bit GC pointer given CPUM offset.
1094 */
1095 case FIX_GC_CPUM_OFF:
1096 {
1097 uint32_t offCPUM = *u.pu32++;
1098 Assert(offCPUM < sizeof(pVM->cpum));
1099 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1100 break;
1101 }
1102
1103 /*
1104 * Make 32-bit GC pointer given VM offset.
1105 */
1106 case FIX_GC_VM_OFF:
1107 {
1108 uint32_t offVM = *u.pu32++;
1109 Assert(offVM < sizeof(VM));
1110 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1111 break;
1112 }
1113
1114 /*
1115 * Make 32-bit HC pointer given CPUM offset.
1116 */
1117 case FIX_HC_CPUM_OFF:
1118 {
1119 uint32_t offCPUM = *u.pu32++;
1120 Assert(offCPUM < sizeof(pVM->cpum));
1121 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1122 break;
1123 }
1124
1125 /*
1126 * Make 32-bit R0 pointer given VM offset.
1127 */
1128 case FIX_HC_VM_OFF:
1129 {
1130 uint32_t offVM = *u.pu32++;
1131 Assert(offVM < sizeof(VM));
1132 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1133 break;
1134 }
1135
1136 /*
1137 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1138 */
1139 case FIX_INTER_32BIT_CR3:
1140 {
1141
1142 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1143 break;
1144 }
1145
1146 /*
1147 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1148 */
1149 case FIX_INTER_PAE_CR3:
1150 {
1151
1152 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1153 break;
1154 }
1155
1156 /*
1157 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1158 */
1159 case FIX_INTER_AMD64_CR3:
1160 {
1161
1162 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1163 break;
1164 }
1165
1166 /*
1167 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1168 */
1169 case FIX_HYPER_32BIT_CR3:
1170 {
1171
1172 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1173 break;
1174 }
1175
1176 /*
1177 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1178 */
1179 case FIX_HYPER_PAE_CR3:
1180 {
1181
1182 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1183 break;
1184 }
1185
1186 /*
1187 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1188 */
1189 case FIX_HYPER_AMD64_CR3:
1190 {
1191
1192 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1193 break;
1194 }
1195
1196 /*
1197 * Store Hypervisor CS (16-bit).
1198 */
1199 case FIX_HYPER_CS:
1200 {
1201 *uSrc.pu16 = SelCS;
1202 break;
1203 }
1204
1205 /*
1206 * Store Hypervisor DS (16-bit).
1207 */
1208 case FIX_HYPER_DS:
1209 {
1210 *uSrc.pu16 = SelDS;
1211 break;
1212 }
1213
1214 /*
1215 * Store Hypervisor TSS (16-bit).
1216 */
1217 case FIX_HYPER_TSS:
1218 {
1219 *uSrc.pu16 = SelTSS;
1220 break;
1221 }
1222
1223 /*
1224 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1225 */
1226 case FIX_GC_TSS_GDTE_DW2:
1227 {
1228 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1229 *uSrc.pu32 = (uint32_t)GCPtr;
1230 break;
1231 }
1232
1233
1234 ///@todo case FIX_CR4_MASK:
1235 ///@todo case FIX_CR4_OSFSXR:
1236
1237 /*
1238 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1239 */
1240 case FIX_NO_FXSAVE_JMP:
1241 {
1242 uint32_t offTrg = *u.pu32++;
1243 Assert(offTrg < pSwitcher->cbCode);
1244 if (!CPUMSupportsFXSR(pVM))
1245 {
1246 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1247 *uSrc.pu32++ = offTrg - (offSrc + 5);
1248 }
1249 else
1250 {
1251 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1252 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1253 }
1254 break;
1255 }
1256
1257 /*
1258 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1259 */
1260 case FIX_NO_SYSENTER_JMP:
1261 {
1262 uint32_t offTrg = *u.pu32++;
1263 Assert(offTrg < pSwitcher->cbCode);
1264 if (!CPUMIsHostUsingSysEnter(pVM))
1265 {
1266 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1267 *uSrc.pu32++ = offTrg - (offSrc + 5);
1268 }
1269 else
1270 {
1271 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1272 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1273 }
1274 break;
1275 }
1276
1277 /*
1278 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1279 */
1280 case FIX_NO_SYSCALL_JMP:
1281 {
1282 uint32_t offTrg = *u.pu32++;
1283 Assert(offTrg < pSwitcher->cbCode);
1284 if (!CPUMIsHostUsingSysEnter(pVM))
1285 {
1286 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1287 *uSrc.pu32++ = offTrg - (offSrc + 5);
1288 }
1289 else
1290 {
1291 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1292 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1293 }
1294 break;
1295 }
1296
1297 /*
1298 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1299 */
1300 case FIX_HC_32BIT:
1301 {
1302 uint32_t offTrg = *u.pu32++;
1303 Assert(offSrc < pSwitcher->cbCode);
1304 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1305 *uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1306 break;
1307 }
1308
1309#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1310 /*
1311 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1312 */
1313 case FIX_HC_64BIT:
1314 {
1315 uint32_t offTrg = *u.pu32++;
1316 Assert(offSrc < pSwitcher->cbCode);
1317 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1318 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1319 break;
1320 }
1321
1322 /*
1323 * 64-bit HC Code Selector (no argument).
1324 */
1325 case FIX_HC_64BIT_CS:
1326 {
1327 Assert(offSrc < pSwitcher->cbCode);
1328#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1329 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1330#else
1331 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1332#endif
1333 break;
1334 }
1335
1336 /*
1337 * 64-bit HC pointer to the CPUM instance data (no argument).
1338 */
1339 case FIX_HC_64BIT_CPUM:
1340 {
1341 Assert(offSrc < pSwitcher->cbCode);
1342 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1343 break;
1344 }
1345#endif
1346
1347 /*
1348 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1349 */
1350 case FIX_ID_32BIT:
1351 {
1352 uint32_t offTrg = *u.pu32++;
1353 Assert(offSrc < pSwitcher->cbCode);
1354 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1355 *uSrc.pu32 = u32IDCode + offTrg;
1356 break;
1357 }
1358
1359 /*
1360 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1361 */
1362 case FIX_ID_64BIT:
1363 {
1364 uint32_t offTrg = *u.pu32++;
1365 Assert(offSrc < pSwitcher->cbCode);
1366 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1367 *uSrc.pu64 = u32IDCode + offTrg;
1368 break;
1369 }
1370
1371 /*
1372 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1373 */
1374 case FIX_ID_FAR32_TO_64BIT_MODE:
1375 {
1376 uint32_t offTrg = *u.pu32++;
1377 Assert(offSrc < pSwitcher->cbCode);
1378 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1379 *uSrc.pu32++ = u32IDCode + offTrg;
1380 *uSrc.pu16 = SelCS64;
1381 AssertRelease(SelCS64);
1382 break;
1383 }
1384
1385#ifdef VBOX_WITH_NMI
1386 /*
1387 * 32-bit address to the APIC base.
1388 */
1389 case FIX_GC_APIC_BASE_32BIT:
1390 {
1391 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1392 break;
1393 }
1394#endif
1395
1396 default:
1397 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1398 break;
1399 }
1400 }
1401
1402#ifdef LOG_ENABLED
1403 /*
1404 * If Log2 is enabled disassemble the switcher code.
1405 *
1406 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1407 */
1408 if (LogIs2Enabled())
1409 {
1410 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1411 " pu8CodeR0 = %p\n"
1412 " pu8CodeR3 = %p\n"
1413 " GCPtrCode = %VGv\n"
1414 " u32IDCode = %08x\n"
1415 " pVMGC = %VGv\n"
1416 " pCPUMGC = %VGv\n"
1417 " pVMHC = %p\n"
1418 " pCPUMHC = %p\n"
1419 " GCPtrGDT = %VGv\n"
1420 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1421 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1422 " SelCS = %04x\n"
1423 " SelDS = %04x\n"
1424 " SelCS64 = %04x\n"
1425 " SelTSS = %04x\n",
1426 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1427 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1428 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1429 GCPtrGDT,
1430 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1431 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1432 SelCS, SelDS, SelCS64, SelTSS);
1433
1434 uint32_t offCode = 0;
1435 while (offCode < pSwitcher->cbCode)
1436 {
1437 /*
1438 * Figure out where this is.
1439 */
1440 const char *pszDesc = NULL;
1441 RTUINTPTR uBase;
1442 uint32_t cbCode;
1443 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1444 {
1445 pszDesc = "HCCode0";
1446 uBase = (RTUINTPTR)pu8CodeR0;
1447 offCode = pSwitcher->offHCCode0;
1448 cbCode = pSwitcher->cbHCCode0;
1449 }
1450 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1451 {
1452 pszDesc = "HCCode1";
1453 uBase = (RTUINTPTR)pu8CodeR0;
1454 offCode = pSwitcher->offHCCode1;
1455 cbCode = pSwitcher->cbHCCode1;
1456 }
1457 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1458 {
1459 pszDesc = "GCCode";
1460 uBase = GCPtrCode;
1461 offCode = pSwitcher->offGCCode;
1462 cbCode = pSwitcher->cbGCCode;
1463 }
1464 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1465 {
1466 pszDesc = "IDCode0";
1467 uBase = u32IDCode;
1468 offCode = pSwitcher->offIDCode0;
1469 cbCode = pSwitcher->cbIDCode0;
1470 }
1471 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1472 {
1473 pszDesc = "IDCode1";
1474 uBase = u32IDCode;
1475 offCode = pSwitcher->offIDCode1;
1476 cbCode = pSwitcher->cbIDCode1;
1477 }
1478 else
1479 {
1480 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1481 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1482 offCode++;
1483 continue;
1484 }
1485
1486 /*
1487 * Disassemble it.
1488 */
1489 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1490 DISCPUSTATE Cpu;
1491
1492 memset(&Cpu, 0, sizeof(Cpu));
1493 Cpu.mode = CPUMODE_32BIT;
1494 while (cbCode > 0)
1495 {
1496 /* try label it */
1497 if (pSwitcher->offR0HostToGuest == offCode)
1498 RTLogPrintf(" *R0HostToGuest:\n");
1499 if (pSwitcher->offGCGuestToHost == offCode)
1500 RTLogPrintf(" *GCGuestToHost:\n");
1501 if (pSwitcher->offGCCallTrampoline == offCode)
1502 RTLogPrintf(" *GCCallTrampoline:\n");
1503 if (pSwitcher->offGCGuestToHostAsm == offCode)
1504 RTLogPrintf(" *GCGuestToHostAsm:\n");
1505 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1506 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1507 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1508 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1509
1510 /* disas */
1511 uint32_t cbInstr = 0;
1512 char szDisas[256];
1513 if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
1514 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1515 else
1516 {
1517 RTLogPrintf(" %04x: %02x '%c'\n",
1518 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1519 cbInstr = 1;
1520 }
1521 offCode += cbInstr;
1522 cbCode -= RT_MIN(cbInstr, cbCode);
1523 }
1524 }
1525 }
1526#endif
1527}
1528
1529
1530/**
1531 * Relocator for the 32-Bit to 32-Bit world switcher.
1532 */
1533DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1534{
1535 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1536 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1537}
1538
1539
1540/**
1541 * Relocator for the 32-Bit to PAE world switcher.
1542 */
1543DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1544{
1545 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1546 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1547}
1548
1549
1550/**
1551 * Relocator for the PAE to 32-Bit world switcher.
1552 */
1553DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1554{
1555 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1556 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1557}
1558
1559
1560/**
1561 * Relocator for the PAE to PAE world switcher.
1562 */
1563DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1564{
1565 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1566 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1567}
1568
1569
1570/**
1571 * Relocator for the AMD64 to PAE world switcher.
1572 */
1573DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1574{
1575 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1576 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1577}
1578
1579
1580/**
1581 * Gets the pointer to g_szRTAssertMsg1 in GC.
1582 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1583 * Returns NULL if not present.
1584 * @param pVM The VM handle.
1585 */
1586VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1587{
1588 RTGCPTR32 GCPtr;
1589 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1590 if (VBOX_SUCCESS(rc))
1591 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1592 return NULL;
1593}
1594
1595
1596/**
1597 * Gets the pointer to g_szRTAssertMsg2 in GC.
1598 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1599 * Returns NULL if not present.
1600 * @param pVM The VM handle.
1601 */
1602VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1603{
1604 RTGCPTR32 GCPtr;
1605 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1606 if (VBOX_SUCCESS(rc))
1607 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1608 return NULL;
1609}
1610
1611
1612/**
1613 * Execute state save operation.
1614 *
1615 * @returns VBox status code.
1616 * @param pVM VM Handle.
1617 * @param pSSM SSM operation handle.
1618 */
1619static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1620{
1621 LogFlow(("vmmR3Save:\n"));
1622
1623 /*
1624 * The hypervisor stack.
1625 */
1626 SSMR3PutRCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1627 RTRCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1628 AssertMsg(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE, ("Bottom %VGv ESP=%VGv\n", pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1629 SSMR3PutRCPtr(pSSM, GCPtrESP);
1630 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1631 return SSMR3PutU32(pSSM, ~0); /* terminator */
1632}
1633
1634
1635/**
1636 * Execute state load operation.
1637 *
1638 * @returns VBox status code.
1639 * @param pVM VM Handle.
1640 * @param pSSM SSM operation handle.
1641 * @param u32Version Data layout version.
1642 */
1643static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1644{
1645 LogFlow(("vmmR3Load:\n"));
1646
1647 /*
1648 * Validate version.
1649 */
1650 if (u32Version != VMM_SAVED_STATE_VERSION)
1651 {
1652 AssertMsgFailed(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1653 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1654 }
1655
1656 /*
1657 * Check that the stack is in the same place, or that it's fearly empty.
1658 */
1659 RTRCPTR GCPtrStackBottom;
1660 SSMR3GetRCPtr(pSSM, &GCPtrStackBottom);
1661 RTRCPTR GCPtrESP;
1662 int rc = SSMR3GetRCPtr(pSSM, &GCPtrESP);
1663 if (VBOX_FAILURE(rc))
1664 return rc;
1665
1666 /* Previously we checked if the location of the stack was identical or that the stack was empty.
1667 * This is not required as we can never initiate a save when GC context code performs a ring 3 call.
1668 */
1669 /* restore the stack. (not necessary; just consistency checking) */
1670 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1671
1672 /* terminator */
1673 uint32_t u32;
1674 rc = SSMR3GetU32(pSSM, &u32);
1675 if (VBOX_FAILURE(rc))
1676 return rc;
1677 if (u32 != ~0U)
1678 {
1679 AssertMsgFailed(("u32=%#x\n", u32));
1680 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1681 }
1682 return VINF_SUCCESS;
1683}
1684
1685
1686/**
1687 * Selects the switcher to be used for switching to GC.
1688 *
1689 * @returns VBox status code.
1690 * @param pVM VM handle.
1691 * @param enmSwitcher The new switcher.
1692 * @remark This function may be called before the VMM is initialized.
1693 */
1694VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1695{
1696 /*
1697 * Validate input.
1698 */
1699 if ( enmSwitcher < VMMSWITCHER_INVALID
1700 || enmSwitcher >= VMMSWITCHER_MAX)
1701 {
1702 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1703 return VERR_INVALID_PARAMETER;
1704 }
1705
1706 /* Do nothing if the switcher is disabled. */
1707 if (pVM->vmm.s.fSwitcherDisabled)
1708 return VINF_SUCCESS;
1709
1710 /*
1711 * Select the new switcher.
1712 */
1713 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1714 if (pSwitcher)
1715 {
1716 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1717 pVM->vmm.s.enmSwitcher = enmSwitcher;
1718
1719 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1720 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1721
1722 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1723 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1724 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1725 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1726 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1727 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1728 return VINF_SUCCESS;
1729 }
1730 return VERR_NOT_IMPLEMENTED;
1731}
1732
1733/**
1734 * Disable the switcher logic permanently.
1735 *
1736 * @returns VBox status code.
1737 * @param pVM VM handle.
1738 */
1739VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1740{
1741/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1742 * @code
1743 * mov eax, VERR_INTERNAL_ERROR
1744 * ret
1745 * @endcode
1746 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1747 */
1748 pVM->vmm.s.fSwitcherDisabled = true;
1749 return VINF_SUCCESS;
1750}
1751
1752
1753/**
1754 * Resolve a builtin GC symbol.
1755 * Called by PDM when loading or relocating GC modules.
1756 *
1757 * @returns VBox status
1758 * @param pVM VM Handle.
1759 * @param pszSymbol Symbol to resolv
1760 * @param pGCPtrValue Where to store the symbol value.
1761 * @remark This has to work before VMMR3Relocate() is called.
1762 */
1763VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1764{
1765 if (!strcmp(pszSymbol, "g_Logger"))
1766 {
1767 if (pVM->vmm.s.pLoggerHC)
1768 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1769 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1770 }
1771 else if (!strcmp(pszSymbol, "g_RelLogger"))
1772 {
1773#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1774 if (pVM->vmm.s.pRelLoggerHC)
1775 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1776 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1777#else
1778 *pGCPtrValue = NIL_RTGCPTR;
1779#endif
1780 }
1781 else
1782 return VERR_SYMBOL_NOT_FOUND;
1783 return VINF_SUCCESS;
1784}
1785
1786
1787/**
1788 * Suspends the the CPU yielder.
1789 *
1790 * @param pVM The VM handle.
1791 */
1792VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1793{
1794 if (!pVM->vmm.s.cYieldResumeMillies)
1795 {
1796 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1797 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1798 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1799 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1800 else
1801 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1802 TMTimerStop(pVM->vmm.s.pYieldTimer);
1803 }
1804 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1805}
1806
1807
1808/**
1809 * Stops the the CPU yielder.
1810 *
1811 * @param pVM The VM handle.
1812 */
1813VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1814{
1815 if (!pVM->vmm.s.cYieldResumeMillies)
1816 TMTimerStop(pVM->vmm.s.pYieldTimer);
1817 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1818 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1819}
1820
1821
1822/**
1823 * Resumes the CPU yielder when it has been a suspended or stopped.
1824 *
1825 * @param pVM The VM handle.
1826 */
1827VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1828{
1829 if (pVM->vmm.s.cYieldResumeMillies)
1830 {
1831 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1832 pVM->vmm.s.cYieldResumeMillies = 0;
1833 }
1834}
1835
1836
1837/**
1838 * Internal timer callback function.
1839 *
1840 * @param pVM The VM.
1841 * @param pTimer The timer handle.
1842 * @param pvUser User argument specified upon timer creation.
1843 */
1844static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1845{
1846 /*
1847 * This really needs some careful tuning. While we shouldn't be too gready since
1848 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1849 * because that'll cause us to stop up.
1850 *
1851 * The current logic is to use the default interval when there is no lag worth
1852 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1853 *
1854 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1855 * so the lag is up to date.)
1856 */
1857 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1858 if ( u64Lag < 50000000 /* 50ms */
1859 || ( u64Lag < 1000000000 /* 1s */
1860 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1861 )
1862 {
1863 uint64_t u64Elapsed = RTTimeNanoTS();
1864 pVM->vmm.s.u64LastYield = u64Elapsed;
1865
1866 RTThreadYield();
1867
1868#ifdef LOG_ENABLED
1869 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1870 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1871#endif
1872 }
1873 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1874}
1875
1876
1877/**
1878 * Acquire global VM lock.
1879 *
1880 * @returns VBox status code
1881 * @param pVM The VM to operate on.
1882 */
1883VMMR3DECL(int) VMMR3Lock(PVM pVM)
1884{
1885 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1886}
1887
1888
1889/**
1890 * Release global VM lock.
1891 *
1892 * @returns VBox status code
1893 * @param pVM The VM to operate on.
1894 */
1895VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1896{
1897 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1898}
1899
1900
1901/**
1902 * Return global VM lock owner.
1903 *
1904 * @returns Thread id of owner.
1905 * @returns NIL_RTTHREAD if no owner.
1906 * @param pVM The VM to operate on.
1907 */
1908VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1909{
1910 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1911}
1912
1913
1914/**
1915 * Checks if the current thread is the owner of the global VM lock.
1916 *
1917 * @returns true if owner.
1918 * @returns false if not owner.
1919 * @param pVM The VM to operate on.
1920 */
1921VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1922{
1923 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1924}
1925
1926
1927/**
1928 * Executes guest code.
1929 *
1930 * @param pVM VM handle.
1931 */
1932VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1933{
1934 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1935
1936 /*
1937 * Set the EIP and ESP.
1938 */
1939 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1940 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1941 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1942 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1943
1944 /*
1945 * We hide log flushes (outer) and hypervisor interrupts (inner).
1946 */
1947 for (;;)
1948 {
1949 int rc;
1950 do
1951 {
1952#ifdef NO_SUPCALLR0VMM
1953 rc = VERR_GENERAL_FAILURE;
1954#else
1955 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
1956 if (RT_LIKELY(rc == VINF_SUCCESS))
1957 rc = pVM->vmm.s.iLastGCRc;
1958#endif
1959 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1960
1961 /*
1962 * Flush the logs.
1963 */
1964#ifdef LOG_ENABLED
1965 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
1966 if ( pLogger
1967 && pLogger->offScratch > 0)
1968 RTLogFlushGC(NULL, pLogger);
1969#endif
1970#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1971 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1972 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1973 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1974#endif
1975 if (rc != VINF_VMM_CALL_HOST)
1976 {
1977 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1978 return rc;
1979 }
1980 rc = vmmR3ServiceCallHostRequest(pVM);
1981 if (VBOX_FAILURE(rc))
1982 return rc;
1983 /* Resume GC */
1984 }
1985}
1986
1987
1988/**
1989 * Executes guest code (Intel VT-x and AMD-V).
1990 *
1991 * @param pVM VM handle.
1992 */
1993VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1994{
1995 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1996
1997 for (;;)
1998 {
1999 int rc;
2000 do
2001 {
2002#ifdef NO_SUPCALLR0VMM
2003 rc = VERR_GENERAL_FAILURE;
2004#else
2005 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN);
2006 if (RT_LIKELY(rc == VINF_SUCCESS))
2007 rc = pVM->vmm.s.iLastGCRc;
2008#endif
2009 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2010
2011#ifdef LOG_ENABLED
2012 /*
2013 * Flush the log
2014 */
2015 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
2016 if ( pR0Logger
2017 && pR0Logger->Logger.offScratch > 0)
2018 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
2019#endif /* !LOG_ENABLED */
2020 if (rc != VINF_VMM_CALL_HOST)
2021 {
2022 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2023 return rc;
2024 }
2025 rc = vmmR3ServiceCallHostRequest(pVM);
2026 if (VBOX_FAILURE(rc) || rc == VINF_EM_DBG_HYPER_ASSERTION)
2027 return rc;
2028 /* Resume R0 */
2029 }
2030}
2031
2032/**
2033 * Calls GC a function.
2034 *
2035 * @param pVM The VM handle.
2036 * @param GCPtrEntry The GC function address.
2037 * @param cArgs The number of arguments in the ....
2038 * @param ... Arguments to the function.
2039 */
2040VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, ...)
2041{
2042 va_list args;
2043 va_start(args, cArgs);
2044 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2045 va_end(args);
2046 return rc;
2047}
2048
2049
2050/**
2051 * Calls GC a function.
2052 *
2053 * @param pVM The VM handle.
2054 * @param GCPtrEntry The GC function address.
2055 * @param cArgs The number of arguments in the ....
2056 * @param args Arguments to the function.
2057 */
2058VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, va_list args)
2059{
2060 Log2(("VMMR3CallGCV: GCPtrEntry=%VRv cArgs=%d\n", GCPtrEntry, cArgs));
2061
2062 /*
2063 * Setup the call frame using the trampoline.
2064 */
2065 CPUMHyperSetCtxCore(pVM, NULL);
2066 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2067 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR32));
2068 PRTGCUINTPTR32 pFrame = (PRTGCUINTPTR32)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2069 int i = cArgs;
2070 while (i-- > 0)
2071 *pFrame++ = va_arg(args, RTGCUINTPTR32);
2072
2073 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR32)); /* stack frame size */
2074 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2075 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2076
2077 /*
2078 * We hide log flushes (outer) and hypervisor interrupts (inner).
2079 */
2080 for (;;)
2081 {
2082 int rc;
2083 do
2084 {
2085#ifdef NO_SUPCALLR0VMM
2086 rc = VERR_GENERAL_FAILURE;
2087#else
2088 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2089 if (RT_LIKELY(rc == VINF_SUCCESS))
2090 rc = pVM->vmm.s.iLastGCRc;
2091#endif
2092 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2093
2094 /*
2095 * Flush the logs.
2096 */
2097#ifdef LOG_ENABLED
2098 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
2099 if ( pLogger
2100 && pLogger->offScratch > 0)
2101 RTLogFlushGC(NULL, pLogger);
2102#endif
2103#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2104 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2105 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2106 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2107#endif
2108 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2109 VMMR3FatalDump(pVM, rc);
2110 if (rc != VINF_VMM_CALL_HOST)
2111 {
2112 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2113 return rc;
2114 }
2115 rc = vmmR3ServiceCallHostRequest(pVM);
2116 if (VBOX_FAILURE(rc))
2117 return rc;
2118 }
2119}
2120
2121
2122/**
2123 * Resumes executing hypervisor code when interrupted
2124 * by a queue flush or a debug event.
2125 *
2126 * @returns VBox status code.
2127 * @param pVM VM handle.
2128 */
2129VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2130{
2131 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2132
2133 /*
2134 * We hide log flushes (outer) and hypervisor interrupts (inner).
2135 */
2136 for (;;)
2137 {
2138 int rc;
2139 do
2140 {
2141#ifdef NO_SUPCALLR0VMM
2142 rc = VERR_GENERAL_FAILURE;
2143#else
2144 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2145 if (RT_LIKELY(rc == VINF_SUCCESS))
2146 rc = pVM->vmm.s.iLastGCRc;
2147#endif
2148 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2149
2150 /*
2151 * Flush the loggers,
2152 */
2153#ifdef LOG_ENABLED
2154 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
2155 if ( pLogger
2156 && pLogger->offScratch > 0)
2157 RTLogFlushGC(NULL, pLogger);
2158#endif
2159#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2160 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2161 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2162 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2163#endif
2164 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2165 VMMR3FatalDump(pVM, rc);
2166 if (rc != VINF_VMM_CALL_HOST)
2167 {
2168 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2169 return rc;
2170 }
2171 rc = vmmR3ServiceCallHostRequest(pVM);
2172 if (VBOX_FAILURE(rc))
2173 return rc;
2174 }
2175}
2176
2177
2178/**
2179 * Service a call to the ring-3 host code.
2180 *
2181 * @returns VBox status code.
2182 * @param pVM VM handle.
2183 * @remark Careful with critsects.
2184 */
2185static int vmmR3ServiceCallHostRequest(PVM pVM)
2186{
2187 switch (pVM->vmm.s.enmCallHostOperation)
2188 {
2189 /*
2190 * Acquire the PDM lock.
2191 */
2192 case VMMCALLHOST_PDM_LOCK:
2193 {
2194 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2195 break;
2196 }
2197
2198 /*
2199 * Flush a PDM queue.
2200 */
2201 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2202 {
2203 PDMR3QueueFlushWorker(pVM, NULL);
2204 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2205 break;
2206 }
2207
2208 /*
2209 * Grow the PGM pool.
2210 */
2211 case VMMCALLHOST_PGM_POOL_GROW:
2212 {
2213 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2214 break;
2215 }
2216
2217 /*
2218 * Maps an page allocation chunk into ring-3 so ring-0 can use it.
2219 */
2220 case VMMCALLHOST_PGM_MAP_CHUNK:
2221 {
2222 pVM->vmm.s.rcCallHost = PGMR3PhysChunkMap(pVM, pVM->vmm.s.u64CallHostArg);
2223 break;
2224 }
2225
2226 /*
2227 * Allocates more handy pages.
2228 */
2229 case VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES:
2230 {
2231 pVM->vmm.s.rcCallHost = PGMR3PhysAllocateHandyPages(pVM);
2232 break;
2233 }
2234#ifndef VBOX_WITH_NEW_PHYS_CODE
2235
2236 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2237 {
2238 const RTGCPHYS GCPhys = pVM->vmm.s.u64CallHostArg;
2239 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, &GCPhys);
2240 break;
2241 }
2242#endif
2243
2244 /*
2245 * Acquire the PGM lock.
2246 */
2247 case VMMCALLHOST_PGM_LOCK:
2248 {
2249 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2250 break;
2251 }
2252
2253 /*
2254 * Flush REM handler notifications.
2255 */
2256 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2257 {
2258 REMR3ReplayHandlerNotifications(pVM);
2259 break;
2260 }
2261
2262 /*
2263 * This is a noop. We just take this route to avoid unnecessary
2264 * tests in the loops.
2265 */
2266 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2267 break;
2268
2269 /*
2270 * Set the VM error message.
2271 */
2272 case VMMCALLHOST_VM_SET_ERROR:
2273 VMR3SetErrorWorker(pVM);
2274 break;
2275
2276 /*
2277 * Set the VM runtime error message.
2278 */
2279 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2280 VMR3SetRuntimeErrorWorker(pVM);
2281 break;
2282
2283 /*
2284 * Signal a ring 0 hypervisor assertion.
2285 * Cancel the longjmp operation that's in progress.
2286 */
2287 case VMMCALLHOST_VM_R0_HYPER_ASSERTION:
2288 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2289 pVM->vmm.s.CallHostR0JmpBuf.fInRing3Call = false;
2290#ifdef RT_ARCH_X86
2291 pVM->vmm.s.CallHostR0JmpBuf.eip = 0;
2292#else
2293 pVM->vmm.s.CallHostR0JmpBuf.rip = 0;
2294#endif
2295 LogRel((pVM->vmm.s.szRing0AssertMsg1));
2296 LogRel((pVM->vmm.s.szRing0AssertMsg2));
2297 return VINF_EM_DBG_HYPER_ASSERTION;
2298
2299 default:
2300 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2301 return VERR_INTERNAL_ERROR;
2302 }
2303
2304 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2305 return VINF_SUCCESS;
2306}
2307
2308
2309
2310/**
2311 * Structure to pass to DBGFR3Info() and for doing all other
2312 * output during fatal dump.
2313 */
2314typedef struct VMMR3FATALDUMPINFOHLP
2315{
2316 /** The helper core. */
2317 DBGFINFOHLP Core;
2318 /** The release logger instance. */
2319 PRTLOGGER pRelLogger;
2320 /** The saved release logger flags. */
2321 RTUINT fRelLoggerFlags;
2322 /** The logger instance. */
2323 PRTLOGGER pLogger;
2324 /** The saved logger flags. */
2325 RTUINT fLoggerFlags;
2326 /** The saved logger destination flags. */
2327 RTUINT fLoggerDestFlags;
2328 /** Whether to output to stderr or not. */
2329 bool fStdErr;
2330} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2331typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2332
2333
2334/**
2335 * Print formatted string.
2336 *
2337 * @param pHlp Pointer to this structure.
2338 * @param pszFormat The format string.
2339 * @param ... Arguments.
2340 */
2341static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2342{
2343 va_list args;
2344 va_start(args, pszFormat);
2345 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2346 va_end(args);
2347}
2348
2349
2350/**
2351 * Print formatted string.
2352 *
2353 * @param pHlp Pointer to this structure.
2354 * @param pszFormat The format string.
2355 * @param args Argument list.
2356 */
2357static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2358{
2359 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2360
2361 if (pMyHlp->pRelLogger)
2362 {
2363 va_list args2;
2364 va_copy(args2, args);
2365 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2366 va_end(args2);
2367 }
2368 if (pMyHlp->pLogger)
2369 {
2370 va_list args2;
2371 va_copy(args2, args);
2372 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2373 va_end(args2);
2374 }
2375 if (pMyHlp->fStdErr)
2376 {
2377 va_list args2;
2378 va_copy(args2, args);
2379 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2380 va_end(args2);
2381 }
2382}
2383
2384
2385/**
2386 * Initializes the fatal dump output helper.
2387 *
2388 * @param pHlp The structure to initialize.
2389 */
2390static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2391{
2392 memset(pHlp, 0, sizeof(*pHlp));
2393
2394 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2395 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2396
2397 /*
2398 * The loggers.
2399 */
2400 pHlp->pRelLogger = RTLogRelDefaultInstance();
2401#ifndef LOG_ENABLED
2402 if (!pHlp->pRelLogger)
2403#endif
2404 pHlp->pLogger = RTLogDefaultInstance();
2405
2406 if (pHlp->pRelLogger)
2407 {
2408 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2409 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2410 }
2411
2412 if (pHlp->pLogger)
2413 {
2414 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2415 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2416 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2417#ifndef DEBUG_sandervl
2418 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2419#endif
2420 }
2421
2422 /*
2423 * Check if we need write to stderr.
2424 */
2425#ifdef DEBUG_sandervl
2426 pHlp->fStdErr = false; /* takes too long to display here */
2427#else
2428 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2429 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2430#endif
2431}
2432
2433
2434/**
2435 * Deletes the fatal dump output helper.
2436 *
2437 * @param pHlp The structure to delete.
2438 */
2439static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2440{
2441 if (pHlp->pRelLogger)
2442 {
2443 RTLogFlush(pHlp->pRelLogger);
2444 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2445 }
2446
2447 if (pHlp->pLogger)
2448 {
2449 RTLogFlush(pHlp->pLogger);
2450 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2451 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2452 }
2453}
2454
2455
2456/**
2457 * Dumps the VM state on a fatal error.
2458 *
2459 * @param pVM VM Handle.
2460 * @param rcErr VBox status code.
2461 */
2462VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2463{
2464 /*
2465 * Create our output helper and sync it with the log settings.
2466 * This helper will be used for all the output.
2467 */
2468 VMMR3FATALDUMPINFOHLP Hlp;
2469 PCDBGFINFOHLP pHlp = &Hlp.Core;
2470 vmmR3FatalDumpInfoHlpInit(&Hlp);
2471
2472 /*
2473 * Header.
2474 */
2475 pHlp->pfnPrintf(pHlp,
2476 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2477 "!!\n"
2478 "!! Guru Meditation %d (%Vrc)\n"
2479 "!!\n",
2480 rcErr, rcErr);
2481
2482 /*
2483 * Continue according to context.
2484 */
2485 bool fDoneHyper = false;
2486 switch (rcErr)
2487 {
2488 /*
2489 * Hyper visor errors.
2490 */
2491 case VINF_EM_DBG_HYPER_ASSERTION:
2492 pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2493 /* fall thru */
2494 case VERR_TRPM_DONT_PANIC:
2495 case VERR_TRPM_PANIC:
2496 case VINF_EM_RAW_STALE_SELECTOR:
2497 case VINF_EM_RAW_IRET_TRAP:
2498 case VINF_EM_DBG_HYPER_BREAKPOINT:
2499 case VINF_EM_DBG_HYPER_STEPPED:
2500 {
2501 /* Trap? */
2502 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2503 TRPMEVENT enmType;
2504 uint8_t u8TrapNo = 0xce;
2505 RTGCUINT uErrorCode = 0xdeadface;
2506 RTGCUINTPTR uCR2 = 0xdeadface;
2507 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2508 if (VBOX_SUCCESS(rc2))
2509 pHlp->pfnPrintf(pHlp,
2510 "!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv Type=%d\n",
2511 u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2512 else
2513 pHlp->pfnPrintf(pHlp,
2514 "!! EIP=%VGv NOTRAP\n",
2515 uEIP);
2516
2517 /*
2518 * Try figure out where eip is.
2519 */
2520 /** @todo make query call for core code or move this function to VMM. */
2521 /* core code? */
2522 //if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2523 // pHlp->pfnPrintf(pHlp,
2524 // "!! EIP is in CoreCode, offset %#x\n",
2525 // uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2526 //else
2527 { /* ask PDM */
2528 /** @todo ask DBGFR3Sym later. */
2529 char szModName[64];
2530 RTGCPTR GCPtrMod;
2531 char szNearSym1[260];
2532 RTGCPTR GCPtrNearSym1;
2533 char szNearSym2[260];
2534 RTGCPTR GCPtrNearSym2;
2535 int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2536 &szModName[0], sizeof(szModName), &GCPtrMod,
2537 &szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2538 &szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2539 if (VBOX_SUCCESS(rc))
2540 {
2541 pHlp->pfnPrintf(pHlp,
2542 "!! EIP in %s (%VGv) at rva %x near symbols:\n"
2543 "!! %VGv rva %VGv off %08x %s\n"
2544 "!! %VGv rva %VGv off -%08x %s\n",
2545 szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2546 GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2547 GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2548 }
2549 else
2550 pHlp->pfnPrintf(pHlp,
2551 "!! EIP is not in any code known to VMM!\n");
2552 }
2553
2554 /* Disassemble the instruction. */
2555 char szInstr[256];
2556 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2557 if (VBOX_SUCCESS(rc2))
2558 pHlp->pfnPrintf(pHlp,
2559 "!! %s\n", szInstr);
2560
2561 /* Dump the hypervisor cpu state. */
2562 pHlp->pfnPrintf(pHlp,
2563 "!!\n"
2564 "!!\n"
2565 "!!\n");
2566 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2567 fDoneHyper = true;
2568
2569 /* Callstack. */
2570 DBGFSTACKFRAME Frame = {0};
2571 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2572 if (VBOX_SUCCESS(rc2))
2573 {
2574 pHlp->pfnPrintf(pHlp,
2575 "!!\n"
2576 "!! Call Stack:\n"
2577 "!!\n"
2578 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2579 do
2580 {
2581 pHlp->pfnPrintf(pHlp,
2582 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2583 (uint32_t)Frame.AddrFrame.off,
2584 (uint32_t)Frame.AddrReturnFrame.off,
2585 (uint32_t)Frame.AddrReturnPC.Sel,
2586 (uint32_t)Frame.AddrReturnPC.off,
2587 Frame.Args.au32[0],
2588 Frame.Args.au32[1],
2589 Frame.Args.au32[2],
2590 Frame.Args.au32[3]);
2591 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2592 if (Frame.pSymPC)
2593 {
2594 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2595 if (offDisp > 0)
2596 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2597 else if (offDisp < 0)
2598 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2599 else
2600 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2601 }
2602 if (Frame.pLinePC)
2603 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2604 pHlp->pfnPrintf(pHlp, "\n");
2605
2606 /* next */
2607 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2608 } while (VBOX_SUCCESS(rc2));
2609 DBGFR3StackWalkEnd(pVM, &Frame);
2610 }
2611
2612 /* raw stack */
2613 pHlp->pfnPrintf(pHlp,
2614 "!!\n"
2615 "!! Raw stack (mind the direction).\n"
2616 "!!\n"
2617 "%.*Vhxd\n",
2618 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2619 break;
2620 }
2621
2622 default:
2623 {
2624 break;
2625 }
2626
2627 } /* switch (rcErr) */
2628
2629
2630 /*
2631 * Generic info dumper loop.
2632 */
2633 static struct
2634 {
2635 const char *pszInfo;
2636 const char *pszArgs;
2637 } const aInfo[] =
2638 {
2639 { "mappings", NULL },
2640 { "hma", NULL },
2641 { "cpumguest", "verbose" },
2642 { "cpumguestinstr", "verbose" },
2643 { "cpumhyper", "verbose" },
2644 { "cpumhost", "verbose" },
2645 { "mode", "all" },
2646 { "cpuid", "verbose" },
2647 { "gdt", NULL },
2648 { "ldt", NULL },
2649 //{ "tss", NULL },
2650 { "ioport", NULL },
2651 { "mmio", NULL },
2652 { "phys", NULL },
2653 //{ "pgmpd", NULL }, - doesn't always work at init time...
2654 { "timers", NULL },
2655 { "activetimers", NULL },
2656 { "handlers", "phys virt hyper stats" },
2657 { "cfgm", NULL },
2658 };
2659 for (unsigned i = 0; i < RT_ELEMENTS(aInfo); i++)
2660 {
2661 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2662 continue;
2663 pHlp->pfnPrintf(pHlp,
2664 "!!\n"
2665 "!! {%s, %s}\n"
2666 "!!\n",
2667 aInfo[i].pszInfo, aInfo[i].pszArgs);
2668 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2669 }
2670
2671 /* done */
2672 pHlp->pfnPrintf(pHlp,
2673 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2674
2675
2676 /*
2677 * Delete the output instance (flushing and restoring of flags).
2678 */
2679 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2680}
2681
2682
2683
2684/**
2685 * Displays the Force action Flags.
2686 *
2687 * @param pVM The VM handle.
2688 * @param pHlp The output helpers.
2689 * @param pszArgs The additional arguments (ignored).
2690 */
2691static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2692{
2693 const uint32_t fForcedActions = pVM->fForcedActions;
2694
2695 pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2696
2697 /* show the flag mnemonics */
2698 int c = 0;
2699 uint32_t f = fForcedActions;
2700#define PRINT_FLAG(flag) do { \
2701 if (f & (flag)) \
2702 { \
2703 static const char *s_psz = #flag; \
2704 if (!(c % 6)) \
2705 pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2706 else \
2707 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2708 c++; \
2709 f &= ~(flag); \
2710 } \
2711 } while (0)
2712 PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2713 PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2714 PRINT_FLAG(VM_FF_TIMER);
2715 PRINT_FLAG(VM_FF_PDM_QUEUES);
2716 PRINT_FLAG(VM_FF_PDM_DMA);
2717 PRINT_FLAG(VM_FF_PDM_CRITSECT);
2718 PRINT_FLAG(VM_FF_DBGF);
2719 PRINT_FLAG(VM_FF_REQUEST);
2720 PRINT_FLAG(VM_FF_TERMINATE);
2721 PRINT_FLAG(VM_FF_RESET);
2722 PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2723 PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2724 PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2725 PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2726 PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2727 PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2728 PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2729 PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2730 PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2731 PRINT_FLAG(VM_FF_TO_R3);
2732 PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2733 if (f)
2734 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2735 else
2736 pHlp->pfnPrintf(pHlp, "\n");
2737#undef PRINT_FLAG
2738
2739 /* the groups */
2740 c = 0;
2741#define PRINT_GROUP(grp) do { \
2742 if (fForcedActions & (grp)) \
2743 { \
2744 static const char *s_psz = #grp; \
2745 if (!(c % 5)) \
2746 pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2747 else \
2748 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2749 c++; \
2750 } \
2751 } while (0)
2752 PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2753 PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2754 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2755 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2756 PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2757 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2758 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2759 PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2760 PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2761 if (c)
2762 pHlp->pfnPrintf(pHlp, "\n");
2763#undef PRINT_GROUP
2764}
2765
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