VirtualBox

source: vbox/trunk/src/VBox/VMM/SELM.cpp@ 19077

Last change on this file since 19077 was 18988, checked in by vboxsync, 16 years ago

PGM api changes
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1/* $Id: SELM.cpp 18988 2009-04-17 13:00:59Z vboxsync $ */
2/** @file
3 * SELM - The Selector Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_selm SELM - The Selector Manager
23 *
24 * SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
25 * of a few hyper selector for the raw-mode context. In the hardware assisted
26 * virtualization mode its only task is to decode entries in the guest GDT or
27 * LDT once in a while.
28 *
29 * @see grp_selm
30 *
31 *
32 * @section seg_selm_shadowing Shadowing
33 *
34 * SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
35 * work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
36 * The idea is to do it in a more on-demand fashion when we get time. There
37 * also a whole bunch of issues with the current synchronization of all three
38 * tables, see notes and todos in the code.
39 *
40 * When the guest makes changes to the GDT we will try update the shadow copy
41 * without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
42 *
43 * When the guest make LDT changes we'll trigger a full resync of the LDT
44 * (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
45 *
46 * The TSS shadowing is limited to the fields we need to care about, namely SS0
47 * and ESP0. The Patch Manager makes use of these. We monitor updates to the
48 * guest TSS and will try keep our SS0 and ESP0 copies up to date this way
49 * rather than go the SELMR3SyncTSS() route.
50 *
51 * When in raw-mode SELM also injects a few extra GDT selectors which are used
52 * by the raw-mode (hyper) context. These start their life at the high end of
53 * the table and will be relocated when the guest tries to make use of them...
54 * Well, that was that idea at least, only the code isn't quite there yet which
55 * is why we have trouble with guests which actually have a full sized GDT.
56 *
57 * So, the summary of the current GDT, LDT and TSS shadowing is that there is a
58 * lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
59 *
60 */
61
62/*******************************************************************************
63* Header Files *
64*******************************************************************************/
65#define LOG_GROUP LOG_GROUP_SELM
66#include <VBox/selm.h>
67#include <VBox/cpum.h>
68#include <VBox/stam.h>
69#include <VBox/mm.h>
70#include <VBox/ssm.h>
71#include <VBox/pgm.h>
72#include <VBox/trpm.h>
73#include <VBox/dbgf.h>
74#include "SELMInternal.h"
75#include <VBox/vm.h>
76#include <VBox/err.h>
77#include <VBox/param.h>
78
79#include <iprt/assert.h>
80#include <VBox/log.h>
81#include <iprt/asm.h>
82#include <iprt/string.h>
83#include <iprt/thread.h>
84#include <iprt/string.h>
85
86
87/**
88 * Enable or disable tracking of Guest's GDT/LDT/TSS.
89 * @{
90 */
91#define SELM_TRACK_GUEST_GDT_CHANGES
92#define SELM_TRACK_GUEST_LDT_CHANGES
93#define SELM_TRACK_GUEST_TSS_CHANGES
94/** @} */
95
96/**
97 * Enable or disable tracking of Shadow GDT/LDT/TSS.
98 * @{
99 */
100#define SELM_TRACK_SHADOW_GDT_CHANGES
101#define SELM_TRACK_SHADOW_LDT_CHANGES
102#define SELM_TRACK_SHADOW_TSS_CHANGES
103/** @} */
104
105
106/** SELM saved state version. */
107#define SELM_SAVED_STATE_VERSION 5
108
109
110/*******************************************************************************
111* Internal Functions *
112*******************************************************************************/
113static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
114static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
115static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
116static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
117static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
118static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
119static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
120static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
121static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
122static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
123//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125
126
127
128/**
129 * Initializes the SELM.
130 *
131 * @returns VBox status code.
132 * @param pVM The VM to operate on.
133 */
134VMMR3DECL(int) SELMR3Init(PVM pVM)
135{
136 LogFlow(("SELMR3Init\n"));
137
138 /*
139 * Assert alignment and sizes.
140 * (The TSS block requires contiguous back.)
141 */
142 AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
143 AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
144#if 0 /* doesn't work */
145 AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
146 AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
147#endif
148 AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
149 AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
150 AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
151
152 /*
153 * Init the structure.
154 */
155 pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
156 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
157 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
158 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
159 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
160 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
161
162 /*
163 * Allocate GDT table.
164 */
165 int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
166 PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
167 AssertRCReturn(rc, rc);
168
169 /*
170 * Allocate LDT area.
171 */
172 rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
173 AssertRCReturn(rc, rc);
174
175 /*
176 * Init Guest's and Shadow GDT, LDT, TSS changes control variables.
177 */
178 pVM->selm.s.cbEffGuestGdtLimit = 0;
179 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
180 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
181 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
182
183 pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
184 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
185 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
186 pVM->selm.s.GCSelTss = RTSEL_MAX;
187
188 pVM->selm.s.fDisableMonitoring = false;
189 pVM->selm.s.fSyncTSSRing0Stack = false;
190
191 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
192 * for I/O operations. */
193 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
194 /* bit set to 1 means no redirection */
195 memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
196
197 /*
198 * Register the saved state data unit.
199 */
200 rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
201 NULL, selmR3Save, NULL,
202 NULL, selmR3Load, selmR3LoadDone);
203 if (RT_FAILURE(rc))
204 return rc;
205
206 /*
207 * Statistics.
208 */
209 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
210 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
211 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
212 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
213 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
214 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
215 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
216 STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
217 STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
218
219 STAM_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
220 STAM_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
221
222 /*
223 * Default action when entering raw mode for the first time
224 */
225 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
226 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
227 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
228
229 /*
230 * Register info handlers.
231 */
232 DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
233 DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
234 DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
235 DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
236 //DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
237 //DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
238
239 return rc;
240}
241
242
243/**
244 * Finalizes HMA page attributes.
245 *
246 * @returns VBox status code.
247 * @param pVM The VM handle.
248 */
249VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
250{
251 /** @cfgm{/DoubleFault,bool,false}
252 * Enables catching of double faults in the raw-mode context VMM code. This can
253 * be used when the tripple faults or hangs occure and one suspect an unhandled
254 * double fault. This is not enabled by default because it means making the
255 * hyper selectors writeable for all supervisor code, including the guest's.
256 * The double fault is a task switch and thus requires write access to the GDT
257 * of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
258 * 8 TSS for the back link.
259 */
260 bool f;
261#if defined(DEBUG_bird)
262 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
263#else
264 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
265#endif
266 AssertLogRelRCReturn(rc, rc);
267 if (f)
268 {
269 PX86DESC paGdt = pVM->selm.s.paGdtR3;
270 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
271 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
272 AssertRC(rc);
273 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
274 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
275 AssertRC(rc);
276 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
277 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
278 AssertRC(rc);
279 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
280 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
281 AssertRC(rc);
282 }
283 return VINF_SUCCESS;
284}
285
286
287/**
288 * Setup the hypervisor GDT selectors in our shadow table
289 *
290 * @param pVM The VM handle.
291 */
292static void selmR3SetupHyperGDTSelectors(PVM pVM)
293{
294 PX86DESC paGdt = pVM->selm.s.paGdtR3;
295
296 /*
297 * Set up global code and data descriptors for use in the guest context.
298 * Both are wide open (base 0, limit 4GB)
299 */
300 PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
301 pDesc->Gen.u16LimitLow = 0xffff;
302 pDesc->Gen.u4LimitHigh = 0xf;
303 pDesc->Gen.u16BaseLow = 0;
304 pDesc->Gen.u8BaseHigh1 = 0;
305 pDesc->Gen.u8BaseHigh2 = 0;
306 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
307 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
308 pDesc->Gen.u2Dpl = 0; /* supervisor */
309 pDesc->Gen.u1Present = 1;
310 pDesc->Gen.u1Available = 0;
311 pDesc->Gen.u1Long = 0;
312 pDesc->Gen.u1DefBig = 1; /* def 32 bit */
313 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
314
315 /* data */
316 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
317 pDesc->Gen.u16LimitLow = 0xffff;
318 pDesc->Gen.u4LimitHigh = 0xf;
319 pDesc->Gen.u16BaseLow = 0;
320 pDesc->Gen.u8BaseHigh1 = 0;
321 pDesc->Gen.u8BaseHigh2 = 0;
322 pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
323 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
324 pDesc->Gen.u2Dpl = 0; /* supervisor */
325 pDesc->Gen.u1Present = 1;
326 pDesc->Gen.u1Available = 0;
327 pDesc->Gen.u1Long = 0;
328 pDesc->Gen.u1DefBig = 1; /* big */
329 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
330
331 /* 64-bit mode code (& data?) */
332 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
333 pDesc->Gen.u16LimitLow = 0xffff;
334 pDesc->Gen.u4LimitHigh = 0xf;
335 pDesc->Gen.u16BaseLow = 0;
336 pDesc->Gen.u8BaseHigh1 = 0;
337 pDesc->Gen.u8BaseHigh2 = 0;
338 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
339 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
340 pDesc->Gen.u2Dpl = 0; /* supervisor */
341 pDesc->Gen.u1Present = 1;
342 pDesc->Gen.u1Available = 0;
343 pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
344 pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
345 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
346
347 /*
348 * TSS descriptor
349 */
350 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
351 RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
352 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
353 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
354 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
355 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
356 pDesc->Gen.u4LimitHigh = 0;
357 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
358 pDesc->Gen.u1DescType = 0; /* system */
359 pDesc->Gen.u2Dpl = 0; /* supervisor */
360 pDesc->Gen.u1Present = 1;
361 pDesc->Gen.u1Available = 0;
362 pDesc->Gen.u1Long = 0;
363 pDesc->Gen.u1DefBig = 0;
364 pDesc->Gen.u1Granularity = 0; /* byte limit */
365
366 /*
367 * TSS descriptor for trap 08
368 */
369 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
370 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
371 pDesc->Gen.u4LimitHigh = 0;
372 RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
373 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
374 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
375 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
376 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
377 pDesc->Gen.u1DescType = 0; /* system */
378 pDesc->Gen.u2Dpl = 0; /* supervisor */
379 pDesc->Gen.u1Present = 1;
380 pDesc->Gen.u1Available = 0;
381 pDesc->Gen.u1Long = 0;
382 pDesc->Gen.u1DefBig = 0;
383 pDesc->Gen.u1Granularity = 0; /* byte limit */
384}
385
386/**
387 * Applies relocations to data and code managed by this
388 * component. This function will be called at init and
389 * whenever the VMM need to relocate it self inside the GC.
390 *
391 * @param pVM The VM.
392 */
393VMMR3DECL(void) SELMR3Relocate(PVM pVM)
394{
395 PX86DESC paGdt = pVM->selm.s.paGdtR3;
396 LogFlow(("SELMR3Relocate\n"));
397
398 for (unsigned i=0;i<pVM->cCPUs;i++)
399 {
400 PVMCPU pVCpu = &pVM->aCpus[i];
401
402 /*
403 * Update GDTR and selector.
404 */
405 CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
406
407 /** @todo selector relocations should be a seperate operation? */
408 CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
409 CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
410 CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
411 CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
412 CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
413 }
414
415 selmR3SetupHyperGDTSelectors(pVM);
416
417/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
418/** @todo PGM knows the proper CR3 values these days, not CPUM. */
419 /*
420 * Update the TSSes.
421 */
422 /* Only applies to raw mode which supports only 1 VCPU */
423 PVMCPU pVCpu = &pVM->aCpus[0];
424
425 /* Current TSS */
426 pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
427 pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
428 pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVM);
429 pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
430 pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
431 pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
432 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
433
434 /* trap 08 */
435 pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
436 pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
437 pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
438 pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVM) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
439 pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
440 pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
441 pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
442 pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
443 pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
444 pVM->selm.s.TssTrap08.fs = 0;
445 pVM->selm.s.TssTrap08.gs = 0;
446 pVM->selm.s.TssTrap08.selLdt = 0;
447 pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
448 pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
449 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
450 pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
451 pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
452 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
453 pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
454 pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
455 /* TRPM will be updating the eip */
456
457 if (!pVM->selm.s.fDisableMonitoring)
458 {
459 /*
460 * Update shadow GDT/LDT/TSS write access handlers.
461 */
462 int rc;
463#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
464 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
465 {
466 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
467 AssertRC(rc);
468 }
469 pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
470 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
471 pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
472 0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
473 AssertRC(rc);
474#endif
475#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
476 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
477 {
478 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
479 AssertRC(rc);
480 }
481 pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
482 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
483 pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
484 0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
485 AssertRC(rc);
486#endif
487
488 /*
489 * Update the GC LDT region handler and address.
490 */
491#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
492 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
493 {
494 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
495 AssertRC(rc);
496 }
497#endif
498 pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
499#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
500 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
501 pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
502 0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
503 AssertRC(rc);
504#endif
505 }
506}
507
508
509/**
510 * Terminates the SELM.
511 *
512 * Termination means cleaning up and freeing all resources,
513 * the VM it self is at this point powered off or suspended.
514 *
515 * @returns VBox status code.
516 * @param pVM The VM to operate on.
517 */
518VMMR3DECL(int) SELMR3Term(PVM pVM)
519{
520 return 0;
521}
522
523
524/**
525 * The VM is being reset.
526 *
527 * For the SELM component this means that any GDT/LDT/TSS monitors
528 * needs to be removed.
529 *
530 * @param pVM VM handle.
531 */
532VMMR3DECL(void) SELMR3Reset(PVM pVM)
533{
534 LogFlow(("SELMR3Reset:\n"));
535 VM_ASSERT_EMT(pVM);
536
537 /*
538 * Uninstall guest GDT/LDT/TSS write access handlers.
539 */
540 int rc;
541#ifdef SELM_TRACK_GUEST_GDT_CHANGES
542 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
543 {
544 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
545 AssertRC(rc);
546 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
547 pVM->selm.s.GuestGdtr.cbGdt = 0;
548 }
549 pVM->selm.s.fGDTRangeRegistered = false;
550#endif
551#ifdef SELM_TRACK_GUEST_LDT_CHANGES
552 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
553 {
554 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
555 AssertRC(rc);
556 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
557 }
558#endif
559#ifdef SELM_TRACK_GUEST_TSS_CHANGES
560 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
561 {
562 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
563 AssertRC(rc);
564 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
565 pVM->selm.s.GCSelTss = RTSEL_MAX;
566 }
567#endif
568
569 /*
570 * Re-initialize other members.
571 */
572 pVM->selm.s.cbLdtLimit = 0;
573 pVM->selm.s.offLdtHyper = 0;
574 pVM->selm.s.cbMonitoredGuestTss = 0;
575
576 pVM->selm.s.fSyncTSSRing0Stack = false;
577
578 /*
579 * Default action when entering raw mode for the first time
580 */
581 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
582 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
583 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
584}
585
586/**
587 * Disable GDT/LDT/TSS monitoring and syncing
588 *
589 * @param pVM The VM to operate on.
590 */
591VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
592{
593 /*
594 * Uninstall guest GDT/LDT/TSS write access handlers.
595 */
596 int rc;
597#ifdef SELM_TRACK_GUEST_GDT_CHANGES
598 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
599 {
600 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
601 AssertRC(rc);
602 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
603 pVM->selm.s.GuestGdtr.cbGdt = 0;
604 }
605 pVM->selm.s.fGDTRangeRegistered = false;
606#endif
607#ifdef SELM_TRACK_GUEST_LDT_CHANGES
608 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
609 {
610 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
611 AssertRC(rc);
612 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
613 }
614#endif
615#ifdef SELM_TRACK_GUEST_TSS_CHANGES
616 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
617 {
618 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
619 AssertRC(rc);
620 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
621 pVM->selm.s.GCSelTss = RTSEL_MAX;
622 }
623#endif
624
625 /*
626 * Unregister shadow GDT/LDT/TSS write access handlers.
627 */
628#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
629 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
630 {
631 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
632 AssertRC(rc);
633 pVM->selm.s.paGdtRC = NIL_RTRCPTR;
634 }
635#endif
636#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
637 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
638 {
639 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
640 AssertRC(rc);
641 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
642 }
643#endif
644#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
645 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
646 {
647 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
648 AssertRC(rc);
649 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
650 }
651#endif
652
653 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
654 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
655 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
656
657 pVM->selm.s.fDisableMonitoring = true;
658}
659
660
661/**
662 * Execute state save operation.
663 *
664 * @returns VBox status code.
665 * @param pVM VM Handle.
666 * @param pSSM SSM operation handle.
667 */
668static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
669{
670 LogFlow(("selmR3Save:\n"));
671
672 /*
673 * Save the basic bits - fortunately all the other things can be resynced on load.
674 */
675 PSELM pSelm = &pVM->selm.s;
676
677 SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
678 SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
679 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
680 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
681 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
682 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
683 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
684 return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
685}
686
687
688/**
689 * Execute state load operation.
690 *
691 * @returns VBox status code.
692 * @param pVM VM Handle.
693 * @param pSSM SSM operation handle.
694 * @param u32Version Data layout version.
695 */
696static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
697{
698 LogFlow(("selmR3Load:\n"));
699
700 /*
701 * Validate version.
702 */
703 if (u32Version != SELM_SAVED_STATE_VERSION)
704 {
705 AssertMsgFailed(("selmR3Load: Invalid version u32Version=%d!\n", u32Version));
706 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
707 }
708
709 /*
710 * Do a reset.
711 */
712 SELMR3Reset(pVM);
713
714 /* Get the monitoring flag. */
715 SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
716
717 /* Get the TSS state flag. */
718 SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
719
720 /*
721 * Get the selectors.
722 */
723 RTSEL SelCS;
724 SSMR3GetSel(pSSM, &SelCS);
725 RTSEL SelDS;
726 SSMR3GetSel(pSSM, &SelDS);
727 RTSEL SelCS64;
728 SSMR3GetSel(pSSM, &SelCS64);
729 RTSEL SelDS64;
730 SSMR3GetSel(pSSM, &SelDS64);
731 RTSEL SelTSS;
732 SSMR3GetSel(pSSM, &SelTSS);
733 RTSEL SelTSSTrap08;
734 SSMR3GetSel(pSSM, &SelTSSTrap08);
735
736 /* Copy the selectors; they will be checked during relocation. */
737 PSELM pSelm = &pVM->selm.s;
738 pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
739 pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
740 pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
741 pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
742 pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
743
744 return VINF_SUCCESS;
745}
746
747
748/**
749 * Sync the GDT, LDT and TSS after loading the state.
750 *
751 * Just to play save, we set the FFs to force syncing before
752 * executing GC code.
753 *
754 * @returns VBox status code.
755 * @param pVM VM Handle.
756 * @param pSSM SSM operation handle.
757 */
758static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
759{
760 PVMCPU pVCpu = VMMGetCpu(pVM);
761
762 LogFlow(("selmR3LoadDone:\n"));
763
764 /*
765 * Don't do anything if it's a load failure.
766 */
767 int rc = SSMR3HandleGetStatus(pSSM);
768 if (RT_FAILURE(rc))
769 return VINF_SUCCESS;
770
771 /*
772 * Do the syncing if we're in protected mode.
773 */
774 if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
775 {
776 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
777 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
778 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
779 SELMR3UpdateFromCPUM(pVM, pVCpu);
780 }
781
782 /*
783 * Flag everything for resync on next raw mode entry.
784 */
785 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
786 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
787 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
788
789 return VINF_SUCCESS;
790}
791
792
793/**
794 * Updates the Guest GDT & LDT virtualization based on current CPU state.
795 *
796 * @returns VBox status code.
797 * @param pVM The VM to operate on.
798 * @param pVCpu The VMCPU to operate on.
799 */
800VMMR3DECL(int) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
801{
802 int rc = VINF_SUCCESS;
803
804 if (pVM->selm.s.fDisableMonitoring)
805 {
806 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
807 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
808 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
809
810 return VINF_SUCCESS;
811 }
812
813 STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
814
815 /*
816 * GDT sync
817 */
818 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_GDT))
819 {
820 /*
821 * Always assume the best
822 */
823 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_GDT);
824
825 /* If the GDT was changed, then make sure the LDT is checked too */
826 /** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
827 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
828 /* Same goes for the TSS selector */
829 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
830
831 /*
832 * Get the GDTR and check if there is anything to do (there usually is).
833 */
834 VBOXGDTR GDTR;
835 CPUMGetGuestGDTR(pVCpu, &GDTR);
836 if (GDTR.cbGdt < sizeof(X86DESC))
837 {
838 Log(("No GDT entries...\n"));
839 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
840 return VINF_SUCCESS;
841 }
842
843 /*
844 * Read the Guest GDT.
845 * ASSUMES that the entire GDT is in memory.
846 */
847 RTUINT cbEffLimit = GDTR.cbGdt;
848 PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
849 rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
850 if (RT_FAILURE(rc))
851 {
852 /*
853 * Read it page by page.
854 *
855 * Keep track of the last valid page and delay memsets and
856 * adjust cbEffLimit to reflect the effective size. The latter
857 * is something we do in the belief that the guest will probably
858 * never actually commit the last page, thus allowing us to keep
859 * our selectors in the high end of the GDT.
860 */
861 RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
862 RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
863 uint8_t *pu8Dst = (uint8_t *)&pVM->selm.s.paGdtR3[1];
864 uint8_t *pu8DstInvalid = pu8Dst;
865
866 while (cbLeft)
867 {
868 RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
869 cb = RT_MIN(cb, cbLeft);
870 rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
871 if (RT_SUCCESS(rc))
872 {
873 if (pu8DstInvalid != pu8Dst)
874 memset(pu8DstInvalid, 0, pu8Dst - pu8DstInvalid);
875 GCPtrSrc += cb;
876 pu8Dst += cb;
877 pu8DstInvalid = pu8Dst;
878 }
879 else if ( rc == VERR_PAGE_NOT_PRESENT
880 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
881 {
882 GCPtrSrc += cb;
883 pu8Dst += cb;
884 }
885 else
886 {
887 AssertReleaseMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
888 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
889 return VERR_NOT_IMPLEMENTED;
890 }
891 cbLeft -= cb;
892 }
893
894 /* any invalid pages at the end? */
895 if (pu8DstInvalid != pu8Dst)
896 {
897 cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
898 /* If any GDTEs was invalidated, zero them. */
899 if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
900 memset(pu8DstInvalid + cbEffLimit + 1, 0, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
901 }
902
903 /* keep track of the effective limit. */
904 if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
905 {
906 Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
907 pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
908 pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
909 }
910 }
911
912 /*
913 * Check if the Guest GDT intrudes on our GDT entries.
914 */
915 /** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
916 RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
917 if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
918 {
919 PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
920 PX86DESC pGDTE = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
921 int iGDT = 0;
922
923 Log(("Internal SELM GDT conflict: use non-present entries\n"));
924 STAM_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
925 while (pGDTE > pGDTEStart)
926 {
927 /* We can reuse non-present entries */
928 if (!pGDTE->Gen.u1Present)
929 {
930 aHyperSel[iGDT] = ((uintptr_t)pGDTE - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
931 aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
932 Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
933 iGDT++;
934 if (iGDT >= SELM_HYPER_SEL_MAX)
935 break;
936 }
937
938 pGDTE--;
939 }
940 if (iGDT != SELM_HYPER_SEL_MAX)
941 {
942 AssertReleaseMsgFailed(("Internal SELM GDT conflict.\n"));
943 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
944 return VERR_NOT_IMPLEMENTED;
945 }
946 }
947 else
948 {
949 aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
950 aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
951 aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
952 aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
953 aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
954 }
955
956 /*
957 * Work thru the copied GDT entries adjusting them for correct virtualization.
958 */
959 PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
960 while (pGDTE < pGDTEEnd)
961 {
962 if (pGDTE->Gen.u1Present)
963 {
964 /*
965 * Code and data selectors are generally 1:1, with the
966 * 'little' adjustment we do for DPL 0 selectors.
967 */
968 if (pGDTE->Gen.u1DescType)
969 {
970 /*
971 * Hack for A-bit against Trap E on read-only GDT.
972 */
973 /** @todo Fix this by loading ds and cs before turning off WP. */
974 pGDTE->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
975
976 /*
977 * All DPL 0 code and data segments are squeezed into DPL 1.
978 *
979 * We're skipping conforming segments here because those
980 * cannot give us any trouble.
981 */
982 if ( pGDTE->Gen.u2Dpl == 0
983 && (pGDTE->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
984 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
985 pGDTE->Gen.u2Dpl = 1;
986 }
987 else
988 {
989 /*
990 * System type selectors are marked not present.
991 * Recompiler or special handling is required for these.
992 */
993 /** @todo what about interrupt gates and rawr0? */
994 pGDTE->Gen.u1Present = 0;
995 }
996 }
997
998 /* Next GDT entry. */
999 pGDTE++;
1000 }
1001
1002 /*
1003 * Check if our hypervisor selectors were changed.
1004 */
1005 if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
1006 || aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
1007 || aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
1008 || aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
1009 || aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
1010 {
1011 /* Reinitialize our hypervisor GDTs */
1012 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
1013 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
1014 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
1015 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
1016 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1017
1018 STAM_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
1019
1020 /*
1021 * Do the relocation callbacks to let everyone update their hyper selector dependencies.
1022 * (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1023 */
1024 VMR3Relocate(pVM, 0);
1025 }
1026 else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1027 /* We overwrote all entries above, so we have to save them again. */
1028 selmR3SetupHyperGDTSelectors(pVM);
1029
1030 /*
1031 * Adjust the cached GDT limit.
1032 * Any GDT entries which have been removed must be cleared.
1033 */
1034 if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1035 {
1036 if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1037 memset(pGDTE, 0, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1038#ifndef SELM_TRACK_GUEST_GDT_CHANGES
1039 pVM->selm.s.GuestGdtr.cbGdt = GDTR.cbGdt;
1040#endif
1041 }
1042
1043#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1044 /*
1045 * Check if Guest's GDTR is changed.
1046 */
1047 if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1048 || GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1049 {
1050 Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1051
1052 /*
1053 * [Re]Register write virtual handler for guest's GDT.
1054 */
1055 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1056 {
1057 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1058 AssertRC(rc);
1059 }
1060
1061 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1062 0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0, "Guest GDT write access handler");
1063 if (RT_FAILURE(rc))
1064 return rc;
1065
1066 /* Update saved Guest GDTR. */
1067 pVM->selm.s.GuestGdtr = GDTR;
1068 pVM->selm.s.fGDTRangeRegistered = true;
1069 }
1070#endif
1071 }
1072
1073 /*
1074 * TSS sync
1075 */
1076 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
1077 {
1078 SELMR3SyncTSS(pVM, pVCpu);
1079 }
1080
1081 /*
1082 * LDT sync
1083 */
1084 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_LDT))
1085 {
1086 /*
1087 * Always assume the best
1088 */
1089 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_LDT);
1090
1091 /*
1092 * LDT handling is done similarly to the GDT handling with a shadow
1093 * array. However, since the LDT is expected to be swappable (at least
1094 * some ancient OSes makes it swappable) it must be floating and
1095 * synced on a per-page basis.
1096 *
1097 * Eventually we will change this to be fully on demand. Meaning that
1098 * we will only sync pages containing LDT selectors actually used and
1099 * let the #PF handler lazily sync pages as they are used.
1100 * (This applies to GDT too, when we start making OS/2 fast.)
1101 */
1102
1103 /*
1104 * First, determin the current LDT selector.
1105 */
1106 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1107 if ((SelLdt & X86_SEL_MASK) == 0)
1108 {
1109 /* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1110 CPUMSetHyperLDTR(pVCpu, 0);
1111#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1112 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1113 {
1114 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1115 AssertRC(rc);
1116 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1117 }
1118#endif
1119 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1120 return VINF_SUCCESS;
1121 }
1122
1123 /*
1124 * Get the LDT selector.
1125 */
1126 PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1127 RTGCPTR GCPtrLdt = X86DESC_BASE(*pDesc);
1128 unsigned cbLdt = X86DESC_LIMIT(*pDesc);
1129 if (pDesc->Gen.u1Granularity)
1130 cbLdt = (cbLdt << PAGE_SHIFT) | PAGE_OFFSET_MASK;
1131
1132 /*
1133 * Validate it.
1134 */
1135 if ( !cbLdt
1136 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1137 || pDesc->Gen.u1DescType
1138 || pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1139 {
1140 AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1141
1142 /* cbLdt > 0:
1143 * This is quite impossible, so we do as most people do when faced with
1144 * the impossible, we simply ignore it.
1145 */
1146 CPUMSetHyperLDTR(pVCpu, 0);
1147#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1148 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1149 {
1150 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1151 AssertRC(rc);
1152 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1153 }
1154#endif
1155 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1156 return VINF_SUCCESS;
1157 }
1158 /** @todo check what intel does about odd limits. */
1159 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1160
1161 /*
1162 * Use the cached guest ldt address if the descriptor has already been modified (see below)
1163 * (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1164 */
1165 if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1166 GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1167
1168
1169#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1170 /** @todo Handle only present LDT segments. */
1171 // if (pDesc->Gen.u1Present)
1172 {
1173 /*
1174 * Check if Guest's LDT address/limit is changed.
1175 */
1176 if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1177 || cbLdt != pVM->selm.s.cbLdtLimit)
1178 {
1179 Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1180 pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1181
1182 /*
1183 * [Re]Register write virtual handler for guest's GDT.
1184 * In the event of LDT overlapping something, don't install it just assume it's being updated.
1185 */
1186 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1187 {
1188 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1189 AssertRC(rc);
1190 }
1191#ifdef DEBUG
1192 if (pDesc->Gen.u1Present)
1193 Log(("LDT selector marked not present!!\n"));
1194#endif
1195 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1196 0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1197 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1198 {
1199 /** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1200 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1201 Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1202 GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1203 }
1204 else if (RT_SUCCESS(rc))
1205 pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1206 else
1207 {
1208 CPUMSetHyperLDTR(pVCpu, 0);
1209 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1210 return rc;
1211 }
1212
1213 pVM->selm.s.cbLdtLimit = cbLdt;
1214 }
1215 }
1216#else
1217 pVM->selm.s.cbLdtLimit = cbLdt;
1218#endif
1219
1220 /*
1221 * Calc Shadow LDT base.
1222 */
1223 unsigned off;
1224 pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1225 RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1226 PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1227
1228 /*
1229 * Enable the LDT selector in the shadow GDT.
1230 */
1231 pDesc->Gen.u1Present = 1;
1232 pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1233 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1234 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1235 pDesc->Gen.u1Available = 0;
1236 pDesc->Gen.u1Long = 0;
1237 if (cbLdt > 0xffff)
1238 {
1239 cbLdt = 0xffff;
1240 pDesc->Gen.u4LimitHigh = 0;
1241 pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1242 }
1243
1244 /*
1245 * Set Hyper LDTR and notify TRPM.
1246 */
1247 CPUMSetHyperLDTR(pVCpu, SelLdt);
1248
1249 /*
1250 * Loop synchronising the LDT page by page.
1251 */
1252 /** @todo investigate how intel handle various operations on half present cross page entries. */
1253 off = GCPtrLdt & (sizeof(X86DESC) - 1);
1254 AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1255
1256 /* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1257 unsigned cbLeft = cbLdt + 1;
1258 PX86DESC pLDTE = pShadowLDT;
1259 while (cbLeft)
1260 {
1261 /*
1262 * Read a chunk.
1263 */
1264 unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1265 if (cbChunk > cbLeft)
1266 cbChunk = cbLeft;
1267 rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1268 if (RT_SUCCESS(rc))
1269 {
1270 /*
1271 * Mark page
1272 */
1273 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D);
1274 AssertRC(rc);
1275
1276 /*
1277 * Loop thru the available LDT entries.
1278 * Figure out where to start and end and the potential cross pageness of
1279 * things adds a little complexity. pLDTE is updated there and not in the
1280 * 'next' part of the loop. The pLDTEEnd is inclusive.
1281 */
1282 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1283 if (pLDTE + 1 < pShadowLDT)
1284 pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1285 while (pLDTE <= pLDTEEnd)
1286 {
1287 if (pLDTE->Gen.u1Present)
1288 {
1289 /*
1290 * Code and data selectors are generally 1:1, with the
1291 * 'little' adjustment we do for DPL 0 selectors.
1292 */
1293 if (pLDTE->Gen.u1DescType)
1294 {
1295 /*
1296 * Hack for A-bit against Trap E on read-only GDT.
1297 */
1298 /** @todo Fix this by loading ds and cs before turning off WP. */
1299 if (!(pLDTE->Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1300 pLDTE->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1301
1302 /*
1303 * All DPL 0 code and data segments are squeezed into DPL 1.
1304 *
1305 * We're skipping conforming segments here because those
1306 * cannot give us any trouble.
1307 */
1308 if ( pLDTE->Gen.u2Dpl == 0
1309 && (pLDTE->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
1310 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
1311 pLDTE->Gen.u2Dpl = 1;
1312 }
1313 else
1314 {
1315 /*
1316 * System type selectors are marked not present.
1317 * Recompiler or special handling is required for these.
1318 */
1319 /** @todo what about interrupt gates and rawr0? */
1320 pLDTE->Gen.u1Present = 0;
1321 }
1322 }
1323
1324 /* Next LDT entry. */
1325 pLDTE++;
1326 }
1327 }
1328 else
1329 {
1330 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1331 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1332 AssertRC(rc);
1333 }
1334
1335 /*
1336 * Advance to the next page.
1337 */
1338 cbLeft -= cbChunk;
1339 GCPtrShadowLDT += cbChunk;
1340 pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1341 GCPtrLdt += cbChunk;
1342 }
1343 }
1344
1345 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1346 return VINF_SUCCESS;
1347}
1348
1349
1350/**
1351 * \#PF Handler callback for virtual access handler ranges.
1352 *
1353 * Important to realize that a physical page in a range can have aliases, and
1354 * for ALL and WRITE handlers these will also trigger.
1355 *
1356 * @returns VINF_SUCCESS if the handler have carried out the operation.
1357 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1358 * @param pVM VM Handle.
1359 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1360 * @param pvPtr The HC mapping of that address.
1361 * @param pvBuf What the guest is reading/writing.
1362 * @param cbBuf How much it's reading/writing.
1363 * @param enmAccessType The access type.
1364 * @param pvUser User argument.
1365 */
1366static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1367{
1368 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1369 Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1370 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
1371
1372 return VINF_PGM_HANDLER_DO_DEFAULT;
1373}
1374
1375
1376/**
1377 * \#PF Handler callback for virtual access handler ranges.
1378 *
1379 * Important to realize that a physical page in a range can have aliases, and
1380 * for ALL and WRITE handlers these will also trigger.
1381 *
1382 * @returns VINF_SUCCESS if the handler have carried out the operation.
1383 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1384 * @param pVM VM Handle.
1385 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1386 * @param pvPtr The HC mapping of that address.
1387 * @param pvBuf What the guest is reading/writing.
1388 * @param cbBuf How much it's reading/writing.
1389 * @param enmAccessType The access type.
1390 * @param pvUser User argument.
1391 */
1392static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1393{
1394 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1395 Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1396 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
1397 return VINF_PGM_HANDLER_DO_DEFAULT;
1398}
1399
1400
1401/**
1402 * \#PF Handler callback for virtual access handler ranges.
1403 *
1404 * Important to realize that a physical page in a range can have aliases, and
1405 * for ALL and WRITE handlers these will also trigger.
1406 *
1407 * @returns VINF_SUCCESS if the handler have carried out the operation.
1408 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1409 * @param pVM VM Handle.
1410 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1411 * @param pvPtr The HC mapping of that address.
1412 * @param pvBuf What the guest is reading/writing.
1413 * @param cbBuf How much it's reading/writing.
1414 * @param enmAccessType The access type.
1415 * @param pvUser User argument.
1416 */
1417static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1418{
1419 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1420 Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1421
1422 /** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1423 * reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1424 * should probably also deregister the virtual handler if TR.base/size
1425 * changes while we're in REM. */
1426
1427 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
1428
1429 return VINF_PGM_HANDLER_DO_DEFAULT;
1430}
1431
1432
1433/**
1434 * Synchronize the shadowed fields in the TSS.
1435 *
1436 * At present we're shadowing the ring-0 stack selector & pointer, and the
1437 * interrupt redirection bitmap (if present). We take the lazy approach wrt to
1438 * REM and this function is called both if REM made any changes to the TSS or
1439 * loaded TR.
1440 *
1441 * @returns VBox status code.
1442 * @param pVM The VM to operate on.
1443 * @param pVCpu The VMCPU to operate on.
1444 */
1445VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1446{
1447 int rc;
1448
1449 if (pVM->selm.s.fDisableMonitoring)
1450 {
1451 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
1452 return VINF_SUCCESS;
1453 }
1454
1455 STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1456 Assert(VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS));
1457
1458 /*
1459 * Get TR and extract and store the basic info.
1460 *
1461 * Note! The TSS limit is not checked by the LTR code, so we
1462 * have to be a bit careful with it. We make sure cbTss
1463 * won't be zero if TR is valid and if it's NULL we'll
1464 * make sure cbTss is 0.
1465 */
1466 CPUMSELREGHID trHid;
1467 RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1468 RTGCPTR GCPtrTss = trHid.u64Base;
1469 uint32_t cbTss = trHid.u32Limit;
1470 Assert( (SelTss & X86_SEL_MASK)
1471 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1472 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1473 if (SelTss & X86_SEL_MASK)
1474 {
1475 Assert(!(SelTss & X86_SEL_LDT));
1476 Assert(trHid.Attr.n.u1DescType == 0);
1477 Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1478 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1479 if (!++cbTss)
1480 cbTss = UINT32_MAX;
1481 }
1482 else
1483 {
1484 Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1485 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1486 cbTss = 0; /* the reset case. */
1487 }
1488 pVM->selm.s.cbGuestTss = cbTss;
1489 pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1490 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1491
1492 /*
1493 * Figure out the size of what need to monitor.
1494 */
1495 /* We're not interested in any 16-bit TSSes. */
1496 uint32_t cbMonitoredTss = cbTss;
1497 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1498 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1499 cbMonitoredTss = 0;
1500
1501 pVM->selm.s.offGuestIoBitmap = 0;
1502 bool fNoRing1Stack = true;
1503 if (cbMonitoredTss)
1504 {
1505 /*
1506 * 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1507 * If VME is enabled we also want to keep an eye on the interrupt
1508 * redirection bitmap.
1509 */
1510 VBOXTSS Tss;
1511 uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1512 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1513 if ( !(cr4 & X86_CR4_VME)
1514 || ( VBOX_SUCCESS(rc)
1515 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1516 && Tss.offIoBitmap > cbTss) /* beyond the end */ /** @todo not sure how the partial case is handled; probably not allowed. */
1517 )
1518 /* No interrupt redirection bitmap, just ESP0 and SS0. */
1519 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1520 else if (RT_SUCCESS(rc))
1521 {
1522 /*
1523 * Everything up to and including the interrupt redirection bitmap. Unfortunately
1524 * this can be quite a large chunk. We use to skip it earlier and just hope it
1525 * was kind of static...
1526 *
1527 * Update the virtual interrupt redirection bitmap while we're here.
1528 * (It is located in the 32 bytes before TR:offIoBitmap.)
1529 */
1530 cbMonitoredTss = Tss.offIoBitmap;
1531 pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1532
1533 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1534 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1535 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1536 AssertRC(rc);
1537 /** @todo memset the bitmap on failure? */
1538 Log2(("Redirection bitmap:\n"));
1539 Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1540 }
1541 else
1542 {
1543 cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1544 pVM->selm.s.offGuestIoBitmap = 0;
1545 /** @todo memset the bitmap? */
1546 }
1547
1548 /*
1549 * Update the ring 0 stack selector and base address.
1550 */
1551 if (RT_SUCCESS(rc))
1552 {
1553#ifdef LOG_ENABLED
1554 if (LogIsEnabled())
1555 {
1556 uint32_t ssr0, espr0;
1557 SELMGetRing1Stack(pVM, &ssr0, &espr0);
1558 if ((ssr0 & ~1) != Tss.ss0 || espr0 != Tss.esp0)
1559 {
1560 RTGCPHYS GCPhys = NIL_RTGCPHYS;
1561 rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1562 Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%VGp)\n",
1563 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1564 AssertMsg(ssr0 != Tss.ss0,
1565 ("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%VGp)\n",
1566 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1567 }
1568 Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1569 }
1570#endif /* LOG_ENABLED */
1571 AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1572
1573 /* Update our TSS structure for the guest's ring 1 stack */
1574 selmSetRing1Stack(pVM, Tss.ss0 | 1, Tss.esp0);
1575 pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1576 }
1577 }
1578
1579 /*
1580 * Flush the ring-1 stack and the direct syscall dispatching if we
1581 * cannot obtain SS0:ESP0.
1582 */
1583 if (fNoRing1Stack)
1584 {
1585 selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1586 pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1587
1588 /** @todo handle these dependencies better! */
1589 TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1590 TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1591 }
1592
1593 /*
1594 * Check for monitor changes and apply them.
1595 */
1596 if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1597 || cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1598 {
1599 Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1600 GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1601
1602 /* Release the old range first. */
1603 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1604 {
1605 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1606 AssertRC(rc);
1607 }
1608
1609 /* Register the write handler if TS != 0. */
1610 if (cbMonitoredTss != 0)
1611 {
1612 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1613 0, selmR3GuestTSSWriteHandler,
1614 "selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1615 if (RT_FAILURE(rc))
1616 {
1617 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1618 return rc;
1619 }
1620
1621 /* Update saved Guest TSS info. */
1622 pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1623 pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1624 pVM->selm.s.GCSelTss = SelTss;
1625 }
1626 else
1627 {
1628 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1629 pVM->selm.s.cbMonitoredGuestTss = 0;
1630 pVM->selm.s.GCSelTss = 0;
1631 }
1632 }
1633
1634 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
1635
1636 STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1637 return VINF_SUCCESS;
1638}
1639
1640
1641/**
1642 * Compares the Guest GDT and LDT with the shadow tables.
1643 * This is a VBOX_STRICT only function.
1644 *
1645 * @returns VBox status code.
1646 * @param pVM The VM Handle.
1647 */
1648VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1649{
1650#ifdef VBOX_STRICT
1651 PVMCPU pVCpu = VMMGetCpu(pVM);
1652
1653 /*
1654 * Get GDTR and check for conflict.
1655 */
1656 VBOXGDTR GDTR;
1657 CPUMGetGuestGDTR(pVCpu, &GDTR);
1658 if (GDTR.cbGdt == 0)
1659 return VINF_SUCCESS;
1660
1661 if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1662 Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1663
1664 if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1665 Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1666
1667 /*
1668 * Loop thru the GDT checking each entry.
1669 */
1670 RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1671 PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1672 PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1673 while (pGDTE < pGDTEEnd)
1674 {
1675 X86DESC GDTEGuest;
1676 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1677 if (RT_SUCCESS(rc))
1678 {
1679 if (pGDTE->Gen.u1DescType || pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1680 {
1681 if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1682 || pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1683 || pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1684 || pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1685 || pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1686 || pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1687 || pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1688 {
1689 unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1690 SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1691 SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1692 }
1693 }
1694 }
1695
1696 /* Advance to the next descriptor. */
1697 GCPtrGDTEGuest += sizeof(X86DESC);
1698 pGDTE++;
1699 }
1700
1701
1702 /*
1703 * LDT?
1704 */
1705 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1706 if ((SelLdt & X86_SEL_MASK) == 0)
1707 return VINF_SUCCESS;
1708 if (SelLdt > GDTR.cbGdt)
1709 {
1710 Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1711 return VERR_INTERNAL_ERROR;
1712 }
1713 X86DESC LDTDesc;
1714 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1715 if (RT_FAILURE(rc))
1716 {
1717 Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1718 return rc;
1719 }
1720 RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(LDTDesc);
1721 unsigned cbLdt = X86DESC_LIMIT(LDTDesc);
1722 if (LDTDesc.Gen.u1Granularity)
1723 cbLdt = (cbLdt << PAGE_SHIFT) | PAGE_OFFSET_MASK;
1724
1725 /*
1726 * Validate it.
1727 */
1728 if (!cbLdt)
1729 return VINF_SUCCESS;
1730 /** @todo check what intel does about odd limits. */
1731 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1732 if ( LDTDesc.Gen.u1DescType
1733 || LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1734 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1735 {
1736 Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1737 return VERR_INTERNAL_ERROR;
1738 }
1739
1740 /*
1741 * Loop thru the LDT checking each entry.
1742 */
1743 unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1744 PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1745 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1746 while (pLDTE < pLDTEEnd)
1747 {
1748 X86DESC LDTEGuest;
1749 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1750 if (RT_SUCCESS(rc))
1751 {
1752 if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1753 || pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1754 || pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1755 || pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1756 || pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1757 || pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1758 || pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1759 {
1760 unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1761 SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1762 SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1763 }
1764 }
1765
1766 /* Advance to the next descriptor. */
1767 GCPtrLDTEGuest += sizeof(X86DESC);
1768 pLDTE++;
1769 }
1770
1771#else /* !VBOX_STRICT */
1772 NOREF(pVM);
1773#endif /* !VBOX_STRICT */
1774
1775 return VINF_SUCCESS;
1776}
1777
1778
1779/**
1780 * Validates the RawR0 TSS values against the one in the Guest TSS.
1781 *
1782 * @returns true if it matches.
1783 * @returns false and assertions on mismatch..
1784 * @param pVM VM Handle.
1785 */
1786VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1787{
1788#ifdef VBOX_STRICT
1789 PVMCPU pVCpu = VMMGetCpu(pVM);
1790
1791 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
1792 return true;
1793
1794 /*
1795 * Get TR and extract the basic info.
1796 */
1797 CPUMSELREGHID trHid;
1798 RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1799 RTGCPTR GCPtrTss = trHid.u64Base;
1800 uint32_t cbTss = trHid.u32Limit;
1801 Assert( (SelTss & X86_SEL_MASK)
1802 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1803 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1804 if (SelTss & X86_SEL_MASK)
1805 {
1806 AssertReturn(!(SelTss & X86_SEL_LDT), false);
1807 AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1808 AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1809 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1810 false);
1811 if (!++cbTss)
1812 cbTss = UINT32_MAX;
1813 }
1814 else
1815 {
1816 AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1817 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */),
1818 false);
1819 cbTss = 0; /* the reset case. */
1820 }
1821 AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1822 AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1823 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1824 ("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1825 false);
1826 AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1827 || (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1828 ("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1829 false);
1830 AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1831 || (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1832 ("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1833 false);
1834
1835
1836 /*
1837 * Figure out the size of what need to monitor.
1838 */
1839 bool fNoRing1Stack = true;
1840 /* We're not interested in any 16-bit TSSes. */
1841 uint32_t cbMonitoredTss = cbTss;
1842 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1843 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1844 cbMonitoredTss = 0;
1845 if (cbMonitoredTss)
1846 {
1847 VBOXTSS Tss;
1848 uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1849 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1850 AssertReturn( rc == VINF_SUCCESS
1851 /* Happends early in XP boot during page table switching. */
1852 || ( (rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT)
1853 && !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
1854 false);
1855 if ( !(cr4 & X86_CR4_VME)
1856 || ( VBOX_SUCCESS(rc)
1857 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1858 && Tss.offIoBitmap > cbTss)
1859 )
1860 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1861 else if (RT_SUCCESS(rc))
1862 {
1863 cbMonitoredTss = Tss.offIoBitmap;
1864 AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1865 ("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1866 false);
1867
1868 /* check the bitmap */
1869 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1870 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
1871 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1872 AssertRCReturn(rc, false);
1873 AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1874 ("offIoBitmap=%#x cbTss=%#x\n"
1875 " Guest: %.32Rhxs\n"
1876 "Shadow: %.32Rhxs\n",
1877 Tss.offIoBitmap, cbTss,
1878 &Tss.IntRedirBitmap[0],
1879 &pVM->selm.s.Tss.IntRedirBitmap[0]),
1880 false);
1881 }
1882 else
1883 cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1884
1885 /*
1886 * Check SS0 and ESP0.
1887 */
1888 if ( !pVM->selm.s.fSyncTSSRing0Stack
1889 && RT_SUCCESS(rc))
1890 {
1891 if ( Tss.esp0 != pVM->selm.s.Tss.esp1
1892 || Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
1893 {
1894 RTGCPHYS GCPhys;
1895 rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1896 AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1897 (pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
1898 Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
1899 return false;
1900 }
1901 }
1902 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1903 }
1904 else
1905 {
1906 AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
1907 AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
1908 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1909 }
1910
1911
1912
1913 return true;
1914
1915#else /* !VBOX_STRICT */
1916 NOREF(pVM);
1917 return true;
1918#endif /* !VBOX_STRICT */
1919}
1920
1921
1922/**
1923 * Returns flat address and limit of LDT by LDT selector from guest GDTR.
1924 *
1925 * Fully validate selector.
1926 *
1927 * @returns VBox status.
1928 * @param pVM VM Handle.
1929 * @param SelLdt LDT selector.
1930 * @param ppvLdt Where to store the flat address of LDT.
1931 * @param pcbLimit Where to store LDT limit.
1932 */
1933VMMDECL(int) SELMGetLDTFromSel(PVM pVM, RTSEL SelLdt, PRTGCPTR ppvLdt, unsigned *pcbLimit)
1934{
1935 PVMCPU pVCpu = VMMGetCpu(pVM);
1936
1937 /* Get guest GDTR. */
1938 VBOXGDTR GDTR;
1939 CPUMGetGuestGDTR(pVCpu, &GDTR);
1940
1941 /* Check selector TI and GDT limit. */
1942 if ( SelLdt & X86_SEL_LDT
1943 || (SelLdt > GDTR.cbGdt))
1944 return VERR_INVALID_SELECTOR;
1945
1946 /* Read descriptor from GC. */
1947 X86DESC Desc;
1948 int rc = PGMPhysSimpleReadGCPtr(pVCpu, (void *)&Desc, (RTGCPTR)(GDTR.pGdt + (SelLdt & X86_SEL_MASK)), sizeof(Desc));
1949 if (RT_FAILURE(rc))
1950 {
1951 /* fatal */
1952 AssertMsgFailed(("Can't read LDT descriptor for selector=%04X\n", SelLdt));
1953 return VERR_SELECTOR_NOT_PRESENT;
1954 }
1955
1956 /* Check if LDT descriptor is not present. */
1957 if (Desc.Gen.u1Present == 0)
1958 return VERR_SELECTOR_NOT_PRESENT;
1959
1960 /* Check LDT descriptor type. */
1961 if ( Desc.Gen.u1DescType == 1
1962 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1963 return VERR_INVALID_SELECTOR;
1964
1965 /* LDT descriptor is ok. */
1966 if (ppvLdt)
1967 {
1968 *ppvLdt = (RTGCPTR)X86DESC_BASE(Desc);
1969 *pcbLimit = X86DESC_LIMIT(Desc);
1970 }
1971 return VINF_SUCCESS;
1972}
1973
1974
1975/**
1976 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
1977 *
1978 * See SELMR3GetSelectorInfo for details.
1979 *
1980 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
1981 *
1982 * @param pVM VM handle.
1983 * @param pVCpu VMCPU handle.
1984 * @param Sel The selector to get info about.
1985 * @param pSelInfo Where to store the information.
1986 */
1987static int selmR3GetSelectorInfo64(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PSELMSELINFO pSelInfo)
1988{
1989 pSelInfo->fHyper = false;
1990
1991 /*
1992 * Read it from the guest descriptor table.
1993 */
1994 X86DESC64 Desc;
1995 VBOXGDTR Gdtr;
1996 RTGCPTR GCPtrDesc;
1997 CPUMGetGuestGDTR(pVCpu, &Gdtr);
1998 if (!(Sel & X86_SEL_LDT))
1999 {
2000 /* GDT */
2001 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2002 return VERR_INVALID_SELECTOR;
2003 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2004 }
2005 else
2006 {
2007 /*
2008 * LDT - must locate the LDT first...
2009 */
2010 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2011 if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */
2012 || (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2013 return VERR_INVALID_SELECTOR;
2014 GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2015 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2016 if (RT_FAILURE(rc))
2017 return rc;
2018
2019 /* validate the LDT descriptor. */
2020 if (Desc.Gen.u1Present == 0)
2021 return VERR_SELECTOR_NOT_PRESENT;
2022 if ( Desc.Gen.u1DescType == 1
2023 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2024 return VERR_INVALID_SELECTOR;
2025
2026 unsigned cbLimit = X86DESC_LIMIT(Desc);
2027 if (Desc.Gen.u1Granularity)
2028 cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2029 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2030 return VERR_INVALID_SELECTOR;
2031
2032 /* calc the descriptor location. */
2033 GCPtrDesc = X86DESC64_BASE(Desc);
2034 GCPtrDesc += (Sel & X86_SEL_MASK);
2035 }
2036
2037 /* read the descriptor. */
2038 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2039 if (RT_FAILURE(rc))
2040 return rc;
2041
2042 /*
2043 * Extract the base and limit
2044 */
2045 pSelInfo->Sel = Sel;
2046 pSelInfo->Raw64 = Desc;
2047 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2048 if (Desc.Gen.u1Granularity)
2049 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2050 pSelInfo->GCPtrBase = X86DESC64_BASE(Desc);
2051 pSelInfo->fRealMode = false;
2052
2053 return VINF_SUCCESS;
2054}
2055
2056
2057/**
2058 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2059 *
2060 * See SELMR3GetSelectorInfo for details.
2061 *
2062 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
2063 *
2064 * @param pVM VM handle.
2065 * @param pVCpu VMCPU handle.
2066 * @param Sel The selector to get info about.
2067 * @param pSelInfo Where to store the information.
2068 */
2069static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PSELMSELINFO pSelInfo)
2070{
2071 /*
2072 * Read the descriptor entry
2073 */
2074 X86DESC Desc;
2075 if ( !(Sel & X86_SEL_LDT)
2076 && ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2077 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2078 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2079 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2080 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK))
2081 )
2082 {
2083 /*
2084 * Hypervisor descriptor.
2085 */
2086 pSelInfo->fHyper = true;
2087 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2088 }
2089 else if (CPUMIsGuestInProtectedMode(pVCpu))
2090 {
2091 /*
2092 * Read it from the guest descriptor table.
2093 */
2094 pSelInfo->fHyper = false;
2095
2096 VBOXGDTR Gdtr;
2097 RTGCPTR GCPtrDesc;
2098 CPUMGetGuestGDTR(pVCpu, &Gdtr);
2099 if (!(Sel & X86_SEL_LDT))
2100 {
2101 /* GDT */
2102 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2103 return VERR_INVALID_SELECTOR;
2104 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2105 }
2106 else
2107 {
2108 /*
2109 * LDT - must locate the LDT first...
2110 */
2111 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2112 if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */
2113 || (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2114 return VERR_INVALID_SELECTOR;
2115 GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2116 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2117 if (RT_FAILURE(rc))
2118 return rc;
2119
2120 /* validate the LDT descriptor. */
2121 if (Desc.Gen.u1Present == 0)
2122 return VERR_SELECTOR_NOT_PRESENT;
2123 if ( Desc.Gen.u1DescType == 1
2124 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2125 return VERR_INVALID_SELECTOR;
2126
2127 unsigned cbLimit = X86DESC_LIMIT(Desc);
2128 if (Desc.Gen.u1Granularity)
2129 cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2130 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2131 return VERR_INVALID_SELECTOR;
2132
2133 /* calc the descriptor location. */
2134 GCPtrDesc = X86DESC_BASE(Desc);
2135 GCPtrDesc += (Sel & X86_SEL_MASK);
2136 }
2137
2138 /* read the descriptor. */
2139 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2140 if (RT_FAILURE(rc))
2141 return rc;
2142 }
2143 else
2144 {
2145 /*
2146 * We're in real mode.
2147 */
2148 pSelInfo->Sel = Sel;
2149 pSelInfo->GCPtrBase = Sel << 4;
2150 pSelInfo->cbLimit = 0xffff;
2151 pSelInfo->fHyper = false;
2152 pSelInfo->fRealMode = true;
2153 memset(&pSelInfo->Raw, 0, sizeof(pSelInfo->Raw));
2154 return VINF_SUCCESS;
2155 }
2156
2157 /*
2158 * Extract the base and limit
2159 */
2160 pSelInfo->Sel = Sel;
2161 pSelInfo->Raw = Desc;
2162 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2163 if (Desc.Gen.u1Granularity)
2164 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2165 pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
2166 pSelInfo->fRealMode = false;
2167
2168 return VINF_SUCCESS;
2169}
2170
2171
2172/**
2173 * Gets information about a selector.
2174 * Intended for the debugger mostly and will prefer the guest
2175 * descriptor tables over the shadow ones.
2176 *
2177 * @returns VINF_SUCCESS on success.
2178 * @returns VERR_INVALID_SELECTOR if the selector isn't fully inside the descriptor table.
2179 * @returns VERR_SELECTOR_NOT_PRESENT if the selector wasn't present.
2180 * @returns VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the pagetable or page
2181 * backing the selector table wasn't present.
2182 * @returns Other VBox status code on other errors.
2183 *
2184 * @param pVM VM handle.
2185 * @param Sel The selector to get info about.
2186 * @param pSelInfo Where to store the information.
2187 */
2188VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PSELMSELINFO pSelInfo)
2189{
2190 AssertPtr(pSelInfo);
2191 if (CPUMIsGuestInLongMode(pVCpu))
2192 return selmR3GetSelectorInfo64(pVM, pVCpu, Sel, pSelInfo);
2193 return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2194}
2195
2196
2197/**
2198 * Gets information about a selector from the shadow tables.
2199 *
2200 * This is intended to be faster than the SELMR3GetSelectorInfo() method, but requires
2201 * that the caller ensures that the shadow tables are up to date.
2202 *
2203 * @returns VINF_SUCCESS on success.
2204 * @returns VERR_INVALID_SELECTOR if the selector isn't fully inside the descriptor table.
2205 * @returns VERR_SELECTOR_NOT_PRESENT if the selector wasn't present.
2206 * @returns VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the pagetable or page
2207 * backing the selector table wasn't present.
2208 * @returns Other VBox status code on other errors.
2209 *
2210 * @param pVM VM handle.
2211 * @param Sel The selector to get info about.
2212 * @param pSelInfo Where to store the information.
2213 */
2214VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo)
2215{
2216 Assert(pSelInfo);
2217
2218 /*
2219 * Read the descriptor entry
2220 */
2221 X86DESC Desc;
2222 if (!(Sel & X86_SEL_LDT))
2223 {
2224 /*
2225 * Global descriptor.
2226 */
2227 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2228 pSelInfo->fHyper = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2229 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2230 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2231 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2232 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK);
2233 /** @todo check that the GDT offset is valid. */
2234 }
2235 else
2236 {
2237 /*
2238 * Local Descriptor.
2239 */
2240 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2241 Desc = paLDT[Sel >> X86_SEL_SHIFT];
2242 /** @todo check if the LDT page is actually available. */
2243 /** @todo check that the LDT offset is valid. */
2244 pSelInfo->fHyper = false;
2245 }
2246
2247 /*
2248 * Extract the base and limit
2249 */
2250 pSelInfo->Sel = Sel;
2251 pSelInfo->Raw = Desc;
2252 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2253 if (Desc.Gen.u1Granularity)
2254 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2255 pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
2256 pSelInfo->fRealMode = false;
2257
2258 return VINF_SUCCESS;
2259}
2260
2261
2262/**
2263 * Formats a descriptor.
2264 *
2265 * @param Desc Descriptor to format.
2266 * @param Sel Selector number.
2267 * @param pszOutput Output buffer.
2268 * @param cchOutput Size of output buffer.
2269 */
2270static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2271{
2272 /*
2273 * Make variable description string.
2274 */
2275 static struct
2276 {
2277 unsigned cch;
2278 const char *psz;
2279 } const aTypes[32] =
2280 {
2281#define STRENTRY(str) { sizeof(str) - 1, str }
2282 /* system */
2283 STRENTRY("Reserved0 "), /* 0x00 */
2284 STRENTRY("TSS16Avail "), /* 0x01 */
2285 STRENTRY("LDT "), /* 0x02 */
2286 STRENTRY("TSS16Busy "), /* 0x03 */
2287 STRENTRY("Call16 "), /* 0x04 */
2288 STRENTRY("Task "), /* 0x05 */
2289 STRENTRY("Int16 "), /* 0x06 */
2290 STRENTRY("Trap16 "), /* 0x07 */
2291 STRENTRY("Reserved8 "), /* 0x08 */
2292 STRENTRY("TSS32Avail "), /* 0x09 */
2293 STRENTRY("ReservedA "), /* 0x0a */
2294 STRENTRY("TSS32Busy "), /* 0x0b */
2295 STRENTRY("Call32 "), /* 0x0c */
2296 STRENTRY("ReservedD "), /* 0x0d */
2297 STRENTRY("Int32 "), /* 0x0e */
2298 STRENTRY("Trap32 "), /* 0x0f */
2299 /* non system */
2300 STRENTRY("DataRO "), /* 0x10 */
2301 STRENTRY("DataRO Accessed "), /* 0x11 */
2302 STRENTRY("DataRW "), /* 0x12 */
2303 STRENTRY("DataRW Accessed "), /* 0x13 */
2304 STRENTRY("DataDownRO "), /* 0x14 */
2305 STRENTRY("DataDownRO Accessed "), /* 0x15 */
2306 STRENTRY("DataDownRW "), /* 0x16 */
2307 STRENTRY("DataDownRW Accessed "), /* 0x17 */
2308 STRENTRY("CodeEO "), /* 0x18 */
2309 STRENTRY("CodeEO Accessed "), /* 0x19 */
2310 STRENTRY("CodeER "), /* 0x1a */
2311 STRENTRY("CodeER Accessed "), /* 0x1b */
2312 STRENTRY("CodeConfEO "), /* 0x1c */
2313 STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2314 STRENTRY("CodeConfER "), /* 0x1e */
2315 STRENTRY("CodeConfER Accessed ") /* 0x1f */
2316#undef SYSENTRY
2317 };
2318#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2319 char szMsg[128];
2320 char *psz = &szMsg[0];
2321 unsigned i = Desc.Gen.u1DescType << 4 | Desc.Gen.u4Type;
2322 memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2323 psz += aTypes[i].cch;
2324
2325 if (Desc.Gen.u1Present)
2326 ADD_STR(psz, "Present ");
2327 else
2328 ADD_STR(psz, "Not-Present ");
2329 if (Desc.Gen.u1Granularity)
2330 ADD_STR(psz, "Page ");
2331 if (Desc.Gen.u1DefBig)
2332 ADD_STR(psz, "32-bit ");
2333 else
2334 ADD_STR(psz, "16-bit ");
2335#undef ADD_STR
2336 *psz = '\0';
2337
2338 /*
2339 * Limit and Base and format the output.
2340 */
2341 uint32_t u32Limit = X86DESC_LIMIT(Desc);
2342 if (Desc.Gen.u1Granularity)
2343 u32Limit = u32Limit << PAGE_SHIFT | PAGE_OFFSET_MASK;
2344 uint32_t u32Base = X86DESC_BASE(Desc);
2345
2346 RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2347 Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2348}
2349
2350
2351/**
2352 * Dumps a descriptor.
2353 *
2354 * @param Desc Descriptor to dump.
2355 * @param Sel Selector number.
2356 * @param pszMsg Message to prepend the log entry with.
2357 */
2358VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2359{
2360 char szOutput[128];
2361 selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2362 Log(("%s: %s\n", pszMsg, szOutput));
2363 NOREF(szOutput[0]);
2364}
2365
2366
2367/**
2368 * Display the shadow gdt.
2369 *
2370 * @param pVM VM Handle.
2371 * @param pHlp The info helpers.
2372 * @param pszArgs Arguments, ignored.
2373 */
2374static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2375{
2376 pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2377 for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2378 {
2379 if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2380 {
2381 char szOutput[128];
2382 selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2383 const char *psz = "";
2384 if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2385 psz = " HyperCS";
2386 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2387 psz = " HyperDS";
2388 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2389 psz = " HyperCS64";
2390 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2391 psz = " HyperTSS";
2392 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2393 psz = " HyperTSSTrap08";
2394 pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2395 }
2396 }
2397}
2398
2399
2400/**
2401 * Display the guest gdt.
2402 *
2403 * @param pVM VM Handle.
2404 * @param pHlp The info helpers.
2405 * @param pszArgs Arguments, ignored.
2406 */
2407static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2408{
2409 /** @todo SMP support! */
2410 PVMCPU pVCpu = &pVM->aCpus[0];
2411
2412 VBOXGDTR GDTR;
2413 CPUMGetGuestGDTR(pVCpu, &GDTR);
2414 RTGCPTR GCPtrGDT = GDTR.pGdt;
2415 unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2416
2417 pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2418 for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2419 {
2420 X86DESC GDTE;
2421 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2422 if (RT_SUCCESS(rc))
2423 {
2424 if (GDTE.Gen.u1Present)
2425 {
2426 char szOutput[128];
2427 selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2428 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2429 }
2430 }
2431 else if (rc == VERR_PAGE_NOT_PRESENT)
2432 {
2433 if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2434 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2435 }
2436 else
2437 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2438 }
2439}
2440
2441
2442/**
2443 * Display the shadow ldt.
2444 *
2445 * @param pVM VM Handle.
2446 * @param pHlp The info helpers.
2447 * @param pszArgs Arguments, ignored.
2448 */
2449static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2450{
2451 unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2452 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2453 pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2454 for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2455 {
2456 if (paLDT[iLDT].Gen.u1Present)
2457 {
2458 char szOutput[128];
2459 selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2460 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2461 }
2462 }
2463}
2464
2465
2466/**
2467 * Display the guest ldt.
2468 *
2469 * @param pVM VM Handle.
2470 * @param pHlp The info helpers.
2471 * @param pszArgs Arguments, ignored.
2472 */
2473static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2474{
2475 /** @todo SMP support! */
2476 PVMCPU pVCpu = &pVM->aCpus[0];
2477
2478 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2479 if (!(SelLdt & X86_SEL_MASK))
2480 {
2481 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2482 return;
2483 }
2484
2485 RTGCPTR GCPtrLdt;
2486 unsigned cbLdt;
2487 int rc = SELMGetLDTFromSel(pVM, SelLdt, &GCPtrLdt, &cbLdt);
2488 if (RT_FAILURE(rc))
2489 {
2490 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): rc=%Rrc\n", SelLdt, rc);
2491 return;
2492 }
2493
2494 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RGv limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2495 unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2496 for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2497 {
2498 X86DESC LdtE;
2499 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2500 if (RT_SUCCESS(rc))
2501 {
2502 if (LdtE.Gen.u1Present)
2503 {
2504 char szOutput[128];
2505 selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2506 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2507 }
2508 }
2509 else if (rc == VERR_PAGE_NOT_PRESENT)
2510 {
2511 if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2512 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, GCPtrLdt);
2513 }
2514 else
2515 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, rc, GCPtrLdt);
2516 }
2517}
2518
2519
2520/**
2521 * Dumps the hypervisor GDT
2522 *
2523 * @param pVM VM handle.
2524 */
2525VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2526{
2527 DBGFR3Info(pVM, "gdt", NULL, NULL);
2528}
2529
2530
2531/**
2532 * Dumps the hypervisor LDT
2533 *
2534 * @param pVM VM handle.
2535 */
2536VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2537{
2538 DBGFR3Info(pVM, "ldt", NULL, NULL);
2539}
2540
2541
2542/**
2543 * Dumps the guest GDT
2544 *
2545 * @param pVM VM handle.
2546 */
2547VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2548{
2549 DBGFR3Info(pVM, "gdtguest", NULL, NULL);
2550}
2551
2552
2553/**
2554 * Dumps the guest LDT
2555 *
2556 * @param pVM VM handle.
2557 */
2558VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2559{
2560 DBGFR3Info(pVM, "ldtguest", NULL, NULL);
2561}
2562
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