PGMSavedState.cpp@ 30160

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1	/* $Id: PGMSavedState.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM
23	#include <VBox/pgm.h>
24	#include <VBox/stam.h>
25	#include <VBox/ssm.h>
26	#include <VBox/pdmdrv.h>
27	#include <VBox/pdmdev.h>
28	#include "PGMInternal.h"
29	#include <VBox/vm.h>
30	#include "PGMInline.h"
31
32	#include <VBox/param.h>
33	#include <VBox/err.h>
34
35	#include <iprt/asm.h>
36	#include <iprt/assert.h>
37	#include <iprt/crc32.h>
38	#include <iprt/mem.h>
39	#include <iprt/sha.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42
43
44	/*******************************************************************************
45	* Defined Constants And Macros *
46	*******************************************************************************/
47	/** Saved state data unit version.
48	* @todo remove the guest mappings from the saved state at next version change! */
49	#define PGM_SAVED_STATE_VERSION 12
50	/** Saved state before the balloon change. */
51	#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
52	/** Saved state data unit version used during 3.1 development, misses the RAM
53	* config. */
54	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
55	/** Saved state data unit version for 3.0 (pre teleportation). */
56	#define PGM_SAVED_STATE_VERSION_3_0_0 9
57	/** Saved state data unit version for 2.2.2 and later. */
58	#define PGM_SAVED_STATE_VERSION_2_2_2 8
59	/** Saved state data unit version for 2.2.0. */
60	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
61	/** Saved state data unit version. */
62	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
63
64
65	/** @name Sparse state record types
66	* @{ */
67	/** Zero page. No data. */
68	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
69	/** Raw page. */
70	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
71	/** Raw MMIO2 page. */
72	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
73	/** Zero MMIO2 page. */
74	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
75	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
76	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
77	/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
78	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
79	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
80	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
81	/** ROM protection (8-bit). */
82	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
83	/** The last record type. */
84	#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
85	/** End marker. */
86	#define PGM_STATE_REC_END UINT8_C(0xff)
87	/** Flag indicating that the data is preceeded by the page address.
88	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
89	* range ID and a 32-bit page index.
90	*/
91	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
92	/** @} */
93
94	/** The CRC-32 for a zero page. */
95	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
96	/** The CRC-32 for a zero half page. */
97	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
98
99
100	/*******************************************************************************
101	* Structures and Typedefs *
102	*******************************************************************************/
103	/** For loading old saved states. (pre-smp) */
104	typedef struct
105	{
106	/** If set no conflict checks are required. (boolean) */
107	bool fMappingsFixed;
108	/** Size of fixed mapping */
109	uint32_t cbMappingFixed;
110	/** Base address (GC) of fixed mapping */
111	RTGCPTR GCPtrMappingFixed;
112	/** A20 gate mask.
113	* Our current approach to A20 emulation is to let REM do it and don't bother
114	* anywhere else. The interesting guests will be operating with it enabled anyway.
115	* But should the need arise, we'll subject physical addresses to this mask. */
116	RTGCPHYS GCPhysA20Mask;
117	/** A20 gate state - boolean! */
118	bool fA20Enabled;
119	/** The guest paging mode. */
120	PGMMODE enmGuestMode;
121	} PGMOLD;
122
123
124	/*******************************************************************************
125	* Global Variables *
126	*******************************************************************************/
127	/** PGM fields to save/load. */
128
129	static const SSMFIELD s_aPGMFields[] =
130	{
131	SSMFIELD_ENTRY( PGM, fMappingsFixed),
132	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
133	SSMFIELD_ENTRY( PGM, cbMappingFixed),
134	SSMFIELD_ENTRY( PGM, cBalloonedPages),
135	SSMFIELD_ENTRY_TERM()
136	};
137
138	static const SSMFIELD s_aPGMFieldsPreBalloon[] =
139	{
140	SSMFIELD_ENTRY( PGM, fMappingsFixed),
141	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
142	SSMFIELD_ENTRY( PGM, cbMappingFixed),
143	SSMFIELD_ENTRY_TERM()
144	};
145
146	static const SSMFIELD s_aPGMCpuFields[] =
147	{
148	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
149	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
150	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
151	SSMFIELD_ENTRY_TERM()
152	};
153
154	static const SSMFIELD s_aPGMFields_Old[] =
155	{
156	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
157	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
158	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
159	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
160	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
161	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
162	SSMFIELD_ENTRY_TERM()
163	};
164
165
166	/**
167	* Find the ROM tracking structure for the given page.
168	*
169	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
170	* that it's a ROM page.
171	* @param pVM The VM handle.
172	* @param GCPhys The address of the ROM page.
173	*/
174	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
175	{
176	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
177	pRomRange;
178	pRomRange = pRomRange->CTX_SUFF(pNext))
179	{
180	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
181	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
182	return &pRomRange->aPages[off >> PAGE_SHIFT];
183	}
184	return NULL;
185	}
186
187
188	/**
189	* Prepares the ROM pages for a live save.
190	*
191	* @returns VBox status code.
192	* @param pVM The VM handle.
193	*/
194	static int pgmR3PrepRomPages(PVM pVM)
195	{
196	/*
197	* Initialize the live save tracking in the ROM page descriptors.
198	*/
199	pgmLock(pVM);
200	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
201	{
202	PPGMRAMRANGE pRamHint = NULL;;
203	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
204
205	for (uint32_t iPage = 0; iPage < cPages; iPage++)
206	{
207	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
208	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
209	pRom->aPages[iPage].LiveSave.fDirty = true;
210	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
211	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
212	{
213	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
214	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
215	else
216	{
217	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
218	PPGMPAGE pPage;
219	int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
220	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
221	if (RT_SUCCESS(rc))
222	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
223	else
224	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
225	}
226	}
227	}
228
229	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
230	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
231	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
232	}
233	pgmUnlock(pVM);
234
235	return VINF_SUCCESS;
236	}
237
238
239	/**
240	* Assigns IDs to the ROM ranges and saves them.
241	*
242	* @returns VBox status code.
243	* @param pVM The VM handle.
244	* @param pSSM Saved state handle.
245	*/
246	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
247	{
248	pgmLock(pVM);
249	uint8_t id = 1;
250	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
251	{
252	pRom->idSavedState = id;
253	SSMR3PutU8(pSSM, id);
254	SSMR3PutStrZ(pSSM, ""); /* device name */
255	SSMR3PutU32(pSSM, 0); /* device instance */
256	SSMR3PutU8(pSSM, 0); /* region */
257	SSMR3PutStrZ(pSSM, pRom->pszDesc);
258	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
259	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
260	if (RT_FAILURE(rc))
261	break;
262	}
263	pgmUnlock(pVM);
264	return SSMR3PutU8(pSSM, UINT8_MAX);
265	}
266
267
268	/**
269	* Loads the ROM range ID assignments.
270	*
271	* @returns VBox status code.
272	*
273	* @param pVM The VM handle.
274	* @param pSSM The saved state handle.
275	*/
276	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
277	{
278	Assert(PGMIsLockOwner(pVM));
279
280	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
281	pRom->idSavedState = UINT8_MAX;
282
283	for (;;)
284	{
285	/*
286	* Read the data.
287	*/
288	uint8_t id;
289	int rc = SSMR3GetU8(pSSM, &id);
290	if (RT_FAILURE(rc))
291	return rc;
292	if (id == UINT8_MAX)
293	{
294	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
295	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX,
296	("The \"%s\" ROM was not found in the saved state. Probably due to some misconfiguration\n",
297	pRom->pszDesc));
298	return VINF_SUCCESS; /* the end */
299	}
300	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
301
302	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
303	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
304	AssertLogRelRCReturn(rc, rc);
305
306	uint32_t uInstance;
307	SSMR3GetU32(pSSM, &uInstance);
308	uint8_t iRegion;
309	SSMR3GetU8(pSSM, &iRegion);
310
311	char szDesc[64];
312	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
313	AssertLogRelRCReturn(rc, rc);
314
315	RTGCPHYS GCPhys;
316	SSMR3GetGCPhys(pSSM, &GCPhys);
317	RTGCPHYS cb;
318	rc = SSMR3GetGCPhys(pSSM, &cb);
319	if (RT_FAILURE(rc))
320	return rc;
321	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
322	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
323
324	/*
325	* Locate a matching ROM range.
326	*/
327	AssertLogRelMsgReturn( uInstance == 0
328	&& iRegion == 0
329	&& szDevName[0] == '\0',
330	("GCPhys=%RGp %s\n", GCPhys, szDesc),
331	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
332	PPGMROMRANGE pRom;
333	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
334	{
335	if ( pRom->idSavedState == UINT8_MAX
336	&& !strcmp(pRom->pszDesc, szDesc))
337	{
338	pRom->idSavedState = id;
339	break;
340	}
341	}
342	if (!pRom)
343	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
344	} /* forever */
345	}
346
347
348	/**
349	* Scan ROM pages.
350	*
351	* @param pVM The VM handle.
352	*/
353	static void pgmR3ScanRomPages(PVM pVM)
354	{
355	/*
356	* The shadow ROMs.
357	*/
358	pgmLock(pVM);
359	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
360	{
361	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
362	{
363	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
364	for (uint32_t iPage = 0; iPage < cPages; iPage++)
365	{
366	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
367	if (pRomPage->LiveSave.fWrittenTo)
368	{
369	pRomPage->LiveSave.fWrittenTo = false;
370	if (!pRomPage->LiveSave.fDirty)
371	{
372	pRomPage->LiveSave.fDirty = true;
373	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
374	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
375	}
376	pRomPage->LiveSave.fDirtiedRecently = true;
377	}
378	else
379	pRomPage->LiveSave.fDirtiedRecently = false;
380	}
381	}
382	}
383	pgmUnlock(pVM);
384	}
385
386
387	/**
388	* Takes care of the virgin ROM pages in the first pass.
389	*
390	* This is an attempt at simplifying the handling of ROM pages a little bit.
391	* This ASSUMES that no new ROM ranges will be added and that they won't be
392	* relinked in any way.
393	*
394	* @param pVM The VM handle.
395	* @param pSSM The SSM handle.
396	* @param fLiveSave Whether we're in a live save or not.
397	*/
398	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
399	{
400	pgmLock(pVM);
401	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
402	{
403	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
404	for (uint32_t iPage = 0; iPage < cPages; iPage++)
405	{
406	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
407	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
408
409	/* Get the virgin page descriptor. */
410	PPGMPAGE pPage;
411	if (PGMROMPROT_IS_ROM(enmProt))
412	pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
413	else
414	pPage = &pRom->aPages[iPage].Virgin;
415
416	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
417	int rc = VINF_SUCCESS;
418	char abPage[PAGE_SIZE];
419	if ( !PGM_PAGE_IS_ZERO(pPage)
420	&& !PGM_PAGE_IS_BALLOONED(pPage))
421	{
422	void const *pvPage;
423	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
424	if (RT_SUCCESS(rc))
425	memcpy(abPage, pvPage, PAGE_SIZE);
426	}
427	else
428	ASMMemZeroPage(abPage);
429	pgmUnlock(pVM);
430	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
431
432	/* Save it. */
433	if (iPage > 0)
434	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
435	else
436	{
437	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
438	SSMR3PutU8(pSSM, pRom->idSavedState);
439	SSMR3PutU32(pSSM, iPage);
440	}
441	SSMR3PutU8(pSSM, (uint8_t)enmProt);
442	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
443	if (RT_FAILURE(rc))
444	return rc;
445
446	/* Update state. */
447	pgmLock(pVM);
448	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
449	if (fLiveSave)
450	{
451	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
452	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
453	pVM->pgm.s.LiveSave.cSavedPages++;
454	}
455	}
456	}
457	pgmUnlock(pVM);
458	return VINF_SUCCESS;
459	}
460
461
462	/**
463	* Saves dirty pages in the shadowed ROM ranges.
464	*
465	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
466	*
467	* @returns VBox status code.
468	* @param pVM The VM handle.
469	* @param pSSM The SSM handle.
470	* @param fLiveSave Whether it's a live save or not.
471	* @param fFinalPass Whether this is the final pass or not.
472	*/
473	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
474	{
475	/*
476	* The Shadowed ROMs.
477	*
478	* ASSUMES that the ROM ranges are fixed.
479	* ASSUMES that all the ROM ranges are mapped.
480	*/
481	pgmLock(pVM);
482	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
483	{
484	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
485	{
486	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
487	uint32_t iPrevPage = cPages;
488	for (uint32_t iPage = 0; iPage < cPages; iPage++)
489	{
490	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
491	if ( !fLiveSave
492	\|\| ( pRomPage->LiveSave.fDirty
493	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
494	&& !pRomPage->LiveSave.fWrittenTo)
495	\|\| fFinalPass
496	)
497	)
498	)
499	{
500	uint8_t abPage[PAGE_SIZE];
501	PGMROMPROT enmProt = pRomPage->enmProt;
502	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
503	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
504	bool fZero = PGM_PAGE_IS_ZERO(pPage) \|\| PGM_PAGE_IS_BALLOONED(pPage);
505	int rc = VINF_SUCCESS;
506	if (!fZero)
507	{
508	void const *pvPage;
509	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
510	if (RT_SUCCESS(rc))
511	memcpy(abPage, pvPage, PAGE_SIZE);
512	}
513	if (fLiveSave && RT_SUCCESS(rc))
514	{
515	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
516	pRomPage->LiveSave.fDirty = false;
517	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
518	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
519	pVM->pgm.s.LiveSave.cSavedPages++;
520	}
521	pgmUnlock(pVM);
522	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
523
524	if (iPage - 1U == iPrevPage && iPage > 0)
525	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
526	else
527	{
528	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
529	SSMR3PutU8(pSSM, pRom->idSavedState);
530	SSMR3PutU32(pSSM, iPage);
531	}
532	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
533	if (!fZero)
534	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
535	if (RT_FAILURE(rc))
536	return rc;
537
538	pgmLock(pVM);
539	iPrevPage = iPage;
540	}
541	/*
542	* In the final pass, make sure the protection is in sync.
543	*/
544	else if ( fFinalPass
545	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
546	{
547	PGMROMPROT enmProt = pRomPage->enmProt;
548	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
549	pgmUnlock(pVM);
550
551	if (iPage - 1U == iPrevPage && iPage > 0)
552	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
553	else
554	{
555	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
556	SSMR3PutU8(pSSM, pRom->idSavedState);
557	SSMR3PutU32(pSSM, iPage);
558	}
559	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
560	if (RT_FAILURE(rc))
561	return rc;
562
563	pgmLock(pVM);
564	iPrevPage = iPage;
565	}
566	}
567	}
568	}
569	pgmUnlock(pVM);
570	return VINF_SUCCESS;
571	}
572
573
574	/**
575	* Cleans up ROM pages after a live save.
576	*
577	* @param pVM The VM handle.
578	*/
579	static void pgmR3DoneRomPages(PVM pVM)
580	{
581	NOREF(pVM);
582	}
583
584
585	/**
586	* Prepares the MMIO2 pages for a live save.
587	*
588	* @returns VBox status code.
589	* @param pVM The VM handle.
590	*/
591	static int pgmR3PrepMmio2Pages(PVM pVM)
592	{
593	/*
594	* Initialize the live save tracking in the MMIO2 ranges.
595	* ASSUME nothing changes here.
596	*/
597	pgmLock(pVM);
598	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
599	{
600	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
601	pgmUnlock(pVM);
602
603	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
604	if (!paLSPages)
605	return VERR_NO_MEMORY;
606	for (uint32_t iPage = 0; iPage < cPages; iPage++)
607	{
608	/* Initialize it as a dirty zero page. */
609	paLSPages[iPage].fDirty = true;
610	paLSPages[iPage].cUnchangedScans = 0;
611	paLSPages[iPage].fZero = true;
612	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
613	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
614	}
615
616	pgmLock(pVM);
617	pMmio2->paLSPages = paLSPages;
618	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
619	}
620	pgmUnlock(pVM);
621	return VINF_SUCCESS;
622	}
623
624
625	/**
626	* Assigns IDs to the MMIO2 ranges and saves them.
627	*
628	* @returns VBox status code.
629	* @param pVM The VM handle.
630	* @param pSSM Saved state handle.
631	*/
632	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
633	{
634	pgmLock(pVM);
635	uint8_t id = 1;
636	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
637	{
638	pMmio2->idSavedState = id;
639	SSMR3PutU8(pSSM, id);
640	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pReg->szName);
641	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
642	SSMR3PutU8(pSSM, pMmio2->iRegion);
643	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
644	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
645	if (RT_FAILURE(rc))
646	break;
647	}
648	pgmUnlock(pVM);
649	return SSMR3PutU8(pSSM, UINT8_MAX);
650	}
651
652
653	/**
654	* Loads the MMIO2 range ID assignments.
655	*
656	* @returns VBox status code.
657	*
658	* @param pVM The VM handle.
659	* @param pSSM The saved state handle.
660	*/
661	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
662	{
663	Assert(PGMIsLockOwner(pVM));
664
665	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
666	pMmio2->idSavedState = UINT8_MAX;
667
668	for (;;)
669	{
670	/*
671	* Read the data.
672	*/
673	uint8_t id;
674	int rc = SSMR3GetU8(pSSM, &id);
675	if (RT_FAILURE(rc))
676	return rc;
677	if (id == UINT8_MAX)
678	{
679	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
680	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
681	return VINF_SUCCESS; /* the end */
682	}
683	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
684
685	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
686	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
687	AssertLogRelRCReturn(rc, rc);
688
689	uint32_t uInstance;
690	SSMR3GetU32(pSSM, &uInstance);
691	uint8_t iRegion;
692	SSMR3GetU8(pSSM, &iRegion);
693
694	char szDesc[64];
695	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
696	AssertLogRelRCReturn(rc, rc);
697
698	RTGCPHYS cb;
699	rc = SSMR3GetGCPhys(pSSM, &cb);
700	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
701
702	/*
703	* Locate a matching MMIO2 range.
704	*/
705	PPGMMMIO2RANGE pMmio2;
706	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
707	{
708	if ( pMmio2->idSavedState == UINT8_MAX
709	&& pMmio2->iRegion == iRegion
710	&& pMmio2->pDevInsR3->iInstance == uInstance
711	&& !strcmp(pMmio2->pDevInsR3->pReg->szName, szDevName))
712	{
713	pMmio2->idSavedState = id;
714	break;
715	}
716	}
717	if (!pMmio2)
718	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
719	szDesc, szDevName, uInstance, iRegion);
720
721	/*
722	* Validate the configuration, the size of the MMIO2 region should be
723	* the same.
724	*/
725	if (cb != pMmio2->RamRange.cb)
726	{
727	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
728	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
729	if (cb > pMmio2->RamRange.cb) /* bad idea? */
730	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
731	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
732	}
733	} /* forever */
734	}
735
736
737	/**
738	* Scans one MMIO2 page.
739	*
740	* @returns True if changed, false if unchanged.
741	*
742	* @param pVM The VM handle
743	* @param pbPage The page bits.
744	* @param pLSPage The live save tracking structure for the page.
745	*
746	*/
747	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
748	{
749	/*
750	* Special handling of zero pages.
751	*/
752	bool const fZero = pLSPage->fZero;
753	if (fZero)
754	{
755	if (ASMMemIsZeroPage(pbPage))
756	{
757	/* Not modified. */
758	if (pLSPage->fDirty)
759	pLSPage->cUnchangedScans++;
760	return false;
761	}
762
763	pLSPage->fZero = false;
764	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
765	}
766	else
767	{
768	/*
769	* CRC the first half, if it doesn't match the page is dirty and
770	* we won't check the 2nd half (we'll do that next time).
771	*/
772	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
773	if (u32CrcH1 == pLSPage->u32CrcH1)
774	{
775	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
776	if (u32CrcH2 == pLSPage->u32CrcH2)
777	{
778	/* Probably not modified. */
779	if (pLSPage->fDirty)
780	pLSPage->cUnchangedScans++;
781	return false;
782	}
783
784	pLSPage->u32CrcH2 = u32CrcH2;
785	}
786	else
787	{
788	pLSPage->u32CrcH1 = u32CrcH1;
789	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
790	&& ASMMemIsZeroPage(pbPage))
791	{
792	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
793	pLSPage->fZero = true;
794	}
795	}
796	}
797
798	/* dirty page path */
799	pLSPage->cUnchangedScans = 0;
800	if (!pLSPage->fDirty)
801	{
802	pLSPage->fDirty = true;
803	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
804	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
805	if (fZero)
806	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
807	}
808	return true;
809	}
810
811
812	/**
813	* Scan for MMIO2 page modifications.
814	*
815	* @param pVM The VM handle.
816	* @param uPass The pass number.
817	*/
818	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
819	{
820	/*
821	* Since this is a bit expensive we lower the scan rate after a little while.
822	*/
823	if ( ( (uPass & 3) != 0
824	&& uPass > 10)
825	\|\| uPass == SSM_PASS_FINAL)
826	return;
827
828	pgmLock(pVM); /* paranoia */
829	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
830	{
831	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
832	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
833	pgmUnlock(pVM);
834
835	for (uint32_t iPage = 0; iPage < cPages; iPage++)
836	{
837	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
838	pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
839	}
840
841	pgmLock(pVM);
842	}
843	pgmUnlock(pVM);
844
845	}
846
847
848	/**
849	* Save quiescent MMIO2 pages.
850	*
851	* @returns VBox status code.
852	* @param pVM The VM handle.
853	* @param pSSM The SSM handle.
854	* @param fLiveSave Whether it's a live save or not.
855	* @param uPass The pass number.
856	*/
857	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
858	{
859	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
860	* device that we wish to know about changes.) */
861
862	int rc = VINF_SUCCESS;
863	if (uPass == SSM_PASS_FINAL)
864	{
865	/*
866	* The mop up round.
867	*/
868	pgmLock(pVM);
869	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
870	pMmio2 && RT_SUCCESS(rc);
871	pMmio2 = pMmio2->pNextR3)
872	{
873	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
874	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
875	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
876	uint32_t iPageLast = cPages;
877	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
878	{
879	uint8_t u8Type;
880	if (!fLiveSave)
881	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
882	else
883	{
884	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
885	if ( !paLSPages[iPage].fDirty
886	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
887	{
888	if (paLSPages[iPage].fZero)
889	continue;
890
891	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
892	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
893	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
894	continue;
895	}
896	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
897	pVM->pgm.s.LiveSave.cSavedPages++;
898	}
899
900	if (iPage != 0 && iPage == iPageLast + 1)
901	rc = SSMR3PutU8(pSSM, u8Type);
902	else
903	{
904	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
905	SSMR3PutU8(pSSM, pMmio2->idSavedState);
906	rc = SSMR3PutU32(pSSM, iPage);
907	}
908	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
909	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
910	if (RT_FAILURE(rc))
911	break;
912	iPageLast = iPage;
913	}
914	}
915	pgmUnlock(pVM);
916	}
917	/*
918	* Reduce the rate after a little while since the current MMIO2 approach is
919	* a bit expensive.
920	* We position it two passes after the scan pass to avoid saving busy pages.
921	*/
922	else if ( uPass <= 10
923	\|\| (uPass & 3) == 2)
924	{
925	pgmLock(pVM);
926	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
927	pMmio2 && RT_SUCCESS(rc);
928	pMmio2 = pMmio2->pNextR3)
929	{
930	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
931	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
932	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
933	uint32_t iPageLast = cPages;
934	pgmUnlock(pVM);
935
936	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
937	{
938	/* Skip clean pages and pages which hasn't quiesced. */
939	if (!paLSPages[iPage].fDirty)
940	continue;
941	if (paLSPages[iPage].cUnchangedScans < 3)
942	continue;
943	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
944	continue;
945
946	/* Save it. */
947	bool const fZero = paLSPages[iPage].fZero;
948	uint8_t abPage[PAGE_SIZE];
949	if (!fZero)
950	{
951	memcpy(abPage, pbPage, PAGE_SIZE);
952	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
953	}
954
955	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
956	if (iPage != 0 && iPage == iPageLast + 1)
957	rc = SSMR3PutU8(pSSM, u8Type);
958	else
959	{
960	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
961	SSMR3PutU8(pSSM, pMmio2->idSavedState);
962	rc = SSMR3PutU32(pSSM, iPage);
963	}
964	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
965	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
966	if (RT_FAILURE(rc))
967	break;
968
969	/* Housekeeping. */
970	paLSPages[iPage].fDirty = false;
971	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
972	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
973	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
974	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
975	pVM->pgm.s.LiveSave.cSavedPages++;
976	iPageLast = iPage;
977	}
978
979	pgmLock(pVM);
980	}
981	pgmUnlock(pVM);
982	}
983
984	return rc;
985	}
986
987
988	/**
989	* Cleans up MMIO2 pages after a live save.
990	*
991	* @param pVM The VM handle.
992	*/
993	static void pgmR3DoneMmio2Pages(PVM pVM)
994	{
995	/*
996	* Free the tracking structures for the MMIO2 pages.
997	* We do the freeing outside the lock in case the VM is running.
998	*/
999	pgmLock(pVM);
1000	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
1001	{
1002	void *pvMmio2ToFree = pMmio2->paLSPages;
1003	if (pvMmio2ToFree)
1004	{
1005	pMmio2->paLSPages = NULL;
1006	pgmUnlock(pVM);
1007	MMR3HeapFree(pvMmio2ToFree);
1008	pgmLock(pVM);
1009	}
1010	}
1011	pgmUnlock(pVM);
1012	}
1013
1014
1015	/**
1016	* Prepares the RAM pages for a live save.
1017	*
1018	* @returns VBox status code.
1019	* @param pVM The VM handle.
1020	*/
1021	static int pgmR3PrepRamPages(PVM pVM)
1022	{
1023
1024	/*
1025	* Try allocating tracking structures for the ram ranges.
1026	*
1027	* To avoid lock contention, we leave the lock every time we're allocating
1028	* a new array. This means we'll have to ditch the allocation and start
1029	* all over again if the RAM range list changes in-between.
1030	*
1031	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1032	* for cleaning up.
1033	*/
1034	PPGMRAMRANGE pCur;
1035	pgmLock(pVM);
1036	do
1037	{
1038	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1039	{
1040	if ( !pCur->paLSPages
1041	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1042	{
1043	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1044	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1045	pgmUnlock(pVM);
1046	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1047	if (!paLSPages)
1048	return VERR_NO_MEMORY;
1049	pgmLock(pVM);
1050	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1051	{
1052	pgmUnlock(pVM);
1053	MMR3HeapFree(paLSPages);
1054	pgmLock(pVM);
1055	break; /* try again */
1056	}
1057	pCur->paLSPages = paLSPages;
1058
1059	/*
1060	* Initialize the array.
1061	*/
1062	uint32_t iPage = cPages;
1063	while (iPage-- > 0)
1064	{
1065	/** @todo yield critsect! (after moving this away from EMT0) */
1066	PCPGMPAGE pPage = &pCur->aPages[iPage];
1067	paLSPages[iPage].cDirtied = 0;
1068	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1069	paLSPages[iPage].fWriteMonitored = 0;
1070	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1071	paLSPages[iPage].u2Reserved = 0;
1072	switch (PGM_PAGE_GET_TYPE(pPage))
1073	{
1074	case PGMPAGETYPE_RAM:
1075	if ( PGM_PAGE_IS_ZERO(pPage)
1076	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1077	{
1078	paLSPages[iPage].fZero = 1;
1079	paLSPages[iPage].fShared = 0;
1080	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1081	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1082	#endif
1083	}
1084	else if (PGM_PAGE_IS_SHARED(pPage))
1085	{
1086	paLSPages[iPage].fZero = 0;
1087	paLSPages[iPage].fShared = 1;
1088	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1089	paLSPages[iPage].u32Crc = UINT32_MAX;
1090	#endif
1091	}
1092	else
1093	{
1094	paLSPages[iPage].fZero = 0;
1095	paLSPages[iPage].fShared = 0;
1096	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1097	paLSPages[iPage].u32Crc = UINT32_MAX;
1098	#endif
1099	}
1100	paLSPages[iPage].fIgnore = 0;
1101	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1102	break;
1103
1104	case PGMPAGETYPE_ROM_SHADOW:
1105	case PGMPAGETYPE_ROM:
1106	{
1107	paLSPages[iPage].fZero = 0;
1108	paLSPages[iPage].fShared = 0;
1109	paLSPages[iPage].fDirty = 0;
1110	paLSPages[iPage].fIgnore = 1;
1111	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1112	paLSPages[iPage].u32Crc = UINT32_MAX;
1113	#endif
1114	pVM->pgm.s.LiveSave.cIgnoredPages++;
1115	break;
1116	}
1117
1118	default:
1119	AssertMsgFailed(("%R[pgmpage]", pPage));
1120	case PGMPAGETYPE_MMIO2:
1121	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1122	paLSPages[iPage].fZero = 0;
1123	paLSPages[iPage].fShared = 0;
1124	paLSPages[iPage].fDirty = 0;
1125	paLSPages[iPage].fIgnore = 1;
1126	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1127	paLSPages[iPage].u32Crc = UINT32_MAX;
1128	#endif
1129	pVM->pgm.s.LiveSave.cIgnoredPages++;
1130	break;
1131
1132	case PGMPAGETYPE_MMIO:
1133	paLSPages[iPage].fZero = 0;
1134	paLSPages[iPage].fShared = 0;
1135	paLSPages[iPage].fDirty = 0;
1136	paLSPages[iPage].fIgnore = 1;
1137	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1138	paLSPages[iPage].u32Crc = UINT32_MAX;
1139	#endif
1140	pVM->pgm.s.LiveSave.cIgnoredPages++;
1141	break;
1142	}
1143	}
1144	}
1145	}
1146	} while (pCur);
1147	pgmUnlock(pVM);
1148
1149	return VINF_SUCCESS;
1150	}
1151
1152
1153	/**
1154	* Saves the RAM configuration.
1155	*
1156	* @returns VBox status code.
1157	* @param pVM The VM handle.
1158	* @param pSSM The saved state handle.
1159	*/
1160	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1161	{
1162	uint32_t cbRamHole = 0;
1163	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1164	AssertRCReturn(rc, rc);
1165
1166	uint64_t cbRam = 0;
1167	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1168	AssertRCReturn(rc, rc);
1169
1170	SSMR3PutU32(pSSM, cbRamHole);
1171	return SSMR3PutU64(pSSM, cbRam);
1172	}
1173
1174
1175	/**
1176	* Loads and verifies the RAM configuration.
1177	*
1178	* @returns VBox status code.
1179	* @param pVM The VM handle.
1180	* @param pSSM The saved state handle.
1181	*/
1182	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1183	{
1184	uint32_t cbRamHoleCfg = 0;
1185	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1186	AssertRCReturn(rc, rc);
1187
1188	uint64_t cbRamCfg = 0;
1189	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1190	AssertRCReturn(rc, rc);
1191
1192	uint32_t cbRamHoleSaved;
1193	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1194
1195	uint64_t cbRamSaved;
1196	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1197	AssertRCReturn(rc, rc);
1198
1199	if ( cbRamHoleCfg != cbRamHoleSaved
1200	\|\| cbRamCfg != cbRamSaved)
1201	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1202	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1203	return VINF_SUCCESS;
1204	}
1205
1206	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1207
1208	/**
1209	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1210	* info with it.
1211	*
1212	* @param pVM The VM handle.
1213	* @param pCur The current RAM range.
1214	* @param paLSPages The current array of live save page tracking
1215	* structures.
1216	* @param iPage The page index.
1217	*/
1218	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1219	{
1220	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1221	void const *pvPage;
1222	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1223	if (RT_SUCCESS(rc))
1224	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1225	else
1226	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1227	}
1228
1229
1230	/**
1231	* Verifies the CRC-32 for a page given it's raw bits.
1232	*
1233	* @param pvPage The page bits.
1234	* @param pCur The current RAM range.
1235	* @param paLSPages The current array of live save page tracking
1236	* structures.
1237	* @param iPage The page index.
1238	*/
1239	static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1240	{
1241	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1242	{
1243	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1244	Assert((!PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) && !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage])) \|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1245	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1246	("%08x != %08x for %RGp %R[pgmpage]\n", paLSPages[iPage].u32Crc, u32Crc,
1247	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1248	}
1249	}
1250
1251
1252	/**
1253	* Verfies the CRC-32 for a RAM page.
1254	*
1255	* @param pVM The VM handle.
1256	* @param pCur The current RAM range.
1257	* @param paLSPages The current array of live save page tracking
1258	* structures.
1259	* @param iPage The page index.
1260	*/
1261	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1262	{
1263	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1264	{
1265	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1266	void const *pvPage;
1267	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1268	if (RT_SUCCESS(rc))
1269	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage);
1270	}
1271	}
1272
1273	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1274
1275	/**
1276	* Scan for RAM page modifications and reprotect them.
1277	*
1278	* @param pVM The VM handle.
1279	* @param fFinalPass Whether this is the final pass or not.
1280	*/
1281	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1282	{
1283	/*
1284	* The RAM.
1285	*/
1286	RTGCPHYS GCPhysCur = 0;
1287	PPGMRAMRANGE pCur;
1288	pgmLock(pVM);
1289	do
1290	{
1291	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1292	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1293	{
1294	if ( pCur->GCPhysLast > GCPhysCur
1295	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1296	{
1297	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1298	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1299	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1300	GCPhysCur = 0;
1301	for (; iPage < cPages; iPage++)
1302	{
1303	/* Do yield first. */
1304	if ( !fFinalPass
1305	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1306	&& (iPage & 0x7ff) == 0x100
1307	#endif
1308	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1309	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1310	{
1311	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1312	break; /* restart */
1313	}
1314
1315	/* Skip already ignored pages. */
1316	if (paLSPages[iPage].fIgnore)
1317	continue;
1318
1319	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1320	{
1321	/*
1322	* A RAM page.
1323	*/
1324	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1325	{
1326	case PGM_PAGE_STATE_ALLOCATED:
1327	/** @todo Optimize this: Don't always re-enable write
1328	* monitoring if the page is known to be very busy. */
1329	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1330	{
1331	Assert(paLSPages[iPage].fWriteMonitored);
1332	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1333	Assert(pVM->pgm.s.cWrittenToPages > 0);
1334	pVM->pgm.s.cWrittenToPages--;
1335	}
1336	else
1337	{
1338	Assert(!paLSPages[iPage].fWriteMonitored);
1339	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1340	}
1341
1342	if (!paLSPages[iPage].fDirty)
1343	{
1344	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1345	if (paLSPages[iPage].fZero)
1346	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1347	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1348	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1349	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1350	}
1351
1352	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1353	pVM->pgm.s.cMonitoredPages++;
1354	paLSPages[iPage].fWriteMonitored = 1;
1355	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1356	paLSPages[iPage].fDirty = 1;
1357	paLSPages[iPage].fZero = 0;
1358	paLSPages[iPage].fShared = 0;
1359	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1360	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1361	#endif
1362	break;
1363
1364	case PGM_PAGE_STATE_WRITE_MONITORED:
1365	Assert(paLSPages[iPage].fWriteMonitored);
1366	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1367	{
1368	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1369	if (paLSPages[iPage].fWriteMonitoredJustNow)
1370	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1371	else
1372	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1373	#endif
1374	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1375	}
1376	else
1377	{
1378	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1379	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1380	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1381	#endif
1382	if (!paLSPages[iPage].fDirty)
1383	{
1384	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1385	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1386	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1387	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1388	}
1389	}
1390	break;
1391
1392	case PGM_PAGE_STATE_ZERO:
1393	if (!paLSPages[iPage].fZero)
1394	{
1395	if (!paLSPages[iPage].fDirty)
1396	{
1397	paLSPages[iPage].fDirty = 1;
1398	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1399	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1400	}
1401	paLSPages[iPage].fZero = 1;
1402	paLSPages[iPage].fShared = 0;
1403	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1404	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1405	#endif
1406	}
1407	break;
1408
1409	case PGM_PAGE_STATE_BALLOONED:
1410	if (!paLSPages[iPage].fZero)
1411	{
1412	if (!paLSPages[iPage].fDirty)
1413	{
1414	paLSPages[iPage].fDirty = 1;
1415	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1416	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1417	}
1418	paLSPages[iPage].fZero = 1;
1419	paLSPages[iPage].fShared = 0;
1420	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1421	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1422	#endif
1423	}
1424	break;
1425
1426	case PGM_PAGE_STATE_SHARED:
1427	if (!paLSPages[iPage].fShared)
1428	{
1429	if (!paLSPages[iPage].fDirty)
1430	{
1431	paLSPages[iPage].fDirty = 1;
1432	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1433	if (paLSPages[iPage].fZero)
1434	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1435	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1436	}
1437	paLSPages[iPage].fZero = 0;
1438	paLSPages[iPage].fShared = 1;
1439	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1440	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1441	#endif
1442	}
1443	break;
1444	}
1445	}
1446	else
1447	{
1448	/*
1449	* All other types => Ignore the page.
1450	*/
1451	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1452	paLSPages[iPage].fIgnore = 1;
1453	if (paLSPages[iPage].fWriteMonitored)
1454	{
1455	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1456	* pages! */
1457	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1458	{
1459	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1460	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1461	Assert(pVM->pgm.s.cMonitoredPages > 0);
1462	pVM->pgm.s.cMonitoredPages--;
1463	}
1464	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1465	{
1466	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1467	Assert(pVM->pgm.s.cWrittenToPages > 0);
1468	pVM->pgm.s.cWrittenToPages--;
1469	}
1470	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1471	}
1472
1473	/** @todo the counting doesn't quite work out here. fix later? */
1474	if (paLSPages[iPage].fDirty)
1475	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1476	else
1477	{
1478	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1479	if (paLSPages[iPage].fZero)
1480	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1481	}
1482	pVM->pgm.s.LiveSave.cIgnoredPages++;
1483	}
1484	} /* for each page in range */
1485
1486	if (GCPhysCur != 0)
1487	break; /* Yield + ramrange change */
1488	GCPhysCur = pCur->GCPhysLast;
1489	}
1490	} /* for each range */
1491	} while (pCur);
1492	pgmUnlock(pVM);
1493	}
1494
1495
1496	/**
1497	* Save quiescent RAM pages.
1498	*
1499	* @returns VBox status code.
1500	* @param pVM The VM handle.
1501	* @param pSSM The SSM handle.
1502	* @param fLiveSave Whether it's a live save or not.
1503	* @param uPass The pass number.
1504	*/
1505	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1506	{
1507	/*
1508	* The RAM.
1509	*/
1510	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1511	RTGCPHYS GCPhysCur = 0;
1512	PPGMRAMRANGE pCur;
1513	pgmLock(pVM);
1514	do
1515	{
1516	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1517	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1518	{
1519	if ( pCur->GCPhysLast > GCPhysCur
1520	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1521	{
1522	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1523	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1524	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1525	GCPhysCur = 0;
1526	for (; iPage < cPages; iPage++)
1527	{
1528	/* Do yield first. */
1529	if ( uPass != SSM_PASS_FINAL
1530	&& (iPage & 0x7ff) == 0x100
1531	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1532	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1533	{
1534	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1535	break; /* restart */
1536	}
1537
1538	/*
1539	* Only save pages that haven't changed since last scan and are dirty.
1540	*/
1541	if ( uPass != SSM_PASS_FINAL
1542	&& paLSPages)
1543	{
1544	if (!paLSPages[iPage].fDirty)
1545	continue;
1546	if (paLSPages[iPage].fWriteMonitoredJustNow)
1547	continue;
1548	if (paLSPages[iPage].fIgnore)
1549	continue;
1550	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM) /* in case of recent ramppings */
1551	continue;
1552	if ( PGM_PAGE_GET_STATE(&pCur->aPages[iPage])
1553	!= ( paLSPages[iPage].fZero
1554	? PGM_PAGE_STATE_ZERO
1555	: paLSPages[iPage].fShared
1556	? PGM_PAGE_STATE_SHARED
1557	: PGM_PAGE_STATE_WRITE_MONITORED))
1558	continue;
1559	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1560	continue;
1561	}
1562	else
1563	{
1564	if ( paLSPages
1565	&& !paLSPages[iPage].fDirty
1566	&& !paLSPages[iPage].fIgnore)
1567	{
1568	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1569	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1570	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1571	#endif
1572	continue;
1573	}
1574	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1575	continue;
1576	}
1577
1578	/*
1579	* Do the saving outside the PGM critsect since SSM may block on I/O.
1580	*/
1581	int rc;
1582	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1583	bool fZero = PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) \|\| PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]);
1584
1585	if (!fZero)
1586	{
1587	/*
1588	* Copy the page and then save it outside the lock (since any
1589	* SSM call may block).
1590	*/
1591	uint8_t abPage[PAGE_SIZE];
1592	void const *pvPage;
1593	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1594	if (RT_SUCCESS(rc))
1595	{
1596	memcpy(abPage, pvPage, PAGE_SIZE);
1597	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1598	if (paLSPages)
1599	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage);
1600	#endif
1601	}
1602	pgmUnlock(pVM);
1603	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1604
1605	if (GCPhys == GCPhysLast + PAGE_SIZE)
1606	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1607	else
1608	{
1609	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1610	SSMR3PutGCPhys(pSSM, GCPhys);
1611	}
1612	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1613	}
1614	else
1615	{
1616	/*
1617	* Dirty zero page.
1618	*/
1619	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1620	if (paLSPages)
1621	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1622	#endif
1623	pgmUnlock(pVM);
1624
1625	if (GCPhys == GCPhysLast + PAGE_SIZE)
1626	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1627	else
1628	{
1629	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1630	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1631	}
1632	}
1633	if (RT_FAILURE(rc))
1634	return rc;
1635
1636	pgmLock(pVM);
1637	GCPhysLast = GCPhys;
1638	if (paLSPages)
1639	{
1640	paLSPages[iPage].fDirty = 0;
1641	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1642	if (fZero)
1643	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1644	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1645	pVM->pgm.s.LiveSave.cSavedPages++;
1646	}
1647	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1648	{
1649	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1650	break; /* restart */
1651	}
1652
1653	} /* for each page in range */
1654
1655	if (GCPhysCur != 0)
1656	break; /* Yield + ramrange change */
1657	GCPhysCur = pCur->GCPhysLast;
1658	}
1659	} /* for each range */
1660	} while (pCur);
1661	pgmUnlock(pVM);
1662
1663	return VINF_SUCCESS;
1664	}
1665
1666
1667	/**
1668	* Cleans up RAM pages after a live save.
1669	*
1670	* @param pVM The VM handle.
1671	*/
1672	static void pgmR3DoneRamPages(PVM pVM)
1673	{
1674	/*
1675	* Free the tracking arrays and disable write monitoring.
1676	*
1677	* Play nice with the PGM lock in case we're called while the VM is still
1678	* running. This means we have to delay the freeing since we wish to use
1679	* paLSPages as an indicator of which RAM ranges which we need to scan for
1680	* write monitored pages.
1681	*/
1682	void *pvToFree = NULL;
1683	PPGMRAMRANGE pCur;
1684	uint32_t cMonitoredPages = 0;
1685	pgmLock(pVM);
1686	do
1687	{
1688	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1689	{
1690	if (pCur->paLSPages)
1691	{
1692	if (pvToFree)
1693	{
1694	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1695	pgmUnlock(pVM);
1696	MMR3HeapFree(pvToFree);
1697	pvToFree = NULL;
1698	pgmLock(pVM);
1699	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1700	break; /* start over again. */
1701	}
1702
1703	pvToFree = pCur->paLSPages;
1704	pCur->paLSPages = NULL;
1705
1706	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1707	while (iPage--)
1708	{
1709	PPGMPAGE pPage = &pCur->aPages[iPage];
1710	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1711	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1712	{
1713	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1714	cMonitoredPages++;
1715	}
1716	}
1717	}
1718	}
1719	} while (pCur);
1720
1721	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1722	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1723	pVM->pgm.s.cMonitoredPages = 0;
1724	else
1725	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1726
1727	pgmUnlock(pVM);
1728
1729	MMR3HeapFree(pvToFree);
1730	pvToFree = NULL;
1731	}
1732
1733
1734	/**
1735	* Execute a live save pass.
1736	*
1737	* @returns VBox status code.
1738	*
1739	* @param pVM The VM handle.
1740	* @param pSSM The SSM handle.
1741	*/
1742	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1743	{
1744	int rc;
1745
1746	/*
1747	* Save the MMIO2 and ROM range IDs in pass 0.
1748	*/
1749	if (uPass == 0)
1750	{
1751	rc = pgmR3SaveRamConfig(pVM, pSSM);
1752	if (RT_FAILURE(rc))
1753	return rc;
1754	rc = pgmR3SaveRomRanges(pVM, pSSM);
1755	if (RT_FAILURE(rc))
1756	return rc;
1757	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1758	if (RT_FAILURE(rc))
1759	return rc;
1760	}
1761	/*
1762	* Reset the page-per-second estimate to avoid inflation by the initial
1763	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1764	*/
1765	else if (uPass == 7)
1766	{
1767	pVM->pgm.s.LiveSave.cSavedPages = 0;
1768	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1769	}
1770
1771	/*
1772	* Do the scanning.
1773	*/
1774	pgmR3ScanRomPages(pVM);
1775	pgmR3ScanMmio2Pages(pVM, uPass);
1776	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1777	pgmR3PoolClearAll(pVM); /** @todo this could perhaps be optimized a bit. */
1778
1779	/*
1780	* Save the pages.
1781	*/
1782	if (uPass == 0)
1783	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1784	else
1785	rc = VINF_SUCCESS;
1786	if (RT_SUCCESS(rc))
1787	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1788	if (RT_SUCCESS(rc))
1789	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1790	if (RT_SUCCESS(rc))
1791	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1792	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1793
1794	return rc;
1795	}
1796
1797
1798	/**
1799	* Votes on whether the live save phase is done or not.
1800	*
1801	* @returns VBox status code.
1802	*
1803	* @param pVM The VM handle.
1804	* @param pSSM The SSM handle.
1805	* @param uPass The data pass.
1806	*/
1807	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1808	{
1809	/*
1810	* Update and calculate parameters used in the decision making.
1811	*/
1812	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1813
1814	/* update history. */
1815	pgmLock(pVM);
1816	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1817	pgmUnlock(pVM);
1818	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1819	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1820	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1821	+ cWrittenToPages;
1822	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1823	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1824	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1825
1826	/* calc shortterm average (4 passes). */
1827	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1828	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1829	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1830	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1831	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1832	uint32_t const cDirtyPagesShort = cTotal / 4;
1833	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1834
1835	/* calc longterm average. */
1836	cTotal = 0;
1837	if (uPass < cHistoryEntries)
1838	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1839	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1840	else
1841	for (i = 0; i < cHistoryEntries; i++)
1842	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1843	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1844	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1845
1846	/* estimate the speed */
1847	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1848	uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1849	/ ((long double)cNsElapsed / 1000000000.0) );
1850	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1851
1852	/*
1853	* Try make a decision.
1854	*/
1855	if ( cDirtyPagesShort <= cDirtyPagesLong
1856	&& ( cDirtyNow <= cDirtyPagesShort
1857	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1858	)
1859	)
1860	{
1861	if (uPass > 10)
1862	{
1863	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1864	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1865	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1866	if (cMsMaxDowntime < 32)
1867	cMsMaxDowntime = 32;
1868	if ( ( cMsLeftLong <= cMsMaxDowntime
1869	&& cMsLeftShort < cMsMaxDowntime)
1870	\|\| cMsLeftShort < cMsMaxDowntime / 2
1871	)
1872	{
1873	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1874	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1875	return VINF_SUCCESS;
1876	}
1877	}
1878	else
1879	{
1880	if ( ( cDirtyPagesShort <= 128
1881	&& cDirtyPagesLong <= 1024)
1882	\|\| cDirtyPagesLong <= 256
1883	)
1884	{
1885	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1886	return VINF_SUCCESS;
1887	}
1888	}
1889	}
1890	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1891	}
1892
1893
1894	/**
1895	* Prepare for a live save operation.
1896	*
1897	* This will attempt to allocate and initialize the tracking structures. It
1898	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1899	* pgmR3SaveDone will do the cleanups.
1900	*
1901	* @returns VBox status code.
1902	*
1903	* @param pVM The VM handle.
1904	* @param pSSM The SSM handle.
1905	*/
1906	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1907	{
1908	/*
1909	* Indicate that we will be using the write monitoring.
1910	*/
1911	pgmLock(pVM);
1912	/** @todo find a way of mediating this when more users are added. */
1913	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1914	{
1915	pgmUnlock(pVM);
1916	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1917	}
1918	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1919	pgmUnlock(pVM);
1920
1921	/*
1922	* Initialize the statistics.
1923	*/
1924	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1925	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1926	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1927	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1928	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1929	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1930	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1931	pVM->pgm.s.LiveSave.fActive = true;
1932	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
1933	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
1934	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
1935	pVM->pgm.s.LiveSave.cSavedPages = 0;
1936	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1937	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
1938
1939	/*
1940	* Per page type.
1941	*/
1942	int rc = pgmR3PrepRomPages(pVM);
1943	if (RT_SUCCESS(rc))
1944	rc = pgmR3PrepMmio2Pages(pVM);
1945	if (RT_SUCCESS(rc))
1946	rc = pgmR3PrepRamPages(pVM);
1947	return rc;
1948	}
1949
1950
1951	/**
1952	* Execute state save operation.
1953	*
1954	* @returns VBox status code.
1955	* @param pVM VM Handle.
1956	* @param pSSM SSM operation handle.
1957	*/
1958	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1959	{
1960	int rc;
1961	unsigned i;
1962	PPGM pPGM = &pVM->pgm.s;
1963
1964	/*
1965	* Lock PGM and set the no-more-writes indicator.
1966	*/
1967	pgmLock(pVM);
1968	pVM->pgm.s.fNoMorePhysWrites = true;
1969
1970	/*
1971	* Save basic data (required / unaffected by relocation).
1972	*/
1973	bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
1974	pVM->pgm.s.fMappingsFixed \|= pVM->pgm.s.fMappingsFixedRestored;
1975	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
1976	pVM->pgm.s.fMappingsFixed = fMappingsFixed;
1977
1978	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1979	SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]);
1980
1981	/*
1982	* The guest mappings.
1983	*/
1984	i = 0;
1985	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1986	{
1987	SSMR3PutU32( pSSM, i);
1988	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1989	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
1990	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1991	}
1992	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1993
1994	/*
1995	* Save the (remainder of the) memory.
1996	*/
1997	if (RT_SUCCESS(rc))
1998	{
1999	if (pVM->pgm.s.LiveSave.fActive)
2000	{
2001	pgmR3ScanRomPages(pVM);
2002	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2003	pgmR3ScanRamPages(pVM, true /fFinalPass/);
2004
2005	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
2006	if (RT_SUCCESS(rc))
2007	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2008	if (RT_SUCCESS(rc))
2009	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2010	}
2011	else
2012	{
2013	rc = pgmR3SaveRamConfig(pVM, pSSM);
2014	if (RT_SUCCESS(rc))
2015	rc = pgmR3SaveRomRanges(pVM, pSSM);
2016	if (RT_SUCCESS(rc))
2017	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2018	if (RT_SUCCESS(rc))
2019	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
2020	if (RT_SUCCESS(rc))
2021	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
2022	if (RT_SUCCESS(rc))
2023	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2024	if (RT_SUCCESS(rc))
2025	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2026	}
2027	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2028	}
2029
2030	pgmUnlock(pVM);
2031	return rc;
2032	}
2033
2034
2035	/**
2036	* Cleans up after an save state operation.
2037	*
2038	* @returns VBox status code.
2039	* @param pVM VM Handle.
2040	* @param pSSM SSM operation handle.
2041	*/
2042	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2043	{
2044	/*
2045	* Do per page type cleanups first.
2046	*/
2047	if (pVM->pgm.s.LiveSave.fActive)
2048	{
2049	pgmR3DoneRomPages(pVM);
2050	pgmR3DoneMmio2Pages(pVM);
2051	pgmR3DoneRamPages(pVM);
2052	}
2053
2054	/*
2055	* Clear the live save indicator and disengage write monitoring.
2056	*/
2057	pgmLock(pVM);
2058	pVM->pgm.s.LiveSave.fActive = false;
2059	/** @todo this is blindly assuming that we're the only user of write
2060	* monitoring. Fix this when more users are added. */
2061	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2062	pgmUnlock(pVM);
2063
2064	return VINF_SUCCESS;
2065	}
2066
2067
2068	/**
2069	* Prepare state load operation.
2070	*
2071	* @returns VBox status code.
2072	* @param pVM VM Handle.
2073	* @param pSSM SSM operation handle.
2074	*/
2075	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2076	{
2077	/*
2078	* Call the reset function to make sure all the memory is cleared.
2079	*/
2080	PGMR3Reset(pVM);
2081	pVM->pgm.s.LiveSave.fActive = false;
2082	NOREF(pSSM);
2083	return VINF_SUCCESS;
2084	}
2085
2086
2087	/**
2088	* Load an ignored page.
2089	*
2090	* @returns VBox status code.
2091	* @param pSSM The saved state handle.
2092	*/
2093	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2094	{
2095	uint8_t abPage[PAGE_SIZE];
2096	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2097	}
2098
2099
2100	/**
2101	* Loads a page without any bits in the saved state, i.e. making sure it's
2102	* really zero.
2103	*
2104	* @returns VBox status code.
2105	* @param pVM The VM handle.
2106	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2107	* state).
2108	* @param pPage The guest page tracking structure.
2109	* @param GCPhys The page address.
2110	* @param pRam The ram range (logging).
2111	*/
2112	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2113	{
2114	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2115	&& uType != PGMPAGETYPE_INVALID)
2116	return VERR_SSM_UNEXPECTED_DATA;
2117
2118	/* I think this should be sufficient. */
2119	if ( !PGM_PAGE_IS_ZERO(pPage)
2120	&& !PGM_PAGE_IS_BALLOONED(pPage))
2121	return VERR_SSM_UNEXPECTED_DATA;
2122
2123	NOREF(pVM);
2124	NOREF(GCPhys);
2125	NOREF(pRam);
2126	return VINF_SUCCESS;
2127	}
2128
2129
2130	/**
2131	* Loads a page from the saved state.
2132	*
2133	* @returns VBox status code.
2134	* @param pVM The VM handle.
2135	* @param pSSM The SSM handle.
2136	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2137	* state).
2138	* @param pPage The guest page tracking structure.
2139	* @param GCPhys The page address.
2140	* @param pRam The ram range (logging).
2141	*/
2142	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2143	{
2144	/*
2145	* Match up the type, dealing with MMIO2 aliases (dropped).
2146	*/
2147	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2148	\|\| uType == PGMPAGETYPE_INVALID,
2149	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2150	VERR_SSM_UNEXPECTED_DATA);
2151
2152	/*
2153	* Load the page.
2154	*/
2155	void *pvPage;
2156	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2157	if (RT_SUCCESS(rc))
2158	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2159
2160	return rc;
2161	}
2162
2163
2164	/**
2165	* Loads a page (counter part to pgmR3SavePage).
2166	*
2167	* @returns VBox status code, fully bitched errors.
2168	* @param pVM The VM handle.
2169	* @param pSSM The SSM handle.
2170	* @param uType The page type.
2171	* @param pPage The page.
2172	* @param GCPhys The page address.
2173	* @param pRam The RAM range (for error messages).
2174	*/
2175	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2176	{
2177	uint8_t uState;
2178	int rc = SSMR3GetU8(pSSM, &uState);
2179	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2180	if (uState == 0 /* zero */)
2181	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2182	else if (uState == 1)
2183	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2184	else
2185	rc = VERR_INTERNAL_ERROR;
2186	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2187	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2188	rc);
2189	return VINF_SUCCESS;
2190	}
2191
2192
2193	/**
2194	* Loads a shadowed ROM page.
2195	*
2196	* @returns VBox status code, errors are fully bitched.
2197	* @param pVM The VM handle.
2198	* @param pSSM The saved state handle.
2199	* @param pPage The page.
2200	* @param GCPhys The page address.
2201	* @param pRam The RAM range (for error messages).
2202	*/
2203	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2204	{
2205	/*
2206	* Load and set the protection first, then load the two pages, the first
2207	* one is the active the other is the passive.
2208	*/
2209	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2210	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2211
2212	uint8_t uProt;
2213	int rc = SSMR3GetU8(pSSM, &uProt);
2214	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2215	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2216	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2217	&& enmProt < PGMROMPROT_END,
2218	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2219	VERR_SSM_UNEXPECTED_DATA);
2220
2221	if (pRomPage->enmProt != enmProt)
2222	{
2223	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2224	AssertLogRelRCReturn(rc, rc);
2225	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2226	}
2227
2228	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2229	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2230	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2231	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2232
2233	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2234	* used down the line (will the 2nd page will be written to the first
2235	* one because of a false TLB hit since the TLB is using GCPhys and
2236	* doesn't check the HCPhys of the desired page). */
2237	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2238	if (RT_SUCCESS(rc))
2239	{
2240	pPageActive = pPage;
2241	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2242	}
2243	return rc;
2244	}
2245
2246	/**
2247	* Ram range flags and bits for older versions of the saved state.
2248	*
2249	* @returns VBox status code.
2250	*
2251	* @param pVM The VM handle
2252	* @param pSSM The SSM handle.
2253	* @param uVersion The saved state version.
2254	*/
2255	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2256	{
2257	PPGM pPGM = &pVM->pgm.s;
2258
2259	/*
2260	* Ram range flags and bits.
2261	*/
2262	uint32_t i = 0;
2263	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2264	{
2265	/* Check the seqence number / separator. */
2266	uint32_t u32Sep;
2267	int rc = SSMR3GetU32(pSSM, &u32Sep);
2268	if (RT_FAILURE(rc))
2269	return rc;
2270	if (u32Sep == ~0U)
2271	break;
2272	if (u32Sep != i)
2273	{
2274	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2275	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2276	}
2277	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2278
2279	/* Get the range details. */
2280	RTGCPHYS GCPhys;
2281	SSMR3GetGCPhys(pSSM, &GCPhys);
2282	RTGCPHYS GCPhysLast;
2283	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2284	RTGCPHYS cb;
2285	SSMR3GetGCPhys(pSSM, &cb);
2286	uint8_t fHaveBits;
2287	rc = SSMR3GetU8(pSSM, &fHaveBits);
2288	if (RT_FAILURE(rc))
2289	return rc;
2290	if (fHaveBits & ~1)
2291	{
2292	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2293	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2294	}
2295	size_t cchDesc = 0;
2296	char szDesc[256];
2297	szDesc[0] = '\0';
2298	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2299	{
2300	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2301	if (RT_FAILURE(rc))
2302	return rc;
2303	/* Since we've modified the description strings in r45878, only compare
2304	them if the saved state is more recent. */
2305	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2306	cchDesc = strlen(szDesc);
2307	}
2308
2309	/*
2310	* Match it up with the current range.
2311	*
2312	* Note there is a hack for dealing with the high BIOS mapping
2313	* in the old saved state format, this means we might not have
2314	* a 1:1 match on success.
2315	*/
2316	if ( ( GCPhys != pRam->GCPhys
2317	\|\| GCPhysLast != pRam->GCPhysLast
2318	\|\| cb != pRam->cb
2319	\|\| ( cchDesc
2320	&& strcmp(szDesc, pRam->pszDesc)) )
2321	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2322	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2323	\|\| GCPhys != UINT32_C(0xfff80000)
2324	\|\| GCPhysLast != UINT32_C(0xffffffff)
2325	\|\| pRam->GCPhysLast != GCPhysLast
2326	\|\| pRam->GCPhys < GCPhys
2327	\|\| !fHaveBits)
2328	)
2329	{
2330	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2331	"State : %RGp-%RGp %RGp bytes %s %s\n",
2332	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2333	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2334	/*
2335	* If we're loading a state for debugging purpose, don't make a fuss if
2336	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2337	*/
2338	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2339	\|\| GCPhys < 8 * _1M)
2340	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2341	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2342	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2343	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2344
2345	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2346	continue;
2347	}
2348
2349	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2350	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2351	{
2352	/*
2353	* Load the pages one by one.
2354	*/
2355	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2356	{
2357	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2358	PPGMPAGE pPage = &pRam->aPages[iPage];
2359	uint8_t uType;
2360	rc = SSMR3GetU8(pSSM, &uType);
2361	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2362	if (uType == PGMPAGETYPE_ROM_SHADOW)
2363	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2364	else
2365	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2366	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2367	}
2368	}
2369	else
2370	{
2371	/*
2372	* Old format.
2373	*/
2374
2375	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2376	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2377	uint32_t fFlags = 0;
2378	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2379	{
2380	uint16_t u16Flags;
2381	rc = SSMR3GetU16(pSSM, &u16Flags);
2382	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2383	fFlags \|= u16Flags;
2384	}
2385
2386	/* Load the bits */
2387	if ( !fHaveBits
2388	&& GCPhysLast < UINT32_C(0xe0000000))
2389	{
2390	/*
2391	* Dynamic chunks.
2392	*/
2393	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2394	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2395	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2396	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2397
2398	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2399	{
2400	uint8_t fPresent;
2401	rc = SSMR3GetU8(pSSM, &fPresent);
2402	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2403	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2404	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2405	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2406
2407	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2408	{
2409	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2410	PPGMPAGE pPage = &pRam->aPages[iPage];
2411	if (fPresent)
2412	{
2413	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2414	rc = pgmR3LoadPageToDevNullOld(pSSM);
2415	else
2416	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2417	}
2418	else
2419	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2420	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2421	}
2422	}
2423	}
2424	else if (pRam->pvR3)
2425	{
2426	/*
2427	* MMIO2.
2428	*/
2429	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2430	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2431	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2432	AssertLogRelMsgReturn(pRam->pvR3,
2433	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2434	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2435
2436	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2437	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2438	}
2439	else if (GCPhysLast < UINT32_C(0xfff80000))
2440	{
2441	/*
2442	* PCI MMIO, no pages saved.
2443	*/
2444	}
2445	else
2446	{
2447	/*
2448	* Load the 0xfff80000..0xffffffff BIOS range.
2449	* It starts with X reserved pages that we have to skip over since
2450	* the RAMRANGE create by the new code won't include those.
2451	*/
2452	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2453	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2454	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2455	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2456	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2457	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2458	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2459
2460	/* Skip wasted reserved pages before the ROM. */
2461	while (GCPhys < pRam->GCPhys)
2462	{
2463	rc = pgmR3LoadPageToDevNullOld(pSSM);
2464	GCPhys += PAGE_SIZE;
2465	}
2466
2467	/* Load the bios pages. */
2468	cPages = pRam->cb >> PAGE_SHIFT;
2469	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2470	{
2471	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2472	PPGMPAGE pPage = &pRam->aPages[iPage];
2473
2474	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2475	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2476	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2477	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2478	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2479	}
2480	}
2481	}
2482	}
2483
2484	return VINF_SUCCESS;
2485	}
2486
2487
2488	/**
2489	* Worker for pgmR3Load and pgmR3LoadLocked.
2490	*
2491	* @returns VBox status code.
2492	*
2493	* @param pVM The VM handle.
2494	* @param pSSM The SSM handle.
2495	* @param uVersion The saved state version.
2496	*
2497	* @todo This needs splitting up if more record types or code twists are
2498	* added...
2499	*/
2500	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2501	{
2502	/*
2503	* Process page records until we hit the terminator.
2504	*/
2505	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2506	PPGMRAMRANGE pRamHint = NULL;
2507	uint8_t id = UINT8_MAX;
2508	uint32_t iPage = UINT32_MAX - 10;
2509	PPGMROMRANGE pRom = NULL;
2510	PPGMMMIO2RANGE pMmio2 = NULL;
2511	for (;;)
2512	{
2513	/*
2514	* Get the record type and flags.
2515	*/
2516	uint8_t u8;
2517	int rc = SSMR3GetU8(pSSM, &u8);
2518	if (RT_FAILURE(rc))
2519	return rc;
2520	if (u8 == PGM_STATE_REC_END)
2521	return VINF_SUCCESS;
2522	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2523	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2524	{
2525	/*
2526	* RAM page.
2527	*/
2528	case PGM_STATE_REC_RAM_ZERO:
2529	case PGM_STATE_REC_RAM_RAW:
2530	{
2531	/*
2532	* Get the address and resolve it into a page descriptor.
2533	*/
2534	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2535	GCPhys += PAGE_SIZE;
2536	else
2537	{
2538	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2539	if (RT_FAILURE(rc))
2540	return rc;
2541	}
2542	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2543
2544	PPGMPAGE pPage;
2545	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2546	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2547
2548	/*
2549	* Take action according to the record type.
2550	*/
2551	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2552	{
2553	case PGM_STATE_REC_RAM_ZERO:
2554	{
2555	if ( PGM_PAGE_IS_ZERO(pPage)
2556	\|\| PGM_PAGE_IS_BALLOONED(pPage))
2557	break;
2558	/** @todo implement zero page replacing. */
2559	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2560	void *pvDstPage;
2561	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2562	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2563	ASMMemZeroPage(pvDstPage);
2564	break;
2565	}
2566
2567	case PGM_STATE_REC_RAM_RAW:
2568	{
2569	void *pvDstPage;
2570	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2571	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2572	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2573	if (RT_FAILURE(rc))
2574	return rc;
2575	break;
2576	}
2577
2578	default:
2579	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2580	}
2581	id = UINT8_MAX;
2582	break;
2583	}
2584
2585	/*
2586	* MMIO2 page.
2587	*/
2588	case PGM_STATE_REC_MMIO2_RAW:
2589	case PGM_STATE_REC_MMIO2_ZERO:
2590	{
2591	/*
2592	* Get the ID + page number and resolved that into a MMIO2 page.
2593	*/
2594	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2595	iPage++;
2596	else
2597	{
2598	SSMR3GetU8(pSSM, &id);
2599	rc = SSMR3GetU32(pSSM, &iPage);
2600	if (RT_FAILURE(rc))
2601	return rc;
2602	}
2603	if ( !pMmio2
2604	\|\| pMmio2->idSavedState != id)
2605	{
2606	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2607	if (pMmio2->idSavedState == id)
2608	break;
2609	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2610	}
2611	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2612	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2613
2614	/*
2615	* Load the page bits.
2616	*/
2617	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2618	ASMMemZeroPage(pvDstPage);
2619	else
2620	{
2621	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2622	if (RT_FAILURE(rc))
2623	return rc;
2624	}
2625	GCPhys = NIL_RTGCPHYS;
2626	break;
2627	}
2628
2629	/*
2630	* ROM pages.
2631	*/
2632	case PGM_STATE_REC_ROM_VIRGIN:
2633	case PGM_STATE_REC_ROM_SHW_RAW:
2634	case PGM_STATE_REC_ROM_SHW_ZERO:
2635	case PGM_STATE_REC_ROM_PROT:
2636	{
2637	/*
2638	* Get the ID + page number and resolved that into a ROM page descriptor.
2639	*/
2640	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2641	iPage++;
2642	else
2643	{
2644	SSMR3GetU8(pSSM, &id);
2645	rc = SSMR3GetU32(pSSM, &iPage);
2646	if (RT_FAILURE(rc))
2647	return rc;
2648	}
2649	if ( !pRom
2650	\|\| pRom->idSavedState != id)
2651	{
2652	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2653	if (pRom->idSavedState == id)
2654	break;
2655	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2656	}
2657	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2658	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2659	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2660
2661	/*
2662	* Get and set the protection.
2663	*/
2664	uint8_t u8Prot;
2665	rc = SSMR3GetU8(pSSM, &u8Prot);
2666	if (RT_FAILURE(rc))
2667	return rc;
2668	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2669	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2670
2671	if (enmProt != pRomPage->enmProt)
2672	{
2673	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2674	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2675	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2676	GCPhys, enmProt, pRom->pszDesc);
2677	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2678	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2679	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2680	}
2681	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2682	break; /* done */
2683
2684	/*
2685	* Get the right page descriptor.
2686	*/
2687	PPGMPAGE pRealPage;
2688	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2689	{
2690	case PGM_STATE_REC_ROM_VIRGIN:
2691	if (!PGMROMPROT_IS_ROM(enmProt))
2692	pRealPage = &pRomPage->Virgin;
2693	else
2694	pRealPage = NULL;
2695	break;
2696
2697	case PGM_STATE_REC_ROM_SHW_RAW:
2698	case PGM_STATE_REC_ROM_SHW_ZERO:
2699	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2700	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2701	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2702	GCPhys, enmProt, pRom->pszDesc);
2703	if (PGMROMPROT_IS_ROM(enmProt))
2704	pRealPage = &pRomPage->Shadow;
2705	else
2706	pRealPage = NULL;
2707	break;
2708
2709	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2710	}
2711	if (!pRealPage)
2712	{
2713	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2714	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2715	}
2716
2717	/*
2718	* Make it writable and map it (if necessary).
2719	*/
2720	void *pvDstPage = NULL;
2721	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2722	{
2723	case PGM_STATE_REC_ROM_SHW_ZERO:
2724	if ( PGM_PAGE_IS_ZERO(pRealPage)
2725	\|\| PGM_PAGE_IS_BALLOONED(pRealPage))
2726	break;
2727	/** @todo implement zero page replacing. */
2728	/* fall thru */
2729	case PGM_STATE_REC_ROM_VIRGIN:
2730	case PGM_STATE_REC_ROM_SHW_RAW:
2731	{
2732	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2733	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2734	break;
2735	}
2736	}
2737
2738	/*
2739	* Load the bits.
2740	*/
2741	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2742	{
2743	case PGM_STATE_REC_ROM_SHW_ZERO:
2744	if (pvDstPage)
2745	ASMMemZeroPage(pvDstPage);
2746	break;
2747
2748	case PGM_STATE_REC_ROM_VIRGIN:
2749	case PGM_STATE_REC_ROM_SHW_RAW:
2750	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2751	if (RT_FAILURE(rc))
2752	return rc;
2753	break;
2754	}
2755	GCPhys = NIL_RTGCPHYS;
2756	break;
2757	}
2758
2759	/*
2760	* Unknown type.
2761	*/
2762	default:
2763	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2764	}
2765	} /* forever */
2766	}
2767
2768
2769	/**
2770	* Worker for pgmR3Load.
2771	*
2772	* @returns VBox status code.
2773	*
2774	* @param pVM The VM handle.
2775	* @param pSSM The SSM handle.
2776	* @param uVersion The saved state version.
2777	*/
2778	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2779	{
2780	PPGM pPGM = &pVM->pgm.s;
2781	int rc;
2782	uint32_t u32Sep;
2783
2784	/*
2785	* Load basic data (required / unaffected by relocation).
2786	*/
2787	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2788	{
2789	if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2790	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2791	else
2792	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFieldsPreBalloon[0]);
2793
2794	AssertLogRelRCReturn(rc, rc);
2795
2796	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2797	{
2798	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2799	AssertLogRelRCReturn(rc, rc);
2800	}
2801	}
2802	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2803	{
2804	AssertRelease(pVM->cCpus == 1);
2805
2806	PGMOLD pgmOld;
2807	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2808	AssertLogRelRCReturn(rc, rc);
2809
2810	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2811	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2812	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2813
2814	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2815	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2816	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2817	}
2818	else
2819	{
2820	AssertRelease(pVM->cCpus == 1);
2821
2822	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2823	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2824	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2825
2826	uint32_t cbRamSizeIgnored;
2827	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2828	if (RT_FAILURE(rc))
2829	return rc;
2830	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2831
2832	uint32_t u32 = 0;
2833	SSMR3GetUInt(pSSM, &u32);
2834	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2835	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2836	RTUINT uGuestMode;
2837	SSMR3GetUInt(pSSM, &uGuestMode);
2838	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2839
2840	/* check separator. */
2841	SSMR3GetU32(pSSM, &u32Sep);
2842	if (RT_FAILURE(rc))
2843	return rc;
2844	if (u32Sep != (uint32_t)~0)
2845	{
2846	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2847	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2848	}
2849	}
2850
2851	/*
2852	* The guest mappings - skipped now, see re-fixation in the caller.
2853	*/
2854	uint32_t i = 0;
2855	for (;; i++)
2856	{
2857	rc = SSMR3GetU32(pSSM, &u32Sep); /* seqence number */
2858	if (RT_FAILURE(rc))
2859	return rc;
2860	if (u32Sep == ~0U)
2861	break;
2862	AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2863
2864	char szDesc[256];
2865	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2866	if (RT_FAILURE(rc))
2867	return rc;
2868	RTGCPTR GCPtrIgnore;
2869	SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
2870	rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
2871	if (RT_FAILURE(rc))
2872	return rc;
2873	}
2874
2875	/*
2876	* Load the RAM contents.
2877	*/
2878	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2879	{
2880	if (!pVM->pgm.s.LiveSave.fActive)
2881	{
2882	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2883	{
2884	rc = pgmR3LoadRamConfig(pVM, pSSM);
2885	if (RT_FAILURE(rc))
2886	return rc;
2887	}
2888	rc = pgmR3LoadRomRanges(pVM, pSSM);
2889	if (RT_FAILURE(rc))
2890	return rc;
2891	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2892	if (RT_FAILURE(rc))
2893	return rc;
2894	}
2895
2896	rc = pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2897	}
2898	else
2899	rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2900
2901	/* Refresh balloon accounting. */
2902	if (pVM->pgm.s.cBalloonedPages)
2903	{
2904	rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
2905	AssertRC(rc);
2906	}
2907	return rc;
2908	}
2909
2910
2911	/**
2912	* Execute state load operation.
2913	*
2914	* @returns VBox status code.
2915	* @param pVM VM Handle.
2916	* @param pSSM SSM operation handle.
2917	* @param uVersion Data layout version.
2918	* @param uPass The data pass.
2919	*/
2920	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2921	{
2922	int rc;
2923	PPGM pPGM = &pVM->pgm.s;
2924
2925	/*
2926	* Validate version.
2927	*/
2928	if ( ( uPass != SSM_PASS_FINAL
2929	&& uVersion != PGM_SAVED_STATE_VERSION
2930	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
2931	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2932	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
2933	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
2934	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
2935	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
2936	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
2937	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
2938	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2939	)
2940	{
2941	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
2942	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2943	}
2944
2945	/*
2946	* Do the loading while owning the lock because a bunch of the functions
2947	* we're using requires this.
2948	*/
2949	if (uPass != SSM_PASS_FINAL)
2950	{
2951	pgmLock(pVM);
2952	if (uPass != 0)
2953	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2954	else
2955	{
2956	pVM->pgm.s.LiveSave.fActive = true;
2957	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2958	rc = pgmR3LoadRamConfig(pVM, pSSM);
2959	else
2960	rc = VINF_SUCCESS;
2961	if (RT_SUCCESS(rc))
2962	rc = pgmR3LoadRomRanges(pVM, pSSM);
2963	if (RT_SUCCESS(rc))
2964	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2965	if (RT_SUCCESS(rc))
2966	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2967	}
2968	pgmUnlock(pVM);
2969	}
2970	else
2971	{
2972	pgmLock(pVM);
2973	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
2974	pVM->pgm.s.LiveSave.fActive = false;
2975	pgmUnlock(pVM);
2976	if (RT_SUCCESS(rc))
2977	{
2978	/*
2979	* We require a full resync now.
2980	*/
2981	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2982	{
2983	PVMCPU pVCpu = &pVM->aCpus[i];
2984	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2985	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2986	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2987	}
2988
2989	pgmR3HandlerPhysicalUpdateAll(pVM);
2990
2991	/*
2992	* Change the paging mode and restore PGMCPU::GCPhysCR3.
2993	* (The latter requires the CPUM state to be restored already.)
2994	*/
2995	if (CPUMR3IsStateRestorePending(pVM))
2996	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
2997	N_("PGM was unexpectedly restored before CPUM"));
2998
2999	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3000	{
3001	PVMCPU pVCpu = &pVM->aCpus[i];
3002
3003	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3004	AssertLogRelRCReturn(rc, rc);
3005
3006	/* Restore pVM->pgm.s.GCPhysCR3. */
3007	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3008	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3009	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3010	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3011	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3012	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3013	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3014	else
3015	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3016	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3017	}
3018
3019	/*
3020	* Try re-fixate the guest mappings.
3021	*/
3022	pVM->pgm.s.fMappingsFixedRestored = false;
3023	if ( pVM->pgm.s.fMappingsFixed
3024	&& pgmMapAreMappingsEnabled(&pVM->pgm.s))
3025	{
3026	RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
3027	uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
3028	pVM->pgm.s.fMappingsFixed = false;
3029
3030	uint32_t cbRequired;
3031	int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
3032	if ( RT_SUCCESS(rc2)
3033	&& cbRequired > cbFixed)
3034	rc2 = VERR_OUT_OF_RANGE;
3035	if (RT_SUCCESS(rc2))
3036	rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
3037	if (RT_FAILURE(rc2))
3038	{
3039	LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
3040	GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
3041	pVM->pgm.s.fMappingsFixed = false;
3042	pVM->pgm.s.fMappingsFixedRestored = true;
3043	pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
3044	pVM->pgm.s.cbMappingFixed = cbFixed;
3045	}
3046	}
3047	else
3048	{
3049	/* We used to set fixed + disabled while we only use disabled now,
3050	so wipe the state to avoid any confusion. */
3051	pVM->pgm.s.fMappingsFixed = false;
3052	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3053	pVM->pgm.s.cbMappingFixed = 0;
3054	}
3055
3056	/*
3057	* If we have floating mappings, do a CR3 sync now to make sure the HMA
3058	* doesn't conflict with guest code / data and thereby cause trouble
3059	* when restoring other components like PATM.
3060	*/
3061	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3062	{
3063	PVMCPU pVCpu = &pVM->aCpus[0];
3064	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3065	if (RT_FAILURE(rc))
3066	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3067	N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3068
3069	/* Make sure to re-sync before executing code. */
3070	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3071	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3072	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3073	}
3074	}
3075	}
3076
3077	return rc;
3078	}
3079
3080
3081	/**
3082	* Registers the saved state callbacks with SSM.
3083	*
3084	* @returns VBox status code.
3085	* @param pVM Pointer to VM structure.
3086	* @param cbRam The RAM size.
3087	*/
3088	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3089	{
3090	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3091	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3092	NULL, pgmR3SaveExec, pgmR3SaveDone,
3093	pgmR3LoadPrep, pgmR3Load, NULL);
3094	}
3095

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source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 30160

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