PGMSavedState.cpp@ 28425

Last change on this file since 28425 was 27566, checked in by vboxsync, 15 years ago
PGMSavedState.cpp: Better message when finding missing ROM.
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1	/* $Id: PGMSavedState.cpp 27566 2010-03-22 00:02:06Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/pgm.h>
28	#include <VBox/stam.h>
29	#include <VBox/ssm.h>
30	#include <VBox/pdmdrv.h>
31	#include <VBox/pdmdev.h>
32	#include "PGMInternal.h"
33	#include <VBox/vm.h>
34	#include "PGMInline.h"
35
36	#include <VBox/param.h>
37	#include <VBox/err.h>
38
39	#include <iprt/asm.h>
40	#include <iprt/assert.h>
41	#include <iprt/crc32.h>
42	#include <iprt/mem.h>
43	#include <iprt/sha.h>
44	#include <iprt/string.h>
45	#include <iprt/thread.h>
46
47
48	/*******************************************************************************
49	* Defined Constants And Macros *
50	*******************************************************************************/
51	/** Saved state data unit version.
52	* @todo remove the guest mappings from the saved state at next version change! */
53	#define PGM_SAVED_STATE_VERSION 12
54	/** Saved state before the balloon change. */
55	#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
56	/** Saved state data unit version used during 3.1 development, misses the RAM
57	* config. */
58	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
59	/** Saved state data unit version for 3.0 (pre teleportation). */
60	#define PGM_SAVED_STATE_VERSION_3_0_0 9
61	/** Saved state data unit version for 2.2.2 and later. */
62	#define PGM_SAVED_STATE_VERSION_2_2_2 8
63	/** Saved state data unit version for 2.2.0. */
64	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
65	/** Saved state data unit version. */
66	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
67
68
69	/** @name Sparse state record types
70	* @{ */
71	/** Zero page. No data. */
72	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
73	/** Raw page. */
74	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
75	/** Raw MMIO2 page. */
76	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
77	/** Zero MMIO2 page. */
78	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
79	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
80	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
81	/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
82	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
83	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
84	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
85	/** ROM protection (8-bit). */
86	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
87	/** The last record type. */
88	#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
89	/** End marker. */
90	#define PGM_STATE_REC_END UINT8_C(0xff)
91	/** Flag indicating that the data is preceeded by the page address.
92	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
93	* range ID and a 32-bit page index.
94	*/
95	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
96	/** @} */
97
98	/** The CRC-32 for a zero page. */
99	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
100	/** The CRC-32 for a zero half page. */
101	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
102
103
104	/*******************************************************************************
105	* Structures and Typedefs *
106	*******************************************************************************/
107	/** For loading old saved states. (pre-smp) */
108	typedef struct
109	{
110	/** If set no conflict checks are required. (boolean) */
111	bool fMappingsFixed;
112	/** Size of fixed mapping */
113	uint32_t cbMappingFixed;
114	/** Base address (GC) of fixed mapping */
115	RTGCPTR GCPtrMappingFixed;
116	/** A20 gate mask.
117	* Our current approach to A20 emulation is to let REM do it and don't bother
118	* anywhere else. The interesting guests will be operating with it enabled anyway.
119	* But should the need arise, we'll subject physical addresses to this mask. */
120	RTGCPHYS GCPhysA20Mask;
121	/** A20 gate state - boolean! */
122	bool fA20Enabled;
123	/** The guest paging mode. */
124	PGMMODE enmGuestMode;
125	} PGMOLD;
126
127
128	/*******************************************************************************
129	* Global Variables *
130	*******************************************************************************/
131	/** PGM fields to save/load. */
132
133	static const SSMFIELD s_aPGMFields[] =
134	{
135	SSMFIELD_ENTRY( PGM, fMappingsFixed),
136	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
137	SSMFIELD_ENTRY( PGM, cbMappingFixed),
138	SSMFIELD_ENTRY( PGM, cBalloonedPages),
139	SSMFIELD_ENTRY_TERM()
140	};
141
142	static const SSMFIELD s_aPGMFieldsPreBalloon[] =
143	{
144	SSMFIELD_ENTRY( PGM, fMappingsFixed),
145	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
146	SSMFIELD_ENTRY( PGM, cbMappingFixed),
147	SSMFIELD_ENTRY_TERM()
148	};
149
150	static const SSMFIELD s_aPGMCpuFields[] =
151	{
152	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
153	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
154	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
155	SSMFIELD_ENTRY_TERM()
156	};
157
158	static const SSMFIELD s_aPGMFields_Old[] =
159	{
160	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
161	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
162	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
163	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
164	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
165	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
166	SSMFIELD_ENTRY_TERM()
167	};
168
169
170	/**
171	* Find the ROM tracking structure for the given page.
172	*
173	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
174	* that it's a ROM page.
175	* @param pVM The VM handle.
176	* @param GCPhys The address of the ROM page.
177	*/
178	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
179	{
180	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
181	pRomRange;
182	pRomRange = pRomRange->CTX_SUFF(pNext))
183	{
184	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
185	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
186	return &pRomRange->aPages[off >> PAGE_SHIFT];
187	}
188	return NULL;
189	}
190
191
192	/**
193	* Prepares the ROM pages for a live save.
194	*
195	* @returns VBox status code.
196	* @param pVM The VM handle.
197	*/
198	static int pgmR3PrepRomPages(PVM pVM)
199	{
200	/*
201	* Initialize the live save tracking in the ROM page descriptors.
202	*/
203	pgmLock(pVM);
204	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
205	{
206	PPGMRAMRANGE pRamHint = NULL;;
207	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
208
209	for (uint32_t iPage = 0; iPage < cPages; iPage++)
210	{
211	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
212	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
213	pRom->aPages[iPage].LiveSave.fDirty = true;
214	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
215	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
216	{
217	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
218	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
219	else
220	{
221	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
222	PPGMPAGE pPage;
223	int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
224	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
225	if (RT_SUCCESS(rc))
226	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
227	else
228	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
229	}
230	}
231	}
232
233	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
234	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
235	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
236	}
237	pgmUnlock(pVM);
238
239	return VINF_SUCCESS;
240	}
241
242
243	/**
244	* Assigns IDs to the ROM ranges and saves them.
245	*
246	* @returns VBox status code.
247	* @param pVM The VM handle.
248	* @param pSSM Saved state handle.
249	*/
250	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
251	{
252	pgmLock(pVM);
253	uint8_t id = 1;
254	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
255	{
256	pRom->idSavedState = id;
257	SSMR3PutU8(pSSM, id);
258	SSMR3PutStrZ(pSSM, ""); /* device name */
259	SSMR3PutU32(pSSM, 0); /* device instance */
260	SSMR3PutU8(pSSM, 0); /* region */
261	SSMR3PutStrZ(pSSM, pRom->pszDesc);
262	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
263	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
264	if (RT_FAILURE(rc))
265	break;
266	}
267	pgmUnlock(pVM);
268	return SSMR3PutU8(pSSM, UINT8_MAX);
269	}
270
271
272	/**
273	* Loads the ROM range ID assignments.
274	*
275	* @returns VBox status code.
276	*
277	* @param pVM The VM handle.
278	* @param pSSM The saved state handle.
279	*/
280	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
281	{
282	Assert(PGMIsLockOwner(pVM));
283
284	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
285	pRom->idSavedState = UINT8_MAX;
286
287	for (;;)
288	{
289	/*
290	* Read the data.
291	*/
292	uint8_t id;
293	int rc = SSMR3GetU8(pSSM, &id);
294	if (RT_FAILURE(rc))
295	return rc;
296	if (id == UINT8_MAX)
297	{
298	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
299	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX,
300	("The \"%s\" ROM was not found in the saved state. Probably due to some misconfiguration\n",
301	pRom->pszDesc));
302	return VINF_SUCCESS; /* the end */
303	}
304	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
305
306	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
307	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
308	AssertLogRelRCReturn(rc, rc);
309
310	uint32_t uInstance;
311	SSMR3GetU32(pSSM, &uInstance);
312	uint8_t iRegion;
313	SSMR3GetU8(pSSM, &iRegion);
314
315	char szDesc[64];
316	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
317	AssertLogRelRCReturn(rc, rc);
318
319	RTGCPHYS GCPhys;
320	SSMR3GetGCPhys(pSSM, &GCPhys);
321	RTGCPHYS cb;
322	rc = SSMR3GetGCPhys(pSSM, &cb);
323	if (RT_FAILURE(rc))
324	return rc;
325	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
326	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
327
328	/*
329	* Locate a matching ROM range.
330	*/
331	AssertLogRelMsgReturn( uInstance == 0
332	&& iRegion == 0
333	&& szDevName[0] == '\0',
334	("GCPhys=%RGp %s\n", GCPhys, szDesc),
335	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
336	PPGMROMRANGE pRom;
337	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
338	{
339	if ( pRom->idSavedState == UINT8_MAX
340	&& !strcmp(pRom->pszDesc, szDesc))
341	{
342	pRom->idSavedState = id;
343	break;
344	}
345	}
346	if (!pRom)
347	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
348	} /* forever */
349	}
350
351
352	/**
353	* Scan ROM pages.
354	*
355	* @param pVM The VM handle.
356	*/
357	static void pgmR3ScanRomPages(PVM pVM)
358	{
359	/*
360	* The shadow ROMs.
361	*/
362	pgmLock(pVM);
363	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
364	{
365	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
366	{
367	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
368	for (uint32_t iPage = 0; iPage < cPages; iPage++)
369	{
370	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
371	if (pRomPage->LiveSave.fWrittenTo)
372	{
373	pRomPage->LiveSave.fWrittenTo = false;
374	if (!pRomPage->LiveSave.fDirty)
375	{
376	pRomPage->LiveSave.fDirty = true;
377	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
378	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
379	}
380	pRomPage->LiveSave.fDirtiedRecently = true;
381	}
382	else
383	pRomPage->LiveSave.fDirtiedRecently = false;
384	}
385	}
386	}
387	pgmUnlock(pVM);
388	}
389
390
391	/**
392	* Takes care of the virgin ROM pages in the first pass.
393	*
394	* This is an attempt at simplifying the handling of ROM pages a little bit.
395	* This ASSUMES that no new ROM ranges will be added and that they won't be
396	* relinked in any way.
397	*
398	* @param pVM The VM handle.
399	* @param pSSM The SSM handle.
400	* @param fLiveSave Whether we're in a live save or not.
401	*/
402	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
403	{
404	pgmLock(pVM);
405	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
406	{
407	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
408	for (uint32_t iPage = 0; iPage < cPages; iPage++)
409	{
410	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
411	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
412
413	/* Get the virgin page descriptor. */
414	PPGMPAGE pPage;
415	if (PGMROMPROT_IS_ROM(enmProt))
416	pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
417	else
418	pPage = &pRom->aPages[iPage].Virgin;
419
420	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
421	int rc = VINF_SUCCESS;
422	char abPage[PAGE_SIZE];
423	if ( !PGM_PAGE_IS_ZERO(pPage)
424	&& !PGM_PAGE_IS_BALLOONED(pPage))
425	{
426	void const *pvPage;
427	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
428	if (RT_SUCCESS(rc))
429	memcpy(abPage, pvPage, PAGE_SIZE);
430	}
431	else
432	ASMMemZeroPage(abPage);
433	pgmUnlock(pVM);
434	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
435
436	/* Save it. */
437	if (iPage > 0)
438	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
439	else
440	{
441	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
442	SSMR3PutU8(pSSM, pRom->idSavedState);
443	SSMR3PutU32(pSSM, iPage);
444	}
445	SSMR3PutU8(pSSM, (uint8_t)enmProt);
446	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
447	if (RT_FAILURE(rc))
448	return rc;
449
450	/* Update state. */
451	pgmLock(pVM);
452	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
453	if (fLiveSave)
454	{
455	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
456	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
457	pVM->pgm.s.LiveSave.cSavedPages++;
458	}
459	}
460	}
461	pgmUnlock(pVM);
462	return VINF_SUCCESS;
463	}
464
465
466	/**
467	* Saves dirty pages in the shadowed ROM ranges.
468	*
469	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
470	*
471	* @returns VBox status code.
472	* @param pVM The VM handle.
473	* @param pSSM The SSM handle.
474	* @param fLiveSave Whether it's a live save or not.
475	* @param fFinalPass Whether this is the final pass or not.
476	*/
477	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
478	{
479	/*
480	* The Shadowed ROMs.
481	*
482	* ASSUMES that the ROM ranges are fixed.
483	* ASSUMES that all the ROM ranges are mapped.
484	*/
485	pgmLock(pVM);
486	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
487	{
488	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
489	{
490	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
491	uint32_t iPrevPage = cPages;
492	for (uint32_t iPage = 0; iPage < cPages; iPage++)
493	{
494	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
495	if ( !fLiveSave
496	\|\| ( pRomPage->LiveSave.fDirty
497	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
498	&& !pRomPage->LiveSave.fWrittenTo)
499	\|\| fFinalPass
500	)
501	)
502	)
503	{
504	uint8_t abPage[PAGE_SIZE];
505	PGMROMPROT enmProt = pRomPage->enmProt;
506	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
507	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
508	bool fZero = PGM_PAGE_IS_ZERO(pPage) \|\| PGM_PAGE_IS_BALLOONED(pPage);
509	int rc = VINF_SUCCESS;
510	if (!fZero)
511	{
512	void const *pvPage;
513	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
514	if (RT_SUCCESS(rc))
515	memcpy(abPage, pvPage, PAGE_SIZE);
516	}
517	if (fLiveSave && RT_SUCCESS(rc))
518	{
519	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
520	pRomPage->LiveSave.fDirty = false;
521	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
522	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
523	pVM->pgm.s.LiveSave.cSavedPages++;
524	}
525	pgmUnlock(pVM);
526	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
527
528	if (iPage - 1U == iPrevPage && iPage > 0)
529	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
530	else
531	{
532	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
533	SSMR3PutU8(pSSM, pRom->idSavedState);
534	SSMR3PutU32(pSSM, iPage);
535	}
536	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
537	if (!fZero)
538	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
539	if (RT_FAILURE(rc))
540	return rc;
541
542	pgmLock(pVM);
543	iPrevPage = iPage;
544	}
545	/*
546	* In the final pass, make sure the protection is in sync.
547	*/
548	else if ( fFinalPass
549	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
550	{
551	PGMROMPROT enmProt = pRomPage->enmProt;
552	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
553	pgmUnlock(pVM);
554
555	if (iPage - 1U == iPrevPage && iPage > 0)
556	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
557	else
558	{
559	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
560	SSMR3PutU8(pSSM, pRom->idSavedState);
561	SSMR3PutU32(pSSM, iPage);
562	}
563	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
564	if (RT_FAILURE(rc))
565	return rc;
566
567	pgmLock(pVM);
568	iPrevPage = iPage;
569	}
570	}
571	}
572	}
573	pgmUnlock(pVM);
574	return VINF_SUCCESS;
575	}
576
577
578	/**
579	* Cleans up ROM pages after a live save.
580	*
581	* @param pVM The VM handle.
582	*/
583	static void pgmR3DoneRomPages(PVM pVM)
584	{
585	NOREF(pVM);
586	}
587
588
589	/**
590	* Prepares the MMIO2 pages for a live save.
591	*
592	* @returns VBox status code.
593	* @param pVM The VM handle.
594	*/
595	static int pgmR3PrepMmio2Pages(PVM pVM)
596	{
597	/*
598	* Initialize the live save tracking in the MMIO2 ranges.
599	* ASSUME nothing changes here.
600	*/
601	pgmLock(pVM);
602	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
603	{
604	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
605	pgmUnlock(pVM);
606
607	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
608	if (!paLSPages)
609	return VERR_NO_MEMORY;
610	for (uint32_t iPage = 0; iPage < cPages; iPage++)
611	{
612	/* Initialize it as a dirty zero page. */
613	paLSPages[iPage].fDirty = true;
614	paLSPages[iPage].cUnchangedScans = 0;
615	paLSPages[iPage].fZero = true;
616	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
617	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
618	}
619
620	pgmLock(pVM);
621	pMmio2->paLSPages = paLSPages;
622	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
623	}
624	pgmUnlock(pVM);
625	return VINF_SUCCESS;
626	}
627
628
629	/**
630	* Assigns IDs to the MMIO2 ranges and saves them.
631	*
632	* @returns VBox status code.
633	* @param pVM The VM handle.
634	* @param pSSM Saved state handle.
635	*/
636	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
637	{
638	pgmLock(pVM);
639	uint8_t id = 1;
640	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
641	{
642	pMmio2->idSavedState = id;
643	SSMR3PutU8(pSSM, id);
644	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pReg->szName);
645	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
646	SSMR3PutU8(pSSM, pMmio2->iRegion);
647	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
648	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
649	if (RT_FAILURE(rc))
650	break;
651	}
652	pgmUnlock(pVM);
653	return SSMR3PutU8(pSSM, UINT8_MAX);
654	}
655
656
657	/**
658	* Loads the MMIO2 range ID assignments.
659	*
660	* @returns VBox status code.
661	*
662	* @param pVM The VM handle.
663	* @param pSSM The saved state handle.
664	*/
665	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
666	{
667	Assert(PGMIsLockOwner(pVM));
668
669	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
670	pMmio2->idSavedState = UINT8_MAX;
671
672	for (;;)
673	{
674	/*
675	* Read the data.
676	*/
677	uint8_t id;
678	int rc = SSMR3GetU8(pSSM, &id);
679	if (RT_FAILURE(rc))
680	return rc;
681	if (id == UINT8_MAX)
682	{
683	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
684	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
685	return VINF_SUCCESS; /* the end */
686	}
687	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
688
689	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
690	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
691	AssertLogRelRCReturn(rc, rc);
692
693	uint32_t uInstance;
694	SSMR3GetU32(pSSM, &uInstance);
695	uint8_t iRegion;
696	SSMR3GetU8(pSSM, &iRegion);
697
698	char szDesc[64];
699	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
700	AssertLogRelRCReturn(rc, rc);
701
702	RTGCPHYS cb;
703	rc = SSMR3GetGCPhys(pSSM, &cb);
704	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
705
706	/*
707	* Locate a matching MMIO2 range.
708	*/
709	PPGMMMIO2RANGE pMmio2;
710	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
711	{
712	if ( pMmio2->idSavedState == UINT8_MAX
713	&& pMmio2->iRegion == iRegion
714	&& pMmio2->pDevInsR3->iInstance == uInstance
715	&& !strcmp(pMmio2->pDevInsR3->pReg->szName, szDevName))
716	{
717	pMmio2->idSavedState = id;
718	break;
719	}
720	}
721	if (!pMmio2)
722	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
723	szDesc, szDevName, uInstance, iRegion);
724
725	/*
726	* Validate the configuration, the size of the MMIO2 region should be
727	* the same.
728	*/
729	if (cb != pMmio2->RamRange.cb)
730	{
731	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
732	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
733	if (cb > pMmio2->RamRange.cb) /* bad idea? */
734	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
735	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
736	}
737	} /* forever */
738	}
739
740
741	/**
742	* Scans one MMIO2 page.
743	*
744	* @returns True if changed, false if unchanged.
745	*
746	* @param pVM The VM handle
747	* @param pbPage The page bits.
748	* @param pLSPage The live save tracking structure for the page.
749	*
750	*/
751	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
752	{
753	/*
754	* Special handling of zero pages.
755	*/
756	bool const fZero = pLSPage->fZero;
757	if (fZero)
758	{
759	if (ASMMemIsZeroPage(pbPage))
760	{
761	/* Not modified. */
762	if (pLSPage->fDirty)
763	pLSPage->cUnchangedScans++;
764	return false;
765	}
766
767	pLSPage->fZero = false;
768	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
769	}
770	else
771	{
772	/*
773	* CRC the first half, if it doesn't match the page is dirty and
774	* we won't check the 2nd half (we'll do that next time).
775	*/
776	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
777	if (u32CrcH1 == pLSPage->u32CrcH1)
778	{
779	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
780	if (u32CrcH2 == pLSPage->u32CrcH2)
781	{
782	/* Probably not modified. */
783	if (pLSPage->fDirty)
784	pLSPage->cUnchangedScans++;
785	return false;
786	}
787
788	pLSPage->u32CrcH2 = u32CrcH2;
789	}
790	else
791	{
792	pLSPage->u32CrcH1 = u32CrcH1;
793	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
794	&& ASMMemIsZeroPage(pbPage))
795	{
796	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
797	pLSPage->fZero = true;
798	}
799	}
800	}
801
802	/* dirty page path */
803	pLSPage->cUnchangedScans = 0;
804	if (!pLSPage->fDirty)
805	{
806	pLSPage->fDirty = true;
807	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
808	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
809	if (fZero)
810	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
811	}
812	return true;
813	}
814
815
816	/**
817	* Scan for MMIO2 page modifications.
818	*
819	* @param pVM The VM handle.
820	* @param uPass The pass number.
821	*/
822	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
823	{
824	/*
825	* Since this is a bit expensive we lower the scan rate after a little while.
826	*/
827	if ( ( (uPass & 3) != 0
828	&& uPass > 10)
829	\|\| uPass == SSM_PASS_FINAL)
830	return;
831
832	pgmLock(pVM); /* paranoia */
833	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
834	{
835	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
836	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
837	pgmUnlock(pVM);
838
839	for (uint32_t iPage = 0; iPage < cPages; iPage++)
840	{
841	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
842	pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
843	}
844
845	pgmLock(pVM);
846	}
847	pgmUnlock(pVM);
848
849	}
850
851
852	/**
853	* Save quiescent MMIO2 pages.
854	*
855	* @returns VBox status code.
856	* @param pVM The VM handle.
857	* @param pSSM The SSM handle.
858	* @param fLiveSave Whether it's a live save or not.
859	* @param uPass The pass number.
860	*/
861	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
862	{
863	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
864	* device that we wish to know about changes.) */
865
866	int rc = VINF_SUCCESS;
867	if (uPass == SSM_PASS_FINAL)
868	{
869	/*
870	* The mop up round.
871	*/
872	pgmLock(pVM);
873	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
874	pMmio2 && RT_SUCCESS(rc);
875	pMmio2 = pMmio2->pNextR3)
876	{
877	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
878	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
879	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
880	uint32_t iPageLast = cPages;
881	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
882	{
883	uint8_t u8Type;
884	if (!fLiveSave)
885	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
886	else
887	{
888	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
889	if ( !paLSPages[iPage].fDirty
890	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
891	{
892	if (paLSPages[iPage].fZero)
893	continue;
894
895	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
896	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
897	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
898	continue;
899	}
900	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
901	pVM->pgm.s.LiveSave.cSavedPages++;
902	}
903
904	if (iPage != 0 && iPage == iPageLast + 1)
905	rc = SSMR3PutU8(pSSM, u8Type);
906	else
907	{
908	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
909	SSMR3PutU8(pSSM, pMmio2->idSavedState);
910	rc = SSMR3PutU32(pSSM, iPage);
911	}
912	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
913	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
914	if (RT_FAILURE(rc))
915	break;
916	iPageLast = iPage;
917	}
918	}
919	pgmUnlock(pVM);
920	}
921	/*
922	* Reduce the rate after a little while since the current MMIO2 approach is
923	* a bit expensive.
924	* We position it two passes after the scan pass to avoid saving busy pages.
925	*/
926	else if ( uPass <= 10
927	\|\| (uPass & 3) == 2)
928	{
929	pgmLock(pVM);
930	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
931	pMmio2 && RT_SUCCESS(rc);
932	pMmio2 = pMmio2->pNextR3)
933	{
934	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
935	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
936	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
937	uint32_t iPageLast = cPages;
938	pgmUnlock(pVM);
939
940	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
941	{
942	/* Skip clean pages and pages which hasn't quiesced. */
943	if (!paLSPages[iPage].fDirty)
944	continue;
945	if (paLSPages[iPage].cUnchangedScans < 3)
946	continue;
947	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
948	continue;
949
950	/* Save it. */
951	bool const fZero = paLSPages[iPage].fZero;
952	uint8_t abPage[PAGE_SIZE];
953	if (!fZero)
954	{
955	memcpy(abPage, pbPage, PAGE_SIZE);
956	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
957	}
958
959	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
960	if (iPage != 0 && iPage == iPageLast + 1)
961	rc = SSMR3PutU8(pSSM, u8Type);
962	else
963	{
964	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
965	SSMR3PutU8(pSSM, pMmio2->idSavedState);
966	rc = SSMR3PutU32(pSSM, iPage);
967	}
968	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
969	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
970	if (RT_FAILURE(rc))
971	break;
972
973	/* Housekeeping. */
974	paLSPages[iPage].fDirty = false;
975	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
976	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
977	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
978	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
979	pVM->pgm.s.LiveSave.cSavedPages++;
980	iPageLast = iPage;
981	}
982
983	pgmLock(pVM);
984	}
985	pgmUnlock(pVM);
986	}
987
988	return rc;
989	}
990
991
992	/**
993	* Cleans up MMIO2 pages after a live save.
994	*
995	* @param pVM The VM handle.
996	*/
997	static void pgmR3DoneMmio2Pages(PVM pVM)
998	{
999	/*
1000	* Free the tracking structures for the MMIO2 pages.
1001	* We do the freeing outside the lock in case the VM is running.
1002	*/
1003	pgmLock(pVM);
1004	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
1005	{
1006	void *pvMmio2ToFree = pMmio2->paLSPages;
1007	if (pvMmio2ToFree)
1008	{
1009	pMmio2->paLSPages = NULL;
1010	pgmUnlock(pVM);
1011	MMR3HeapFree(pvMmio2ToFree);
1012	pgmLock(pVM);
1013	}
1014	}
1015	pgmUnlock(pVM);
1016	}
1017
1018
1019	/**
1020	* Prepares the RAM pages for a live save.
1021	*
1022	* @returns VBox status code.
1023	* @param pVM The VM handle.
1024	*/
1025	static int pgmR3PrepRamPages(PVM pVM)
1026	{
1027
1028	/*
1029	* Try allocating tracking structures for the ram ranges.
1030	*
1031	* To avoid lock contention, we leave the lock every time we're allocating
1032	* a new array. This means we'll have to ditch the allocation and start
1033	* all over again if the RAM range list changes in-between.
1034	*
1035	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1036	* for cleaning up.
1037	*/
1038	PPGMRAMRANGE pCur;
1039	pgmLock(pVM);
1040	do
1041	{
1042	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1043	{
1044	if ( !pCur->paLSPages
1045	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1046	{
1047	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1048	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1049	pgmUnlock(pVM);
1050	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1051	if (!paLSPages)
1052	return VERR_NO_MEMORY;
1053	pgmLock(pVM);
1054	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1055	{
1056	pgmUnlock(pVM);
1057	MMR3HeapFree(paLSPages);
1058	pgmLock(pVM);
1059	break; /* try again */
1060	}
1061	pCur->paLSPages = paLSPages;
1062
1063	/*
1064	* Initialize the array.
1065	*/
1066	uint32_t iPage = cPages;
1067	while (iPage-- > 0)
1068	{
1069	/** @todo yield critsect! (after moving this away from EMT0) */
1070	PCPGMPAGE pPage = &pCur->aPages[iPage];
1071	paLSPages[iPage].cDirtied = 0;
1072	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1073	paLSPages[iPage].fWriteMonitored = 0;
1074	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1075	paLSPages[iPage].u2Reserved = 0;
1076	switch (PGM_PAGE_GET_TYPE(pPage))
1077	{
1078	case PGMPAGETYPE_RAM:
1079	if ( PGM_PAGE_IS_ZERO(pPage)
1080	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1081	{
1082	paLSPages[iPage].fZero = 1;
1083	paLSPages[iPage].fShared = 0;
1084	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1085	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1086	#endif
1087	}
1088	else if (PGM_PAGE_IS_SHARED(pPage))
1089	{
1090	paLSPages[iPage].fZero = 0;
1091	paLSPages[iPage].fShared = 1;
1092	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1093	paLSPages[iPage].u32Crc = UINT32_MAX;
1094	#endif
1095	}
1096	else
1097	{
1098	paLSPages[iPage].fZero = 0;
1099	paLSPages[iPage].fShared = 0;
1100	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1101	paLSPages[iPage].u32Crc = UINT32_MAX;
1102	#endif
1103	}
1104	paLSPages[iPage].fIgnore = 0;
1105	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1106	break;
1107
1108	case PGMPAGETYPE_ROM_SHADOW:
1109	case PGMPAGETYPE_ROM:
1110	{
1111	paLSPages[iPage].fZero = 0;
1112	paLSPages[iPage].fShared = 0;
1113	paLSPages[iPage].fDirty = 0;
1114	paLSPages[iPage].fIgnore = 1;
1115	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1116	paLSPages[iPage].u32Crc = UINT32_MAX;
1117	#endif
1118	pVM->pgm.s.LiveSave.cIgnoredPages++;
1119	break;
1120	}
1121
1122	default:
1123	AssertMsgFailed(("%R[pgmpage]", pPage));
1124	case PGMPAGETYPE_MMIO2:
1125	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1126	paLSPages[iPage].fZero = 0;
1127	paLSPages[iPage].fShared = 0;
1128	paLSPages[iPage].fDirty = 0;
1129	paLSPages[iPage].fIgnore = 1;
1130	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1131	paLSPages[iPage].u32Crc = UINT32_MAX;
1132	#endif
1133	pVM->pgm.s.LiveSave.cIgnoredPages++;
1134	break;
1135
1136	case PGMPAGETYPE_MMIO:
1137	paLSPages[iPage].fZero = 0;
1138	paLSPages[iPage].fShared = 0;
1139	paLSPages[iPage].fDirty = 0;
1140	paLSPages[iPage].fIgnore = 1;
1141	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1142	paLSPages[iPage].u32Crc = UINT32_MAX;
1143	#endif
1144	pVM->pgm.s.LiveSave.cIgnoredPages++;
1145	break;
1146	}
1147	}
1148	}
1149	}
1150	} while (pCur);
1151	pgmUnlock(pVM);
1152
1153	return VINF_SUCCESS;
1154	}
1155
1156
1157	/**
1158	* Saves the RAM configuration.
1159	*
1160	* @returns VBox status code.
1161	* @param pVM The VM handle.
1162	* @param pSSM The saved state handle.
1163	*/
1164	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1165	{
1166	uint32_t cbRamHole = 0;
1167	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1168	AssertRCReturn(rc, rc);
1169
1170	uint64_t cbRam = 0;
1171	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1172	AssertRCReturn(rc, rc);
1173
1174	SSMR3PutU32(pSSM, cbRamHole);
1175	return SSMR3PutU64(pSSM, cbRam);
1176	}
1177
1178
1179	/**
1180	* Loads and verifies the RAM configuration.
1181	*
1182	* @returns VBox status code.
1183	* @param pVM The VM handle.
1184	* @param pSSM The saved state handle.
1185	*/
1186	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1187	{
1188	uint32_t cbRamHoleCfg = 0;
1189	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1190	AssertRCReturn(rc, rc);
1191
1192	uint64_t cbRamCfg = 0;
1193	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1194	AssertRCReturn(rc, rc);
1195
1196	uint32_t cbRamHoleSaved;
1197	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1198
1199	uint64_t cbRamSaved;
1200	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1201	AssertRCReturn(rc, rc);
1202
1203	if ( cbRamHoleCfg != cbRamHoleSaved
1204	\|\| cbRamCfg != cbRamSaved)
1205	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1206	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1207	return VINF_SUCCESS;
1208	}
1209
1210	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1211
1212	/**
1213	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1214	* info with it.
1215	*
1216	* @param pVM The VM handle.
1217	* @param pCur The current RAM range.
1218	* @param paLSPages The current array of live save page tracking
1219	* structures.
1220	* @param iPage The page index.
1221	*/
1222	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1223	{
1224	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1225	void const *pvPage;
1226	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1227	if (RT_SUCCESS(rc))
1228	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1229	else
1230	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1231	}
1232
1233
1234	/**
1235	* Verifies the CRC-32 for a page given it's raw bits.
1236	*
1237	* @param pvPage The page bits.
1238	* @param pCur The current RAM range.
1239	* @param paLSPages The current array of live save page tracking
1240	* structures.
1241	* @param iPage The page index.
1242	*/
1243	static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1244	{
1245	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1246	{
1247	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1248	Assert((!PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) && !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage])) \|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1249	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1250	("%08x != %08x for %RGp %R[pgmpage]\n", paLSPages[iPage].u32Crc, u32Crc,
1251	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1252	}
1253	}
1254
1255
1256	/**
1257	* Verfies the CRC-32 for a RAM page.
1258	*
1259	* @param pVM The VM handle.
1260	* @param pCur The current RAM range.
1261	* @param paLSPages The current array of live save page tracking
1262	* structures.
1263	* @param iPage The page index.
1264	*/
1265	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1266	{
1267	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1268	{
1269	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1270	void const *pvPage;
1271	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1272	if (RT_SUCCESS(rc))
1273	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage);
1274	}
1275	}
1276
1277	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1278
1279	/**
1280	* Scan for RAM page modifications and reprotect them.
1281	*
1282	* @param pVM The VM handle.
1283	* @param fFinalPass Whether this is the final pass or not.
1284	*/
1285	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1286	{
1287	/*
1288	* The RAM.
1289	*/
1290	RTGCPHYS GCPhysCur = 0;
1291	PPGMRAMRANGE pCur;
1292	pgmLock(pVM);
1293	do
1294	{
1295	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1296	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1297	{
1298	if ( pCur->GCPhysLast > GCPhysCur
1299	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1300	{
1301	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1302	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1303	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1304	GCPhysCur = 0;
1305	for (; iPage < cPages; iPage++)
1306	{
1307	/* Do yield first. */
1308	if ( !fFinalPass
1309	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1310	&& (iPage & 0x7ff) == 0x100
1311	#endif
1312	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1313	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1314	{
1315	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1316	break; /* restart */
1317	}
1318
1319	/* Skip already ignored pages. */
1320	if (paLSPages[iPage].fIgnore)
1321	continue;
1322
1323	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1324	{
1325	/*
1326	* A RAM page.
1327	*/
1328	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1329	{
1330	case PGM_PAGE_STATE_ALLOCATED:
1331	/** @todo Optimize this: Don't always re-enable write
1332	* monitoring if the page is known to be very busy. */
1333	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1334	{
1335	Assert(paLSPages[iPage].fWriteMonitored);
1336	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1337	Assert(pVM->pgm.s.cWrittenToPages > 0);
1338	pVM->pgm.s.cWrittenToPages--;
1339	}
1340	else
1341	{
1342	Assert(!paLSPages[iPage].fWriteMonitored);
1343	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1344	}
1345
1346	if (!paLSPages[iPage].fDirty)
1347	{
1348	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1349	if (paLSPages[iPage].fZero)
1350	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1351	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1352	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1353	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1354	}
1355
1356	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1357	pVM->pgm.s.cMonitoredPages++;
1358	paLSPages[iPage].fWriteMonitored = 1;
1359	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1360	paLSPages[iPage].fDirty = 1;
1361	paLSPages[iPage].fZero = 0;
1362	paLSPages[iPage].fShared = 0;
1363	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1364	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1365	#endif
1366	break;
1367
1368	case PGM_PAGE_STATE_WRITE_MONITORED:
1369	Assert(paLSPages[iPage].fWriteMonitored);
1370	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1371	{
1372	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1373	if (paLSPages[iPage].fWriteMonitoredJustNow)
1374	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1375	else
1376	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1377	#endif
1378	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1379	}
1380	else
1381	{
1382	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1383	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1384	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1385	#endif
1386	if (!paLSPages[iPage].fDirty)
1387	{
1388	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1389	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1390	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1391	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1392	}
1393	}
1394	break;
1395
1396	case PGM_PAGE_STATE_ZERO:
1397	if (!paLSPages[iPage].fZero)
1398	{
1399	if (!paLSPages[iPage].fDirty)
1400	{
1401	paLSPages[iPage].fDirty = 1;
1402	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1403	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1404	}
1405	paLSPages[iPage].fZero = 1;
1406	paLSPages[iPage].fShared = 0;
1407	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1408	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1409	#endif
1410	}
1411	break;
1412
1413	case PGM_PAGE_STATE_BALLOONED:
1414	if (!paLSPages[iPage].fZero)
1415	{
1416	if (!paLSPages[iPage].fDirty)
1417	{
1418	paLSPages[iPage].fDirty = 1;
1419	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1420	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1421	}
1422	paLSPages[iPage].fZero = 1;
1423	paLSPages[iPage].fShared = 0;
1424	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1425	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1426	#endif
1427	}
1428	break;
1429
1430	case PGM_PAGE_STATE_SHARED:
1431	if (!paLSPages[iPage].fShared)
1432	{
1433	if (!paLSPages[iPage].fDirty)
1434	{
1435	paLSPages[iPage].fDirty = 1;
1436	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1437	if (paLSPages[iPage].fZero)
1438	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1439	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1440	}
1441	paLSPages[iPage].fZero = 0;
1442	paLSPages[iPage].fShared = 1;
1443	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1444	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1445	#endif
1446	}
1447	break;
1448	}
1449	}
1450	else
1451	{
1452	/*
1453	* All other types => Ignore the page.
1454	*/
1455	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1456	paLSPages[iPage].fIgnore = 1;
1457	if (paLSPages[iPage].fWriteMonitored)
1458	{
1459	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1460	* pages! */
1461	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1462	{
1463	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1464	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1465	Assert(pVM->pgm.s.cMonitoredPages > 0);
1466	pVM->pgm.s.cMonitoredPages--;
1467	}
1468	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1469	{
1470	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1471	Assert(pVM->pgm.s.cWrittenToPages > 0);
1472	pVM->pgm.s.cWrittenToPages--;
1473	}
1474	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1475	}
1476
1477	/** @todo the counting doesn't quite work out here. fix later? */
1478	if (paLSPages[iPage].fDirty)
1479	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1480	else
1481	{
1482	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1483	if (paLSPages[iPage].fZero)
1484	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1485	}
1486	pVM->pgm.s.LiveSave.cIgnoredPages++;
1487	}
1488	} /* for each page in range */
1489
1490	if (GCPhysCur != 0)
1491	break; /* Yield + ramrange change */
1492	GCPhysCur = pCur->GCPhysLast;
1493	}
1494	} /* for each range */
1495	} while (pCur);
1496	pgmUnlock(pVM);
1497	}
1498
1499
1500	/**
1501	* Save quiescent RAM pages.
1502	*
1503	* @returns VBox status code.
1504	* @param pVM The VM handle.
1505	* @param pSSM The SSM handle.
1506	* @param fLiveSave Whether it's a live save or not.
1507	* @param uPass The pass number.
1508	*/
1509	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1510	{
1511	/*
1512	* The RAM.
1513	*/
1514	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1515	RTGCPHYS GCPhysCur = 0;
1516	PPGMRAMRANGE pCur;
1517	pgmLock(pVM);
1518	do
1519	{
1520	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1521	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1522	{
1523	if ( pCur->GCPhysLast > GCPhysCur
1524	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1525	{
1526	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1527	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1528	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1529	GCPhysCur = 0;
1530	for (; iPage < cPages; iPage++)
1531	{
1532	/* Do yield first. */
1533	if ( uPass != SSM_PASS_FINAL
1534	&& (iPage & 0x7ff) == 0x100
1535	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1536	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1537	{
1538	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1539	break; /* restart */
1540	}
1541
1542	/*
1543	* Only save pages that haven't changed since last scan and are dirty.
1544	*/
1545	if ( uPass != SSM_PASS_FINAL
1546	&& paLSPages)
1547	{
1548	if (!paLSPages[iPage].fDirty)
1549	continue;
1550	if (paLSPages[iPage].fWriteMonitoredJustNow)
1551	continue;
1552	if (paLSPages[iPage].fIgnore)
1553	continue;
1554	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM) /* in case of recent ramppings */
1555	continue;
1556	if ( PGM_PAGE_GET_STATE(&pCur->aPages[iPage])
1557	!= ( paLSPages[iPage].fZero
1558	? PGM_PAGE_STATE_ZERO
1559	: paLSPages[iPage].fShared
1560	? PGM_PAGE_STATE_SHARED
1561	: PGM_PAGE_STATE_WRITE_MONITORED))
1562	continue;
1563	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1564	continue;
1565	}
1566	else
1567	{
1568	if ( paLSPages
1569	&& !paLSPages[iPage].fDirty
1570	&& !paLSPages[iPage].fIgnore)
1571	{
1572	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1573	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1574	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1575	#endif
1576	continue;
1577	}
1578	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1579	continue;
1580	}
1581
1582	/*
1583	* Do the saving outside the PGM critsect since SSM may block on I/O.
1584	*/
1585	int rc;
1586	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1587	bool fZero = PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) \|\| PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]);
1588
1589	if (!fZero)
1590	{
1591	/*
1592	* Copy the page and then save it outside the lock (since any
1593	* SSM call may block).
1594	*/
1595	uint8_t abPage[PAGE_SIZE];
1596	void const *pvPage;
1597	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1598	if (RT_SUCCESS(rc))
1599	{
1600	memcpy(abPage, pvPage, PAGE_SIZE);
1601	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1602	if (paLSPages)
1603	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage);
1604	#endif
1605	}
1606	pgmUnlock(pVM);
1607	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1608
1609	if (GCPhys == GCPhysLast + PAGE_SIZE)
1610	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1611	else
1612	{
1613	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1614	SSMR3PutGCPhys(pSSM, GCPhys);
1615	}
1616	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1617	}
1618	else
1619	{
1620	/*
1621	* Dirty zero page.
1622	*/
1623	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1624	if (paLSPages)
1625	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1626	#endif
1627	pgmUnlock(pVM);
1628
1629	if (GCPhys == GCPhysLast + PAGE_SIZE)
1630	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1631	else
1632	{
1633	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1634	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1635	}
1636	}
1637	if (RT_FAILURE(rc))
1638	return rc;
1639
1640	pgmLock(pVM);
1641	GCPhysLast = GCPhys;
1642	if (paLSPages)
1643	{
1644	paLSPages[iPage].fDirty = 0;
1645	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1646	if (fZero)
1647	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1648	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1649	pVM->pgm.s.LiveSave.cSavedPages++;
1650	}
1651	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1652	{
1653	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1654	break; /* restart */
1655	}
1656
1657	} /* for each page in range */
1658
1659	if (GCPhysCur != 0)
1660	break; /* Yield + ramrange change */
1661	GCPhysCur = pCur->GCPhysLast;
1662	}
1663	} /* for each range */
1664	} while (pCur);
1665	pgmUnlock(pVM);
1666
1667	return VINF_SUCCESS;
1668	}
1669
1670
1671	/**
1672	* Cleans up RAM pages after a live save.
1673	*
1674	* @param pVM The VM handle.
1675	*/
1676	static void pgmR3DoneRamPages(PVM pVM)
1677	{
1678	/*
1679	* Free the tracking arrays and disable write monitoring.
1680	*
1681	* Play nice with the PGM lock in case we're called while the VM is still
1682	* running. This means we have to delay the freeing since we wish to use
1683	* paLSPages as an indicator of which RAM ranges which we need to scan for
1684	* write monitored pages.
1685	*/
1686	void *pvToFree = NULL;
1687	PPGMRAMRANGE pCur;
1688	uint32_t cMonitoredPages = 0;
1689	pgmLock(pVM);
1690	do
1691	{
1692	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1693	{
1694	if (pCur->paLSPages)
1695	{
1696	if (pvToFree)
1697	{
1698	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1699	pgmUnlock(pVM);
1700	MMR3HeapFree(pvToFree);
1701	pvToFree = NULL;
1702	pgmLock(pVM);
1703	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1704	break; /* start over again. */
1705	}
1706
1707	pvToFree = pCur->paLSPages;
1708	pCur->paLSPages = NULL;
1709
1710	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1711	while (iPage--)
1712	{
1713	PPGMPAGE pPage = &pCur->aPages[iPage];
1714	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1715	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1716	{
1717	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1718	cMonitoredPages++;
1719	}
1720	}
1721	}
1722	}
1723	} while (pCur);
1724
1725	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1726	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1727	pVM->pgm.s.cMonitoredPages = 0;
1728	else
1729	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1730
1731	pgmUnlock(pVM);
1732
1733	MMR3HeapFree(pvToFree);
1734	pvToFree = NULL;
1735	}
1736
1737
1738	/**
1739	* Execute a live save pass.
1740	*
1741	* @returns VBox status code.
1742	*
1743	* @param pVM The VM handle.
1744	* @param pSSM The SSM handle.
1745	*/
1746	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1747	{
1748	int rc;
1749
1750	/*
1751	* Save the MMIO2 and ROM range IDs in pass 0.
1752	*/
1753	if (uPass == 0)
1754	{
1755	rc = pgmR3SaveRamConfig(pVM, pSSM);
1756	if (RT_FAILURE(rc))
1757	return rc;
1758	rc = pgmR3SaveRomRanges(pVM, pSSM);
1759	if (RT_FAILURE(rc))
1760	return rc;
1761	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1762	if (RT_FAILURE(rc))
1763	return rc;
1764	}
1765	/*
1766	* Reset the page-per-second estimate to avoid inflation by the initial
1767	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1768	*/
1769	else if (uPass == 7)
1770	{
1771	pVM->pgm.s.LiveSave.cSavedPages = 0;
1772	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1773	}
1774
1775	/*
1776	* Do the scanning.
1777	*/
1778	pgmR3ScanRomPages(pVM);
1779	pgmR3ScanMmio2Pages(pVM, uPass);
1780	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1781	pgmR3PoolClearAll(pVM); /** @todo this could perhaps be optimized a bit. */
1782
1783	/*
1784	* Save the pages.
1785	*/
1786	if (uPass == 0)
1787	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1788	else
1789	rc = VINF_SUCCESS;
1790	if (RT_SUCCESS(rc))
1791	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1792	if (RT_SUCCESS(rc))
1793	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1794	if (RT_SUCCESS(rc))
1795	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1796	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1797
1798	return rc;
1799	}
1800
1801
1802	/**
1803	* Votes on whether the live save phase is done or not.
1804	*
1805	* @returns VBox status code.
1806	*
1807	* @param pVM The VM handle.
1808	* @param pSSM The SSM handle.
1809	* @param uPass The data pass.
1810	*/
1811	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1812	{
1813	/*
1814	* Update and calculate parameters used in the decision making.
1815	*/
1816	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1817
1818	/* update history. */
1819	pgmLock(pVM);
1820	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1821	pgmUnlock(pVM);
1822	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1823	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1824	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1825	+ cWrittenToPages;
1826	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1827	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1828	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1829
1830	/* calc shortterm average (4 passes). */
1831	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1832	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1833	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1834	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1835	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1836	uint32_t const cDirtyPagesShort = cTotal / 4;
1837	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1838
1839	/* calc longterm average. */
1840	cTotal = 0;
1841	if (uPass < cHistoryEntries)
1842	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1843	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1844	else
1845	for (i = 0; i < cHistoryEntries; i++)
1846	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1847	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1848	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1849
1850	/* estimate the speed */
1851	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1852	uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1853	/ ((long double)cNsElapsed / 1000000000.0) );
1854	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1855
1856	/*
1857	* Try make a decision.
1858	*/
1859	if ( cDirtyPagesShort <= cDirtyPagesLong
1860	&& ( cDirtyNow <= cDirtyPagesShort
1861	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1862	)
1863	)
1864	{
1865	if (uPass > 10)
1866	{
1867	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1868	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1869	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1870	if (cMsMaxDowntime < 32)
1871	cMsMaxDowntime = 32;
1872	if ( ( cMsLeftLong <= cMsMaxDowntime
1873	&& cMsLeftShort < cMsMaxDowntime)
1874	\|\| cMsLeftShort < cMsMaxDowntime / 2
1875	)
1876	{
1877	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1878	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1879	return VINF_SUCCESS;
1880	}
1881	}
1882	else
1883	{
1884	if ( ( cDirtyPagesShort <= 128
1885	&& cDirtyPagesLong <= 1024)
1886	\|\| cDirtyPagesLong <= 256
1887	)
1888	{
1889	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1890	return VINF_SUCCESS;
1891	}
1892	}
1893	}
1894	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1895	}
1896
1897
1898	/**
1899	* Prepare for a live save operation.
1900	*
1901	* This will attempt to allocate and initialize the tracking structures. It
1902	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1903	* pgmR3SaveDone will do the cleanups.
1904	*
1905	* @returns VBox status code.
1906	*
1907	* @param pVM The VM handle.
1908	* @param pSSM The SSM handle.
1909	*/
1910	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1911	{
1912	/*
1913	* Indicate that we will be using the write monitoring.
1914	*/
1915	pgmLock(pVM);
1916	/** @todo find a way of mediating this when more users are added. */
1917	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1918	{
1919	pgmUnlock(pVM);
1920	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1921	}
1922	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1923	pgmUnlock(pVM);
1924
1925	/*
1926	* Initialize the statistics.
1927	*/
1928	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1929	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1930	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1931	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1932	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1933	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1934	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1935	pVM->pgm.s.LiveSave.fActive = true;
1936	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
1937	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
1938	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
1939	pVM->pgm.s.LiveSave.cSavedPages = 0;
1940	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1941	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
1942
1943	/*
1944	* Per page type.
1945	*/
1946	int rc = pgmR3PrepRomPages(pVM);
1947	if (RT_SUCCESS(rc))
1948	rc = pgmR3PrepMmio2Pages(pVM);
1949	if (RT_SUCCESS(rc))
1950	rc = pgmR3PrepRamPages(pVM);
1951	return rc;
1952	}
1953
1954
1955	/**
1956	* Execute state save operation.
1957	*
1958	* @returns VBox status code.
1959	* @param pVM VM Handle.
1960	* @param pSSM SSM operation handle.
1961	*/
1962	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1963	{
1964	int rc;
1965	unsigned i;
1966	PPGM pPGM = &pVM->pgm.s;
1967
1968	/*
1969	* Lock PGM and set the no-more-writes indicator.
1970	*/
1971	pgmLock(pVM);
1972	pVM->pgm.s.fNoMorePhysWrites = true;
1973
1974	/*
1975	* Save basic data (required / unaffected by relocation).
1976	*/
1977	bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
1978	pVM->pgm.s.fMappingsFixed \|= pVM->pgm.s.fMappingsFixedRestored;
1979	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
1980	pVM->pgm.s.fMappingsFixed = fMappingsFixed;
1981
1982	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1983	SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]);
1984
1985	/*
1986	* The guest mappings.
1987	*/
1988	i = 0;
1989	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1990	{
1991	SSMR3PutU32( pSSM, i);
1992	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1993	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
1994	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1995	}
1996	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1997
1998	/*
1999	* Save the (remainder of the) memory.
2000	*/
2001	if (RT_SUCCESS(rc))
2002	{
2003	if (pVM->pgm.s.LiveSave.fActive)
2004	{
2005	pgmR3ScanRomPages(pVM);
2006	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2007	pgmR3ScanRamPages(pVM, true /fFinalPass/);
2008
2009	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
2010	if (RT_SUCCESS(rc))
2011	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2012	if (RT_SUCCESS(rc))
2013	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2014	}
2015	else
2016	{
2017	rc = pgmR3SaveRamConfig(pVM, pSSM);
2018	if (RT_SUCCESS(rc))
2019	rc = pgmR3SaveRomRanges(pVM, pSSM);
2020	if (RT_SUCCESS(rc))
2021	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2022	if (RT_SUCCESS(rc))
2023	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
2024	if (RT_SUCCESS(rc))
2025	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
2026	if (RT_SUCCESS(rc))
2027	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2028	if (RT_SUCCESS(rc))
2029	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2030	}
2031	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2032	}
2033
2034	pgmUnlock(pVM);
2035	return rc;
2036	}
2037
2038
2039	/**
2040	* Cleans up after an save state operation.
2041	*
2042	* @returns VBox status code.
2043	* @param pVM VM Handle.
2044	* @param pSSM SSM operation handle.
2045	*/
2046	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2047	{
2048	/*
2049	* Do per page type cleanups first.
2050	*/
2051	if (pVM->pgm.s.LiveSave.fActive)
2052	{
2053	pgmR3DoneRomPages(pVM);
2054	pgmR3DoneMmio2Pages(pVM);
2055	pgmR3DoneRamPages(pVM);
2056	}
2057
2058	/*
2059	* Clear the live save indicator and disengage write monitoring.
2060	*/
2061	pgmLock(pVM);
2062	pVM->pgm.s.LiveSave.fActive = false;
2063	/** @todo this is blindly assuming that we're the only user of write
2064	* monitoring. Fix this when more users are added. */
2065	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2066	pgmUnlock(pVM);
2067
2068	return VINF_SUCCESS;
2069	}
2070
2071
2072	/**
2073	* Prepare state load operation.
2074	*
2075	* @returns VBox status code.
2076	* @param pVM VM Handle.
2077	* @param pSSM SSM operation handle.
2078	*/
2079	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2080	{
2081	/*
2082	* Call the reset function to make sure all the memory is cleared.
2083	*/
2084	PGMR3Reset(pVM);
2085	pVM->pgm.s.LiveSave.fActive = false;
2086	NOREF(pSSM);
2087	return VINF_SUCCESS;
2088	}
2089
2090
2091	/**
2092	* Load an ignored page.
2093	*
2094	* @returns VBox status code.
2095	* @param pSSM The saved state handle.
2096	*/
2097	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2098	{
2099	uint8_t abPage[PAGE_SIZE];
2100	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2101	}
2102
2103
2104	/**
2105	* Loads a page without any bits in the saved state, i.e. making sure it's
2106	* really zero.
2107	*
2108	* @returns VBox status code.
2109	* @param pVM The VM handle.
2110	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2111	* state).
2112	* @param pPage The guest page tracking structure.
2113	* @param GCPhys The page address.
2114	* @param pRam The ram range (logging).
2115	*/
2116	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2117	{
2118	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2119	&& uType != PGMPAGETYPE_INVALID)
2120	return VERR_SSM_UNEXPECTED_DATA;
2121
2122	/* I think this should be sufficient. */
2123	if ( !PGM_PAGE_IS_ZERO(pPage)
2124	&& !PGM_PAGE_IS_BALLOONED(pPage))
2125	return VERR_SSM_UNEXPECTED_DATA;
2126
2127	NOREF(pVM);
2128	NOREF(GCPhys);
2129	NOREF(pRam);
2130	return VINF_SUCCESS;
2131	}
2132
2133
2134	/**
2135	* Loads a page from the saved state.
2136	*
2137	* @returns VBox status code.
2138	* @param pVM The VM handle.
2139	* @param pSSM The SSM handle.
2140	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2141	* state).
2142	* @param pPage The guest page tracking structure.
2143	* @param GCPhys The page address.
2144	* @param pRam The ram range (logging).
2145	*/
2146	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2147	{
2148	/*
2149	* Match up the type, dealing with MMIO2 aliases (dropped).
2150	*/
2151	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2152	\|\| uType == PGMPAGETYPE_INVALID,
2153	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2154	VERR_SSM_UNEXPECTED_DATA);
2155
2156	/*
2157	* Load the page.
2158	*/
2159	void *pvPage;
2160	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2161	if (RT_SUCCESS(rc))
2162	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2163
2164	return rc;
2165	}
2166
2167
2168	/**
2169	* Loads a page (counter part to pgmR3SavePage).
2170	*
2171	* @returns VBox status code, fully bitched errors.
2172	* @param pVM The VM handle.
2173	* @param pSSM The SSM handle.
2174	* @param uType The page type.
2175	* @param pPage The page.
2176	* @param GCPhys The page address.
2177	* @param pRam The RAM range (for error messages).
2178	*/
2179	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2180	{
2181	uint8_t uState;
2182	int rc = SSMR3GetU8(pSSM, &uState);
2183	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2184	if (uState == 0 /* zero */)
2185	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2186	else if (uState == 1)
2187	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2188	else
2189	rc = VERR_INTERNAL_ERROR;
2190	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2191	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2192	rc);
2193	return VINF_SUCCESS;
2194	}
2195
2196
2197	/**
2198	* Loads a shadowed ROM page.
2199	*
2200	* @returns VBox status code, errors are fully bitched.
2201	* @param pVM The VM handle.
2202	* @param pSSM The saved state handle.
2203	* @param pPage The page.
2204	* @param GCPhys The page address.
2205	* @param pRam The RAM range (for error messages).
2206	*/
2207	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2208	{
2209	/*
2210	* Load and set the protection first, then load the two pages, the first
2211	* one is the active the other is the passive.
2212	*/
2213	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2214	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2215
2216	uint8_t uProt;
2217	int rc = SSMR3GetU8(pSSM, &uProt);
2218	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2219	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2220	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2221	&& enmProt < PGMROMPROT_END,
2222	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2223	VERR_SSM_UNEXPECTED_DATA);
2224
2225	if (pRomPage->enmProt != enmProt)
2226	{
2227	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2228	AssertLogRelRCReturn(rc, rc);
2229	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2230	}
2231
2232	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2233	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2234	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2235	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2236
2237	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2238	* used down the line (will the 2nd page will be written to the first
2239	* one because of a false TLB hit since the TLB is using GCPhys and
2240	* doesn't check the HCPhys of the desired page). */
2241	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2242	if (RT_SUCCESS(rc))
2243	{
2244	pPageActive = pPage;
2245	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2246	}
2247	return rc;
2248	}
2249
2250	/**
2251	* Ram range flags and bits for older versions of the saved state.
2252	*
2253	* @returns VBox status code.
2254	*
2255	* @param pVM The VM handle
2256	* @param pSSM The SSM handle.
2257	* @param uVersion The saved state version.
2258	*/
2259	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2260	{
2261	PPGM pPGM = &pVM->pgm.s;
2262
2263	/*
2264	* Ram range flags and bits.
2265	*/
2266	uint32_t i = 0;
2267	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2268	{
2269	/* Check the seqence number / separator. */
2270	uint32_t u32Sep;
2271	int rc = SSMR3GetU32(pSSM, &u32Sep);
2272	if (RT_FAILURE(rc))
2273	return rc;
2274	if (u32Sep == ~0U)
2275	break;
2276	if (u32Sep != i)
2277	{
2278	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2279	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2280	}
2281	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2282
2283	/* Get the range details. */
2284	RTGCPHYS GCPhys;
2285	SSMR3GetGCPhys(pSSM, &GCPhys);
2286	RTGCPHYS GCPhysLast;
2287	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2288	RTGCPHYS cb;
2289	SSMR3GetGCPhys(pSSM, &cb);
2290	uint8_t fHaveBits;
2291	rc = SSMR3GetU8(pSSM, &fHaveBits);
2292	if (RT_FAILURE(rc))
2293	return rc;
2294	if (fHaveBits & ~1)
2295	{
2296	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2297	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2298	}
2299	size_t cchDesc = 0;
2300	char szDesc[256];
2301	szDesc[0] = '\0';
2302	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2303	{
2304	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2305	if (RT_FAILURE(rc))
2306	return rc;
2307	/* Since we've modified the description strings in r45878, only compare
2308	them if the saved state is more recent. */
2309	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2310	cchDesc = strlen(szDesc);
2311	}
2312
2313	/*
2314	* Match it up with the current range.
2315	*
2316	* Note there is a hack for dealing with the high BIOS mapping
2317	* in the old saved state format, this means we might not have
2318	* a 1:1 match on success.
2319	*/
2320	if ( ( GCPhys != pRam->GCPhys
2321	\|\| GCPhysLast != pRam->GCPhysLast
2322	\|\| cb != pRam->cb
2323	\|\| ( cchDesc
2324	&& strcmp(szDesc, pRam->pszDesc)) )
2325	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2326	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2327	\|\| GCPhys != UINT32_C(0xfff80000)
2328	\|\| GCPhysLast != UINT32_C(0xffffffff)
2329	\|\| pRam->GCPhysLast != GCPhysLast
2330	\|\| pRam->GCPhys < GCPhys
2331	\|\| !fHaveBits)
2332	)
2333	{
2334	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2335	"State : %RGp-%RGp %RGp bytes %s %s\n",
2336	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2337	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2338	/*
2339	* If we're loading a state for debugging purpose, don't make a fuss if
2340	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2341	*/
2342	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2343	\|\| GCPhys < 8 * _1M)
2344	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2345	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2346	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2347	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2348
2349	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2350	continue;
2351	}
2352
2353	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2354	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2355	{
2356	/*
2357	* Load the pages one by one.
2358	*/
2359	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2360	{
2361	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2362	PPGMPAGE pPage = &pRam->aPages[iPage];
2363	uint8_t uType;
2364	rc = SSMR3GetU8(pSSM, &uType);
2365	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2366	if (uType == PGMPAGETYPE_ROM_SHADOW)
2367	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2368	else
2369	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2370	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2371	}
2372	}
2373	else
2374	{
2375	/*
2376	* Old format.
2377	*/
2378
2379	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2380	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2381	uint32_t fFlags = 0;
2382	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2383	{
2384	uint16_t u16Flags;
2385	rc = SSMR3GetU16(pSSM, &u16Flags);
2386	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2387	fFlags \|= u16Flags;
2388	}
2389
2390	/* Load the bits */
2391	if ( !fHaveBits
2392	&& GCPhysLast < UINT32_C(0xe0000000))
2393	{
2394	/*
2395	* Dynamic chunks.
2396	*/
2397	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2398	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2399	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2400	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2401
2402	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2403	{
2404	uint8_t fPresent;
2405	rc = SSMR3GetU8(pSSM, &fPresent);
2406	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2407	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2408	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2409	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2410
2411	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2412	{
2413	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2414	PPGMPAGE pPage = &pRam->aPages[iPage];
2415	if (fPresent)
2416	{
2417	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2418	rc = pgmR3LoadPageToDevNullOld(pSSM);
2419	else
2420	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2421	}
2422	else
2423	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2424	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2425	}
2426	}
2427	}
2428	else if (pRam->pvR3)
2429	{
2430	/*
2431	* MMIO2.
2432	*/
2433	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2434	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2435	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2436	AssertLogRelMsgReturn(pRam->pvR3,
2437	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2438	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2439
2440	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2441	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2442	}
2443	else if (GCPhysLast < UINT32_C(0xfff80000))
2444	{
2445	/*
2446	* PCI MMIO, no pages saved.
2447	*/
2448	}
2449	else
2450	{
2451	/*
2452	* Load the 0xfff80000..0xffffffff BIOS range.
2453	* It starts with X reserved pages that we have to skip over since
2454	* the RAMRANGE create by the new code won't include those.
2455	*/
2456	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2457	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2458	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2459	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2460	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2461	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2462	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2463
2464	/* Skip wasted reserved pages before the ROM. */
2465	while (GCPhys < pRam->GCPhys)
2466	{
2467	rc = pgmR3LoadPageToDevNullOld(pSSM);
2468	GCPhys += PAGE_SIZE;
2469	}
2470
2471	/* Load the bios pages. */
2472	cPages = pRam->cb >> PAGE_SHIFT;
2473	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2474	{
2475	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2476	PPGMPAGE pPage = &pRam->aPages[iPage];
2477
2478	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2479	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2480	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2481	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2482	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2483	}
2484	}
2485	}
2486	}
2487
2488	return VINF_SUCCESS;
2489	}
2490
2491
2492	/**
2493	* Worker for pgmR3Load and pgmR3LoadLocked.
2494	*
2495	* @returns VBox status code.
2496	*
2497	* @param pVM The VM handle.
2498	* @param pSSM The SSM handle.
2499	* @param uVersion The saved state version.
2500	*
2501	* @todo This needs splitting up if more record types or code twists are
2502	* added...
2503	*/
2504	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2505	{
2506	/*
2507	* Process page records until we hit the terminator.
2508	*/
2509	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2510	PPGMRAMRANGE pRamHint = NULL;
2511	uint8_t id = UINT8_MAX;
2512	uint32_t iPage = UINT32_MAX - 10;
2513	PPGMROMRANGE pRom = NULL;
2514	PPGMMMIO2RANGE pMmio2 = NULL;
2515	for (;;)
2516	{
2517	/*
2518	* Get the record type and flags.
2519	*/
2520	uint8_t u8;
2521	int rc = SSMR3GetU8(pSSM, &u8);
2522	if (RT_FAILURE(rc))
2523	return rc;
2524	if (u8 == PGM_STATE_REC_END)
2525	return VINF_SUCCESS;
2526	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2527	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2528	{
2529	/*
2530	* RAM page.
2531	*/
2532	case PGM_STATE_REC_RAM_ZERO:
2533	case PGM_STATE_REC_RAM_RAW:
2534	{
2535	/*
2536	* Get the address and resolve it into a page descriptor.
2537	*/
2538	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2539	GCPhys += PAGE_SIZE;
2540	else
2541	{
2542	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2543	if (RT_FAILURE(rc))
2544	return rc;
2545	}
2546	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2547
2548	PPGMPAGE pPage;
2549	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2550	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2551
2552	/*
2553	* Take action according to the record type.
2554	*/
2555	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2556	{
2557	case PGM_STATE_REC_RAM_ZERO:
2558	{
2559	if ( PGM_PAGE_IS_ZERO(pPage)
2560	\|\| PGM_PAGE_IS_BALLOONED(pPage))
2561	break;
2562	/** @todo implement zero page replacing. */
2563	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2564	void *pvDstPage;
2565	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2566	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2567	ASMMemZeroPage(pvDstPage);
2568	break;
2569	}
2570
2571	case PGM_STATE_REC_RAM_RAW:
2572	{
2573	void *pvDstPage;
2574	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2575	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2576	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2577	if (RT_FAILURE(rc))
2578	return rc;
2579	break;
2580	}
2581
2582	default:
2583	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2584	}
2585	id = UINT8_MAX;
2586	break;
2587	}
2588
2589	/*
2590	* MMIO2 page.
2591	*/
2592	case PGM_STATE_REC_MMIO2_RAW:
2593	case PGM_STATE_REC_MMIO2_ZERO:
2594	{
2595	/*
2596	* Get the ID + page number and resolved that into a MMIO2 page.
2597	*/
2598	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2599	iPage++;
2600	else
2601	{
2602	SSMR3GetU8(pSSM, &id);
2603	rc = SSMR3GetU32(pSSM, &iPage);
2604	if (RT_FAILURE(rc))
2605	return rc;
2606	}
2607	if ( !pMmio2
2608	\|\| pMmio2->idSavedState != id)
2609	{
2610	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2611	if (pMmio2->idSavedState == id)
2612	break;
2613	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2614	}
2615	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2616	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2617
2618	/*
2619	* Load the page bits.
2620	*/
2621	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2622	ASMMemZeroPage(pvDstPage);
2623	else
2624	{
2625	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2626	if (RT_FAILURE(rc))
2627	return rc;
2628	}
2629	GCPhys = NIL_RTGCPHYS;
2630	break;
2631	}
2632
2633	/*
2634	* ROM pages.
2635	*/
2636	case PGM_STATE_REC_ROM_VIRGIN:
2637	case PGM_STATE_REC_ROM_SHW_RAW:
2638	case PGM_STATE_REC_ROM_SHW_ZERO:
2639	case PGM_STATE_REC_ROM_PROT:
2640	{
2641	/*
2642	* Get the ID + page number and resolved that into a ROM page descriptor.
2643	*/
2644	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2645	iPage++;
2646	else
2647	{
2648	SSMR3GetU8(pSSM, &id);
2649	rc = SSMR3GetU32(pSSM, &iPage);
2650	if (RT_FAILURE(rc))
2651	return rc;
2652	}
2653	if ( !pRom
2654	\|\| pRom->idSavedState != id)
2655	{
2656	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2657	if (pRom->idSavedState == id)
2658	break;
2659	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2660	}
2661	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2662	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2663	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2664
2665	/*
2666	* Get and set the protection.
2667	*/
2668	uint8_t u8Prot;
2669	rc = SSMR3GetU8(pSSM, &u8Prot);
2670	if (RT_FAILURE(rc))
2671	return rc;
2672	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2673	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2674
2675	if (enmProt != pRomPage->enmProt)
2676	{
2677	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2678	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2679	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2680	GCPhys, enmProt, pRom->pszDesc);
2681	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2682	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2683	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2684	}
2685	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2686	break; /* done */
2687
2688	/*
2689	* Get the right page descriptor.
2690	*/
2691	PPGMPAGE pRealPage;
2692	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2693	{
2694	case PGM_STATE_REC_ROM_VIRGIN:
2695	if (!PGMROMPROT_IS_ROM(enmProt))
2696	pRealPage = &pRomPage->Virgin;
2697	else
2698	pRealPage = NULL;
2699	break;
2700
2701	case PGM_STATE_REC_ROM_SHW_RAW:
2702	case PGM_STATE_REC_ROM_SHW_ZERO:
2703	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2704	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2705	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2706	GCPhys, enmProt, pRom->pszDesc);
2707	if (PGMROMPROT_IS_ROM(enmProt))
2708	pRealPage = &pRomPage->Shadow;
2709	else
2710	pRealPage = NULL;
2711	break;
2712
2713	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2714	}
2715	if (!pRealPage)
2716	{
2717	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2718	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2719	}
2720
2721	/*
2722	* Make it writable and map it (if necessary).
2723	*/
2724	void *pvDstPage = NULL;
2725	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2726	{
2727	case PGM_STATE_REC_ROM_SHW_ZERO:
2728	if ( PGM_PAGE_IS_ZERO(pRealPage)
2729	\|\| PGM_PAGE_IS_BALLOONED(pRealPage))
2730	break;
2731	/** @todo implement zero page replacing. */
2732	/* fall thru */
2733	case PGM_STATE_REC_ROM_VIRGIN:
2734	case PGM_STATE_REC_ROM_SHW_RAW:
2735	{
2736	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2737	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2738	break;
2739	}
2740	}
2741
2742	/*
2743	* Load the bits.
2744	*/
2745	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2746	{
2747	case PGM_STATE_REC_ROM_SHW_ZERO:
2748	if (pvDstPage)
2749	ASMMemZeroPage(pvDstPage);
2750	break;
2751
2752	case PGM_STATE_REC_ROM_VIRGIN:
2753	case PGM_STATE_REC_ROM_SHW_RAW:
2754	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2755	if (RT_FAILURE(rc))
2756	return rc;
2757	break;
2758	}
2759	GCPhys = NIL_RTGCPHYS;
2760	break;
2761	}
2762
2763	/*
2764	* Unknown type.
2765	*/
2766	default:
2767	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2768	}
2769	} /* forever */
2770	}
2771
2772
2773	/**
2774	* Worker for pgmR3Load.
2775	*
2776	* @returns VBox status code.
2777	*
2778	* @param pVM The VM handle.
2779	* @param pSSM The SSM handle.
2780	* @param uVersion The saved state version.
2781	*/
2782	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2783	{
2784	PPGM pPGM = &pVM->pgm.s;
2785	int rc;
2786	uint32_t u32Sep;
2787
2788	/*
2789	* Load basic data (required / unaffected by relocation).
2790	*/
2791	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2792	{
2793	if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2794	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2795	else
2796	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFieldsPreBalloon[0]);
2797
2798	AssertLogRelRCReturn(rc, rc);
2799
2800	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2801	{
2802	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2803	AssertLogRelRCReturn(rc, rc);
2804	}
2805	}
2806	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2807	{
2808	AssertRelease(pVM->cCpus == 1);
2809
2810	PGMOLD pgmOld;
2811	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2812	AssertLogRelRCReturn(rc, rc);
2813
2814	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2815	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2816	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2817
2818	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2819	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2820	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2821	}
2822	else
2823	{
2824	AssertRelease(pVM->cCpus == 1);
2825
2826	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2827	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2828	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2829
2830	uint32_t cbRamSizeIgnored;
2831	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2832	if (RT_FAILURE(rc))
2833	return rc;
2834	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2835
2836	uint32_t u32 = 0;
2837	SSMR3GetUInt(pSSM, &u32);
2838	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2839	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2840	RTUINT uGuestMode;
2841	SSMR3GetUInt(pSSM, &uGuestMode);
2842	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2843
2844	/* check separator. */
2845	SSMR3GetU32(pSSM, &u32Sep);
2846	if (RT_FAILURE(rc))
2847	return rc;
2848	if (u32Sep != (uint32_t)~0)
2849	{
2850	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2851	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2852	}
2853	}
2854
2855	/*
2856	* The guest mappings - skipped now, see re-fixation in the caller.
2857	*/
2858	uint32_t i = 0;
2859	for (;; i++)
2860	{
2861	rc = SSMR3GetU32(pSSM, &u32Sep); /* seqence number */
2862	if (RT_FAILURE(rc))
2863	return rc;
2864	if (u32Sep == ~0U)
2865	break;
2866	AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2867
2868	char szDesc[256];
2869	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2870	if (RT_FAILURE(rc))
2871	return rc;
2872	RTGCPTR GCPtrIgnore;
2873	SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
2874	rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
2875	if (RT_FAILURE(rc))
2876	return rc;
2877	}
2878
2879	/*
2880	* Load the RAM contents.
2881	*/
2882	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2883	{
2884	if (!pVM->pgm.s.LiveSave.fActive)
2885	{
2886	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2887	{
2888	rc = pgmR3LoadRamConfig(pVM, pSSM);
2889	if (RT_FAILURE(rc))
2890	return rc;
2891	}
2892	rc = pgmR3LoadRomRanges(pVM, pSSM);
2893	if (RT_FAILURE(rc))
2894	return rc;
2895	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2896	if (RT_FAILURE(rc))
2897	return rc;
2898	}
2899
2900	rc = pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2901	}
2902	else
2903	rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2904
2905	/* Refresh balloon accounting. */
2906	if (pVM->pgm.s.cBalloonedPages)
2907	{
2908	rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
2909	AssertRC(rc);
2910	}
2911	return rc;
2912	}
2913
2914
2915	/**
2916	* Execute state load operation.
2917	*
2918	* @returns VBox status code.
2919	* @param pVM VM Handle.
2920	* @param pSSM SSM operation handle.
2921	* @param uVersion Data layout version.
2922	* @param uPass The data pass.
2923	*/
2924	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2925	{
2926	int rc;
2927	PPGM pPGM = &pVM->pgm.s;
2928
2929	/*
2930	* Validate version.
2931	*/
2932	if ( ( uPass != SSM_PASS_FINAL
2933	&& uVersion != PGM_SAVED_STATE_VERSION
2934	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
2935	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2936	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
2937	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
2938	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
2939	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
2940	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
2941	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
2942	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2943	)
2944	{
2945	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
2946	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2947	}
2948
2949	/*
2950	* Do the loading while owning the lock because a bunch of the functions
2951	* we're using requires this.
2952	*/
2953	if (uPass != SSM_PASS_FINAL)
2954	{
2955	pgmLock(pVM);
2956	if (uPass != 0)
2957	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2958	else
2959	{
2960	pVM->pgm.s.LiveSave.fActive = true;
2961	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2962	rc = pgmR3LoadRamConfig(pVM, pSSM);
2963	else
2964	rc = VINF_SUCCESS;
2965	if (RT_SUCCESS(rc))
2966	rc = pgmR3LoadRomRanges(pVM, pSSM);
2967	if (RT_SUCCESS(rc))
2968	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2969	if (RT_SUCCESS(rc))
2970	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2971	}
2972	pgmUnlock(pVM);
2973	}
2974	else
2975	{
2976	pgmLock(pVM);
2977	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
2978	pVM->pgm.s.LiveSave.fActive = false;
2979	pgmUnlock(pVM);
2980	if (RT_SUCCESS(rc))
2981	{
2982	/*
2983	* We require a full resync now.
2984	*/
2985	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2986	{
2987	PVMCPU pVCpu = &pVM->aCpus[i];
2988	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2989	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2990	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2991	}
2992
2993	pgmR3HandlerPhysicalUpdateAll(pVM);
2994
2995	/*
2996	* Change the paging mode and restore PGMCPU::GCPhysCR3.
2997	* (The latter requires the CPUM state to be restored already.)
2998	*/
2999	if (CPUMR3IsStateRestorePending(pVM))
3000	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3001	N_("PGM was unexpectedly restored before CPUM"));
3002
3003	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3004	{
3005	PVMCPU pVCpu = &pVM->aCpus[i];
3006
3007	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3008	AssertLogRelRCReturn(rc, rc);
3009
3010	/* Restore pVM->pgm.s.GCPhysCR3. */
3011	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3012	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3013	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3014	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3015	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3016	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3017	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3018	else
3019	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3020	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3021	}
3022
3023	/*
3024	* Try re-fixate the guest mappings.
3025	*/
3026	pVM->pgm.s.fMappingsFixedRestored = false;
3027	if ( pVM->pgm.s.fMappingsFixed
3028	&& pgmMapAreMappingsEnabled(&pVM->pgm.s))
3029	{
3030	RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
3031	uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
3032	pVM->pgm.s.fMappingsFixed = false;
3033
3034	uint32_t cbRequired;
3035	int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
3036	if ( RT_SUCCESS(rc2)
3037	&& cbRequired > cbFixed)
3038	rc2 = VERR_OUT_OF_RANGE;
3039	if (RT_SUCCESS(rc2))
3040	rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
3041	if (RT_FAILURE(rc2))
3042	{
3043	LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
3044	GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
3045	pVM->pgm.s.fMappingsFixed = false;
3046	pVM->pgm.s.fMappingsFixedRestored = true;
3047	pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
3048	pVM->pgm.s.cbMappingFixed = cbFixed;
3049	}
3050	}
3051	else
3052	{
3053	/* We used to set fixed + disabled while we only use disabled now,
3054	so wipe the state to avoid any confusion. */
3055	pVM->pgm.s.fMappingsFixed = false;
3056	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3057	pVM->pgm.s.cbMappingFixed = 0;
3058	}
3059
3060	/*
3061	* If we have floating mappings, do a CR3 sync now to make sure the HMA
3062	* doesn't conflict with guest code / data and thereby cause trouble
3063	* when restoring other components like PATM.
3064	*/
3065	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3066	{
3067	PVMCPU pVCpu = &pVM->aCpus[0];
3068	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3069	if (RT_FAILURE(rc))
3070	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3071	N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3072
3073	/* Make sure to re-sync before executing code. */
3074	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3075	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3076	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3077	}
3078	}
3079	}
3080
3081	return rc;
3082	}
3083
3084
3085	/**
3086	* Registers the saved state callbacks with SSM.
3087	*
3088	* @returns VBox status code.
3089	* @param pVM Pointer to VM structure.
3090	* @param cbRam The RAM size.
3091	*/
3092	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3093	{
3094	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3095	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3096	NULL, pgmR3SaveExec, pgmR3SaveDone,
3097	pgmR3LoadPrep, pgmR3Load, NULL);
3098	}
3099

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source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 28425

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