PGMSavedState.cpp@ 24808

Last change on this file since 24808 was 24808, checked in by vboxsync, 15 years ago
PGMSavedState.cpp: More teleportation trickery.
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1	/* $Id: PGMSavedState.cpp 24808 2009-11-19 18:19:36Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/pgm.h>
28	#include <VBox/stam.h>
29	#include <VBox/ssm.h>
30	#include <VBox/pdm.h>
31	#include "PGMInternal.h"
32	#include <VBox/vm.h>
33
34	#include <VBox/param.h>
35	#include <VBox/err.h>
36
37	#include <iprt/asm.h>
38	#include <iprt/assert.h>
39	#include <iprt/crc32.h>
40	#include <iprt/mem.h>
41	#include <iprt/sha.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44
45
46	/*******************************************************************************
47	* Defined Constants And Macros *
48	*******************************************************************************/
49	/** Saved state data unit version. */
50	#define PGM_SAVED_STATE_VERSION 11
51	/** Saved state data unit version used during 3.1 development, misses the RAM
52	* config. */
53	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
54	/** Saved state data unit version for 3.0 (pre teleportation). */
55	#define PGM_SAVED_STATE_VERSION_3_0_0 9
56	/** Saved state data unit version for 2.2.2 and later. */
57	#define PGM_SAVED_STATE_VERSION_2_2_2 8
58	/** Saved state data unit version for 2.2.0. */
59	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
60	/** Saved state data unit version. */
61	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
62
63
64	/** @name Sparse state record types
65	* @{ */
66	/** Zero page. No data. */
67	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
68	/** Raw page. */
69	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
70	/** Raw MMIO2 page. */
71	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
72	/** Zero MMIO2 page. */
73	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
74	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
75	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
76	/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
77	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
78	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
79	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
80	/** ROM protection (8-bit). */
81	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
82	/** The last record type. */
83	#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
84	/** End marker. */
85	#define PGM_STATE_REC_END UINT8_C(0xff)
86	/** Flag indicating that the data is preceeded by the page address.
87	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
88	* range ID and a 32-bit page index.
89	*/
90	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
91	/** @} */
92
93	/** The CRC-32 for a zero page. */
94	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
95	/** The CRC-32 for a zero half page. */
96	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
97
98
99	/*******************************************************************************
100	* Structures and Typedefs *
101	*******************************************************************************/
102	/** For loading old saved states. (pre-smp) */
103	typedef struct
104	{
105	/** If set no conflict checks are required. (boolean) */
106	bool fMappingsFixed;
107	/** Size of fixed mapping */
108	uint32_t cbMappingFixed;
109	/** Base address (GC) of fixed mapping */
110	RTGCPTR GCPtrMappingFixed;
111	/** A20 gate mask.
112	* Our current approach to A20 emulation is to let REM do it and don't bother
113	* anywhere else. The interesting Guests will be operating with it enabled anyway.
114	* But whould need arrise, we'll subject physical addresses to this mask. */
115	RTGCPHYS GCPhysA20Mask;
116	/** A20 gate state - boolean! */
117	bool fA20Enabled;
118	/** The guest paging mode. */
119	PGMMODE enmGuestMode;
120	} PGMOLD;
121
122
123	/*******************************************************************************
124	* Global Variables *
125	*******************************************************************************/
126	/** PGM fields to save/load. */
127	static const SSMFIELD s_aPGMFields[] =
128	{
129	SSMFIELD_ENTRY( PGM, fMappingsFixed),
130	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
131	SSMFIELD_ENTRY( PGM, cbMappingFixed),
132	SSMFIELD_ENTRY_TERM()
133	};
134
135	static const SSMFIELD s_aPGMCpuFields[] =
136	{
137	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
138	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
139	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
140	SSMFIELD_ENTRY_TERM()
141	};
142
143	static const SSMFIELD s_aPGMFields_Old[] =
144	{
145	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
146	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
147	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
148	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
149	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
150	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
151	SSMFIELD_ENTRY_TERM()
152	};
153
154
155	/**
156	* Find the ROM tracking structure for the given page.
157	*
158	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
159	* that it's a ROM page.
160	* @param pVM The VM handle.
161	* @param GCPhys The address of the ROM page.
162	*/
163	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
164	{
165	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
166	pRomRange;
167	pRomRange = pRomRange->CTX_SUFF(pNext))
168	{
169	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
170	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
171	return &pRomRange->aPages[off >> PAGE_SHIFT];
172	}
173	return NULL;
174	}
175
176
177	/**
178	* Prepares the ROM pages for a live save.
179	*
180	* @returns VBox status code.
181	* @param pVM The VM handle.
182	*/
183	static int pgmR3PrepRomPages(PVM pVM)
184	{
185	/*
186	* Initialize the live save tracking in the ROM page descriptors.
187	*/
188	pgmLock(pVM);
189	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
190	{
191	PPGMRAMRANGE pRamHint = NULL;;
192	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
193
194	for (uint32_t iPage = 0; iPage < cPages; iPage++)
195	{
196	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
197	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
198	pRom->aPages[iPage].LiveSave.fDirty = true;
199	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
200	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
201	{
202	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
203	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
204	else
205	{
206	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
207	PPGMPAGE pPage;
208	int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
209	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
210	if (RT_SUCCESS(rc))
211	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage);
212	else
213	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
214	}
215	}
216	}
217
218	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
219	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
220	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
221	}
222	pgmUnlock(pVM);
223
224	return VINF_SUCCESS;
225	}
226
227
228	/**
229	* Assigns IDs to the ROM ranges and saves them.
230	*
231	* @returns VBox status code.
232	* @param pVM The VM handle.
233	* @param pSSM Saved state handle.
234	*/
235	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
236	{
237	pgmLock(pVM);
238	uint8_t id = 1;
239	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
240	{
241	pRom->idSavedState = id;
242	SSMR3PutU8(pSSM, id);
243	SSMR3PutStrZ(pSSM, ""); /* device name */
244	SSMR3PutU32(pSSM, 0); /* device instance */
245	SSMR3PutU8(pSSM, 0); /* region */
246	SSMR3PutStrZ(pSSM, pRom->pszDesc);
247	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
248	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
249	if (RT_FAILURE(rc))
250	break;
251	}
252	pgmUnlock(pVM);
253	return SSMR3PutU8(pSSM, UINT8_MAX);
254	}
255
256
257	/**
258	* Loads the ROM range ID assignments.
259	*
260	* @returns VBox status code.
261	*
262	* @param pVM The VM handle.
263	* @param pSSM The saved state handle.
264	*/
265	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
266	{
267	Assert(PGMIsLockOwner(pVM));
268
269	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
270	pRom->idSavedState = UINT8_MAX;
271
272	for (;;)
273	{
274	/*
275	* Read the data.
276	*/
277	uint8_t id;
278	int rc = SSMR3GetU8(pSSM, &id);
279	if (RT_FAILURE(rc))
280	return rc;
281	if (id == UINT8_MAX)
282	{
283	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
284	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX, ("%s\n", pRom->pszDesc));
285	return VINF_SUCCESS; /* the end */
286	}
287	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
288
289	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szDeviceName)];
290	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
291	AssertLogRelRCReturn(rc, rc);
292
293	uint32_t uInstance;
294	SSMR3GetU32(pSSM, &uInstance);
295	uint8_t iRegion;
296	SSMR3GetU8(pSSM, &iRegion);
297
298	char szDesc[64];
299	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
300	AssertLogRelRCReturn(rc, rc);
301
302	RTGCPHYS GCPhys;
303	SSMR3GetGCPhys(pSSM, &GCPhys);
304	RTGCPHYS cb;
305	rc = SSMR3GetGCPhys(pSSM, &cb);
306	if (RT_FAILURE(rc))
307	return rc;
308	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
309	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
310
311	/*
312	* Locate a matching ROM range.
313	*/
314	AssertLogRelMsgReturn( uInstance == 0
315	&& iRegion == 0
316	&& szDevName[0] == '\0',
317	("GCPhys=%RGp %s\n", GCPhys, szDesc),
318	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
319	PPGMROMRANGE pRom;
320	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
321	{
322	if ( pRom->idSavedState == UINT8_MAX
323	&& !strcmp(pRom->pszDesc, szDesc))
324	{
325	pRom->idSavedState = id;
326	break;
327	}
328	}
329	if (!pRom)
330	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
331	} /* forever */
332	}
333
334
335	/**
336	* Scan ROM pages.
337	*
338	* @param pVM The VM handle.
339	*/
340	static void pgmR3ScanRomPages(PVM pVM)
341	{
342	/*
343	* The shadow ROMs.
344	*/
345	pgmLock(pVM);
346	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
347	{
348	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
349	{
350	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
351	for (uint32_t iPage = 0; iPage < cPages; iPage++)
352	{
353	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
354	if (pRomPage->LiveSave.fWrittenTo)
355	{
356	pRomPage->LiveSave.fWrittenTo = false;
357	if (!pRomPage->LiveSave.fDirty)
358	{
359	pRomPage->LiveSave.fDirty = true;
360	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
361	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
362	}
363	pRomPage->LiveSave.fDirtiedRecently = true;
364	}
365	else
366	pRomPage->LiveSave.fDirtiedRecently = false;
367	}
368	}
369	}
370	pgmUnlock(pVM);
371	}
372
373
374	/**
375	* Takes care of the virgin ROM pages in the first pass.
376	*
377	* This is an attempt at simplifying the handling of ROM pages a little bit.
378	* This ASSUMES that no new ROM ranges will be added and that they won't be
379	* relinked in any way.
380	*
381	* @param pVM The VM handle.
382	* @param pSSM The SSM handle.
383	* @param fLiveSave Whether we're in a live save or not.
384	*/
385	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
386	{
387	pgmLock(pVM);
388	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
389	{
390	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
391	for (uint32_t iPage = 0; iPage < cPages; iPage++)
392	{
393	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
394	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
395
396	/* Get the virgin page descriptor. */
397	PPGMPAGE pPage;
398	if (PGMROMPROT_IS_ROM(enmProt))
399	pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
400	else
401	pPage = &pRom->aPages[iPage].Virgin;
402
403	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
404	int rc = VINF_SUCCESS;
405	char abPage[PAGE_SIZE];
406	if (!PGM_PAGE_IS_ZERO(pPage))
407	{
408	void const *pvPage;
409	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
410	if (RT_SUCCESS(rc))
411	memcpy(abPage, pvPage, PAGE_SIZE);
412	}
413	else
414	ASMMemZeroPage(abPage);
415	pgmUnlock(pVM);
416	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
417
418	/* Save it. */
419	if (iPage > 0)
420	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
421	else
422	{
423	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
424	SSMR3PutU8(pSSM, pRom->idSavedState);
425	SSMR3PutU32(pSSM, iPage);
426	}
427	SSMR3PutU8(pSSM, (uint8_t)enmProt);
428	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
429	if (RT_FAILURE(rc))
430	return rc;
431
432	/* Update state. */
433	pgmLock(pVM);
434	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
435	if (fLiveSave)
436	{
437	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
438	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
439	}
440	}
441	}
442	pgmUnlock(pVM);
443	return VINF_SUCCESS;
444	}
445
446
447	/**
448	* Saves dirty pages in the shadowed ROM ranges.
449	*
450	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
451	*
452	* @returns VBox status code.
453	* @param pVM The VM handle.
454	* @param pSSM The SSM handle.
455	* @param fLiveSave Whether it's a live save or not.
456	* @param fFinalPass Whether this is the final pass or not.
457	*/
458	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
459	{
460	/*
461	* The Shadowed ROMs.
462	*
463	* ASSUMES that the ROM ranges are fixed.
464	* ASSUMES that all the ROM ranges are mapped.
465	*/
466	pgmLock(pVM);
467	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
468	{
469	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
470	{
471	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
472	uint32_t iPrevPage = cPages;
473	for (uint32_t iPage = 0; iPage < cPages; iPage++)
474	{
475	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
476	if ( !fLiveSave
477	\|\| ( pRomPage->LiveSave.fDirty
478	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
479	&& !pRomPage->LiveSave.fWrittenTo)
480	\|\| fFinalPass
481	)
482	)
483	)
484	{
485	uint8_t abPage[PAGE_SIZE];
486	PGMROMPROT enmProt = pRomPage->enmProt;
487	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
488	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
489	bool fZero = PGM_PAGE_IS_ZERO(pPage);
490	int rc = VINF_SUCCESS;
491	if (!fZero)
492	{
493	void const *pvPage;
494	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
495	if (RT_SUCCESS(rc))
496	memcpy(abPage, pvPage, PAGE_SIZE);
497	}
498	if (fLiveSave && RT_SUCCESS(rc))
499	{
500	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
501	pRomPage->LiveSave.fDirty = false;
502	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
503	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
504	}
505	pgmUnlock(pVM);
506	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
507
508	if (iPage - 1U == iPrevPage && iPage > 0)
509	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
510	else
511	{
512	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
513	SSMR3PutU8(pSSM, pRom->idSavedState);
514	SSMR3PutU32(pSSM, iPage);
515	}
516	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
517	if (!fZero)
518	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
519	if (RT_FAILURE(rc))
520	return rc;
521
522	pgmLock(pVM);
523	iPrevPage = iPage;
524	}
525	/*
526	* In the final pass, make sure the protection is in sync.
527	*/
528	else if ( fFinalPass
529	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
530	{
531	PGMROMPROT enmProt = pRomPage->enmProt;
532	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
533	pgmUnlock(pVM);
534
535	if (iPage - 1U == iPrevPage && iPage > 0)
536	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
537	else
538	{
539	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
540	SSMR3PutU8(pSSM, pRom->idSavedState);
541	SSMR3PutU32(pSSM, iPage);
542	}
543	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
544	if (RT_FAILURE(rc))
545	return rc;
546
547	pgmLock(pVM);
548	iPrevPage = iPage;
549	}
550	}
551	}
552	}
553	pgmUnlock(pVM);
554	return VINF_SUCCESS;
555	}
556
557
558	/**
559	* Cleans up ROM pages after a live save.
560	*
561	* @param pVM The VM handle.
562	*/
563	static void pgmR3DoneRomPages(PVM pVM)
564	{
565	NOREF(pVM);
566	}
567
568
569	/**
570	* Prepares the MMIO2 pages for a live save.
571	*
572	* @returns VBox status code.
573	* @param pVM The VM handle.
574	*/
575	static int pgmR3PrepMmio2Pages(PVM pVM)
576	{
577	/*
578	* Initialize the live save tracking in the MMIO2 ranges.
579	* ASSUME nothing changes here.
580	*/
581	pgmLock(pVM);
582	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
583	{
584	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
585	pgmUnlock(pVM);
586
587	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
588	if (!paLSPages)
589	return VERR_NO_MEMORY;
590	for (uint32_t iPage = 0; iPage < cPages; iPage++)
591	{
592	/* Initialize it as a dirty zero page. */
593	paLSPages[iPage].fDirty = true;
594	paLSPages[iPage].cUnchangedScans = 0;
595	paLSPages[iPage].fZero = true;
596	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
597	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
598	}
599
600	pgmLock(pVM);
601	pMmio2->paLSPages = paLSPages;
602	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
603	}
604	pgmUnlock(pVM);
605	return VINF_SUCCESS;
606	}
607
608
609	/**
610	* Assigns IDs to the MMIO2 ranges and saves them.
611	*
612	* @returns VBox status code.
613	* @param pVM The VM handle.
614	* @param pSSM Saved state handle.
615	*/
616	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
617	{
618	pgmLock(pVM);
619	uint8_t id = 1;
620	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
621	{
622	pMmio2->idSavedState = id;
623	SSMR3PutU8(pSSM, id);
624	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pDevReg->szDeviceName);
625	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
626	SSMR3PutU8(pSSM, pMmio2->iRegion);
627	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
628	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
629	if (RT_FAILURE(rc))
630	break;
631	}
632	pgmUnlock(pVM);
633	return SSMR3PutU8(pSSM, UINT8_MAX);
634	}
635
636
637	/**
638	* Loads the MMIO2 range ID assignments.
639	*
640	* @returns VBox status code.
641	*
642	* @param pVM The VM handle.
643	* @param pSSM The saved state handle.
644	*/
645	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
646	{
647	Assert(PGMIsLockOwner(pVM));
648
649	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
650	pMmio2->idSavedState = UINT8_MAX;
651
652	for (;;)
653	{
654	/*
655	* Read the data.
656	*/
657	uint8_t id;
658	int rc = SSMR3GetU8(pSSM, &id);
659	if (RT_FAILURE(rc))
660	return rc;
661	if (id == UINT8_MAX)
662	{
663	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
664	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
665	return VINF_SUCCESS; /* the end */
666	}
667	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
668
669	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szDeviceName)];
670	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
671	AssertLogRelRCReturn(rc, rc);
672
673	uint32_t uInstance;
674	SSMR3GetU32(pSSM, &uInstance);
675	uint8_t iRegion;
676	SSMR3GetU8(pSSM, &iRegion);
677
678	char szDesc[64];
679	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
680	AssertLogRelRCReturn(rc, rc);
681
682	RTGCPHYS cb;
683	rc = SSMR3GetGCPhys(pSSM, &cb);
684	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
685
686	/*
687	* Locate a matching MMIO2 range.
688	*/
689	PPGMMMIO2RANGE pMmio2;
690	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
691	{
692	if ( pMmio2->idSavedState == UINT8_MAX
693	&& pMmio2->iRegion == iRegion
694	&& pMmio2->pDevInsR3->iInstance == uInstance
695	&& !strcmp(pMmio2->pDevInsR3->pDevReg->szDeviceName, szDevName))
696	{
697	pMmio2->idSavedState = id;
698	break;
699	}
700	}
701	if (!pMmio2)
702	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
703	szDesc, szDevName, uInstance, iRegion);
704
705	/*
706	* Validate the configuration, the size of the MMIO2 region should be
707	* the same.
708	*/
709	if (cb != pMmio2->RamRange.cb)
710	{
711	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
712	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
713	if (cb > pMmio2->RamRange.cb) /* bad idea? */
714	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
715	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
716	}
717	} /* forever */
718	}
719
720
721	/**
722	* Scans one MMIO2 page.
723	*
724	* @returns True if changed, false if unchanged.
725	*
726	* @param pVM The VM handle
727	* @param pbPage The page bits.
728	* @param pLSPage The live save tracking structure for the page.
729	*
730	*/
731	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
732	{
733	/*
734	* Special handling of zero pages.
735	*/
736	bool const fZero = pLSPage->fZero;
737	if (fZero)
738	{
739	if (ASMMemIsZeroPage(pbPage))
740	{
741	/* Not modified. */
742	if (pLSPage->fDirty)
743	pLSPage->cUnchangedScans++;
744	return false;
745	}
746
747	pLSPage->fZero = false;
748	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
749	}
750	else
751	{
752	/*
753	* CRC the first half, if it doesn't match the page is dirty and
754	* we won't check the 2nd half (we'll do that next time).
755	*/
756	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
757	if (u32CrcH1 == pLSPage->u32CrcH1)
758	{
759	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
760	if (u32CrcH2 == pLSPage->u32CrcH2)
761	{
762	/* Probably not modified. */
763	if (pLSPage->fDirty)
764	pLSPage->cUnchangedScans++;
765	return false;
766	}
767
768	pLSPage->u32CrcH2 = u32CrcH2;
769	}
770	else
771	{
772	pLSPage->u32CrcH1 = u32CrcH1;
773	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
774	&& ASMMemIsZeroPage(pbPage))
775	{
776	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
777	pLSPage->fZero = true;
778	}
779	}
780	}
781
782	/* dirty page path */
783	pLSPage->cUnchangedScans = 0;
784	if (!pLSPage->fDirty)
785	{
786	pLSPage->fDirty = true;
787	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
788	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
789	if (fZero)
790	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
791	}
792	return true;
793	}
794
795
796	/**
797	* Scan for MMIO2 page modifications.
798	*
799	* @param pVM The VM handle.
800	* @param uPass The pass number.
801	*/
802	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
803	{
804	/*
805	* Since this is a bit expensive we lower the scan rate after a little while.
806	*/
807	if ( ( (uPass & 3) != 0
808	&& uPass > 10)
809	\|\| uPass == SSM_PASS_FINAL)
810	return;
811
812	pgmLock(pVM); /* paranoia */
813	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
814	{
815	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
816	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
817	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
818	pgmUnlock(pVM);
819
820	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
821	{
822	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
823	pgmR3ScanMmio2Page(pVM,pbPage, &paLSPages[iPage]);
824	}
825
826	pgmLock(pVM);
827	}
828	pgmUnlock(pVM);
829
830	}
831
832
833	/**
834	* Save quiescent MMIO2 pages.
835	*
836	* @returns VBox status code.
837	* @param pVM The VM handle.
838	* @param pSSM The SSM handle.
839	* @param fLiveSave Whether it's a live save or not.
840	* @param uPass The pass number.
841	*/
842	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
843	{
844	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
845	* device that we wish to know about changes.) */
846
847	int rc = VINF_SUCCESS;
848	if (uPass == SSM_PASS_FINAL)
849	{
850	/*
851	* The mop up round.
852	*/
853	pgmLock(pVM);
854	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
855	pMmio2 && RT_SUCCESS(rc);
856	pMmio2 = pMmio2->pNextR3)
857	{
858	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
859	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
860	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
861	uint32_t iPageLast = cPages;
862	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
863	{
864	uint8_t u8Type;
865	if (!fLiveSave)
866	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
867	else
868	{
869	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
870	if ( !paLSPages[iPage].fDirty
871	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
872	{
873	if (paLSPages[iPage].fZero)
874	continue;
875
876	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
877	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
878	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
879	continue;
880	}
881	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
882	}
883
884	if (iPage != 0 && iPage == iPageLast + 1)
885	rc = SSMR3PutU8(pSSM, u8Type);
886	else
887	{
888	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
889	SSMR3PutU8(pSSM, pMmio2->idSavedState);
890	rc = SSMR3PutU32(pSSM, iPage);
891	}
892	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
893	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
894	if (RT_FAILURE(rc))
895	break;
896	iPageLast = iPage;
897	}
898	}
899	pgmUnlock(pVM);
900	}
901	/*
902	* Reduce the rate after a little while since the current MMIO2 approach is
903	* a bit expensive.
904	* We position it two passes after the scan pass to avoid saving busy pages.
905	*/
906	else if ( uPass <= 10
907	\|\| (uPass & 3) == 2)
908	{
909	pgmLock(pVM);
910	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
911	pMmio2 && RT_SUCCESS(rc);
912	pMmio2 = pMmio2->pNextR3)
913	{
914	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
915	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
916	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
917	uint32_t iPageLast = cPages;
918	pgmUnlock(pVM);
919
920	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
921	{
922	/* Skip clean pages and pages which hasn't quiesced. */
923	if (!paLSPages[iPage].fDirty)
924	continue;
925	if (paLSPages[iPage].cUnchangedScans < 3)
926	continue;
927	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
928	continue;
929
930	/* Save it. */
931	bool const fZero = paLSPages[iPage].fZero;
932	uint8_t abPage[PAGE_SIZE];
933	if (!fZero)
934	{
935	memcpy(abPage, pbPage, PAGE_SIZE);
936	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
937	}
938
939	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
940	if (iPage != 0 && iPage == iPageLast + 1)
941	rc = SSMR3PutU8(pSSM, u8Type);
942	else
943	{
944	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
945	SSMR3PutU8(pSSM, pMmio2->idSavedState);
946	rc = SSMR3PutU32(pSSM, iPage);
947	}
948	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
949	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
950	if (RT_FAILURE(rc))
951	break;
952
953	/* Housekeeping. */
954	paLSPages[iPage].fDirty = false;
955	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
956	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
957	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
958	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
959	iPageLast = iPage;
960	}
961
962	pgmLock(pVM);
963	}
964	pgmUnlock(pVM);
965	}
966
967	return rc;
968	}
969
970
971	/**
972	* Cleans up MMIO2 pages after a live save.
973	*
974	* @param pVM The VM handle.
975	*/
976	static void pgmR3DoneMmio2Pages(PVM pVM)
977	{
978	/*
979	* Free the tracking structures for the MMIO2 pages.
980	* We do the freeing outside the lock in case the VM is running.
981	*/
982	pgmLock(pVM);
983	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
984	{
985	void *pvMmio2ToFree = pMmio2->paLSPages;
986	if (pvMmio2ToFree)
987	{
988	pMmio2->paLSPages = NULL;
989	pgmUnlock(pVM);
990	MMR3HeapFree(pvMmio2ToFree);
991	pgmLock(pVM);
992	}
993	}
994	pgmUnlock(pVM);
995	}
996
997
998	/**
999	* Prepares the RAM pages for a live save.
1000	*
1001	* @returns VBox status code.
1002	* @param pVM The VM handle.
1003	*/
1004	static int pgmR3PrepRamPages(PVM pVM)
1005	{
1006
1007	/*
1008	* Try allocating tracking structures for the ram ranges.
1009	*
1010	* To avoid lock contention, we leave the lock every time we're allocating
1011	* a new array. This means we'll have to ditch the allocation and start
1012	* all over again if the RAM range list changes in-between.
1013	*
1014	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1015	* for cleaning up.
1016	*/
1017	PPGMRAMRANGE pCur;
1018	pgmLock(pVM);
1019	do
1020	{
1021	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1022	{
1023	if ( !pCur->paLSPages
1024	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1025	{
1026	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1027	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1028	pgmUnlock(pVM);
1029	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1030	if (!paLSPages)
1031	return VERR_NO_MEMORY;
1032	pgmLock(pVM);
1033	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1034	{
1035	pgmUnlock(pVM);
1036	MMR3HeapFree(paLSPages);
1037	pgmLock(pVM);
1038	break; /* try again */
1039	}
1040	pCur->paLSPages = paLSPages;
1041
1042	/*
1043	* Initialize the array.
1044	*/
1045	uint32_t iPage = cPages;
1046	while (iPage-- > 0)
1047	{
1048	/** @todo yield critsect! (after moving this away from EMT0) */
1049	PCPGMPAGE pPage = &pCur->aPages[iPage];
1050	paLSPages[iPage].cDirtied = 0;
1051	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1052	paLSPages[iPage].fWriteMonitored = 0;
1053	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1054	paLSPages[iPage].u2Reserved = 0;
1055	switch (PGM_PAGE_GET_TYPE(pPage))
1056	{
1057	case PGMPAGETYPE_RAM:
1058	if (PGM_PAGE_IS_ZERO(pPage))
1059	{
1060	paLSPages[iPage].fZero = 1;
1061	paLSPages[iPage].fShared = 0;
1062	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1063	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1064	#endif
1065	}
1066	else if (PGM_PAGE_IS_SHARED(pPage))
1067	{
1068	paLSPages[iPage].fZero = 0;
1069	paLSPages[iPage].fShared = 1;
1070	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1071	paLSPages[iPage].u32Crc = UINT32_MAX;
1072	#endif
1073	}
1074	else
1075	{
1076	paLSPages[iPage].fZero = 0;
1077	paLSPages[iPage].fShared = 0;
1078	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1079	paLSPages[iPage].u32Crc = UINT32_MAX;
1080	#endif
1081	}
1082	paLSPages[iPage].fIgnore = 0;
1083	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1084	break;
1085
1086	case PGMPAGETYPE_ROM_SHADOW:
1087	case PGMPAGETYPE_ROM:
1088	{
1089	paLSPages[iPage].fZero = 0;
1090	paLSPages[iPage].fShared = 0;
1091	paLSPages[iPage].fDirty = 0;
1092	paLSPages[iPage].fIgnore = 1;
1093	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1094	paLSPages[iPage].u32Crc = UINT32_MAX;
1095	#endif
1096	pVM->pgm.s.LiveSave.cIgnoredPages++;
1097	break;
1098	}
1099
1100	default:
1101	AssertMsgFailed(("%R[pgmpage]", pPage));
1102	case PGMPAGETYPE_MMIO2:
1103	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1104	paLSPages[iPage].fZero = 0;
1105	paLSPages[iPage].fShared = 0;
1106	paLSPages[iPage].fDirty = 0;
1107	paLSPages[iPage].fIgnore = 1;
1108	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1109	paLSPages[iPage].u32Crc = UINT32_MAX;
1110	#endif
1111	pVM->pgm.s.LiveSave.cIgnoredPages++;
1112	break;
1113
1114	case PGMPAGETYPE_MMIO:
1115	paLSPages[iPage].fZero = 0;
1116	paLSPages[iPage].fShared = 0;
1117	paLSPages[iPage].fDirty = 0;
1118	paLSPages[iPage].fIgnore = 1;
1119	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1120	paLSPages[iPage].u32Crc = UINT32_MAX;
1121	#endif
1122	pVM->pgm.s.LiveSave.cIgnoredPages++;
1123	break;
1124	}
1125	}
1126	}
1127	}
1128	} while (pCur);
1129	pgmUnlock(pVM);
1130
1131	return VINF_SUCCESS;
1132	}
1133
1134
1135	/**
1136	* Saves the RAM configuration.
1137	*
1138	* @returns VBox status code.
1139	* @param pVM The VM handle.
1140	* @param pSSM The saved state handle.
1141	*/
1142	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1143	{
1144	uint32_t cbRamHole = 0;
1145	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1146	AssertRCReturn(rc, rc);
1147
1148	uint64_t cbRam = 0;
1149	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1150	AssertRCReturn(rc, rc);
1151
1152	SSMR3PutU32(pSSM, cbRamHole);
1153	return SSMR3PutU64(pSSM, cbRam);
1154	}
1155
1156
1157	/**
1158	* Loads and verifies the RAM configuration.
1159	*
1160	* @returns VBox status code.
1161	* @param pVM The VM handle.
1162	* @param pSSM The saved state handle.
1163	*/
1164	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1165	{
1166	uint32_t cbRamHoleCfg = 0;
1167	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1168	AssertRCReturn(rc, rc);
1169
1170	uint64_t cbRamCfg = 0;
1171	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1172	AssertRCReturn(rc, rc);
1173
1174	uint32_t cbRamHoleSaved;
1175	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1176
1177	uint64_t cbRamSaved;
1178	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1179	AssertRCReturn(rc, rc);
1180
1181	if ( cbRamHoleCfg != cbRamHoleSaved
1182	\|\| cbRamCfg != cbRamSaved)
1183	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1184	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1185	return VINF_SUCCESS;
1186	}
1187
1188	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1189
1190	/**
1191	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1192	* info with it.
1193	*
1194	* @param pVM The VM handle.
1195	* @param pCur The current RAM range.
1196	* @param paLSPages The current array of live save page tracking
1197	* structures.
1198	* @param iPage The page index.
1199	*/
1200	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1201	{
1202	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1203	void const *pvPage;
1204	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1205	if (RT_SUCCESS(rc))
1206	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1207	else
1208	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1209	}
1210
1211
1212	/**
1213	* Verifies the CRC-32 for a page given it's raw bits.
1214	*
1215	* @param pvPage The page bits.
1216	* @param pCur The current RAM range.
1217	* @param paLSPages The current array of live save page tracking
1218	* structures.
1219	* @param iPage The page index.
1220	*/
1221	static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1222	{
1223	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1224	{
1225	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1226	Assert(!PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) \|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1227	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1228	("%08x != %08x for %RGp %R[pgmpage]\n", paLSPages[iPage].u32Crc, u32Crc,
1229	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1230	}
1231	}
1232
1233
1234	/**
1235	* Verfies the CRC-32 for a RAM page.
1236	*
1237	* @param pVM The VM handle.
1238	* @param pCur The current RAM range.
1239	* @param paLSPages The current array of live save page tracking
1240	* structures.
1241	* @param iPage The page index.
1242	*/
1243	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1244	{
1245	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1246	{
1247	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1248	void const *pvPage;
1249	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1250	if (RT_SUCCESS(rc))
1251	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage);
1252	}
1253	}
1254
1255	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1256
1257	/**
1258	* Scan for RAM page modifications and reprotect them.
1259	*
1260	* @param pVM The VM handle.
1261	* @param fFinalPass Whether this is the final pass or not.
1262	*/
1263	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1264	{
1265	/*
1266	* The RAM.
1267	*/
1268	RTGCPHYS GCPhysCur = 0;
1269	PPGMRAMRANGE pCur;
1270	pgmLock(pVM);
1271	do
1272	{
1273	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1274	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1275	{
1276	if ( pCur->GCPhysLast > GCPhysCur
1277	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1278	{
1279	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1280	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1281	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1282	GCPhysCur = 0;
1283	for (; iPage < cPages; iPage++)
1284	{
1285	/* Do yield first. */
1286	if ( !fFinalPass
1287	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1288	&& (iPage & 0x7ff) == 0x100
1289	#endif
1290	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1291	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1292	{
1293	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1294	break; /* restart */
1295	}
1296
1297	/* Skip already ignored pages. */
1298	if (paLSPages[iPage].fIgnore)
1299	continue;
1300
1301	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1302	{
1303	/*
1304	* A RAM page.
1305	*/
1306	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1307	{
1308	case PGM_PAGE_STATE_ALLOCATED:
1309	/** @todo Optimize this: Don't always re-enable write
1310	* monitoring if the page is known to be very busy. */
1311	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1312	{
1313	Assert(paLSPages[iPage].fWriteMonitored);
1314	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1315	Assert(pVM->pgm.s.cWrittenToPages > 0);
1316	pVM->pgm.s.cWrittenToPages--;
1317	}
1318	else
1319	{
1320	Assert(!paLSPages[iPage].fWriteMonitored);
1321	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1322	}
1323
1324	if (!paLSPages[iPage].fDirty)
1325	{
1326	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1327	if (paLSPages[iPage].fZero)
1328	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1329	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1330	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1331	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1332	}
1333
1334	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1335	pVM->pgm.s.cMonitoredPages++;
1336	paLSPages[iPage].fWriteMonitored = 1;
1337	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1338	paLSPages[iPage].fDirty = 1;
1339	paLSPages[iPage].fZero = 0;
1340	paLSPages[iPage].fShared = 0;
1341	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1342	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1343	#endif
1344	break;
1345
1346	case PGM_PAGE_STATE_WRITE_MONITORED:
1347	Assert(paLSPages[iPage].fWriteMonitored);
1348	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1349	{
1350	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1351	if (paLSPages[iPage].fWriteMonitoredJustNow)
1352	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1353	else
1354	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1355	#endif
1356	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1357	}
1358	else
1359	{
1360	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1361	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1362	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1363	#endif
1364	if (!paLSPages[iPage].fDirty)
1365	{
1366	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1367	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1368	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1369	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1370	}
1371	}
1372	break;
1373
1374	case PGM_PAGE_STATE_ZERO:
1375	if (!paLSPages[iPage].fZero)
1376	{
1377	if (!paLSPages[iPage].fDirty)
1378	{
1379	paLSPages[iPage].fDirty = 1;
1380	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1381	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1382	}
1383	paLSPages[iPage].fZero = 1;
1384	paLSPages[iPage].fShared = 0;
1385	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1386	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1387	#endif
1388	}
1389	break;
1390
1391	case PGM_PAGE_STATE_SHARED:
1392	if (!paLSPages[iPage].fShared)
1393	{
1394	if (!paLSPages[iPage].fDirty)
1395	{
1396	paLSPages[iPage].fDirty = 1;
1397	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1398	if (paLSPages[iPage].fZero)
1399	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1400	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1401	}
1402	paLSPages[iPage].fZero = 0;
1403	paLSPages[iPage].fShared = 1;
1404	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1405	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1406	#endif
1407	}
1408	break;
1409	}
1410	}
1411	else
1412	{
1413	/*
1414	* All other types => Ignore the page.
1415	*/
1416	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1417	paLSPages[iPage].fIgnore = 1;
1418	if (paLSPages[iPage].fWriteMonitored)
1419	{
1420	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1421	* pages! */
1422	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1423	{
1424	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1425	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1426	Assert(pVM->pgm.s.cMonitoredPages > 0);
1427	pVM->pgm.s.cMonitoredPages--;
1428	}
1429	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1430	{
1431	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1432	Assert(pVM->pgm.s.cWrittenToPages > 0);
1433	pVM->pgm.s.cWrittenToPages--;
1434	}
1435	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1436	}
1437
1438	/** @todo the counting doesn't quite work out here. fix later? */
1439	if (paLSPages[iPage].fDirty)
1440	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1441	else
1442	{
1443	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1444	if (paLSPages[iPage].fZero)
1445	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1446	}
1447	pVM->pgm.s.LiveSave.cIgnoredPages++;
1448	}
1449	} /* for each page in range */
1450
1451	if (GCPhysCur != 0)
1452	break; /* Yield + ramrange change */
1453	GCPhysCur = pCur->GCPhysLast;
1454	}
1455	} /* for each range */
1456	} while (pCur);
1457	pgmUnlock(pVM);
1458	}
1459
1460
1461	/**
1462	* Save quiescent RAM pages.
1463	*
1464	* @returns VBox status code.
1465	* @param pVM The VM handle.
1466	* @param pSSM The SSM handle.
1467	* @param fLiveSave Whether it's a live save or not.
1468	* @param uPass The pass number.
1469	*/
1470	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1471	{
1472	/*
1473	* The RAM.
1474	*/
1475	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1476	RTGCPHYS GCPhysCur = 0;
1477	PPGMRAMRANGE pCur;
1478	pgmLock(pVM);
1479	do
1480	{
1481	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1482	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1483	{
1484	if ( pCur->GCPhysLast > GCPhysCur
1485	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1486	{
1487	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1488	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1489	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1490	GCPhysCur = 0;
1491	for (; iPage < cPages; iPage++)
1492	{
1493	/* Do yield first. */
1494	if ( uPass != SSM_PASS_FINAL
1495	&& (iPage & 0x7ff) == 0x100
1496	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1497	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1498	{
1499	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1500	break; /* restart */
1501	}
1502
1503	/*
1504	* Only save pages that hasn't changed since last scan and are dirty.
1505	*/
1506	if ( uPass != SSM_PASS_FINAL
1507	&& paLSPages)
1508	{
1509	if (!paLSPages[iPage].fDirty)
1510	continue;
1511	if (paLSPages[iPage].fWriteMonitoredJustNow)
1512	continue;
1513	if (paLSPages[iPage].fIgnore)
1514	continue;
1515	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM) /* in case of recent ramppings */
1516	continue;
1517	if ( PGM_PAGE_GET_STATE(&pCur->aPages[iPage])
1518	!= ( paLSPages[iPage].fZero
1519	? PGM_PAGE_STATE_ZERO
1520	: paLSPages[iPage].fShared
1521	? PGM_PAGE_STATE_SHARED
1522	: PGM_PAGE_STATE_WRITE_MONITORED))
1523	continue;
1524	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1525	continue;
1526	}
1527	else
1528	{
1529	if ( paLSPages
1530	&& !paLSPages[iPage].fDirty
1531	&& !paLSPages[iPage].fIgnore)
1532	{
1533	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1534	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1535	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1536	#endif
1537	continue;
1538	}
1539	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1540	continue;
1541	}
1542
1543	/*
1544	* Do the saving outside the PGM critsect since SSM may block on I/O.
1545	*/
1546	int rc;
1547	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1548	bool fZero = PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]);
1549
1550	if (!fZero)
1551	{
1552	/*
1553	* Copy the page and then save it outside the lock (since any
1554	* SSM call may block).
1555	*/
1556	uint8_t abPage[PAGE_SIZE];
1557	void const *pvPage;
1558	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1559	if (RT_SUCCESS(rc))
1560	{
1561	memcpy(abPage, pvPage, PAGE_SIZE);
1562	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1563	if (paLSPages)
1564	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage);
1565	#endif
1566	}
1567	pgmUnlock(pVM);
1568	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1569
1570	if (GCPhys == GCPhysLast + PAGE_SIZE)
1571	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1572	else
1573	{
1574	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1575	SSMR3PutGCPhys(pSSM, GCPhys);
1576	}
1577	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1578	}
1579	else
1580	{
1581	/*
1582	* Dirty zero page.
1583	*/
1584	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1585	if (paLSPages)
1586	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1587	#endif
1588	pgmUnlock(pVM);
1589
1590	if (GCPhys == GCPhysLast + PAGE_SIZE)
1591	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1592	else
1593	{
1594	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1595	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1596	}
1597	}
1598	if (RT_FAILURE(rc))
1599	return rc;
1600
1601	pgmLock(pVM);
1602	GCPhysLast = GCPhys;
1603	if (paLSPages)
1604	{
1605	paLSPages[iPage].fDirty = 0;
1606	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1607	if (fZero)
1608	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1609	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1610	}
1611	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1612	{
1613	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1614	break; /* restart */
1615	}
1616
1617	} /* for each page in range */
1618
1619	if (GCPhysCur != 0)
1620	break; /* Yield + ramrange change */
1621	GCPhysCur = pCur->GCPhysLast;
1622	}
1623	} /* for each range */
1624	} while (pCur);
1625	pgmUnlock(pVM);
1626
1627	return VINF_SUCCESS;
1628	}
1629
1630
1631	/**
1632	* Cleans up RAM pages after a live save.
1633	*
1634	* @param pVM The VM handle.
1635	*/
1636	static void pgmR3DoneRamPages(PVM pVM)
1637	{
1638	/*
1639	* Free the tracking arrays and disable write monitoring.
1640	*
1641	* Play nice with the PGM lock in case we're called while the VM is still
1642	* running. This means we have to delay the freeing since we wish to use
1643	* paLSPages as an indicator of which RAM ranges which we need to scan for
1644	* write monitored pages.
1645	*/
1646	void *pvToFree = NULL;
1647	PPGMRAMRANGE pCur;
1648	uint32_t cMonitoredPages = 0;
1649	pgmLock(pVM);
1650	do
1651	{
1652	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1653	{
1654	if (pCur->paLSPages)
1655	{
1656	if (pvToFree)
1657	{
1658	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1659	pgmUnlock(pVM);
1660	MMR3HeapFree(pvToFree);
1661	pvToFree = NULL;
1662	pgmLock(pVM);
1663	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1664	break; /* start over again. */
1665	}
1666
1667	pvToFree = pCur->paLSPages;
1668	pCur->paLSPages = NULL;
1669
1670	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1671	while (iPage--)
1672	{
1673	PPGMPAGE pPage = &pCur->aPages[iPage];
1674	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1675	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1676	{
1677	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1678	cMonitoredPages++;
1679	}
1680	}
1681	}
1682	}
1683	} while (pCur);
1684
1685	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1686	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1687	pVM->pgm.s.cMonitoredPages = 0;
1688	else
1689	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1690
1691	pgmUnlock(pVM);
1692
1693	MMR3HeapFree(pvToFree);
1694	pvToFree = NULL;
1695	}
1696
1697
1698	/**
1699	* Execute a live save pass.
1700	*
1701	* @returns VBox status code.
1702	*
1703	* @param pVM The VM handle.
1704	* @param pSSM The SSM handle.
1705	*/
1706	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1707	{
1708	int rc;
1709
1710	/*
1711	* Save the MMIO2 and ROM range IDs in pass 0.
1712	*/
1713	if (uPass == 0)
1714	{
1715	rc = pgmR3SaveRamConfig(pVM, pSSM);
1716	if (RT_FAILURE(rc))
1717	return rc;
1718	rc = pgmR3SaveRomRanges(pVM, pSSM);
1719	if (RT_FAILURE(rc))
1720	return rc;
1721	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1722	if (RT_FAILURE(rc))
1723	return rc;
1724	}
1725
1726	/*
1727	* Do the scanning.
1728	*/
1729	pgmR3ScanRomPages(pVM);
1730	pgmR3ScanMmio2Pages(pVM, uPass);
1731	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1732	pgmR3PoolClearAll(pVM); /** @todo this could perhaps be optimized a bit. */
1733
1734	/*
1735	* Save the pages.
1736	*/
1737	if (uPass == 0)
1738	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1739	else
1740	rc = VINF_SUCCESS;
1741	if (RT_SUCCESS(rc))
1742	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1743	if (RT_SUCCESS(rc))
1744	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1745	if (RT_SUCCESS(rc))
1746	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1747	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1748
1749	return rc;
1750	}
1751
1752
1753	/**
1754	* Votes on whether the live save phase is done or not.
1755	*
1756	* @returns VBox status code.
1757	*
1758	* @param pVM The VM handle.
1759	* @param pSSM The SSM handle.
1760	* @param uPass The data pass.
1761	*/
1762	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1763	{
1764	/*
1765	* Update and calculate parameters used in the decision making.
1766	*/
1767	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1768
1769	/* update history. */
1770	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1771	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1772	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1773	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages;
1774	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1775
1776	/* calc shortterm average (4 passes). */
1777	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1778	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1779	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1780	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1781	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1782	uint32_t const cDirtyPagesShort = cTotal / 4;
1783	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1784
1785	/* calc longterm average. */
1786	cTotal = 0;
1787	if (uPass < cHistoryEntries)
1788	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1789	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1790	else
1791	for (i = 0; i < cHistoryEntries; i++)
1792	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1793	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1794	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1795
1796	/*
1797	* Try make a decision.
1798	*/
1799	/** @todo take the count dirtied write-monitored page into account here. */
1800	if (cDirtyPagesShort <= cDirtyPagesLong)
1801	{
1802	if ( cDirtyPagesShort <= 128
1803	&& cDirtyPagesLong <= 1024)
1804	return VINF_SUCCESS;
1805	if (cDirtyPagesLong <= 256)
1806	return VINF_SUCCESS;
1807	/* !! hack !! */
1808	if ( cDirtyPagesShort <= 512
1809	&& cDirtyPagesLong <= 640
1810	&& uPass >= 1024)
1811	return VINF_SUCCESS;
1812	if ( cDirtyPagesShort <= 896
1813	&& cDirtyPagesLong <= 1024
1814	&& uPass >= 2048)
1815	return VINF_SUCCESS;
1816	if ( cDirtyPagesShort <= 1512
1817	&& cDirtyPagesLong <= 1536
1818	&& uPass >= 4096)
1819	return VINF_SUCCESS;
1820	if ( cDirtyPagesLong <= 4096
1821	&& uPass >= 8192)
1822	return VINF_SUCCESS;
1823	}
1824	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1825	}
1826
1827
1828	/**
1829	* Prepare for a live save operation.
1830	*
1831	* This will attempt to allocate and initialize the tracking structures. It
1832	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1833	* pgmR3SaveDone will do the cleanups.
1834	*
1835	* @returns VBox status code.
1836	*
1837	* @param pVM The VM handle.
1838	* @param pSSM The SSM handle.
1839	*/
1840	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1841	{
1842	/*
1843	* Indicate that we will be using the write monitoring.
1844	*/
1845	pgmLock(pVM);
1846	/** @todo find a way of mediating this when more users are added. */
1847	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1848	{
1849	pgmUnlock(pVM);
1850	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1851	}
1852	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1853	pgmUnlock(pVM);
1854
1855	/*
1856	* Initialize the statistics.
1857	*/
1858	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1859	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1860	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1861	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1862	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1863	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1864	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1865	pVM->pgm.s.LiveSave.fActive = true;
1866	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
1867	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
1868	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
1869
1870	/*
1871	* Per page type.
1872	*/
1873	int rc = pgmR3PrepRomPages(pVM);
1874	if (RT_SUCCESS(rc))
1875	rc = pgmR3PrepMmio2Pages(pVM);
1876	if (RT_SUCCESS(rc))
1877	rc = pgmR3PrepRamPages(pVM);
1878	return rc;
1879	}
1880
1881
1882	/**
1883	* Execute state save operation.
1884	*
1885	* @returns VBox status code.
1886	* @param pVM VM Handle.
1887	* @param pSSM SSM operation handle.
1888	*/
1889	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1890	{
1891	int rc;
1892	unsigned i;
1893	PPGM pPGM = &pVM->pgm.s;
1894
1895	/*
1896	* Lock PGM and set the no-more-writes indicator.
1897	*/
1898	pgmLock(pVM);
1899	pVM->pgm.s.fNoMorePhysWrites = true;
1900
1901	/*
1902	* Save basic data (required / unaffected by relocation).
1903	*/
1904	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
1905
1906	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1907	{
1908	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1909	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
1910	}
1911
1912	/*
1913	* The guest mappings.
1914	*/
1915	i = 0;
1916	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1917	{
1918	SSMR3PutU32( pSSM, i);
1919	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1920	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
1921	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1922	}
1923	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1924
1925	/*
1926	* Save the (remainder of the) memory.
1927	*/
1928	if (RT_SUCCESS(rc))
1929	{
1930	if (pVM->pgm.s.LiveSave.fActive)
1931	{
1932	pgmR3ScanRomPages(pVM);
1933	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
1934	pgmR3ScanRamPages(pVM, true /fFinalPass/);
1935
1936	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
1937	if (RT_SUCCESS(rc))
1938	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1939	if (RT_SUCCESS(rc))
1940	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1941	}
1942	else
1943	{
1944	rc = pgmR3SaveRamConfig(pVM, pSSM);
1945	if (RT_SUCCESS(rc))
1946	rc = pgmR3SaveRomRanges(pVM, pSSM);
1947	if (RT_SUCCESS(rc))
1948	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1949	if (RT_SUCCESS(rc))
1950	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
1951	if (RT_SUCCESS(rc))
1952	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
1953	if (RT_SUCCESS(rc))
1954	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
1955	if (RT_SUCCESS(rc))
1956	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
1957	}
1958	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1959	}
1960
1961	pgmUnlock(pVM);
1962	return rc;
1963	}
1964
1965
1966	/**
1967	* Cleans up after an save state operation.
1968	*
1969	* @returns VBox status code.
1970	* @param pVM VM Handle.
1971	* @param pSSM SSM operation handle.
1972	*/
1973	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
1974	{
1975	/*
1976	* Do per page type cleanups first.
1977	*/
1978	if (pVM->pgm.s.LiveSave.fActive)
1979	{
1980	pgmR3DoneRomPages(pVM);
1981	pgmR3DoneMmio2Pages(pVM);
1982	pgmR3DoneRamPages(pVM);
1983	}
1984
1985	/*
1986	* Clear the live save indicator and disengage write monitoring.
1987	*/
1988	pgmLock(pVM);
1989	pVM->pgm.s.LiveSave.fActive = false;
1990	/** @todo this is blindly assuming that we're the only user of write
1991	* monitoring. Fix this when more users are added. */
1992	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
1993	pgmUnlock(pVM);
1994
1995	return VINF_SUCCESS;
1996	}
1997
1998
1999	/**
2000	* Prepare state load operation.
2001	*
2002	* @returns VBox status code.
2003	* @param pVM VM Handle.
2004	* @param pSSM SSM operation handle.
2005	*/
2006	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2007	{
2008	/*
2009	* Call the reset function to make sure all the memory is cleared.
2010	*/
2011	PGMR3Reset(pVM);
2012	pVM->pgm.s.LiveSave.fActive = false;
2013	NOREF(pSSM);
2014	return VINF_SUCCESS;
2015	}
2016
2017
2018	/**
2019	* Load an ignored page.
2020	*
2021	* @returns VBox status code.
2022	* @param pSSM The saved state handle.
2023	*/
2024	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2025	{
2026	uint8_t abPage[PAGE_SIZE];
2027	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2028	}
2029
2030
2031	/**
2032	* Loads a page without any bits in the saved state, i.e. making sure it's
2033	* really zero.
2034	*
2035	* @returns VBox status code.
2036	* @param pVM The VM handle.
2037	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2038	* state).
2039	* @param pPage The guest page tracking structure.
2040	* @param GCPhys The page address.
2041	* @param pRam The ram range (logging).
2042	*/
2043	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2044	{
2045	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2046	&& uType != PGMPAGETYPE_INVALID)
2047	return VERR_SSM_UNEXPECTED_DATA;
2048
2049	/* I think this should be sufficient. */
2050	if (!PGM_PAGE_IS_ZERO(pPage))
2051	return VERR_SSM_UNEXPECTED_DATA;
2052
2053	NOREF(pVM);
2054	NOREF(GCPhys);
2055	NOREF(pRam);
2056	return VINF_SUCCESS;
2057	}
2058
2059
2060	/**
2061	* Loads a page from the saved state.
2062	*
2063	* @returns VBox status code.
2064	* @param pVM The VM handle.
2065	* @param pSSM The SSM handle.
2066	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2067	* state).
2068	* @param pPage The guest page tracking structure.
2069	* @param GCPhys The page address.
2070	* @param pRam The ram range (logging).
2071	*/
2072	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2073	{
2074	/*
2075	* Match up the type, dealing with MMIO2 aliases (dropped).
2076	*/
2077	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2078	\|\| uType == PGMPAGETYPE_INVALID,
2079	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2080	VERR_SSM_UNEXPECTED_DATA);
2081
2082	/*
2083	* Load the page.
2084	*/
2085	void *pvPage;
2086	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2087	if (RT_SUCCESS(rc))
2088	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2089
2090	return rc;
2091	}
2092
2093
2094	/**
2095	* Loads a page (counter part to pgmR3SavePage).
2096	*
2097	* @returns VBox status code, fully bitched errors.
2098	* @param pVM The VM handle.
2099	* @param pSSM The SSM handle.
2100	* @param uType The page type.
2101	* @param pPage The page.
2102	* @param GCPhys The page address.
2103	* @param pRam The RAM range (for error messages).
2104	*/
2105	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2106	{
2107	uint8_t uState;
2108	int rc = SSMR3GetU8(pSSM, &uState);
2109	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2110	if (uState == 0 /* zero */)
2111	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2112	else if (uState == 1)
2113	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2114	else
2115	rc = VERR_INTERNAL_ERROR;
2116	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2117	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2118	rc);
2119	return VINF_SUCCESS;
2120	}
2121
2122
2123	/**
2124	* Loads a shadowed ROM page.
2125	*
2126	* @returns VBox status code, errors are fully bitched.
2127	* @param pVM The VM handle.
2128	* @param pSSM The saved state handle.
2129	* @param pPage The page.
2130	* @param GCPhys The page address.
2131	* @param pRam The RAM range (for error messages).
2132	*/
2133	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2134	{
2135	/*
2136	* Load and set the protection first, then load the two pages, the first
2137	* one is the active the other is the passive.
2138	*/
2139	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2140	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2141
2142	uint8_t uProt;
2143	int rc = SSMR3GetU8(pSSM, &uProt);
2144	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2145	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2146	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2147	&& enmProt < PGMROMPROT_END,
2148	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2149	VERR_SSM_UNEXPECTED_DATA);
2150
2151	if (pRomPage->enmProt != enmProt)
2152	{
2153	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2154	AssertLogRelRCReturn(rc, rc);
2155	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2156	}
2157
2158	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2159	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2160	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2161	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2162
2163	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2164	* used down the line (will the 2nd page will be written to the first
2165	* one because of a false TLB hit since the TLB is using GCPhys and
2166	* doesn't check the HCPhys of the desired page). */
2167	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2168	if (RT_SUCCESS(rc))
2169	{
2170	pPageActive = pPage;
2171	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2172	}
2173	return rc;
2174	}
2175
2176	/**
2177	* Ram range flags and bits for older versions of the saved state.
2178	*
2179	* @returns VBox status code.
2180	*
2181	* @param pVM The VM handle
2182	* @param pSSM The SSM handle.
2183	* @param uVersion The saved state version.
2184	*/
2185	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2186	{
2187	PPGM pPGM = &pVM->pgm.s;
2188
2189	/*
2190	* Ram range flags and bits.
2191	*/
2192	uint32_t i = 0;
2193	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2194	{
2195	/* Check the seqence number / separator. */
2196	uint32_t u32Sep;
2197	int rc = SSMR3GetU32(pSSM, &u32Sep);
2198	if (RT_FAILURE(rc))
2199	return rc;
2200	if (u32Sep == ~0U)
2201	break;
2202	if (u32Sep != i)
2203	{
2204	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2205	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2206	}
2207	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2208
2209	/* Get the range details. */
2210	RTGCPHYS GCPhys;
2211	SSMR3GetGCPhys(pSSM, &GCPhys);
2212	RTGCPHYS GCPhysLast;
2213	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2214	RTGCPHYS cb;
2215	SSMR3GetGCPhys(pSSM, &cb);
2216	uint8_t fHaveBits;
2217	rc = SSMR3GetU8(pSSM, &fHaveBits);
2218	if (RT_FAILURE(rc))
2219	return rc;
2220	if (fHaveBits & ~1)
2221	{
2222	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2223	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2224	}
2225	size_t cchDesc = 0;
2226	char szDesc[256];
2227	szDesc[0] = '\0';
2228	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2229	{
2230	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2231	if (RT_FAILURE(rc))
2232	return rc;
2233	/* Since we've modified the description strings in r45878, only compare
2234	them if the saved state is more recent. */
2235	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2236	cchDesc = strlen(szDesc);
2237	}
2238
2239	/*
2240	* Match it up with the current range.
2241	*
2242	* Note there is a hack for dealing with the high BIOS mapping
2243	* in the old saved state format, this means we might not have
2244	* a 1:1 match on success.
2245	*/
2246	if ( ( GCPhys != pRam->GCPhys
2247	\|\| GCPhysLast != pRam->GCPhysLast
2248	\|\| cb != pRam->cb
2249	\|\| ( cchDesc
2250	&& strcmp(szDesc, pRam->pszDesc)) )
2251	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2252	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2253	\|\| GCPhys != UINT32_C(0xfff80000)
2254	\|\| GCPhysLast != UINT32_C(0xffffffff)
2255	\|\| pRam->GCPhysLast != GCPhysLast
2256	\|\| pRam->GCPhys < GCPhys
2257	\|\| !fHaveBits)
2258	)
2259	{
2260	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2261	"State : %RGp-%RGp %RGp bytes %s %s\n",
2262	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2263	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2264	/*
2265	* If we're loading a state for debugging purpose, don't make a fuss if
2266	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2267	*/
2268	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2269	\|\| GCPhys < 8 * _1M)
2270	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2271	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2272	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2273	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2274
2275	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2276	continue;
2277	}
2278
2279	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2280	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2281	{
2282	/*
2283	* Load the pages one by one.
2284	*/
2285	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2286	{
2287	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2288	PPGMPAGE pPage = &pRam->aPages[iPage];
2289	uint8_t uType;
2290	rc = SSMR3GetU8(pSSM, &uType);
2291	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2292	if (uType == PGMPAGETYPE_ROM_SHADOW)
2293	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2294	else
2295	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2296	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2297	}
2298	}
2299	else
2300	{
2301	/*
2302	* Old format.
2303	*/
2304
2305	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2306	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2307	uint32_t fFlags = 0;
2308	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2309	{
2310	uint16_t u16Flags;
2311	rc = SSMR3GetU16(pSSM, &u16Flags);
2312	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2313	fFlags \|= u16Flags;
2314	}
2315
2316	/* Load the bits */
2317	if ( !fHaveBits
2318	&& GCPhysLast < UINT32_C(0xe0000000))
2319	{
2320	/*
2321	* Dynamic chunks.
2322	*/
2323	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2324	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2325	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2326	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2327
2328	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2329	{
2330	uint8_t fPresent;
2331	rc = SSMR3GetU8(pSSM, &fPresent);
2332	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2333	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2334	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2335	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2336
2337	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2338	{
2339	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2340	PPGMPAGE pPage = &pRam->aPages[iPage];
2341	if (fPresent)
2342	{
2343	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2344	rc = pgmR3LoadPageToDevNullOld(pSSM);
2345	else
2346	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2347	}
2348	else
2349	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2350	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2351	}
2352	}
2353	}
2354	else if (pRam->pvR3)
2355	{
2356	/*
2357	* MMIO2.
2358	*/
2359	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2360	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2361	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2362	AssertLogRelMsgReturn(pRam->pvR3,
2363	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2364	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2365
2366	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2367	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2368	}
2369	else if (GCPhysLast < UINT32_C(0xfff80000))
2370	{
2371	/*
2372	* PCI MMIO, no pages saved.
2373	*/
2374	}
2375	else
2376	{
2377	/*
2378	* Load the 0xfff80000..0xffffffff BIOS range.
2379	* It starts with X reserved pages that we have to skip over since
2380	* the RAMRANGE create by the new code won't include those.
2381	*/
2382	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2383	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2384	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2385	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2386	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2387	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2388	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2389
2390	/* Skip wasted reserved pages before the ROM. */
2391	while (GCPhys < pRam->GCPhys)
2392	{
2393	rc = pgmR3LoadPageToDevNullOld(pSSM);
2394	GCPhys += PAGE_SIZE;
2395	}
2396
2397	/* Load the bios pages. */
2398	cPages = pRam->cb >> PAGE_SHIFT;
2399	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2400	{
2401	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2402	PPGMPAGE pPage = &pRam->aPages[iPage];
2403
2404	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2405	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2406	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2407	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2408	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2409	}
2410	}
2411	}
2412	}
2413
2414	return VINF_SUCCESS;
2415	}
2416
2417
2418	/**
2419	* Worker for pgmR3Load and pgmR3LoadLocked.
2420	*
2421	* @returns VBox status code.
2422	*
2423	* @param pVM The VM handle.
2424	* @param pSSM The SSM handle.
2425	* @param uVersion The saved state version.
2426	*
2427	* @todo This needs splitting up if more record types or code twists are
2428	* added...
2429	*/
2430	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2431	{
2432	/*
2433	* Process page records until we hit the terminator.
2434	*/
2435	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2436	PPGMRAMRANGE pRamHint = NULL;
2437	uint8_t id = UINT8_MAX;
2438	uint32_t iPage = UINT32_MAX - 10;
2439	PPGMROMRANGE pRom = NULL;
2440	PPGMMMIO2RANGE pMmio2 = NULL;
2441	for (;;)
2442	{
2443	/*
2444	* Get the record type and flags.
2445	*/
2446	uint8_t u8;
2447	int rc = SSMR3GetU8(pSSM, &u8);
2448	if (RT_FAILURE(rc))
2449	return rc;
2450	if (u8 == PGM_STATE_REC_END)
2451	return VINF_SUCCESS;
2452	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2453	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2454	{
2455	/*
2456	* RAM page.
2457	*/
2458	case PGM_STATE_REC_RAM_ZERO:
2459	case PGM_STATE_REC_RAM_RAW:
2460	{
2461	/*
2462	* Get the address and resolve it into a page descriptor.
2463	*/
2464	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2465	GCPhys += PAGE_SIZE;
2466	else
2467	{
2468	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2469	if (RT_FAILURE(rc))
2470	return rc;
2471	}
2472	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2473
2474	PPGMPAGE pPage;
2475	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2476	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2477
2478	/*
2479	* Take action according to the record type.
2480	*/
2481	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2482	{
2483	case PGM_STATE_REC_RAM_ZERO:
2484	{
2485	if (PGM_PAGE_IS_ZERO(pPage))
2486	break;
2487	/** @todo implement zero page replacing. */
2488	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2489	void *pvDstPage;
2490	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2491	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2492	ASMMemZeroPage(pvDstPage);
2493	break;
2494	}
2495
2496	case PGM_STATE_REC_RAM_RAW:
2497	{
2498	void *pvDstPage;
2499	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2500	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2501	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2502	if (RT_FAILURE(rc))
2503	return rc;
2504	break;
2505	}
2506
2507	default:
2508	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2509	}
2510	id = UINT8_MAX;
2511	break;
2512	}
2513
2514	/*
2515	* MMIO2 page.
2516	*/
2517	case PGM_STATE_REC_MMIO2_RAW:
2518	case PGM_STATE_REC_MMIO2_ZERO:
2519	{
2520	/*
2521	* Get the ID + page number and resolved that into a MMIO2 page.
2522	*/
2523	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2524	iPage++;
2525	else
2526	{
2527	SSMR3GetU8(pSSM, &id);
2528	rc = SSMR3GetU32(pSSM, &iPage);
2529	if (RT_FAILURE(rc))
2530	return rc;
2531	}
2532	if ( !pMmio2
2533	\|\| pMmio2->idSavedState != id)
2534	{
2535	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2536	if (pMmio2->idSavedState == id)
2537	break;
2538	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2539	}
2540	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2541	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2542
2543	/*
2544	* Load the page bits.
2545	*/
2546	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2547	ASMMemZeroPage(pvDstPage);
2548	else
2549	{
2550	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2551	if (RT_FAILURE(rc))
2552	return rc;
2553	}
2554	GCPhys = NIL_RTGCPHYS;
2555	break;
2556	}
2557
2558	/*
2559	* ROM pages.
2560	*/
2561	case PGM_STATE_REC_ROM_VIRGIN:
2562	case PGM_STATE_REC_ROM_SHW_RAW:
2563	case PGM_STATE_REC_ROM_SHW_ZERO:
2564	case PGM_STATE_REC_ROM_PROT:
2565	{
2566	/*
2567	* Get the ID + page number and resolved that into a ROM page descriptor.
2568	*/
2569	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2570	iPage++;
2571	else
2572	{
2573	SSMR3GetU8(pSSM, &id);
2574	rc = SSMR3GetU32(pSSM, &iPage);
2575	if (RT_FAILURE(rc))
2576	return rc;
2577	}
2578	if ( !pRom
2579	\|\| pRom->idSavedState != id)
2580	{
2581	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2582	if (pRom->idSavedState == id)
2583	break;
2584	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2585	}
2586	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2587	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2588	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2589
2590	/*
2591	* Get and set the protection.
2592	*/
2593	uint8_t u8Prot;
2594	rc = SSMR3GetU8(pSSM, &u8Prot);
2595	if (RT_FAILURE(rc))
2596	return rc;
2597	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2598	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2599
2600	if (enmProt != pRomPage->enmProt)
2601	{
2602	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2603	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2604	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2605	GCPhys, enmProt, pRom->pszDesc);
2606	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2607	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2608	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2609	}
2610	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2611	break; /* done */
2612
2613	/*
2614	* Get the right page descriptor.
2615	*/
2616	PPGMPAGE pRealPage;
2617	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2618	{
2619	case PGM_STATE_REC_ROM_VIRGIN:
2620	if (!PGMROMPROT_IS_ROM(enmProt))
2621	pRealPage = &pRomPage->Virgin;
2622	else
2623	pRealPage = NULL;
2624	break;
2625
2626	case PGM_STATE_REC_ROM_SHW_RAW:
2627	case PGM_STATE_REC_ROM_SHW_ZERO:
2628	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2629	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2630	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2631	GCPhys, enmProt, pRom->pszDesc);
2632	if (PGMROMPROT_IS_ROM(enmProt))
2633	pRealPage = &pRomPage->Shadow;
2634	else
2635	pRealPage = NULL;
2636	break;
2637
2638	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2639	}
2640	if (!pRealPage)
2641	{
2642	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2643	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2644	}
2645
2646	/*
2647	* Make it writable and map it (if necessary).
2648	*/
2649	void *pvDstPage = NULL;
2650	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2651	{
2652	case PGM_STATE_REC_ROM_SHW_ZERO:
2653	if (PGM_PAGE_IS_ZERO(pRealPage))
2654	break;
2655	/** @todo implement zero page replacing. */
2656	/* fall thru */
2657	case PGM_STATE_REC_ROM_VIRGIN:
2658	case PGM_STATE_REC_ROM_SHW_RAW:
2659	{
2660	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2661	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2662	break;
2663	}
2664	}
2665
2666	/*
2667	* Load the bits.
2668	*/
2669	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2670	{
2671	case PGM_STATE_REC_ROM_SHW_ZERO:
2672	if (pvDstPage)
2673	ASMMemZeroPage(pvDstPage);
2674	break;
2675
2676	case PGM_STATE_REC_ROM_VIRGIN:
2677	case PGM_STATE_REC_ROM_SHW_RAW:
2678	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2679	if (RT_FAILURE(rc))
2680	return rc;
2681	break;
2682	}
2683	GCPhys = NIL_RTGCPHYS;
2684	break;
2685	}
2686
2687	/*
2688	* Unknown type.
2689	*/
2690	default:
2691	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2692	}
2693	} /* forever */
2694	}
2695
2696
2697	/**
2698	* Worker for pgmR3Load.
2699	*
2700	* @returns VBox status code.
2701	*
2702	* @param pVM The VM handle.
2703	* @param pSSM The SSM handle.
2704	* @param uVersion The saved state version.
2705	*/
2706	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2707	{
2708	PPGM pPGM = &pVM->pgm.s;
2709	int rc;
2710	uint32_t u32Sep;
2711
2712	/*
2713	* Load basic data (required / unaffected by relocation).
2714	*/
2715	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2716	{
2717	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2718	AssertLogRelRCReturn(rc, rc);
2719
2720	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2721	{
2722	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2723	AssertLogRelRCReturn(rc, rc);
2724	}
2725	}
2726	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2727	{
2728	AssertRelease(pVM->cCpus == 1);
2729
2730	PGMOLD pgmOld;
2731	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2732	AssertLogRelRCReturn(rc, rc);
2733
2734	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2735	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2736	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2737
2738	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2739	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2740	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2741	}
2742	else
2743	{
2744	AssertRelease(pVM->cCpus == 1);
2745
2746	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2747	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2748	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2749
2750	uint32_t cbRamSizeIgnored;
2751	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2752	if (RT_FAILURE(rc))
2753	return rc;
2754	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2755
2756	uint32_t u32 = 0;
2757	SSMR3GetUInt(pSSM, &u32);
2758	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2759	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2760	RTUINT uGuestMode;
2761	SSMR3GetUInt(pSSM, &uGuestMode);
2762	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2763
2764	/* check separator. */
2765	SSMR3GetU32(pSSM, &u32Sep);
2766	if (RT_FAILURE(rc))
2767	return rc;
2768	if (u32Sep != (uint32_t)~0)
2769	{
2770	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2771	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2772	}
2773	}
2774
2775	/*
2776	* The guest mappings.
2777	*/
2778	uint32_t i = 0;
2779	for (;; i++)
2780	{
2781	/* Check the seqence number / separator. */
2782	rc = SSMR3GetU32(pSSM, &u32Sep);
2783	if (RT_FAILURE(rc))
2784	return rc;
2785	if (u32Sep == ~0U)
2786	break;
2787	if (u32Sep != i)
2788	{
2789	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2790	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2791	}
2792
2793	/* get the mapping details. */
2794	char szDesc[256];
2795	szDesc[0] = '\0';
2796	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2797	if (RT_FAILURE(rc))
2798	return rc;
2799	RTGCPTR GCPtr;
2800	SSMR3GetGCPtr(pSSM, &GCPtr);
2801	RTGCPTR cPTs;
2802	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2803	if (RT_FAILURE(rc))
2804	return rc;
2805
2806	/* find matching range. */
2807	PPGMMAPPING pMapping;
2808	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2809	{
2810	if ( pMapping->cPTs == cPTs
2811	&& !strcmp(pMapping->pszDesc, szDesc))
2812	break;
2813	#ifdef DEBUG_sandervl
2814	if ( !strcmp(szDesc, "Hypervisor Memory Area")
2815	&& HWACCMIsEnabled(pVM))
2816	break;
2817	#endif
2818	}
2819	if (!pMapping)
2820	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)"),
2821	cPTs, szDesc, GCPtr);
2822
2823	/* relocate it. */
2824	if ( pMapping->GCPtr != GCPtr
2825	#ifdef DEBUG_sandervl
2826	&& !(!strcmp(szDesc, "Hypervisor Memory Area") && HWACCMIsEnabled(pVM))
2827	#endif
2828	)
2829	{
2830	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2831	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2832	}
2833	else
2834	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2835	}
2836
2837	/*
2838	* Load the RAM contents.
2839	*/
2840	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2841	{
2842	if (!pVM->pgm.s.LiveSave.fActive)
2843	{
2844	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2845	{
2846	rc = pgmR3LoadRamConfig(pVM, pSSM);
2847	if (RT_FAILURE(rc))
2848	return rc;
2849	}
2850	rc = pgmR3LoadRomRanges(pVM, pSSM);
2851	if (RT_FAILURE(rc))
2852	return rc;
2853	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2854	if (RT_FAILURE(rc))
2855	return rc;
2856	}
2857
2858	return pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2859	}
2860	return pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2861	}
2862
2863
2864	/**
2865	* Execute state load operation.
2866	*
2867	* @returns VBox status code.
2868	* @param pVM VM Handle.
2869	* @param pSSM SSM operation handle.
2870	* @param uVersion Data layout version.
2871	* @param uPass The data pass.
2872	*/
2873	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2874	{
2875	int rc;
2876	PPGM pPGM = &pVM->pgm.s;
2877
2878	/*
2879	* Validate version.
2880	*/
2881	if ( ( uPass != SSM_PASS_FINAL
2882	&& uVersion != PGM_SAVED_STATE_VERSION
2883	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2884	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
2885	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
2886	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
2887	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
2888	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
2889	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2890	)
2891	{
2892	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
2893	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2894	}
2895
2896	/*
2897	* Do the loading while owning the lock because a bunch of the functions
2898	* we're using requires this.
2899	*/
2900	if (uPass != SSM_PASS_FINAL)
2901	{
2902	pgmLock(pVM);
2903	if (uPass != 0)
2904	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2905	else
2906	{
2907	pVM->pgm.s.LiveSave.fActive = true;
2908	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2909	rc = pgmR3LoadRamConfig(pVM, pSSM);
2910	else
2911	rc = VINF_SUCCESS;
2912	if (RT_SUCCESS(rc))
2913	rc = pgmR3LoadRomRanges(pVM, pSSM);
2914	if (RT_SUCCESS(rc))
2915	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2916	if (RT_SUCCESS(rc))
2917	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2918	}
2919	pgmUnlock(pVM);
2920	}
2921	else
2922	{
2923	pgmLock(pVM);
2924	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
2925	pVM->pgm.s.LiveSave.fActive = false;
2926	pgmUnlock(pVM);
2927	if (RT_SUCCESS(rc))
2928	{
2929	/*
2930	* We require a full resync now.
2931	*/
2932	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2933	{
2934	PVMCPU pVCpu = &pVM->aCpus[i];
2935	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2936	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2937
2938	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2939	}
2940
2941	pgmR3HandlerPhysicalUpdateAll(pVM);
2942
2943	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2944	{
2945	PVMCPU pVCpu = &pVM->aCpus[i];
2946
2947	/*
2948	* Change the paging mode.
2949	*/
2950	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
2951
2952	/* Restore pVM->pgm.s.GCPhysCR3. */
2953	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2954	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
2955	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
2956	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2957	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
2958	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2959	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2960	else
2961	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2962	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2963	}
2964	}
2965	}
2966
2967	return rc;
2968	}
2969
2970
2971	/**
2972	* Registers the saved state callbacks with SSM.
2973	*
2974	* @returns VBox status code.
2975	* @param pVM Pointer to VM structure.
2976	* @param cbRam The RAM size.
2977	*/
2978	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
2979	{
2980	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
2981	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
2982	NULL, pgmR3SaveExec, pgmR3SaveDone,
2983	pgmR3LoadPrep, pgmR3Load, NULL);
2984	}
2985

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source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 24808

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