VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 32059

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1/* $Id: PGMSavedState.cpp 32053 2010-08-27 14:10:39Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, The Saved State Part.
4 */
5
6/*
7 * Copyright (C) 2006-2009 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM
23#include <VBox/pgm.h>
24#include <VBox/stam.h>
25#include <VBox/ssm.h>
26#include <VBox/pdmdrv.h>
27#include <VBox/pdmdev.h>
28#include "PGMInternal.h"
29#include <VBox/vm.h>
30#include "PGMInline.h"
31
32#include <VBox/param.h>
33#include <VBox/err.h>
34#include <VBox/ftm.h>
35
36#include <iprt/asm.h>
37#include <iprt/assert.h>
38#include <iprt/crc.h>
39#include <iprt/mem.h>
40#include <iprt/sha.h>
41#include <iprt/string.h>
42#include <iprt/thread.h>
43
44
45/*******************************************************************************
46* Defined Constants And Macros *
47*******************************************************************************/
48/** Saved state data unit version.
49 * @todo remove the guest mappings from the saved state at next version change! */
50#define PGM_SAVED_STATE_VERSION 12
51/** Saved state before the balloon change. */
52#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
53/** Saved state data unit version used during 3.1 development, misses the RAM
54 * config. */
55#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
56/** Saved state data unit version for 3.0 (pre teleportation). */
57#define PGM_SAVED_STATE_VERSION_3_0_0 9
58/** Saved state data unit version for 2.2.2 and later. */
59#define PGM_SAVED_STATE_VERSION_2_2_2 8
60/** Saved state data unit version for 2.2.0. */
61#define PGM_SAVED_STATE_VERSION_RR_DESC 7
62/** Saved state data unit version. */
63#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
64
65
66/** @name Sparse state record types
67 * @{ */
68/** Zero page. No data. */
69#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
70/** Raw page. */
71#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
72/** Raw MMIO2 page. */
73#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
74/** Zero MMIO2 page. */
75#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
76/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
77#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
78/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
79#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
80/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
81#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
82/** ROM protection (8-bit). */
83#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
84/** The last record type. */
85#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
86/** End marker. */
87#define PGM_STATE_REC_END UINT8_C(0xff)
88/** Flag indicating that the data is preceeded by the page address.
89 * For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
90 * range ID and a 32-bit page index.
91 */
92#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
93/** @} */
94
95/** The CRC-32 for a zero page. */
96#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
97/** The CRC-32 for a zero half page. */
98#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
99
100
101/*******************************************************************************
102* Structures and Typedefs *
103*******************************************************************************/
104/** For loading old saved states. (pre-smp) */
105typedef struct
106{
107 /** If set no conflict checks are required. (boolean) */
108 bool fMappingsFixed;
109 /** Size of fixed mapping */
110 uint32_t cbMappingFixed;
111 /** Base address (GC) of fixed mapping */
112 RTGCPTR GCPtrMappingFixed;
113 /** A20 gate mask.
114 * Our current approach to A20 emulation is to let REM do it and don't bother
115 * anywhere else. The interesting guests will be operating with it enabled anyway.
116 * But should the need arise, we'll subject physical addresses to this mask. */
117 RTGCPHYS GCPhysA20Mask;
118 /** A20 gate state - boolean! */
119 bool fA20Enabled;
120 /** The guest paging mode. */
121 PGMMODE enmGuestMode;
122} PGMOLD;
123
124
125/*******************************************************************************
126* Global Variables *
127*******************************************************************************/
128/** PGM fields to save/load. */
129
130static const SSMFIELD s_aPGMFields[] =
131{
132 SSMFIELD_ENTRY( PGM, fMappingsFixed),
133 SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
134 SSMFIELD_ENTRY( PGM, cbMappingFixed),
135 SSMFIELD_ENTRY( PGM, cBalloonedPages),
136 SSMFIELD_ENTRY_TERM()
137};
138
139static const SSMFIELD s_aPGMFieldsPreBalloon[] =
140{
141 SSMFIELD_ENTRY( PGM, fMappingsFixed),
142 SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
143 SSMFIELD_ENTRY( PGM, cbMappingFixed),
144 SSMFIELD_ENTRY_TERM()
145};
146
147static const SSMFIELD s_aPGMCpuFields[] =
148{
149 SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
150 SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
151 SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
152 SSMFIELD_ENTRY_TERM()
153};
154
155static const SSMFIELD s_aPGMFields_Old[] =
156{
157 SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
158 SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
159 SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
160 SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
161 SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
162 SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
163 SSMFIELD_ENTRY_TERM()
164};
165
166
167/**
168 * Find the ROM tracking structure for the given page.
169 *
170 * @returns Pointer to the ROM page structure. NULL if the caller didn't check
171 * that it's a ROM page.
172 * @param pVM The VM handle.
173 * @param GCPhys The address of the ROM page.
174 */
175static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
176{
177 for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
178 pRomRange;
179 pRomRange = pRomRange->CTX_SUFF(pNext))
180 {
181 RTGCPHYS off = GCPhys - pRomRange->GCPhys;
182 if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
183 return &pRomRange->aPages[off >> PAGE_SHIFT];
184 }
185 return NULL;
186}
187
188
189/**
190 * Prepares the ROM pages for a live save.
191 *
192 * @returns VBox status code.
193 * @param pVM The VM handle.
194 */
195static int pgmR3PrepRomPages(PVM pVM)
196{
197 /*
198 * Initialize the live save tracking in the ROM page descriptors.
199 */
200 pgmLock(pVM);
201 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
202 {
203 PPGMRAMRANGE pRamHint = NULL;;
204 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
205
206 for (uint32_t iPage = 0; iPage < cPages; iPage++)
207 {
208 pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
209 pRom->aPages[iPage].LiveSave.fWrittenTo = false;
210 pRom->aPages[iPage].LiveSave.fDirty = true;
211 pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
212 if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
213 {
214 if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
215 pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
216 else
217 {
218 RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
219 PPGMPAGE pPage;
220 int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
221 AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
222 if (RT_SUCCESS(rc))
223 pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
224 else
225 pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
226 }
227 }
228 }
229
230 pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
231 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
232 pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
233 }
234 pgmUnlock(pVM);
235
236 return VINF_SUCCESS;
237}
238
239
240/**
241 * Assigns IDs to the ROM ranges and saves them.
242 *
243 * @returns VBox status code.
244 * @param pVM The VM handle.
245 * @param pSSM Saved state handle.
246 */
247static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
248{
249 pgmLock(pVM);
250 uint8_t id = 1;
251 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
252 {
253 pRom->idSavedState = id;
254 SSMR3PutU8(pSSM, id);
255 SSMR3PutStrZ(pSSM, ""); /* device name */
256 SSMR3PutU32(pSSM, 0); /* device instance */
257 SSMR3PutU8(pSSM, 0); /* region */
258 SSMR3PutStrZ(pSSM, pRom->pszDesc);
259 SSMR3PutGCPhys(pSSM, pRom->GCPhys);
260 int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
261 if (RT_FAILURE(rc))
262 break;
263 }
264 pgmUnlock(pVM);
265 return SSMR3PutU8(pSSM, UINT8_MAX);
266}
267
268
269/**
270 * Loads the ROM range ID assignments.
271 *
272 * @returns VBox status code.
273 *
274 * @param pVM The VM handle.
275 * @param pSSM The saved state handle.
276 */
277static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
278{
279 Assert(PGMIsLockOwner(pVM));
280
281 if (FTMIsDeltaLoadSaveActive(pVM))
282 return VINF_SUCCESS; /* nothing to do as nothing has changed here */
283
284 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
285 pRom->idSavedState = UINT8_MAX;
286
287 for (;;)
288 {
289 /*
290 * Read the data.
291 */
292 uint8_t id;
293 int rc = SSMR3GetU8(pSSM, &id);
294 if (RT_FAILURE(rc))
295 return rc;
296 if (id == UINT8_MAX)
297 {
298 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
299 AssertLogRelMsg(pRom->idSavedState != UINT8_MAX,
300 ("The \"%s\" ROM was not found in the saved state. Probably due to some misconfiguration\n",
301 pRom->pszDesc));
302 return VINF_SUCCESS; /* the end */
303 }
304 AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
305
306 char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
307 rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
308 AssertLogRelRCReturn(rc, rc);
309
310 uint32_t uInstance;
311 SSMR3GetU32(pSSM, &uInstance);
312 uint8_t iRegion;
313 SSMR3GetU8(pSSM, &iRegion);
314
315 char szDesc[64];
316 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
317 AssertLogRelRCReturn(rc, rc);
318
319 RTGCPHYS GCPhys;
320 SSMR3GetGCPhys(pSSM, &GCPhys);
321 RTGCPHYS cb;
322 rc = SSMR3GetGCPhys(pSSM, &cb);
323 if (RT_FAILURE(rc))
324 return rc;
325 AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
326 AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
327
328 /*
329 * Locate a matching ROM range.
330 */
331 AssertLogRelMsgReturn( uInstance == 0
332 && iRegion == 0
333 && szDevName[0] == '\0',
334 ("GCPhys=%RGp %s\n", GCPhys, szDesc),
335 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
336 PPGMROMRANGE pRom;
337 for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
338 {
339 if ( pRom->idSavedState == UINT8_MAX
340 && !strcmp(pRom->pszDesc, szDesc))
341 {
342 pRom->idSavedState = id;
343 break;
344 }
345 }
346 if (!pRom)
347 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
348 } /* forever */
349}
350
351
352/**
353 * Scan ROM pages.
354 *
355 * @param pVM The VM handle.
356 */
357static void pgmR3ScanRomPages(PVM pVM)
358{
359 /*
360 * The shadow ROMs.
361 */
362 pgmLock(pVM);
363 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
364 {
365 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
366 {
367 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
368 for (uint32_t iPage = 0; iPage < cPages; iPage++)
369 {
370 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
371 if (pRomPage->LiveSave.fWrittenTo)
372 {
373 pRomPage->LiveSave.fWrittenTo = false;
374 if (!pRomPage->LiveSave.fDirty)
375 {
376 pRomPage->LiveSave.fDirty = true;
377 pVM->pgm.s.LiveSave.Rom.cReadyPages--;
378 pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
379 }
380 pRomPage->LiveSave.fDirtiedRecently = true;
381 }
382 else
383 pRomPage->LiveSave.fDirtiedRecently = false;
384 }
385 }
386 }
387 pgmUnlock(pVM);
388}
389
390
391/**
392 * Takes care of the virgin ROM pages in the first pass.
393 *
394 * This is an attempt at simplifying the handling of ROM pages a little bit.
395 * This ASSUMES that no new ROM ranges will be added and that they won't be
396 * relinked in any way.
397 *
398 * @param pVM The VM handle.
399 * @param pSSM The SSM handle.
400 * @param fLiveSave Whether we're in a live save or not.
401 */
402static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
403{
404 if (FTMIsDeltaLoadSaveActive(pVM))
405 return VINF_SUCCESS; /* nothing to do as nothing has changed here */
406
407 pgmLock(pVM);
408 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
409 {
410 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
411 for (uint32_t iPage = 0; iPage < cPages; iPage++)
412 {
413 RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
414 PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
415
416 /* Get the virgin page descriptor. */
417 PPGMPAGE pPage;
418 if (PGMROMPROT_IS_ROM(enmProt))
419 pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
420 else
421 pPage = &pRom->aPages[iPage].Virgin;
422
423 /* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
424 int rc = VINF_SUCCESS;
425 char abPage[PAGE_SIZE];
426 if ( !PGM_PAGE_IS_ZERO(pPage)
427 && !PGM_PAGE_IS_BALLOONED(pPage))
428 {
429 void const *pvPage;
430 rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
431 if (RT_SUCCESS(rc))
432 memcpy(abPage, pvPage, PAGE_SIZE);
433 }
434 else
435 ASMMemZeroPage(abPage);
436 pgmUnlock(pVM);
437 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
438
439 /* Save it. */
440 if (iPage > 0)
441 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
442 else
443 {
444 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN | PGM_STATE_REC_FLAG_ADDR);
445 SSMR3PutU8(pSSM, pRom->idSavedState);
446 SSMR3PutU32(pSSM, iPage);
447 }
448 SSMR3PutU8(pSSM, (uint8_t)enmProt);
449 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
450 if (RT_FAILURE(rc))
451 return rc;
452
453 /* Update state. */
454 pgmLock(pVM);
455 pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
456 if (fLiveSave)
457 {
458 pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
459 pVM->pgm.s.LiveSave.Rom.cReadyPages++;
460 pVM->pgm.s.LiveSave.cSavedPages++;
461 }
462 }
463 }
464 pgmUnlock(pVM);
465 return VINF_SUCCESS;
466}
467
468
469/**
470 * Saves dirty pages in the shadowed ROM ranges.
471 *
472 * Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
473 *
474 * @returns VBox status code.
475 * @param pVM The VM handle.
476 * @param pSSM The SSM handle.
477 * @param fLiveSave Whether it's a live save or not.
478 * @param fFinalPass Whether this is the final pass or not.
479 */
480static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
481{
482 if (FTMIsDeltaLoadSaveActive(pVM))
483 return VINF_SUCCESS; /* nothing to do as we deal with those pages seperately */
484
485 /*
486 * The Shadowed ROMs.
487 *
488 * ASSUMES that the ROM ranges are fixed.
489 * ASSUMES that all the ROM ranges are mapped.
490 */
491 pgmLock(pVM);
492 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
493 {
494 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
495 {
496 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
497 uint32_t iPrevPage = cPages;
498 for (uint32_t iPage = 0; iPage < cPages; iPage++)
499 {
500 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
501 if ( !fLiveSave
502 || ( pRomPage->LiveSave.fDirty
503 && ( ( !pRomPage->LiveSave.fDirtiedRecently
504 && !pRomPage->LiveSave.fWrittenTo)
505 || fFinalPass
506 )
507 )
508 )
509 {
510 uint8_t abPage[PAGE_SIZE];
511 PGMROMPROT enmProt = pRomPage->enmProt;
512 RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
513 PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
514 bool fZero = PGM_PAGE_IS_ZERO(pPage) || PGM_PAGE_IS_BALLOONED(pPage);
515 int rc = VINF_SUCCESS;
516 if (!fZero)
517 {
518 void const *pvPage;
519 rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
520 if (RT_SUCCESS(rc))
521 memcpy(abPage, pvPage, PAGE_SIZE);
522 }
523 if (fLiveSave && RT_SUCCESS(rc))
524 {
525 pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
526 pRomPage->LiveSave.fDirty = false;
527 pVM->pgm.s.LiveSave.Rom.cReadyPages++;
528 pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
529 pVM->pgm.s.LiveSave.cSavedPages++;
530 }
531 pgmUnlock(pVM);
532 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
533
534 if (iPage - 1U == iPrevPage && iPage > 0)
535 SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
536 else
537 {
538 SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) | PGM_STATE_REC_FLAG_ADDR);
539 SSMR3PutU8(pSSM, pRom->idSavedState);
540 SSMR3PutU32(pSSM, iPage);
541 }
542 rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
543 if (!fZero)
544 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
545 if (RT_FAILURE(rc))
546 return rc;
547
548 pgmLock(pVM);
549 iPrevPage = iPage;
550 }
551 /*
552 * In the final pass, make sure the protection is in sync.
553 */
554 else if ( fFinalPass
555 && pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
556 {
557 PGMROMPROT enmProt = pRomPage->enmProt;
558 pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
559 pgmUnlock(pVM);
560
561 if (iPage - 1U == iPrevPage && iPage > 0)
562 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
563 else
564 {
565 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT | PGM_STATE_REC_FLAG_ADDR);
566 SSMR3PutU8(pSSM, pRom->idSavedState);
567 SSMR3PutU32(pSSM, iPage);
568 }
569 int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
570 if (RT_FAILURE(rc))
571 return rc;
572
573 pgmLock(pVM);
574 iPrevPage = iPage;
575 }
576 }
577 }
578 }
579 pgmUnlock(pVM);
580 return VINF_SUCCESS;
581}
582
583
584/**
585 * Cleans up ROM pages after a live save.
586 *
587 * @param pVM The VM handle.
588 */
589static void pgmR3DoneRomPages(PVM pVM)
590{
591 NOREF(pVM);
592}
593
594
595/**
596 * Prepares the MMIO2 pages for a live save.
597 *
598 * @returns VBox status code.
599 * @param pVM The VM handle.
600 */
601static int pgmR3PrepMmio2Pages(PVM pVM)
602{
603 /*
604 * Initialize the live save tracking in the MMIO2 ranges.
605 * ASSUME nothing changes here.
606 */
607 pgmLock(pVM);
608 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
609 {
610 uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
611 pgmUnlock(pVM);
612
613 PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
614 if (!paLSPages)
615 return VERR_NO_MEMORY;
616 for (uint32_t iPage = 0; iPage < cPages; iPage++)
617 {
618 /* Initialize it as a dirty zero page. */
619 paLSPages[iPage].fDirty = true;
620 paLSPages[iPage].cUnchangedScans = 0;
621 paLSPages[iPage].fZero = true;
622 paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
623 paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
624 }
625
626 pgmLock(pVM);
627 pMmio2->paLSPages = paLSPages;
628 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
629 }
630 pgmUnlock(pVM);
631 return VINF_SUCCESS;
632}
633
634
635/**
636 * Assigns IDs to the MMIO2 ranges and saves them.
637 *
638 * @returns VBox status code.
639 * @param pVM The VM handle.
640 * @param pSSM Saved state handle.
641 */
642static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
643{
644 pgmLock(pVM);
645 uint8_t id = 1;
646 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
647 {
648 pMmio2->idSavedState = id;
649 SSMR3PutU8(pSSM, id);
650 SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pReg->szName);
651 SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
652 SSMR3PutU8(pSSM, pMmio2->iRegion);
653 SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
654 int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
655 if (RT_FAILURE(rc))
656 break;
657 }
658 pgmUnlock(pVM);
659 return SSMR3PutU8(pSSM, UINT8_MAX);
660}
661
662
663/**
664 * Loads the MMIO2 range ID assignments.
665 *
666 * @returns VBox status code.
667 *
668 * @param pVM The VM handle.
669 * @param pSSM The saved state handle.
670 */
671static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
672{
673 Assert(PGMIsLockOwner(pVM));
674
675 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
676 pMmio2->idSavedState = UINT8_MAX;
677
678 for (;;)
679 {
680 /*
681 * Read the data.
682 */
683 uint8_t id;
684 int rc = SSMR3GetU8(pSSM, &id);
685 if (RT_FAILURE(rc))
686 return rc;
687 if (id == UINT8_MAX)
688 {
689 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
690 AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
691 return VINF_SUCCESS; /* the end */
692 }
693 AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
694
695 char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
696 rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
697 AssertLogRelRCReturn(rc, rc);
698
699 uint32_t uInstance;
700 SSMR3GetU32(pSSM, &uInstance);
701 uint8_t iRegion;
702 SSMR3GetU8(pSSM, &iRegion);
703
704 char szDesc[64];
705 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
706 AssertLogRelRCReturn(rc, rc);
707
708 RTGCPHYS cb;
709 rc = SSMR3GetGCPhys(pSSM, &cb);
710 AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
711
712 /*
713 * Locate a matching MMIO2 range.
714 */
715 PPGMMMIO2RANGE pMmio2;
716 for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
717 {
718 if ( pMmio2->idSavedState == UINT8_MAX
719 && pMmio2->iRegion == iRegion
720 && pMmio2->pDevInsR3->iInstance == uInstance
721 && !strcmp(pMmio2->pDevInsR3->pReg->szName, szDevName))
722 {
723 pMmio2->idSavedState = id;
724 break;
725 }
726 }
727 if (!pMmio2)
728 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
729 szDesc, szDevName, uInstance, iRegion);
730
731 /*
732 * Validate the configuration, the size of the MMIO2 region should be
733 * the same.
734 */
735 if (cb != pMmio2->RamRange.cb)
736 {
737 LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
738 pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
739 if (cb > pMmio2->RamRange.cb) /* bad idea? */
740 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
741 pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
742 }
743 } /* forever */
744}
745
746
747/**
748 * Scans one MMIO2 page.
749 *
750 * @returns True if changed, false if unchanged.
751 *
752 * @param pVM The VM handle
753 * @param pbPage The page bits.
754 * @param pLSPage The live save tracking structure for the page.
755 *
756 */
757DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
758{
759 /*
760 * Special handling of zero pages.
761 */
762 bool const fZero = pLSPage->fZero;
763 if (fZero)
764 {
765 if (ASMMemIsZeroPage(pbPage))
766 {
767 /* Not modified. */
768 if (pLSPage->fDirty)
769 pLSPage->cUnchangedScans++;
770 return false;
771 }
772
773 pLSPage->fZero = false;
774 pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
775 }
776 else
777 {
778 /*
779 * CRC the first half, if it doesn't match the page is dirty and
780 * we won't check the 2nd half (we'll do that next time).
781 */
782 uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
783 if (u32CrcH1 == pLSPage->u32CrcH1)
784 {
785 uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
786 if (u32CrcH2 == pLSPage->u32CrcH2)
787 {
788 /* Probably not modified. */
789 if (pLSPage->fDirty)
790 pLSPage->cUnchangedScans++;
791 return false;
792 }
793
794 pLSPage->u32CrcH2 = u32CrcH2;
795 }
796 else
797 {
798 pLSPage->u32CrcH1 = u32CrcH1;
799 if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
800 && ASMMemIsZeroPage(pbPage))
801 {
802 pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
803 pLSPage->fZero = true;
804 }
805 }
806 }
807
808 /* dirty page path */
809 pLSPage->cUnchangedScans = 0;
810 if (!pLSPage->fDirty)
811 {
812 pLSPage->fDirty = true;
813 pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
814 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
815 if (fZero)
816 pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
817 }
818 return true;
819}
820
821
822/**
823 * Scan for MMIO2 page modifications.
824 *
825 * @param pVM The VM handle.
826 * @param uPass The pass number.
827 */
828static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
829{
830 /*
831 * Since this is a bit expensive we lower the scan rate after a little while.
832 */
833 if ( ( (uPass & 3) != 0
834 && uPass > 10)
835 || uPass == SSM_PASS_FINAL)
836 return;
837
838 pgmLock(pVM); /* paranoia */
839 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
840 {
841 PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
842 uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
843 pgmUnlock(pVM);
844
845 for (uint32_t iPage = 0; iPage < cPages; iPage++)
846 {
847 uint8_t const *pbPage = (uint8_t const *)pMmio2->pvR3 + iPage * PAGE_SIZE;
848 pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
849 }
850
851 pgmLock(pVM);
852 }
853 pgmUnlock(pVM);
854
855}
856
857
858/**
859 * Save quiescent MMIO2 pages.
860 *
861 * @returns VBox status code.
862 * @param pVM The VM handle.
863 * @param pSSM The SSM handle.
864 * @param fLiveSave Whether it's a live save or not.
865 * @param uPass The pass number.
866 */
867static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
868{
869 /** @todo implement live saving of MMIO2 pages. (Need some way of telling the
870 * device that we wish to know about changes.) */
871
872 int rc = VINF_SUCCESS;
873 if (uPass == SSM_PASS_FINAL)
874 {
875 /*
876 * The mop up round.
877 */
878 pgmLock(pVM);
879 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
880 pMmio2 && RT_SUCCESS(rc);
881 pMmio2 = pMmio2->pNextR3)
882 {
883 PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
884 uint8_t const *pbPage = (uint8_t const *)pMmio2->RamRange.pvR3;
885 uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
886 uint32_t iPageLast = cPages;
887 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
888 {
889 uint8_t u8Type;
890 if (!fLiveSave)
891 u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
892 else
893 {
894 /* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
895 if ( !paLSPages[iPage].fDirty
896 && !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
897 {
898 if (paLSPages[iPage].fZero)
899 continue;
900
901 uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
902 RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
903 if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
904 continue;
905 }
906 u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
907 pVM->pgm.s.LiveSave.cSavedPages++;
908 }
909
910 if (iPage != 0 && iPage == iPageLast + 1)
911 rc = SSMR3PutU8(pSSM, u8Type);
912 else
913 {
914 SSMR3PutU8(pSSM, u8Type | PGM_STATE_REC_FLAG_ADDR);
915 SSMR3PutU8(pSSM, pMmio2->idSavedState);
916 rc = SSMR3PutU32(pSSM, iPage);
917 }
918 if (u8Type == PGM_STATE_REC_MMIO2_RAW)
919 rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
920 if (RT_FAILURE(rc))
921 break;
922 iPageLast = iPage;
923 }
924 }
925 pgmUnlock(pVM);
926 }
927 /*
928 * Reduce the rate after a little while since the current MMIO2 approach is
929 * a bit expensive.
930 * We position it two passes after the scan pass to avoid saving busy pages.
931 */
932 else if ( uPass <= 10
933 || (uPass & 3) == 2)
934 {
935 pgmLock(pVM);
936 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
937 pMmio2 && RT_SUCCESS(rc);
938 pMmio2 = pMmio2->pNextR3)
939 {
940 PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
941 uint8_t const *pbPage = (uint8_t const *)pMmio2->RamRange.pvR3;
942 uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
943 uint32_t iPageLast = cPages;
944 pgmUnlock(pVM);
945
946 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
947 {
948 /* Skip clean pages and pages which hasn't quiesced. */
949 if (!paLSPages[iPage].fDirty)
950 continue;
951 if (paLSPages[iPage].cUnchangedScans < 3)
952 continue;
953 if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
954 continue;
955
956 /* Save it. */
957 bool const fZero = paLSPages[iPage].fZero;
958 uint8_t abPage[PAGE_SIZE];
959 if (!fZero)
960 {
961 memcpy(abPage, pbPage, PAGE_SIZE);
962 RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
963 }
964
965 uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
966 if (iPage != 0 && iPage == iPageLast + 1)
967 rc = SSMR3PutU8(pSSM, u8Type);
968 else
969 {
970 SSMR3PutU8(pSSM, u8Type | PGM_STATE_REC_FLAG_ADDR);
971 SSMR3PutU8(pSSM, pMmio2->idSavedState);
972 rc = SSMR3PutU32(pSSM, iPage);
973 }
974 if (u8Type == PGM_STATE_REC_MMIO2_RAW)
975 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
976 if (RT_FAILURE(rc))
977 break;
978
979 /* Housekeeping. */
980 paLSPages[iPage].fDirty = false;
981 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
982 pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
983 if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
984 pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
985 pVM->pgm.s.LiveSave.cSavedPages++;
986 iPageLast = iPage;
987 }
988
989 pgmLock(pVM);
990 }
991 pgmUnlock(pVM);
992 }
993
994 return rc;
995}
996
997
998/**
999 * Cleans up MMIO2 pages after a live save.
1000 *
1001 * @param pVM The VM handle.
1002 */
1003static void pgmR3DoneMmio2Pages(PVM pVM)
1004{
1005 /*
1006 * Free the tracking structures for the MMIO2 pages.
1007 * We do the freeing outside the lock in case the VM is running.
1008 */
1009 pgmLock(pVM);
1010 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
1011 {
1012 void *pvMmio2ToFree = pMmio2->paLSPages;
1013 if (pvMmio2ToFree)
1014 {
1015 pMmio2->paLSPages = NULL;
1016 pgmUnlock(pVM);
1017 MMR3HeapFree(pvMmio2ToFree);
1018 pgmLock(pVM);
1019 }
1020 }
1021 pgmUnlock(pVM);
1022}
1023
1024
1025/**
1026 * Prepares the RAM pages for a live save.
1027 *
1028 * @returns VBox status code.
1029 * @param pVM The VM handle.
1030 */
1031static int pgmR3PrepRamPages(PVM pVM)
1032{
1033
1034 /*
1035 * Try allocating tracking structures for the ram ranges.
1036 *
1037 * To avoid lock contention, we leave the lock every time we're allocating
1038 * a new array. This means we'll have to ditch the allocation and start
1039 * all over again if the RAM range list changes in-between.
1040 *
1041 * Note! pgmR3SaveDone will always be called and it is therefore responsible
1042 * for cleaning up.
1043 */
1044 PPGMRAMRANGE pCur;
1045 pgmLock(pVM);
1046 do
1047 {
1048 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1049 {
1050 if ( !pCur->paLSPages
1051 && !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1052 {
1053 uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1054 uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1055 pgmUnlock(pVM);
1056 PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1057 if (!paLSPages)
1058 return VERR_NO_MEMORY;
1059 pgmLock(pVM);
1060 if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1061 {
1062 pgmUnlock(pVM);
1063 MMR3HeapFree(paLSPages);
1064 pgmLock(pVM);
1065 break; /* try again */
1066 }
1067 pCur->paLSPages = paLSPages;
1068
1069 /*
1070 * Initialize the array.
1071 */
1072 uint32_t iPage = cPages;
1073 while (iPage-- > 0)
1074 {
1075 /** @todo yield critsect! (after moving this away from EMT0) */
1076 PCPGMPAGE pPage = &pCur->aPages[iPage];
1077 paLSPages[iPage].cDirtied = 0;
1078 paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1079 paLSPages[iPage].fWriteMonitored = 0;
1080 paLSPages[iPage].fWriteMonitoredJustNow = 0;
1081 paLSPages[iPage].u2Reserved = 0;
1082 switch (PGM_PAGE_GET_TYPE(pPage))
1083 {
1084 case PGMPAGETYPE_RAM:
1085 if ( PGM_PAGE_IS_ZERO(pPage)
1086 || PGM_PAGE_IS_BALLOONED(pPage))
1087 {
1088 paLSPages[iPage].fZero = 1;
1089 paLSPages[iPage].fShared = 0;
1090#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1091 paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1092#endif
1093 }
1094 else if (PGM_PAGE_IS_SHARED(pPage))
1095 {
1096 paLSPages[iPage].fZero = 0;
1097 paLSPages[iPage].fShared = 1;
1098#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1099 paLSPages[iPage].u32Crc = UINT32_MAX;
1100#endif
1101 }
1102 else
1103 {
1104 paLSPages[iPage].fZero = 0;
1105 paLSPages[iPage].fShared = 0;
1106#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1107 paLSPages[iPage].u32Crc = UINT32_MAX;
1108#endif
1109 }
1110 paLSPages[iPage].fIgnore = 0;
1111 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1112 break;
1113
1114 case PGMPAGETYPE_ROM_SHADOW:
1115 case PGMPAGETYPE_ROM:
1116 {
1117 paLSPages[iPage].fZero = 0;
1118 paLSPages[iPage].fShared = 0;
1119 paLSPages[iPage].fDirty = 0;
1120 paLSPages[iPage].fIgnore = 1;
1121#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1122 paLSPages[iPage].u32Crc = UINT32_MAX;
1123#endif
1124 pVM->pgm.s.LiveSave.cIgnoredPages++;
1125 break;
1126 }
1127
1128 default:
1129 AssertMsgFailed(("%R[pgmpage]", pPage));
1130 case PGMPAGETYPE_MMIO2:
1131 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1132 paLSPages[iPage].fZero = 0;
1133 paLSPages[iPage].fShared = 0;
1134 paLSPages[iPage].fDirty = 0;
1135 paLSPages[iPage].fIgnore = 1;
1136#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1137 paLSPages[iPage].u32Crc = UINT32_MAX;
1138#endif
1139 pVM->pgm.s.LiveSave.cIgnoredPages++;
1140 break;
1141
1142 case PGMPAGETYPE_MMIO:
1143 paLSPages[iPage].fZero = 0;
1144 paLSPages[iPage].fShared = 0;
1145 paLSPages[iPage].fDirty = 0;
1146 paLSPages[iPage].fIgnore = 1;
1147#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1148 paLSPages[iPage].u32Crc = UINT32_MAX;
1149#endif
1150 pVM->pgm.s.LiveSave.cIgnoredPages++;
1151 break;
1152 }
1153 }
1154 }
1155 }
1156 } while (pCur);
1157 pgmUnlock(pVM);
1158
1159 return VINF_SUCCESS;
1160}
1161
1162
1163/**
1164 * Saves the RAM configuration.
1165 *
1166 * @returns VBox status code.
1167 * @param pVM The VM handle.
1168 * @param pSSM The saved state handle.
1169 */
1170static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1171{
1172 uint32_t cbRamHole = 0;
1173 int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1174 AssertRCReturn(rc, rc);
1175
1176 uint64_t cbRam = 0;
1177 rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1178 AssertRCReturn(rc, rc);
1179
1180 SSMR3PutU32(pSSM, cbRamHole);
1181 return SSMR3PutU64(pSSM, cbRam);
1182}
1183
1184
1185/**
1186 * Loads and verifies the RAM configuration.
1187 *
1188 * @returns VBox status code.
1189 * @param pVM The VM handle.
1190 * @param pSSM The saved state handle.
1191 */
1192static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1193{
1194 uint32_t cbRamHoleCfg = 0;
1195 int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1196 AssertRCReturn(rc, rc);
1197
1198 uint64_t cbRamCfg = 0;
1199 rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1200 AssertRCReturn(rc, rc);
1201
1202 uint32_t cbRamHoleSaved;
1203 SSMR3GetU32(pSSM, &cbRamHoleSaved);
1204
1205 uint64_t cbRamSaved;
1206 rc = SSMR3GetU64(pSSM, &cbRamSaved);
1207 AssertRCReturn(rc, rc);
1208
1209 if ( cbRamHoleCfg != cbRamHoleSaved
1210 || cbRamCfg != cbRamSaved)
1211 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1212 cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1213 return VINF_SUCCESS;
1214}
1215
1216#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1217
1218/**
1219 * Calculates the CRC-32 for a RAM page and updates the live save page tracking
1220 * info with it.
1221 *
1222 * @param pVM The VM handle.
1223 * @param pCur The current RAM range.
1224 * @param paLSPages The current array of live save page tracking
1225 * structures.
1226 * @param iPage The page index.
1227 */
1228static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1229{
1230 RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1231 void const *pvPage;
1232 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1233 if (RT_SUCCESS(rc))
1234 paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1235 else
1236 paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1237}
1238
1239
1240/**
1241 * Verifies the CRC-32 for a page given it's raw bits.
1242 *
1243 * @param pvPage The page bits.
1244 * @param pCur The current RAM range.
1245 * @param paLSPages The current array of live save page tracking
1246 * structures.
1247 * @param iPage The page index.
1248 */
1249static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1250{
1251 if (paLSPages[iPage].u32Crc != UINT32_MAX)
1252 {
1253 uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1254 Assert( ( !PGM_PAGE_IS_ZERO(&pCur->aPages[iPage])
1255 && !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]))
1256 || u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1257 AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1258 ("%08x != %08x for %RGp %R[pgmpage] %s\n", paLSPages[iPage].u32Crc, u32Crc,
1259 pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage], pszWhere));
1260 }
1261}
1262
1263
1264/**
1265 * Verfies the CRC-32 for a RAM page.
1266 *
1267 * @param pVM The VM handle.
1268 * @param pCur The current RAM range.
1269 * @param paLSPages The current array of live save page tracking
1270 * structures.
1271 * @param iPage The page index.
1272 */
1273static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1274{
1275 if (paLSPages[iPage].u32Crc != UINT32_MAX)
1276 {
1277 RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1278 void const *pvPage;
1279 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1280 if (RT_SUCCESS(rc))
1281 pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage, pszWhere);
1282 }
1283}
1284
1285#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1286
1287/**
1288 * Scan for RAM page modifications and reprotect them.
1289 *
1290 * @param pVM The VM handle.
1291 * @param fFinalPass Whether this is the final pass or not.
1292 */
1293static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1294{
1295 /*
1296 * The RAM.
1297 */
1298 RTGCPHYS GCPhysCur = 0;
1299 PPGMRAMRANGE pCur;
1300 pgmLock(pVM);
1301 do
1302 {
1303 uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1304 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1305 {
1306 if ( pCur->GCPhysLast > GCPhysCur
1307 && !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1308 {
1309 PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1310 uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1311 uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1312 GCPhysCur = 0;
1313 for (; iPage < cPages; iPage++)
1314 {
1315 /* Do yield first. */
1316 if ( !fFinalPass
1317#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1318 && (iPage & 0x7ff) == 0x100
1319#endif
1320 && PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1321 && pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1322 {
1323 GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1324 break; /* restart */
1325 }
1326
1327 /* Skip already ignored pages. */
1328 if (paLSPages[iPage].fIgnore)
1329 continue;
1330
1331 if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1332 {
1333 /*
1334 * A RAM page.
1335 */
1336 switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1337 {
1338 case PGM_PAGE_STATE_ALLOCATED:
1339 /** @todo Optimize this: Don't always re-enable write
1340 * monitoring if the page is known to be very busy. */
1341 if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1342 {
1343 Assert(paLSPages[iPage].fWriteMonitored);
1344 PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1345 Assert(pVM->pgm.s.cWrittenToPages > 0);
1346 pVM->pgm.s.cWrittenToPages--;
1347 }
1348 else
1349 {
1350 Assert(!paLSPages[iPage].fWriteMonitored);
1351 pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1352 }
1353
1354 if (!paLSPages[iPage].fDirty)
1355 {
1356 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1357 if (paLSPages[iPage].fZero)
1358 pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1359 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1360 if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1361 paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1362 }
1363
1364 PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1365 pVM->pgm.s.cMonitoredPages++;
1366 paLSPages[iPage].fWriteMonitored = 1;
1367 paLSPages[iPage].fWriteMonitoredJustNow = 1;
1368 paLSPages[iPage].fDirty = 1;
1369 paLSPages[iPage].fZero = 0;
1370 paLSPages[iPage].fShared = 0;
1371#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1372 paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1373#endif
1374 break;
1375
1376 case PGM_PAGE_STATE_WRITE_MONITORED:
1377 Assert(paLSPages[iPage].fWriteMonitored);
1378 if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1379 {
1380#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1381 if (paLSPages[iPage].fWriteMonitoredJustNow)
1382 pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1383 else
1384 pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "scan");
1385#endif
1386 paLSPages[iPage].fWriteMonitoredJustNow = 0;
1387 }
1388 else
1389 {
1390 paLSPages[iPage].fWriteMonitoredJustNow = 1;
1391#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1392 paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1393#endif
1394 if (!paLSPages[iPage].fDirty)
1395 {
1396 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1397 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1398 if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1399 paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1400 }
1401 }
1402 break;
1403
1404 case PGM_PAGE_STATE_ZERO:
1405 if (!paLSPages[iPage].fZero)
1406 {
1407 if (!paLSPages[iPage].fDirty)
1408 {
1409 paLSPages[iPage].fDirty = 1;
1410 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1411 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1412 }
1413 paLSPages[iPage].fZero = 1;
1414 paLSPages[iPage].fShared = 0;
1415#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1416 paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1417#endif
1418 }
1419 break;
1420
1421 case PGM_PAGE_STATE_BALLOONED:
1422 if (!paLSPages[iPage].fZero)
1423 {
1424 if (!paLSPages[iPage].fDirty)
1425 {
1426 paLSPages[iPage].fDirty = 1;
1427 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1428 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1429 }
1430 paLSPages[iPage].fZero = 1;
1431 paLSPages[iPage].fShared = 0;
1432#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1433 paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1434#endif
1435 }
1436 break;
1437
1438 case PGM_PAGE_STATE_SHARED:
1439 if (!paLSPages[iPage].fShared)
1440 {
1441 if (!paLSPages[iPage].fDirty)
1442 {
1443 paLSPages[iPage].fDirty = 1;
1444 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1445 if (paLSPages[iPage].fZero)
1446 pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1447 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1448 }
1449 paLSPages[iPage].fZero = 0;
1450 paLSPages[iPage].fShared = 1;
1451#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1452 pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1453#endif
1454 }
1455 break;
1456 }
1457 }
1458 else
1459 {
1460 /*
1461 * All other types => Ignore the page.
1462 */
1463 Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1464 paLSPages[iPage].fIgnore = 1;
1465 if (paLSPages[iPage].fWriteMonitored)
1466 {
1467 /** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1468 * pages! */
1469 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1470 {
1471 AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1472 PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1473 Assert(pVM->pgm.s.cMonitoredPages > 0);
1474 pVM->pgm.s.cMonitoredPages--;
1475 }
1476 if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1477 {
1478 PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1479 Assert(pVM->pgm.s.cWrittenToPages > 0);
1480 pVM->pgm.s.cWrittenToPages--;
1481 }
1482 pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1483 }
1484
1485 /** @todo the counting doesn't quite work out here. fix later? */
1486 if (paLSPages[iPage].fDirty)
1487 pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1488 else
1489 {
1490 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1491 if (paLSPages[iPage].fZero)
1492 pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1493 }
1494 pVM->pgm.s.LiveSave.cIgnoredPages++;
1495 }
1496 } /* for each page in range */
1497
1498 if (GCPhysCur != 0)
1499 break; /* Yield + ramrange change */
1500 GCPhysCur = pCur->GCPhysLast;
1501 }
1502 } /* for each range */
1503 } while (pCur);
1504 pgmUnlock(pVM);
1505}
1506
1507
1508/**
1509 * Save quiescent RAM pages.
1510 *
1511 * @returns VBox status code.
1512 * @param pVM The VM handle.
1513 * @param pSSM The SSM handle.
1514 * @param fLiveSave Whether it's a live save or not.
1515 * @param uPass The pass number.
1516 */
1517static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1518{
1519 /*
1520 * The RAM.
1521 */
1522 RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1523 RTGCPHYS GCPhysCur = 0;
1524 PPGMRAMRANGE pCur;
1525 bool fFTMDeltaSaveActive = FTMIsDeltaLoadSaveActive(pVM);
1526
1527 pgmLock(pVM);
1528 do
1529 {
1530 uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1531 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1532 {
1533 if ( pCur->GCPhysLast > GCPhysCur
1534 && !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1535 {
1536 PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1537 uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1538 uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1539 GCPhysCur = 0;
1540 for (; iPage < cPages; iPage++)
1541 {
1542 /* Do yield first. */
1543 if ( uPass != SSM_PASS_FINAL
1544 && (iPage & 0x7ff) == 0x100
1545 && PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1546 && pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1547 {
1548 GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1549 break; /* restart */
1550 }
1551
1552 PPGMPAGE pCurPage = &pCur->aPages[iPage];
1553
1554 /*
1555 * Only save pages that haven't changed since last scan and are dirty.
1556 */
1557 if ( uPass != SSM_PASS_FINAL
1558 && paLSPages)
1559 {
1560 if (!paLSPages[iPage].fDirty)
1561 continue;
1562 if (paLSPages[iPage].fWriteMonitoredJustNow)
1563 continue;
1564 if (paLSPages[iPage].fIgnore)
1565 continue;
1566 if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM) /* in case of recent remappings */
1567 continue;
1568 if ( PGM_PAGE_GET_STATE(pCurPage)
1569 != ( paLSPages[iPage].fZero
1570 ? PGM_PAGE_STATE_ZERO
1571 : paLSPages[iPage].fShared
1572 ? PGM_PAGE_STATE_SHARED
1573 : PGM_PAGE_STATE_WRITE_MONITORED))
1574 continue;
1575 if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1576 continue;
1577 }
1578 else
1579 {
1580 if ( paLSPages
1581 && !paLSPages[iPage].fDirty
1582 && !paLSPages[iPage].fIgnore)
1583 {
1584#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1585 if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1586 pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#1");
1587#endif
1588 continue;
1589 }
1590 if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1591 continue;
1592 }
1593
1594 /*
1595 * Do the saving outside the PGM critsect since SSM may block on I/O.
1596 */
1597 int rc;
1598 RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1599 bool fZero = PGM_PAGE_IS_ZERO(pCurPage) || PGM_PAGE_IS_BALLOONED(pCurPage);
1600
1601 if (!fZero)
1602 {
1603 /*
1604 * Copy the page and then save it outside the lock (since any
1605 * SSM call may block).
1606 */
1607 uint8_t abPage[PAGE_SIZE];
1608 void const *pvPage;
1609 rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pCurPage, GCPhys, &pvPage);
1610 if (RT_SUCCESS(rc))
1611 {
1612 memcpy(abPage, pvPage, PAGE_SIZE);
1613#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1614 if (paLSPages)
1615 pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage, "save#3");
1616#endif
1617 }
1618 pgmUnlock(pVM);
1619 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1620
1621 /* Try save some memory when restoring. */
1622 if (!ASMMemIsZeroPage(pvPage))
1623 {
1624 if (fFTMDeltaSaveActive)
1625 {
1626 if ( PGM_PAGE_IS_WRITTEN_TO(pCurPage)
1627 || PGM_PAGE_IS_FT_DIRTY(pCurPage))
1628 {
1629 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW | PGM_STATE_REC_FLAG_ADDR);
1630 SSMR3PutGCPhys(pSSM, GCPhys);
1631 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1632 PGM_PAGE_CLEAR_WRITTEN_TO(pCurPage);
1633 PGM_PAGE_CLEAR_FT_DIRTY(pCurPage);
1634 }
1635 /* else nothing changed, so skip it. */
1636 }
1637 else
1638 {
1639 if (GCPhys == GCPhysLast + PAGE_SIZE)
1640 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1641 else
1642 {
1643 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW | PGM_STATE_REC_FLAG_ADDR);
1644 SSMR3PutGCPhys(pSSM, GCPhys);
1645 }
1646 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1647 }
1648 }
1649 else
1650 {
1651 if (GCPhys == GCPhysLast + PAGE_SIZE)
1652 rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1653 else
1654 {
1655 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO | PGM_STATE_REC_FLAG_ADDR);
1656 rc = SSMR3PutGCPhys(pSSM, GCPhys);
1657 }
1658 }
1659 }
1660 else
1661 {
1662 /*
1663 * Dirty zero page.
1664 */
1665#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1666 if (paLSPages)
1667 pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#2");
1668#endif
1669 pgmUnlock(pVM);
1670
1671 if (GCPhys == GCPhysLast + PAGE_SIZE)
1672 rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1673 else
1674 {
1675 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO | PGM_STATE_REC_FLAG_ADDR);
1676 rc = SSMR3PutGCPhys(pSSM, GCPhys);
1677 }
1678 }
1679 if (RT_FAILURE(rc))
1680 return rc;
1681
1682 pgmLock(pVM);
1683 GCPhysLast = GCPhys;
1684 if (paLSPages)
1685 {
1686 paLSPages[iPage].fDirty = 0;
1687 pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1688 if (fZero)
1689 pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1690 pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1691 pVM->pgm.s.LiveSave.cSavedPages++;
1692 }
1693 if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1694 {
1695 GCPhysCur = GCPhys | PAGE_OFFSET_MASK;
1696 break; /* restart */
1697 }
1698
1699 } /* for each page in range */
1700
1701 if (GCPhysCur != 0)
1702 break; /* Yield + ramrange change */
1703 GCPhysCur = pCur->GCPhysLast;
1704 }
1705 } /* for each range */
1706 } while (pCur);
1707
1708 pgmUnlock(pVM);
1709
1710 return VINF_SUCCESS;
1711}
1712
1713
1714/**
1715 * Cleans up RAM pages after a live save.
1716 *
1717 * @param pVM The VM handle.
1718 */
1719static void pgmR3DoneRamPages(PVM pVM)
1720{
1721 /*
1722 * Free the tracking arrays and disable write monitoring.
1723 *
1724 * Play nice with the PGM lock in case we're called while the VM is still
1725 * running. This means we have to delay the freeing since we wish to use
1726 * paLSPages as an indicator of which RAM ranges which we need to scan for
1727 * write monitored pages.
1728 */
1729 void *pvToFree = NULL;
1730 PPGMRAMRANGE pCur;
1731 uint32_t cMonitoredPages = 0;
1732 pgmLock(pVM);
1733 do
1734 {
1735 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1736 {
1737 if (pCur->paLSPages)
1738 {
1739 if (pvToFree)
1740 {
1741 uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1742 pgmUnlock(pVM);
1743 MMR3HeapFree(pvToFree);
1744 pvToFree = NULL;
1745 pgmLock(pVM);
1746 if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1747 break; /* start over again. */
1748 }
1749
1750 pvToFree = pCur->paLSPages;
1751 pCur->paLSPages = NULL;
1752
1753 uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1754 while (iPage--)
1755 {
1756 PPGMPAGE pPage = &pCur->aPages[iPage];
1757 PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1758 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1759 {
1760 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1761 cMonitoredPages++;
1762 }
1763 }
1764 }
1765 }
1766 } while (pCur);
1767
1768 Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1769 if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1770 pVM->pgm.s.cMonitoredPages = 0;
1771 else
1772 pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1773
1774 pgmUnlock(pVM);
1775
1776 MMR3HeapFree(pvToFree);
1777 pvToFree = NULL;
1778}
1779
1780
1781/**
1782 * Execute a live save pass.
1783 *
1784 * @returns VBox status code.
1785 *
1786 * @param pVM The VM handle.
1787 * @param pSSM The SSM handle.
1788 */
1789static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1790{
1791 int rc;
1792
1793 /*
1794 * Save the MMIO2 and ROM range IDs in pass 0.
1795 */
1796 if (uPass == 0)
1797 {
1798 rc = pgmR3SaveRamConfig(pVM, pSSM);
1799 if (RT_FAILURE(rc))
1800 return rc;
1801 rc = pgmR3SaveRomRanges(pVM, pSSM);
1802 if (RT_FAILURE(rc))
1803 return rc;
1804 rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1805 if (RT_FAILURE(rc))
1806 return rc;
1807 }
1808 /*
1809 * Reset the page-per-second estimate to avoid inflation by the initial
1810 * load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1811 */
1812 else if (uPass == 7)
1813 {
1814 pVM->pgm.s.LiveSave.cSavedPages = 0;
1815 pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1816 }
1817
1818 /*
1819 * Do the scanning.
1820 */
1821 pgmR3ScanRomPages(pVM);
1822 pgmR3ScanMmio2Pages(pVM, uPass);
1823 pgmR3ScanRamPages(pVM, false /*fFinalPass*/);
1824 pgmR3PoolClearAll(pVM, true /*fFlushRemTlb*/); /** @todo this could perhaps be optimized a bit. */
1825
1826 /*
1827 * Save the pages.
1828 */
1829 if (uPass == 0)
1830 rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /*fLiveSave*/);
1831 else
1832 rc = VINF_SUCCESS;
1833 if (RT_SUCCESS(rc))
1834 rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /*fLiveSave*/, false /*fFinalPass*/);
1835 if (RT_SUCCESS(rc))
1836 rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /*fLiveSave*/, uPass);
1837 if (RT_SUCCESS(rc))
1838 rc = pgmR3SaveRamPages( pVM, pSSM, true /*fLiveSave*/, uPass);
1839 SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes care of it.) */
1840
1841 return rc;
1842}
1843
1844
1845/**
1846 * Votes on whether the live save phase is done or not.
1847 *
1848 * @returns VBox status code.
1849 *
1850 * @param pVM The VM handle.
1851 * @param pSSM The SSM handle.
1852 * @param uPass The data pass.
1853 */
1854static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1855{
1856 /*
1857 * Update and calculate parameters used in the decision making.
1858 */
1859 const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1860
1861 /* update history. */
1862 pgmLock(pVM);
1863 uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1864 pgmUnlock(pVM);
1865 uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1866 + pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1867 + pVM->pgm.s.LiveSave.Ram.cDirtyPages
1868 + cWrittenToPages;
1869 uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1870 pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1871 pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1872
1873 /* calc shortterm average (4 passes). */
1874 AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1875 uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1876 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1877 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1878 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1879 uint32_t const cDirtyPagesShort = cTotal / 4;
1880 pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1881
1882 /* calc longterm average. */
1883 cTotal = 0;
1884 if (uPass < cHistoryEntries)
1885 for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1886 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1887 else
1888 for (i = 0; i < cHistoryEntries; i++)
1889 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1890 uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1891 pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1892
1893 /* estimate the speed */
1894 uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1895 uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1896 / ((long double)cNsElapsed / 1000000000.0) );
1897 pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1898
1899 /*
1900 * Try make a decision.
1901 */
1902 if ( cDirtyPagesShort <= cDirtyPagesLong
1903 && ( cDirtyNow <= cDirtyPagesShort
1904 || cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1905 )
1906 )
1907 {
1908 if (uPass > 10)
1909 {
1910 uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1911 uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1912 uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1913 if (cMsMaxDowntime < 32)
1914 cMsMaxDowntime = 32;
1915 if ( ( cMsLeftLong <= cMsMaxDowntime
1916 && cMsLeftShort < cMsMaxDowntime)
1917 || cMsLeftShort < cMsMaxDowntime / 2
1918 )
1919 {
1920 Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u|%ums cDirtyPagesLong=%u|%ums cMsMaxDowntime=%u\n",
1921 uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1922 return VINF_SUCCESS;
1923 }
1924 }
1925 else
1926 {
1927 if ( ( cDirtyPagesShort <= 128
1928 && cDirtyPagesLong <= 1024)
1929 || cDirtyPagesLong <= 256
1930 )
1931 {
1932 Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1933 return VINF_SUCCESS;
1934 }
1935 }
1936 }
1937
1938 /*
1939 * Come up with a completion percentage. Currently this is a simple
1940 * dirty page (long term) vs. total pages ratio + some pass trickery.
1941 */
1942 unsigned uPctDirty = (unsigned)( (long double)cDirtyPagesLong
1943 / (pVM->pgm.s.cAllPages - pVM->pgm.s.LiveSave.cIgnoredPages - pVM->pgm.s.cZeroPages) );
1944 if (uPctDirty <= 100)
1945 SSMR3HandleReportLivePercent(pSSM, RT_MIN(100 - uPctDirty, uPass * 2));
1946 else
1947 AssertMsgFailed(("uPctDirty=%u cDirtyPagesLong=%#x cAllPages=%#x cIgnoredPages=%#x cZeroPages=%#x\n",
1948 uPctDirty, cDirtyPagesLong, pVM->pgm.s.cAllPages, pVM->pgm.s.LiveSave.cIgnoredPages, pVM->pgm.s.cZeroPages));
1949
1950 return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1951}
1952
1953
1954/**
1955 * Prepare for a live save operation.
1956 *
1957 * This will attempt to allocate and initialize the tracking structures. It
1958 * will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1959 * pgmR3SaveDone will do the cleanups.
1960 *
1961 * @returns VBox status code.
1962 *
1963 * @param pVM The VM handle.
1964 * @param pSSM The SSM handle.
1965 */
1966static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1967{
1968 /*
1969 * Indicate that we will be using the write monitoring.
1970 */
1971 pgmLock(pVM);
1972 /** @todo find a way of mediating this when more users are added. */
1973 if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1974 {
1975 pgmUnlock(pVM);
1976 AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1977 }
1978 pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1979 pgmUnlock(pVM);
1980
1981 /*
1982 * Initialize the statistics.
1983 */
1984 pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1985 pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1986 pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1987 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1988 pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1989 pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1990 pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1991 pVM->pgm.s.LiveSave.fActive = true;
1992 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
1993 pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
1994 pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
1995 pVM->pgm.s.LiveSave.cSavedPages = 0;
1996 pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1997 pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
1998
1999 /*
2000 * Per page type.
2001 */
2002 int rc = pgmR3PrepRomPages(pVM);
2003 if (RT_SUCCESS(rc))
2004 rc = pgmR3PrepMmio2Pages(pVM);
2005 if (RT_SUCCESS(rc))
2006 rc = pgmR3PrepRamPages(pVM);
2007 return rc;
2008}
2009
2010
2011/**
2012 * Execute state save operation.
2013 *
2014 * @returns VBox status code.
2015 * @param pVM VM Handle.
2016 * @param pSSM SSM operation handle.
2017 */
2018static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2019{
2020 int rc;
2021 unsigned i;
2022 PPGM pPGM = &pVM->pgm.s;
2023
2024 /*
2025 * Lock PGM and set the no-more-writes indicator.
2026 */
2027 pgmLock(pVM);
2028 pVM->pgm.s.fNoMorePhysWrites = true;
2029
2030 /*
2031 * Save basic data (required / unaffected by relocation).
2032 */
2033 bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
2034 pVM->pgm.s.fMappingsFixed |= pVM->pgm.s.fMappingsFixedRestored;
2035 SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2036 pVM->pgm.s.fMappingsFixed = fMappingsFixed;
2037
2038 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2039 SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]);
2040
2041 /*
2042 * The guest mappings.
2043 */
2044 i = 0;
2045 for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2046 {
2047 SSMR3PutU32( pSSM, i);
2048 SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2049 SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2050 SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2051 }
2052 rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2053
2054 /*
2055 * Save the (remainder of the) memory.
2056 */
2057 if (RT_SUCCESS(rc))
2058 {
2059 if (pVM->pgm.s.LiveSave.fActive)
2060 {
2061 pgmR3ScanRomPages(pVM);
2062 pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2063 pgmR3ScanRamPages(pVM, true /*fFinalPass*/);
2064
2065 rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /*fLiveSave*/, true /*fFinalPass*/);
2066 if (RT_SUCCESS(rc))
2067 rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /*fLiveSave*/, SSM_PASS_FINAL);
2068 if (RT_SUCCESS(rc))
2069 rc = pgmR3SaveRamPages( pVM, pSSM, true /*fLiveSave*/, SSM_PASS_FINAL);
2070 }
2071 else
2072 {
2073 rc = pgmR3SaveRamConfig(pVM, pSSM);
2074 if (RT_SUCCESS(rc))
2075 rc = pgmR3SaveRomRanges(pVM, pSSM);
2076 if (RT_SUCCESS(rc))
2077 rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2078 if (RT_SUCCESS(rc))
2079 rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /*fLiveSave*/);
2080 if (RT_SUCCESS(rc))
2081 rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /*fLiveSave*/, true /*fFinalPass*/);
2082 if (RT_SUCCESS(rc))
2083 rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /*fLiveSave*/, SSM_PASS_FINAL);
2084 if (RT_SUCCESS(rc))
2085 rc = pgmR3SaveRamPages( pVM, pSSM, false /*fLiveSave*/, SSM_PASS_FINAL);
2086 }
2087 SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2088 }
2089
2090 pgmUnlock(pVM);
2091 return rc;
2092}
2093
2094
2095/**
2096 * Cleans up after an save state operation.
2097 *
2098 * @returns VBox status code.
2099 * @param pVM VM Handle.
2100 * @param pSSM SSM operation handle.
2101 */
2102static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2103{
2104 /*
2105 * Do per page type cleanups first.
2106 */
2107 if (pVM->pgm.s.LiveSave.fActive)
2108 {
2109 pgmR3DoneRomPages(pVM);
2110 pgmR3DoneMmio2Pages(pVM);
2111 pgmR3DoneRamPages(pVM);
2112 }
2113
2114 /*
2115 * Clear the live save indicator and disengage write monitoring.
2116 */
2117 pgmLock(pVM);
2118 pVM->pgm.s.LiveSave.fActive = false;
2119 /** @todo this is blindly assuming that we're the only user of write
2120 * monitoring. Fix this when more users are added. */
2121 pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2122 pgmUnlock(pVM);
2123
2124 return VINF_SUCCESS;
2125}
2126
2127
2128/**
2129 * Prepare state load operation.
2130 *
2131 * @returns VBox status code.
2132 * @param pVM VM Handle.
2133 * @param pSSM SSM operation handle.
2134 */
2135static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2136{
2137 /*
2138 * Call the reset function to make sure all the memory is cleared.
2139 */
2140 PGMR3Reset(pVM);
2141 pVM->pgm.s.LiveSave.fActive = false;
2142 NOREF(pSSM);
2143 return VINF_SUCCESS;
2144}
2145
2146
2147/**
2148 * Load an ignored page.
2149 *
2150 * @returns VBox status code.
2151 * @param pSSM The saved state handle.
2152 */
2153static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2154{
2155 uint8_t abPage[PAGE_SIZE];
2156 return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2157}
2158
2159
2160/**
2161 * Loads a page without any bits in the saved state, i.e. making sure it's
2162 * really zero.
2163 *
2164 * @returns VBox status code.
2165 * @param pVM The VM handle.
2166 * @param uType The page type or PGMPAGETYPE_INVALID (old saved
2167 * state).
2168 * @param pPage The guest page tracking structure.
2169 * @param GCPhys The page address.
2170 * @param pRam The ram range (logging).
2171 */
2172static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2173{
2174 if ( PGM_PAGE_GET_TYPE(pPage) != uType
2175 && uType != PGMPAGETYPE_INVALID)
2176 return VERR_SSM_UNEXPECTED_DATA;
2177
2178 /* I think this should be sufficient. */
2179 if ( !PGM_PAGE_IS_ZERO(pPage)
2180 && !PGM_PAGE_IS_BALLOONED(pPage))
2181 return VERR_SSM_UNEXPECTED_DATA;
2182
2183 NOREF(pVM);
2184 NOREF(GCPhys);
2185 NOREF(pRam);
2186 return VINF_SUCCESS;
2187}
2188
2189
2190/**
2191 * Loads a page from the saved state.
2192 *
2193 * @returns VBox status code.
2194 * @param pVM The VM handle.
2195 * @param pSSM The SSM handle.
2196 * @param uType The page type or PGMPAGETYEP_INVALID (old saved
2197 * state).
2198 * @param pPage The guest page tracking structure.
2199 * @param GCPhys The page address.
2200 * @param pRam The ram range (logging).
2201 */
2202static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2203{
2204 /*
2205 * Match up the type, dealing with MMIO2 aliases (dropped).
2206 */
2207 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2208 || uType == PGMPAGETYPE_INVALID,
2209 ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2210 VERR_SSM_UNEXPECTED_DATA);
2211
2212 /*
2213 * Load the page.
2214 */
2215 void *pvPage;
2216 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2217 if (RT_SUCCESS(rc))
2218 rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2219
2220 return rc;
2221}
2222
2223
2224/**
2225 * Loads a page (counter part to pgmR3SavePage).
2226 *
2227 * @returns VBox status code, fully bitched errors.
2228 * @param pVM The VM handle.
2229 * @param pSSM The SSM handle.
2230 * @param uType The page type.
2231 * @param pPage The page.
2232 * @param GCPhys The page address.
2233 * @param pRam The RAM range (for error messages).
2234 */
2235static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2236{
2237 uint8_t uState;
2238 int rc = SSMR3GetU8(pSSM, &uState);
2239 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2240 if (uState == 0 /* zero */)
2241 rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2242 else if (uState == 1)
2243 rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2244 else
2245 rc = VERR_INTERNAL_ERROR;
2246 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2247 pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2248 rc);
2249 return VINF_SUCCESS;
2250}
2251
2252
2253/**
2254 * Loads a shadowed ROM page.
2255 *
2256 * @returns VBox status code, errors are fully bitched.
2257 * @param pVM The VM handle.
2258 * @param pSSM The saved state handle.
2259 * @param pPage The page.
2260 * @param GCPhys The page address.
2261 * @param pRam The RAM range (for error messages).
2262 */
2263static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2264{
2265 /*
2266 * Load and set the protection first, then load the two pages, the first
2267 * one is the active the other is the passive.
2268 */
2269 PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2270 AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2271
2272 uint8_t uProt;
2273 int rc = SSMR3GetU8(pSSM, &uProt);
2274 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2275 PGMROMPROT enmProt = (PGMROMPROT)uProt;
2276 AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2277 && enmProt < PGMROMPROT_END,
2278 ("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2279 VERR_SSM_UNEXPECTED_DATA);
2280
2281 if (pRomPage->enmProt != enmProt)
2282 {
2283 rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2284 AssertLogRelRCReturn(rc, rc);
2285 AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2286 }
2287
2288 PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2289 PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2290 uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2291 uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2292
2293 /** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2294 * used down the line (will the 2nd page will be written to the first
2295 * one because of a false TLB hit since the TLB is using GCPhys and
2296 * doesn't check the HCPhys of the desired page). */
2297 rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2298 if (RT_SUCCESS(rc))
2299 {
2300 *pPageActive = *pPage;
2301 rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2302 }
2303 return rc;
2304}
2305
2306/**
2307 * Ram range flags and bits for older versions of the saved state.
2308 *
2309 * @returns VBox status code.
2310 *
2311 * @param pVM The VM handle
2312 * @param pSSM The SSM handle.
2313 * @param uVersion The saved state version.
2314 */
2315static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2316{
2317 PPGM pPGM = &pVM->pgm.s;
2318
2319 /*
2320 * Ram range flags and bits.
2321 */
2322 uint32_t i = 0;
2323 for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2324 {
2325 /* Check the seqence number / separator. */
2326 uint32_t u32Sep;
2327 int rc = SSMR3GetU32(pSSM, &u32Sep);
2328 if (RT_FAILURE(rc))
2329 return rc;
2330 if (u32Sep == ~0U)
2331 break;
2332 if (u32Sep != i)
2333 {
2334 AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2335 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2336 }
2337 AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2338
2339 /* Get the range details. */
2340 RTGCPHYS GCPhys;
2341 SSMR3GetGCPhys(pSSM, &GCPhys);
2342 RTGCPHYS GCPhysLast;
2343 SSMR3GetGCPhys(pSSM, &GCPhysLast);
2344 RTGCPHYS cb;
2345 SSMR3GetGCPhys(pSSM, &cb);
2346 uint8_t fHaveBits;
2347 rc = SSMR3GetU8(pSSM, &fHaveBits);
2348 if (RT_FAILURE(rc))
2349 return rc;
2350 if (fHaveBits & ~1)
2351 {
2352 AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2353 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2354 }
2355 size_t cchDesc = 0;
2356 char szDesc[256];
2357 szDesc[0] = '\0';
2358 if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2359 {
2360 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2361 if (RT_FAILURE(rc))
2362 return rc;
2363 /* Since we've modified the description strings in r45878, only compare
2364 them if the saved state is more recent. */
2365 if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2366 cchDesc = strlen(szDesc);
2367 }
2368
2369 /*
2370 * Match it up with the current range.
2371 *
2372 * Note there is a hack for dealing with the high BIOS mapping
2373 * in the old saved state format, this means we might not have
2374 * a 1:1 match on success.
2375 */
2376 if ( ( GCPhys != pRam->GCPhys
2377 || GCPhysLast != pRam->GCPhysLast
2378 || cb != pRam->cb
2379 || ( cchDesc
2380 && strcmp(szDesc, pRam->pszDesc)) )
2381 /* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2382 && ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2383 || GCPhys != UINT32_C(0xfff80000)
2384 || GCPhysLast != UINT32_C(0xffffffff)
2385 || pRam->GCPhysLast != GCPhysLast
2386 || pRam->GCPhys < GCPhys
2387 || !fHaveBits)
2388 )
2389 {
2390 LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2391 "State : %RGp-%RGp %RGp bytes %s %s\n",
2392 pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2393 GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2394 /*
2395 * If we're loading a state for debugging purpose, don't make a fuss if
2396 * the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2397 */
2398 if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2399 || GCPhys < 8 * _1M)
2400 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2401 N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2402 GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2403 pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2404
2405 AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2406 continue;
2407 }
2408
2409 uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2410 if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2411 {
2412 /*
2413 * Load the pages one by one.
2414 */
2415 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2416 {
2417 RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2418 PPGMPAGE pPage = &pRam->aPages[iPage];
2419 uint8_t uType;
2420 rc = SSMR3GetU8(pSSM, &uType);
2421 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2422 if (uType == PGMPAGETYPE_ROM_SHADOW)
2423 rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2424 else
2425 rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2426 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2427 }
2428 }
2429 else
2430 {
2431 /*
2432 * Old format.
2433 */
2434
2435 /* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2436 The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2437 uint32_t fFlags = 0;
2438 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2439 {
2440 uint16_t u16Flags;
2441 rc = SSMR3GetU16(pSSM, &u16Flags);
2442 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2443 fFlags |= u16Flags;
2444 }
2445
2446 /* Load the bits */
2447 if ( !fHaveBits
2448 && GCPhysLast < UINT32_C(0xe0000000))
2449 {
2450 /*
2451 * Dynamic chunks.
2452 */
2453 const uint32_t cPagesInChunk = (1*1024*1024) >> PAGE_SHIFT;
2454 AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2455 ("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2456 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2457
2458 for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2459 {
2460 uint8_t fPresent;
2461 rc = SSMR3GetU8(pSSM, &fPresent);
2462 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2463 AssertLogRelMsgReturn(fPresent == (uint8_t)true || fPresent == (uint8_t)false,
2464 ("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2465 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2466
2467 for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2468 {
2469 RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2470 PPGMPAGE pPage = &pRam->aPages[iPage];
2471 if (fPresent)
2472 {
2473 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2474 rc = pgmR3LoadPageToDevNullOld(pSSM);
2475 else
2476 rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2477 }
2478 else
2479 rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2480 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2481 }
2482 }
2483 }
2484 else if (pRam->pvR3)
2485 {
2486 /*
2487 * MMIO2.
2488 */
2489 AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /*MM_RAM_FLAGS_MMIO2*/,
2490 ("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2491 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2492 AssertLogRelMsgReturn(pRam->pvR3,
2493 ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2494 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2495
2496 rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2497 AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2498 }
2499 else if (GCPhysLast < UINT32_C(0xfff80000))
2500 {
2501 /*
2502 * PCI MMIO, no pages saved.
2503 */
2504 }
2505 else
2506 {
2507 /*
2508 * Load the 0xfff80000..0xffffffff BIOS range.
2509 * It starts with X reserved pages that we have to skip over since
2510 * the RAMRANGE create by the new code won't include those.
2511 */
2512 AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /*MM_RAM_FLAGS_MMIO2*/)
2513 && (fFlags & RT_BIT(0) /*MM_RAM_FLAGS_RESERVED*/),
2514 ("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2515 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2516 AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2517 ("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2518 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2519
2520 /* Skip wasted reserved pages before the ROM. */
2521 while (GCPhys < pRam->GCPhys)
2522 {
2523 rc = pgmR3LoadPageToDevNullOld(pSSM);
2524 GCPhys += PAGE_SIZE;
2525 }
2526
2527 /* Load the bios pages. */
2528 cPages = pRam->cb >> PAGE_SHIFT;
2529 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2530 {
2531 RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2532 PPGMPAGE pPage = &pRam->aPages[iPage];
2533
2534 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2535 ("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2536 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2537 rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2538 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2539 }
2540 }
2541 }
2542 }
2543
2544 return VINF_SUCCESS;
2545}
2546
2547
2548/**
2549 * Worker for pgmR3Load and pgmR3LoadLocked.
2550 *
2551 * @returns VBox status code.
2552 *
2553 * @param pVM The VM handle.
2554 * @param pSSM The SSM handle.
2555 * @param uVersion The saved state version.
2556 *
2557 * @todo This needs splitting up if more record types or code twists are
2558 * added...
2559 */
2560static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2561{
2562 /*
2563 * Process page records until we hit the terminator.
2564 */
2565 RTGCPHYS GCPhys = NIL_RTGCPHYS;
2566 PPGMRAMRANGE pRamHint = NULL;
2567 uint8_t id = UINT8_MAX;
2568 uint32_t iPage = UINT32_MAX - 10;
2569 PPGMROMRANGE pRom = NULL;
2570 PPGMMMIO2RANGE pMmio2 = NULL;
2571
2572 /*
2573 * We batch up pages that should be freed instead of calling GMM for
2574 * each and every one of them.
2575 */
2576 uint32_t cPendingPages = 0;
2577 PGMMFREEPAGESREQ pReq;
2578 int rc = GMMR3FreePagesPrepare(pVM, &pReq, 128 /* batch size */, GMMACCOUNT_BASE);
2579 AssertLogRelRCReturn(rc, rc);
2580
2581 for (;;)
2582 {
2583 /*
2584 * Get the record type and flags.
2585 */
2586 uint8_t u8;
2587 rc = SSMR3GetU8(pSSM, &u8);
2588 if (RT_FAILURE(rc))
2589 return rc;
2590 if (u8 == PGM_STATE_REC_END)
2591 {
2592 /*
2593 * Finish off any pages pending freeing.
2594 */
2595 if (cPendingPages)
2596 {
2597 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2598 AssertLogRelRCReturn(rc, rc);
2599 }
2600 GMMR3FreePagesCleanup(pReq);
2601 return VINF_SUCCESS;
2602 }
2603 AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2604 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2605 {
2606 /*
2607 * RAM page.
2608 */
2609 case PGM_STATE_REC_RAM_ZERO:
2610 case PGM_STATE_REC_RAM_RAW:
2611 {
2612 /*
2613 * Get the address and resolve it into a page descriptor.
2614 */
2615 if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2616 GCPhys += PAGE_SIZE;
2617 else
2618 {
2619 rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2620 if (RT_FAILURE(rc))
2621 return rc;
2622 }
2623 AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2624
2625 PPGMPAGE pPage;
2626 rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2627 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2628
2629 /*
2630 * Take action according to the record type.
2631 */
2632 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2633 {
2634 case PGM_STATE_REC_RAM_ZERO:
2635 {
2636 if ( PGM_PAGE_IS_ZERO(pPage)
2637 || PGM_PAGE_IS_BALLOONED(pPage))
2638 break;
2639 AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2640 /* Allocated before (prealloc), so free it now. */
2641 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys);
2642 AssertRC(rc);
2643 break;
2644 }
2645
2646 case PGM_STATE_REC_RAM_RAW:
2647 {
2648 void *pvDstPage;
2649 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2650 AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2651 rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2652 if (RT_FAILURE(rc))
2653 return rc;
2654 break;
2655 }
2656
2657 default:
2658 AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2659 }
2660 id = UINT8_MAX;
2661 break;
2662 }
2663
2664 /*
2665 * MMIO2 page.
2666 */
2667 case PGM_STATE_REC_MMIO2_RAW:
2668 case PGM_STATE_REC_MMIO2_ZERO:
2669 {
2670 /*
2671 * Get the ID + page number and resolved that into a MMIO2 page.
2672 */
2673 if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2674 iPage++;
2675 else
2676 {
2677 SSMR3GetU8(pSSM, &id);
2678 rc = SSMR3GetU32(pSSM, &iPage);
2679 if (RT_FAILURE(rc))
2680 return rc;
2681 }
2682 if ( !pMmio2
2683 || pMmio2->idSavedState != id)
2684 {
2685 for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2686 if (pMmio2->idSavedState == id)
2687 break;
2688 AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2689 }
2690 AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2691 void *pvDstPage = (uint8_t *)pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2692
2693 /*
2694 * Load the page bits.
2695 */
2696 if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2697 ASMMemZeroPage(pvDstPage);
2698 else
2699 {
2700 rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2701 if (RT_FAILURE(rc))
2702 return rc;
2703 }
2704 GCPhys = NIL_RTGCPHYS;
2705 break;
2706 }
2707
2708 /*
2709 * ROM pages.
2710 */
2711 case PGM_STATE_REC_ROM_VIRGIN:
2712 case PGM_STATE_REC_ROM_SHW_RAW:
2713 case PGM_STATE_REC_ROM_SHW_ZERO:
2714 case PGM_STATE_REC_ROM_PROT:
2715 {
2716 /*
2717 * Get the ID + page number and resolved that into a ROM page descriptor.
2718 */
2719 if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2720 iPage++;
2721 else
2722 {
2723 SSMR3GetU8(pSSM, &id);
2724 rc = SSMR3GetU32(pSSM, &iPage);
2725 if (RT_FAILURE(rc))
2726 return rc;
2727 }
2728 if ( !pRom
2729 || pRom->idSavedState != id)
2730 {
2731 for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2732 if (pRom->idSavedState == id)
2733 break;
2734 AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2735 }
2736 AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2737 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2738 GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2739
2740 /*
2741 * Get and set the protection.
2742 */
2743 uint8_t u8Prot;
2744 rc = SSMR3GetU8(pSSM, &u8Prot);
2745 if (RT_FAILURE(rc))
2746 return rc;
2747 PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2748 AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2749
2750 if (enmProt != pRomPage->enmProt)
2751 {
2752 if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2753 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2754 N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2755 GCPhys, enmProt, pRom->pszDesc);
2756 rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2757 AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2758 AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2759 }
2760 if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2761 break; /* done */
2762
2763 /*
2764 * Get the right page descriptor.
2765 */
2766 PPGMPAGE pRealPage;
2767 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2768 {
2769 case PGM_STATE_REC_ROM_VIRGIN:
2770 if (!PGMROMPROT_IS_ROM(enmProt))
2771 pRealPage = &pRomPage->Virgin;
2772 else
2773 pRealPage = NULL;
2774 break;
2775
2776 case PGM_STATE_REC_ROM_SHW_RAW:
2777 case PGM_STATE_REC_ROM_SHW_ZERO:
2778 if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2779 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2780 N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2781 GCPhys, enmProt, pRom->pszDesc);
2782 if (PGMROMPROT_IS_ROM(enmProt))
2783 pRealPage = &pRomPage->Shadow;
2784 else
2785 pRealPage = NULL;
2786 break;
2787
2788 default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2789 }
2790 if (!pRealPage)
2791 {
2792 rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2793 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2794 }
2795
2796 /*
2797 * Make it writable and map it (if necessary).
2798 */
2799 void *pvDstPage = NULL;
2800 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2801 {
2802 case PGM_STATE_REC_ROM_SHW_ZERO:
2803 if ( PGM_PAGE_IS_ZERO(pRealPage)
2804 || PGM_PAGE_IS_BALLOONED(pRealPage))
2805 break;
2806 /** @todo implement zero page replacing. */
2807 /* fall thru */
2808 case PGM_STATE_REC_ROM_VIRGIN:
2809 case PGM_STATE_REC_ROM_SHW_RAW:
2810 {
2811 rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2812 AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2813 break;
2814 }
2815 }
2816
2817 /*
2818 * Load the bits.
2819 */
2820 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2821 {
2822 case PGM_STATE_REC_ROM_SHW_ZERO:
2823 if (pvDstPage)
2824 ASMMemZeroPage(pvDstPage);
2825 break;
2826
2827 case PGM_STATE_REC_ROM_VIRGIN:
2828 case PGM_STATE_REC_ROM_SHW_RAW:
2829 rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2830 if (RT_FAILURE(rc))
2831 return rc;
2832 break;
2833 }
2834 GCPhys = NIL_RTGCPHYS;
2835 break;
2836 }
2837
2838 /*
2839 * Unknown type.
2840 */
2841 default:
2842 AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2843 }
2844 } /* forever */
2845}
2846
2847
2848/**
2849 * Worker for pgmR3Load.
2850 *
2851 * @returns VBox status code.
2852 *
2853 * @param pVM The VM handle.
2854 * @param pSSM The SSM handle.
2855 * @param uVersion The saved state version.
2856 */
2857static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2858{
2859 PPGM pPGM = &pVM->pgm.s;
2860 int rc;
2861 uint32_t u32Sep;
2862
2863 /*
2864 * Load basic data (required / unaffected by relocation).
2865 */
2866 if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2867 {
2868 if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2869 rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2870 else
2871 rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFieldsPreBalloon[0]);
2872
2873 AssertLogRelRCReturn(rc, rc);
2874
2875 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2876 {
2877 rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2878 AssertLogRelRCReturn(rc, rc);
2879 }
2880 }
2881 else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2882 {
2883 AssertRelease(pVM->cCpus == 1);
2884
2885 PGMOLD pgmOld;
2886 rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2887 AssertLogRelRCReturn(rc, rc);
2888
2889 pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2890 pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2891 pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2892
2893 pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2894 pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2895 pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2896 }
2897 else
2898 {
2899 AssertRelease(pVM->cCpus == 1);
2900
2901 SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2902 SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2903 SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2904
2905 uint32_t cbRamSizeIgnored;
2906 rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2907 if (RT_FAILURE(rc))
2908 return rc;
2909 SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2910
2911 uint32_t u32 = 0;
2912 SSMR3GetUInt(pSSM, &u32);
2913 pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2914 SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2915 RTUINT uGuestMode;
2916 SSMR3GetUInt(pSSM, &uGuestMode);
2917 pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2918
2919 /* check separator. */
2920 SSMR3GetU32(pSSM, &u32Sep);
2921 if (RT_FAILURE(rc))
2922 return rc;
2923 if (u32Sep != (uint32_t)~0)
2924 {
2925 AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2926 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2927 }
2928 }
2929
2930 /*
2931 * The guest mappings - skipped now, see re-fixation in the caller.
2932 */
2933 uint32_t i = 0;
2934 for (;; i++)
2935 {
2936 rc = SSMR3GetU32(pSSM, &u32Sep); /* seqence number */
2937 if (RT_FAILURE(rc))
2938 return rc;
2939 if (u32Sep == ~0U)
2940 break;
2941 AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2942
2943 char szDesc[256];
2944 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2945 if (RT_FAILURE(rc))
2946 return rc;
2947 RTGCPTR GCPtrIgnore;
2948 SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
2949 rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
2950 if (RT_FAILURE(rc))
2951 return rc;
2952 }
2953
2954 /*
2955 * Load the RAM contents.
2956 */
2957 if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2958 {
2959 if (!pVM->pgm.s.LiveSave.fActive)
2960 {
2961 if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2962 {
2963 rc = pgmR3LoadRamConfig(pVM, pSSM);
2964 if (RT_FAILURE(rc))
2965 return rc;
2966 }
2967 rc = pgmR3LoadRomRanges(pVM, pSSM);
2968 if (RT_FAILURE(rc))
2969 return rc;
2970 rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2971 if (RT_FAILURE(rc))
2972 return rc;
2973 }
2974
2975 rc = pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2976 }
2977 else
2978 rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2979
2980 /* Refresh balloon accounting. */
2981 if (pVM->pgm.s.cBalloonedPages)
2982 {
2983 rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
2984 AssertRC(rc);
2985 }
2986 return rc;
2987}
2988
2989
2990/**
2991 * Execute state load operation.
2992 *
2993 * @returns VBox status code.
2994 * @param pVM VM Handle.
2995 * @param pSSM SSM operation handle.
2996 * @param uVersion Data layout version.
2997 * @param uPass The data pass.
2998 */
2999static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3000{
3001 int rc;
3002 PPGM pPGM = &pVM->pgm.s;
3003
3004 /*
3005 * Validate version.
3006 */
3007 if ( ( uPass != SSM_PASS_FINAL
3008 && uVersion != PGM_SAVED_STATE_VERSION
3009 && uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3010 && uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3011 || ( uVersion != PGM_SAVED_STATE_VERSION
3012 && uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3013 && uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
3014 && uVersion != PGM_SAVED_STATE_VERSION_3_0_0
3015 && uVersion != PGM_SAVED_STATE_VERSION_2_2_2
3016 && uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
3017 && uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3018 )
3019 {
3020 AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
3021 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3022 }
3023
3024 /*
3025 * Do the loading while owning the lock because a bunch of the functions
3026 * we're using requires this.
3027 */
3028 if (uPass != SSM_PASS_FINAL)
3029 {
3030 pgmLock(pVM);
3031 if (uPass != 0)
3032 rc = pgmR3LoadMemory(pVM, pSSM, uPass);
3033 else
3034 {
3035 pVM->pgm.s.LiveSave.fActive = true;
3036 if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3037 rc = pgmR3LoadRamConfig(pVM, pSSM);
3038 else
3039 rc = VINF_SUCCESS;
3040 if (RT_SUCCESS(rc))
3041 rc = pgmR3LoadRomRanges(pVM, pSSM);
3042 if (RT_SUCCESS(rc))
3043 rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3044 if (RT_SUCCESS(rc))
3045 rc = pgmR3LoadMemory(pVM, pSSM, uPass);
3046 }
3047 pgmUnlock(pVM);
3048 }
3049 else
3050 {
3051 pgmLock(pVM);
3052 rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
3053 pVM->pgm.s.LiveSave.fActive = false;
3054 pgmUnlock(pVM);
3055 if (RT_SUCCESS(rc))
3056 {
3057 /*
3058 * We require a full resync now.
3059 */
3060 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3061 {
3062 PVMCPU pVCpu = &pVM->aCpus[i];
3063 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3064 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3065 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3066 }
3067
3068 pgmR3HandlerPhysicalUpdateAll(pVM);
3069
3070 /*
3071 * Change the paging mode and restore PGMCPU::GCPhysCR3.
3072 * (The latter requires the CPUM state to be restored already.)
3073 */
3074 if (CPUMR3IsStateRestorePending(pVM))
3075 return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3076 N_("PGM was unexpectedly restored before CPUM"));
3077
3078 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3079 {
3080 PVMCPU pVCpu = &pVM->aCpus[i];
3081
3082 rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3083 AssertLogRelRCReturn(rc, rc);
3084
3085 /* Update pVM->pgm.s.GCPhysCR3. */
3086 Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3087 RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3088 if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3089 || pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3090 || pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3091 || pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3092 GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3093 else
3094 GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3095 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3096
3097 /* Update the PSE, NX flags and validity masks. */
3098 pVCpu->pgm.s.fGst32BitPageSizeExtension = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3099 PGMNotifyNxeChanged(pVCpu, CPUMIsGuestNXEnabled(pVCpu));
3100 }
3101
3102 /*
3103 * Try re-fixate the guest mappings.
3104 */
3105 pVM->pgm.s.fMappingsFixedRestored = false;
3106 if ( pVM->pgm.s.fMappingsFixed
3107 && pgmMapAreMappingsEnabled(&pVM->pgm.s))
3108 {
3109 RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
3110 uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
3111 pVM->pgm.s.fMappingsFixed = false;
3112
3113 uint32_t cbRequired;
3114 int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
3115 if ( RT_SUCCESS(rc2)
3116 && cbRequired > cbFixed)
3117 rc2 = VERR_OUT_OF_RANGE;
3118 if (RT_SUCCESS(rc2))
3119 rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
3120 if (RT_FAILURE(rc2))
3121 {
3122 LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
3123 GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
3124 pVM->pgm.s.fMappingsFixed = false;
3125 pVM->pgm.s.fMappingsFixedRestored = true;
3126 pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
3127 pVM->pgm.s.cbMappingFixed = cbFixed;
3128 }
3129 }
3130 else
3131 {
3132 /* We used to set fixed + disabled while we only use disabled now,
3133 so wipe the state to avoid any confusion. */
3134 pVM->pgm.s.fMappingsFixed = false;
3135 pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3136 pVM->pgm.s.cbMappingFixed = 0;
3137 }
3138
3139 /*
3140 * If we have floating mappings, do a CR3 sync now to make sure the HMA
3141 * doesn't conflict with guest code / data and thereby cause trouble
3142 * when restoring other components like PATM.
3143 */
3144 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3145 {
3146 PVMCPU pVCpu = &pVM->aCpus[0];
3147 rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3148 if (RT_FAILURE(rc))
3149 return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3150 N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3151
3152 /* Make sure to re-sync before executing code. */
3153 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3154 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3155 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3156 }
3157 }
3158 }
3159
3160 return rc;
3161}
3162
3163
3164/**
3165 * Registers the saved state callbacks with SSM.
3166 *
3167 * @returns VBox status code.
3168 * @param pVM Pointer to VM structure.
3169 * @param cbRam The RAM size.
3170 */
3171int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3172{
3173 return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3174 pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3175 NULL, pgmR3SaveExec, pgmR3SaveDone,
3176 pgmR3LoadPrep, pgmR3Load, NULL);
3177}
3178
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