PGMMap.cpp@ 12623

Last change on this file since 12623 was 11996, checked in by vboxsync, 16 years ago
PAE+NX = PAE (relevant for testing purposes).
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1	/* $Id: PGMMap.cpp 11996 2008-09-02 16:40:12Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager, Guest Context Mappings.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/dbgf.h>
28	#include <VBox/pgm.h>
29	#include "PGMInternal.h"
30	#include <VBox/vm.h>
31
32	#include <VBox/log.h>
33	#include <VBox/err.h>
34	#include <iprt/asm.h>
35	#include <iprt/assert.h>
36	#include <iprt/string.h>
37
38
39	/*******************************************************************************
40	* Internal Functions *
41	*******************************************************************************/
42	static void pgmR3MapClearPDEs(PPGM pPGM, PPGMMAPPING pMap, unsigned iOldPDE);
43	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
44	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
45	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault);
46
47
48
49	/**
50	* Creates a page table based mapping in GC.
51	*
52	* @returns VBox status code.
53	* @param pVM VM Handle.
54	* @param GCPtr Virtual Address. (Page table aligned!)
55	* @param cb Size of the range. Must be a 4MB aligned!
56	* @param pfnRelocate Relocation callback function.
57	* @param pvUser User argument to the callback.
58	* @param pszDesc Pointer to description string. This must not be freed.
59	*/
60	PGMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc)
61	{
62	LogFlow(("PGMR3MapPT: GCPtr=%#x cb=%d pfnRelocate=%p pvUser=%p pszDesc=%s\n", GCPtr, cb, pfnRelocate, pvUser, pszDesc));
63	AssertMsg(pVM->pgm.s.pInterPD && pVM->pgm.s.pHC32BitPD, ("Paging isn't initialized, init order problems!\n"));
64
65	/*
66	* Validate input.
67	*/
68	if (cb < _2M \|\| cb > 64 * _1M)
69	{
70	AssertMsgFailed(("Serious? cb=%d\n", cb));
71	return VERR_INVALID_PARAMETER;
72	}
73	cb = RT_ALIGN_32(cb, _4M);
74	RTGCPTR GCPtrLast = GCPtr + cb - 1;
75	if (GCPtrLast < GCPtr)
76	{
77	AssertMsgFailed(("Range wraps! GCPtr=%x GCPtrLast=%x\n", GCPtr, GCPtrLast));
78	return VERR_INVALID_PARAMETER;
79	}
80	if (pVM->pgm.s.fMappingsFixed)
81	{
82	AssertMsgFailed(("Mappings are fixed! It's not possible to add new mappings at this time!\n"));
83	return VERR_PGM_MAPPINGS_FIXED;
84	}
85	if (!pfnRelocate)
86	{
87	AssertMsgFailed(("Callback is required\n"));
88	return VERR_INVALID_PARAMETER;
89	}
90
91	/*
92	* Find list location.
93	*/
94	PPGMMAPPING pPrev = NULL;
95	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
96	while (pCur)
97	{
98	if (pCur->GCPtrLast >= GCPtr && pCur->GCPtr <= GCPtrLast)
99	{
100	AssertMsgFailed(("Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
101	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
102	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address is already in use by %s. req %#x-%#x take %#x-%#x\n",
103	pCur->pszDesc, GCPtr, GCPtrLast, pCur->GCPtr, pCur->GCPtrLast));
104	return VERR_PGM_MAPPING_CONFLICT;
105	}
106	if (pCur->GCPtr > GCPtr)
107	break;
108	pPrev = pCur;
109	pCur = pCur->pNextR3;
110	}
111
112	/*
113	* Check for conflicts with intermediate mappings.
114	*/
115	const unsigned iPageDir = GCPtr >> X86_PD_SHIFT;
116	const unsigned cPTs = cb >> X86_PD_SHIFT;
117	unsigned i;
118	for (i = 0; i < cPTs; i++)
119	{
120	if (pVM->pgm.s.pInterPD->a[iPageDir + i].n.u1Present)
121	{
122	AssertMsgFailed(("Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
123	LogRel(("VERR_PGM_MAPPING_CONFLICT: Address %#x is already in use by an intermediate mapping.\n", GCPtr + (i << PAGE_SHIFT)));
124	return VERR_PGM_MAPPING_CONFLICT;
125	}
126	}
127	/** @todo AMD64: add check in PAE structures too, so we can remove all the 32-Bit paging stuff there. */
128
129	/*
130	* Allocate and initialize the new list node.
131	*/
132	PPGMMAPPING pNew;
133	int rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMMAPPING, aPTs[cPTs]), 0, MM_TAG_PGM, (void **)&pNew);
134	if (VBOX_FAILURE(rc))
135	return rc;
136	pNew->GCPtr = GCPtr;
137	pNew->GCPtrLast = GCPtrLast;
138	pNew->cb = cb;
139	pNew->pszDesc = pszDesc;
140	pNew->pfnRelocate = pfnRelocate;
141	pNew->pvUser = pvUser;
142	pNew->cPTs = cPTs;
143
144	/*
145	* Allocate page tables and insert them into the page directories.
146	* (One 32-bit PT and two PAE PTs.)
147	*/
148	uint8_t *pbPTs;
149	rc = MMHyperAlloc(pVM, PAGE_SIZE * 3 * cPTs, PAGE_SIZE, MM_TAG_PGM, (void **)&pbPTs);
150	if (VBOX_FAILURE(rc))
151	{
152	MMHyperFree(pVM, pNew);
153	return VERR_NO_MEMORY;
154	}
155
156	/*
157	* Init the page tables and insert them into the page directories.
158	*/
159	Log4(("PGMR3MapPT: GCPtr=%VGv cPTs=%u pbPTs=%p\n", GCPtr, cPTs, pbPTs));
160	for (i = 0; i < cPTs; i++)
161	{
162	/*
163	* 32-bit.
164	*/
165	pNew->aPTs[i].pPTR3 = (PX86PT)pbPTs;
166	pNew->aPTs[i].pPTGC = MMHyperR3ToRC(pVM, pNew->aPTs[i].pPTR3);
167	pNew->aPTs[i].pPTR0 = MMHyperR3ToR0(pVM, pNew->aPTs[i].pPTR3);
168	pNew->aPTs[i].HCPhysPT = MMR3HyperHCVirt2HCPhys(pVM, pNew->aPTs[i].pPTR3);
169	pbPTs += PAGE_SIZE;
170	Log4(("PGMR3MapPT: i=%d: pPTHC=%p pPTGC=%p HCPhysPT=%RHp\n",
171	i, pNew->aPTs[i].pPTR3, pNew->aPTs[i].pPTGC, pNew->aPTs[i].HCPhysPT));
172
173	/*
174	* PAE.
175	*/
176	pNew->aPTs[i].HCPhysPaePT0 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs);
177	pNew->aPTs[i].HCPhysPaePT1 = MMR3HyperHCVirt2HCPhys(pVM, pbPTs + PAGE_SIZE);
178	pNew->aPTs[i].paPaePTsR3 = (PX86PTPAE)pbPTs;
179	pNew->aPTs[i].paPaePTsGC = MMHyperR3ToRC(pVM, pbPTs);
180	pNew->aPTs[i].paPaePTsR0 = MMHyperR3ToR0(pVM, pbPTs);
181	pbPTs += PAGE_SIZE * 2;
182	Log4(("PGMR3MapPT: i=%d: paPaePTsHC=%p paPaePTsGC=%p HCPhysPaePT0=%RHp HCPhysPaePT1=%RHp\n",
183	i, pNew->aPTs[i].paPaePTsR3, pNew->aPTs[i].paPaePTsGC, pNew->aPTs[i].HCPhysPaePT0, pNew->aPTs[i].HCPhysPaePT1));
184	}
185	pgmR3MapSetPDEs(pVM, pNew, iPageDir);
186
187	/*
188	* Insert the new mapping.
189	*/
190	pNew->pNextR3 = pCur;
191	pNew->pNextGC = pCur ? MMHyperR3ToRC(pVM, pCur) : 0;
192	pNew->pNextR0 = pCur ? MMHyperR3ToR0(pVM, pCur) : 0;
193	if (pPrev)
194	{
195	pPrev->pNextR3 = pNew;
196	pPrev->pNextGC = MMHyperR3ToRC(pVM, pNew);
197	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pNew);
198	}
199	else
200	{
201	pVM->pgm.s.pMappingsR3 = pNew;
202	pVM->pgm.s.pMappingsGC = MMHyperR3ToRC(pVM, pNew);
203	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pNew);
204	}
205
206	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
207	return VINF_SUCCESS;
208	}
209
210
211	/**
212	* Removes a page table based mapping.
213	*
214	* @returns VBox status code.
215	* @param pVM VM Handle.
216	* @param GCPtr Virtual Address. (Page table aligned!)
217	*/
218	PGMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr)
219	{
220	LogFlow(("PGMR3UnmapPT: GCPtr=%#x\n", GCPtr));
221
222	/*
223	* Find it.
224	*/
225	PPGMMAPPING pPrev = NULL;
226	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
227	while (pCur)
228	{
229	if (pCur->GCPtr == GCPtr)
230	{
231	/*
232	* Unlink it.
233	*/
234	if (pPrev)
235	{
236	pPrev->pNextR3 = pCur->pNextR3;
237	pPrev->pNextGC = pCur->pNextGC;
238	pPrev->pNextR0 = pCur->pNextR0;
239	}
240	else
241	{
242	pVM->pgm.s.pMappingsR3 = pCur->pNextR3;
243	pVM->pgm.s.pMappingsGC = pCur->pNextGC;
244	pVM->pgm.s.pMappingsR0 = pCur->pNextR0;
245	}
246
247	/*
248	* Free the page table memory, clear page directory entries
249	* and free the page tables and node memory.
250	*/
251	MMHyperFree(pVM, pCur->aPTs[0].pPTR3);
252	pgmR3MapClearPDEs(&pVM->pgm.s, pCur, pCur->GCPtr >> X86_PD_SHIFT);
253	MMHyperFree(pVM, pCur);
254
255	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
256	return VINF_SUCCESS;
257	}
258
259	/* done? */
260	if (pCur->GCPtr > GCPtr)
261	break;
262
263	/* next */
264	pPrev = pCur;
265	pCur = pCur->pNextR3;
266	}
267
268	AssertMsgFailed(("No mapping for %#x found!\n", GCPtr));
269	return VERR_INVALID_PARAMETER;
270	}
271
272
273	/**
274	* Gets the size of the current guest mappings if they were to be
275	* put next to oneanother.
276	*
277	* @returns VBox status code.
278	* @param pVM The VM.
279	* @param pcb Where to store the size.
280	*/
281	PGMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb)
282	{
283	RTGCUINTPTR cb = 0;
284	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
285	cb += pCur->cb;
286
287	*pcb = cb;
288	AssertReturn(*pcb == cb, VERR_NUMBER_TOO_BIG);
289	Log(("PGMR3MappingsSize: return %d (%#x) bytes\n", cb, cb));
290	return VINF_SUCCESS;
291	}
292
293
294	/**
295	* Fixes the guest context mappings in a range reserved from the Guest OS.
296	*
297	* @returns VBox status code.
298	* @param pVM The VM.
299	* @param GCPtrBase The address of the reserved range of guest memory.
300	* @param cb The size of the range starting at GCPtrBase.
301	*/
302	PGMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb)
303	{
304	Log(("PGMR3MappingsFix: GCPtrBase=%#x cb=%#x\n", GCPtrBase, cb));
305
306	/* Ignore the additions mapping fix call in VT-x/AMD-V. */
307	if ( pVM->pgm.s.fMappingsFixed
308	&& HWACCMR3IsActive(pVM))
309	return VINF_SUCCESS;
310
311	/*
312	* This is all or nothing at all. So, a tiny bit of paranoia first.
313	*/
314	if (GCPtrBase & X86_PAGE_4M_OFFSET_MASK)
315	{
316	AssertMsgFailed(("GCPtrBase (%#x) has to be aligned on a 4MB address!\n", GCPtrBase));
317	return VERR_INVALID_PARAMETER;
318	}
319	if (!cb \|\| (cb & X86_PAGE_4M_OFFSET_MASK))
320	{
321	AssertMsgFailed(("cb (%#x) is 0 or not aligned on a 4MB address!\n", cb));
322	return VERR_INVALID_PARAMETER;
323	}
324
325	/*
326	* Before we do anything we'll do a forced PD sync to try make sure any
327	* pending relocations because of these mappings have been resolved.
328	*/
329	PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), true);
330
331	/*
332	* Check that it's not conflicting with a core code mapping in the intermediate page table.
333	*/
334	unsigned iPDNew = GCPtrBase >> X86_PD_SHIFT;
335	unsigned i = cb >> X86_PD_SHIFT;
336	while (i-- > 0)
337	{
338	if (pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present)
339	{
340	/* Check that it's not one or our mappings. */
341	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
342	while (pCur)
343	{
344	if (iPDNew + i - (pCur->GCPtr >> X86_PD_SHIFT) < (pCur->cb >> X86_PD_SHIFT))
345	break;
346	pCur = pCur->pNextR3;
347	}
348	if (!pCur)
349	{
350	LogRel(("PGMR3MappingsFix: Conflicts with intermediate PDE %#x (GCPtrBase=%VGv cb=%#zx). The guest should retry.\n",
351	iPDNew + i, GCPtrBase, cb));
352	return VERR_PGM_MAPPINGS_FIX_CONFLICT;
353	}
354	}
355	}
356
357	/*
358	* Loop the mappings and check that they all agree on their new locations.
359	*/
360	RTGCPTR GCPtrCur = GCPtrBase;
361	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
362	while (pCur)
363	{
364	if (!pCur->pfnRelocate(pVM, pCur->GCPtr, GCPtrCur, PGMRELOCATECALL_SUGGEST, pCur->pvUser))
365	{
366	AssertMsgFailed(("The suggested fixed address %#x was rejected by '%s'!\n", GCPtrCur, pCur->pszDesc));
367	return VERR_PGM_MAPPINGS_FIX_REJECTED;
368	}
369	/* next */
370	GCPtrCur += pCur->cb;
371	pCur = pCur->pNextR3;
372	}
373	if (GCPtrCur > GCPtrBase + cb)
374	{
375	AssertMsgFailed(("cb (%#x) is less than the required range %#x!\n", cb, GCPtrCur - GCPtrBase));
376	return VERR_PGM_MAPPINGS_FIX_TOO_SMALL;
377	}
378
379	/*
380	* Loop the table assigning the mappings to the passed in memory
381	* and call their relocator callback.
382	*/
383	GCPtrCur = GCPtrBase;
384	pCur = pVM->pgm.s.pMappingsR3;
385	while (pCur)
386	{
387	unsigned iPDOld = pCur->GCPtr >> X86_PD_SHIFT;
388	iPDNew = GCPtrCur >> X86_PD_SHIFT;
389
390	/*
391	* Relocate the page table(s).
392	*/
393	pgmR3MapClearPDEs(&pVM->pgm.s, pCur, iPDOld);
394	pgmR3MapSetPDEs(pVM, pCur, iPDNew);
395
396	/*
397	* Update the entry.
398	*/
399	pCur->GCPtr = GCPtrCur;
400	pCur->GCPtrLast = GCPtrCur + pCur->cb - 1;
401
402	/*
403	* Callback to execute the relocation.
404	*/
405	pCur->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pCur->pvUser);
406
407	/*
408	* Advance.
409	*/
410	GCPtrCur += pCur->cb;
411	pCur = pCur->pNextR3;
412	}
413
414	/*
415	* Turn off CR3 updating monitoring.
416	*/
417	int rc2 = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
418	AssertRC(rc2);
419
420	/*
421	* Mark the mappings as fixed and return.
422	*/
423	pVM->pgm.s.fMappingsFixed = true;
424	pVM->pgm.s.GCPtrMappingFixed = GCPtrBase;
425	pVM->pgm.s.cbMappingFixed = cb;
426	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
427	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
428	return VINF_SUCCESS;
429	}
430
431
432	/**
433	* Unfixes the mappings.
434	* After calling this function mapping conflict detection will be enabled.
435	*
436	* @returns VBox status code.
437	* @param pVM The VM.
438	*/
439	PGMR3DECL(int) PGMR3MappingsUnfix(PVM pVM)
440	{
441	Log(("PGMR3MappingsUnfix: fMappingsFixed=%d\n", pVM->pgm.s.fMappingsFixed));
442
443	/* Refuse in VT-x/AMD-V mode. */
444	if (HWACCMR3IsActive(pVM))
445	return VINF_SUCCESS;
446
447	pVM->pgm.s.fMappingsFixed = false;
448	pVM->pgm.s.GCPtrMappingFixed = 0;
449	pVM->pgm.s.cbMappingFixed = 0;
450	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
451
452	/*
453	* Re-enable the CR3 monitoring.
454	*
455	* Paranoia: We flush the page pool before doing that because Windows
456	* is using the CR3 page both as a PD and a PT, e.g. the pool may
457	* be monitoring it.
458	*/
459	#ifdef PGMPOOL_WITH_MONITORING
460	pgmPoolFlushAll(pVM);
461	#endif
462	/* Remap CR3 as we have just flushed the CR3 shadow PML4 in case we're in long mode. */
463	int rc = PGM_GST_PFN(MapCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
464	AssertRC(rc);
465
466	rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
467	AssertRC(rc);
468
469	return VINF_SUCCESS;
470	}
471
472
473	/**
474	* Map pages into the intermediate context (switcher code).
475	* These pages are mapped at both the give virtual address and at
476	* the physical address (for identity mapping).
477	*
478	* @returns VBox status code.
479	* @param pVM The virtual machine.
480	* @param Addr Intermediate context address of the mapping.
481	* @param HCPhys Start of the range of physical pages. This must be entriely below 4GB!
482	* @param cbPages Number of bytes to map.
483	*
484	* @remark This API shall not be used to anything but mapping the switcher code.
485	*/
486	PGMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages)
487	{
488	LogFlow(("PGMR3MapIntermediate: Addr=%RTptr HCPhys=%VHp cbPages=%#x\n", Addr, HCPhys, cbPages));
489
490	/*
491	* Adjust input.
492	*/
493	cbPages += (uint32_t)HCPhys & PAGE_OFFSET_MASK;
494	cbPages = RT_ALIGN(cbPages, PAGE_SIZE);
495	HCPhys &= X86_PTE_PAE_PG_MASK;
496	Addr &= PAGE_BASE_MASK;
497	/* We only care about the first 4GB, because on AMD64 we'll be repeating them all over the address space. */
498	uint32_t uAddress = (uint32_t)Addr;
499
500	/*
501	* Assert input and state.
502	*/
503	AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
504	AssertMsg(pVM->pgm.s.pInterPD, ("Bad init order, paging.\n"));
505	AssertMsg(cbPages <= (512 << PAGE_SHIFT), ("The mapping is too big %d bytes\n", cbPages));
506	AssertMsg(HCPhys < _4G && HCPhys + cbPages < _4G, ("Addr=%RTptr HCPhys=%VHp cbPages=%d\n", Addr, HCPhys, cbPages));
507
508	/*
509	* Check for internal conflicts between the virtual address and the physical address.
510	*/
511	if ( uAddress != HCPhys
512	&& ( uAddress < HCPhys
513	? HCPhys - uAddress < cbPages
514	: uAddress - HCPhys < cbPages
515	)
516	)
517	AssertLogRelMsgFailedReturn(("Addr=%RTptr HCPhys=%VHp cbPages=%d\n", Addr, HCPhys, cbPages),
518	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
519
520	/* The intermediate mapping must not conflict with our default hypervisor address. */
521	size_t cbHyper;
522	RTGCPTR pvHyperGC = MMHyperGetArea(pVM, &cbHyper);
523	if (uAddress < pvHyperGC
524	? uAddress + cbPages > pvHyperGC
525	: pvHyperGC + cbHyper > uAddress
526	)
527	AssertLogRelMsgFailedReturn(("Addr=%RTptr HyperGC=%VGv cbPages=%zu\n", Addr, pvHyperGC, cbPages),
528	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
529
530	const unsigned cPages = cbPages >> PAGE_SHIFT;
531	int rc = pgmR3MapIntermediateCheckOne(pVM, uAddress, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
532	if (VBOX_FAILURE(rc))
533	return rc;
534	rc = pgmR3MapIntermediateCheckOne(pVM, (uintptr_t)HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
535	if (VBOX_FAILURE(rc))
536	return rc;
537
538	/*
539	* Everythings fine, do the mapping.
540	*/
541	pgmR3MapIntermediateDoOne(pVM, uAddress, HCPhys, cPages, pVM->pgm.s.apInterPTs[0], pVM->pgm.s.apInterPaePTs[0]);
542	pgmR3MapIntermediateDoOne(pVM, (uintptr_t)HCPhys, HCPhys, cPages, pVM->pgm.s.apInterPTs[1], pVM->pgm.s.apInterPaePTs[1]);
543
544	return VINF_SUCCESS;
545	}
546
547
548	/**
549	* Validates that there are no conflicts for this mapping into the intermediate context.
550	*
551	* @returns VBox status code.
552	* @param pVM VM handle.
553	* @param uAddress Address of the mapping.
554	* @param cPages Number of pages.
555	* @param pPTDefault Pointer to the default page table for this mapping.
556	* @param pPTPaeDefault Pointer to the default page table for this mapping.
557	*/
558	static int pgmR3MapIntermediateCheckOne(PVM pVM, uintptr_t uAddress, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
559	{
560	AssertMsg((uAddress >> X86_PD_SHIFT) + cPages <= 1024, ("64-bit fixme\n"));
561
562	/*
563	* Check that the ranges are available.
564	* (This codes doesn't have to be fast.)
565	*/
566	while (cPages > 0)
567	{
568	/*
569	* 32-Bit.
570	*/
571	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
572	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
573	PX86PT pPT = pPTDefault;
574	if (pVM->pgm.s.pInterPD->a[iPDE].u)
575	{
576	RTHCPHYS HCPhysPT = pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK;
577	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]))
578	pPT = pVM->pgm.s.apInterPTs[0];
579	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]))
580	pPT = pVM->pgm.s.apInterPTs[1];
581	else
582	{
583	/** @todo this must be handled with a relocation of the conflicting mapping!
584	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
585	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%VHv\n", uAddress),
586	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
587	}
588	}
589	if (pPT->a[iPTE].u)
590	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%VHv pPT->a[iPTE].u=%RX32\n", iPTE, iPDE, uAddress, pPT->a[iPTE].u),
591	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
592
593	/*
594	* PAE.
595	*/
596	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
597	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
598	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
599	Assert(iPDPE < 4);
600	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
601	PX86PTPAE pPTPae = pPTPaeDefault;
602	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
603	{
604	RTHCPHYS HCPhysPT = pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK;
605	if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
606	pPTPae = pVM->pgm.s.apInterPaePTs[0];
607	else if (HCPhysPT == MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]))
608	pPTPae = pVM->pgm.s.apInterPaePTs[1];
609	else
610	{
611	/** @todo this must be handled with a relocation of the conflicting mapping!
612	* Which of course cannot be done because we're in the middle of the initialization. bad design! */
613	AssertLogRelMsgFailedReturn(("Conflict between core code and PGMR3Mapping(). uAddress=%VHv\n", uAddress),
614	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
615	}
616	}
617	if (pPTPae->a[iPTE].u)
618	AssertLogRelMsgFailedReturn(("Conflict iPTE=%#x iPDE=%#x uAddress=%VHv pPTPae->a[iPTE].u=%#RX64\n", iPTE, iPDE, uAddress, pPTPae->a[iPTE].u),
619	VERR_PGM_INTERMEDIATE_PAGING_CONFLICT);
620
621	/* next */
622	uAddress += PAGE_SIZE;
623	cPages--;
624	}
625
626	return VINF_SUCCESS;
627	}
628
629
630
631	/**
632	* Sets up the intermediate page tables for a verified mapping.
633	*
634	* @param pVM VM handle.
635	* @param uAddress Address of the mapping.
636	* @param HCPhys The physical address of the page range.
637	* @param cPages Number of pages.
638	* @param pPTDefault Pointer to the default page table for this mapping.
639	* @param pPTPaeDefault Pointer to the default page table for this mapping.
640	*/
641	static void pgmR3MapIntermediateDoOne(PVM pVM, uintptr_t uAddress, RTHCPHYS HCPhys, unsigned cPages, PX86PT pPTDefault, PX86PTPAE pPTPaeDefault)
642	{
643	while (cPages > 0)
644	{
645	/*
646	* 32-Bit.
647	*/
648	unsigned iPDE = (uAddress >> X86_PD_SHIFT) & X86_PD_MASK;
649	unsigned iPTE = (uAddress >> X86_PT_SHIFT) & X86_PT_MASK;
650	PX86PT pPT;
651	if (pVM->pgm.s.pInterPD->a[iPDE].u)
652	pPT = (PX86PT)MMPagePhys2Page(pVM, pVM->pgm.s.pInterPD->a[iPDE].u & X86_PDE_PG_MASK);
653	else
654	{
655	pVM->pgm.s.pInterPD->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
656	\| (uint32_t)MMPage2Phys(pVM, pPTDefault);
657	pPT = pPTDefault;
658	}
659	pPT->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| (uint32_t)HCPhys;
660
661	/*
662	* PAE
663	*/
664	const unsigned iPDPE= (uAddress >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
665	iPDE = (uAddress >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
666	iPTE = (uAddress >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK;
667	Assert(iPDPE < 4);
668	Assert(pVM->pgm.s.apInterPaePDs[iPDPE]);
669	PX86PTPAE pPTPae;
670	if (pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u)
671	pPTPae = (PX86PTPAE)MMPagePhys2Page(pVM, pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u & X86_PDE_PAE_PG_MASK);
672	else
673	{
674	pPTPae = pPTPaeDefault;
675	pVM->pgm.s.apInterPaePDs[iPDPE]->a[iPDE].u = X86_PDE_P \| X86_PDE_A \| X86_PDE_RW
676	\| MMPage2Phys(pVM, pPTPaeDefault);
677	}
678	pPTPae->a[iPTE].u = X86_PTE_P \| X86_PTE_RW \| X86_PTE_A \| X86_PTE_D \| HCPhys;
679
680	/* next */
681	cPages--;
682	HCPhys += PAGE_SIZE;
683	uAddress += PAGE_SIZE;
684	}
685	}
686
687
688	/**
689	* Clears all PDEs involved with the mapping.
690	*
691	* @param pPGM Pointer to the PGM instance data.
692	* @param pMap Pointer to the mapping in question.
693	* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
694	*/
695	static void pgmR3MapClearPDEs(PPGM pPGM, PPGMMAPPING pMap, unsigned iOldPDE)
696	{
697	unsigned i = pMap->cPTs;
698	iOldPDE += i;
699	while (i-- > 0)
700	{
701	iOldPDE--;
702
703	/*
704	* 32-bit.
705	*/
706	pPGM->pInterPD->a[iOldPDE].u = 0;
707	pPGM->pHC32BitPD->a[iOldPDE].u = 0;
708
709	/*
710	* PAE.
711	*/
712	const unsigned iPD = iOldPDE / 256;
713	unsigned iPDE = iOldPDE * 2 % 512;
714	pPGM->apInterPaePDs[iPD]->a[iPDE].u = 0;
715	pPGM->apHCPaePDs[iPD]->a[iPDE].u = 0;
716	iPDE++;
717	pPGM->apInterPaePDs[iPD]->a[iPDE].u = 0;
718	pPGM->apHCPaePDs[iPD]->a[iPDE].u = 0;
719
720	/* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode) */
721	pPGM->pHCPaePDPT->a[iPD].u &= ~PGM_PLXFLAGS_MAPPING;
722	}
723	}
724
725
726	/**
727	* Sets all PDEs involved with the mapping.
728	*
729	* @param pVM The VM handle.
730	* @param pMap Pointer to the mapping in question.
731	* @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
732	*/
733	static void pgmR3MapSetPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
734	{
735	PPGM pPGM = &pVM->pgm.s;
736
737	/* If mappings are not supposed to be put in the shadow page table, then this function is a nop. */
738	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
739	return;
740
741	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE_NX);
742
743	/*
744	* Init the page tables and insert them into the page directories.
745	*/
746	unsigned i = pMap->cPTs;
747	iNewPDE += i;
748	while (i-- > 0)
749	{
750	iNewPDE--;
751
752	/*
753	* 32-bit.
754	*/
755	if (pPGM->pHC32BitPD->a[iNewPDE].n.u1Present)
756	pgmPoolFree(pVM, pPGM->pHC32BitPD->a[iNewPDE].u & X86_PDE_PG_MASK, PGMPOOL_IDX_PD, iNewPDE);
757	X86PDE Pde;
758	/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
759	Pde.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT;
760	pPGM->pInterPD->a[iNewPDE] = Pde;
761	pPGM->pHC32BitPD->a[iNewPDE] = Pde;
762
763	/*
764	* PAE.
765	*/
766	const unsigned iPD = iNewPDE / 256;
767	unsigned iPDE = iNewPDE * 2 % 512;
768	if (pPGM->apHCPaePDs[iPD]->a[iPDE].n.u1Present)
769	pgmPoolFree(pVM, pPGM->apHCPaePDs[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2);
770	X86PDEPAE PdePae0;
771	PdePae0.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0;
772	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae0;
773	pPGM->apHCPaePDs[iPD]->a[iPDE] = PdePae0;
774
775	iPDE++;
776	if (pPGM->apHCPaePDs[iPD]->a[iPDE].n.u1Present)
777	pgmPoolFree(pVM, pPGM->apHCPaePDs[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2 + 1);
778	X86PDEPAE PdePae1;
779	PdePae1.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1;
780	pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae1;
781	pPGM->apHCPaePDs[iPD]->a[iPDE] = PdePae1;
782
783	/* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode) */
784	pPGM->pHCPaePDPT->a[iPD].u \|= PGM_PLXFLAGS_MAPPING;
785	}
786	}
787
788	/**
789	* Relocates a mapping to a new address.
790	*
791	* @param pVM VM handle.
792	* @param pMapping The mapping to relocate.
793	* @param GCPtrOldMapping The address of the start of the old mapping.
794	* @param GCPtrNewMapping The address of the start of the new mapping.
795	*/
796	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping)
797	{
798	unsigned iPDOld = GCPtrOldMapping >> X86_PD_SHIFT;
799	unsigned iPDNew = GCPtrNewMapping >> X86_PD_SHIFT;
800
801	Log(("PGM: Relocating %s from %VGv to %VGv\n", pMapping->pszDesc, GCPtrOldMapping, GCPtrNewMapping));
802	Assert(((unsigned)iPDOld << X86_PD_SHIFT) == pMapping->GCPtr);
803
804	/*
805	* Relocate the page table(s).
806	*/
807	pgmR3MapClearPDEs(&pVM->pgm.s, pMapping, iPDOld);
808	pgmR3MapSetPDEs(pVM, pMapping, iPDNew);
809
810	/*
811	* Update and resort the mapping list.
812	*/
813
814	/* Find previous mapping for pMapping, put result into pPrevMap. */
815	PPGMMAPPING pPrevMap = NULL;
816	PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3;
817	while (pCur && pCur != pMapping)
818	{
819	/* next */
820	pPrevMap = pCur;
821	pCur = pCur->pNextR3;
822	}
823	Assert(pCur);
824
825	/* Find mapping which >= than pMapping. */
826	RTGCPTR GCPtrNew = iPDNew << X86_PD_SHIFT;
827	PPGMMAPPING pPrev = NULL;
828	pCur = pVM->pgm.s.pMappingsR3;
829	while (pCur && pCur->GCPtr < GCPtrNew)
830	{
831	/* next */
832	pPrev = pCur;
833	pCur = pCur->pNextR3;
834	}
835
836	if (pCur != pMapping && pPrev != pMapping)
837	{
838	/*
839	* Unlink.
840	*/
841	if (pPrevMap)
842	{
843	pPrevMap->pNextR3 = pMapping->pNextR3;
844	pPrevMap->pNextGC = pMapping->pNextGC;
845	pPrevMap->pNextR0 = pMapping->pNextR0;
846	}
847	else
848	{
849	pVM->pgm.s.pMappingsR3 = pMapping->pNextR3;
850	pVM->pgm.s.pMappingsGC = pMapping->pNextGC;
851	pVM->pgm.s.pMappingsR0 = pMapping->pNextR0;
852	}
853
854	/*
855	* Link
856	*/
857	pMapping->pNextR3 = pCur;
858	if (pPrev)
859	{
860	pMapping->pNextGC = pPrev->pNextGC;
861	pMapping->pNextR0 = pPrev->pNextR0;
862	pPrev->pNextR3 = pMapping;
863	pPrev->pNextGC = MMHyperR3ToRC(pVM, pMapping);
864	pPrev->pNextR0 = MMHyperR3ToR0(pVM, pMapping);
865	}
866	else
867	{
868	pMapping->pNextGC = pVM->pgm.s.pMappingsGC;
869	pMapping->pNextR0 = pVM->pgm.s.pMappingsR0;
870	pVM->pgm.s.pMappingsR3 = pMapping;
871	pVM->pgm.s.pMappingsGC = MMHyperR3ToRC(pVM, pMapping);
872	pVM->pgm.s.pMappingsR0 = MMHyperR3ToR0(pVM, pMapping);
873	}
874	}
875
876	/*
877	* Update the entry.
878	*/
879	pMapping->GCPtr = GCPtrNew;
880	pMapping->GCPtrLast = GCPtrNew + pMapping->cb - 1;
881
882	/*
883	* Callback to execute the relocation.
884	*/
885	pMapping->pfnRelocate(pVM, iPDOld << X86_PD_SHIFT, iPDNew << X86_PD_SHIFT, PGMRELOCATECALL_RELOCATE, pMapping->pvUser);
886	}
887
888
889	/**
890	* Resolves a conflict between a page table based GC mapping and
891	* the Guest OS page tables. (32 bits version)
892	*
893	* @returns VBox status code.
894	* @param pVM VM Handle.
895	* @param pMapping The mapping which conflicts.
896	* @param pPDSrc The page directory of the guest OS.
897	* @param GCPtrOldMapping The address of the start of the current mapping.
898	*/
899	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping)
900	{
901	STAM_PROFILE_START(&pVM->pgm.s.StatHCResolveConflict, a);
902
903	/*
904	* Scan for free page directory entries.
905	*
906	* Note that we do not support mappings at the very end of the
907	* address space since that will break our GCPtrEnd assumptions.
908	*/
909	const unsigned cPTs = pMapping->cPTs;
910	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
911	while (iPDNew-- > 0)
912	{
913	if (pPDSrc->a[iPDNew].n.u1Present)
914	continue;
915	if (cPTs > 1)
916	{
917	bool fOk = true;
918	for (unsigned i = 1; fOk && i < cPTs; i++)
919	if (pPDSrc->a[iPDNew + i].n.u1Present)
920	fOk = false;
921	if (!fOk)
922	continue;
923	}
924
925	/*
926	* Check that it's not conflicting with an intermediate page table mapping.
927	*/
928	bool fOk = true;
929	unsigned i = cPTs;
930	while (fOk && i-- > 0)
931	fOk = !pVM->pgm.s.pInterPD->a[iPDNew + i].n.u1Present;
932	if (!fOk)
933	continue;
934	/** @todo AMD64 should check the PAE directories and skip the 32bit stuff. */
935
936	/*
937	* Ask for the mapping.
938	*/
939	RTGCPTR GCPtrNewMapping = iPDNew << X86_PD_SHIFT;
940
941	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
942	{
943	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
944	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCResolveConflict, a);
945	return VINF_SUCCESS;
946	}
947	}
948
949	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCResolveConflict, a);
950	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, cPTs));
951	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
952	}
953
954	/**
955	* Resolves a conflict between a page table based GC mapping and
956	* the Guest OS page tables. (PAE bits version)
957	*
958	* @returns VBox status code.
959	* @param pVM VM Handle.
960	* @param pMapping The mapping which conflicts.
961	* @param GCPtrOldMapping The address of the start of the current mapping.
962	*/
963	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping)
964	{
965	STAM_PROFILE_START(&pVM->pgm.s.StatHCResolveConflict, a);
966
967	for (unsigned iPDPTE = X86_PG_PAE_PDPE_ENTRIES - 1; iPDPTE >= 0; iPDPTE--)
968	{
969	unsigned iPDSrc;
970	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPDPTE << X86_PDPT_SHIFT, &iPDSrc);
971
972	/*
973	* Scan for free page directory entries.
974	*
975	* Note that we do not support mappings at the very end of the
976	* address space since that will break our GCPtrEnd assumptions.
977	*/
978	const unsigned cPTs = pMapping->cb >> X86_PD_PAE_SHIFT;
979	unsigned iPDNew = RT_ELEMENTS(pPDSrc->a) - cPTs; /* (+ 1 - 1) */
980
981	while (iPDNew-- > 0)
982	{
983	/* Ugly assumption that mappings start on a 4 MB boundary. */
984	if (iPDNew & 1)
985	continue;
986
987	if (pPDSrc)
988	{
989	if (pPDSrc->a[iPDNew].n.u1Present)
990	continue;
991	if (cPTs > 1)
992	{
993	bool fOk = true;
994	for (unsigned i = 1; fOk && i < cPTs; i++)
995	if (pPDSrc->a[iPDNew + i].n.u1Present)
996	fOk = false;
997	if (!fOk)
998	continue;
999	}
1000	}
1001	/*
1002	* Check that it's not conflicting with an intermediate page table mapping.
1003	*/
1004	bool fOk = true;
1005	unsigned i = cPTs;
1006	while (fOk && i-- > 0)
1007	fOk = !pVM->pgm.s.apInterPaePDs[iPDPTE]->a[iPDNew + i].n.u1Present;
1008	if (!fOk)
1009	continue;
1010
1011	/*
1012	* Ask for the mapping.
1013	*/
1014	RTGCPTR GCPtrNewMapping = (iPDPTE << X86_PDPT_SHIFT) + (iPDNew << X86_PD_PAE_SHIFT);
1015
1016	if (pMapping->pfnRelocate(pVM, GCPtrOldMapping, GCPtrNewMapping, PGMRELOCATECALL_SUGGEST, pMapping->pvUser))
1017	{
1018	pgmR3MapRelocate(pVM, pMapping, GCPtrOldMapping, GCPtrNewMapping);
1019	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCResolveConflict, a);
1020	return VINF_SUCCESS;
1021	}
1022	}
1023	}
1024	STAM_PROFILE_STOP(&pVM->pgm.s.StatHCResolveConflict, a);
1025	AssertMsgFailed(("Failed to relocate page table mapping '%s' from %#x! (cPTs=%d)\n", pMapping->pszDesc, GCPtrOldMapping, pMapping->cb >> X86_PD_PAE_SHIFT));
1026	return VERR_PGM_NO_HYPERVISOR_ADDRESS;
1027	}
1028
1029	/**
1030	* Checks guest PD for conflicts with VMM GC mappings.
1031	*
1032	* @returns true if conflict detected.
1033	* @returns false if not.
1034	* @param pVM The virtual machine.
1035	* @param cr3 Guest context CR3 register.
1036	* @param fRawR0 Whether RawR0 is enabled or not.
1037	*/
1038	PGMR3DECL(bool) PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0) /** @todo how many HasConflict constructs do we really need? */
1039	{
1040	/*
1041	* Can skip this if mappings are safely fixed.
1042	*/
1043	if (pVM->pgm.s.fMappingsFixed)
1044	return false;
1045
1046	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE_NX);
1047
1048	/*
1049	* Iterate mappings.
1050	*/
1051	if (PGMGetGuestMode(pVM) == PGMMODE_32_BIT)
1052	{
1053	/*
1054	* Resolve the page directory.
1055	*/
1056	PX86PD pPD = pVM->pgm.s.pGuestPDHC;
1057	Assert(pPD);
1058	Assert(pPD == (PX86PD)MMPhysGCPhys2HCVirt(pVM, cr3 & X86_CR3_PAGE_MASK, sizeof(*pPD)));
1059
1060	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1061	{
1062	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
1063	unsigned iPT = pCur->cPTs;
1064	while (iPT-- > 0)
1065	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
1066	&& (fRawR0 \|\| pPD->a[iPDE + iPT].n.u1User))
1067	{
1068	STAM_COUNTER_INC(&pVM->pgm.s.StatHCDetectedConflicts);
1069	Log(("PGMR3HasMappingConflicts: Conflict was detected at %VGv for mapping %s (32 bits)\n"
1070	" iPDE=%#x iPT=%#x PDE=%VGp.\n",
1071	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
1072	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
1073	return true;
1074	}
1075	}
1076	}
1077	else
1078	if ( PGMGetGuestMode(pVM) == PGMMODE_PAE
1079	\|\| PGMGetGuestMode(pVM) == PGMMODE_PAE_NX)
1080	{
1081	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1082	{
1083	X86PDEPAE Pde;
1084	RTGCPTR GCPtr = pCur->GCPtr;
1085
1086	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
1087	while (iPT-- > 0)
1088	{
1089	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
1090
1091	if ( Pde.n.u1Present
1092	&& (fRawR0 \|\| Pde.n.u1User))
1093	{
1094	STAM_COUNTER_INC(&pVM->pgm.s.StatHCDetectedConflicts);
1095	Log(("PGMR3HasMappingConflicts: Conflict was detected at %VGv for mapping %s (PAE)\n"
1096	" PDE=%VGp.\n",
1097	GCPtr, pCur->pszDesc, Pde.u));
1098	return true;
1099	}
1100	GCPtr += (1 << X86_PD_PAE_SHIFT);
1101	}
1102	}
1103	}
1104	else
1105	AssertFailed();
1106
1107	return false;
1108	}
1109
1110
1111	/**
1112	* Read memory from the guest mappings.
1113	*
1114	* This will use the page tables associated with the mappings to
1115	* read the memory. This means that not all kind of memory is readable
1116	* since we don't necessarily know how to convert that physical address
1117	* to a HC virtual one.
1118	*
1119	* @returns VBox status.
1120	* @param pVM VM handle.
1121	* @param pvDst The destination address (HC of course).
1122	* @param GCPtrSrc The source address (GC virtual address).
1123	* @param cb Number of bytes to read.
1124	*/
1125	PGMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
1126	{
1127	/** @todo remove this simplicity hack */
1128	/*
1129	* Simplicity over speed... Chop the request up into chunks
1130	* which don't cross pages.
1131	*/
1132	if (cb + (GCPtrSrc & PAGE_OFFSET_MASK) > PAGE_SIZE)
1133	{
1134	for (;;)
1135	{
1136	unsigned cbRead = RT_MIN(cb, PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK));
1137	int rc = PGMR3MapRead(pVM, pvDst, GCPtrSrc, cbRead);
1138	if (VBOX_FAILURE(rc))
1139	return rc;
1140	cb -= cbRead;
1141	if (!cb)
1142	break;
1143	pvDst = (char *)pvDst + cbRead;
1144	GCPtrSrc += cbRead;
1145	}
1146	return VINF_SUCCESS;
1147	}
1148
1149	/*
1150	* Find the mapping.
1151	*/
1152	PPGMMAPPING pCur = CTXALLSUFF(pVM->pgm.s.pMappings);
1153	while (pCur)
1154	{
1155	RTGCUINTPTR off = (RTGCUINTPTR)GCPtrSrc - (RTGCUINTPTR)pCur->GCPtr;
1156	if (off < pCur->cb)
1157	{
1158	if (off + cb > pCur->cb)
1159	{
1160	AssertMsgFailed(("Invalid page range %VGv LB%#x. mapping '%s' %VGv to %VGv\n",
1161	GCPtrSrc, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast));
1162	return VERR_INVALID_PARAMETER;
1163	}
1164
1165	unsigned iPT = off >> X86_PD_SHIFT;
1166	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
1167	while (cb > 0 && iPTE < RT_ELEMENTS(CTXALLSUFF(pCur->aPTs[iPT].pPT)->a))
1168	{
1169	if (!CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].n.u1Present)
1170	return VERR_PAGE_NOT_PRESENT;
1171	RTHCPHYS HCPhys = CTXALLSUFF(pCur->aPTs[iPT].paPaePTs)[iPTE / 512].a[iPTE % 512].u & X86_PTE_PAE_PG_MASK;
1172
1173	/*
1174	* Get the virtual page from the physical one.
1175	*/
1176	void *pvPage;
1177	int rc = MMR3HCPhys2HCVirt(pVM, HCPhys, &pvPage);
1178	if (VBOX_FAILURE(rc))
1179	return rc;
1180
1181	memcpy(pvDst, (char *)pvPage + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
1182	return VINF_SUCCESS;
1183	}
1184	}
1185
1186	/* next */
1187	pCur = CTXALLSUFF(pCur->pNext);
1188	}
1189
1190	return VERR_INVALID_POINTER;
1191	}
1192
1193
1194	/**
1195	* Info callback for 'pgmhandlers'.
1196	*
1197	* @param pHlp The output helpers.
1198	* @param pszArgs The arguments. phys or virt.
1199	*/
1200	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1201	{
1202	pHlp->pfnPrintf(pHlp, pVM->pgm.s.fMappingsFixed
1203	? "\nThe mappings are FIXED.\n"
1204	: "\nThe mappings are FLOATING.\n");
1205	PPGMMAPPING pCur;
1206	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1207	pHlp->pfnPrintf(pHlp, "%VGv - %VGv %s\n", pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
1208	}
1209

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source: vbox/trunk/src/VBox/VMM/PGMMap.cpp@ 12623

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