VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 7961

Last change on this file since 7961 was 7961, checked in by vboxsync, 17 years ago

Updates for PAE paging in raw mode
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File size: 144.8 KB
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1/* $Id: PGMInternal.h 7961 2008-04-14 17:09:45Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/stam.h>
25#include <VBox/param.h>
26#include <VBox/vmm.h>
27#include <VBox/mm.h>
28#include <VBox/pdmcritsect.h>
29#include <VBox/pdmapi.h>
30#include <VBox/dis.h>
31#include <VBox/dbgf.h>
32#include <VBox/log.h>
33#include <VBox/gmm.h>
34#include <iprt/avl.h>
35#include <iprt/assert.h>
36#include <iprt/critsect.h>
37
38#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
39# error "Not in PGM! This is an internal header!"
40#endif
41
42
43/** @defgroup grp_pgm_int Internals
44 * @ingroup grp_pgm
45 * @internal
46 * @{
47 */
48
49
50/** @name PGM Compile Time Config
51 * @{
52 */
53
54/**
55 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
56 * Comment it if it will break something.
57 */
58#define PGM_OUT_OF_SYNC_IN_GC
59
60/**
61 * Virtualize the dirty bit
62 * This also makes a half-hearted attempt at the accessed bit. For full
63 * accessed bit virtualization define PGM_SYNC_ACCESSED_BIT.
64 */
65#define PGM_SYNC_DIRTY_BIT
66
67/**
68 * Fully virtualize the accessed bit.
69 * @remark This requires SYNC_DIRTY_ACCESSED_BITS to be defined!
70 */
71#define PGM_SYNC_ACCESSED_BIT
72
73/**
74 * Check and skip global PDEs for non-global flushes
75 */
76#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
77
78/**
79 * Sync N pages instead of a whole page table
80 */
81#define PGM_SYNC_N_PAGES
82
83/**
84 * Number of pages to sync during a page fault
85 *
86 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
87 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
88 */
89#define PGM_SYNC_NR_PAGES 8
90
91/**
92 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
93 */
94#define PGM_MAX_PHYSCACHE_ENTRIES 64
95#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
96
97/**
98 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
99 */
100#define PGM_PHYSMEMACCESS_CACHING
101
102/*
103 * Assert Sanity.
104 */
105#if defined(PGM_SYNC_ACCESSED_BIT) && !defined(PGM_SYNC_DIRTY_BIT)
106# error "PGM_SYNC_ACCESSED_BIT requires PGM_SYNC_DIRTY_BIT!"
107#endif
108
109/** @def PGMPOOL_WITH_CACHE
110 * Enable agressive caching using the page pool.
111 *
112 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
113 */
114#define PGMPOOL_WITH_CACHE
115
116/** @def PGMPOOL_WITH_MIXED_PT_CR3
117 * When defined, we'll deal with 'uncachable' pages.
118 */
119#ifdef PGMPOOL_WITH_CACHE
120# define PGMPOOL_WITH_MIXED_PT_CR3
121#endif
122
123/** @def PGMPOOL_WITH_MONITORING
124 * Monitor the guest pages which are shadowed.
125 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
126 * be enabled as well.
127 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
128 */
129#ifdef PGMPOOL_WITH_CACHE
130# define PGMPOOL_WITH_MONITORING
131#endif
132
133/** @def PGMPOOL_WITH_GCPHYS_TRACKING
134 * Tracking the of shadow pages mapping guest physical pages.
135 *
136 * This is very expensive, the current cache prototype is trying to figure out
137 * whether it will be acceptable with an agressive caching policy.
138 */
139#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
140# define PGMPOOL_WITH_GCPHYS_TRACKING
141#endif
142
143/** @def PGMPOOL_WITH_USER_TRACKNG
144 * Tracking users of shadow pages. This is required for the linking of shadow page
145 * tables and physical guest addresses.
146 */
147#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
148# define PGMPOOL_WITH_USER_TRACKING
149#endif
150
151/** @def PGMPOOL_CFG_MAX_GROW
152 * The maximum number of pages to add to the pool in one go.
153 */
154#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
155
156/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
157 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
158 */
159#ifdef VBOX_STRICT
160# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
161#endif
162/** @} */
163
164
165/** @name PDPT and PML4 flags.
166 * These are placed in the three bits available for system programs in
167 * the PDPT and PML4 entries.
168 * @{ */
169/** The entry is a permanent one and it's must always be present.
170 * Never free such an entry. */
171#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172/** @} */
173
174/** @name Page directory flags.
175 * These are placed in the three bits available for system programs in
176 * the page directory entries.
177 * @{ */
178/** Mapping (hypervisor allocated pagetable). */
179#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
180/** Made read-only to facilitate dirty bit tracking. */
181#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
182/** @} */
183
184/** @name Page flags.
185 * These are placed in the three bits available for system programs in
186 * the page entries.
187 * @{ */
188/** Made read-only to facilitate dirty bit tracking. */
189#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
190
191#ifndef PGM_PTFLAGS_CSAM_VALIDATED
192/** Scanned and approved by CSAM (tm).
193 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
194 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
195#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
196#endif
197/** @} */
198
199/** @name Defines used to indicate the shadow and guest paging in the templates.
200 * @{ */
201#define PGM_TYPE_REAL 1
202#define PGM_TYPE_PROT 2
203#define PGM_TYPE_32BIT 3
204#define PGM_TYPE_PAE 4
205#define PGM_TYPE_AMD64 5
206/** @} */
207
208/** Macro for checking if the guest is using paging.
209 * @param uType PGM_TYPE_*
210 * @remark ASSUMES certain order of the PGM_TYPE_* values.
211 */
212#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT)
213
214/** Macro for checking if the guest supports the NX bit.
215 * @param uType PGM_TYPE_*
216 * @remark ASSUMES certain order of the PGM_TYPE_* values.
217 */
218#define PGM_WITH_NX(uType) ((uType) >= PGM_TYPE_PAE)
219
220
221/** @def PGM_HCPHYS_2_PTR
222 * Maps a HC physical page pool address to a virtual address.
223 *
224 * @returns VBox status code.
225 * @param pVM The VM handle.
226 * @param HCPhys The HC physical address to map to a virtual one.
227 * @param ppv Where to store the virtual address. No need to cast this.
228 *
229 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
230 * small page window employeed by that function. Be careful.
231 * @remark There is no need to assert on the result.
232 */
233#ifdef IN_GC
234# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
235#else
236# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
237#endif
238
239/** @def PGM_GCPHYS_2_PTR
240 * Maps a GC physical page address to a virtual address.
241 *
242 * @returns VBox status code.
243 * @param pVM The VM handle.
244 * @param GCPhys The GC physical address to map to a virtual one.
245 * @param ppv Where to store the virtual address. No need to cast this.
246 *
247 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
248 * small page window employeed by that function. Be careful.
249 * @remark There is no need to assert on the result.
250 */
251#ifdef IN_GC
252# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
253#else
254# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
255#endif
256
257/** @def PGM_GCPHYS_2_PTR_EX
258 * Maps a unaligned GC physical page address to a virtual address.
259 *
260 * @returns VBox status code.
261 * @param pVM The VM handle.
262 * @param GCPhys The GC physical address to map to a virtual one.
263 * @param ppv Where to store the virtual address. No need to cast this.
264 *
265 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
266 * small page window employeed by that function. Be careful.
267 * @remark There is no need to assert on the result.
268 */
269#ifdef IN_GC
270# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
271#else
272# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
273#endif
274
275/** @def PGM_INVL_PG
276 * Invalidates a page when in GC does nothing in HC.
277 *
278 * @param GCVirt The virtual address of the page to invalidate.
279 */
280#ifdef IN_GC
281# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
282#else
283# define PGM_INVL_PG(GCVirt) ((void)0)
284#endif
285
286/** @def PGM_INVL_BIG_PG
287 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
288 *
289 * @param GCVirt The virtual address within the page directory to invalidate.
290 */
291#ifdef IN_GC
292# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
293#else
294# define PGM_INVL_BIG_PG(GCVirt) ((void)0)
295#endif
296
297/** @def PGM_INVL_GUEST_TLBS()
298 * Invalidates all guest TLBs.
299 */
300#ifdef IN_GC
301# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
302#else
303# define PGM_INVL_GUEST_TLBS() ((void)0)
304#endif
305
306
307/**
308 * Structure for tracking GC Mappings.
309 *
310 * This structure is used by linked list in both GC and HC.
311 */
312typedef struct PGMMAPPING
313{
314 /** Pointer to next entry. */
315 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
316 /** Pointer to next entry. */
317 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
318 /** Pointer to next entry. */
319 GCPTRTYPE(struct PGMMAPPING *) pNextGC;
320 /** Start Virtual address. */
321 RTGCUINTPTR GCPtr;
322 /** Last Virtual address (inclusive). */
323 RTGCUINTPTR GCPtrLast;
324 /** Range size (bytes). */
325 RTGCUINTPTR cb;
326 /** Pointer to relocation callback function. */
327 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
328 /** User argument to the callback. */
329 R3PTRTYPE(void *) pvUser;
330 /** Mapping description / name. For easing debugging. */
331 R3PTRTYPE(const char *) pszDesc;
332 /** Number of page tables. */
333 RTUINT cPTs;
334#if HC_ARCH_BITS != GC_ARCH_BITS
335 RTUINT uPadding0; /**< Alignment padding. */
336#endif
337 /** Array of page table mapping data. Each entry
338 * describes one page table. The array can be longer
339 * than the declared length.
340 */
341 struct
342 {
343 /** The HC physical address of the page table. */
344 RTHCPHYS HCPhysPT;
345 /** The HC physical address of the first PAE page table. */
346 RTHCPHYS HCPhysPaePT0;
347 /** The HC physical address of the second PAE page table. */
348 RTHCPHYS HCPhysPaePT1;
349 /** The HC virtual address of the 32-bit page table. */
350 R3PTRTYPE(PX86PT) pPTR3;
351 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
352 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
353 /** The GC virtual address of the 32-bit page table. */
354 GCPTRTYPE(PX86PT) pPTGC;
355 /** The GC virtual address of the two PAE page table. */
356 GCPTRTYPE(PX86PTPAE) paPaePTsGC;
357 /** The GC virtual address of the 32-bit page table. */
358 R0PTRTYPE(PX86PT) pPTR0;
359 /** The GC virtual address of the two PAE page table. */
360 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
361 } aPTs[1];
362} PGMMAPPING;
363/** Pointer to structure for tracking GC Mappings. */
364typedef struct PGMMAPPING *PPGMMAPPING;
365
366
367/**
368 * Physical page access handler structure.
369 *
370 * This is used to keep track of physical address ranges
371 * which are being monitored in some kind of way.
372 */
373typedef struct PGMPHYSHANDLER
374{
375 AVLROGCPHYSNODECORE Core;
376 /** Access type. */
377 PGMPHYSHANDLERTYPE enmType;
378 /** Number of pages to update. */
379 uint32_t cPages;
380 /** Pointer to R3 callback function. */
381 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
382 /** User argument for R3 handlers. */
383 R3PTRTYPE(void *) pvUserR3;
384 /** Pointer to R0 callback function. */
385 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
386 /** User argument for R0 handlers. */
387 R0PTRTYPE(void *) pvUserR0;
388 /** Pointer to GC callback function. */
389 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
390 /** User argument for GC handlers. */
391 GCPTRTYPE(void *) pvUserGC;
392 /** Description / Name. For easing debugging. */
393 R3PTRTYPE(const char *) pszDesc;
394#ifdef VBOX_WITH_STATISTICS
395 /** Profiling of this handler. */
396 STAMPROFILE Stat;
397#endif
398} PGMPHYSHANDLER;
399/** Pointer to a physical page access handler structure. */
400typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
401
402
403/**
404 * Cache node for the physical addresses covered by a virtual handler.
405 */
406typedef struct PGMPHYS2VIRTHANDLER
407{
408 /** Core node for the tree based on physical ranges. */
409 AVLROGCPHYSNODECORE Core;
410 /** Offset from this struct to the PGMVIRTHANDLER structure. */
411 int32_t offVirtHandler;
412 /** Offset of the next alias relative to this one.
413 * Bit 0 is used for indicating whether we're in the tree.
414 * Bit 1 is used for indicating that we're the head node.
415 */
416 int32_t offNextAlias;
417} PGMPHYS2VIRTHANDLER;
418/** Pointer to a phys to virtual handler structure. */
419typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
420
421/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
422 * node is in the tree. */
423#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
424/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
425 * node is in the head of an alias chain.
426 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
427#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
428/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
429#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
430
431
432/**
433 * Virtual page access handler structure.
434 *
435 * This is used to keep track of virtual address ranges
436 * which are being monitored in some kind of way.
437 */
438typedef struct PGMVIRTHANDLER
439{
440 /** Core node for the tree based on virtual ranges. */
441 AVLROGCPTRNODECORE Core;
442 /** Number of cache pages. */
443 uint32_t u32Padding;
444 /** Access type. */
445 PGMVIRTHANDLERTYPE enmType;
446 /** Number of cache pages. */
447 uint32_t cPages;
448
449/** @todo The next two members are redundant. It adds some readability though. */
450 /** Start of the range. */
451 RTGCPTR GCPtr;
452 /** End of the range (exclusive). */
453 RTGCPTR GCPtrLast;
454 /** Size of the range (in bytes). */
455 RTGCUINTPTR cb;
456 /** Pointer to the GC callback function. */
457 GCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
458 /** Pointer to the HC callback function for invalidation. */
459 R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
460 /** Pointer to the HC callback function. */
461 R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
462 /** Description / Name. For easing debugging. */
463 R3PTRTYPE(const char *) pszDesc;
464#ifdef VBOX_WITH_STATISTICS
465 /** Profiling of this handler. */
466 STAMPROFILE Stat;
467#endif
468 /** Array of cached physical addresses for the monitored ranged. */
469 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
470} PGMVIRTHANDLER;
471/** Pointer to a virtual page access handler structure. */
472typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
473
474
475/**
476 * Page type.
477 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
478 * @todo convert to \#defines.
479 */
480typedef enum PGMPAGETYPE
481{
482 /** The usual invalid zero entry. */
483 PGMPAGETYPE_INVALID = 0,
484 /** RAM page. (RWX) */
485 PGMPAGETYPE_RAM,
486 /** MMIO2 page. (RWX) */
487 PGMPAGETYPE_MMIO2,
488 /** Shadowed ROM. (RWX) */
489 PGMPAGETYPE_ROM_SHADOW,
490 /** ROM page. (R-X) */
491 PGMPAGETYPE_ROM,
492 /** MMIO page. (---) */
493 PGMPAGETYPE_MMIO,
494 /** End of valid entries. */
495 PGMPAGETYPE_END
496} PGMPAGETYPE;
497AssertCompile(PGMPAGETYPE_END < 7);
498
499/** @name Page type predicates.
500 * @{ */
501#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
502#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
503#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
504#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
505#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
506/** @} */
507
508
509/**
510 * A Physical Guest Page tracking structure.
511 *
512 * The format of this structure is complicated because we have to fit a lot
513 * of information into as few bits as possible. The format is also subject
514 * to change (there is one comming up soon). Which means that for we'll be
515 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
516 * accessess to the structure.
517 */
518typedef struct PGMPAGE
519{
520 /** The physical address and a whole lot of other stuff. All bits are used! */
521 RTHCPHYS HCPhys;
522 /** The page state. */
523 uint32_t u2StateX : 2;
524 /** Flag indicating that a write monitored page was written to when set. */
525 uint32_t fWrittenToX : 1;
526 /** For later. */
527 uint32_t fSomethingElse : 1;
528 /** The Page ID.
529 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
530 * The HCPhys will be 100% static. */
531 uint32_t idPageX : 28;
532 /** The page type (PGMPAGETYPE). */
533 uint32_t u3Type : 3;
534 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
535 uint32_t u2HandlerPhysStateX : 2;
536 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
537 uint32_t u2HandlerVirtStateX : 2;
538 uint32_t u29B : 25;
539} PGMPAGE;
540AssertCompileSize(PGMPAGE, 16);
541/** Pointer to a physical guest page. */
542typedef PGMPAGE *PPGMPAGE;
543/** Pointer to a const physical guest page. */
544typedef const PGMPAGE *PCPGMPAGE;
545/** Pointer to a physical guest page pointer. */
546typedef PPGMPAGE *PPPGMPAGE;
547
548
549/**
550 * Clears the page structure.
551 * @param pPage Pointer to the physical guest page tracking structure.
552 */
553#define PGM_PAGE_CLEAR(pPage) \
554 do { \
555 (pPage)->HCPhys = 0; \
556 (pPage)->u2StateX = 0; \
557 (pPage)->fWrittenToX = 0; \
558 (pPage)->fSomethingElse = 0; \
559 (pPage)->idPageX = 0; \
560 (pPage)->u3Type = 0; \
561 (pPage)->u29B = 0; \
562 } while (0)
563
564/**
565 * Initializes the page structure.
566 * @param pPage Pointer to the physical guest page tracking structure.
567 */
568#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
569 do { \
570 (pPage)->HCPhys = (_HCPhys); \
571 (pPage)->u2StateX = (_uState); \
572 (pPage)->fWrittenToX = 0; \
573 (pPage)->fSomethingElse = 0; \
574 (pPage)->idPageX = (_idPage); \
575 /*(pPage)->u3Type = (_uType); - later */ \
576 PGM_PAGE_SET_TYPE(pPage, _uType); \
577 (pPage)->u29B = 0; \
578 } while (0)
579
580/**
581 * Initializes the page structure of a ZERO page.
582 * @param pPage Pointer to the physical guest page tracking structure.
583 */
584#ifdef VBOX_WITH_NEW_PHYS_CODE
585# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
586 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
587#else
588# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
589 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
590#endif
591/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
592# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
593 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
594
595
596/** @name The Page state, PGMPAGE::u2StateX.
597 * @{ */
598/** The zero page.
599 * This is a per-VM page that's never ever mapped writable. */
600#define PGM_PAGE_STATE_ZERO 0
601/** A allocated page.
602 * This is a per-VM page allocated from the page pool (or wherever
603 * we get MMIO2 pages from if the type is MMIO2).
604 */
605#define PGM_PAGE_STATE_ALLOCATED 1
606/** A allocated page that's being monitored for writes.
607 * The shadow page table mappings are read-only. When a write occurs, the
608 * fWrittenTo member is set, the page remapped as read-write and the state
609 * moved back to allocated. */
610#define PGM_PAGE_STATE_WRITE_MONITORED 2
611/** The page is shared, aka. copy-on-write.
612 * This is a page that's shared with other VMs. */
613#define PGM_PAGE_STATE_SHARED 3
614/** @} */
615
616
617/**
618 * Gets the page state.
619 * @returns page state (PGM_PAGE_STATE_*).
620 * @param pPage Pointer to the physical guest page tracking structure.
621 */
622#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
623
624/**
625 * Sets the page state.
626 * @param pPage Pointer to the physical guest page tracking structure.
627 * @param _uState The new page state.
628 */
629#define PGM_PAGE_SET_STATE(pPage, _uState) \
630 do { (pPage)->u2StateX = (_uState); } while (0)
631
632
633/**
634 * Gets the host physical address of the guest page.
635 * @returns host physical address (RTHCPHYS).
636 * @param pPage Pointer to the physical guest page tracking structure.
637 */
638#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
639
640/**
641 * Sets the host physical address of the guest page.
642 * @param pPage Pointer to the physical guest page tracking structure.
643 * @param _HCPhys The new host physical address.
644 */
645#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
646 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
647 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
648
649/**
650 * Get the Page ID.
651 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
652 * @param pPage Pointer to the physical guest page tracking structure.
653 */
654#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
655/* later:
656#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
657 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
658*/
659/**
660 * Sets the Page ID.
661 * @param pPage Pointer to the physical guest page tracking structure.
662 */
663#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
664/* later:
665#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
666 | ((_idPage) & 0xfff) \
667 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
668*/
669
670/**
671 * Get the Chunk ID.
672 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
673 * @param pPage Pointer to the physical guest page tracking structure.
674 */
675#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
676/* later:
677#if GMM_CHUNKID_SHIFT == 12
678# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
679#elif GMM_CHUNKID_SHIFT > 12
680# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
681#elif GMM_CHUNKID_SHIFT < 12
682# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
683 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
684#else
685# error "GMM_CHUNKID_SHIFT isn't defined or something."
686#endif
687*/
688
689/**
690 * Get the index of the page within the allocaiton chunk.
691 * @returns The page index.
692 * @param pPage Pointer to the physical guest page tracking structure.
693 */
694#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
695/* later:
696#if GMM_CHUNKID_SHIFT <= 12
697# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
698#else
699# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
700 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
701#endif
702*/
703
704
705/**
706 * Gets the page type.
707 * @returns The page type.
708 * @param pPage Pointer to the physical guest page tracking structure.
709 */
710#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
711
712/**
713 * Sets the page type.
714 * @param pPage Pointer to the physical guest page tracking structure.
715 * @param _enmType The new page type (PGMPAGETYPE).
716 */
717#ifdef VBOX_WITH_NEW_PHYS_CODE
718#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
719 do { (pPage)->u3Type = (_enmType); } while (0)
720#else
721#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
722 do { \
723 (pPage)->u3Type = (_enmType); \
724 if ((_enmType) == PGMPAGETYPE_ROM) \
725 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
726 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
727 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
728 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
729 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
730 } while (0)
731#endif
732
733
734/**
735 * Checks if the page is 'reserved'.
736 * @returns true/false.
737 * @param pPage Pointer to the physical guest page tracking structure.
738 */
739#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
740
741/**
742 * Checks if the page is marked for MMIO.
743 * @returns true/false.
744 * @param pPage Pointer to the physical guest page tracking structure.
745 */
746#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
747
748/**
749 * Checks if the page is backed by the ZERO page.
750 * @returns true/false.
751 * @param pPage Pointer to the physical guest page tracking structure.
752 */
753#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
754
755/**
756 * Checks if the page is backed by a SHARED page.
757 * @returns true/false.
758 * @param pPage Pointer to the physical guest page tracking structure.
759 */
760#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
761
762
763/**
764 * Marks the paget as written to (for GMM change monitoring).
765 * @param pPage Pointer to the physical guest page tracking structure.
766 */
767#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
768
769/**
770 * Clears the written-to indicator.
771 * @param pPage Pointer to the physical guest page tracking structure.
772 */
773#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
774
775/**
776 * Checks if the page was marked as written-to.
777 * @returns true/false.
778 * @param pPage Pointer to the physical guest page tracking structure.
779 */
780#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
781
782
783/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
784 *
785 * @remarks The values are assigned in order of priority, so we can calculate
786 * the correct state for a page with different handlers installed.
787 * @{ */
788/** No handler installed. */
789#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
790/** Monitoring is temporarily disabled. */
791#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
792/** Write access is monitored. */
793#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
794/** All access is monitored. */
795#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
796/** @} */
797
798/**
799 * Gets the physical access handler state of a page.
800 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
801 * @param pPage Pointer to the physical guest page tracking structure.
802 */
803#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
804
805/**
806 * Sets the physical access handler state of a page.
807 * @param pPage Pointer to the physical guest page tracking structure.
808 * @param _uState The new state value.
809 */
810#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
811 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
812
813/**
814 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
815 * @returns true/false
816 * @param pPage Pointer to the physical guest page tracking structure.
817 */
818#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
819
820/**
821 * Checks if the page has any active physical access handlers.
822 * @returns true/false
823 * @param pPage Pointer to the physical guest page tracking structure.
824 */
825#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
826
827
828/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
829 *
830 * @remarks The values are assigned in order of priority, so we can calculate
831 * the correct state for a page with different handlers installed.
832 * @{ */
833/** No handler installed. */
834#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
835/* 1 is reserved so the lineup is identical with the physical ones. */
836/** Write access is monitored. */
837#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
838/** All access is monitored. */
839#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
840/** @} */
841
842/**
843 * Gets the virtual access handler state of a page.
844 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
845 * @param pPage Pointer to the physical guest page tracking structure.
846 */
847#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
848
849/**
850 * Sets the virtual access handler state of a page.
851 * @param pPage Pointer to the physical guest page tracking structure.
852 * @param _uState The new state value.
853 */
854#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
855 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
856
857/**
858 * Checks if the page has any virtual access handlers.
859 * @returns true/false
860 * @param pPage Pointer to the physical guest page tracking structure.
861 */
862#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
863
864/**
865 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
866 * virtual handlers.
867 * @returns true/false
868 * @param pPage Pointer to the physical guest page tracking structure.
869 */
870#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
871
872
873
874/**
875 * Checks if the page has any access handlers, including temporarily disabled ones.
876 * @returns true/false
877 * @param pPage Pointer to the physical guest page tracking structure.
878 */
879#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
880 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
881 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
882
883/**
884 * Checks if the page has any active access handlers.
885 * @returns true/false
886 * @param pPage Pointer to the physical guest page tracking structure.
887 */
888#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
889 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
890 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
891
892/**
893 * Checks if the page has any active access handlers catching all accesses.
894 * @returns true/false
895 * @param pPage Pointer to the physical guest page tracking structure.
896 */
897#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
898 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
899 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
900
901
902/**
903 * Ram range for GC Phys to HC Phys conversion.
904 *
905 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
906 * conversions too, but we'll let MM handle that for now.
907 *
908 * This structure is used by linked lists in both GC and HC.
909 */
910typedef struct PGMRAMRANGE
911{
912 /** Pointer to the next RAM range - for R3. */
913 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
914 /** Pointer to the next RAM range - for R0. */
915 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
916 /** Pointer to the next RAM range - for GC. */
917 GCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
918#if GC_ARCH_BITS == 32
919 /** Pointer alignment. */
920 RTGCPTR GCPtrAlignment;
921#endif
922 /** Start of the range. Page aligned. */
923 RTGCPHYS GCPhys;
924 /** Last address in the range (inclusive). Page aligned (-1). */
925 RTGCPHYS GCPhysLast;
926 /** Size of the range. (Page aligned of course). */
927 RTGCPHYS cb;
928 /** MM_RAM_* flags */
929 uint32_t fFlags;
930#ifdef VBOX_WITH_NEW_PHYS_CODE
931 uint32_t u32Alignment; /**< alignment. */
932#else
933 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
934 GCPTRTYPE(PRTHCPTR) pavHCChunkGC;
935 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
936 R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
937#endif
938 /** Start of the HC mapping of the range. This is only used for MMIO2. */
939 R3PTRTYPE(void *) pvHC;
940 /** The range description. */
941 R3PTRTYPE(const char *) pszDesc;
942
943 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
944#ifdef VBOX_WITH_NEW_PHYS_CODE
945 uint32_t au32Reserved[2];
946#elif HC_ARCH_BITS == 32
947 uint32_t au32Reserved[1];
948#endif
949
950 /** Array of physical guest page tracking structures. */
951 PGMPAGE aPages[1];
952} PGMRAMRANGE;
953/** Pointer to Ram range for GC Phys to HC Phys conversion. */
954typedef PGMRAMRANGE *PPGMRAMRANGE;
955
956/** Return hc ptr corresponding to the ram range and physical offset */
957#define PGMRAMRANGE_GETHCPTR(pRam, off) \
958 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
959 : (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
960
961/**
962 * Per page tracking structure for ROM image.
963 *
964 * A ROM image may have a shadow page, in which case we may have
965 * two pages backing it. This structure contains the PGMPAGE for
966 * both while PGMRAMRANGE have a copy of the active one. It is
967 * important that these aren't out of sync in any regard other
968 * than page pool tracking data.
969 */
970typedef struct PGMROMPAGE
971{
972 /** The page structure for the virgin ROM page. */
973 PGMPAGE Virgin;
974 /** The page structure for the shadow RAM page. */
975 PGMPAGE Shadow;
976 /** The current protection setting. */
977 PGMROMPROT enmProt;
978 /** Pad the structure size to a multiple of 8. */
979 uint32_t u32Padding;
980} PGMROMPAGE;
981/** Pointer to a ROM page tracking structure. */
982typedef PGMROMPAGE *PPGMROMPAGE;
983
984
985/**
986 * A registered ROM image.
987 *
988 * This is needed to keep track of ROM image since they generally
989 * intrude into a PGMRAMRANGE. It also keeps track of additional
990 * info like the two page sets (read-only virgin and read-write shadow),
991 * the current state of each page.
992 *
993 * Because access handlers cannot easily be executed in a different
994 * context, the ROM ranges needs to be accessible and in all contexts.
995 */
996typedef struct PGMROMRANGE
997{
998 /** Pointer to the next range - R3. */
999 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1000 /** Pointer to the next range - R0. */
1001 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1002 /** Pointer to the next range - GC. */
1003 GCPTRTYPE(struct PGMROMRANGE *) pNextGC;
1004#if GC_ARCH_BITS == 32
1005 RTGCPTR GCPtrAlignment; /**< Pointer alignment. */
1006#endif
1007 /** Address of the range. */
1008 RTGCPHYS GCPhys;
1009 /** Address of the last byte in the range. */
1010 RTGCPHYS GCPhysLast;
1011 /** Size of the range. */
1012 RTGCPHYS cb;
1013 /** The flags (PGMPHYS_ROM_FLAG_*). */
1014 uint32_t fFlags;
1015 /**< Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1016 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1017 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1018 * This is used for strictness checks. */
1019 R3PTRTYPE(const void *) pvOriginal;
1020 /** The ROM description. */
1021 R3PTRTYPE(const char *) pszDesc;
1022 /** The per page tracking structures. */
1023 PGMROMPAGE aPages[1];
1024} PGMROMRANGE;
1025/** Pointer to a ROM range. */
1026typedef PGMROMRANGE *PPGMROMRANGE;
1027
1028
1029/**
1030 * A registered MMIO2 (= Device RAM) range.
1031 *
1032 * There are a few reason why we need to keep track of these
1033 * registrations. One of them is the deregistration & cleanup
1034 * stuff, while another is that the PGMRAMRANGE associated with
1035 * such a region may have to be removed from the ram range list.
1036 *
1037 * Overlapping with a RAM range has to be 100% or none at all. The
1038 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1039 * meditation will be raised if a partial overlap or an overlap of
1040 * ROM pages is encountered. On an overlap we will free all the
1041 * existing RAM pages and put in the ram range pages instead.
1042 */
1043typedef struct PGMMMIO2RANGE
1044{
1045 /** The owner of the range. (a device) */
1046 PPDMDEVINSR3 pDevInsR3;
1047 /** Pointer to the ring-3 mapping of the allocation. */
1048 RTR3PTR pvR3;
1049 /** Pointer to the next range - R3. */
1050 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1051 /** Whether it's mapped or not. */
1052 bool fMapped;
1053 /** Whether it's overlapping or not. */
1054 bool fOverlapping;
1055 /** The PCI region number.
1056 * @remarks This ASSUMES that nobody will ever really need to have multiple
1057 * PCI devices with matching MMIO region numbers on a single device. */
1058 uint8_t iRegion;
1059 /**< Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1060 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1061 /** The associated RAM range. */
1062 PGMRAMRANGE RamRange;
1063} PGMMMIO2RANGE;
1064/** Pointer to a MMIO2 range. */
1065typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1066
1067
1068
1069
1070/** @todo r=bird: fix typename. */
1071/**
1072 * PGMPhysRead/Write cache entry
1073 */
1074typedef struct PGMPHYSCACHE_ENTRY
1075{
1076 /** HC pointer to physical page */
1077 R3PTRTYPE(uint8_t *) pbHC;
1078 /** GC Physical address for cache entry */
1079 RTGCPHYS GCPhys;
1080#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1081 RTGCPHYS u32Padding0; /**< alignment padding. */
1082#endif
1083} PGMPHYSCACHE_ENTRY;
1084
1085/**
1086 * PGMPhysRead/Write cache to reduce REM memory access overhead
1087 */
1088typedef struct PGMPHYSCACHE
1089{
1090 /** Bitmap of valid cache entries */
1091 uint64_t aEntries;
1092 /** Cache entries */
1093 PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1094} PGMPHYSCACHE;
1095
1096
1097/** Pointer to an allocation chunk ring-3 mapping. */
1098typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1099/** Pointer to an allocation chunk ring-3 mapping pointer. */
1100typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1101
1102/**
1103 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1104 *
1105 * The primary tree (Core) uses the chunk id as key.
1106 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1107 */
1108typedef struct PGMCHUNKR3MAP
1109{
1110 /** The key is the chunk id. */
1111 AVLU32NODECORE Core;
1112 /** The key is the ageing sequence number. */
1113 AVLLU32NODECORE AgeCore;
1114 /** The current age thingy. */
1115 uint32_t iAge;
1116 /** The current reference count. */
1117 uint32_t volatile cRefs;
1118 /** The current permanent reference count. */
1119 uint32_t volatile cPermRefs;
1120 /** The mapping address. */
1121 void *pv;
1122} PGMCHUNKR3MAP;
1123
1124/**
1125 * Allocation chunk ring-3 mapping TLB entry.
1126 */
1127typedef struct PGMCHUNKR3MAPTLBE
1128{
1129 /** The chunk id. */
1130 uint32_t volatile idChunk;
1131#if HC_ARCH_BITS == 64
1132 uint32_t u32Padding; /**< alignment padding. */
1133#endif
1134 /** The chunk map. */
1135 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1136} PGMCHUNKR3MAPTLBE;
1137/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1138typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1139
1140/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1141 * @remark Must be a power of two value. */
1142#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1143
1144/**
1145 * Allocation chunk ring-3 mapping TLB.
1146 *
1147 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1148 * At first glance this might look kinda odd since AVL trees are
1149 * supposed to give the most optimial lookup times of all trees
1150 * due to their balancing. However, take a tree with 1023 nodes
1151 * in it, that's 10 levels, meaning that most searches has to go
1152 * down 9 levels before they find what they want. This isn't fast
1153 * compared to a TLB hit. There is the factor of cache misses,
1154 * and of course the problem with trees and branch prediction.
1155 * This is why we use TLBs in front of most of the trees.
1156 *
1157 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1158 * difficult when we switch to inlined AVL trees (from kStuff).
1159 */
1160typedef struct PGMCHUNKR3MAPTLB
1161{
1162 /** The TLB entries. */
1163 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1164} PGMCHUNKR3MAPTLB;
1165
1166/**
1167 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1168 * @returns Chunk TLB index.
1169 * @param idChunk The Chunk ID.
1170 */
1171#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1172
1173
1174/**
1175 * Ring-3 guest page mapping TLB entry.
1176 * @remarks used in ring-0 as well at the moment.
1177 */
1178typedef struct PGMPAGER3MAPTLBE
1179{
1180 /** Address of the page. */
1181 RTGCPHYS volatile GCPhys;
1182 /** The guest page. */
1183 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1184 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1185 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1186 /** The address */
1187 R3R0PTRTYPE(void *) volatile pv;
1188#if HC_ARCH_BITS == 32
1189 uint32_t u32Padding; /**< alignment padding. */
1190#endif
1191} PGMPAGER3MAPTLBE;
1192/** Pointer to an entry in the HC physical TLB. */
1193typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1194
1195
1196/** The number of entries in the ring-3 guest page mapping TLB.
1197 * @remarks The value must be a power of two. */
1198#define PGM_PAGER3MAPTLB_ENTRIES 64
1199
1200/**
1201 * Ring-3 guest page mapping TLB.
1202 * @remarks used in ring-0 as well at the moment.
1203 */
1204typedef struct PGMPAGER3MAPTLB
1205{
1206 /** The TLB entries. */
1207 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1208} PGMPAGER3MAPTLB;
1209/** Pointer to the ring-3 guest page mapping TLB. */
1210typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1211
1212/**
1213 * Calculates the index of the TLB entry for the specified guest page.
1214 * @returns Physical TLB index.
1215 * @param GCPhys The guest physical address.
1216 */
1217#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1218
1219
1220/** @name Context neutrual page mapper TLB.
1221 *
1222 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1223 * code is writting in a kind of context neutrual way. Time will show whether
1224 * this actually makes sense or not...
1225 *
1226 * @{ */
1227/** @typedef PPGMPAGEMAPTLB
1228 * The page mapper TLB pointer type for the current context. */
1229/** @typedef PPGMPAGEMAPTLB
1230 * The page mapper TLB entry pointer type for the current context. */
1231/** @typedef PPGMPAGEMAPTLB
1232 * The page mapper TLB entry pointer pointer type for the current context. */
1233/** @def PGMPAGEMAPTLB_ENTRIES
1234 * The number of TLB entries in the page mapper TLB for the current context. */
1235/** @def PGM_PAGEMAPTLB_IDX
1236 * Calculate the TLB index for a guest physical address.
1237 * @returns The TLB index.
1238 * @param GCPhys The guest physical address. */
1239/** @typedef PPGMPAGEMAP
1240 * Pointer to a page mapper unit for current context. */
1241/** @typedef PPPGMPAGEMAP
1242 * Pointer to a page mapper unit pointer for current context. */
1243#ifdef IN_GC
1244// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1245// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1246// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1247# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1248# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1249 typedef void * PPGMPAGEMAP;
1250 typedef void ** PPPGMPAGEMAP;
1251//#elif IN_RING0
1252// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1253// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1254// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1255//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1256//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1257// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1258// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1259#else
1260 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1261 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1262 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1263# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1264# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1265 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1266 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1267#endif
1268/** @} */
1269
1270
1271/** @name PGM Pool Indexes.
1272 * Aka. the unique shadow page identifier.
1273 * @{ */
1274/** NIL page pool IDX. */
1275#define NIL_PGMPOOL_IDX 0
1276/** The first normal index. */
1277#define PGMPOOL_IDX_FIRST_SPECIAL 1
1278/** Page directory (32-bit root). */
1279#define PGMPOOL_IDX_PD 1
1280/** The extended PAE page directory (2048 entries, works as root currently). */
1281#define PGMPOOL_IDX_PAE_PD 2
1282 /** PAE Page Directory Table 0. */
1283#define PGMPOOL_IDX_PAE_PD_0 3
1284 /** PAE Page Directory Table 1. */
1285#define PGMPOOL_IDX_PAE_PD_1 4
1286 /** PAE Page Directory Table 2. */
1287#define PGMPOOL_IDX_PAE_PD_2 5
1288 /** PAE Page Directory Table 3. */
1289#define PGMPOOL_IDX_PAE_PD_4 6
1290/** Page Directory Pointer Table (PAE root, not currently used). */
1291#define PGMPOOL_IDX_PDPT 7
1292/** Page Map Level-4 (64-bit root). */
1293#define PGMPOOL_IDX_PML4 8
1294/** The first normal index. */
1295#define PGMPOOL_IDX_FIRST 9
1296/** The last valid index. (inclusive, 14 bits) */
1297#define PGMPOOL_IDX_LAST 0x3fff
1298/** @} */
1299
1300/** The NIL index for the parent chain. */
1301#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1302
1303/**
1304 * Node in the chain linking a shadowed page to it's parent (user).
1305 */
1306#pragma pack(1)
1307typedef struct PGMPOOLUSER
1308{
1309 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1310 uint16_t iNext;
1311 /** The user page index. */
1312 uint16_t iUser;
1313 /** Index into the user table. */
1314 uint16_t iUserTable;
1315} PGMPOOLUSER, *PPGMPOOLUSER;
1316typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1317#pragma pack()
1318
1319
1320/** The NIL index for the phys ext chain. */
1321#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1322
1323/**
1324 * Node in the chain of physical cross reference extents.
1325 */
1326#pragma pack(1)
1327typedef struct PGMPOOLPHYSEXT
1328{
1329 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1330 uint16_t iNext;
1331 /** The user page index. */
1332 uint16_t aidx[3];
1333} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1334typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1335#pragma pack()
1336
1337
1338/**
1339 * The kind of page that's being shadowed.
1340 */
1341typedef enum PGMPOOLKIND
1342{
1343 /** The virtual invalid 0 entry. */
1344 PGMPOOLKIND_INVALID = 0,
1345 /** The entry is free (=unused). */
1346 PGMPOOLKIND_FREE,
1347
1348 /** Shw: 32-bit page table; Gst: no paging */
1349 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1350 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1351 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1352 /** Shw: 32-bit page table; Gst: 4MB page. */
1353 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1354 /** Shw: PAE page table; Gst: no paging */
1355 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1356 /** Shw: PAE page table; Gst: 32-bit page table. */
1357 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1358 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1359 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1360 /** Shw: PAE page table; Gst: PAE page table. */
1361 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1362 /** Shw: PAE page table; Gst: 2MB page. */
1363 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1364
1365 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1366 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1367 /** Shw: PAE page directory; Gst: PAE page directory. */
1368 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1369
1370 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1371 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1372
1373 /** Shw: Root 32-bit page directory. */
1374 PGMPOOLKIND_ROOT_32BIT_PD,
1375 /** Shw: Root PAE page directory */
1376 PGMPOOLKIND_ROOT_PAE_PD,
1377 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1378 PGMPOOLKIND_ROOT_PDPT,
1379 /** Shw: Root page map level-4 table. */
1380 PGMPOOLKIND_ROOT_PML4,
1381
1382 /** The last valid entry. */
1383 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
1384} PGMPOOLKIND;
1385
1386
1387/**
1388 * The tracking data for a page in the pool.
1389 */
1390typedef struct PGMPOOLPAGE
1391{
1392 /** AVL node code with the (HC) physical address of this page. */
1393 AVLOHCPHYSNODECORE Core;
1394 /** Pointer to the HC mapping of the page. */
1395 R3R0PTRTYPE(void *) pvPageHC;
1396 /** The guest physical address. */
1397 RTGCPHYS GCPhys;
1398 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1399 uint8_t enmKind;
1400 uint8_t bPadding;
1401 /** The index of this page. */
1402 uint16_t idx;
1403 /** The next entry in the list this page currently resides in.
1404 * It's either in the free list or in the GCPhys hash. */
1405 uint16_t iNext;
1406#ifdef PGMPOOL_WITH_USER_TRACKING
1407 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1408 uint16_t iUserHead;
1409 /** The number of present entries. */
1410 uint16_t cPresent;
1411 /** The first entry in the table which is present. */
1412 uint16_t iFirstPresent;
1413#endif
1414#ifdef PGMPOOL_WITH_MONITORING
1415 /** The number of modifications to the monitored page. */
1416 uint16_t cModifications;
1417 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1418 uint16_t iModifiedNext;
1419 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1420 uint16_t iModifiedPrev;
1421 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1422 uint16_t iMonitoredNext;
1423 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1424 uint16_t iMonitoredPrev;
1425#endif
1426#ifdef PGMPOOL_WITH_CACHE
1427 /** The next page in the age list. */
1428 uint16_t iAgeNext;
1429 /** The previous page in the age list. */
1430 uint16_t iAgePrev;
1431#endif /* PGMPOOL_WITH_CACHE */
1432 /** Used to indicate that the page is zeroed. */
1433 bool fZeroed;
1434 /** Used to indicate that a PT has non-global entries. */
1435 bool fSeenNonGlobal;
1436 /** Used to indicate that we're monitoring writes to the guest page. */
1437 bool fMonitored;
1438 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1439 * (All pages are in the age list.) */
1440 bool fCached;
1441 /** This is used by the R3 access handlers when invoked by an async thread.
1442 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1443 bool volatile fReusedFlushPending;
1444 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1445 * In these cases the access handler acts differently and will check
1446 * for mapping conflicts like the normal CR3 handler.
1447 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1448 * replaced by a list of pages which share access handler.
1449 */
1450 bool fCR3Mix;
1451} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1452
1453
1454#ifdef PGMPOOL_WITH_CACHE
1455/** The hash table size. */
1456# define PGMPOOL_HASH_SIZE 0x40
1457/** The hash function. */
1458# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1459#endif
1460
1461
1462/**
1463 * The shadow page pool instance data.
1464 *
1465 * It's all one big allocation made at init time, except for the
1466 * pages that is. The user nodes follows immediatly after the
1467 * page structures.
1468 */
1469typedef struct PGMPOOL
1470{
1471 /** The VM handle - HC Ptr. */
1472 R3R0PTRTYPE(PVM) pVMHC;
1473 /** The VM handle - GC Ptr. */
1474 GCPTRTYPE(PVM) pVMGC;
1475 /** The max pool size. This includes the special IDs. */
1476 uint16_t cMaxPages;
1477 /** The current pool size. */
1478 uint16_t cCurPages;
1479 /** The head of the free page list. */
1480 uint16_t iFreeHead;
1481 /* Padding. */
1482 uint16_t u16Padding;
1483#ifdef PGMPOOL_WITH_USER_TRACKING
1484 /** Head of the chain of free user nodes. */
1485 uint16_t iUserFreeHead;
1486 /** The number of user nodes we've allocated. */
1487 uint16_t cMaxUsers;
1488 /** The number of present page table entries in the entire pool. */
1489 uint32_t cPresent;
1490 /** Pointer to the array of user nodes - GC pointer. */
1491 GCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1492 /** Pointer to the array of user nodes - HC pointer. */
1493 R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1494#endif /* PGMPOOL_WITH_USER_TRACKING */
1495#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1496 /** Head of the chain of free phys ext nodes. */
1497 uint16_t iPhysExtFreeHead;
1498 /** The number of user nodes we've allocated. */
1499 uint16_t cMaxPhysExts;
1500 /** Pointer to the array of physical xref extent - GC pointer. */
1501 GCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1502 /** Pointer to the array of physical xref extent nodes - HC pointer. */
1503 R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1504#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1505#ifdef PGMPOOL_WITH_CACHE
1506 /** Hash table for GCPhys addresses. */
1507 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1508 /** The head of the age list. */
1509 uint16_t iAgeHead;
1510 /** The tail of the age list. */
1511 uint16_t iAgeTail;
1512 /** Set if the cache is enabled. */
1513 bool fCacheEnabled;
1514#endif /* PGMPOOL_WITH_CACHE */
1515#ifdef PGMPOOL_WITH_MONITORING
1516 /** Head of the list of modified pages. */
1517 uint16_t iModifiedHead;
1518 /** The current number of modified pages. */
1519 uint16_t cModifiedPages;
1520 /** Access handler, GC. */
1521 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1522 /** Access handler, R0. */
1523 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1524 /** Access handler, R3. */
1525 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1526 /** The access handler description (HC ptr). */
1527 R3PTRTYPE(const char *) pszAccessHandler;
1528#endif /* PGMPOOL_WITH_MONITORING */
1529 /** The number of pages currently in use. */
1530 uint16_t cUsedPages;
1531#ifdef VBOX_WITH_STATISTICS
1532 /** The high wather mark for cUsedPages. */
1533 uint16_t cUsedPagesHigh;
1534 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1535 /** Profiling pgmPoolAlloc(). */
1536 STAMPROFILEADV StatAlloc;
1537 /** Profiling pgmPoolClearAll(). */
1538 STAMPROFILE StatClearAll;
1539 /** Profiling pgmPoolFlushAllInt(). */
1540 STAMPROFILE StatFlushAllInt;
1541 /** Profiling pgmPoolFlushPage(). */
1542 STAMPROFILE StatFlushPage;
1543 /** Profiling pgmPoolFree(). */
1544 STAMPROFILE StatFree;
1545 /** Profiling time spent zeroing pages. */
1546 STAMPROFILE StatZeroPage;
1547# ifdef PGMPOOL_WITH_USER_TRACKING
1548 /** Profiling of pgmPoolTrackDeref. */
1549 STAMPROFILE StatTrackDeref;
1550 /** Profiling pgmTrackFlushGCPhysPT. */
1551 STAMPROFILE StatTrackFlushGCPhysPT;
1552 /** Profiling pgmTrackFlushGCPhysPTs. */
1553 STAMPROFILE StatTrackFlushGCPhysPTs;
1554 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1555 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1556 /** Number of times we've been out of user records. */
1557 STAMCOUNTER StatTrackFreeUpOneUser;
1558# endif
1559# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1560 /** Profiling deref activity related tracking GC physical pages. */
1561 STAMPROFILE StatTrackDerefGCPhys;
1562 /** Number of linear searches for a HCPhys in the ram ranges. */
1563 STAMCOUNTER StatTrackLinearRamSearches;
1564 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1565 STAMCOUNTER StamTrackPhysExtAllocFailures;
1566# endif
1567# ifdef PGMPOOL_WITH_MONITORING
1568 /** Profiling the GC PT access handler. */
1569 STAMPROFILE StatMonitorGC;
1570 /** Times we've failed interpreting the instruction. */
1571 STAMCOUNTER StatMonitorGCEmulateInstr;
1572 /** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1573 STAMPROFILE StatMonitorGCFlushPage;
1574 /** Times we've detected fork(). */
1575 STAMCOUNTER StatMonitorGCFork;
1576 /** Profiling the GC access we've handled (except REP STOSD). */
1577 STAMPROFILE StatMonitorGCHandled;
1578 /** Times we've failed interpreting a patch code instruction. */
1579 STAMCOUNTER StatMonitorGCIntrFailPatch1;
1580 /** Times we've failed interpreting a patch code instruction during flushing. */
1581 STAMCOUNTER StatMonitorGCIntrFailPatch2;
1582 /** The number of times we've seen rep prefixes we can't handle. */
1583 STAMCOUNTER StatMonitorGCRepPrefix;
1584 /** Profiling the REP STOSD cases we've handled. */
1585 STAMPROFILE StatMonitorGCRepStosd;
1586
1587 /** Profiling the HC PT access handler. */
1588 STAMPROFILE StatMonitorHC;
1589 /** Times we've failed interpreting the instruction. */
1590 STAMCOUNTER StatMonitorHCEmulateInstr;
1591 /** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1592 STAMPROFILE StatMonitorHCFlushPage;
1593 /** Times we've detected fork(). */
1594 STAMCOUNTER StatMonitorHCFork;
1595 /** Profiling the HC access we've handled (except REP STOSD). */
1596 STAMPROFILE StatMonitorHCHandled;
1597 /** The number of times we've seen rep prefixes we can't handle. */
1598 STAMCOUNTER StatMonitorHCRepPrefix;
1599 /** Profiling the REP STOSD cases we've handled. */
1600 STAMPROFILE StatMonitorHCRepStosd;
1601 /** The number of times we're called in an async thread an need to flush. */
1602 STAMCOUNTER StatMonitorHCAsync;
1603 /** The high wather mark for cModifiedPages. */
1604 uint16_t cModifiedPagesHigh;
1605 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1606# endif
1607# ifdef PGMPOOL_WITH_CACHE
1608 /** The number of cache hits. */
1609 STAMCOUNTER StatCacheHits;
1610 /** The number of cache misses. */
1611 STAMCOUNTER StatCacheMisses;
1612 /** The number of times we've got a conflict of 'kind' in the cache. */
1613 STAMCOUNTER StatCacheKindMismatches;
1614 /** Number of times we've been out of pages. */
1615 STAMCOUNTER StatCacheFreeUpOne;
1616 /** The number of cacheable allocations. */
1617 STAMCOUNTER StatCacheCacheable;
1618 /** The number of uncacheable allocations. */
1619 STAMCOUNTER StatCacheUncacheable;
1620# endif
1621#elif HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1622 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1623#endif
1624 /** The AVL tree for looking up a page by its HC physical address. */
1625 AVLOHCPHYSTREE HCPhysTree;
1626 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1627 /** Array of pages. (cMaxPages in length)
1628 * The Id is the index into thist array.
1629 */
1630 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1631} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1632
1633
1634/** @def PGMPOOL_PAGE_2_PTR
1635 * Maps a pool page pool into the current context.
1636 *
1637 * @returns VBox status code.
1638 * @param pVM The VM handle.
1639 * @param pPage The pool page.
1640 *
1641 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1642 * small page window employeed by that function. Be careful.
1643 * @remark There is no need to assert on the result.
1644 */
1645#ifdef IN_GC
1646# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1647#else
1648# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1649#endif
1650
1651
1652/**
1653 * Trees are using self relative offsets as pointers.
1654 * So, all its data, including the root pointer, must be in the heap for HC and GC
1655 * to have the same layout.
1656 */
1657typedef struct PGMTREES
1658{
1659 /** Physical access handlers (AVL range+offsetptr tree). */
1660 AVLROGCPHYSTREE PhysHandlers;
1661 /** Virtual access handlers (AVL range + GC ptr tree). */
1662 AVLROGCPTRTREE VirtHandlers;
1663 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1664 AVLROGCPHYSTREE PhysToVirtHandlers;
1665 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1666 AVLROGCPTRTREE HyperVirtHandlers;
1667} PGMTREES;
1668/** Pointer to PGM trees. */
1669typedef PGMTREES *PPGMTREES;
1670
1671
1672/** @name Paging mode macros
1673 * @{ */
1674#ifdef IN_GC
1675# define PGM_CTX(a,b) a##GC##b
1676# define PGM_CTX_STR(a,b) a "GC" b
1677# define PGM_CTX_DECL(type) PGMGCDECL(type)
1678#else
1679# ifdef IN_RING3
1680# define PGM_CTX(a,b) a##R3##b
1681# define PGM_CTX_STR(a,b) a "R3" b
1682# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1683# else
1684# define PGM_CTX(a,b) a##R0##b
1685# define PGM_CTX_STR(a,b) a "R0" b
1686# define PGM_CTX_DECL(type) PGMDECL(type)
1687# endif
1688#endif
1689
1690#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1691#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1692#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1693#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1694#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1695#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1696#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1697#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1698#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1699#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1700#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1701#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1702#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1703#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1704#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1705#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1706#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1707
1708#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1709#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1710#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1711#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1712#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1713#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1714#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1715#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1716#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1717#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1718#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1719
1720/* Shw_Gst */
1721#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1722#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1723#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1724#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1725#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1726#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1727#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1728#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1729#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1730#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1731#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1732#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1733#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1734#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1735#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1736#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1737#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1738#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1739#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1740#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1741#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1742#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1743#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1744#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1745#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1746#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1747/** @} */
1748
1749/**
1750 * Data for each paging mode.
1751 */
1752typedef struct PGMMODEDATA
1753{
1754 /** The guest mode type. */
1755 uint32_t uGstType;
1756 /** The shadow mode type. */
1757 uint32_t uShwType;
1758
1759 /** @name Function pointers for Shadow paging.
1760 * @{
1761 */
1762 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1763 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1764 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1765 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1766 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1767 DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1768 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1769
1770 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1771 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1772 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1773 DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1774 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1775
1776 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1777 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1778 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1779 DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1780 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1781 /** @} */
1782
1783 /** @name Function pointers for Guest paging.
1784 * @{
1785 */
1786 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1787 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1788 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1789 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1790 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1791 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1792 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1793 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1794 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1795 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1796 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1797 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1798 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1799
1800 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1801 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1802 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1803 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1804 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1805 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1806 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1807 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1808 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1809
1810 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1811 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1812 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1813 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1814 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1815 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1816 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1817 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1818 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1819 /** @} */
1820
1821 /** @name Function pointers for Both Shadow and Guest paging.
1822 * @{
1823 */
1824 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1825 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1826 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1827 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1828 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1829 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1830 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1831#ifdef VBOX_STRICT
1832 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1833#endif
1834
1835 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1836 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1837 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1838 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1839 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1840 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1841#ifdef VBOX_STRICT
1842 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1843#endif
1844
1845 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1846 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1847 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1848 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1849 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1850 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1851#ifdef VBOX_STRICT
1852 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1853#endif
1854 /** @} */
1855} PGMMODEDATA, *PPGMMODEDATA;
1856
1857
1858
1859/**
1860 * Converts a PGM pointer into a VM pointer.
1861 * @returns Pointer to the VM structure the PGM is part of.
1862 * @param pPGM Pointer to PGM instance data.
1863 */
1864#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1865
1866/**
1867 * PGM Data (part of VM)
1868 */
1869typedef struct PGM
1870{
1871 /** Offset to the VM structure. */
1872 RTINT offVM;
1873
1874 /*
1875 * This will be redefined at least two more times before we're done, I'm sure.
1876 * The current code is only to get on with the coding.
1877 * - 2004-06-10: initial version, bird.
1878 * - 2004-07-02: 1st time, bird.
1879 * - 2004-10-18: 2nd time, bird.
1880 * - 2005-07-xx: 3rd time, bird.
1881 */
1882
1883 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1884 GCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1885 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1886 GCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1887
1888 /** The host paging mode. (This is what SUPLib reports.) */
1889 SUPPAGINGMODE enmHostMode;
1890 /** The shadow paging mode. */
1891 PGMMODE enmShadowMode;
1892 /** The guest paging mode. */
1893 PGMMODE enmGuestMode;
1894
1895 /** The current physical address representing in the guest CR3 register. */
1896 RTGCPHYS GCPhysCR3;
1897 /** Pointer to the 5 page CR3 content mapping.
1898 * The first page is always the CR3 (in some form) while the 4 other pages
1899 * are used of the PDs in PAE mode. */
1900 RTGCPTR GCPtrCR3Mapping;
1901#if HC_ARCH_BITS == 64
1902 uint32_t u32Alignment;
1903#endif
1904 /** The physical address of the currently monitored guest CR3 page.
1905 * When this value is NIL_RTGCPHYS no page is being monitored. */
1906 RTGCPHYS GCPhysGstCR3Monitored;
1907
1908 /** @name 32-bit Guest Paging.
1909 * @{ */
1910 /** The guest's page directory, HC pointer. */
1911 R3R0PTRTYPE(PX86PD) pGuestPDHC;
1912 /** The guest's page directory, static GC mapping. */
1913 GCPTRTYPE(PX86PD) pGuestPDGC;
1914 /** @} */
1915
1916 /** @name PAE Guest Paging.
1917 * @{ */
1918 /** The guest's page directory pointer table, static GC mapping. */
1919 GCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1920 /** The guest's page directory pointer table, HC pointer. */
1921 R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1922 /** The guest's page directories, HC pointers.
1923 * These are individual pointers and don't have to be adjecent.
1924 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1925 R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1926 /** The guest's page directories, static GC mapping.
1927 * Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1928 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1929 GCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1930 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1931 RTGCPHYS aGCPhysGstPaePDs[4];
1932 /** The physical addresses of the monitored guest page directories (PAE). */
1933 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1934 /** @} */
1935
1936
1937 /** @name 32-bit Shadow Paging
1938 * @{ */
1939 /** The 32-Bit PD - HC Ptr. */
1940 R3R0PTRTYPE(PX86PD) pHC32BitPD;
1941 /** The 32-Bit PD - GC Ptr. */
1942 GCPTRTYPE(PX86PD) pGC32BitPD;
1943#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1944 uint32_t u32Padding1; /**< alignment padding. */
1945#endif
1946 /** The Physical Address (HC) of the 32-Bit PD. */
1947 RTHCPHYS HCPhys32BitPD;
1948 /** @} */
1949
1950 /** @name PAE Shadow Paging
1951 * @{ */
1952 /** The four PDs for the low 4GB - HC Ptr.
1953 * Even though these are 4 pointers, what they point at is a single table.
1954 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1955 R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1956 /** The four PDs for the low 4GB - GC Ptr.
1957 * Same kind of mapping as apHCPaePDs. */
1958 GCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1959 /** The Physical Address (HC) of the four PDs for the low 4GB.
1960 * These are *NOT* 4 contiguous pages. */
1961 RTHCPHYS aHCPhysPaePDs[4];
1962 /** The PAE PDP - HC Ptr. */
1963 R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
1964 /** The Physical Address (HC) of the PAE PDPT. */
1965 RTHCPHYS HCPhysPaePDPT;
1966 /** The PAE PDPT - GC Ptr. */
1967 GCPTRTYPE(PX86PDPT) pGCPaePDPT;
1968 /** @} */
1969
1970 /** @name AMD64 Shadow Paging
1971 * Extends PAE Paging.
1972 * @{ */
1973 /** The Page Map Level 4 table - HC Ptr. */
1974 GCPTRTYPE(PX86PML4) pGCPaePML4;
1975 /** The Page Map Level 4 table - GC Ptr. */
1976 R3R0PTRTYPE(PX86PML4) pHCPaePML4;
1977 /** The Physical Address (HC) of the Page Map Level 4 table. */
1978 RTHCPHYS HCPhysPaePML4;
1979 /** @}*/
1980
1981 /** @name Function pointers for Shadow paging.
1982 * @{
1983 */
1984 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1985 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1986 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1987 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1988 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1989 DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1990 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1991
1992 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1993 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1994 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1995 DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1996 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1997#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1998 RTGCPTR alignment0; /**< structure size alignment. */
1999#endif
2000
2001 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2002 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2003 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
2004 DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
2005 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
2006
2007 /** @} */
2008
2009 /** @name Function pointers for Guest paging.
2010 * @{
2011 */
2012 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2013 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2014 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2015 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2016 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2017 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2018 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2019 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2020 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2021 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2022 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2023 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2024 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2025
2026 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2027 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2028 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2029 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2030 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
2031 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2032 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
2033 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
2034 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
2035#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2036 RTGCPTR alignment3; /**< structure size alignment. */
2037#endif
2038
2039 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2040 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2041 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2042 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2043 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2044 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2045 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2046 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2047 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2048 /** @} */
2049
2050 /** @name Function pointers for Both Shadow and Guest paging.
2051 * @{
2052 */
2053 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2054 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2055 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2056 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2057 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2058 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2059 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2060 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2061
2062 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2063 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2064 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2065 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2066 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2067 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2068 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2069
2070 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2071 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2072 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2073 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2074 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2075 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2076 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2077#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2078 RTGCPTR alignment2; /**< structure size alignment. */
2079#endif
2080 /** @} */
2081
2082 /** Pointer to SHW+GST mode data (function pointers).
2083 * The index into this table is made up from */
2084 R3PTRTYPE(PPGMMODEDATA) paModeData;
2085
2086 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2087 * This is sorted by physical address and contains no overlapping ranges. */
2088 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2089 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2090 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2091 /** GC pointer corresponding to PGM::pRamRangesR3. */
2092 GCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
2093 /** The configured RAM size. */
2094 RTUINT cbRamSize;
2095
2096 /** Pointer to the list of ROM ranges - for R3.
2097 * This is sorted by physical address and contains no overlapping ranges. */
2098 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2099 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2100 R0PTRTYPE(PPGMRAMRANGE) pRomRangesR0;
2101 /** GC pointer corresponding to PGM::pRomRangesR3. */
2102 GCPTRTYPE(PPGMRAMRANGE) pRomRangesGC;
2103 /** Alignment padding. */
2104 RTGCPTR GCPtrPadding2;
2105
2106 /** Pointer to the list of MMIO2 ranges - for R3.
2107 * Registration order. */
2108 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2109
2110 /** PGM offset based trees - HC Ptr. */
2111 R3R0PTRTYPE(PPGMTREES) pTreesHC;
2112 /** PGM offset based trees - GC Ptr. */
2113 GCPTRTYPE(PPGMTREES) pTreesGC;
2114
2115 /** Linked list of GC mappings - for GC.
2116 * The list is sorted ascending on address.
2117 */
2118 GCPTRTYPE(PPGMMAPPING) pMappingsGC;
2119 /** Linked list of GC mappings - for HC.
2120 * The list is sorted ascending on address.
2121 */
2122 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2123 /** Linked list of GC mappings - for R0.
2124 * The list is sorted ascending on address.
2125 */
2126 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2127
2128 /** If set no conflict checks are required. (boolean) */
2129 bool fMappingsFixed;
2130 /** If set, then no mappings are put into the shadow page table. (boolean) */
2131 bool fDisableMappings;
2132 /** Size of fixed mapping */
2133 uint32_t cbMappingFixed;
2134 /** Base address (GC) of fixed mapping */
2135 RTGCPTR GCPtrMappingFixed;
2136#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2137 uint32_t u32Padding0; /**< alignment padding. */
2138#endif
2139
2140
2141 /** @name Intermediate Context
2142 * @{ */
2143 /** Pointer to the intermediate page directory - Normal. */
2144 R3PTRTYPE(PX86PD) pInterPD;
2145 /** Pointer to the intermedate page tables - Normal.
2146 * There are two page tables, one for the identity mapping and one for
2147 * the host context mapping (of the core code). */
2148 R3PTRTYPE(PX86PT) apInterPTs[2];
2149 /** Pointer to the intermedate page tables - PAE. */
2150 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2151 /** Pointer to the intermedate page directory - PAE. */
2152 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2153 /** Pointer to the intermedate page directory - PAE. */
2154 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2155 /** Pointer to the intermedate page-map level 4 - AMD64. */
2156 R3PTRTYPE(PX86PML4) pInterPaePML4;
2157 /** Pointer to the intermedate page directory - AMD64. */
2158 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2159 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2160 RTHCPHYS HCPhysInterPD;
2161 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2162 RTHCPHYS HCPhysInterPaePDPT;
2163 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2164 RTHCPHYS HCPhysInterPaePML4;
2165 /** @} */
2166
2167 /** Base address of the dynamic page mapping area.
2168 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2169 */
2170 GCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2171 /** The index of the last entry used in the dynamic page mapping area. */
2172 RTUINT iDynPageMapLast;
2173 /** Cache containing the last entries in the dynamic page mapping area.
2174 * The cache size is covering half of the mapping area. */
2175 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2176
2177 /** A20 gate mask.
2178 * Our current approach to A20 emulation is to let REM do it and don't bother
2179 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2180 * But whould need arrise, we'll subject physical addresses to this mask. */
2181 RTGCPHYS GCPhysA20Mask;
2182 /** A20 gate state - boolean! */
2183 RTUINT fA20Enabled;
2184
2185 /** What needs syncing (PGM_SYNC_*).
2186 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2187 * PGMFlushTLB, and PGMR3Load. */
2188 RTUINT fSyncFlags;
2189
2190 /** PGM critical section.
2191 * This protects the physical & virtual access handlers, ram ranges,
2192 * and the page flag updating (some of it anyway).
2193 */
2194 PDMCRITSECT CritSect;
2195
2196 /** Shadow Page Pool - HC Ptr. */
2197 R3R0PTRTYPE(PPGMPOOL) pPoolHC;
2198 /** Shadow Page Pool - GC Ptr. */
2199 GCPTRTYPE(PPGMPOOL) pPoolGC;
2200
2201 /** We're not in a state which permits writes to guest memory.
2202 * (Only used in strict builds.) */
2203 bool fNoMorePhysWrites;
2204
2205 /** Flush the cache on the next access. */
2206 bool fPhysCacheFlushPending;
2207/** @todo r=bird: Fix member names!*/
2208 /** PGMPhysRead cache */
2209 PGMPHYSCACHE pgmphysreadcache;
2210 /** PGMPhysWrite cache */
2211 PGMPHYSCACHE pgmphyswritecache;
2212
2213 /**
2214 * Data associated with managing the ring-3 mappings of the allocation chunks.
2215 */
2216 struct
2217 {
2218 /** The chunk tree, ordered by chunk id. */
2219 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2220 /** The chunk mapping TLB. */
2221 PGMCHUNKR3MAPTLB Tlb;
2222 /** The number of mapped chunks. */
2223 uint32_t c;
2224 /** The maximum number of mapped chunks.
2225 * @cfgm PGM/MaxRing3Chunks */
2226 uint32_t cMax;
2227 /** The chunk age tree, ordered by ageing sequence number. */
2228 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2229 /** The current time. */
2230 uint32_t iNow;
2231 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2232 uint32_t AgeingCountdown;
2233 } ChunkR3Map;
2234
2235 /**
2236 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2237 */
2238 PGMPAGER3MAPTLB PhysTlbHC;
2239
2240 /** @name The zero page.
2241 * @{ */
2242 /** The host physical address of the zero page. */
2243 RTHCPHYS HCPhysZeroPg;
2244 /** The ring-3 mapping of the zero page. */
2245 RTR3PTR pvZeroPgR3;
2246 /** The ring-0 mapping of the zero page. */
2247 RTR0PTR pvZeroPgR0;
2248 /** The GC mapping of the zero page. */
2249 RTGCPTR pvZeroPgGC;
2250#if GC_ARCH_BITS != 32
2251 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2252#endif
2253 /** @}*/
2254
2255 /** The number of handy pages. */
2256 uint32_t cHandyPages;
2257 /**
2258 * Array of handy pages.
2259 *
2260 * This array is used in a two way communication between pgmPhysAllocPage
2261 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2262 * an intermediary.
2263 *
2264 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2265 * (The current size of 32 pages, means 128 KB of handy memory.)
2266 */
2267 GMMPAGEDESC aHandyPages[32];
2268
2269 /** @name Release Statistics
2270 * @{ */
2271 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2272 uint32_t cPrivatePages; /**< The number of private pages. */
2273 uint32_t cSharedPages; /**< The number of shared pages. */
2274 uint32_t cZeroPages; /**< The number of zero backed pages. */
2275 /** The number of times the guest has switched mode since last reset or statistics reset. */
2276 STAMCOUNTER cGuestModeChanges;
2277 /** @} */
2278
2279#ifdef VBOX_WITH_STATISTICS
2280 /** GC: Which statistic this \#PF should be attributed to. */
2281 GCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
2282 RTGCPTR padding0;
2283 /** HC: Which statistic this \#PF should be attributed to. */
2284 R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
2285 RTHCPTR padding1;
2286 STAMPROFILE StatGCTrap0e; /**< GC: PGMGCTrap0eHandler() profiling. */
2287 STAMPROFILE StatTrap0eCSAM; /**< Profiling of the Trap0eHandler body when the cause is CSAM. */
2288 STAMPROFILE StatTrap0eDirtyAndAccessedBits; /**< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2289 STAMPROFILE StatTrap0eGuestTrap; /**< Profiling of the Trap0eHandler body when the cause is a guest trap. */
2290 STAMPROFILE StatTrap0eHndPhys; /**< Profiling of the Trap0eHandler body when the cause is a physical handler. */
2291 STAMPROFILE StatTrap0eHndVirt; /**< Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2292 STAMPROFILE StatTrap0eHndUnhandled; /**< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2293 STAMPROFILE StatTrap0eMisc; /**< Profiling of the Trap0eHandler body when the cause is not known. */
2294 STAMPROFILE StatTrap0eOutOfSync; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2295 STAMPROFILE StatTrap0eOutOfSyncHndPhys; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2296 STAMPROFILE StatTrap0eOutOfSyncHndVirt; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2297 STAMPROFILE StatTrap0eOutOfSyncObsHnd; /**< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2298 STAMPROFILE StatTrap0eSyncPT; /**< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2299
2300 STAMCOUNTER StatTrap0eMapHandler; /**< Number of traps due to access handlers in mappings. */
2301 STAMCOUNTER StatGCTrap0eConflicts; /**< GC: The number of times \#PF was caused by an undetected conflict. */
2302
2303 STAMCOUNTER StatGCTrap0eUSNotPresentRead;
2304 STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
2305 STAMCOUNTER StatGCTrap0eUSWrite;
2306 STAMCOUNTER StatGCTrap0eUSReserved;
2307 STAMCOUNTER StatGCTrap0eUSNXE;
2308 STAMCOUNTER StatGCTrap0eUSRead;
2309
2310 STAMCOUNTER StatGCTrap0eSVNotPresentRead;
2311 STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
2312 STAMCOUNTER StatGCTrap0eSVWrite;
2313 STAMCOUNTER StatGCTrap0eSVReserved;
2314 STAMCOUNTER StatGCTrap0eSNXE;
2315
2316 STAMCOUNTER StatTrap0eWPEmulGC;
2317 STAMCOUNTER StatTrap0eWPEmulR3;
2318
2319 STAMCOUNTER StatGCTrap0eUnhandled;
2320 STAMCOUNTER StatGCTrap0eMap;
2321
2322 /** GC: PGMSyncPT() profiling. */
2323 STAMPROFILE StatGCSyncPT;
2324 /** GC: The number of times PGMSyncPT() needed to allocate page tables. */
2325 STAMCOUNTER StatGCSyncPTAlloc;
2326 /** GC: The number of times PGMSyncPT() detected conflicts. */
2327 STAMCOUNTER StatGCSyncPTConflict;
2328 /** GC: The number of times PGMSyncPT() failed. */
2329 STAMCOUNTER StatGCSyncPTFailed;
2330 /** GC: PGMGCInvalidatePage() profiling. */
2331 STAMPROFILE StatGCInvalidatePage;
2332 /** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
2333 STAMCOUNTER StatGCInvalidatePage4KBPages;
2334 /** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
2335 STAMCOUNTER StatGCInvalidatePage4MBPages;
2336 /** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
2337 STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
2338 /** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
2339 STAMCOUNTER StatGCInvalidatePagePDNAs;
2340 /** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
2341 STAMCOUNTER StatGCInvalidatePagePDNPs;
2342 /** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
2343 STAMCOUNTER StatGCInvalidatePagePDMappings;
2344 /** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2345 STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
2346 /** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2347 STAMCOUNTER StatGCInvalidatePageSkipped;
2348 /** GC: The number of times user page is out of sync was detected in GC. */
2349 STAMCOUNTER StatGCPageOutOfSyncUser;
2350 /** GC: The number of times supervisor page is out of sync was detected in GC. */
2351 STAMCOUNTER StatGCPageOutOfSyncSupervisor;
2352 /** GC: The number of dynamic page mapping cache hits */
2353 STAMCOUNTER StatDynMapCacheMisses;
2354 /** GC: The number of dynamic page mapping cache misses */
2355 STAMCOUNTER StatDynMapCacheHits;
2356 /** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
2357 STAMCOUNTER StatGCGuestCR3WriteHandled;
2358 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
2359 STAMCOUNTER StatGCGuestCR3WriteUnhandled;
2360 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
2361 STAMCOUNTER StatGCGuestCR3WriteConflict;
2362 /** GC: Number of out-of-sync handled pages. */
2363 STAMCOUNTER StatHandlersOutOfSync;
2364 /** GC: Number of traps due to physical access handlers. */
2365 STAMCOUNTER StatHandlersPhysical;
2366 /** GC: Number of traps due to virtual access handlers. */
2367 STAMCOUNTER StatHandlersVirtual;
2368 /** GC: Number of traps due to virtual access handlers found by physical address. */
2369 STAMCOUNTER StatHandlersVirtualByPhys;
2370 /** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2371 STAMCOUNTER StatHandlersVirtualUnmarked;
2372 /** GC: Number of traps due to access outside range of monitored page(s). */
2373 STAMCOUNTER StatHandlersUnhandled;
2374
2375 /** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
2376 STAMCOUNTER StatGCGuestROMWriteHandled;
2377 /** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
2378 STAMCOUNTER StatGCGuestROMWriteUnhandled;
2379
2380 /** HC: PGMR3InvalidatePage() profiling. */
2381 STAMPROFILE StatHCInvalidatePage;
2382 /** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
2383 STAMCOUNTER StatHCInvalidatePage4KBPages;
2384 /** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2385 STAMCOUNTER StatHCInvalidatePage4MBPages;
2386 /** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2387 STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2388 /** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2389 STAMCOUNTER StatHCInvalidatePagePDNAs;
2390 /** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2391 STAMCOUNTER StatHCInvalidatePagePDNPs;
2392 /** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2393 STAMCOUNTER StatHCInvalidatePagePDMappings;
2394 /** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2395 STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2396 /** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2397 STAMCOUNTER StatHCInvalidatePageSkipped;
2398 /** HC: PGMR3SyncPT() profiling. */
2399 STAMPROFILE StatHCSyncPT;
2400 /** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2401 STAMPROFILE StatHCResolveConflict;
2402 /** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2403 STAMCOUNTER StatHCDetectedConflicts;
2404 /** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2405 STAMCOUNTER StatHCGuestPDWrite;
2406 /** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2407 STAMCOUNTER StatHCGuestPDWriteConflict;
2408
2409 /** HC: The number of pages marked not present for accessed bit emulation. */
2410 STAMCOUNTER StatHCAccessedPage;
2411 /** HC: The number of pages marked read-only for dirty bit tracking. */
2412 STAMCOUNTER StatHCDirtyPage;
2413 /** HC: The number of pages marked read-only for dirty bit tracking. */
2414 STAMCOUNTER StatHCDirtyPageBig;
2415 /** HC: The number of traps generated for dirty bit tracking. */
2416 STAMCOUNTER StatHCDirtyPageTrap;
2417 /** HC: The number of pages already dirty or readonly. */
2418 STAMCOUNTER StatHCDirtyPageSkipped;
2419
2420 /** GC: The number of pages marked not present for accessed bit emulation. */
2421 STAMCOUNTER StatGCAccessedPage;
2422 /** GC: The number of pages marked read-only for dirty bit tracking. */
2423 STAMCOUNTER StatGCDirtyPage;
2424 /** GC: The number of pages marked read-only for dirty bit tracking. */
2425 STAMCOUNTER StatGCDirtyPageBig;
2426 /** GC: The number of traps generated for dirty bit tracking. */
2427 STAMCOUNTER StatGCDirtyPageTrap;
2428 /** GC: The number of pages already dirty or readonly. */
2429 STAMCOUNTER StatGCDirtyPageSkipped;
2430 /** GC: The number of pages marked dirty because of write accesses. */
2431 STAMCOUNTER StatGCDirtiedPage;
2432 /** GC: The number of pages already marked dirty because of write accesses. */
2433 STAMCOUNTER StatGCPageAlreadyDirty;
2434 /** GC: The number of real pages faults during dirty bit tracking. */
2435 STAMCOUNTER StatGCDirtyTrackRealPF;
2436
2437 /** GC: Profiling of the PGMTrackDirtyBit() body */
2438 STAMPROFILE StatGCDirtyBitTracking;
2439 /** HC: Profiling of the PGMTrackDirtyBit() body */
2440 STAMPROFILE StatHCDirtyBitTracking;
2441
2442 /** GC: Profiling of the PGMGstModifyPage() body */
2443 STAMPROFILE StatGCGstModifyPage;
2444 /** HC: Profiling of the PGMGstModifyPage() body */
2445 STAMPROFILE StatHCGstModifyPage;
2446
2447 /** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2448 STAMCOUNTER StatGCSyncPagePDNAs;
2449 /** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2450 STAMCOUNTER StatGCSyncPagePDOutOfSync;
2451 /** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2452 STAMCOUNTER StatHCSyncPagePDNAs;
2453 /** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2454 STAMCOUNTER StatHCSyncPagePDOutOfSync;
2455
2456 STAMCOUNTER StatSynPT4kGC;
2457 STAMCOUNTER StatSynPT4kHC;
2458 STAMCOUNTER StatSynPT4MGC;
2459 STAMCOUNTER StatSynPT4MHC;
2460
2461 /** Profiling of the PGMFlushTLB() body. */
2462 STAMPROFILE StatFlushTLB;
2463 /** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2464 STAMCOUNTER StatFlushTLBNewCR3;
2465 /** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2466 STAMCOUNTER StatFlushTLBNewCR3Global;
2467 /** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2468 STAMCOUNTER StatFlushTLBSameCR3;
2469 /** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2470 STAMCOUNTER StatFlushTLBSameCR3Global;
2471
2472 STAMPROFILE StatGCSyncCR3; /**< GC: PGMSyncCR3() profiling. */
2473 STAMPROFILE StatGCSyncCR3Handlers; /**< GC: Profiling of the PGMSyncCR3() update handler section. */
2474 STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /**< GC: Profiling of the virtual handler resets. */
2475 STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /**< GC: Profiling of the virtual handler updates. */
2476 STAMCOUNTER StatGCSyncCR3Global; /**< GC: The number of global CR3 syncs. */
2477 STAMCOUNTER StatGCSyncCR3NotGlobal; /**< GC: The number of non-global CR3 syncs. */
2478 STAMCOUNTER StatGCSyncCR3DstFreed; /**< GC: The number of times we've had to free a shadow entry. */
2479 STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /**< GC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2480 STAMCOUNTER StatGCSyncCR3DstNotPresent; /**< GC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2481 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /**< GC: The number of times a global page directory wasn't flushed. */
2482 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /**< GC: The number of times a page table with only global entries wasn't flushed. */
2483 STAMCOUNTER StatGCSyncCR3DstCacheHit; /**< GC: The number of times we got some kind of cache hit on a page table. */
2484
2485 STAMPROFILE StatHCSyncCR3; /**< HC: PGMSyncCR3() profiling. */
2486 STAMPROFILE StatHCSyncCR3Handlers; /**< HC: Profiling of the PGMSyncCR3() update handler section. */
2487 STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /**< HC: Profiling of the virtual handler resets. */
2488 STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /**< HC: Profiling of the virtual handler updates. */
2489 STAMCOUNTER StatHCSyncCR3Global; /**< HC: The number of global CR3 syncs. */
2490 STAMCOUNTER StatHCSyncCR3NotGlobal; /**< HC: The number of non-global CR3 syncs. */
2491 STAMCOUNTER StatHCSyncCR3DstFreed; /**< HC: The number of times we've had to free a shadow entry. */
2492 STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /**< HC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2493 STAMCOUNTER StatHCSyncCR3DstNotPresent; /**< HC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2494 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /**< HC: The number of times a global page directory wasn't flushed. */
2495 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /**< HC: The number of times a page table with only global entries wasn't flushed. */
2496 STAMCOUNTER StatHCSyncCR3DstCacheHit; /**< HC: The number of times we got some kind of cache hit on a page table. */
2497
2498 /** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2499 STAMPROFILE StatVirtHandleSearchByPhysGC;
2500 /** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2501 STAMPROFILE StatVirtHandleSearchByPhysHC;
2502 /** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2503 STAMCOUNTER StatHandlePhysicalReset;
2504
2505 STAMPROFILE StatCheckPageFault;
2506 STAMPROFILE StatLazySyncPT;
2507 STAMPROFILE StatMapping;
2508 STAMPROFILE StatOutOfSync;
2509 STAMPROFILE StatHandlers;
2510 STAMPROFILE StatEIPHandlers;
2511 STAMPROFILE StatHCPrefetch;
2512
2513# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2514 /** The number of first time shadowings. */
2515 STAMCOUNTER StatTrackVirgin;
2516 /** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2517 STAMCOUNTER StatTrackAliased;
2518 /** The number of times we're tracking using cRef2. */
2519 STAMCOUNTER StatTrackAliasedMany;
2520 /** The number of times we're hitting pages which has overflowed cRef2. */
2521 STAMCOUNTER StatTrackAliasedLots;
2522 /** The number of times the extent list grows to long. */
2523 STAMCOUNTER StatTrackOverflows;
2524 /** Profiling of SyncPageWorkerTrackDeref (expensive). */
2525 STAMPROFILE StatTrackDeref;
2526# endif
2527
2528 /** Ring-3/0 page mapper TLB hits. */
2529 STAMCOUNTER StatPageHCMapTlbHits;
2530 /** Ring-3/0 page mapper TLB misses. */
2531 STAMCOUNTER StatPageHCMapTlbMisses;
2532 /** Ring-3/0 chunk mapper TLB hits. */
2533 STAMCOUNTER StatChunkR3MapTlbHits;
2534 /** Ring-3/0 chunk mapper TLB misses. */
2535 STAMCOUNTER StatChunkR3MapTlbMisses;
2536 /** Times a shared page has been replaced by a private one. */
2537 STAMCOUNTER StatPageReplaceShared;
2538 /** Times the zero page has been replaced by a private one. */
2539 STAMCOUNTER StatPageReplaceZero;
2540 /** The number of times we've executed GMMR3AllocateHandyPages. */
2541 STAMCOUNTER StatPageHandyAllocs;
2542
2543 /** Allocated mbs of guest ram */
2544 STAMCOUNTER StatDynRamTotal;
2545 /** Nr of pgmr3PhysGrowRange calls. */
2546 STAMCOUNTER StatDynRamGrow;
2547
2548 STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2549 STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2550 STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2551#endif
2552} PGM, *PPGM;
2553
2554
2555/** @name PGM::fSyncFlags Flags
2556 * @{
2557 */
2558/** Updates the virtual access handler state bit in PGMPAGE. */
2559#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2560/** Always sync CR3. */
2561#define PGM_SYNC_ALWAYS RT_BIT(1)
2562/** Check monitoring on next CR3 (re)load and invalidate page. */
2563#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2564/** Clear the page pool (a light weight flush). */
2565#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2566/** @} */
2567
2568
2569__BEGIN_DECLS
2570
2571int pgmLock(PVM pVM);
2572void pgmUnlock(PVM pVM);
2573
2574PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2575PGMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2576int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
2577
2578int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, int iPDOld);
2579PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2580void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, int iPDOld, int iPDNew);
2581DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2582
2583void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2584int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2585DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2586#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2587void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2588#else
2589# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2590#endif
2591DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2592
2593
2594void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2595int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2596int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2597int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2598#ifdef IN_RING3
2599int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2600int pgmR3PhysRamReset(PVM pVM);
2601int pgmR3PhysRomReset(PVM pVM);
2602#ifndef VBOX_WITH_NEW_PHYS_CODE
2603int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2604#endif
2605
2606int pgmR3PoolInit(PVM pVM);
2607void pgmR3PoolRelocate(PVM pVM);
2608void pgmR3PoolReset(PVM pVM);
2609
2610#endif /* IN_RING3 */
2611#ifdef IN_GC
2612void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2613#endif
2614int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage);
2615PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2616void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable);
2617void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
2618int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2619void pgmPoolFlushAll(PVM pVM);
2620void pgmPoolClearAll(PVM pVM);
2621void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2622void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2623int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2624PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2625void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2626void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2627uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2628void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2629#ifdef PGMPOOL_WITH_MONITORING
2630# ifdef IN_RING3
2631void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2632# else
2633void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2634# endif
2635int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2636void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2637void pgmPoolMonitorModifiedClearAll(PVM pVM);
2638int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2639int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2640#endif
2641
2642__END_DECLS
2643
2644
2645/**
2646 * Gets the PGMRAMRANGE structure for a guest page.
2647 *
2648 * @returns Pointer to the RAM range on success.
2649 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2650 *
2651 * @param pPGM PGM handle.
2652 * @param GCPhys The GC physical address.
2653 */
2654DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2655{
2656 /*
2657 * Optimize for the first range.
2658 */
2659 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2660 RTGCPHYS off = GCPhys - pRam->GCPhys;
2661 if (RT_UNLIKELY(off >= pRam->cb))
2662 {
2663 do
2664 {
2665 pRam = CTXALLSUFF(pRam->pNext);
2666 if (RT_UNLIKELY(!pRam))
2667 break;
2668 off = GCPhys - pRam->GCPhys;
2669 } while (off >= pRam->cb);
2670 }
2671 return pRam;
2672}
2673
2674
2675/**
2676 * Gets the PGMPAGE structure for a guest page.
2677 *
2678 * @returns Pointer to the page on success.
2679 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2680 *
2681 * @param pPGM PGM handle.
2682 * @param GCPhys The GC physical address.
2683 */
2684DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2685{
2686 /*
2687 * Optimize for the first range.
2688 */
2689 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2690 RTGCPHYS off = GCPhys - pRam->GCPhys;
2691 if (RT_UNLIKELY(off >= pRam->cb))
2692 {
2693 do
2694 {
2695 pRam = CTXALLSUFF(pRam->pNext);
2696 if (RT_UNLIKELY(!pRam))
2697 return NULL;
2698 off = GCPhys - pRam->GCPhys;
2699 } while (off >= pRam->cb);
2700 }
2701 return &pRam->aPages[off >> PAGE_SHIFT];
2702}
2703
2704
2705/**
2706 * Gets the PGMPAGE structure for a guest page.
2707 *
2708 * Old Phys code: Will make sure the page is present.
2709 *
2710 * @returns VBox status code.
2711 * @retval VINF_SUCCESS and a valid *ppPage on success.
2712 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2713 *
2714 * @param pPGM PGM handle.
2715 * @param GCPhys The GC physical address.
2716 * @param ppPage Where to store the page poitner on success.
2717 */
2718DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2719{
2720 /*
2721 * Optimize for the first range.
2722 */
2723 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2724 RTGCPHYS off = GCPhys - pRam->GCPhys;
2725 if (RT_UNLIKELY(off >= pRam->cb))
2726 {
2727 do
2728 {
2729 pRam = CTXALLSUFF(pRam->pNext);
2730 if (RT_UNLIKELY(!pRam))
2731 {
2732 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2733 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2734 }
2735 off = GCPhys - pRam->GCPhys;
2736 } while (off >= pRam->cb);
2737 }
2738 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2739#ifndef VBOX_WITH_NEW_PHYS_CODE
2740
2741 /*
2742 * Make sure it's present.
2743 */
2744 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2745 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2746 {
2747#ifdef IN_RING3
2748 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2749#else
2750 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2751#endif
2752 if (VBOX_FAILURE(rc))
2753 {
2754 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2755 return rc;
2756 }
2757 Assert(rc == VINF_SUCCESS);
2758 }
2759#endif
2760 return VINF_SUCCESS;
2761}
2762
2763
2764
2765
2766/**
2767 * Gets the PGMPAGE structure for a guest page.
2768 *
2769 * Old Phys code: Will make sure the page is present.
2770 *
2771 * @returns VBox status code.
2772 * @retval VINF_SUCCESS and a valid *ppPage on success.
2773 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2774 *
2775 * @param pPGM PGM handle.
2776 * @param GCPhys The GC physical address.
2777 * @param ppPage Where to store the page poitner on success.
2778 * @param ppRamHint Where to read and store the ram list hint.
2779 * The caller initializes this to NULL before the call.
2780 */
2781DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2782{
2783 RTGCPHYS off;
2784 PPGMRAMRANGE pRam = *ppRamHint;
2785 if ( !pRam
2786 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2787 {
2788 pRam = CTXALLSUFF(pPGM->pRamRanges);
2789 off = GCPhys - pRam->GCPhys;
2790 if (RT_UNLIKELY(off >= pRam->cb))
2791 {
2792 do
2793 {
2794 pRam = CTXALLSUFF(pRam->pNext);
2795 if (RT_UNLIKELY(!pRam))
2796 {
2797 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2798 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2799 }
2800 off = GCPhys - pRam->GCPhys;
2801 } while (off >= pRam->cb);
2802 }
2803 *ppRamHint = pRam;
2804 }
2805 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2806#ifndef VBOX_WITH_NEW_PHYS_CODE
2807
2808 /*
2809 * Make sure it's present.
2810 */
2811 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2812 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2813 {
2814#ifdef IN_RING3
2815 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2816#else
2817 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2818#endif
2819 if (VBOX_FAILURE(rc))
2820 {
2821 *ppPage = NULL; /* Shut up annoying smart ass. */
2822 return rc;
2823 }
2824 Assert(rc == VINF_SUCCESS);
2825 }
2826#endif
2827 return VINF_SUCCESS;
2828}
2829
2830
2831/**
2832 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2833 *
2834 * @returns Pointer to the page on success.
2835 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2836 *
2837 * @param pPGM PGM handle.
2838 * @param GCPhys The GC physical address.
2839 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2840 */
2841DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2842{
2843 /*
2844 * Optimize for the first range.
2845 */
2846 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2847 RTGCPHYS off = GCPhys - pRam->GCPhys;
2848 if (RT_UNLIKELY(off >= pRam->cb))
2849 {
2850 do
2851 {
2852 pRam = CTXALLSUFF(pRam->pNext);
2853 if (RT_UNLIKELY(!pRam))
2854 return NULL;
2855 off = GCPhys - pRam->GCPhys;
2856 } while (off >= pRam->cb);
2857 }
2858 *ppRam = pRam;
2859 return &pRam->aPages[off >> PAGE_SHIFT];
2860}
2861
2862
2863
2864
2865/**
2866 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2867 *
2868 * @returns Pointer to the page on success.
2869 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2870 *
2871 * @param pPGM PGM handle.
2872 * @param GCPhys The GC physical address.
2873 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2874 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2875 */
2876DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2877{
2878 /*
2879 * Optimize for the first range.
2880 */
2881 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2882 RTGCPHYS off = GCPhys - pRam->GCPhys;
2883 if (RT_UNLIKELY(off >= pRam->cb))
2884 {
2885 do
2886 {
2887 pRam = CTXALLSUFF(pRam->pNext);
2888 if (RT_UNLIKELY(!pRam))
2889 {
2890 *ppRam = NULL; /* Shut up silly GCC warnings. */
2891 *ppPage = NULL; /* ditto */
2892 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2893 }
2894 off = GCPhys - pRam->GCPhys;
2895 } while (off >= pRam->cb);
2896 }
2897 *ppRam = pRam;
2898 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2899#ifndef VBOX_WITH_NEW_PHYS_CODE
2900
2901 /*
2902 * Make sure it's present.
2903 */
2904 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2905 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2906 {
2907#ifdef IN_RING3
2908 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2909#else
2910 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2911#endif
2912 if (VBOX_FAILURE(rc))
2913 {
2914 *ppPage = NULL; /* Shut up silly GCC warnings. */
2915 *ppPage = NULL; /* ditto */
2916 return rc;
2917 }
2918 Assert(rc == VINF_SUCCESS);
2919
2920 }
2921#endif
2922 return VINF_SUCCESS;
2923}
2924
2925
2926/**
2927 * Convert GC Phys to HC Phys.
2928 *
2929 * @returns VBox status.
2930 * @param pPGM PGM handle.
2931 * @param GCPhys The GC physical address.
2932 * @param pHCPhys Where to store the corresponding HC physical address.
2933 *
2934 * @deprecated Doesn't deal with zero, shared or write monitored pages.
2935 * Avoid when writing new code!
2936 */
2937DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2938{
2939 PPGMPAGE pPage;
2940 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2941 if (VBOX_FAILURE(rc))
2942 return rc;
2943 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
2944 return VINF_SUCCESS;
2945}
2946
2947
2948#ifndef IN_GC
2949/**
2950 * Queries the Physical TLB entry for a physical guest page,
2951 * attemting to load the TLB entry if necessary.
2952 *
2953 * @returns VBox status code.
2954 * @retval VINF_SUCCESS on success
2955 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2956 * @param pPGM The PGM instance handle.
2957 * @param GCPhys The address of the guest page.
2958 * @param ppTlbe Where to store the pointer to the TLB entry.
2959 */
2960
2961DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2962{
2963 int rc;
2964 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2965 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2966 {
2967 STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
2968 rc = VINF_SUCCESS;
2969 }
2970 else
2971 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
2972 *ppTlbe = pTlbe;
2973 return rc;
2974}
2975#endif /* !IN_GC */
2976
2977
2978#ifndef VBOX_WITH_NEW_PHYS_CODE
2979/**
2980 * Convert GC Phys to HC Virt.
2981 *
2982 * @returns VBox status.
2983 * @param pPGM PGM handle.
2984 * @param GCPhys The GC physical address.
2985 * @param pHCPtr Where to store the corresponding HC virtual address.
2986 *
2987 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
2988 */
2989DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2990{
2991 PPGMRAMRANGE pRam;
2992 PPGMPAGE pPage;
2993 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2994 if (VBOX_FAILURE(rc))
2995 {
2996 *pHCPtr = 0; /* Shut up silly GCC warnings. */
2997 return rc;
2998 }
2999 RTGCPHYS off = GCPhys - pRam->GCPhys;
3000
3001 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3002 {
3003 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3004 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3005 return VINF_SUCCESS;
3006 }
3007 if (pRam->pvHC)
3008 {
3009 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3010 return VINF_SUCCESS;
3011 }
3012 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3013 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3014}
3015#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3016
3017
3018/**
3019 * Convert GC Phys to HC Virt.
3020 *
3021 * @returns VBox status.
3022 * @param PVM VM handle.
3023 * @param pRam Ram range
3024 * @param GCPhys The GC physical address.
3025 * @param pHCPtr Where to store the corresponding HC virtual address.
3026 *
3027 * @deprecated This will be eliminated. Don't use it.
3028 */
3029DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3030{
3031 RTGCPHYS off = GCPhys - pRam->GCPhys;
3032 Assert(off < pRam->cb);
3033
3034 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3035 {
3036 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3037 /* Physical chunk in dynamically allocated range not present? */
3038 if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
3039 {
3040#ifdef IN_RING3
3041 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3042#else
3043 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3044#endif
3045 if (rc != VINF_SUCCESS)
3046 {
3047 *pHCPtr = 0; /* GCC crap */
3048 return rc;
3049 }
3050 }
3051 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3052 return VINF_SUCCESS;
3053 }
3054 if (pRam->pvHC)
3055 {
3056 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3057 return VINF_SUCCESS;
3058 }
3059 *pHCPtr = 0; /* GCC crap */
3060 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3061}
3062
3063
3064/**
3065 * Convert GC Phys to HC Virt and HC Phys.
3066 *
3067 * @returns VBox status.
3068 * @param pPGM PGM handle.
3069 * @param GCPhys The GC physical address.
3070 * @param pHCPtr Where to store the corresponding HC virtual address.
3071 * @param pHCPhys Where to store the HC Physical address and its flags.
3072 *
3073 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3074 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3075 */
3076DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3077{
3078 PPGMRAMRANGE pRam;
3079 PPGMPAGE pPage;
3080 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3081 if (VBOX_FAILURE(rc))
3082 {
3083 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3084 *pHCPhys = 0; /* ditto */
3085 return rc;
3086 }
3087 RTGCPHYS off = GCPhys - pRam->GCPhys;
3088
3089 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3090 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3091 {
3092 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3093 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3094 return VINF_SUCCESS;
3095 }
3096 if (pRam->pvHC)
3097 {
3098 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3099 return VINF_SUCCESS;
3100 }
3101 *pHCPtr = 0;
3102 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3103}
3104
3105
3106/**
3107 * Clears flags associated with a RAM address.
3108 *
3109 * @returns VBox status code.
3110 * @param pPGM PGM handle.
3111 * @param GCPhys Guest context physical address.
3112 * @param fFlags fFlags to clear. (Bits 0-11.)
3113 */
3114DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3115{
3116 PPGMPAGE pPage;
3117 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3118 if (VBOX_FAILURE(rc))
3119 return rc;
3120
3121 fFlags &= ~X86_PTE_PAE_PG_MASK;
3122 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3123 return VINF_SUCCESS;
3124}
3125
3126
3127/**
3128 * Clears flags associated with a RAM address.
3129 *
3130 * @returns VBox status code.
3131 * @param pPGM PGM handle.
3132 * @param GCPhys Guest context physical address.
3133 * @param fFlags fFlags to clear. (Bits 0-11.)
3134 * @param ppRamHint Where to read and store the ram list hint.
3135 * The caller initializes this to NULL before the call.
3136 */
3137DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3138{
3139 PPGMPAGE pPage;
3140 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3141 if (VBOX_FAILURE(rc))
3142 return rc;
3143
3144 fFlags &= ~X86_PTE_PAE_PG_MASK;
3145 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3146 return VINF_SUCCESS;
3147}
3148
3149/**
3150 * Sets (bitwise OR) flags associated with a RAM address.
3151 *
3152 * @returns VBox status code.
3153 * @param pPGM PGM handle.
3154 * @param GCPhys Guest context physical address.
3155 * @param fFlags fFlags to set clear. (Bits 0-11.)
3156 */
3157DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3158{
3159 PPGMPAGE pPage;
3160 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3161 if (VBOX_FAILURE(rc))
3162 return rc;
3163
3164 fFlags &= ~X86_PTE_PAE_PG_MASK;
3165 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3166 return VINF_SUCCESS;
3167}
3168
3169
3170/**
3171 * Sets (bitwise OR) flags associated with a RAM address.
3172 *
3173 * @returns VBox status code.
3174 * @param pPGM PGM handle.
3175 * @param GCPhys Guest context physical address.
3176 * @param fFlags fFlags to set clear. (Bits 0-11.)
3177 * @param ppRamHint Where to read and store the ram list hint.
3178 * The caller initializes this to NULL before the call.
3179 */
3180DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3181{
3182 PPGMPAGE pPage;
3183 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3184 if (VBOX_FAILURE(rc))
3185 return rc;
3186
3187 fFlags &= ~X86_PTE_PAE_PG_MASK;
3188 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3189 return VINF_SUCCESS;
3190}
3191
3192
3193/**
3194 * Gets the page directory for the specified address.
3195 *
3196 * @returns Pointer to the page directory in question.
3197 * @returns NULL if the page directory is not present or on an invalid page.
3198 * @param pPGM Pointer to the PGM instance data.
3199 * @param GCPtr The address.
3200 */
3201DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3202{
3203 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3204 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3205 {
3206 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3207 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3208
3209 /* cache is out-of-sync. */
3210 PX86PDPAE pPD;
3211 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3212 if (VBOX_SUCCESS(rc))
3213 return pPD;
3214 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3215 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3216 }
3217 return NULL;
3218}
3219
3220
3221/**
3222 * Gets the page directory entry for the specified address.
3223 *
3224 * @returns Pointer to the page directory entry in question.
3225 * @returns NULL if the page directory is not present or on an invalid page.
3226 * @param pPGM Pointer to the PGM instance data.
3227 * @param GCPtr The address.
3228 */
3229DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3230{
3231 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3232 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3233 {
3234 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3235 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3236 return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3237
3238 /* The cache is out-of-sync. */
3239 PX86PDPAE pPD;
3240 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3241 if (VBOX_SUCCESS(rc))
3242 return &pPD->a[iPD];
3243 AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3244 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3245 }
3246 return NULL;
3247}
3248
3249
3250/**
3251 * Gets the page directory entry for the specified address.
3252 *
3253 * @returns The page directory entry in question.
3254 * @returns A non-present entry if the page directory is not present or on an invalid page.
3255 * @param pPGM Pointer to the PGM instance data.
3256 * @param GCPtr The address.
3257 */
3258DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3259{
3260 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3261 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3262 {
3263 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3264 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3265 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3266
3267 /* cache is out-of-sync. */
3268 PX86PDPAE pPD;
3269 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3270 if (VBOX_SUCCESS(rc))
3271 return pPD->a[iPD].u;
3272 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3273 }
3274 return 0ULL;
3275}
3276
3277
3278/**
3279 * Gets the page directory pointer table entry for the specified address
3280 * and returns the index into the page directory
3281 *
3282 * @returns Pointer to the page directory in question.
3283 * @returns NULL if the page directory is not present or on an invalid page.
3284 * @param pPGM Pointer to the PGM instance data.
3285 * @param GCPtr The address.
3286 * @param piPD Receives the index into the returned page directory
3287 */
3288DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3289{
3290 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3291 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3292 {
3293 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3294 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3295 {
3296 *piPD = iPD;
3297 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3298 }
3299
3300 /* cache is out-of-sync. */
3301 PX86PDPAE pPD;
3302 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3303 if (VBOX_SUCCESS(rc))
3304 {
3305 *piPD = iPD;
3306 return pPD;
3307 }
3308 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3309 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3310 }
3311 return NULL;
3312}
3313
3314
3315/**
3316 * Checks if any of the specified page flags are set for the given page.
3317 *
3318 * @returns true if any of the flags are set.
3319 * @returns false if all the flags are clear.
3320 * @param pPGM PGM handle.
3321 * @param GCPhys The GC physical address.
3322 * @param fFlags The flags to check for.
3323 */
3324DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3325{
3326 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3327 return pPage
3328 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3329}
3330
3331
3332/**
3333 * Gets the page state for a physical handler.
3334 *
3335 * @returns The physical handler page state.
3336 * @param pCur The physical handler in question.
3337 */
3338DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3339{
3340 switch (pCur->enmType)
3341 {
3342 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3343 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3344
3345 case PGMPHYSHANDLERTYPE_MMIO:
3346 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3347 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3348
3349 default:
3350 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3351 }
3352}
3353
3354
3355/**
3356 * Gets the page state for a virtual handler.
3357 *
3358 * @returns The virtual handler page state.
3359 * @param pCur The virtual handler in question.
3360 * @remarks This should never be used on a hypervisor access handler.
3361 */
3362DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3363{
3364 switch (pCur->enmType)
3365 {
3366 case PGMVIRTHANDLERTYPE_WRITE:
3367 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3368 case PGMVIRTHANDLERTYPE_ALL:
3369 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3370 default:
3371 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3372 }
3373}
3374
3375
3376/**
3377 * Clears one physical page of a virtual handler
3378 *
3379 * @param pPGM Pointer to the PGM instance.
3380 * @param pCur Virtual handler structure
3381 * @param iPage Physical page index
3382 *
3383 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3384 * need to care about other handlers in the same page.
3385 */
3386DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3387{
3388 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3389
3390 /*
3391 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
3392 */
3393#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3394 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3395 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3396 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3397#endif
3398 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3399 {
3400 /* We're the head of the alias chain. */
3401 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3402#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3403 AssertReleaseMsg(pRemove != NULL,
3404 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3405 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3406 AssertReleaseMsg(pRemove == pPhys2Virt,
3407 ("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3408 " got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3409 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3410 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3411#endif
3412 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3413 {
3414 /* Insert the next list in the alias chain into the tree. */
3415 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3416#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3417 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3418 ("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3419 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3420#endif
3421 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
3422 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3423 AssertRelease(fRc);
3424 }
3425 }
3426 else
3427 {
3428 /* Locate the previous node in the alias chain. */
3429 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3430#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3431 AssertReleaseMsg(pPrev != pPhys2Virt,
3432 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3433 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3434#endif
3435 for (;;)
3436 {
3437 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3438 if (pNext == pPhys2Virt)
3439 {
3440 /* unlink. */
3441 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3442 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3443 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3444 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3445 else
3446 {
3447 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3448 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3449 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3450 }
3451 break;
3452 }
3453
3454 /* next */
3455 if (pNext == pPrev)
3456 {
3457#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3458 AssertReleaseMsg(pNext != pPrev,
3459 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3460 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3461#endif
3462 break;
3463 }
3464 pPrev = pNext;
3465 }
3466 }
3467 Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3468 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3469 pPhys2Virt->offNextAlias = 0;
3470 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3471
3472 /*
3473 * Clear the ram flags for this page.
3474 */
3475 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3476 AssertReturnVoid(pPage);
3477 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3478}
3479
3480
3481/**
3482 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3483 *
3484 * @returns Pointer to the shadow page structure.
3485 * @param pPool The pool.
3486 * @param HCPhys The HC physical address of the shadow page.
3487 */
3488DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3489{
3490 /*
3491 * Look up the page.
3492 */
3493 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3494 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3495 return pPage;
3496}
3497
3498
3499/**
3500 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3501 *
3502 * @returns Pointer to the shadow page structure.
3503 * @param pPool The pool.
3504 * @param idx The pool page index.
3505 */
3506DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3507{
3508 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3509 return &pPool->aPages[idx];
3510}
3511
3512
3513#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3514/**
3515 * Clear references to guest physical memory.
3516 *
3517 * @param pPool The pool.
3518 * @param pPoolPage The pool page.
3519 * @param pPhysPage The physical guest page tracking structure.
3520 */
3521DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3522{
3523 /*
3524 * Just deal with the simple case here.
3525 */
3526#ifdef LOG_ENABLED
3527 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3528#endif
3529 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3530 if (cRefs == 1)
3531 {
3532 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3533 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3534 }
3535 else
3536 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3537 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3538}
3539#endif
3540
3541
3542#ifdef PGMPOOL_WITH_CACHE
3543/**
3544 * Moves the page to the head of the age list.
3545 *
3546 * This is done when the cached page is used in one way or another.
3547 *
3548 * @param pPool The pool.
3549 * @param pPage The cached page.
3550 * @todo inline in PGMInternal.h!
3551 */
3552DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3553{
3554 /*
3555 * Move to the head of the age list.
3556 */
3557 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3558 {
3559 /* unlink */
3560 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3561 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3562 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3563 else
3564 pPool->iAgeTail = pPage->iAgePrev;
3565
3566 /* insert at head */
3567 pPage->iAgePrev = NIL_PGMPOOL_IDX;
3568 pPage->iAgeNext = pPool->iAgeHead;
3569 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3570 pPool->iAgeHead = pPage->idx;
3571 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3572 }
3573}
3574#endif /* PGMPOOL_WITH_CACHE */
3575
3576/**
3577 * Tells if mappings are to be put into the shadow page table or not
3578 *
3579 * @returns boolean result
3580 * @param pVM VM handle.
3581 */
3582
3583DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3584{
3585 return !pPGM->fDisableMappings;
3586}
3587
3588/** @} */
3589
3590#endif
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