VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 6347

Last change on this file since 6347 was 5999, checked in by vboxsync, 17 years ago

The Giant CDDL Dual-License Header Change.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 128.6 KB
Line 
1/* $Id: PGMInternal.h 5999 2007-12-07 15:05:06Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/stam.h>
25#include <VBox/param.h>
26#include <VBox/vmm.h>
27#include <VBox/mm.h>
28#include <VBox/pdmcritsect.h>
29#include <VBox/pdmapi.h>
30#include <VBox/dis.h>
31#include <VBox/dbgf.h>
32#include <VBox/log.h>
33#include <VBox/gmm.h>
34#include <iprt/avl.h>
35#include <iprt/assert.h>
36#include <iprt/critsect.h>
37
38#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
39# error "Not in PGM! This is an internal header!"
40#endif
41
42
43/** @defgroup grp_pgm_int Internals
44 * @ingroup grp_pgm
45 * @internal
46 * @{
47 */
48
49
50/** @name PGM Compile Time Config
51 * @{
52 */
53
54/**
55 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
56 * Comment it if it will break something.
57 */
58#define PGM_OUT_OF_SYNC_IN_GC
59
60/**
61 * Virtualize the dirty bit
62 * This also makes a half-hearted attempt at the accessed bit. For full
63 * accessed bit virtualization define PGM_SYNC_ACCESSED_BIT.
64 */
65#define PGM_SYNC_DIRTY_BIT
66
67/**
68 * Fully virtualize the accessed bit.
69 * @remark This requires SYNC_DIRTY_ACCESSED_BITS to be defined!
70 */
71#define PGM_SYNC_ACCESSED_BIT
72
73/**
74 * Check and skip global PDEs for non-global flushes
75 */
76#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
77
78/**
79 * Sync N pages instead of a whole page table
80 */
81#define PGM_SYNC_N_PAGES
82
83/**
84 * Number of pages to sync during a page fault
85 *
86 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
87 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
88 */
89#define PGM_SYNC_NR_PAGES 8
90
91/**
92 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
93 */
94#define PGM_MAX_PHYSCACHE_ENTRIES 64
95#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
96
97/**
98 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
99 */
100#define PGM_PHYSMEMACCESS_CACHING
101
102/*
103 * Assert Sanity.
104 */
105#if defined(PGM_SYNC_ACCESSED_BIT) && !defined(PGM_SYNC_DIRTY_BIT)
106# error "PGM_SYNC_ACCESSED_BIT requires PGM_SYNC_DIRTY_BIT!"
107#endif
108
109/** @def PGMPOOL_WITH_CACHE
110 * Enable agressive caching using the page pool.
111 *
112 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
113 */
114#define PGMPOOL_WITH_CACHE
115
116/** @def PGMPOOL_WITH_MIXED_PT_CR3
117 * When defined, we'll deal with 'uncachable' pages.
118 */
119#ifdef PGMPOOL_WITH_CACHE
120# define PGMPOOL_WITH_MIXED_PT_CR3
121#endif
122
123/** @def PGMPOOL_WITH_MONITORING
124 * Monitor the guest pages which are shadowed.
125 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
126 * be enabled as well.
127 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
128 */
129#ifdef PGMPOOL_WITH_CACHE
130# define PGMPOOL_WITH_MONITORING
131#endif
132
133/** @def PGMPOOL_WITH_GCPHYS_TRACKING
134 * Tracking the of shadow pages mapping guest physical pages.
135 *
136 * This is very expensive, the current cache prototype is trying to figure out
137 * whether it will be acceptable with an agressive caching policy.
138 */
139#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
140# define PGMPOOL_WITH_GCPHYS_TRACKING
141#endif
142
143/** @def PGMPOOL_WITH_USER_TRACKNG
144 * Tracking users of shadow pages. This is required for the linking of shadow page
145 * tables and physical guest addresses.
146 */
147#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
148# define PGMPOOL_WITH_USER_TRACKING
149#endif
150
151/** @def PGMPOOL_CFG_MAX_GROW
152 * The maximum number of pages to add to the pool in one go.
153 */
154#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
155
156/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
157 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
158 */
159#ifdef VBOX_STRICT
160# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
161#endif
162/** @} */
163
164
165/** @name PDPTR and PML4 flags.
166 * These are placed in the three bits available for system programs in
167 * the PDPTR and PML4 entries.
168 * @{ */
169/** The entry is a permanent one and it's must always be present.
170 * Never free such an entry. */
171#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172/** @} */
173
174/** @name Page directory flags.
175 * These are placed in the three bits available for system programs in
176 * the page directory entries.
177 * @{ */
178/** Mapping (hypervisor allocated pagetable). */
179#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
180/** Made read-only to facilitate dirty bit tracking. */
181#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
182/** @} */
183
184/** @name Page flags.
185 * These are placed in the three bits available for system programs in
186 * the page entries.
187 * @{ */
188/** Made read-only to facilitate dirty bit tracking. */
189#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
190
191#ifndef PGM_PTFLAGS_CSAM_VALIDATED
192/** Scanned and approved by CSAM (tm).
193 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
194 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
195#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
196#endif
197/** @} */
198
199/** @name Defines used to indicate the shadow and guest paging in the templates.
200 * @{ */
201#define PGM_TYPE_REAL 1
202#define PGM_TYPE_PROT 2
203#define PGM_TYPE_32BIT 3
204#define PGM_TYPE_PAE 4
205#define PGM_TYPE_AMD64 5
206/** @} */
207
208/** Macro for checking if the guest is using paging.
209 * @param uType PGM_TYPE_*
210 * @remark ASSUMES certain order of the PGM_TYPE_* values.
211 */
212#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT)
213
214
215/** @def PGM_HCPHYS_2_PTR
216 * Maps a HC physical page pool address to a virtual address.
217 *
218 * @returns VBox status code.
219 * @param pVM The VM handle.
220 * @param HCPhys The HC physical address to map to a virtual one.
221 * @param ppv Where to store the virtual address. No need to cast this.
222 *
223 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
224 * small page window employeed by that function. Be careful.
225 * @remark There is no need to assert on the result.
226 */
227#ifdef IN_GC
228# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
229#else
230# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
231#endif
232
233/** @def PGM_GCPHYS_2_PTR
234 * Maps a GC physical page address to a virtual address.
235 *
236 * @returns VBox status code.
237 * @param pVM The VM handle.
238 * @param GCPhys The GC physical address to map to a virtual one.
239 * @param ppv Where to store the virtual address. No need to cast this.
240 *
241 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
242 * small page window employeed by that function. Be careful.
243 * @remark There is no need to assert on the result.
244 */
245#ifdef IN_GC
246# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
247#else
248# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
249#endif
250
251/** @def PGM_GCPHYS_2_PTR_EX
252 * Maps a unaligned GC physical page address to a virtual address.
253 *
254 * @returns VBox status code.
255 * @param pVM The VM handle.
256 * @param GCPhys The GC physical address to map to a virtual one.
257 * @param ppv Where to store the virtual address. No need to cast this.
258 *
259 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
260 * small page window employeed by that function. Be careful.
261 * @remark There is no need to assert on the result.
262 */
263#ifdef IN_GC
264# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
265#else
266# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_INVL_PG
270 * Invalidates a page when in GC does nothing in HC.
271 *
272 * @param GCVirt The virtual address of the page to invalidate.
273 */
274#ifdef IN_GC
275# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
276#else
277# define PGM_INVL_PG(GCVirt) ((void)0)
278#endif
279
280/** @def PGM_INVL_BIG_PG
281 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
282 *
283 * @param GCVirt The virtual address within the page directory to invalidate.
284 */
285#ifdef IN_GC
286# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
287#else
288# define PGM_INVL_BIG_PG(GCVirt) ((void)0)
289#endif
290
291/** @def PGM_INVL_GUEST_TLBS()
292 * Invalidates all guest TLBs.
293 */
294#ifdef IN_GC
295# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
296#else
297# define PGM_INVL_GUEST_TLBS() ((void)0)
298#endif
299
300
301/**
302 * Structure for tracking GC Mappings.
303 *
304 * This structure is used by linked list in both GC and HC.
305 */
306typedef struct PGMMAPPING
307{
308 /** Pointer to next entry. */
309 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
310 /** Pointer to next entry. */
311 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
312 /** Pointer to next entry. */
313 GCPTRTYPE(struct PGMMAPPING *) pNextGC;
314 /** Start Virtual address. */
315 RTGCUINTPTR GCPtr;
316 /** Last Virtual address (inclusive). */
317 RTGCUINTPTR GCPtrLast;
318 /** Range size (bytes). */
319 RTGCUINTPTR cb;
320 /** Pointer to relocation callback function. */
321 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
322 /** User argument to the callback. */
323 R3PTRTYPE(void *) pvUser;
324 /** Mapping description / name. For easing debugging. */
325 R3PTRTYPE(const char *) pszDesc;
326 /** Number of page tables. */
327 RTUINT cPTs;
328#if HC_ARCH_BITS != GC_ARCH_BITS
329 RTUINT uPadding0; /**< Alignment padding. */
330#endif
331 /** Array of page table mapping data. Each entry
332 * describes one page table. The array can be longer
333 * than the declared length.
334 */
335 struct
336 {
337 /** The HC physical address of the page table. */
338 RTHCPHYS HCPhysPT;
339 /** The HC physical address of the first PAE page table. */
340 RTHCPHYS HCPhysPaePT0;
341 /** The HC physical address of the second PAE page table. */
342 RTHCPHYS HCPhysPaePT1;
343 /** The HC virtual address of the 32-bit page table. */
344 R3PTRTYPE(PVBOXPT) pPTR3;
345 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
346 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
347 /** The GC virtual address of the 32-bit page table. */
348 GCPTRTYPE(PVBOXPT) pPTGC;
349 /** The GC virtual address of the two PAE page table. */
350 GCPTRTYPE(PX86PTPAE) paPaePTsGC;
351 /** The GC virtual address of the 32-bit page table. */
352 R0PTRTYPE(PVBOXPT) pPTR0;
353 /** The GC virtual address of the two PAE page table. */
354 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
355 } aPTs[1];
356} PGMMAPPING;
357/** Pointer to structure for tracking GC Mappings. */
358typedef struct PGMMAPPING *PPGMMAPPING;
359
360
361/**
362 * Physical page access handler structure.
363 *
364 * This is used to keep track of physical address ranges
365 * which are being monitored in some kind of way.
366 */
367typedef struct PGMPHYSHANDLER
368{
369 AVLROGCPHYSNODECORE Core;
370 /** Alignment padding. */
371 uint32_t u32Padding;
372 /** Access type. */
373 PGMPHYSHANDLERTYPE enmType;
374 /** Number of pages to update. */
375 uint32_t cPages;
376 /** Pointer to R3 callback function. */
377 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
378 /** User argument for R3 handlers. */
379 R3PTRTYPE(void *) pvUserR3;
380 /** Pointer to R0 callback function. */
381 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
382 /** User argument for R0 handlers. */
383 R0PTRTYPE(void *) pvUserR0;
384 /** Pointer to GC callback function. */
385 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
386 /** User argument for GC handlers. */
387 GCPTRTYPE(void *) pvUserGC;
388 /** Description / Name. For easing debugging. */
389 R3PTRTYPE(const char *) pszDesc;
390#ifdef VBOX_WITH_STATISTICS
391 /** Profiling of this handler. */
392 STAMPROFILE Stat;
393#endif
394} PGMPHYSHANDLER;
395/** Pointer to a physical page access handler structure. */
396typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
397
398
399/**
400 * Cache node for the physical addresses covered by a virtual handler.
401 */
402typedef struct PGMPHYS2VIRTHANDLER
403{
404 /** Core node for the tree based on physical ranges. */
405 AVLROGCPHYSNODECORE Core;
406 /** Offset from this struct to the PGMVIRTHANDLER structure. */
407 RTGCINTPTR offVirtHandler;
408 /** Offset of the next alias relativer to this one.
409 * Bit 0 is used for indicating whether we're in the tree.
410 * Bit 1 is used for indicating that we're the head node.
411 */
412 int32_t offNextAlias;
413} PGMPHYS2VIRTHANDLER;
414/** Pointer to a phys to virtual handler structure. */
415typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
416
417/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
418 * node is in the tree. */
419#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
420/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
421 * node is in the head of an alias chain.
422 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
423#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
424/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
425#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
426
427
428/**
429 * Virtual page access handler structure.
430 *
431 * This is used to keep track of virtual address ranges
432 * which are being monitored in some kind of way.
433 */
434typedef struct PGMVIRTHANDLER
435{
436 /** Core node for the tree based on virtual ranges. */
437 AVLROGCPTRNODECORE Core;
438 /** Number of cache pages. */
439 uint32_t u32Padding;
440 /** Access type. */
441 PGMVIRTHANDLERTYPE enmType;
442 /** Number of cache pages. */
443 uint32_t cPages;
444
445/** @todo The next two members are redundant. It adds some readability though. */
446 /** Start of the range. */
447 RTGCPTR GCPtr;
448 /** End of the range (exclusive). */
449 RTGCPTR GCPtrLast;
450 /** Size of the range (in bytes). */
451 RTGCUINTPTR cb;
452 /** Pointer to the GC callback function. */
453 GCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
454 /** Pointer to the HC callback function for invalidation. */
455 R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
456 /** Pointer to the HC callback function. */
457 R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
458 /** Description / Name. For easing debugging. */
459 R3PTRTYPE(const char *) pszDesc;
460#ifdef VBOX_WITH_STATISTICS
461 /** Profiling of this handler. */
462 STAMPROFILE Stat;
463#endif
464 /** Array of cached physical addresses for the monitored ranged. */
465 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
466} PGMVIRTHANDLER;
467/** Pointer to a virtual page access handler structure. */
468typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
469
470
471/**
472 * A Physical Guest Page tracking structure.
473 *
474 * The format of this structure is complicated because we have to fit a lot
475 * of information into as few bits as possible. The format is also subject
476 * to change (there is one comming up soon). Which means that for we'll be
477 * using PGM_PAGE_GET_* and PGM_PAGE_SET_* macros for all accessess to the
478 * structure.
479 */
480typedef struct PGMPAGE
481{
482 /** The physical address and a whole lot of other stuff. All bits are used! */
483 RTHCPHYS HCPhys;
484 /** The page state. */
485 uint32_t u2State : 2;
486 /** Flag indicating that a write monitored page was written to when set. */
487 uint32_t fWrittenTo : 1;
488 /** For later. */
489 uint32_t fSomethingElse : 1;
490 /** The Page ID. */
491 uint32_t idPage : 28;
492 uint32_t u32B;
493} PGMPAGE;
494AssertCompileSize(PGMPAGE, 16);
495/** Pointer to a physical guest page. */
496typedef PGMPAGE *PPGMPAGE;
497/** Pointer to a const physical guest page. */
498typedef const PGMPAGE *PCPGMPAGE;
499/** Pointer to a physical guest page pointer. */
500typedef PPGMPAGE *PPPGMPAGE;
501
502/** @name The Page state, PGMPAGE::u2State.
503 * @{ */
504/** The zero page.
505 * This is a per-VM page that's never ever mapped writable. */
506#define PGM_PAGE_STATE_ZERO 0
507/** A allocated page.
508 * This is a per-VM page allocated from the page pool.
509 */
510#define PGM_PAGE_STATE_ALLOCATED 1
511/** A allocated page that's being monitored for writes.
512 * The shadow page table mappings are read-only. When a write occurs, the
513 * fWrittenTo member is set, the page remapped as read-write and the state
514 * moved back to allocated. */
515#define PGM_PAGE_STATE_WRITE_MONITORED 2
516/** The page is shared, aka. copy-on-write.
517 * This is a page that's shared with other VMs. */
518#define PGM_PAGE_STATE_SHARED 3
519/** @} */
520
521
522/**
523 * Gets the page state.
524 * @returns page state (PGM_PAGE_STATE_*).
525 * @param pPage Pointer to the physical guest page tracking structure.
526 */
527#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2State )
528
529/**
530 * Sets the page state.
531 * @param pPage Pointer to the physical guest page tracking structure.
532 * @param _uState The new page state.
533 */
534#define PGM_PAGE_SET_STATE(pPage, _uState) \
535 do { (pPage)->u2State = (_uState); } while (0)
536
537
538/**
539 * Gets the host physical address of the guest page.
540 * @returns host physical address (RTHCPHYS).
541 * @param pPage Pointer to the physical guest page tracking structure.
542 */
543#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
544
545/**
546 * Sets the host physical address of the guest page.
547 * @param pPage Pointer to the physical guest page tracking structure.
548 * @param _HCPhys The new host physical address.
549 */
550#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
551 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
552 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
553
554/**
555 * Get the Page ID.
556 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
557 * @param pPage Pointer to the physical guest page tracking structure.
558 */
559#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPage )
560/* later:
561#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
562 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
563*/
564/**
565 * Sets the Page ID.
566 * @param pPage Pointer to the physical guest page tracking structure.
567 */
568#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPage = (_idPage); } while (0)
569/* later:
570#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
571 | ((_idPage) & 0xfff) \
572 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
573*/
574
575/**
576 * Get the Chunk ID.
577 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
578 * @param pPage Pointer to the physical guest page tracking structure.
579 */
580#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPage >> GMM_CHUNKID_SHIFT )
581/* later:
582#if GMM_CHUNKID_SHIFT == 12
583# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
584#elif GMM_CHUNKID_SHIFT > 12
585# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
586#elif GMM_CHUNKID_SHIFT < 12
587# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
588 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
589#else
590# error "GMM_CHUNKID_SHIFT isn't defined or something."
591#endif
592*/
593
594/**
595 * Get the index of the page within the allocaiton chunk.
596 * @returns The page index.
597 * @param pPage Pointer to the physical guest page tracking structure.
598 */
599#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPage & (RT_BIT_32(GMM_CHUNKID_SHIFT) - 1) )
600/* later:
601#if GMM_CHUNKID_SHIFT <= 12
602# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & (RT_BIT_32(GMM_CHUNKID_SHIFT) - 1)) )
603#else
604# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
605 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
606#endif
607*/
608
609/**
610 * Checks if the page is 'reserved'.
611 * @returns true/false.
612 * @param pPage Pointer to the physical guest page tracking structure.
613 */
614#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
615
616/**
617 * Checks if the page is marked for MMIO.
618 * @returns true/false.
619 * @param pPage Pointer to the physical guest page tracking structure.
620 */
621#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
622
623/**
624 * Checks if the page is backed by the ZERO page.
625 * @returns true/false.
626 * @param pPage Pointer to the physical guest page tracking structure.
627 */
628#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2State == PGM_PAGE_STATE_ZERO )
629
630/**
631 * Checks if the page is backed by a SHARED page.
632 * @returns true/false.
633 * @param pPage Pointer to the physical guest page tracking structure.
634 */
635#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2State == PGM_PAGE_STATE_SHARED )
636
637
638
639/**
640 * Ram range for GC Phys to HC Phys conversion.
641 *
642 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
643 * conversions too, but we'll let MM handle that for now.
644 *
645 * This structure is used by linked lists in both GC and HC.
646 */
647typedef struct PGMRAMRANGE
648{
649 /** Pointer to the next RAM range - for HC. */
650 R3R0PTRTYPE(struct PGMRAMRANGE *) pNextHC;
651 /** Pointer to the next RAM range - for GC. */
652 GCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
653 /** Start of the range. Page aligned. */
654 RTGCPHYS GCPhys;
655 /** Last address in the range (inclusive). Page aligned (-1). */
656 RTGCPHYS GCPhysLast;
657 /** Size of the range. (Page aligned of course). */
658 RTGCPHYS cb;
659 /** MM_RAM_* flags */
660 uint32_t fFlags;
661
662 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
663 GCPTRTYPE(PRTHCPTR) pavHCChunkGC;
664 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
665 R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
666
667 /** Start of the HC mapping of the range.
668 * For pure MMIO and dynamically allocated ranges this is NULL, while for all ranges this is a valid pointer. */
669 R3PTRTYPE(void *) pvHC;
670
671 /** Array of physical guest page tracking structures. */
672 PGMPAGE aPages[1];
673} PGMRAMRANGE;
674/** Pointer to Ram range for GC Phys to HC Phys conversion. */
675typedef PGMRAMRANGE *PPGMRAMRANGE;
676
677/** Return hc ptr corresponding to the ram range and physical offset */
678#define PGMRAMRANGE_GETHCPTR(pRam, off) \
679 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
680 : (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
681
682/** @todo r=bird: fix typename. */
683/**
684 * PGMPhysRead/Write cache entry
685 */
686typedef struct PGMPHYSCACHE_ENTRY
687{
688 /** HC pointer to physical page */
689 R3PTRTYPE(uint8_t *) pbHC;
690 /** GC Physical address for cache entry */
691 RTGCPHYS GCPhys;
692#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
693 RTGCPHYS u32Padding0; /**< alignment padding. */
694#endif
695} PGMPHYSCACHE_ENTRY;
696
697/**
698 * PGMPhysRead/Write cache to reduce REM memory access overhead
699 */
700typedef struct PGMPHYSCACHE
701{
702 /** Bitmap of valid cache entries */
703 uint64_t aEntries;
704 /** Cache entries */
705 PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
706} PGMPHYSCACHE;
707
708
709/** Pointer to an allocation chunk ring-3 mapping. */
710typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
711/** Pointer to an allocation chunk ring-3 mapping pointer. */
712typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
713
714/**
715 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
716 *
717 * The primary tree (Core) uses the chunk id as key.
718 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
719 */
720typedef struct PGMCHUNKR3MAP
721{
722 /** The key is the chunk id. */
723 AVLU32NODECORE Core;
724 /** The key is the ageing sequence number. */
725 AVLLU32NODECORE AgeCore;
726 /** The current age thingy. */
727 uint32_t iAge;
728 /** The current reference count. */
729 uint32_t volatile cRefs;
730 /** The current permanent reference count. */
731 uint32_t volatile cPermRefs;
732 /** The mapping address. */
733 void *pv;
734} PGMCHUNKR3MAP;
735
736/**
737 * Allocation chunk ring-3 mapping TLB entry.
738 */
739typedef struct PGMCHUNKR3MAPTLBE
740{
741 /** The chunk id. */
742 uint32_t volatile idChunk;
743#if HC_ARCH_BITS == 64
744 uint32_t u32Padding; /**< alignment padding. */
745#endif
746 /** The chunk map. */
747 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
748} PGMCHUNKR3MAPTLBE;
749/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
750typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
751
752/** The number of TLB entries in PGMCHUNKR3MAPTLB.
753 * @remark Must be a power of two value. */
754#define PGM_CHUNKR3MAPTLB_ENTRIES 32
755
756/**
757 * Allocation chunk ring-3 mapping TLB.
758 *
759 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
760 * At first glance this might look kinda odd since AVL trees are
761 * supposed to give the most optimial lookup times of all trees
762 * due to their balancing. However, take a tree with 1023 nodes
763 * in it, that's 10 levels, meaning that most searches has to go
764 * down 9 levels before they find what they want. This isn't fast
765 * compared to a TLB hit. There is the factor of cache misses,
766 * and of course the problem with trees and branch prediction.
767 * This is why we use TLBs in front of most of the trees.
768 *
769 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
770 * difficult when we switch to inlined AVL trees (from kStuff).
771 */
772typedef struct PGMCHUNKR3MAPTLB
773{
774 /** The TLB entries. */
775 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
776} PGMCHUNKR3MAPTLB;
777
778/**
779 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
780 * @returns Chunk TLB index.
781 * @param idChunk The Chunk ID.
782 */
783#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
784
785
786/**
787 * Ring-3 guest page mapping TLB entry.
788 * @remarks used in ring-0 as well at the moment.
789 */
790typedef struct PGMPAGER3MAPTLBE
791{
792 /** Address of the page. */
793 RTGCPHYS volatile GCPhys;
794#if HC_ARCH_BITS == 64
795 uint32_t u32Padding; /**< alignment padding. */
796#endif
797 /** The guest page. */
798 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
799 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
800 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
801 /** The address */
802 R3R0PTRTYPE(void *) volatile pv;
803} PGMPAGER3MAPTLBE;
804/** Pointer to an entry in the HC physical TLB. */
805typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
806
807
808/** The number of entries in the ring-3 guest page mapping TLB.
809 * @remarks The value must be a power of two. */
810#define PGM_PAGER3MAPTLB_ENTRIES 64
811
812/**
813 * Ring-3 guest page mapping TLB.
814 * @remarks used in ring-0 as well at the moment.
815 */
816typedef struct PGMPAGER3MAPTLB
817{
818 /** The TLB entries. */
819 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
820} PGMPAGER3MAPTLB;
821/** Pointer to the ring-3 guest page mapping TLB. */
822typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
823
824/**
825 * Calculates the index of the TLB entry for the specified guest page.
826 * @returns Physical TLB index.
827 * @param GCPhys The guest physical address.
828 */
829#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
830
831
832/** @name Context neutrual page mapper TLB.
833 *
834 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
835 * code is writting in a kind of context neutrual way. Time will show whether
836 * this actually makes sense or not...
837 *
838 * @{ */
839/** @typedef PPGMPAGEMAPTLB
840 * The page mapper TLB pointer type for the current context. */
841/** @typedef PPGMPAGEMAPTLB
842 * The page mapper TLB entry pointer type for the current context. */
843/** @typedef PPGMPAGEMAPTLB
844 * The page mapper TLB entry pointer pointer type for the current context. */
845/** @def PGMPAGEMAPTLB_ENTRIES
846 * The number of TLB entries in the page mapper TLB for the current context. */
847/** @def PGM_PAGEMAPTLB_IDX
848 * Calculate the TLB index for a guest physical address.
849 * @returns The TLB index.
850 * @param GCPhys The guest physical address. */
851/** @typedef PPGMPAGEMAP
852 * Pointer to a page mapper unit for current context. */
853/** @typedef PPPGMPAGEMAP
854 * Pointer to a page mapper unit pointer for current context. */
855#ifdef IN_GC
856// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
857// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
858// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
859# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
860# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
861 typedef void * PPGMPAGEMAP;
862 typedef void ** PPPGMPAGEMAP;
863//#elif IN_RING0
864// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
865// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
866// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
867//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
868//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
869// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
870// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
871#else
872 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
873 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
874 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
875# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
876# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
877 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
878 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
879#endif
880/** @} */
881
882
883/** @name PGM Pool Indexes.
884 * Aka. the unique shadow page identifier.
885 * @{ */
886/** NIL page pool IDX. */
887#define NIL_PGMPOOL_IDX 0
888/** The first normal index. */
889#define PGMPOOL_IDX_FIRST_SPECIAL 1
890/** Page directory (32-bit root). */
891#define PGMPOOL_IDX_PD 1
892/** The extended PAE page directory (2048 entries, works as root currently). */
893#define PGMPOOL_IDX_PAE_PD 2
894/** Page Directory Pointer Table (PAE root, not currently used). */
895#define PGMPOOL_IDX_PDPTR 3
896/** Page Map Level-4 (64-bit root). */
897#define PGMPOOL_IDX_PML4 4
898/** The first normal index. */
899#define PGMPOOL_IDX_FIRST 5
900/** The last valid index. (inclusive, 14 bits) */
901#define PGMPOOL_IDX_LAST 0x3fff
902/** @} */
903
904/** The NIL index for the parent chain. */
905#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
906
907/**
908 * Node in the chain linking a shadowed page to it's parent (user).
909 */
910#pragma pack(1)
911typedef struct PGMPOOLUSER
912{
913 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
914 uint16_t iNext;
915 /** The user page index. */
916 uint16_t iUser;
917 /** Index into the user table. */
918 uint16_t iUserTable;
919} PGMPOOLUSER, *PPGMPOOLUSER;
920typedef const PGMPOOLUSER *PCPGMPOOLUSER;
921#pragma pack()
922
923
924/** The NIL index for the phys ext chain. */
925#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
926
927/**
928 * Node in the chain of physical cross reference extents.
929 */
930#pragma pack(1)
931typedef struct PGMPOOLPHYSEXT
932{
933 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
934 uint16_t iNext;
935 /** The user page index. */
936 uint16_t aidx[3];
937} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
938typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
939#pragma pack()
940
941
942/**
943 * The kind of page that's being shadowed.
944 */
945typedef enum PGMPOOLKIND
946{
947 /** The virtual invalid 0 entry. */
948 PGMPOOLKIND_INVALID = 0,
949 /** The entry is free (=unused). */
950 PGMPOOLKIND_FREE,
951
952 /** Shw: 32-bit page table; Gst: no paging */
953 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
954 /** Shw: 32-bit page table; Gst: 32-bit page table. */
955 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
956 /** Shw: 32-bit page table; Gst: 4MB page. */
957 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
958 /** Shw: PAE page table; Gst: no paging */
959 PGMPOOLKIND_PAE_PT_FOR_PHYS,
960 /** Shw: PAE page table; Gst: 32-bit page table. */
961 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
962 /** Shw: PAE page table; Gst: Half of a 4MB page. */
963 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
964 /** Shw: PAE page table; Gst: PAE page table. */
965 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
966 /** Shw: PAE page table; Gst: 2MB page. */
967 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
968
969 /** Shw: PAE page directory; Gst: 32-bit page directory. */
970 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
971 /** Shw: PAE page directory; Gst: PAE page directory. */
972 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
973
974 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
975 PGMPOOLKIND_64BIT_PDPTR_FOR_64BIT_PDPTR,
976
977 /** Shw: Root 32-bit page directory. */
978 PGMPOOLKIND_ROOT_32BIT_PD,
979 /** Shw: Root PAE page directory */
980 PGMPOOLKIND_ROOT_PAE_PD,
981 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
982 PGMPOOLKIND_ROOT_PDPTR,
983 /** Shw: Root page map level-4 table. */
984 PGMPOOLKIND_ROOT_PML4,
985
986 /** The last valid entry. */
987 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
988} PGMPOOLKIND;
989
990
991/**
992 * The tracking data for a page in the pool.
993 */
994typedef struct PGMPOOLPAGE
995{
996 /** AVL node code with the (HC) physical address of this page. */
997 AVLOHCPHYSNODECORE Core;
998 /** Pointer to the HC mapping of the page. */
999 R3R0PTRTYPE(void *) pvPageHC;
1000 /** The guest physical address. */
1001 RTGCPHYS GCPhys;
1002 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1003 uint8_t enmKind;
1004 uint8_t bPadding;
1005 /** The index of this page. */
1006 uint16_t idx;
1007 /** The next entry in the list this page currently resides in.
1008 * It's either in the free list or in the GCPhys hash. */
1009 uint16_t iNext;
1010#ifdef PGMPOOL_WITH_USER_TRACKING
1011 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1012 uint16_t iUserHead;
1013 /** The number of present entries. */
1014 uint16_t cPresent;
1015 /** The first entry in the table which is present. */
1016 uint16_t iFirstPresent;
1017#endif
1018#ifdef PGMPOOL_WITH_MONITORING
1019 /** The number of modifications to the monitored page. */
1020 uint16_t cModifications;
1021 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1022 uint16_t iModifiedNext;
1023 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1024 uint16_t iModifiedPrev;
1025 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1026 uint16_t iMonitoredNext;
1027 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1028 uint16_t iMonitoredPrev;
1029#endif
1030#ifdef PGMPOOL_WITH_CACHE
1031 /** The next page in the age list. */
1032 uint16_t iAgeNext;
1033 /** The previous page in the age list. */
1034 uint16_t iAgePrev;
1035#endif /* PGMPOOL_WITH_CACHE */
1036 /** Used to indicate that the page is zeroed. */
1037 bool fZeroed;
1038 /** Used to indicate that a PT has non-global entries. */
1039 bool fSeenNonGlobal;
1040 /** Used to indicate that we're monitoring writes to the guest page. */
1041 bool fMonitored;
1042 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1043 * (All pages are in the age list.) */
1044 bool fCached;
1045 /** This is used by the R3 access handlers when invoked by an async thread.
1046 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1047 bool volatile fReusedFlushPending;
1048 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1049 * In these cases the access handler acts differently and will check
1050 * for mapping conflicts like the normal CR3 handler.
1051 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1052 * replaced by a list of pages which share access handler.
1053 */
1054 bool fCR3Mix;
1055#if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
1056 bool Alignment[4]; /**< Align the structure size on a 64-bit boundrary. */
1057#endif
1058} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1059
1060
1061#ifdef PGMPOOL_WITH_CACHE
1062/** The hash table size. */
1063# define PGMPOOL_HASH_SIZE 0x40
1064/** The hash function. */
1065# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1066#endif
1067
1068
1069/**
1070 * The shadow page pool instance data.
1071 *
1072 * It's all one big allocation made at init time, except for the
1073 * pages that is. The user nodes follows immediatly after the
1074 * page structures.
1075 */
1076typedef struct PGMPOOL
1077{
1078 /** The VM handle - HC Ptr. */
1079 R3R0PTRTYPE(PVM) pVMHC;
1080 /** The VM handle - GC Ptr. */
1081 GCPTRTYPE(PVM) pVMGC;
1082 /** The max pool size. This includes the special IDs. */
1083 uint16_t cMaxPages;
1084 /** The current pool size. */
1085 uint16_t cCurPages;
1086 /** The head of the free page list. */
1087 uint16_t iFreeHead;
1088 /* Padding. */
1089 uint16_t u16Padding;
1090#ifdef PGMPOOL_WITH_USER_TRACKING
1091 /** Head of the chain of free user nodes. */
1092 uint16_t iUserFreeHead;
1093 /** The number of user nodes we've allocated. */
1094 uint16_t cMaxUsers;
1095 /** The number of present page table entries in the entire pool. */
1096 uint32_t cPresent;
1097 /** Pointer to the array of user nodes - GC pointer. */
1098 GCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1099 /** Pointer to the array of user nodes - HC pointer. */
1100 R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1101#endif /* PGMPOOL_WITH_USER_TRACKING */
1102#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1103 /** Head of the chain of free phys ext nodes. */
1104 uint16_t iPhysExtFreeHead;
1105 /** The number of user nodes we've allocated. */
1106 uint16_t cMaxPhysExts;
1107 /** Pointer to the array of physical xref extent - GC pointer. */
1108 GCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1109 /** Pointer to the array of physical xref extent nodes - HC pointer. */
1110 R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1111#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1112#ifdef PGMPOOL_WITH_CACHE
1113 /** Hash table for GCPhys addresses. */
1114 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1115 /** The head of the age list. */
1116 uint16_t iAgeHead;
1117 /** The tail of the age list. */
1118 uint16_t iAgeTail;
1119 /** Set if the cache is enabled. */
1120 bool fCacheEnabled;
1121#endif /* PGMPOOL_WITH_CACHE */
1122#ifdef PGMPOOL_WITH_MONITORING
1123 /** Head of the list of modified pages. */
1124 uint16_t iModifiedHead;
1125 /** The current number of modified pages. */
1126 uint16_t cModifiedPages;
1127 /** Access handler, GC. */
1128 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1129 /** Access handler, R0. */
1130 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1131 /** Access handler, R3. */
1132 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1133 /** The access handler description (HC ptr). */
1134 R3PTRTYPE(const char *) pszAccessHandler;
1135#endif /* PGMPOOL_WITH_MONITORING */
1136 /** The number of pages currently in use. */
1137 uint16_t cUsedPages;
1138#ifdef VBOX_WITH_STATISTICS
1139 /** The high wather mark for cUsedPages. */
1140 uint16_t cUsedPagesHigh;
1141 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1142 /** Profiling pgmPoolAlloc(). */
1143 STAMPROFILEADV StatAlloc;
1144 /** Profiling pgmPoolClearAll(). */
1145 STAMPROFILE StatClearAll;
1146 /** Profiling pgmPoolFlushAllInt(). */
1147 STAMPROFILE StatFlushAllInt;
1148 /** Profiling pgmPoolFlushPage(). */
1149 STAMPROFILE StatFlushPage;
1150 /** Profiling pgmPoolFree(). */
1151 STAMPROFILE StatFree;
1152 /** Profiling time spent zeroing pages. */
1153 STAMPROFILE StatZeroPage;
1154# ifdef PGMPOOL_WITH_USER_TRACKING
1155 /** Profiling of pgmPoolTrackDeref. */
1156 STAMPROFILE StatTrackDeref;
1157 /** Profiling pgmTrackFlushGCPhysPT. */
1158 STAMPROFILE StatTrackFlushGCPhysPT;
1159 /** Profiling pgmTrackFlushGCPhysPTs. */
1160 STAMPROFILE StatTrackFlushGCPhysPTs;
1161 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1162 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1163 /** Number of times we've been out of user records. */
1164 STAMCOUNTER StatTrackFreeUpOneUser;
1165# endif
1166# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1167 /** Profiling deref activity related tracking GC physical pages. */
1168 STAMPROFILE StatTrackDerefGCPhys;
1169 /** Number of linear searches for a HCPhys in the ram ranges. */
1170 STAMCOUNTER StatTrackLinearRamSearches;
1171 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1172 STAMCOUNTER StamTrackPhysExtAllocFailures;
1173# endif
1174# ifdef PGMPOOL_WITH_MONITORING
1175 /** Profiling the GC PT access handler. */
1176 STAMPROFILE StatMonitorGC;
1177 /** Times we've failed interpreting the instruction. */
1178 STAMCOUNTER StatMonitorGCEmulateInstr;
1179 /** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1180 STAMPROFILE StatMonitorGCFlushPage;
1181 /** Times we've detected fork(). */
1182 STAMCOUNTER StatMonitorGCFork;
1183 /** Profiling the GC access we've handled (except REP STOSD). */
1184 STAMPROFILE StatMonitorGCHandled;
1185 /** Times we've failed interpreting a patch code instruction. */
1186 STAMCOUNTER StatMonitorGCIntrFailPatch1;
1187 /** Times we've failed interpreting a patch code instruction during flushing. */
1188 STAMCOUNTER StatMonitorGCIntrFailPatch2;
1189 /** The number of times we've seen rep prefixes we can't handle. */
1190 STAMCOUNTER StatMonitorGCRepPrefix;
1191 /** Profiling the REP STOSD cases we've handled. */
1192 STAMPROFILE StatMonitorGCRepStosd;
1193
1194 /** Profiling the HC PT access handler. */
1195 STAMPROFILE StatMonitorHC;
1196 /** Times we've failed interpreting the instruction. */
1197 STAMCOUNTER StatMonitorHCEmulateInstr;
1198 /** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1199 STAMPROFILE StatMonitorHCFlushPage;
1200 /** Times we've detected fork(). */
1201 STAMCOUNTER StatMonitorHCFork;
1202 /** Profiling the HC access we've handled (except REP STOSD). */
1203 STAMPROFILE StatMonitorHCHandled;
1204 /** The number of times we've seen rep prefixes we can't handle. */
1205 STAMCOUNTER StatMonitorHCRepPrefix;
1206 /** Profiling the REP STOSD cases we've handled. */
1207 STAMPROFILE StatMonitorHCRepStosd;
1208 /** The number of times we're called in an async thread an need to flush. */
1209 STAMCOUNTER StatMonitorHCAsync;
1210 /** The high wather mark for cModifiedPages. */
1211 uint16_t cModifiedPagesHigh;
1212 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1213# endif
1214# ifdef PGMPOOL_WITH_CACHE
1215 /** The number of cache hits. */
1216 STAMCOUNTER StatCacheHits;
1217 /** The number of cache misses. */
1218 STAMCOUNTER StatCacheMisses;
1219 /** The number of times we've got a conflict of 'kind' in the cache. */
1220 STAMCOUNTER StatCacheKindMismatches;
1221 /** Number of times we've been out of pages. */
1222 STAMCOUNTER StatCacheFreeUpOne;
1223 /** The number of cacheable allocations. */
1224 STAMCOUNTER StatCacheCacheable;
1225 /** The number of uncacheable allocations. */
1226 STAMCOUNTER StatCacheUncacheable;
1227# endif
1228#elif HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1229 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1230#endif
1231 /** The AVL tree for looking up a page by its HC physical address. */
1232 AVLOHCPHYSTREE HCPhysTree;
1233 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1234 /** Array of pages. (cMaxPages in length)
1235 * The Id is the index into thist array.
1236 */
1237 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1238} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1239
1240
1241/** @def PGMPOOL_PAGE_2_PTR
1242 * Maps a pool page pool into the current context.
1243 *
1244 * @returns VBox status code.
1245 * @param pVM The VM handle.
1246 * @param pPage The pool page.
1247 *
1248 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1249 * small page window employeed by that function. Be careful.
1250 * @remark There is no need to assert on the result.
1251 */
1252#ifdef IN_GC
1253# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1254#else
1255# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1256#endif
1257
1258
1259/**
1260 * Trees are using self relative offsets as pointers.
1261 * So, all its data, including the root pointer, must be in the heap for HC and GC
1262 * to have the same layout.
1263 */
1264typedef struct PGMTREES
1265{
1266 /** Physical access handlers (AVL range+offsetptr tree). */
1267 AVLROGCPHYSTREE PhysHandlers;
1268 /** Virtual access handlers (AVL range + GC ptr tree). */
1269 AVLROGCPTRTREE VirtHandlers;
1270 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1271 AVLROGCPHYSTREE PhysToVirtHandlers;
1272 uint32_t auPadding[1];
1273} PGMTREES;
1274/** Pointer to PGM trees. */
1275typedef PGMTREES *PPGMTREES;
1276
1277
1278/** @name Paging mode macros
1279 * @{ */
1280#ifdef IN_GC
1281# define PGM_CTX(a,b) a##GC##b
1282# define PGM_CTX_STR(a,b) a "GC" b
1283# define PGM_CTX_DECL(type) PGMGCDECL(type)
1284#else
1285# ifdef IN_RING3
1286# define PGM_CTX(a,b) a##R3##b
1287# define PGM_CTX_STR(a,b) a "R3" b
1288# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1289# else
1290# define PGM_CTX(a,b) a##R0##b
1291# define PGM_CTX_STR(a,b) a "R0" b
1292# define PGM_CTX_DECL(type) PGMDECL(type)
1293# endif
1294#endif
1295
1296#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1297#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1298#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1299#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1300#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1301#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1302#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1303#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1304#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1305#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1306#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1307#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1308#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1309#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1310#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1311#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1312#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1313
1314#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1315#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1316#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1317#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1318#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1319#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1320#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1321#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1322#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1323#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1324#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1325
1326/* Shw_Gst */
1327#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1328#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1329#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1330#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1331#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1332#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1333#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1334#define PGM_BTH_NAME_AMD64_REAL(name) PGM_CTX(pgm,BthAMD64Real##name)
1335#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1336#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1337#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1338#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1339#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1340#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1341#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1342#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1343#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1344#define PGM_BTH_NAME_GC_AMD64_REAL_STR(name) "pgmGCBthAMD64Real" #name
1345#define PGM_BTH_NAME_GC_AMD64_PROT_STR(name) "pgmGCBthAMD64Prot" #name
1346#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1347#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1348#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1349#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1350#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1351#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1352#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1353#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1354#define PGM_BTH_NAME_R0_AMD64_REAL_STR(name) "pgmR0BthAMD64Real" #name
1355#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1356#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1357#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1358#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1359/** @} */
1360
1361/**
1362 * Data for each paging mode.
1363 */
1364typedef struct PGMMODEDATA
1365{
1366 /** The guest mode type. */
1367 uint32_t uGstType;
1368 /** The shadow mode type. */
1369 uint32_t uShwType;
1370
1371 /** @name Function pointers for Shadow paging.
1372 * @{
1373 */
1374 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1375 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1376 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1377 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1378 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1379 DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1380 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1381
1382 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1383 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1384 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1385 DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1386 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1387
1388 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1389 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1390 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1391 DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1392 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1393 /** @} */
1394
1395 /** @name Function pointers for Guest paging.
1396 * @{
1397 */
1398 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1399 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1400 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1401 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1402 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1403 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1404 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1405 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1406 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1407 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1408 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1409 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1410 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1411
1412 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1413 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1414 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1415 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1416 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1417 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1418 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1419 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1420 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1421
1422 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1423 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1424 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1425 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1426 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1427 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1428 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1429 /** @} */
1430
1431 /** @name Function pointers for Both Shadow and Guest paging.
1432 * @{
1433 */
1434 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1435 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1436 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1437 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1438 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1439 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1440 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1441#ifdef VBOX_STRICT
1442 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1443#endif
1444
1445 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1446 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1447 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1448 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1449 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1450 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1451#ifdef VBOX_STRICT
1452 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1453#endif
1454
1455 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1456 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1457 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1458 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1459 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1460 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1461#ifdef VBOX_STRICT
1462 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1463#endif
1464 /** @} */
1465} PGMMODEDATA, *PPGMMODEDATA;
1466
1467
1468
1469/**
1470 * Converts a PGM pointer into a VM pointer.
1471 * @returns Pointer to the VM structure the PGM is part of.
1472 * @param pPGM Pointer to PGM instance data.
1473 */
1474#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1475
1476/**
1477 * PGM Data (part of VM)
1478 */
1479typedef struct PGM
1480{
1481 /** Offset to the VM structure. */
1482 RTINT offVM;
1483
1484 /*
1485 * This will be redefined at least two more times before we're done, I'm sure.
1486 * The current code is only to get on with the coding.
1487 * - 2004-06-10: initial version, bird.
1488 * - 2004-07-02: 1st time, bird.
1489 * - 2004-10-18: 2nd time, bird.
1490 * - 2005-07-xx: 3rd time, bird.
1491 */
1492
1493 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1494 GCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1495 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1496 GCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1497
1498 /** The host paging mode. (This is what SUPLib reports.) */
1499 SUPPAGINGMODE enmHostMode;
1500 /** The shadow paging mode. */
1501 PGMMODE enmShadowMode;
1502 /** The guest paging mode. */
1503 PGMMODE enmGuestMode;
1504
1505 /** The current physical address representing in the guest CR3 register. */
1506 RTGCPHYS GCPhysCR3;
1507 /** Pointer to the 5 page CR3 content mapping.
1508 * The first page is always the CR3 (in some form) while the 4 other pages
1509 * are used of the PDs in PAE mode. */
1510 RTGCPTR GCPtrCR3Mapping;
1511 /** The physical address of the currently monitored guest CR3 page.
1512 * When this value is NIL_RTGCPHYS no page is being monitored. */
1513 RTGCPHYS GCPhysGstCR3Monitored;
1514#if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
1515 RTGCPHYS GCPhysPadding0; /**< alignment padding. */
1516#endif
1517
1518 /** @name 32-bit Guest Paging.
1519 * @{ */
1520 /** The guest's page directory, HC pointer. */
1521 R3R0PTRTYPE(PVBOXPD) pGuestPDHC;
1522 /** The guest's page directory, static GC mapping. */
1523 GCPTRTYPE(PVBOXPD) pGuestPDGC;
1524 /** @} */
1525
1526 /** @name PAE Guest Paging.
1527 * @{ */
1528 /** The guest's page directory pointer table, static GC mapping. */
1529 GCPTRTYPE(PX86PDPTR) pGstPaePDPTRGC;
1530 /** The guest's page directory pointer table, HC pointer. */
1531 R3R0PTRTYPE(PX86PDPTR) pGstPaePDPTRHC;
1532 /** The guest's page directories, HC pointers.
1533 * These are individual pointers and doesn't have to be adjecent.
1534 * These doesn't have to be update to date - use pgmGstGetPaePD() to access them. */
1535 R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1536 /** The guest's page directories, static GC mapping.
1537 * Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1538 * These doesn't have to be update to date - use pgmGstGetPaePD() to access them. */
1539 GCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1540 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1541 RTGCPHYS aGCPhysGstPaePDs[4];
1542 /** The physical addresses of the monitored guest page directories (PAE). */
1543 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1544 /** @} */
1545
1546
1547 /** @name 32-bit Shadow Paging
1548 * @{ */
1549 /** The 32-Bit PD - HC Ptr. */
1550 R3R0PTRTYPE(PX86PD) pHC32BitPD;
1551 /** The 32-Bit PD - GC Ptr. */
1552 GCPTRTYPE(PX86PD) pGC32BitPD;
1553#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1554 uint32_t u32Padding1; /**< alignment padding. */
1555#endif
1556 /** The Physical Address (HC) of the 32-Bit PD. */
1557 RTHCPHYS HCPhys32BitPD;
1558 /** @} */
1559
1560 /** @name PAE Shadow Paging
1561 * @{ */
1562 /** The four PDs for the low 4GB - HC Ptr.
1563 * Even though these are 4 pointers, what they point at is a single table.
1564 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1565 R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1566 /** The four PDs for the low 4GB - GC Ptr.
1567 * Same kind of mapping as apHCPaePDs. */
1568 GCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1569 /** The Physical Address (HC) of the four PDs for the low 4GB.
1570 * These are *NOT* 4 contiguous pages. */
1571 RTHCPHYS aHCPhysPaePDs[4];
1572 /** The PAE PDPTR - HC Ptr. */
1573 R3R0PTRTYPE(PX86PDPTR) pHCPaePDPTR;
1574 /** The Physical Address (HC) of the PAE PDPTR. */
1575 RTHCPHYS HCPhysPaePDPTR;
1576 /** The PAE PDPTR - GC Ptr. */
1577 GCPTRTYPE(PX86PDPTR) pGCPaePDPTR;
1578 /** @} */
1579
1580 /** @name AMD64 Shadow Paging
1581 * Extends PAE Paging.
1582 * @{ */
1583 /** The Page Map Level 4 table - HC Ptr. */
1584 GCPTRTYPE(PX86PML4) pGCPaePML4;
1585 /** The Page Map Level 4 table - GC Ptr. */
1586 R3R0PTRTYPE(PX86PML4) pHCPaePML4;
1587 /** The Physical Address (HC) of the Page Map Level 4 table. */
1588 RTHCPHYS HCPhysPaePML4;
1589 /** @}*/
1590
1591 /** @name Function pointers for Shadow paging.
1592 * @{
1593 */
1594 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1595 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1596 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1597 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1598 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1599 DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1600 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1601
1602 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1603 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1604 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1605 DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1606 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1607#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1608 RTGCPTR alignment0; /**< structure size alignment. */
1609#endif
1610
1611 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1612 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1613 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1614 DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1615 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1616
1617 /** @} */
1618
1619 /** @name Function pointers for Guest paging.
1620 * @{
1621 */
1622 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1623 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1624 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1625 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1626 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1627 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1628 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1629 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1630 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1631 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1632 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1633 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1634 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1635
1636 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1637 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1638 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1639 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1640 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1641 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1642 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1643 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1644 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1645#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1646 RTGCPTR alignment3; /**< structure size alignment. */
1647#endif
1648
1649 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1650 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1651 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1652 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1653 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1654 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1655 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1656 /** @} */
1657
1658 /** @name Function pointers for Both Shadow and Guest paging.
1659 * @{
1660 */
1661 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1662 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1663 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1664 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1665 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1666 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1667 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1668 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1669
1670 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1671 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1672 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1673 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1674 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1675 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1676 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1677
1678 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1679 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1680 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal));
1681 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1682 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1683 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1684 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1685#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
1686 RTGCPTR alignment2; /**< structure size alignment. */
1687#endif
1688 /** @} */
1689
1690 /** Pointer to SHW+GST mode data (function pointers).
1691 * The index into this table is made up from */
1692 R3PTRTYPE(PPGMMODEDATA) paModeData;
1693
1694
1695 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for HC.
1696 * This is sorted by physical address and contains no overlaps.
1697 * The memory locks and other conversions are managed by MM at the moment.
1698 */
1699 R3R0PTRTYPE(PPGMRAMRANGE) pRamRangesHC;
1700 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for GC.
1701 * This is sorted by physical address and contains no overlaps.
1702 * The memory locks and other conversions are managed by MM at the moment.
1703 */
1704 GCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
1705 /** The configured RAM size. */
1706 RTUINT cbRamSize;
1707
1708 /** PGM offset based trees - HC Ptr. */
1709 R3R0PTRTYPE(PPGMTREES) pTreesHC;
1710 /** PGM offset based trees - GC Ptr. */
1711 GCPTRTYPE(PPGMTREES) pTreesGC;
1712
1713 /** Linked list of GC mappings - for GC.
1714 * The list is sorted ascending on address.
1715 */
1716 GCPTRTYPE(PPGMMAPPING) pMappingsGC;
1717 /** Linked list of GC mappings - for HC.
1718 * The list is sorted ascending on address.
1719 */
1720 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
1721 /** Linked list of GC mappings - for R0.
1722 * The list is sorted ascending on address.
1723 */
1724 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
1725
1726 /** If set no conflict checks are required. (boolean) */
1727 bool fMappingsFixed;
1728 /** If set, then no mappings are put into the shadow page table. (boolean) */
1729 bool fDisableMappings;
1730 /** Size of fixed mapping */
1731 uint32_t cbMappingFixed;
1732 /** Base address (GC) of fixed mapping */
1733 RTGCPTR GCPtrMappingFixed;
1734#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1735 uint32_t u32Padding0; /**< alignment padding. */
1736#endif
1737
1738
1739 /** @name Intermediate Context
1740 * @{ */
1741 /** Pointer to the intermediate page directory - Normal. */
1742 R3PTRTYPE(PX86PD) pInterPD;
1743 /** Pointer to the intermedate page tables - Normal.
1744 * There are two page tables, one for the identity mapping and one for
1745 * the host context mapping (of the core code). */
1746 R3PTRTYPE(PX86PT) apInterPTs[2];
1747 /** Pointer to the intermedate page tables - PAE. */
1748 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
1749 /** Pointer to the intermedate page directory - PAE. */
1750 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
1751 /** Pointer to the intermedate page directory - PAE. */
1752 R3PTRTYPE(PX86PDPTR) pInterPaePDPTR;
1753 /** Pointer to the intermedate page-map level 4 - AMD64. */
1754 R3PTRTYPE(PX86PML4) pInterPaePML4;
1755 /** Pointer to the intermedate page directory - AMD64. */
1756 R3PTRTYPE(PX86PDPTR) pInterPaePDPTR64;
1757 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
1758 RTHCPHYS HCPhysInterPD;
1759 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
1760 RTHCPHYS HCPhysInterPaePDPTR;
1761 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
1762 RTHCPHYS HCPhysInterPaePML4;
1763 /** @} */
1764
1765 /** Base address of the dynamic page mapping area.
1766 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
1767 */
1768 GCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
1769 /** The index of the last entry used in the dynamic page mapping area. */
1770 RTUINT iDynPageMapLast;
1771 /** Cache containing the last entries in the dynamic page mapping area.
1772 * The cache size is covering half of the mapping area. */
1773 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
1774
1775 /** A20 gate mask.
1776 * Our current approach to A20 emulation is to let REM do it and don't bother
1777 * anywhere else. The interesting Guests will be operating with it enabled anyway.
1778 * But whould need arrise, we'll subject physical addresses to this mask. */
1779 RTGCPHYS GCPhysA20Mask;
1780 /** A20 gate state - boolean! */
1781 RTUINT fA20Enabled;
1782
1783 /** What needs syncing (PGM_SYNC_*).
1784 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
1785 * PGMFlushTLB, and PGMR3Load. */
1786 RTUINT fSyncFlags;
1787
1788#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1789 RTUINT uPadding3; /**< alignment padding. */
1790#endif
1791 /** PGM critical section.
1792 * This protects the physical & virtual access handlers, ram ranges,
1793 * and the page flag updating (some of it anyway).
1794 */
1795 PDMCRITSECT CritSect;
1796
1797 /** Shadow Page Pool - HC Ptr. */
1798 R3R0PTRTYPE(PPGMPOOL) pPoolHC;
1799 /** Shadow Page Pool - GC Ptr. */
1800 GCPTRTYPE(PPGMPOOL) pPoolGC;
1801
1802 /** We're not in a state which permits writes to guest memory.
1803 * (Only used in strict builds.) */
1804 bool fNoMorePhysWrites;
1805
1806 /** Flush the cache on the next access. */
1807 bool fPhysCacheFlushPending;
1808/** @todo r=bird: Fix member names!*/
1809 /** PGMPhysRead cache */
1810 PGMPHYSCACHE pgmphysreadcache;
1811 /** PGMPhysWrite cache */
1812 PGMPHYSCACHE pgmphyswritecache;
1813
1814 /**
1815 * Data associated with managing the ring-3 mappings of the allocation chunks.
1816 */
1817 struct
1818 {
1819 /** The chunk tree, ordered by chunk id. */
1820 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
1821 /** The chunk mapping TLB. */
1822 PGMCHUNKR3MAPTLB Tlb;
1823 /** The number of mapped chunks. */
1824 uint32_t c;
1825 /** The maximum number of mapped chunks.
1826 * @cfgm PGM/MaxRing3Chunks */
1827 uint32_t cMax;
1828 /** The chunk age tree, ordered by ageing sequence number. */
1829 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
1830 /** The current time. */
1831 uint32_t iNow;
1832 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
1833 uint32_t AgeingCountdown;
1834 } ChunkR3Map;
1835
1836 /**
1837 * The page mapping TLB for ring-3 and (for the time being) ring-0.
1838 */
1839 PGMPAGER3MAPTLB PhysTlbHC;
1840
1841 /** @name The zero page.
1842 * @{ */
1843 /** The host physical address of the zero page. */
1844 RTHCPHYS HCPhysZeroPg;
1845 /** The ring-3 mapping of the zero page. */
1846 RTR3PTR pvZeroPgR3;
1847 /** The ring-0 mapping of the zero page. */
1848 RTR0PTR pvZeroPgR0;
1849 /** The GC mapping of the zero page. */
1850 RTGCPTR pvZeroPgGC;
1851#if GC_ARCH_BITS != 32
1852 uint32_t u32ZeroAlignment; /**< Alignment padding. */
1853#endif
1854 /** @}*/
1855
1856 /** The number of handy pages. */
1857 uint32_t cHandyPages;
1858 /**
1859 * Array of handy pages.
1860 *
1861 * This array is used in a two way communication between pgmPhysAllocPage
1862 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
1863 * an intermediary.
1864 *
1865 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
1866 * (The current size of 32 pages, means 128 KB of handy memory.)
1867 */
1868 GMMPAGEDESC aHandyPages[32];
1869
1870 /** @name Release Statistics
1871 * @{ */
1872 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
1873 uint32_t cPrivatePages; /**< The number of private pages. */
1874 uint32_t cSharedPages; /**< The number of shared pages. */
1875 uint32_t cZeroPages; /**< The number of zero backed pages. */
1876 /** The number of times the guest has switched mode since last reset or statistics reset. */
1877 STAMCOUNTER cGuestModeChanges;
1878 /** @} */
1879
1880#ifdef VBOX_WITH_STATISTICS
1881 /** GC: Which statistic this \#PF should be attributed to. */
1882 GCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
1883 RTGCPTR padding0;
1884 /** HC: Which statistic this \#PF should be attributed to. */
1885 R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
1886 RTHCPTR padding1;
1887 STAMPROFILE StatGCTrap0e; /**< GC: PGMGCTrap0eHandler() profiling. */
1888 STAMPROFILE StatTrap0eCSAM; /**< Profiling of the Trap0eHandler body when the cause is CSAM. */
1889 STAMPROFILE StatTrap0eDirtyAndAccessedBits; /**< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
1890 STAMPROFILE StatTrap0eGuestTrap; /**< Profiling of the Trap0eHandler body when the cause is a guest trap. */
1891 STAMPROFILE StatTrap0eHndPhys; /**< Profiling of the Trap0eHandler body when the cause is a physical handler. */
1892 STAMPROFILE StatTrap0eHndVirt; /**< Profiling of the Trap0eHandler body when the cause is a virtual handler. */
1893 STAMPROFILE StatTrap0eHndUnhandled; /**< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
1894 STAMPROFILE StatTrap0eMisc; /**< Profiling of the Trap0eHandler body when the cause is not known. */
1895 STAMPROFILE StatTrap0eOutOfSync; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
1896 STAMPROFILE StatTrap0eOutOfSyncHndPhys; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
1897 STAMPROFILE StatTrap0eOutOfSyncHndVirt; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
1898 STAMPROFILE StatTrap0eOutOfSyncObsHnd; /**< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
1899 STAMPROFILE StatTrap0eSyncPT; /**< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
1900
1901 STAMCOUNTER StatTrap0eMapHandler; /**< Number of traps due to access handlers in mappings. */
1902 STAMCOUNTER StatGCTrap0eConflicts; /**< GC: The number of times \#PF was caused by an undetected conflict. */
1903
1904 STAMCOUNTER StatGCTrap0eUSNotPresentRead;
1905 STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
1906 STAMCOUNTER StatGCTrap0eUSWrite;
1907 STAMCOUNTER StatGCTrap0eUSReserved;
1908 STAMCOUNTER StatGCTrap0eUSRead;
1909
1910 STAMCOUNTER StatGCTrap0eSVNotPresentRead;
1911 STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
1912 STAMCOUNTER StatGCTrap0eSVWrite;
1913 STAMCOUNTER StatGCTrap0eSVReserved;
1914
1915 STAMCOUNTER StatGCTrap0eUnhandled;
1916 STAMCOUNTER StatGCTrap0eMap;
1917
1918 /** GC: PGMSyncPT() profiling. */
1919 STAMPROFILE StatGCSyncPT;
1920 /** GC: The number of times PGMSyncPT() needed to allocate page tables. */
1921 STAMCOUNTER StatGCSyncPTAlloc;
1922 /** GC: The number of times PGMSyncPT() detected conflicts. */
1923 STAMCOUNTER StatGCSyncPTConflict;
1924 /** GC: The number of times PGMSyncPT() failed. */
1925 STAMCOUNTER StatGCSyncPTFailed;
1926 /** GC: PGMGCInvalidatePage() profiling. */
1927 STAMPROFILE StatGCInvalidatePage;
1928 /** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
1929 STAMCOUNTER StatGCInvalidatePage4KBPages;
1930 /** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
1931 STAMCOUNTER StatGCInvalidatePage4MBPages;
1932 /** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
1933 STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
1934 /** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
1935 STAMCOUNTER StatGCInvalidatePagePDNAs;
1936 /** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
1937 STAMCOUNTER StatGCInvalidatePagePDNPs;
1938 /** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
1939 STAMCOUNTER StatGCInvalidatePagePDMappings;
1940 /** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
1941 STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
1942 /** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
1943 STAMCOUNTER StatGCInvalidatePageSkipped;
1944 /** GC: The number of times user page is out of sync was detected in GC. */
1945 STAMCOUNTER StatGCPageOutOfSyncUser;
1946 /** GC: The number of times supervisor page is out of sync was detected in GC. */
1947 STAMCOUNTER StatGCPageOutOfSyncSupervisor;
1948 /** GC: The number of dynamic page mapping cache hits */
1949 STAMCOUNTER StatDynMapCacheMisses;
1950 /** GC: The number of dynamic page mapping cache misses */
1951 STAMCOUNTER StatDynMapCacheHits;
1952 /** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
1953 STAMCOUNTER StatGCGuestCR3WriteHandled;
1954 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
1955 STAMCOUNTER StatGCGuestCR3WriteUnhandled;
1956 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
1957 STAMCOUNTER StatGCGuestCR3WriteConflict;
1958 /** GC: Number of out-of-sync handled pages. */
1959 STAMCOUNTER StatHandlersOutOfSync;
1960 /** GC: Number of traps due to physical access handlers. */
1961 STAMCOUNTER StatHandlersPhysical;
1962 /** GC: Number of traps due to virtual access handlers. */
1963 STAMCOUNTER StatHandlersVirtual;
1964 /** GC: Number of traps due to virtual access handlers found by physical address. */
1965 STAMCOUNTER StatHandlersVirtualByPhys;
1966 /** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
1967 STAMCOUNTER StatHandlersVirtualUnmarked;
1968 /** GC: Number of traps due to access outside range of monitored page(s). */
1969 STAMCOUNTER StatHandlersUnhandled;
1970
1971 /** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
1972 STAMCOUNTER StatGCGuestROMWriteHandled;
1973 /** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
1974 STAMCOUNTER StatGCGuestROMWriteUnhandled;
1975
1976 /** HC: PGMR3InvalidatePage() profiling. */
1977 STAMPROFILE StatHCInvalidatePage;
1978 /** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
1979 STAMCOUNTER StatHCInvalidatePage4KBPages;
1980 /** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
1981 STAMCOUNTER StatHCInvalidatePage4MBPages;
1982 /** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
1983 STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
1984 /** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
1985 STAMCOUNTER StatHCInvalidatePagePDNAs;
1986 /** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
1987 STAMCOUNTER StatHCInvalidatePagePDNPs;
1988 /** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
1989 STAMCOUNTER StatHCInvalidatePagePDMappings;
1990 /** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
1991 STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
1992 /** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
1993 STAMCOUNTER StatHCInvalidatePageSkipped;
1994 /** HC: PGMR3SyncPT() profiling. */
1995 STAMPROFILE StatHCSyncPT;
1996 /** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
1997 STAMPROFILE StatHCResolveConflict;
1998 /** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
1999 STAMCOUNTER StatHCDetectedConflicts;
2000 /** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2001 STAMCOUNTER StatHCGuestPDWrite;
2002 /** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2003 STAMCOUNTER StatHCGuestPDWriteConflict;
2004
2005 /** HC: The number of pages marked not present for accessed bit emulation. */
2006 STAMCOUNTER StatHCAccessedPage;
2007 /** HC: The number of pages marked read-only for dirty bit tracking. */
2008 STAMCOUNTER StatHCDirtyPage;
2009 /** HC: The number of pages marked read-only for dirty bit tracking. */
2010 STAMCOUNTER StatHCDirtyPageBig;
2011 /** HC: The number of traps generated for dirty bit tracking. */
2012 STAMCOUNTER StatHCDirtyPageTrap;
2013 /** HC: The number of pages already dirty or readonly. */
2014 STAMCOUNTER StatHCDirtyPageSkipped;
2015
2016 /** GC: The number of pages marked not present for accessed bit emulation. */
2017 STAMCOUNTER StatGCAccessedPage;
2018 /** GC: The number of pages marked read-only for dirty bit tracking. */
2019 STAMCOUNTER StatGCDirtyPage;
2020 /** GC: The number of pages marked read-only for dirty bit tracking. */
2021 STAMCOUNTER StatGCDirtyPageBig;
2022 /** GC: The number of traps generated for dirty bit tracking. */
2023 STAMCOUNTER StatGCDirtyPageTrap;
2024 /** GC: The number of pages already dirty or readonly. */
2025 STAMCOUNTER StatGCDirtyPageSkipped;
2026 /** GC: The number of pages marked dirty because of write accesses. */
2027 STAMCOUNTER StatGCDirtiedPage;
2028 /** GC: The number of pages already marked dirty because of write accesses. */
2029 STAMCOUNTER StatGCPageAlreadyDirty;
2030 /** GC: The number of real pages faults during dirty bit tracking. */
2031 STAMCOUNTER StatGCDirtyTrackRealPF;
2032
2033 /** GC: Profiling of the PGMTrackDirtyBit() body */
2034 STAMPROFILE StatGCDirtyBitTracking;
2035 /** HC: Profiling of the PGMTrackDirtyBit() body */
2036 STAMPROFILE StatHCDirtyBitTracking;
2037
2038 /** GC: Profiling of the PGMGstModifyPage() body */
2039 STAMPROFILE StatGCGstModifyPage;
2040 /** HC: Profiling of the PGMGstModifyPage() body */
2041 STAMPROFILE StatHCGstModifyPage;
2042
2043 /** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2044 STAMCOUNTER StatGCSyncPagePDNAs;
2045 /** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2046 STAMCOUNTER StatGCSyncPagePDOutOfSync;
2047 /** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2048 STAMCOUNTER StatHCSyncPagePDNAs;
2049 /** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2050 STAMCOUNTER StatHCSyncPagePDOutOfSync;
2051
2052 STAMCOUNTER StatSynPT4kGC;
2053 STAMCOUNTER StatSynPT4kHC;
2054 STAMCOUNTER StatSynPT4MGC;
2055 STAMCOUNTER StatSynPT4MHC;
2056
2057 /** Profiling of the PGMFlushTLB() body. */
2058 STAMPROFILE StatFlushTLB;
2059 /** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2060 STAMCOUNTER StatFlushTLBNewCR3;
2061 /** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2062 STAMCOUNTER StatFlushTLBNewCR3Global;
2063 /** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2064 STAMCOUNTER StatFlushTLBSameCR3;
2065 /** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2066 STAMCOUNTER StatFlushTLBSameCR3Global;
2067
2068 STAMPROFILE StatGCSyncCR3; /**< GC: PGMSyncCR3() profiling. */
2069 STAMPROFILE StatGCSyncCR3Handlers; /**< GC: Profiling of the PGMSyncCR3() update handler section. */
2070 STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /**< GC: Profiling of the virtual handler resets. */
2071 STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /**< GC: Profiling of the virtual handler updates. */
2072 STAMCOUNTER StatGCSyncCR3Global; /**< GC: The number of global CR3 syncs. */
2073 STAMCOUNTER StatGCSyncCR3NotGlobal; /**< GC: The number of non-global CR3 syncs. */
2074 STAMCOUNTER StatGCSyncCR3DstFreed; /**< GC: The number of times we've had to free a shadow entry. */
2075 STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /**< GC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2076 STAMCOUNTER StatGCSyncCR3DstNotPresent; /**< GC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2077 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /**< GC: The number of times a global page directory wasn't flushed. */
2078 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /**< GC: The number of times a page table with only global entries wasn't flushed. */
2079 STAMCOUNTER StatGCSyncCR3DstCacheHit; /**< GC: The number of times we got some kind of cache hit on a page table. */
2080
2081 STAMPROFILE StatHCSyncCR3; /**< HC: PGMSyncCR3() profiling. */
2082 STAMPROFILE StatHCSyncCR3Handlers; /**< HC: Profiling of the PGMSyncCR3() update handler section. */
2083 STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /**< HC: Profiling of the virtual handler resets. */
2084 STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /**< HC: Profiling of the virtual handler updates. */
2085 STAMCOUNTER StatHCSyncCR3Global; /**< HC: The number of global CR3 syncs. */
2086 STAMCOUNTER StatHCSyncCR3NotGlobal; /**< HC: The number of non-global CR3 syncs. */
2087 STAMCOUNTER StatHCSyncCR3DstFreed; /**< HC: The number of times we've had to free a shadow entry. */
2088 STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /**< HC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2089 STAMCOUNTER StatHCSyncCR3DstNotPresent; /**< HC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2090 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /**< HC: The number of times a global page directory wasn't flushed. */
2091 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /**< HC: The number of times a page table with only global entries wasn't flushed. */
2092 STAMCOUNTER StatHCSyncCR3DstCacheHit; /**< HC: The number of times we got some kind of cache hit on a page table. */
2093
2094 /** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2095 STAMPROFILE StatVirtHandleSearchByPhysGC;
2096 /** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2097 STAMPROFILE StatVirtHandleSearchByPhysHC;
2098 /** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2099 STAMCOUNTER StatHandlePhysicalReset;
2100
2101 STAMPROFILE StatCheckPageFault;
2102 STAMPROFILE StatLazySyncPT;
2103 STAMPROFILE StatMapping;
2104 STAMPROFILE StatOutOfSync;
2105 STAMPROFILE StatHandlers;
2106 STAMPROFILE StatEIPHandlers;
2107 STAMPROFILE StatHCPrefetch;
2108
2109# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2110 /** The number of first time shadowings. */
2111 STAMCOUNTER StatTrackVirgin;
2112 /** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2113 STAMCOUNTER StatTrackAliased;
2114 /** The number of times we're tracking using cRef2. */
2115 STAMCOUNTER StatTrackAliasedMany;
2116 /** The number of times we're hitting pages which has overflowed cRef2. */
2117 STAMCOUNTER StatTrackAliasedLots;
2118 /** The number of times the extent list grows to long. */
2119 STAMCOUNTER StatTrackOverflows;
2120 /** Profiling of SyncPageWorkerTrackDeref (expensive). */
2121 STAMPROFILE StatTrackDeref;
2122# endif
2123
2124 /** Ring-3/0 page mapper TLB hits. */
2125 STAMCOUNTER StatPageHCMapTlbHits;
2126 /** Ring-3/0 page mapper TLB misses. */
2127 STAMCOUNTER StatPageHCMapTlbMisses;
2128 /** Ring-3/0 chunk mapper TLB hits. */
2129 STAMCOUNTER StatChunkR3MapTlbHits;
2130 /** Ring-3/0 chunk mapper TLB misses. */
2131 STAMCOUNTER StatChunkR3MapTlbMisses;
2132 /** Times a shared page has been replaced by a private one. */
2133 STAMCOUNTER StatPageReplaceShared;
2134 /** Times the zero page has been replaced by a private one. */
2135 STAMCOUNTER StatPageReplaceZero;
2136 /** The number of times we've executed GMMR3AllocateHandyPages. */
2137 STAMCOUNTER StatPageHandyAllocs;
2138
2139 /** Allocated mbs of guest ram */
2140 STAMCOUNTER StatDynRamTotal;
2141 /** Nr of pgmr3PhysGrowRange calls. */
2142 STAMCOUNTER StatDynRamGrow;
2143
2144 STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2145 STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2146 STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2147#endif
2148} PGM, *PPGM;
2149
2150
2151/** @name PGM::fSyncFlags Flags
2152 * @{
2153 */
2154/** Updates the MM_RAM_FLAGS_VIRTUAL_HANDLER page bit. */
2155#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2156/** Always sync CR3. */
2157#define PGM_SYNC_ALWAYS RT_BIT(1)
2158/** Check monitoring on next CR3 (re)load and invalidate page. */
2159#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2160/** Clear the page pool (a light weight flush). */
2161#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2162/** @} */
2163
2164
2165__BEGIN_DECLS
2166
2167PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2168PGMDECL(int) pgmGuestROMWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2169PGMGCDECL(int) pgmCachePTWriteGC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2170int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PVBOXPD pPDSrc, int iPDOld);
2171PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2172void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, int iPDOld, int iPDNew);
2173int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
2174int pgmLock(PVM pVM);
2175void pgmUnlock(PVM pVM);
2176
2177void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2178int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2179DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2180#ifdef VBOX_STRICT
2181void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2182#else
2183# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2184#endif
2185DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2186
2187
2188int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2189#ifdef IN_RING3
2190int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2191#ifndef NEW_PHYS_CODE
2192int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2193#endif
2194
2195int pgmR3PoolInit(PVM pVM);
2196void pgmR3PoolRelocate(PVM pVM);
2197void pgmR3PoolReset(PVM pVM);
2198
2199#endif /* IN_RING3 */
2200#ifdef IN_GC
2201void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2202#endif
2203int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage);
2204PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2205void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable);
2206void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
2207int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2208void pgmPoolFlushAll(PVM pVM);
2209void pgmPoolClearAll(PVM pVM);
2210void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2211void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2212int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2213PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2214void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2215void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2216uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2217void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2218#ifdef PGMPOOL_WITH_MONITORING
2219# ifdef IN_RING3
2220void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2221# else
2222void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2223# endif
2224int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2225void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2226void pgmPoolMonitorModifiedClearAll(PVM pVM);
2227int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2228int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2229#endif
2230
2231__END_DECLS
2232
2233
2234/**
2235 * Gets the PGMPAGE structure for a guest page.
2236 *
2237 * @returns Pointer to the page on success.
2238 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2239 *
2240 * @param pPGM PGM handle.
2241 * @param GCPhys The GC physical address.
2242 */
2243DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2244{
2245 /*
2246 * Optimize for the first range.
2247 */
2248 PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges);
2249 RTGCPHYS off = GCPhys - pRam->GCPhys;
2250 if (RT_UNLIKELY(off >= pRam->cb))
2251 {
2252 do
2253 {
2254 pRam = CTXSUFF(pRam->pNext);
2255 if (RT_UNLIKELY(!pRam))
2256 return NULL;
2257 off = GCPhys - pRam->GCPhys;
2258 } while (off >= pRam->cb);
2259 }
2260 return &pRam->aPages[off >> PAGE_SHIFT];
2261}
2262
2263
2264/**
2265 * Gets the PGMPAGE structure for a guest page.
2266 *
2267 * Old Phys code: Will make sure the page is present.
2268 *
2269 * @returns VBox status code.
2270 * @retval VINF_SUCCESS and a valid *ppPage on success.
2271 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2272 *
2273 * @param pPGM PGM handle.
2274 * @param GCPhys The GC physical address.
2275 * @param ppPage Where to store the page poitner on success.
2276 */
2277DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2278{
2279 /*
2280 * Optimize for the first range.
2281 */
2282 PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges);
2283 RTGCPHYS off = GCPhys - pRam->GCPhys;
2284 if (RT_UNLIKELY(off >= pRam->cb))
2285 {
2286 do
2287 {
2288 pRam = CTXSUFF(pRam->pNext);
2289 if (RT_UNLIKELY(!pRam))
2290 {
2291 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2292 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2293 }
2294 off = GCPhys - pRam->GCPhys;
2295 } while (off >= pRam->cb);
2296 }
2297 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2298#ifndef NEW_PHYS_CODE
2299
2300 /*
2301 * Make sure it's present.
2302 */
2303 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2304 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2305 {
2306#ifdef IN_RING3
2307 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2308#else
2309 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2310#endif
2311 if (VBOX_FAILURE(rc))
2312 {
2313 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2314 return rc;
2315 }
2316 Assert(rc == VINF_SUCCESS);
2317 }
2318#endif
2319 return VINF_SUCCESS;
2320}
2321
2322
2323
2324
2325/**
2326 * Gets the PGMPAGE structure for a guest page.
2327 *
2328 * Old Phys code: Will make sure the page is present.
2329 *
2330 * @returns VBox status code.
2331 * @retval VINF_SUCCESS and a valid *ppPage on success.
2332 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2333 *
2334 * @param pPGM PGM handle.
2335 * @param GCPhys The GC physical address.
2336 * @param ppPage Where to store the page poitner on success.
2337 * @param ppRamHint Where to read and store the ram list hint.
2338 * The caller initializes this to NULL before the call.
2339 */
2340DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2341{
2342 RTGCPHYS off;
2343 PPGMRAMRANGE pRam = *ppRamHint;
2344 if ( !pRam
2345 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2346 {
2347 pRam = CTXSUFF(pPGM->pRamRanges);
2348 off = GCPhys - pRam->GCPhys;
2349 if (RT_UNLIKELY(off >= pRam->cb))
2350 {
2351 do
2352 {
2353 pRam = CTXSUFF(pRam->pNext);
2354 if (RT_UNLIKELY(!pRam))
2355 {
2356 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2357 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2358 }
2359 off = GCPhys - pRam->GCPhys;
2360 } while (off >= pRam->cb);
2361 }
2362 *ppRamHint = pRam;
2363 }
2364 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2365#ifndef NEW_PHYS_CODE
2366
2367 /*
2368 * Make sure it's present.
2369 */
2370 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2371 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2372 {
2373#ifdef IN_RING3
2374 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2375#else
2376 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2377#endif
2378 if (VBOX_FAILURE(rc))
2379 {
2380 *ppPage = NULL; /* Shut up annoying smart ass. */
2381 return rc;
2382 }
2383 Assert(rc == VINF_SUCCESS);
2384 }
2385#endif
2386 return VINF_SUCCESS;
2387}
2388
2389
2390/**
2391 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2392 *
2393 * @returns Pointer to the page on success.
2394 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2395 *
2396 * @param pPGM PGM handle.
2397 * @param GCPhys The GC physical address.
2398 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2399 */
2400DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2401{
2402 /*
2403 * Optimize for the first range.
2404 */
2405 PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges);
2406 RTGCPHYS off = GCPhys - pRam->GCPhys;
2407 if (RT_UNLIKELY(off >= pRam->cb))
2408 {
2409 do
2410 {
2411 pRam = CTXSUFF(pRam->pNext);
2412 if (RT_UNLIKELY(!pRam))
2413 return NULL;
2414 off = GCPhys - pRam->GCPhys;
2415 } while (off >= pRam->cb);
2416 }
2417 *ppRam = pRam;
2418 return &pRam->aPages[off >> PAGE_SHIFT];
2419}
2420
2421
2422
2423
2424/**
2425 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2426 *
2427 * @returns Pointer to the page on success.
2428 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2429 *
2430 * @param pPGM PGM handle.
2431 * @param GCPhys The GC physical address.
2432 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2433 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2434 */
2435DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2436{
2437 /*
2438 * Optimize for the first range.
2439 */
2440 PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges);
2441 RTGCPHYS off = GCPhys - pRam->GCPhys;
2442 if (RT_UNLIKELY(off >= pRam->cb))
2443 {
2444 do
2445 {
2446 pRam = CTXSUFF(pRam->pNext);
2447 if (RT_UNLIKELY(!pRam))
2448 {
2449 *ppRam = NULL; /* Shut up silly GCC warnings. */
2450 *ppPage = NULL; /* ditto */
2451 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2452 }
2453 off = GCPhys - pRam->GCPhys;
2454 } while (off >= pRam->cb);
2455 }
2456 *ppRam = pRam;
2457 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2458#ifndef NEW_PHYS_CODE
2459
2460 /*
2461 * Make sure it's present.
2462 */
2463 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2464 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2465 {
2466#ifdef IN_RING3
2467 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2468#else
2469 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2470#endif
2471 if (VBOX_FAILURE(rc))
2472 {
2473 *ppPage = NULL; /* Shut up silly GCC warnings. */
2474 *ppPage = NULL; /* ditto */
2475 return rc;
2476 }
2477 Assert(rc == VINF_SUCCESS);
2478
2479 }
2480#endif
2481 return VINF_SUCCESS;
2482}
2483
2484
2485/**
2486 * Convert GC Phys to HC Phys.
2487 *
2488 * @returns VBox status.
2489 * @param pPGM PGM handle.
2490 * @param GCPhys The GC physical address.
2491 * @param pHCPhys Where to store the corresponding HC physical address.
2492 *
2493 * @deprecated Doesn't deal with zero, shared or write monitored pages.
2494 * Avoid when writing new code!
2495 */
2496DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2497{
2498 PPGMPAGE pPage;
2499 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2500 if (VBOX_FAILURE(rc))
2501 return rc;
2502 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
2503 return VINF_SUCCESS;
2504}
2505
2506
2507#ifndef IN_GC
2508/**
2509 * Queries the Physical TLB entry for a physical guest page,
2510 * attemting to load the TLB entry if necessary.
2511 *
2512 * @returns VBox status code.
2513 * @retval VINF_SUCCESS on success
2514 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2515 * @param pPGM The PGM instance handle.
2516 * @param GCPhys The address of the guest page.
2517 * @param ppTlbe Where to store the pointer to the TLB entry.
2518 */
2519
2520DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2521{
2522 int rc;
2523 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2524 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2525 {
2526 STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
2527 rc = VINF_SUCCESS;
2528 }
2529 else
2530 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
2531 *ppTlbe = pTlbe;
2532 return rc;
2533}
2534#endif /* !IN_GC */
2535
2536
2537#ifndef NEW_PHYS_CODE
2538/**
2539 * Convert GC Phys to HC Virt.
2540 *
2541 * @returns VBox status.
2542 * @param pPGM PGM handle.
2543 * @param GCPhys The GC physical address.
2544 * @param pHCPtr Where to store the corresponding HC virtual address.
2545 *
2546 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
2547 */
2548DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2549{
2550 PPGMRAMRANGE pRam;
2551 PPGMPAGE pPage;
2552 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2553 if (VBOX_FAILURE(rc))
2554 {
2555 *pHCPtr = 0; /* Shut up silly GCC warnings. */
2556 return rc;
2557 }
2558 RTGCPHYS off = GCPhys - pRam->GCPhys;
2559
2560 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2561 {
2562 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
2563 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2564 return VINF_SUCCESS;
2565 }
2566 if (pRam->pvHC)
2567 {
2568 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2569 return VINF_SUCCESS;
2570 }
2571 *pHCPtr = 0; /* Shut up silly GCC warnings. */
2572 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2573}
2574#endif /* !NEW_PHYS_CODE */
2575
2576
2577/**
2578 * Convert GC Phys to HC Virt.
2579 *
2580 * @returns VBox status.
2581 * @param PVM VM handle.
2582 * @param pRam Ram range
2583 * @param GCPhys The GC physical address.
2584 * @param pHCPtr Where to store the corresponding HC virtual address.
2585 *
2586 * @deprecated This will be eliminated. Don't use it.
2587 */
2588DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2589{
2590 RTGCPHYS off = GCPhys - pRam->GCPhys;
2591 Assert(off < pRam->cb);
2592
2593 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2594 {
2595 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
2596 /* Physical chunk in dynamically allocated range not present? */
2597 if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
2598 {
2599#ifdef IN_RING3
2600 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2601#else
2602 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2603#endif
2604 if (rc != VINF_SUCCESS)
2605 {
2606 *pHCPtr = 0; /* GCC crap */
2607 return rc;
2608 }
2609 }
2610 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2611 return VINF_SUCCESS;
2612 }
2613 if (pRam->pvHC)
2614 {
2615 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2616 return VINF_SUCCESS;
2617 }
2618 *pHCPtr = 0; /* GCC crap */
2619 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2620}
2621
2622
2623/**
2624 * Convert GC Phys to HC Virt and HC Phys.
2625 *
2626 * @returns VBox status.
2627 * @param pPGM PGM handle.
2628 * @param GCPhys The GC physical address.
2629 * @param pHCPtr Where to store the corresponding HC virtual address.
2630 * @param pHCPhys Where to store the HC Physical address and its flags.
2631 *
2632 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
2633 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
2634 */
2635DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
2636{
2637 PPGMRAMRANGE pRam;
2638 PPGMPAGE pPage;
2639 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2640 if (VBOX_FAILURE(rc))
2641 {
2642 *pHCPtr = 0; /* Shut up crappy GCC warnings */
2643 *pHCPhys = 0; /* ditto */
2644 return rc;
2645 }
2646 RTGCPHYS off = GCPhys - pRam->GCPhys;
2647
2648 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
2649 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2650 {
2651 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
2652 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2653 return VINF_SUCCESS;
2654 }
2655 if (pRam->pvHC)
2656 {
2657 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
2658 return VINF_SUCCESS;
2659 }
2660 *pHCPtr = 0;
2661 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2662}
2663
2664
2665/**
2666 * Clears flags associated with a RAM address.
2667 *
2668 * @returns VBox status code.
2669 * @param pPGM PGM handle.
2670 * @param GCPhys Guest context physical address.
2671 * @param fFlags fFlags to clear. (Bits 0-11.)
2672 */
2673DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
2674{
2675 PPGMPAGE pPage;
2676 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2677 if (VBOX_FAILURE(rc))
2678 return rc;
2679
2680 fFlags &= ~X86_PTE_PAE_PG_MASK;
2681 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
2682 return VINF_SUCCESS;
2683}
2684
2685
2686/**
2687 * Clears flags associated with a RAM address.
2688 *
2689 * @returns VBox status code.
2690 * @param pPGM PGM handle.
2691 * @param GCPhys Guest context physical address.
2692 * @param fFlags fFlags to clear. (Bits 0-11.)
2693 * @param ppRamHint Where to read and store the ram list hint.
2694 * The caller initializes this to NULL before the call.
2695 */
2696DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
2697{
2698 PPGMPAGE pPage;
2699 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
2700 if (VBOX_FAILURE(rc))
2701 return rc;
2702
2703 fFlags &= ~X86_PTE_PAE_PG_MASK;
2704 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
2705 return VINF_SUCCESS;
2706}
2707
2708/**
2709 * Sets (bitwise OR) flags associated with a RAM address.
2710 *
2711 * @returns VBox status code.
2712 * @param pPGM PGM handle.
2713 * @param GCPhys Guest context physical address.
2714 * @param fFlags fFlags to set clear. (Bits 0-11.)
2715 */
2716DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
2717{
2718 PPGMPAGE pPage;
2719 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2720 if (VBOX_FAILURE(rc))
2721 return rc;
2722
2723 fFlags &= ~X86_PTE_PAE_PG_MASK;
2724 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
2725 return VINF_SUCCESS;
2726}
2727
2728
2729/**
2730 * Sets (bitwise OR) flags associated with a RAM address.
2731 *
2732 * @returns VBox status code.
2733 * @param pPGM PGM handle.
2734 * @param GCPhys Guest context physical address.
2735 * @param fFlags fFlags to set clear. (Bits 0-11.)
2736 * @param ppRamHint Where to read and store the ram list hint.
2737 * The caller initializes this to NULL before the call.
2738 */
2739DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
2740{
2741 PPGMPAGE pPage;
2742 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
2743 if (VBOX_FAILURE(rc))
2744 return rc;
2745
2746 fFlags &= ~X86_PTE_PAE_PG_MASK;
2747 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
2748 return VINF_SUCCESS;
2749}
2750
2751
2752/**
2753 * Gets the page directory for the specified address.
2754 *
2755 * @returns Pointer to the page directory in question.
2756 * @returns NULL if the page directory is not present or on an invalid page.
2757 * @param pPGM Pointer to the PGM instance data.
2758 * @param GCPtr The address.
2759 */
2760DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
2761{
2762 const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2763 if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2764 {
2765 if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2766 return CTXSUFF(pPGM->apGstPaePDs)[iPdPtr];
2767
2768 /* cache is out-of-sync. */
2769 PX86PDPAE pPD;
2770 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2771 if (VBOX_SUCCESS(rc))
2772 return pPD;
2773 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2774 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
2775 }
2776 return NULL;
2777}
2778
2779
2780/**
2781 * Gets the page directory entry for the specified address.
2782 *
2783 * @returns Pointer to the page directory entry in question.
2784 * @returns NULL if the page directory is not present or on an invalid page.
2785 * @param pPGM Pointer to the PGM instance data.
2786 * @param GCPtr The address.
2787 */
2788DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
2789{
2790 const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2791 if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2792 {
2793 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
2794 if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2795 return &CTXSUFF(pPGM->apGstPaePDs)[iPdPtr]->a[iPD];
2796
2797 /* The cache is out-of-sync. */
2798 PX86PDPAE pPD;
2799 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2800 if (VBOX_SUCCESS(rc))
2801 return &pPD->a[iPD];
2802 AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2803 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
2804 }
2805 return NULL;
2806}
2807
2808
2809/**
2810 * Gets the page directory entry for the specified address.
2811 *
2812 * @returns The page directory entry in question.
2813 * @returns A non-present entry if the page directory is not present or on an invalid page.
2814 * @param pPGM Pointer to the PGM instance data.
2815 * @param GCPtr The address.
2816 */
2817DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
2818{
2819 const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2820 if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2821 {
2822 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
2823 if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2824 return CTXSUFF(pPGM->apGstPaePDs)[iPdPtr]->a[iPD].u;
2825
2826 /* cache is out-of-sync. */
2827 PX86PDPAE pPD;
2828 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2829 if (VBOX_SUCCESS(rc))
2830 return pPD->a[iPD].u;
2831 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2832 }
2833 return 0;
2834}
2835
2836
2837/**
2838 * Gets the page directory for the specified address and returns the index into the page directory
2839 *
2840 * @returns Pointer to the page directory in question.
2841 * @returns NULL if the page directory is not present or on an invalid page.
2842 * @param pPGM Pointer to the PGM instance data.
2843 * @param GCPtr The address.
2844 * @param piPD Receives the index into the returned page directory
2845 */
2846DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
2847{
2848 const unsigned iPdPtr = GCPtr >> X86_PDPTR_SHIFT;
2849 if (CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].n.u1Present)
2850 {
2851 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
2852 if ((CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPtr])
2853 {
2854 *piPD = iPD;
2855 return CTXSUFF(pPGM->apGstPaePDs)[iPdPtr];
2856 }
2857
2858 /* cache is out-of-sync. */
2859 PX86PDPAE pPD;
2860 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u & X86_PDPE_PG_MASK, &pPD);
2861 if (VBOX_SUCCESS(rc))
2862 {
2863 *piPD = iPD;
2864 return pPD;
2865 }
2866 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPTR)->a[iPdPtr].u));
2867 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
2868 }
2869 return NULL;
2870}
2871
2872
2873/**
2874 * Checks if any of the specified page flags are set for the given page.
2875 *
2876 * @returns true if any of the flags are set.
2877 * @returns false if all the flags are clear.
2878 * @param pPGM PGM handle.
2879 * @param GCPhys The GC physical address.
2880 * @param fFlags The flags to check for.
2881 */
2882DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
2883{
2884 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
2885 return pPage
2886 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
2887}
2888
2889
2890/**
2891 * Gets the ram flags for a handler.
2892 *
2893 * @returns The ram flags.
2894 * @param pCur The physical handler in question.
2895 */
2896DECLINLINE(unsigned) pgmHandlerPhysicalCalcFlags(PPGMPHYSHANDLER pCur)
2897{
2898 switch (pCur->enmType)
2899 {
2900 case PGMPHYSHANDLERTYPE_PHYSICAL:
2901 return MM_RAM_FLAGS_PHYSICAL_HANDLER;
2902
2903 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
2904 return MM_RAM_FLAGS_PHYSICAL_HANDLER | MM_RAM_FLAGS_PHYSICAL_WRITE;
2905
2906 case PGMPHYSHANDLERTYPE_MMIO:
2907 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
2908 return MM_RAM_FLAGS_PHYSICAL_HANDLER | MM_RAM_FLAGS_PHYSICAL_ALL;
2909
2910 default:
2911 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
2912 }
2913}
2914
2915
2916/**
2917 * Clears one physical page of a virtual handler
2918 *
2919 * @param pPGM Pointer to the PGM instance.
2920 * @param pCur Virtual handler structure
2921 * @param iPage Physical page index
2922 */
2923DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
2924{
2925 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
2926
2927 /*
2928 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
2929 */
2930#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2931 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
2932 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2933 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
2934#endif
2935 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
2936 {
2937 /* We're the head of the alias chain. */
2938 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
2939#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2940 AssertReleaseMsg(pRemove != NULL,
2941 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2942 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
2943 AssertReleaseMsg(pRemove == pPhys2Virt,
2944 ("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
2945 " got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2946 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
2947 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
2948#endif
2949 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
2950 {
2951 /* Insert the next list in the alias chain into the tree. */
2952 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
2953#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2954 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
2955 ("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
2956 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
2957#endif
2958 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
2959 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
2960 AssertRelease(fRc);
2961 }
2962 }
2963 else
2964 {
2965 /* Locate the previous node in the alias chain. */
2966 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
2967#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2968 AssertReleaseMsg(pPrev != pPhys2Virt,
2969 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
2970 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
2971#endif
2972 for (;;)
2973 {
2974 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
2975 if (pNext == pPhys2Virt)
2976 {
2977 /* unlink. */
2978 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
2979 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
2980 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
2981 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
2982 else
2983 {
2984 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
2985 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
2986 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
2987 }
2988 break;
2989 }
2990
2991 /* next */
2992 if (pNext == pPrev)
2993 {
2994#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
2995 AssertReleaseMsg(pNext != pPrev,
2996 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
2997 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
2998#endif
2999 break;
3000 }
3001 pPrev = pNext;
3002 }
3003 }
3004 Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3005 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3006 pPhys2Virt->offNextAlias = 0;
3007 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3008
3009 /*
3010 * Clear the ram flags for this page.
3011 */
3012 int rc = pgmRamFlagsClearByGCPhys(pPGM, pPhys2Virt->Core.Key,
3013 MM_RAM_FLAGS_VIRTUAL_HANDLER | MM_RAM_FLAGS_VIRTUAL_ALL | MM_RAM_FLAGS_VIRTUAL_WRITE);
3014 AssertRC(rc);
3015}
3016
3017
3018/**
3019 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3020 *
3021 * @returns Pointer to the shadow page structure.
3022 * @param pPool The pool.
3023 * @param HCPhys The HC physical address of the shadow page.
3024 */
3025DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3026{
3027 /*
3028 * Look up the page.
3029 */
3030 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3031 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3032 return pPage;
3033}
3034
3035
3036/**
3037 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3038 *
3039 * @returns Pointer to the shadow page structure.
3040 * @param pPool The pool.
3041 * @param idx The pool page index.
3042 */
3043DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3044{
3045 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3046 return &pPool->aPages[idx];
3047}
3048
3049
3050#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3051/**
3052 * Clear references to guest physical memory.
3053 *
3054 * @param pPool The pool.
3055 * @param pPoolPage The pool page.
3056 * @param pPhysPage The physical guest page tracking structure.
3057 */
3058DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3059{
3060 /*
3061 * Just deal with the simple case here.
3062 */
3063#ifdef LOG_ENABLED
3064 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3065#endif
3066 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3067 if (cRefs == 1)
3068 {
3069 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3070 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3071 }
3072 else
3073 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3074 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3075}
3076#endif
3077
3078
3079#ifdef PGMPOOL_WITH_CACHE
3080/**
3081 * Moves the page to the head of the age list.
3082 *
3083 * This is done when the cached page is used in one way or another.
3084 *
3085 * @param pPool The pool.
3086 * @param pPage The cached page.
3087 * @todo inline in PGMInternal.h!
3088 */
3089DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3090{
3091 /*
3092 * Move to the head of the age list.
3093 */
3094 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3095 {
3096 /* unlink */
3097 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3098 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3099 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3100 else
3101 pPool->iAgeTail = pPage->iAgePrev;
3102
3103 /* insert at head */
3104 pPage->iAgePrev = NIL_PGMPOOL_IDX;
3105 pPage->iAgeNext = pPool->iAgeHead;
3106 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3107 pPool->iAgeHead = pPage->idx;
3108 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3109 }
3110}
3111#endif /* PGMPOOL_WITH_CACHE */
3112
3113/**
3114 * Tells if mappings are to be put into the shadow page table or not
3115 *
3116 * @returns boolean result
3117 * @param pVM VM handle.
3118 */
3119
3120DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3121{
3122 return !pPGM->fDisableMappings;
3123}
3124
3125/** @} */
3126
3127#endif
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette