PGMInternal.h@ 30326

Last change on this file since 30326 was 30326, checked in by vboxsync, 15 years ago
PGM: PGMShwModifyPage/PGMShwSetPage -> PGMShwMakePageWritable, PGMShwMakePageReadonly & PGMShwMakePageNotPresent and made the low level worker make the page writable before setting the X86_PTE_RW bit. PGMR3PhysTlbGCPhys2Ptr should make write monitored pages writable (?). PGMDynMapGCPage and PGMDynMapGCPageOff must make the pages writable and take the PGM lock.
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File size: 157.9 KB

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1	/* $Id: PGMInternal.h 30326 2010-06-21 12:35:33Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/stam.h>
25	#include <VBox/param.h>
26	#include <VBox/vmm.h>
27	#include <VBox/mm.h>
28	#include <VBox/pdmcritsect.h>
29	#include <VBox/pdmapi.h>
30	#include <VBox/dis.h>
31	#include <VBox/dbgf.h>
32	#include <VBox/log.h>
33	#include <VBox/gmm.h>
34	#include <VBox/hwaccm.h>
35	#include <iprt/asm.h>
36	#include <iprt/assert.h>
37	#include <iprt/avl.h>
38	#include <iprt/critsect.h>
39	#include <iprt/sha.h>
40
41
42
43	/** @defgroup grp_pgm_int Internals
44	* @ingroup grp_pgm
45	* @internal
46	* @{
47	*/
48
49
50	/** @name PGM Compile Time Config
51	* @{
52	*/
53
54	/**
55	* Indicates that there are no guest mappings to care about.
56	* Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
57	*/
58	#if defined(IN_RING0) \|\| !defined(VBOX_WITH_RAW_MODE)
59	# define PGM_WITHOUT_MAPPINGS
60	#endif
61
62	/**
63	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
64	* Comment it if it will break something.
65	*/
66	#define PGM_OUT_OF_SYNC_IN_GC
67
68	/**
69	* Check and skip global PDEs for non-global flushes
70	*/
71	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
72
73	/**
74	* Optimization for PAE page tables that are modified often
75	*/
76	//#if 0 /* disabled again while debugging */
77	#ifndef IN_RC
78	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
79	#endif
80	//#endif
81
82	/**
83	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
84	*/
85	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
86	# define PGM_WITH_LARGE_PAGES
87	#endif
88
89	/**
90	* Sync N pages instead of a whole page table
91	*/
92	#define PGM_SYNC_N_PAGES
93
94	/**
95	* Number of pages to sync during a page fault
96	*
97	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
98	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
99	*
100	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
101	* world switch overhead, so let's sync more.
102	*/
103	# ifdef IN_RING0
104	/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
105	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
106	* but ~5% fewer faults.
107	*/
108	# define PGM_SYNC_NR_PAGES 32
109	#else
110	# define PGM_SYNC_NR_PAGES 8
111	#endif
112
113	/**
114	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
115	*/
116	#define PGM_MAX_PHYSCACHE_ENTRIES 64
117	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
118
119
120	/** @def PGMPOOL_CFG_MAX_GROW
121	* The maximum number of pages to add to the pool in one go.
122	*/
123	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
124
125	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
126	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
127	*/
128	#ifdef VBOX_STRICT
129	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
130	#endif
131
132	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
133	* Enables the experimental lazy page allocation code. */
134	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
135
136	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
137	* Enables real write monitoring of pages, i.e. mapping them read-only and
138	* only making them writable when getting a write access #PF. */
139	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
140
141	/** @} */
142
143
144	/** @name PDPT and PML4 flags.
145	* These are placed in the three bits available for system programs in
146	* the PDPT and PML4 entries.
147	* @{ */
148	/** The entry is a permanent one and it's must always be present.
149	* Never free such an entry. */
150	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
151	/** Mapping (hypervisor allocated pagetable). */
152	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
153	/** @} */
154
155	/** @name Page directory flags.
156	* These are placed in the three bits available for system programs in
157	* the page directory entries.
158	* @{ */
159	/** Mapping (hypervisor allocated pagetable). */
160	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
161	/** Made read-only to facilitate dirty bit tracking. */
162	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
163	/** @} */
164
165	/** @name Page flags.
166	* These are placed in the three bits available for system programs in
167	* the page entries.
168	* @{ */
169	/** Made read-only to facilitate dirty bit tracking. */
170	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
171
172	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
173	/** Scanned and approved by CSAM (tm).
174	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
175	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
176	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
177	#endif
178
179	/** @} */
180
181	/** @name Defines used to indicate the shadow and guest paging in the templates.
182	* @{ */
183	#define PGM_TYPE_REAL 1
184	#define PGM_TYPE_PROT 2
185	#define PGM_TYPE_32BIT 3
186	#define PGM_TYPE_PAE 4
187	#define PGM_TYPE_AMD64 5
188	#define PGM_TYPE_NESTED 6
189	#define PGM_TYPE_EPT 7
190	#define PGM_TYPE_MAX PGM_TYPE_EPT
191	/** @} */
192
193	/** Macro for checking if the guest is using paging.
194	* @param uGstType PGM_TYPE_*
195	* @param uShwType PGM_TYPE_*
196	* @remark ASSUMES certain order of the PGM_TYPE_* values.
197	*/
198	#define PGM_WITH_PAGING(uGstType, uShwType) \
199	( (uGstType) >= PGM_TYPE_32BIT \
200	&& (uShwType) != PGM_TYPE_NESTED \
201	&& (uShwType) != PGM_TYPE_EPT)
202
203	/** Macro for checking if the guest supports the NX bit.
204	* @param uGstType PGM_TYPE_*
205	* @param uShwType PGM_TYPE_*
206	* @remark ASSUMES certain order of the PGM_TYPE_* values.
207	*/
208	#define PGM_WITH_NX(uGstType, uShwType) \
209	( (uGstType) >= PGM_TYPE_PAE \
210	&& (uShwType) != PGM_TYPE_NESTED \
211	&& (uShwType) != PGM_TYPE_EPT)
212
213
214	/** @def PGM_HCPHYS_2_PTR
215	* Maps a HC physical page pool address to a virtual address.
216	*
217	* @returns VBox status code.
218	* @param pVM The VM handle.
219	* @param HCPhys The HC physical address to map to a virtual one.
220	* @param ppv Where to store the virtual address. No need to cast this.
221	*
222	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
223	* small page window employeed by that function. Be careful.
224	* @remark There is no need to assert on the result.
225	*/
226	#ifdef IN_RC
227	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
228	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
229	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
230	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
231	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
232	#else
233	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
234	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
235	#endif
236
237	/** @def PGM_GCPHYS_2_PTR
238	* Maps a GC physical page address to a virtual address.
239	*
240	* @returns VBox status code.
241	* @param pVM The VM handle.
242	* @param GCPhys The GC physical address to map to a virtual one.
243	* @param ppv Where to store the virtual address. No need to cast this.
244	*
245	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
246	* small page window employeed by that function. Be careful.
247	* @remark There is no need to assert on the result.
248	*/
249	#ifdef IN_RC
250	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
251	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
252	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
253	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
254	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
255	#else
256	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
257	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
258	#endif
259
260	/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
261	* Maps a GC physical page address to a virtual address.
262	*
263	* @returns VBox status code.
264	* @param pPGM Pointer to the PGM instance data.
265	* @param GCPhys The GC physical address to map to a virtual one.
266	* @param ppv Where to store the virtual address. No need to cast this.
267	*
268	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
269	* small page window employeed by that function. Be careful.
270	* @remark There is no need to assert on the result.
271	*/
272	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
273	# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
274	pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
275	#else
276	# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
277	PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
278	#endif
279
280	/** @def PGM_GCPHYS_2_PTR_EX
281	* Maps a unaligned GC physical page address to a virtual address.
282	*
283	* @returns VBox status code.
284	* @param pVM The VM handle.
285	* @param GCPhys The GC physical address to map to a virtual one.
286	* @param ppv Where to store the virtual address. No need to cast this.
287	*
288	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
289	* small page window employeed by that function. Be careful.
290	* @remark There is no need to assert on the result.
291	*/
292	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
293	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
294	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
295	#else
296	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
297	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
298	#endif
299
300	/** @def PGM_INVL_PG
301	* Invalidates a page.
302	*
303	* @param pVCpu The VMCPU handle.
304	* @param GCVirt The virtual address of the page to invalidate.
305	*/
306	#ifdef IN_RC
307	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
308	#elif defined(IN_RING0)
309	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
310	#else
311	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
312	#endif
313
314	/** @def PGM_INVL_PG_ALL_VCPU
315	* Invalidates a page on all VCPUs
316	*
317	* @param pVM The VM handle.
318	* @param GCVirt The virtual address of the page to invalidate.
319	*/
320	#ifdef IN_RC
321	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
322	#elif defined(IN_RING0)
323	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
324	#else
325	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
326	#endif
327
328	/** @def PGM_INVL_BIG_PG
329	* Invalidates a 4MB page directory entry.
330	*
331	* @param pVCpu The VMCPU handle.
332	* @param GCVirt The virtual address within the page directory to invalidate.
333	*/
334	#ifdef IN_RC
335	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
336	#elif defined(IN_RING0)
337	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
338	#else
339	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
340	#endif
341
342	/** @def PGM_INVL_VCPU_TLBS()
343	* Invalidates the TLBs of the specified VCPU
344	*
345	* @param pVCpu The VMCPU handle.
346	*/
347	#ifdef IN_RC
348	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
349	#elif defined(IN_RING0)
350	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
351	#else
352	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
353	#endif
354
355	/** @def PGM_INVL_ALL_VCPU_TLBS()
356	* Invalidates the TLBs of all VCPUs
357	*
358	* @param pVM The VM handle.
359	*/
360	#ifdef IN_RC
361	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
362	#elif defined(IN_RING0)
363	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
364	#else
365	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
366	#endif
367
368	/** Size of the GCPtrConflict array in PGMMAPPING.
369	* @remarks Must be a power of two. */
370	#define PGMMAPPING_CONFLICT_MAX 8
371
372	/**
373	* Structure for tracking GC Mappings.
374	*
375	* This structure is used by linked list in both GC and HC.
376	*/
377	typedef struct PGMMAPPING
378	{
379	/** Pointer to next entry. */
380	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
381	/** Pointer to next entry. */
382	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
383	/** Pointer to next entry. */
384	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
385	/** Indicate whether this entry is finalized. */
386	bool fFinalized;
387	/** Start Virtual address. */
388	RTGCPTR GCPtr;
389	/** Last Virtual address (inclusive). */
390	RTGCPTR GCPtrLast;
391	/** Range size (bytes). */
392	RTGCPTR cb;
393	/** Pointer to relocation callback function. */
394	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
395	/** User argument to the callback. */
396	R3PTRTYPE(void *) pvUser;
397	/** Mapping description / name. For easing debugging. */
398	R3PTRTYPE(const char *) pszDesc;
399	/** Last 8 addresses that caused conflicts. */
400	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
401	/** Number of conflicts for this hypervisor mapping. */
402	uint32_t cConflicts;
403	/** Number of page tables. */
404	uint32_t cPTs;
405
406	/** Array of page table mapping data. Each entry
407	* describes one page table. The array can be longer
408	* than the declared length.
409	*/
410	struct
411	{
412	/** The HC physical address of the page table. */
413	RTHCPHYS HCPhysPT;
414	/** The HC physical address of the first PAE page table. */
415	RTHCPHYS HCPhysPaePT0;
416	/** The HC physical address of the second PAE page table. */
417	RTHCPHYS HCPhysPaePT1;
418	/** The HC virtual address of the 32-bit page table. */
419	R3PTRTYPE(PX86PT) pPTR3;
420	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
421	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
422	/** The RC virtual address of the 32-bit page table. */
423	RCPTRTYPE(PX86PT) pPTRC;
424	/** The RC virtual address of the two PAE page table. */
425	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
426	/** The R0 virtual address of the 32-bit page table. */
427	R0PTRTYPE(PX86PT) pPTR0;
428	/** The R0 virtual address of the two PAE page table. */
429	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
430	} aPTs[1];
431	} PGMMAPPING;
432	/** Pointer to structure for tracking GC Mappings. */
433	typedef struct PGMMAPPING *PPGMMAPPING;
434
435
436	/**
437	* Physical page access handler structure.
438	*
439	* This is used to keep track of physical address ranges
440	* which are being monitored in some kind of way.
441	*/
442	typedef struct PGMPHYSHANDLER
443	{
444	AVLROGCPHYSNODECORE Core;
445	/** Access type. */
446	PGMPHYSHANDLERTYPE enmType;
447	/** Number of pages to update. */
448	uint32_t cPages;
449	/** Pointer to R3 callback function. */
450	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
451	/** User argument for R3 handlers. */
452	R3PTRTYPE(void *) pvUserR3;
453	/** Pointer to R0 callback function. */
454	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
455	/** User argument for R0 handlers. */
456	R0PTRTYPE(void *) pvUserR0;
457	/** Pointer to RC callback function. */
458	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
459	/** User argument for RC handlers. */
460	RCPTRTYPE(void *) pvUserRC;
461	/** Description / Name. For easing debugging. */
462	R3PTRTYPE(const char *) pszDesc;
463	#ifdef VBOX_WITH_STATISTICS
464	/** Profiling of this handler. */
465	STAMPROFILE Stat;
466	#endif
467	} PGMPHYSHANDLER;
468	/** Pointer to a physical page access handler structure. */
469	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
470
471
472	/**
473	* Cache node for the physical addresses covered by a virtual handler.
474	*/
475	typedef struct PGMPHYS2VIRTHANDLER
476	{
477	/** Core node for the tree based on physical ranges. */
478	AVLROGCPHYSNODECORE Core;
479	/** Offset from this struct to the PGMVIRTHANDLER structure. */
480	int32_t offVirtHandler;
481	/** Offset of the next alias relative to this one.
482	* Bit 0 is used for indicating whether we're in the tree.
483	* Bit 1 is used for indicating that we're the head node.
484	*/
485	int32_t offNextAlias;
486	} PGMPHYS2VIRTHANDLER;
487	/** Pointer to a phys to virtual handler structure. */
488	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
489
490	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
491	* node is in the tree. */
492	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
493	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
494	* node is in the head of an alias chain.
495	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
496	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
497	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
498	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
499
500
501	/**
502	* Virtual page access handler structure.
503	*
504	* This is used to keep track of virtual address ranges
505	* which are being monitored in some kind of way.
506	*/
507	typedef struct PGMVIRTHANDLER
508	{
509	/** Core node for the tree based on virtual ranges. */
510	AVLROGCPTRNODECORE Core;
511	/** Size of the range (in bytes). */
512	RTGCPTR cb;
513	/** Number of cache pages. */
514	uint32_t cPages;
515	/** Access type. */
516	PGMVIRTHANDLERTYPE enmType;
517	/** Pointer to the RC callback function. */
518	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
519	#if HC_ARCH_BITS == 64
520	RTRCPTR padding;
521	#endif
522	/** Pointer to the R3 callback function for invalidation. */
523	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
524	/** Pointer to the R3 callback function. */
525	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
526	/** Description / Name. For easing debugging. */
527	R3PTRTYPE(const char *) pszDesc;
528	#ifdef VBOX_WITH_STATISTICS
529	/** Profiling of this handler. */
530	STAMPROFILE Stat;
531	#endif
532	/** Array of cached physical addresses for the monitored ranged. */
533	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
534	} PGMVIRTHANDLER;
535	/** Pointer to a virtual page access handler structure. */
536	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
537
538
539	/**
540	* Page type.
541	*
542	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
543	* @remarks This is used in the saved state, so changes to it requires bumping
544	* the saved state version.
545	* @todo So, convert to \#defines!
546	*/
547	typedef enum PGMPAGETYPE
548	{
549	/** The usual invalid zero entry. */
550	PGMPAGETYPE_INVALID = 0,
551	/** RAM page. (RWX) */
552	PGMPAGETYPE_RAM,
553	/** MMIO2 page. (RWX) */
554	PGMPAGETYPE_MMIO2,
555	/** MMIO2 page aliased over an MMIO page. (RWX)
556	* See PGMHandlerPhysicalPageAlias(). */
557	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
558	/** Shadowed ROM. (RWX) */
559	PGMPAGETYPE_ROM_SHADOW,
560	/** ROM page. (R-X) */
561	PGMPAGETYPE_ROM,
562	/** MMIO page. (---) */
563	PGMPAGETYPE_MMIO,
564	/** End of valid entries. */
565	PGMPAGETYPE_END
566	} PGMPAGETYPE;
567	AssertCompile(PGMPAGETYPE_END <= 7);
568
569	/** @name Page type predicates.
570	* @{ */
571	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
572	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
573	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
574	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
575	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
576	/** @} */
577
578
579	/**
580	* A Physical Guest Page tracking structure.
581	*
582	* The format of this structure is complicated because we have to fit a lot
583	* of information into as few bits as possible. The format is also subject
584	* to change (there is one comming up soon). Which means that for we'll be
585	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
586	* accesses to the structure.
587	*/
588	typedef struct PGMPAGE
589	{
590	/** The physical address and the Page ID. */
591	RTHCPHYS HCPhysAndPageID;
592	/** Combination of:
593	* - [0-7]: u2HandlerPhysStateY - the physical handler state
594	* (PGM_PAGE_HNDL_PHYS_STATE_*).
595	* - [8-9]: u2HandlerVirtStateY - the virtual handler state
596	* (PGM_PAGE_HNDL_VIRT_STATE_*).
597	* - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
598	* - [15]: fWrittenToY - flag indicating that a write monitored page was
599	* written to when set.
600	* - [10-13]: 4 unused bits.
601	* @remarks Warning! All accesses to the bits are hardcoded.
602	*
603	* @todo Change this to a union with both bitfields, u8 and u accessors.
604	* That'll help deal with some of the hardcoded accesses.
605	*
606	* @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
607	* will make it possible to turn some of the 16-bit accesses into
608	* 32-bit ones, which may be efficient (stalls).
609	*/
610	RTUINT16U u16MiscY;
611	/** The page state.
612	* Only 3 bits are really needed for this. */
613	uint16_t uStateY : 3;
614	/** The page type (PGMPAGETYPE).
615	* Only 3 bits are really needed for this. */
616	uint16_t uTypeY : 3;
617	/** PTE index for usage tracking (page pool). */
618	uint16_t uPteIdx : 10;
619	/** Usage tracking (page pool). */
620	uint16_t u16TrackingY;
621	/** The number of read locks on this page. */
622	uint8_t cReadLocksY;
623	/** The number of write locks on this page. */
624	uint8_t cWriteLocksY;
625	} PGMPAGE;
626	AssertCompileSize(PGMPAGE, 16);
627	/** Pointer to a physical guest page. */
628	typedef PGMPAGE *PPGMPAGE;
629	/** Pointer to a const physical guest page. */
630	typedef const PGMPAGE *PCPGMPAGE;
631	/** Pointer to a physical guest page pointer. */
632	typedef PPGMPAGE *PPPGMPAGE;
633
634
635	/**
636	* Clears the page structure.
637	* @param pPage Pointer to the physical guest page tracking structure.
638	*/
639	#define PGM_PAGE_CLEAR(pPage) \
640	do { \
641	(pPage)->HCPhysAndPageID = 0; \
642	(pPage)->uStateY = 0; \
643	(pPage)->uTypeY = 0; \
644	(pPage)->uPteIdx = 0; \
645	(pPage)->u16MiscY.u = 0; \
646	(pPage)->u16TrackingY = 0; \
647	(pPage)->cReadLocksY = 0; \
648	(pPage)->cWriteLocksY = 0; \
649	} while (0)
650
651	/**
652	* Initializes the page structure.
653	* @param pPage Pointer to the physical guest page tracking structure.
654	*/
655	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
656	do { \
657	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
658	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
659	(pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) \| ((_idPage) & UINT32_C(0x0fffffff)); \
660	(pPage)->uStateY = (_uState); \
661	(pPage)->uTypeY = (_uType); \
662	(pPage)->uPteIdx = 0; \
663	(pPage)->u16MiscY.u = 0; \
664	(pPage)->u16TrackingY = 0; \
665	(pPage)->cReadLocksY = 0; \
666	(pPage)->cWriteLocksY = 0; \
667	} while (0)
668
669	/**
670	* Initializes the page structure of a ZERO page.
671	* @param pPage Pointer to the physical guest page tracking structure.
672	* @param pVM The VM handle (for getting the zero page address).
673	* @param uType The page type (PGMPAGETYPE).
674	*/
675	#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
676	PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
677
678
679	/** @name The Page state, PGMPAGE::uStateY.
680	* @{ */
681	/** The zero page.
682	* This is a per-VM page that's never ever mapped writable. */
683	#define PGM_PAGE_STATE_ZERO 0
684	/** A allocated page.
685	* This is a per-VM page allocated from the page pool (or wherever
686	* we get MMIO2 pages from if the type is MMIO2).
687	*/
688	#define PGM_PAGE_STATE_ALLOCATED 1
689	/** A allocated page that's being monitored for writes.
690	* The shadow page table mappings are read-only. When a write occurs, the
691	* fWrittenTo member is set, the page remapped as read-write and the state
692	* moved back to allocated. */
693	#define PGM_PAGE_STATE_WRITE_MONITORED 2
694	/** The page is shared, aka. copy-on-write.
695	* This is a page that's shared with other VMs. */
696	#define PGM_PAGE_STATE_SHARED 3
697	/** The page is ballooned, so no longer available for this VM. */
698	#define PGM_PAGE_STATE_BALLOONED 4
699	/** @} */
700
701
702	/**
703	* Gets the page state.
704	* @returns page state (PGM_PAGE_STATE_*).
705	* @param pPage Pointer to the physical guest page tracking structure.
706	*/
707	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
708
709	/**
710	* Sets the page state.
711	* @param pPage Pointer to the physical guest page tracking structure.
712	* @param _uState The new page state.
713	*/
714	#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
715
716
717	/**
718	* Gets the host physical address of the guest page.
719	* @returns host physical address (RTHCPHYS).
720	* @param pPage Pointer to the physical guest page tracking structure.
721	*/
722	#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
723
724	/**
725	* Sets the host physical address of the guest page.
726	* @param pPage Pointer to the physical guest page tracking structure.
727	* @param _HCPhys The new host physical address.
728	*/
729	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
730	do { \
731	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
732	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
733	(pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
734	\| (SetHCPhysTmp << (28-12)); \
735	} while (0)
736
737	/**
738	* Get the Page ID.
739	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
740	* @param pPage Pointer to the physical guest page tracking structure.
741	*/
742	#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
743
744	/**
745	* Sets the Page ID.
746	* @param pPage Pointer to the physical guest page tracking structure.
747	*/
748	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
749	do { \
750	(pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
751	\| ((_idPage) & UINT32_C(0x0fffffff)); \
752	} while (0)
753
754	/**
755	* Get the Chunk ID.
756	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
757	* @param pPage Pointer to the physical guest page tracking structure.
758	*/
759	#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
760
761	/**
762	* Get the index of the page within the allocation chunk.
763	* @returns The page index.
764	* @param pPage Pointer to the physical guest page tracking structure.
765	*/
766	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
767
768	/**
769	* Gets the page type.
770	* @returns The page type.
771	* @param pPage Pointer to the physical guest page tracking structure.
772	*/
773	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
774
775	/**
776	* Sets the page type.
777	* @param pPage Pointer to the physical guest page tracking structure.
778	* @param _enmType The new page type (PGMPAGETYPE).
779	*/
780	#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
781
782	/**
783	* Gets the page table index
784	* @returns The page table index.
785	* @param pPage Pointer to the physical guest page tracking structure.
786	*/
787	#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
788
789	/**
790	* Sets the page table index
791	* @param pPage Pointer to the physical guest page tracking structure.
792	* @param iPte New page table index.
793	*/
794	#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
795
796	/**
797	* Checks if the page is marked for MMIO.
798	* @returns true/false.
799	* @param pPage Pointer to the physical guest page tracking structure.
800	*/
801	#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
802
803	/**
804	* Checks if the page is backed by the ZERO page.
805	* @returns true/false.
806	* @param pPage Pointer to the physical guest page tracking structure.
807	*/
808	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
809
810	/**
811	* Checks if the page is backed by a SHARED page.
812	* @returns true/false.
813	* @param pPage Pointer to the physical guest page tracking structure.
814	*/
815	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
816
817	/**
818	* Checks if the page is ballooned.
819	* @returns true/false.
820	* @param pPage Pointer to the physical guest page tracking structure.
821	*/
822	#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
823
824	/**
825	* Marks the page as written to (for GMM change monitoring).
826	* @param pPage Pointer to the physical guest page tracking structure.
827	*/
828	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] \|= UINT8_C(0x80); } while (0)
829
830	/**
831	* Clears the written-to indicator.
832	* @param pPage Pointer to the physical guest page tracking structure.
833	*/
834	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
835
836	/**
837	* Checks if the page was marked as written-to.
838	* @returns true/false.
839	* @param pPage Pointer to the physical guest page tracking structure.
840	*/
841	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
842
843	/** @name PT usage values (PGMPAGE::u2PDEType).
844	*
845	* @{ */
846	/** Either as a PT or PDE. */
847	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
848	/** Must use a page table to map the range. */
849	#define PGM_PAGE_PDE_TYPE_PT 1
850	/** Can use a page directory entry to map the continous range. */
851	#define PGM_PAGE_PDE_TYPE_PDE 2
852	/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
853	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
854	/** @} */
855
856	/**
857	* Set the PDE type of the page
858	* @param pPage Pointer to the physical guest page tracking structure.
859	* @param uType PGM_PAGE_PDE_TYPE_*
860	*/
861	#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
862	do { \
863	(pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
864	\| (((uType) & UINT8_C(0x03)) << 5); \
865	} while (0)
866
867	/**
868	* Checks if the page was marked being part of a large page
869	* @returns true/false.
870	* @param pPage Pointer to the physical guest page tracking structure.
871	*/
872	#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
873
874	/** Enabled optimized access handler tests.
875	* These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
876	* layout. When enabled, the compiler should normally generate more compact
877	* code.
878	*/
879	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
880
881	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
882	*
883	* @remarks The values are assigned in order of priority, so we can calculate
884	* the correct state for a page with different handlers installed.
885	* @{ */
886	/** No handler installed. */
887	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
888	/** Monitoring is temporarily disabled. */
889	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
890	/** Write access is monitored. */
891	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
892	/** All access is monitored. */
893	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
894	/** @} */
895
896	/**
897	* Gets the physical access handler state of a page.
898	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
899	* @param pPage Pointer to the physical guest page tracking structure.
900	*/
901	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
902	( (pPage)->u16MiscY.au8[0] )
903
904	/**
905	* Sets the physical access handler state of a page.
906	* @param pPage Pointer to the physical guest page tracking structure.
907	* @param _uState The new state value.
908	*/
909	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
910	do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
911
912	/**
913	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
914	* @returns true/false
915	* @param pPage Pointer to the physical guest page tracking structure.
916	*/
917	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
918	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
919
920	/**
921	* Checks if the page has any active physical access handlers.
922	* @returns true/false
923	* @param pPage Pointer to the physical guest page tracking structure.
924	*/
925	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
926	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
927
928
929	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
930	*
931	* @remarks The values are assigned in order of priority, so we can calculate
932	* the correct state for a page with different handlers installed.
933	* @{ */
934	/** No handler installed. */
935	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
936	/* 1 is reserved so the lineup is identical with the physical ones. */
937	/** Write access is monitored. */
938	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
939	/** All access is monitored. */
940	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
941	/** @} */
942
943	/**
944	* Gets the virtual access handler state of a page.
945	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
946	* @param pPage Pointer to the physical guest page tracking structure.
947	*/
948	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
949
950	/**
951	* Sets the virtual access handler state of a page.
952	* @param pPage Pointer to the physical guest page tracking structure.
953	* @param _uState The new state value.
954	*/
955	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
956	do { \
957	(pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
958	\| ((_uState) & UINT8_C(0x03)); \
959	} while (0)
960
961	/**
962	* Checks if the page has any virtual access handlers.
963	* @returns true/false
964	* @param pPage Pointer to the physical guest page tracking structure.
965	*/
966	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
967	( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
968
969	/**
970	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
971	* virtual handlers.
972	* @returns true/false
973	* @param pPage Pointer to the physical guest page tracking structure.
974	*/
975	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
976	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
977
978
979	/**
980	* Checks if the page has any access handlers, including temporarily disabled ones.
981	* @returns true/false
982	* @param pPage Pointer to the physical guest page tracking structure.
983	*/
984	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
985	# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
986	( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
987	#else
988	# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
989	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
990	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
991	#endif
992
993	/**
994	* Checks if the page has any active access handlers.
995	* @returns true/false
996	* @param pPage Pointer to the physical guest page tracking structure.
997	*/
998	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
999	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1000	( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1001	#else
1002	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1003	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1004	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1005	#endif
1006
1007	/**
1008	* Checks if the page has any active access handlers catching all accesses.
1009	* @returns true/false
1010	* @param pPage Pointer to the physical guest page tracking structure.
1011	*/
1012	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1013	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1014	( ( ((pPage)->u16MiscY.au8[0] \| (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1015	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1016	#else
1017	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1018	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1019	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1020	#endif
1021
1022
1023	/** @def PGM_PAGE_GET_TRACKING
1024	* Gets the packed shadow page pool tracking data associated with a guest page.
1025	* @returns uint16_t containing the data.
1026	* @param pPage Pointer to the physical guest page tracking structure.
1027	*/
1028	#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1029
1030	/** @def PGM_PAGE_SET_TRACKING
1031	* Sets the packed shadow page pool tracking data associated with a guest page.
1032	* @param pPage Pointer to the physical guest page tracking structure.
1033	* @param u16TrackingData The tracking data to store.
1034	*/
1035	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1036	do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1037
1038	/** @def PGM_PAGE_GET_TD_CREFS
1039	* Gets the @a cRefs tracking data member.
1040	* @returns cRefs.
1041	* @param pPage Pointer to the physical guest page tracking structure.
1042	*/
1043	#define PGM_PAGE_GET_TD_CREFS(pPage) \
1044	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1045
1046	/** @def PGM_PAGE_GET_TD_IDX
1047	* Gets the @a idx tracking data member.
1048	* @returns idx.
1049	* @param pPage Pointer to the physical guest page tracking structure.
1050	*/
1051	#define PGM_PAGE_GET_TD_IDX(pPage) \
1052	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1053
1054
1055	/** Max number of locks on a page. */
1056	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1057
1058	/** Get the read lock count.
1059	* @returns count.
1060	* @param pPage Pointer to the physical guest page tracking structure.
1061	*/
1062	#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1063
1064	/** Get the write lock count.
1065	* @returns count.
1066	* @param pPage Pointer to the physical guest page tracking structure.
1067	*/
1068	#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1069
1070	/** Decrement the read lock counter.
1071	* @param pPage Pointer to the physical guest page tracking structure.
1072	*/
1073	#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1074
1075	/** Decrement the write lock counter.
1076	* @param pPage Pointer to the physical guest page tracking structure.
1077	*/
1078	#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1079
1080	/** Increment the read lock counter.
1081	* @param pPage Pointer to the physical guest page tracking structure.
1082	*/
1083	#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1084
1085	/** Increment the write lock counter.
1086	* @param pPage Pointer to the physical guest page tracking structure.
1087	*/
1088	#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1089
1090
1091	#if 0
1092	/** Enables sanity checking of write monitoring using CRC-32. */
1093	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1094	#endif
1095
1096	/**
1097	* Per page live save tracking data.
1098	*/
1099	typedef struct PGMLIVESAVERAMPAGE
1100	{
1101	/** Number of times it has been dirtied. */
1102	uint32_t cDirtied : 24;
1103	/** Whether it is currently dirty. */
1104	uint32_t fDirty : 1;
1105	/** Ignore the page.
1106	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1107	* deal with these after pausing the VM and DevPCI have said it bit about
1108	* remappings. */
1109	uint32_t fIgnore : 1;
1110	/** Was a ZERO page last time around. */
1111	uint32_t fZero : 1;
1112	/** Was a SHARED page last time around. */
1113	uint32_t fShared : 1;
1114	/** Whether the page is/was write monitored in a previous pass. */
1115	uint32_t fWriteMonitored : 1;
1116	/** Whether the page is/was write monitored earlier in this pass. */
1117	uint32_t fWriteMonitoredJustNow : 1;
1118	/** Bits reserved for future use. */
1119	uint32_t u2Reserved : 2;
1120	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1121	/** CRC-32 for the page. This is for internal consistency checks. */
1122	uint32_t u32Crc;
1123	#endif
1124	} PGMLIVESAVERAMPAGE;
1125	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1126	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1127	#else
1128	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1129	#endif
1130	/** Pointer to the per page live save tracking data. */
1131	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1132
1133	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1134	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1135
1136
1137	/**
1138	* Ram range for GC Phys to HC Phys conversion.
1139	*
1140	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1141	* conversions too, but we'll let MM handle that for now.
1142	*
1143	* This structure is used by linked lists in both GC and HC.
1144	*/
1145	typedef struct PGMRAMRANGE
1146	{
1147	/** Start of the range. Page aligned. */
1148	RTGCPHYS GCPhys;
1149	/** Size of the range. (Page aligned of course). */
1150	RTGCPHYS cb;
1151	/** Pointer to the next RAM range - for R3. */
1152	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1153	/** Pointer to the next RAM range - for R0. */
1154	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1155	/** Pointer to the next RAM range - for RC. */
1156	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1157	/** PGM_RAM_RANGE_FLAGS_* flags. */
1158	uint32_t fFlags;
1159	/** Last address in the range (inclusive). Page aligned (-1). */
1160	RTGCPHYS GCPhysLast;
1161	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1162	R3PTRTYPE(void *) pvR3;
1163	/** Live save per page tracking data. */
1164	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1165	/** The range description. */
1166	R3PTRTYPE(const char *) pszDesc;
1167	/** Pointer to self - R0 pointer. */
1168	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1169	/** Pointer to self - RC pointer. */
1170	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1171	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1172	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1173	/** Array of physical guest page tracking structures. */
1174	PGMPAGE aPages[1];
1175	} PGMRAMRANGE;
1176	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1177	typedef PGMRAMRANGE *PPGMRAMRANGE;
1178
1179	/** @name PGMRAMRANGE::fFlags
1180	* @{ */
1181	/** The RAM range is floating around as an independent guest mapping. */
1182	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1183	/** Ad hoc RAM range for an ROM mapping. */
1184	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1185	/** Ad hoc RAM range for an MMIO mapping. */
1186	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1187	/** Ad hoc RAM range for an MMIO2 mapping. */
1188	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1189	/** @} */
1190
1191	/** Tests if a RAM range is an ad hoc one or not.
1192	* @returns true/false.
1193	* @param pRam The RAM range.
1194	*/
1195	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1196	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1197
1198
1199	/**
1200	* Per page tracking structure for ROM image.
1201	*
1202	* A ROM image may have a shadow page, in which case we may have two pages
1203	* backing it. This structure contains the PGMPAGE for both while
1204	* PGMRAMRANGE have a copy of the active one. It is important that these
1205	* aren't out of sync in any regard other than page pool tracking data.
1206	*/
1207	typedef struct PGMROMPAGE
1208	{
1209	/** The page structure for the virgin ROM page. */
1210	PGMPAGE Virgin;
1211	/** The page structure for the shadow RAM page. */
1212	PGMPAGE Shadow;
1213	/** The current protection setting. */
1214	PGMROMPROT enmProt;
1215	/** Live save status information. Makes use of unused alignment space. */
1216	struct
1217	{
1218	/** The previous protection value. */
1219	uint8_t u8Prot;
1220	/** Written to flag set by the handler. */
1221	bool fWrittenTo;
1222	/** Whether the shadow page is dirty or not. */
1223	bool fDirty;
1224	/** Whether it was dirtied in the recently. */
1225	bool fDirtiedRecently;
1226	} LiveSave;
1227	} PGMROMPAGE;
1228	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1229	/** Pointer to a ROM page tracking structure. */
1230	typedef PGMROMPAGE *PPGMROMPAGE;
1231
1232
1233	/**
1234	* A registered ROM image.
1235	*
1236	* This is needed to keep track of ROM image since they generally intrude
1237	* into a PGMRAMRANGE. It also keeps track of additional info like the
1238	* two page sets (read-only virgin and read-write shadow), the current
1239	* state of each page.
1240	*
1241	* Because access handlers cannot easily be executed in a different
1242	* context, the ROM ranges needs to be accessible and in all contexts.
1243	*/
1244	typedef struct PGMROMRANGE
1245	{
1246	/** Pointer to the next range - R3. */
1247	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1248	/** Pointer to the next range - R0. */
1249	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1250	/** Pointer to the next range - RC. */
1251	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1252	/** Pointer alignment */
1253	RTRCPTR RCPtrAlignment;
1254	/** Address of the range. */
1255	RTGCPHYS GCPhys;
1256	/** Address of the last byte in the range. */
1257	RTGCPHYS GCPhysLast;
1258	/** Size of the range. */
1259	RTGCPHYS cb;
1260	/** The flags (PGMPHYS_ROM_FLAGS_). /
1261	uint32_t fFlags;
1262	/** The saved state range ID. */
1263	uint8_t idSavedState;
1264	/** Alignment padding. */
1265	uint8_t au8Alignment[3];
1266	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1267	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1268	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1269	* This is used for strictness checks. */
1270	R3PTRTYPE(const void *) pvOriginal;
1271	/** The ROM description. */
1272	R3PTRTYPE(const char *) pszDesc;
1273	/** The per page tracking structures. */
1274	PGMROMPAGE aPages[1];
1275	} PGMROMRANGE;
1276	/** Pointer to a ROM range. */
1277	typedef PGMROMRANGE *PPGMROMRANGE;
1278
1279
1280	/**
1281	* Live save per page data for an MMIO2 page.
1282	*
1283	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1284	* of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1285	* CRC-32 for detecting changes as well as special handling of zero pages. This
1286	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1287	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1288	* because of speed (2.5x and 6x slower).)
1289	*
1290	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1291	* save but normally is disabled. Since we can write monitore guest
1292	* accesses on our own, we only need this for host accesses. Shouldn't be
1293	* too difficult for DevVGA, VMMDev might be doable, the planned
1294	* networking fun will be fun since it involves ring-0.
1295	*/
1296	typedef struct PGMLIVESAVEMMIO2PAGE
1297	{
1298	/** Set if the page is considered dirty. */
1299	bool fDirty;
1300	/** The number of scans this page has remained unchanged for.
1301	* Only updated for dirty pages. */
1302	uint8_t cUnchangedScans;
1303	/** Whether this page was zero at the last scan. */
1304	bool fZero;
1305	/** Alignment padding. */
1306	bool fReserved;
1307	/** CRC-32 for the first half of the page.
1308	* This is used together with u32CrcH2 to quickly detect changes in the page
1309	* during the non-final passes. */
1310	uint32_t u32CrcH1;
1311	/** CRC-32 for the second half of the page. */
1312	uint32_t u32CrcH2;
1313	/** SHA-1 for the saved page.
1314	* This is used in the final pass to skip pages without changes. */
1315	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1316	} PGMLIVESAVEMMIO2PAGE;
1317	/** Pointer to a live save status data for an MMIO2 page. */
1318	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1319
1320	/**
1321	* A registered MMIO2 (= Device RAM) range.
1322	*
1323	* There are a few reason why we need to keep track of these
1324	* registrations. One of them is the deregistration & cleanup stuff,
1325	* while another is that the PGMRAMRANGE associated with such a region may
1326	* have to be removed from the ram range list.
1327	*
1328	* Overlapping with a RAM range has to be 100% or none at all. The pages
1329	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1330	* will be raised if a partial overlap or an overlap of ROM pages is
1331	* encountered. On an overlap we will free all the existing RAM pages and
1332	* put in the ram range pages instead.
1333	*/
1334	typedef struct PGMMMIO2RANGE
1335	{
1336	/** The owner of the range. (a device) */
1337	PPDMDEVINSR3 pDevInsR3;
1338	/** Pointer to the ring-3 mapping of the allocation. */
1339	RTR3PTR pvR3;
1340	/** Pointer to the next range - R3. */
1341	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1342	/** Whether it's mapped or not. */
1343	bool fMapped;
1344	/** Whether it's overlapping or not. */
1345	bool fOverlapping;
1346	/** The PCI region number.
1347	* @remarks This ASSUMES that nobody will ever really need to have multiple
1348	* PCI devices with matching MMIO region numbers on a single device. */
1349	uint8_t iRegion;
1350	/** The saved state range ID. */
1351	uint8_t idSavedState;
1352	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1353	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1354	/** Live save per page tracking data. */
1355	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1356	/** The associated RAM range. */
1357	PGMRAMRANGE RamRange;
1358	} PGMMMIO2RANGE;
1359	/** Pointer to a MMIO2 range. */
1360	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1361
1362
1363
1364
1365	/**
1366	* PGMPhysRead/Write cache entry
1367	*/
1368	typedef struct PGMPHYSCACHEENTRY
1369	{
1370	/** R3 pointer to physical page. */
1371	R3PTRTYPE(uint8_t *) pbR3;
1372	/** GC Physical address for cache entry */
1373	RTGCPHYS GCPhys;
1374	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1375	RTGCPHYS u32Padding0; /*< alignment padding. /
1376	#endif
1377	} PGMPHYSCACHEENTRY;
1378
1379	/**
1380	* PGMPhysRead/Write cache to reduce REM memory access overhead
1381	*/
1382	typedef struct PGMPHYSCACHE
1383	{
1384	/** Bitmap of valid cache entries */
1385	uint64_t aEntries;
1386	/** Cache entries */
1387	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1388	} PGMPHYSCACHE;
1389
1390
1391	/** Pointer to an allocation chunk ring-3 mapping. */
1392	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1393	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1394	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1395
1396	/**
1397	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1398	*
1399	* The primary tree (Core) uses the chunk id as key.
1400	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1401	*/
1402	typedef struct PGMCHUNKR3MAP
1403	{
1404	/** The key is the chunk id. */
1405	AVLU32NODECORE Core;
1406	/** The key is the ageing sequence number. */
1407	AVLLU32NODECORE AgeCore;
1408	/** The current age thingy. */
1409	uint32_t iAge;
1410	/** The current reference count. */
1411	uint32_t volatile cRefs;
1412	/** The current permanent reference count. */
1413	uint32_t volatile cPermRefs;
1414	/** The mapping address. */
1415	void *pv;
1416	} PGMCHUNKR3MAP;
1417
1418	/**
1419	* Allocation chunk ring-3 mapping TLB entry.
1420	*/
1421	typedef struct PGMCHUNKR3MAPTLBE
1422	{
1423	/** The chunk id. */
1424	uint32_t volatile idChunk;
1425	#if HC_ARCH_BITS == 64
1426	uint32_t u32Padding; /*< alignment padding. /
1427	#endif
1428	/** The chunk map. */
1429	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1430	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1431	#else
1432	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1433	#endif
1434	} PGMCHUNKR3MAPTLBE;
1435	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1436	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1437
1438	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1439	* @remark Must be a power of two value. */
1440	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1441
1442	/**
1443	* Allocation chunk ring-3 mapping TLB.
1444	*
1445	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1446	* At first glance this might look kinda odd since AVL trees are
1447	* supposed to give the most optimial lookup times of all trees
1448	* due to their balancing. However, take a tree with 1023 nodes
1449	* in it, that's 10 levels, meaning that most searches has to go
1450	* down 9 levels before they find what they want. This isn't fast
1451	* compared to a TLB hit. There is the factor of cache misses,
1452	* and of course the problem with trees and branch prediction.
1453	* This is why we use TLBs in front of most of the trees.
1454	*
1455	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1456	* difficult when we switch to the new inlined AVL trees (from kStuff).
1457	*/
1458	typedef struct PGMCHUNKR3MAPTLB
1459	{
1460	/** The TLB entries. */
1461	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1462	} PGMCHUNKR3MAPTLB;
1463
1464	/**
1465	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1466	* @returns Chunk TLB index.
1467	* @param idChunk The Chunk ID.
1468	*/
1469	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1470
1471
1472	/**
1473	* Ring-3 guest page mapping TLB entry.
1474	* @remarks used in ring-0 as well at the moment.
1475	*/
1476	typedef struct PGMPAGER3MAPTLBE
1477	{
1478	/** Address of the page. */
1479	RTGCPHYS volatile GCPhys;
1480	/** The guest page. */
1481	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1482	R3PTRTYPE(PPGMPAGE) volatile pPage;
1483	#else
1484	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1485	#endif
1486	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1487	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1488	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1489	#else
1490	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1491	#endif
1492	/** The address */
1493	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1494	R3PTRTYPE(void *) volatile pv;
1495	#else
1496	R3R0PTRTYPE(void *) volatile pv;
1497	#endif
1498	#if HC_ARCH_BITS == 32
1499	uint32_t u32Padding; /*< alignment padding. /
1500	#endif
1501	} PGMPAGER3MAPTLBE;
1502	/** Pointer to an entry in the HC physical TLB. */
1503	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1504
1505
1506	/** The number of entries in the ring-3 guest page mapping TLB.
1507	* @remarks The value must be a power of two. */
1508	#define PGM_PAGER3MAPTLB_ENTRIES 256
1509
1510	/**
1511	* Ring-3 guest page mapping TLB.
1512	* @remarks used in ring-0 as well at the moment.
1513	*/
1514	typedef struct PGMPAGER3MAPTLB
1515	{
1516	/** The TLB entries. */
1517	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1518	} PGMPAGER3MAPTLB;
1519	/** Pointer to the ring-3 guest page mapping TLB. */
1520	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1521
1522	/**
1523	* Calculates the index of the TLB entry for the specified guest page.
1524	* @returns Physical TLB index.
1525	* @param GCPhys The guest physical address.
1526	*/
1527	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1528
1529
1530	/**
1531	* Mapping cache usage set entry.
1532	*
1533	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1534	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1535	* cache. If it's extended to include ring-3, well, then something will
1536	* have be changed here...
1537	*/
1538	typedef struct PGMMAPSETENTRY
1539	{
1540	/** The mapping cache index. */
1541	uint16_t iPage;
1542	/** The number of references.
1543	* The max is UINT16_MAX - 1. */
1544	uint16_t cRefs;
1545	#if HC_ARCH_BITS == 64
1546	uint32_t alignment;
1547	#endif
1548	/** Pointer to the page. */
1549	RTR0PTR pvPage;
1550	/** The physical address for this entry. */
1551	RTHCPHYS HCPhys;
1552	} PGMMAPSETENTRY;
1553	/** Pointer to a mapping cache usage set entry. */
1554	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1555
1556	/**
1557	* Mapping cache usage set.
1558	*
1559	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1560	* done during exits / traps. The set is
1561	*/
1562	typedef struct PGMMAPSET
1563	{
1564	/** The number of occupied entries.
1565	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1566	* dynamic mappings. */
1567	uint32_t cEntries;
1568	/** The start of the current subset.
1569	* This is UINT32_MAX if no subset is currently open. */
1570	uint32_t iSubset;
1571	/** The index of the current CPU, only valid if the set is open. */
1572	int32_t iCpu;
1573	uint32_t alignment;
1574	/** The entries. */
1575	PGMMAPSETENTRY aEntries[64];
1576	/** HCPhys -> iEntry fast lookup table.
1577	* Use PGMMAPSET_HASH for hashing.
1578	* The entries may or may not be valid, check against cEntries. */
1579	uint8_t aiHashTable[128];
1580	} PGMMAPSET;
1581	AssertCompileSizeAlignment(PGMMAPSET, 8);
1582	/** Pointer to the mapping cache set. */
1583	typedef PGMMAPSET *PPGMMAPSET;
1584
1585	/** PGMMAPSET::cEntries value for a closed set. */
1586	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1587
1588	/** Hash function for aiHashTable. */
1589	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1590
1591	/** The max fill size (strict builds). */
1592	#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1593
1594
1595	/** @name Context neutrual page mapper TLB.
1596	*
1597	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1598	* code is writting in a kind of context neutrual way. Time will show whether
1599	* this actually makes sense or not...
1600	*
1601	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1602	* context ends up using a global mapping cache on some platforms
1603	* (darwin).
1604	*
1605	* @{ */
1606	/** @typedef PPGMPAGEMAPTLB
1607	* The page mapper TLB pointer type for the current context. */
1608	/** @typedef PPGMPAGEMAPTLB
1609	* The page mapper TLB entry pointer type for the current context. */
1610	/** @typedef PPGMPAGEMAPTLB
1611	* The page mapper TLB entry pointer pointer type for the current context. */
1612	/** @def PGM_PAGEMAPTLB_ENTRIES
1613	* The number of TLB entries in the page mapper TLB for the current context. */
1614	/** @def PGM_PAGEMAPTLB_IDX
1615	* Calculate the TLB index for a guest physical address.
1616	* @returns The TLB index.
1617	* @param GCPhys The guest physical address. */
1618	/** @typedef PPGMPAGEMAP
1619	* Pointer to a page mapper unit for current context. */
1620	/** @typedef PPPGMPAGEMAP
1621	* Pointer to a page mapper unit pointer for current context. */
1622	#ifdef IN_RC
1623	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1624	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1625	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1626	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1627	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1628	typedef void * PPGMPAGEMAP;
1629	typedef void ** PPPGMPAGEMAP;
1630	//#elif IN_RING0
1631	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1632	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1633	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1634	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1635	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1636	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1637	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1638	#else
1639	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1640	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1641	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1642	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1643	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1644	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1645	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1646	#endif
1647	/** @} */
1648
1649
1650	/** @name PGM Pool Indexes.
1651	* Aka. the unique shadow page identifier.
1652	* @{ */
1653	/** NIL page pool IDX. */
1654	#define NIL_PGMPOOL_IDX 0
1655	/** The first normal index. */
1656	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1657	/** Page directory (32-bit root). */
1658	#define PGMPOOL_IDX_PD 1
1659	/** Page Directory Pointer Table (PAE root). */
1660	#define PGMPOOL_IDX_PDPT 2
1661	/** AMD64 CR3 level index.*/
1662	#define PGMPOOL_IDX_AMD64_CR3 3
1663	/** Nested paging root.*/
1664	#define PGMPOOL_IDX_NESTED_ROOT 4
1665	/** The first normal index. */
1666	#define PGMPOOL_IDX_FIRST 5
1667	/** The last valid index. (inclusive, 14 bits) */
1668	#define PGMPOOL_IDX_LAST 0x3fff
1669	/** @} */
1670
1671	/** The NIL index for the parent chain. */
1672	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1673	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1674
1675	/**
1676	* Node in the chain linking a shadowed page to it's parent (user).
1677	*/
1678	#pragma pack(1)
1679	typedef struct PGMPOOLUSER
1680	{
1681	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1682	uint16_t iNext;
1683	/** The user page index. */
1684	uint16_t iUser;
1685	/** Index into the user table. */
1686	uint32_t iUserTable;
1687	} PGMPOOLUSER, *PPGMPOOLUSER;
1688	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1689	#pragma pack()
1690
1691
1692	/** The NIL index for the phys ext chain. */
1693	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1694	/** The NIL pte index for a phys ext chain slot. */
1695	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1696
1697	/**
1698	* Node in the chain of physical cross reference extents.
1699	* @todo Calling this an 'extent' is not quite right, find a better name.
1700	* @todo find out the optimal size of the aidx array
1701	*/
1702	#pragma pack(1)
1703	typedef struct PGMPOOLPHYSEXT
1704	{
1705	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1706	uint16_t iNext;
1707	/** Alignment. */
1708	uint16_t u16Align;
1709	/** The user page index. */
1710	uint16_t aidx[3];
1711	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1712	uint16_t apte[3];
1713	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1714	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1715	#pragma pack()
1716
1717
1718	/**
1719	* The kind of page that's being shadowed.
1720	*/
1721	typedef enum PGMPOOLKIND
1722	{
1723	/** The virtual invalid 0 entry. */
1724	PGMPOOLKIND_INVALID = 0,
1725	/** The entry is free (=unused). */
1726	PGMPOOLKIND_FREE,
1727
1728	/** Shw: 32-bit page table; Gst: no paging */
1729	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1730	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1731	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1732	/** Shw: 32-bit page table; Gst: 4MB page. */
1733	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1734	/** Shw: PAE page table; Gst: no paging */
1735	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1736	/** Shw: PAE page table; Gst: 32-bit page table. */
1737	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1738	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1739	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1740	/** Shw: PAE page table; Gst: PAE page table. */
1741	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1742	/** Shw: PAE page table; Gst: 2MB page. */
1743	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1744
1745	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1746	PGMPOOLKIND_32BIT_PD,
1747	/** Shw: 32-bit page directory. Gst: no paging. */
1748	PGMPOOLKIND_32BIT_PD_PHYS,
1749	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1750	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1751	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1752	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1753	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1754	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1755	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1756	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1757	/** Shw: PAE page directory; Gst: PAE page directory. */
1758	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1759	/** Shw: PAE page directory; Gst: no paging. */
1760	PGMPOOLKIND_PAE_PD_PHYS,
1761
1762	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1763	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1764	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1765	PGMPOOLKIND_PAE_PDPT,
1766	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1767	PGMPOOLKIND_PAE_PDPT_PHYS,
1768
1769	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1770	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1771	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1772	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1773	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1774	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1775	/** Shw: 64-bit page directory table; Gst: no paging */
1776	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1777
1778	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1779	PGMPOOLKIND_64BIT_PML4,
1780
1781	/** Shw: EPT page directory pointer table; Gst: no paging */
1782	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1783	/** Shw: EPT page directory table; Gst: no paging */
1784	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1785	/** Shw: EPT page table; Gst: no paging */
1786	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1787
1788	/** Shw: Root Nested paging table. */
1789	PGMPOOLKIND_ROOT_NESTED,
1790
1791	/** The last valid entry. */
1792	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1793	} PGMPOOLKIND;
1794
1795	/**
1796	* The access attributes of the page; only applies to big pages.
1797	*/
1798	typedef enum
1799	{
1800	PGMPOOLACCESS_DONTCARE = 0,
1801	PGMPOOLACCESS_USER_RW,
1802	PGMPOOLACCESS_USER_R,
1803	PGMPOOLACCESS_USER_RW_NX,
1804	PGMPOOLACCESS_USER_R_NX,
1805	PGMPOOLACCESS_SUPERVISOR_RW,
1806	PGMPOOLACCESS_SUPERVISOR_R,
1807	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1808	PGMPOOLACCESS_SUPERVISOR_R_NX
1809	} PGMPOOLACCESS;
1810
1811	/**
1812	* The tracking data for a page in the pool.
1813	*/
1814	typedef struct PGMPOOLPAGE
1815	{
1816	/** AVL node code with the (R3) physical address of this page. */
1817	AVLOHCPHYSNODECORE Core;
1818	/** Pointer to the R3 mapping of the page. */
1819	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1820	R3PTRTYPE(void *) pvPageR3;
1821	#else
1822	R3R0PTRTYPE(void *) pvPageR3;
1823	#endif
1824	/** The guest physical address. */
1825	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1826	uint32_t Alignment0;
1827	#endif
1828	RTGCPHYS GCPhys;
1829
1830	/** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1831	RTGCPTR pvLastAccessHandlerRip;
1832	RTGCPTR pvLastAccessHandlerFault;
1833	uint64_t cLastAccessHandlerCount;
1834
1835	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1836	uint8_t enmKind;
1837	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1838	uint8_t enmAccess;
1839	/** The index of this page. */
1840	uint16_t idx;
1841	/** The next entry in the list this page currently resides in.
1842	* It's either in the free list or in the GCPhys hash. */
1843	uint16_t iNext;
1844	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1845	uint16_t iUserHead;
1846	/** The number of present entries. */
1847	uint16_t cPresent;
1848	/** The first entry in the table which is present. */
1849	uint16_t iFirstPresent;
1850	/** The number of modifications to the monitored page. */
1851	uint16_t cModifications;
1852	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1853	uint16_t iModifiedNext;
1854	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1855	uint16_t iModifiedPrev;
1856	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1857	uint16_t iMonitoredNext;
1858	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1859	uint16_t iMonitoredPrev;
1860	/** The next page in the age list. */
1861	uint16_t iAgeNext;
1862	/** The previous page in the age list. */
1863	uint16_t iAgePrev;
1864	/** Used to indicate that the page is zeroed. */
1865	bool fZeroed;
1866	/** Used to indicate that a PT has non-global entries. */
1867	bool fSeenNonGlobal;
1868	/** Used to indicate that we're monitoring writes to the guest page. */
1869	bool fMonitored;
1870	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1871	* (All pages are in the age list.) */
1872	bool fCached;
1873	/** This is used by the R3 access handlers when invoked by an async thread.
1874	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1875	bool volatile fReusedFlushPending;
1876	/** Used to mark the page as dirty (write monitoring if temporarily off. */
1877	bool fDirty;
1878
1879	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1880	uint32_t cLocked;
1881	uint32_t idxDirty;
1882	RTGCPTR pvDirtyFault;
1883	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1884	/** Pointer to a const pool page. */
1885	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1886
1887
1888	/** The hash table size. */
1889	# define PGMPOOL_HASH_SIZE 0x40
1890	/** The hash function. */
1891	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1892
1893
1894	/**
1895	* The shadow page pool instance data.
1896	*
1897	* It's all one big allocation made at init time, except for the
1898	* pages that is. The user nodes follows immediatly after the
1899	* page structures.
1900	*/
1901	typedef struct PGMPOOL
1902	{
1903	/** The VM handle - R3 Ptr. */
1904	PVMR3 pVMR3;
1905	/** The VM handle - R0 Ptr. */
1906	PVMR0 pVMR0;
1907	/** The VM handle - RC Ptr. */
1908	PVMRC pVMRC;
1909	/** The max pool size. This includes the special IDs. */
1910	uint16_t cMaxPages;
1911	/** The current pool size. */
1912	uint16_t cCurPages;
1913	/** The head of the free page list. */
1914	uint16_t iFreeHead;
1915	/* Padding. */
1916	uint16_t u16Padding;
1917	/** Head of the chain of free user nodes. */
1918	uint16_t iUserFreeHead;
1919	/** The number of user nodes we've allocated. */
1920	uint16_t cMaxUsers;
1921	/** The number of present page table entries in the entire pool. */
1922	uint32_t cPresent;
1923	/** Pointer to the array of user nodes - RC pointer. */
1924	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1925	/** Pointer to the array of user nodes - R3 pointer. */
1926	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1927	/** Pointer to the array of user nodes - R0 pointer. */
1928	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1929	/** Head of the chain of free phys ext nodes. */
1930	uint16_t iPhysExtFreeHead;
1931	/** The number of user nodes we've allocated. */
1932	uint16_t cMaxPhysExts;
1933	/** Pointer to the array of physical xref extent - RC pointer. */
1934	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1935	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1936	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1937	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1938	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1939	/** Hash table for GCPhys addresses. */
1940	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1941	/** The head of the age list. */
1942	uint16_t iAgeHead;
1943	/** The tail of the age list. */
1944	uint16_t iAgeTail;
1945	/** Set if the cache is enabled. */
1946	bool fCacheEnabled;
1947	/** Alignment padding. */
1948	bool afPadding1[3];
1949	/** Head of the list of modified pages. */
1950	uint16_t iModifiedHead;
1951	/** The current number of modified pages. */
1952	uint16_t cModifiedPages;
1953	/** Access handler, RC. */
1954	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1955	/** Access handler, R0. */
1956	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1957	/** Access handler, R3. */
1958	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1959	/** The access handler description (R3 ptr). */
1960	R3PTRTYPE(const char *) pszAccessHandler;
1961	# if HC_ARCH_BITS == 32
1962	/** Alignment padding. */
1963	uint32_t u32Padding2;
1964	# endif
1965	/* Next available slot. */
1966	uint32_t idxFreeDirtyPage;
1967	/* Number of active dirty pages. */
1968	uint32_t cDirtyPages;
1969	/* Array of current dirty pgm pool page indices. */
1970	uint16_t aIdxDirtyPages[16];
1971	uint64_t aDirtyPages[16][512];
1972	/** The number of pages currently in use. */
1973	uint16_t cUsedPages;
1974	#ifdef VBOX_WITH_STATISTICS
1975	/** The high water mark for cUsedPages. */
1976	uint16_t cUsedPagesHigh;
1977	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1978	/** Profiling pgmPoolAlloc(). */
1979	STAMPROFILEADV StatAlloc;
1980	/** Profiling pgmR3PoolClearDoIt(). */
1981	STAMPROFILE StatClearAll;
1982	/** Profiling pgmR3PoolReset(). */
1983	STAMPROFILE StatR3Reset;
1984	/** Profiling pgmPoolFlushPage(). */
1985	STAMPROFILE StatFlushPage;
1986	/** Profiling pgmPoolFree(). */
1987	STAMPROFILE StatFree;
1988	/** Counting explicit flushes by PGMPoolFlushPage(). */
1989	STAMCOUNTER StatForceFlushPage;
1990	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
1991	STAMCOUNTER StatForceFlushDirtyPage;
1992	/** Counting flushes for reused pages. */
1993	STAMCOUNTER StatForceFlushReused;
1994	/** Profiling time spent zeroing pages. */
1995	STAMPROFILE StatZeroPage;
1996	/** Profiling of pgmPoolTrackDeref. */
1997	STAMPROFILE StatTrackDeref;
1998	/** Profiling pgmTrackFlushGCPhysPT. */
1999	STAMPROFILE StatTrackFlushGCPhysPT;
2000	/** Profiling pgmTrackFlushGCPhysPTs. */
2001	STAMPROFILE StatTrackFlushGCPhysPTs;
2002	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2003	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2004	/** Number of times we've been out of user records. */
2005	STAMCOUNTER StatTrackFreeUpOneUser;
2006	/** Nr of flushed entries. */
2007	STAMCOUNTER StatTrackFlushEntry;
2008	/** Nr of updated entries. */
2009	STAMCOUNTER StatTrackFlushEntryKeep;
2010	/** Profiling deref activity related tracking GC physical pages. */
2011	STAMPROFILE StatTrackDerefGCPhys;
2012	/** Number of linear searches for a HCPhys in the ram ranges. */
2013	STAMCOUNTER StatTrackLinearRamSearches;
2014	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2015	STAMCOUNTER StamTrackPhysExtAllocFailures;
2016	/** Profiling the RC/R0 access handler. */
2017	STAMPROFILE StatMonitorRZ;
2018	/** Times we've failed interpreting the instruction. */
2019	STAMCOUNTER StatMonitorRZEmulateInstr;
2020	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2021	STAMPROFILE StatMonitorRZFlushPage;
2022	/* Times we've detected a page table reinit. */
2023	STAMCOUNTER StatMonitorRZFlushReinit;
2024	/** Counting flushes for pages that are modified too often. */
2025	STAMCOUNTER StatMonitorRZFlushModOverflow;
2026	/** Times we've detected fork(). */
2027	STAMCOUNTER StatMonitorRZFork;
2028	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2029	STAMPROFILE StatMonitorRZHandled;
2030	/** Times we've failed interpreting a patch code instruction. */
2031	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2032	/** Times we've failed interpreting a patch code instruction during flushing. */
2033	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2034	/** The number of times we've seen rep prefixes we can't handle. */
2035	STAMCOUNTER StatMonitorRZRepPrefix;
2036	/** Profiling the REP STOSD cases we've handled. */
2037	STAMPROFILE StatMonitorRZRepStosd;
2038	/** Nr of handled PT faults. */
2039	STAMCOUNTER StatMonitorRZFaultPT;
2040	/** Nr of handled PD faults. */
2041	STAMCOUNTER StatMonitorRZFaultPD;
2042	/** Nr of handled PDPT faults. */
2043	STAMCOUNTER StatMonitorRZFaultPDPT;
2044	/** Nr of handled PML4 faults. */
2045	STAMCOUNTER StatMonitorRZFaultPML4;
2046
2047	/** Profiling the R3 access handler. */
2048	STAMPROFILE StatMonitorR3;
2049	/** Times we've failed interpreting the instruction. */
2050	STAMCOUNTER StatMonitorR3EmulateInstr;
2051	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2052	STAMPROFILE StatMonitorR3FlushPage;
2053	/* Times we've detected a page table reinit. */
2054	STAMCOUNTER StatMonitorR3FlushReinit;
2055	/** Counting flushes for pages that are modified too often. */
2056	STAMCOUNTER StatMonitorR3FlushModOverflow;
2057	/** Times we've detected fork(). */
2058	STAMCOUNTER StatMonitorR3Fork;
2059	/** Profiling the R3 access we've handled (except REP STOSD). */
2060	STAMPROFILE StatMonitorR3Handled;
2061	/** The number of times we've seen rep prefixes we can't handle. */
2062	STAMCOUNTER StatMonitorR3RepPrefix;
2063	/** Profiling the REP STOSD cases we've handled. */
2064	STAMPROFILE StatMonitorR3RepStosd;
2065	/** Nr of handled PT faults. */
2066	STAMCOUNTER StatMonitorR3FaultPT;
2067	/** Nr of handled PD faults. */
2068	STAMCOUNTER StatMonitorR3FaultPD;
2069	/** Nr of handled PDPT faults. */
2070	STAMCOUNTER StatMonitorR3FaultPDPT;
2071	/** Nr of handled PML4 faults. */
2072	STAMCOUNTER StatMonitorR3FaultPML4;
2073	/** The number of times we're called in an async thread an need to flush. */
2074	STAMCOUNTER StatMonitorR3Async;
2075	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2076	STAMCOUNTER StatResetDirtyPages;
2077	/** Times we've called pgmPoolAddDirtyPage. */
2078	STAMCOUNTER StatDirtyPage;
2079	/** Times we've had to flush duplicates for dirty page management. */
2080	STAMCOUNTER StatDirtyPageDupFlush;
2081	/** Times we've had to flush because of overflow. */
2082	STAMCOUNTER StatDirtyPageOverFlowFlush;
2083
2084	/** The high wather mark for cModifiedPages. */
2085	uint16_t cModifiedPagesHigh;
2086	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
2087
2088	/** The number of cache hits. */
2089	STAMCOUNTER StatCacheHits;
2090	/** The number of cache misses. */
2091	STAMCOUNTER StatCacheMisses;
2092	/** The number of times we've got a conflict of 'kind' in the cache. */
2093	STAMCOUNTER StatCacheKindMismatches;
2094	/** Number of times we've been out of pages. */
2095	STAMCOUNTER StatCacheFreeUpOne;
2096	/** The number of cacheable allocations. */
2097	STAMCOUNTER StatCacheCacheable;
2098	/** The number of uncacheable allocations. */
2099	STAMCOUNTER StatCacheUncacheable;
2100	#else
2101	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
2102	#endif
2103	/** The AVL tree for looking up a page by its HC physical address. */
2104	AVLOHCPHYSTREE HCPhysTree;
2105	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
2106	/** Array of pages. (cMaxPages in length)
2107	* The Id is the index into thist array.
2108	*/
2109	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2110	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2111	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2112	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2113	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2114	#ifdef VBOX_WITH_STATISTICS
2115	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2116	#endif
2117	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2118
2119
2120	/** @def PGMPOOL_PAGE_2_PTR
2121	* Maps a pool page pool into the current context.
2122	*
2123	* @returns VBox status code.
2124	* @param pVM The VM handle.
2125	* @param pPage The pool page.
2126	*
2127	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2128	* small page window employeed by that function. Be careful.
2129	* @remark There is no need to assert on the result.
2130	*/
2131	#if defined(IN_RC)
2132	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2133	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2134	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2135	#elif defined(VBOX_STRICT)
2136	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2137	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2138	{
2139	Assert(pPage && pPage->pvPageR3);
2140	return pPage->pvPageR3;
2141	}
2142	#else
2143	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2144	#endif
2145
2146	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2147	* Maps a pool page pool into the current context.
2148	*
2149	* @returns VBox status code.
2150	* @param pPGM Pointer to the PGM instance data.
2151	* @param pPage The pool page.
2152	*
2153	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2154	* small page window employeed by that function. Be careful.
2155	* @remark There is no need to assert on the result.
2156	*/
2157	#if defined(IN_RC)
2158	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2159	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2160	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2161	#else
2162	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2163	#endif
2164
2165	/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2166	* Maps a pool page pool into the current context.
2167	*
2168	* @returns VBox status code.
2169	* @param pPGM Pointer to the PGMCPU instance data.
2170	* @param pPage The pool page.
2171	*
2172	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2173	* small page window employeed by that function. Be careful.
2174	* @remark There is no need to assert on the result.
2175	*/
2176	#if defined(IN_RC)
2177	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2178	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2179	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2180	#else
2181	# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2182	#endif
2183
2184
2185	/** @name Per guest page tracking data.
2186	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2187	* is to use more bits for it and split it up later on. But for now we'll play
2188	* safe and change as little as possible.
2189	*
2190	* The 16-bit word has two parts:
2191	*
2192	* The first 14-bit forms the @a idx field. It is either the index of a page in
2193	* the shadow page pool, or and index into the extent list.
2194	*
2195	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2196	* shadow page pool references to the page. If cRefs equals
2197	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2198	* (misnomer) table and not the shadow page pool.
2199	*
2200	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2201	* the 16-bit word.
2202	*
2203	* @{ */
2204	/** The shift count for getting to the cRefs part. */
2205	#define PGMPOOL_TD_CREFS_SHIFT 14
2206	/** The mask applied after shifting the tracking data down by
2207	* PGMPOOL_TD_CREFS_SHIFT. */
2208	#define PGMPOOL_TD_CREFS_MASK 0x3
2209	/** The cRef value used to indiciate that the idx is the head of a
2210	* physical cross reference list. */
2211	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2212	/** The shift used to get idx. */
2213	#define PGMPOOL_TD_IDX_SHIFT 0
2214	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2215	#define PGMPOOL_TD_IDX_MASK 0x3fff
2216	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2217	* simply too many mappings of this page. */
2218	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2219
2220	/** @def PGMPOOL_TD_MAKE
2221	* Makes a 16-bit tracking data word.
2222	*
2223	* @returns tracking data.
2224	* @param cRefs The @a cRefs field. Must be within bounds!
2225	* @param idx The @a idx field. Must also be within bounds! */
2226	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2227
2228	/** @def PGMPOOL_TD_GET_CREFS
2229	* Get the @a cRefs field from a tracking data word.
2230	*
2231	* @returns The @a cRefs field
2232	* @param u16 The tracking data word. */
2233	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2234
2235	/** @def PGMPOOL_TD_GET_IDX
2236	* Get the @a idx field from a tracking data word.
2237	*
2238	* @returns The @a idx field
2239	* @param u16 The tracking data word. */
2240	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2241	/** @} */
2242
2243
2244	/**
2245	* Trees are using self relative offsets as pointers.
2246	* So, all its data, including the root pointer, must be in the heap for HC and GC
2247	* to have the same layout.
2248	*/
2249	typedef struct PGMTREES
2250	{
2251	/** Physical access handlers (AVL range+offsetptr tree). */
2252	AVLROGCPHYSTREE PhysHandlers;
2253	/** Virtual access handlers (AVL range + GC ptr tree). */
2254	AVLROGCPTRTREE VirtHandlers;
2255	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2256	AVLROGCPHYSTREE PhysToVirtHandlers;
2257	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2258	AVLROGCPTRTREE HyperVirtHandlers;
2259	} PGMTREES;
2260	/** Pointer to PGM trees. */
2261	typedef PGMTREES *PPGMTREES;
2262
2263
2264	/** @name Paging mode macros
2265	* @{ */
2266	#ifdef IN_RC
2267	# define PGM_CTX(a,b) a##RC##b
2268	# define PGM_CTX_STR(a,b) a "GC" b
2269	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2270	#else
2271	# ifdef IN_RING3
2272	# define PGM_CTX(a,b) a##R3##b
2273	# define PGM_CTX_STR(a,b) a "R3" b
2274	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2275	# else
2276	# define PGM_CTX(a,b) a##R0##b
2277	# define PGM_CTX_STR(a,b) a "R0" b
2278	# define PGM_CTX_DECL(type) VMMDECL(type)
2279	# endif
2280	#endif
2281
2282	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2283	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2284	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2285	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2286	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2287	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2288	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2289	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2290	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2291	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2292	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2293	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2294	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2295	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2296	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2297	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2298	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2299
2300	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2301	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2302	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2303	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2304	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2305	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2306	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2307	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2308	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2309	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2310	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2311	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2312	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2313	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2314	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2315	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2316	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2317
2318	/* Shw_Gst */
2319	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2320	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2321	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2322	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2323	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2324	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2325	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2326	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2327	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2328	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2329	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2330	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2331	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2332	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2333	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2334	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2335	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2336	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2337	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2338
2339	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2340	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2341	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2342	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2343	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2344	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2345	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2346	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2347	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2348	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2349	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2350	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2351	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2352	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2353	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2354	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2355	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2356	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2357	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2358	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2359	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2360	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2361	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2362	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2363	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2364	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2365	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2366	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2367	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2368	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2369	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2370	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2371	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2372	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2373	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2374	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2375	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2376
2377	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2378	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2379	/** @} */
2380
2381	/**
2382	* Data for each paging mode.
2383	*/
2384	typedef struct PGMMODEDATA
2385	{
2386	/** The guest mode type. */
2387	uint32_t uGstType;
2388	/** The shadow mode type. */
2389	uint32_t uShwType;
2390
2391	/** @name Function pointers for Shadow paging.
2392	* @{
2393	*/
2394	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2395	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2396	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2397	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2398
2399	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2400	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2401
2402	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2403	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2404	/** @} */
2405
2406	/** @name Function pointers for Guest paging.
2407	* @{
2408	*/
2409	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2410	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2411	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2412	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2413	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2414	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2415	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2416	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2417	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2418	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2419	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2420	/** @} */
2421
2422	/** @name Function pointers for Both Shadow and Guest paging.
2423	* @{
2424	*/
2425	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2426	/* no pfnR3BthTrap0eHandler */
2427	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2428	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2429	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2430	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2431	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2432	#ifdef VBOX_STRICT
2433	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2434	#endif
2435	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2436	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2437
2438	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2439	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2440	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2441	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2442	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2443	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2444	#ifdef VBOX_STRICT
2445	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2446	#endif
2447	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2448	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2449
2450	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2451	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2452	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2453	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2454	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2455	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2456	#ifdef VBOX_STRICT
2457	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2458	#endif
2459	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2460	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2461	/** @} */
2462	} PGMMODEDATA, *PPGMMODEDATA;
2463
2464
2465
2466	/**
2467	* Converts a PGM pointer into a VM pointer.
2468	* @returns Pointer to the VM structure the PGM is part of.
2469	* @param pPGM Pointer to PGM instance data.
2470	*/
2471	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2472
2473	/**
2474	* PGM Data (part of VM)
2475	*/
2476	typedef struct PGM
2477	{
2478	/** Offset to the VM structure. */
2479	RTINT offVM;
2480	/** Offset of the PGMCPU structure relative to VMCPU. */
2481	RTINT offVCpuPGM;
2482
2483	/** @cfgm{RamPreAlloc, boolean, false}
2484	* Indicates whether the base RAM should all be allocated before starting
2485	* the VM (default), or if it should be allocated when first written to.
2486	*/
2487	bool fRamPreAlloc;
2488	/** Indicates whether write monitoring is currently in use.
2489	* This is used to prevent conflicts between live saving and page sharing
2490	* detection. */
2491	bool fPhysWriteMonitoringEngaged;
2492	/** Alignment padding. */
2493	bool afAlignment0[2];
2494
2495	/*
2496	* This will be redefined at least two more times before we're done, I'm sure.
2497	* The current code is only to get on with the coding.
2498	* - 2004-06-10: initial version, bird.
2499	* - 2004-07-02: 1st time, bird.
2500	* - 2004-10-18: 2nd time, bird.
2501	* - 2005-07-xx: 3rd time, bird.
2502	*/
2503
2504	/** The host paging mode. (This is what SUPLib reports.) */
2505	SUPPAGINGMODE enmHostMode;
2506
2507	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2508	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2509	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2510	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2511
2512	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2513	RTGCPHYS GCPhys4MBPSEMask;
2514
2515	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2516	* This is sorted by physical address and contains no overlapping ranges. */
2517	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2518	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2519	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2520	/** RC pointer corresponding to PGM::pRamRangesR3. */
2521	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2522	/** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2523	* range is linked or unlinked. */
2524	uint32_t volatile idRamRangesGen;
2525
2526	/** Pointer to the list of ROM ranges - for R3.
2527	* This is sorted by physical address and contains no overlapping ranges. */
2528	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2529	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2530	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2531	/** RC pointer corresponding to PGM::pRomRangesR3. */
2532	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2533	#if HC_ARCH_BITS == 64
2534	/** Alignment padding. */
2535	RTRCPTR GCPtrPadding2;
2536	#endif
2537
2538	/** Pointer to the list of MMIO2 ranges - for R3.
2539	* Registration order. */
2540	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2541
2542	/** PGM offset based trees - R3 Ptr. */
2543	R3PTRTYPE(PPGMTREES) pTreesR3;
2544	/** PGM offset based trees - R0 Ptr. */
2545	R0PTRTYPE(PPGMTREES) pTreesR0;
2546	/** PGM offset based trees - RC Ptr. */
2547	RCPTRTYPE(PPGMTREES) pTreesRC;
2548
2549	/** Linked list of GC mappings - for RC.
2550	* The list is sorted ascending on address.
2551	*/
2552	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2553	/** Linked list of GC mappings - for HC.
2554	* The list is sorted ascending on address.
2555	*/
2556	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2557	/** Linked list of GC mappings - for R0.
2558	* The list is sorted ascending on address.
2559	*/
2560	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2561
2562	/** Pointer to the 5 page CR3 content mapping.
2563	* The first page is always the CR3 (in some form) while the 4 other pages
2564	* are used of the PDs in PAE mode. */
2565	RTGCPTR GCPtrCR3Mapping;
2566	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2567	uint32_t u32Alignment1;
2568	#endif
2569
2570	/** Indicates that PGMR3FinalizeMappings has been called and that further
2571	* PGMR3MapIntermediate calls will be rejected. */
2572	bool fFinalizedMappings;
2573	/** If set no conflict checks are required. */
2574	bool fMappingsFixed;
2575	/** If set if restored as fixed but we were unable to re-fixate at the old
2576	* location because of room or address incompatibilities. */
2577	bool fMappingsFixedRestored;
2578	/** If set, then no mappings are put into the shadow page table.
2579	* Use pgmMapAreMappingsEnabled() instead of direct access. */
2580	bool fMappingsDisabled;
2581	/** Size of fixed mapping.
2582	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2583	uint32_t cbMappingFixed;
2584	/** Base address (GC) of fixed mapping.
2585	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2586	RTGCPTR GCPtrMappingFixed;
2587	/** The address of the previous RAM range mapping. */
2588	RTGCPTR GCPtrPrevRamRangeMapping;
2589
2590	/** @name Intermediate Context
2591	* @{ */
2592	/** Pointer to the intermediate page directory - Normal. */
2593	R3PTRTYPE(PX86PD) pInterPD;
2594	/** Pointer to the intermedate page tables - Normal.
2595	* There are two page tables, one for the identity mapping and one for
2596	* the host context mapping (of the core code). */
2597	R3PTRTYPE(PX86PT) apInterPTs[2];
2598	/** Pointer to the intermedate page tables - PAE. */
2599	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2600	/** Pointer to the intermedate page directory - PAE. */
2601	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2602	/** Pointer to the intermedate page directory - PAE. */
2603	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2604	/** Pointer to the intermedate page-map level 4 - AMD64. */
2605	R3PTRTYPE(PX86PML4) pInterPaePML4;
2606	/** Pointer to the intermedate page directory - AMD64. */
2607	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2608	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2609	RTHCPHYS HCPhysInterPD;
2610	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2611	RTHCPHYS HCPhysInterPaePDPT;
2612	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2613	RTHCPHYS HCPhysInterPaePML4;
2614	/** @} */
2615
2616	/** Base address of the dynamic page mapping area.
2617	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2618	*/
2619	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2620	/** The index of the last entry used in the dynamic page mapping area. */
2621	RTUINT iDynPageMapLast;
2622	/** Cache containing the last entries in the dynamic page mapping area.
2623	* The cache size is covering half of the mapping area. */
2624	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2625	/** Keep a lock counter for the full (!) mapping area. */
2626	uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2627
2628	/** The address of the ring-0 mapping cache if we're making use of it. */
2629	RTR0PTR pvR0DynMapUsed;
2630	#if HC_ARCH_BITS == 32
2631	/** Alignment padding that makes the next member start on a 8 byte boundrary. */
2632	uint32_t u32Alignment2;
2633	#endif
2634
2635	/** PGM critical section.
2636	* This protects the physical & virtual access handlers, ram ranges,
2637	* and the page flag updating (some of it anyway).
2638	*/
2639	PDMCRITSECT CritSect;
2640
2641	/** Pointer to SHW+GST mode data (function pointers).
2642	* The index into this table is made up from */
2643	R3PTRTYPE(PPGMMODEDATA) paModeData;
2644
2645	/** Shadow Page Pool - R3 Ptr. */
2646	R3PTRTYPE(PPGMPOOL) pPoolR3;
2647	/** Shadow Page Pool - R0 Ptr. */
2648	R0PTRTYPE(PPGMPOOL) pPoolR0;
2649	/** Shadow Page Pool - RC Ptr. */
2650	RCPTRTYPE(PPGMPOOL) pPoolRC;
2651
2652	/** We're not in a state which permits writes to guest memory.
2653	* (Only used in strict builds.) */
2654	bool fNoMorePhysWrites;
2655	/** Alignment padding that makes the next member start on a 8 byte boundrary. */
2656	bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2657
2658	/**
2659	* Data associated with managing the ring-3 mappings of the allocation chunks.
2660	*/
2661	struct
2662	{
2663	/** The chunk tree, ordered by chunk id. */
2664	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2665	R3PTRTYPE(PAVLU32NODECORE) pTree;
2666	#else
2667	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2668	#endif
2669	/** The chunk age tree, ordered by ageing sequence number. */
2670	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2671	/** The chunk mapping TLB. */
2672	PGMCHUNKR3MAPTLB Tlb;
2673	/** The number of mapped chunks. */
2674	uint32_t c;
2675	/** The maximum number of mapped chunks.
2676	* @cfgm PGM/MaxRing3Chunks */
2677	uint32_t cMax;
2678	/** The current time. */
2679	uint32_t iNow;
2680	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2681	uint32_t AgeingCountdown;
2682	} ChunkR3Map;
2683
2684	/**
2685	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2686	*/
2687	PGMPAGER3MAPTLB PhysTlbHC;
2688
2689	/** @name The zero page.
2690	* @{ */
2691	/** The host physical address of the zero page. */
2692	RTHCPHYS HCPhysZeroPg;
2693	/** The ring-3 mapping of the zero page. */
2694	RTR3PTR pvZeroPgR3;
2695	/** The ring-0 mapping of the zero page. */
2696	RTR0PTR pvZeroPgR0;
2697	/** The GC mapping of the zero page. */
2698	RTGCPTR pvZeroPgRC;
2699	/** @}*/
2700
2701	/** The number of handy pages. */
2702	uint32_t cHandyPages;
2703
2704	/** The number of large handy pages. */
2705	uint32_t cLargeHandyPages;
2706
2707	/**
2708	* Array of handy pages.
2709	*
2710	* This array is used in a two way communication between pgmPhysAllocPage
2711	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2712	* an intermediary.
2713	*
2714	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2715	* (The current size of 32 pages, means 128 KB of handy memory.)
2716	*/
2717	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2718
2719	/**
2720	* Array of large handy pages. (currently size 1)
2721	*
2722	* This array is used in a two way communication between pgmPhysAllocLargePage
2723	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
2724	* an intermediary.
2725	*/
2726	GMMPAGEDESC aLargeHandyPage[1];
2727
2728	/**
2729	* Live save data.
2730	*/
2731	struct
2732	{
2733	/** Per type statistics. */
2734	struct
2735	{
2736	/** The number of ready pages. */
2737	uint32_t cReadyPages;
2738	/** The number of dirty pages. */
2739	uint32_t cDirtyPages;
2740	/** The number of ready zero pages. */
2741	uint32_t cZeroPages;
2742	/** The number of write monitored pages. */
2743	uint32_t cMonitoredPages;
2744	} Rom,
2745	Mmio2,
2746	Ram;
2747	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
2748	uint32_t cIgnoredPages;
2749	/** Indicates that a live save operation is active. */
2750	bool fActive;
2751	/** Padding. */
2752	bool afReserved[2];
2753	/** The next history index. */
2754	uint8_t iDirtyPagesHistory;
2755	/** History of the total amount of dirty pages. */
2756	uint32_t acDirtyPagesHistory[64];
2757	/** Short term dirty page average. */
2758	uint32_t cDirtyPagesShort;
2759	/** Long term dirty page average. */
2760	uint32_t cDirtyPagesLong;
2761	/** The number of saved pages. This is used to get some kind of estimate of the
2762	* link speed so we can decide when we're done. It is reset after the first
2763	* 7 passes so the speed estimate doesn't get inflated by the initial set of
2764	* zero pages. */
2765	uint64_t cSavedPages;
2766	/** The nanosecond timestamp when cSavedPages was 0. */
2767	uint64_t uSaveStartNS;
2768	/** Pages per second (for statistics). */
2769	uint32_t cPagesPerSecond;
2770	uint32_t cAlignment;
2771	} LiveSave;
2772
2773	/** @name Error injection.
2774	* @{ */
2775	/** Inject handy page allocation errors pretending we're completely out of
2776	* memory. */
2777	bool volatile fErrInjHandyPages;
2778	/** Padding. */
2779	bool afReserved[3];
2780	/** @} */
2781
2782	/** @name Release Statistics
2783	* @{ */
2784	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
2785	uint32_t cPrivatePages; /*< The number of private pages. /
2786	uint32_t cSharedPages; /*< The number of shared pages. /
2787	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
2788	uint32_t cZeroPages; /*< The number of zero backed pages. /
2789	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
2790	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
2791	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
2792	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
2793	uint32_t cReadLockedPages; /*< The number of read locked pages. /
2794	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
2795	/* uint32_t aAlignment4[1]; */
2796
2797	/** The number of times we were forced to change the hypervisor region location. */
2798	STAMCOUNTER cRelocations;
2799
2800	STAMCOUNTER StatLargePageAlloc; /*< The number of large pages we've allocated./
2801	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
2802	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
2803	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
2804	/** @} */
2805
2806	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2807	/* R3 only: */
2808	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2809	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2810
2811	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2812	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2813	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2814	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2815	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2816	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2817	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2818	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2819	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2820	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2821	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2822	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2823	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2824	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2825	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2826	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2827	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2828	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2829	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2830	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2831	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2832	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2833	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2834	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2835
2836	/* RC only: */
2837	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache misses /
2838	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache hits /
2839	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2840	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2841
2842	STAMCOUNTER StatRZPhysRead;
2843	STAMCOUNTER StatRZPhysReadBytes;
2844	STAMCOUNTER StatRZPhysWrite;
2845	STAMCOUNTER StatRZPhysWriteBytes;
2846	STAMCOUNTER StatR3PhysRead;
2847	STAMCOUNTER StatR3PhysReadBytes;
2848	STAMCOUNTER StatR3PhysWrite;
2849	STAMCOUNTER StatR3PhysWriteBytes;
2850	STAMCOUNTER StatRCPhysRead;
2851	STAMCOUNTER StatRCPhysReadBytes;
2852	STAMCOUNTER StatRCPhysWrite;
2853	STAMCOUNTER StatRCPhysWriteBytes;
2854
2855	STAMCOUNTER StatRZPhysSimpleRead;
2856	STAMCOUNTER StatRZPhysSimpleReadBytes;
2857	STAMCOUNTER StatRZPhysSimpleWrite;
2858	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2859	STAMCOUNTER StatR3PhysSimpleRead;
2860	STAMCOUNTER StatR3PhysSimpleReadBytes;
2861	STAMCOUNTER StatR3PhysSimpleWrite;
2862	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2863	STAMCOUNTER StatRCPhysSimpleRead;
2864	STAMCOUNTER StatRCPhysSimpleReadBytes;
2865	STAMCOUNTER StatRCPhysSimpleWrite;
2866	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2867
2868	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2869	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2870	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2871	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2872	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2873	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2874	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2875
2876	/** Time spent by the host OS for large page allocation. */
2877	STAMPROFILE StatAllocLargePage;
2878	/** Time spent clearing the newly allocated large pages. */
2879	STAMPROFILE StatClearLargePage;
2880	/** pgmPhysIsValidLargePage profiling - R3 */
2881	STAMPROFILE StatR3IsValidLargePage;
2882	/** pgmPhysIsValidLargePage profiling - RZ*/
2883	STAMPROFILE StatRZIsValidLargePage;
2884	#endif
2885	} PGM;
2886	#ifndef IN_TSTVMSTRUCTGC /* HACK */
2887	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2888	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2889	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2890	AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2891	AssertCompileMemberAlignment(PGM, CritSect, 8);
2892	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2893	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2894	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2895	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2896	AssertCompileMemberAlignment(PGM, cRelocations, 8);
2897	#endif /* !IN_TSTVMSTRUCTGC */
2898	/** Pointer to the PGM instance data. */
2899	typedef PGM *PPGM;
2900
2901
2902	/**
2903	* Converts a PGMCPU pointer into a VM pointer.
2904	* @returns Pointer to the VM structure the PGM is part of.
2905	* @param pPGM Pointer to PGMCPU instance data.
2906	*/
2907	#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2908
2909	/**
2910	* Converts a PGMCPU pointer into a PGM pointer.
2911	* @returns Pointer to the VM structure the PGM is part of.
2912	* @param pPGM Pointer to PGMCPU instance data.
2913	*/
2914	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2915
2916	/**
2917	* PGMCPU Data (part of VMCPU).
2918	*/
2919	typedef struct PGMCPU
2920	{
2921	/** Offset to the VM structure. */
2922	RTINT offVM;
2923	/** Offset to the VMCPU structure. */
2924	RTINT offVCpu;
2925	/** Offset of the PGM structure relative to VMCPU. */
2926	RTINT offPGM;
2927	RTINT uPadding0; /*< structure size alignment. /
2928
2929	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2930	/** Automatically tracked physical memory mapping set.
2931	* Ring-0 and strict raw-mode builds. */
2932	PGMMAPSET AutoSet;
2933	#endif
2934
2935	/** A20 gate mask.
2936	* Our current approach to A20 emulation is to let REM do it and don't bother
2937	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2938	* But whould need arrise, we'll subject physical addresses to this mask. */
2939	RTGCPHYS GCPhysA20Mask;
2940	/** A20 gate state - boolean! */
2941	bool fA20Enabled;
2942
2943	/** What needs syncing (PGM_SYNC_*).
2944	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2945	* PGMFlushTLB, and PGMR3Load. */
2946	RTUINT fSyncFlags;
2947
2948	/** The shadow paging mode. */
2949	PGMMODE enmShadowMode;
2950	/** The guest paging mode. */
2951	PGMMODE enmGuestMode;
2952
2953	/** The current physical address representing in the guest CR3 register. */
2954	RTGCPHYS GCPhysCR3;
2955
2956	/** @name 32-bit Guest Paging.
2957	* @{ */
2958	/** The guest's page directory, R3 pointer. */
2959	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2960	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2961	/** The guest's page directory, R0 pointer. */
2962	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2963	#endif
2964	/** The guest's page directory, static RC mapping. */
2965	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2966	/** @} */
2967
2968	/** @name PAE Guest Paging.
2969	* @{ */
2970	/** The guest's page directory pointer table, static RC mapping. */
2971	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2972	/** The guest's page directory pointer table, R3 pointer. */
2973	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2974	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2975	/** The guest's page directory pointer table, R0 pointer. */
2976	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2977	#endif
2978
2979	/** The guest's page directories, R3 pointers.
2980	* These are individual pointers and don't have to be adjecent.
2981	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2982	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2983	/** The guest's page directories, R0 pointers.
2984	* Same restrictions as apGstPaePDsR3. */
2985	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2986	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2987	#endif
2988	/** The guest's page directories, static GC mapping.
2989	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2990	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2991	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2992	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2993	RTGCPHYS aGCPhysGstPaePDs[4];
2994	/** The physical addresses of the monitored guest page directories (PAE). */
2995	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2996	/** @} */
2997
2998	/** @name AMD64 Guest Paging.
2999	* @{ */
3000	/** The guest's page directory pointer table, R3 pointer. */
3001	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3002	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3003	/** The guest's page directory pointer table, R0 pointer. */
3004	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3005	#else
3006	RTR0PTR alignment6b; /*< alignment equalizer. /
3007	#endif
3008	/** @} */
3009
3010	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3011	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3012	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3013	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3014	/** Pointer to the page of the current active CR3 - RC Ptr. */
3015	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3016	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3017	uint32_t iShwUser;
3018	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3019	uint32_t iShwUserTable;
3020	# if HC_ARCH_BITS == 64
3021	RTRCPTR alignment6; /*< structure size alignment. /
3022	# endif
3023	/** @} */
3024
3025	/** @name Function pointers for Shadow paging.
3026	* @{
3027	*/
3028	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3029	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3030	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3031	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3032
3033	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3034	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3035
3036	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3037	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3038
3039	/** @} */
3040
3041	/** @name Function pointers for Guest paging.
3042	* @{
3043	*/
3044	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3045	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3046	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3047	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3048	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3049	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3050	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3051	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3052	#if HC_ARCH_BITS == 64
3053	RTRCPTR alignment3; /*< structure size alignment. /
3054	#endif
3055
3056	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3057	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3058	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3059	/** @} */
3060
3061	/** @name Function pointers for Both Shadow and Guest paging.
3062	* @{
3063	*/
3064	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3065	/* no pfnR3BthTrap0eHandler */
3066	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3067	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3068	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3069	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3070	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3071	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3072	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3073	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3074
3075	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3076	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3077	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3078	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3079	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3080	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3081	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3082	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3083	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3084
3085	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3086	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3087	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3088	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3089	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3090	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3091	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3092	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3093	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3094	RTRCPTR alignment2; /*< structure size alignment. /
3095	/** @} */
3096
3097	/** For saving stack space, the disassembler state is allocated here instead of
3098	* on the stack.
3099	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3100	union
3101	{
3102	/** The disassembler scratch space. */
3103	DISCPUSTATE DisState;
3104	/** Padding. */
3105	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3106	};
3107
3108	/* Count the number of pgm pool access handler calls. */
3109	uint64_t cPoolAccessHandler;
3110
3111	/** @name Release Statistics
3112	* @{ */
3113	/** The number of times the guest has switched mode since last reset or statistics reset. */
3114	STAMCOUNTER cGuestModeChanges;
3115	/** @} */
3116
3117	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3118	/** @name Statistics
3119	* @{ */
3120	/** RC: Which statistic this \#PF should be attributed to. */
3121	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3122	RTRCPTR padding0;
3123	/** R0: Which statistic this \#PF should be attributed to. */
3124	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3125	RTR0PTR padding1;
3126
3127	/* Common */
3128	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3129	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3130
3131	/* R0 only: */
3132	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
3133	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
3134	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
3135	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
3136	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
3137	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
3138	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
3139	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
3140	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
3141	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
3142	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
3143	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
3144	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
3145	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
3146	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
3147	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
3148	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
3149	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
3150	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
3151	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
3152	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
3153	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
3154	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
3155	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
3156	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
3157	STAMCOUNTER aStatR0DynMapSetSize[11]; /*< R0: Set size distribution. /
3158
3159	/* RZ only: */
3160	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3161	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3162	STAMPROFILE StatRZTrap0eTimeSyncPT;
3163	STAMPROFILE StatRZTrap0eTimeMapping;
3164	STAMPROFILE StatRZTrap0eTimeOutOfSync;
3165	STAMPROFILE StatRZTrap0eTimeHandlers;
3166	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3167	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3168	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3169	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3170	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3171	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3172	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3173	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3174	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3175	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3176	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3177	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3178	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3179	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3180	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3181	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
3182	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3183	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3184	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3185	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3186	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3187	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3188	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3189	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3190	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3191	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3192	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3193	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3194	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3195	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3196	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3197	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3198	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3199	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest \#PF ending up at the end of the \#PF code. /
3200	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3201	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3202	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3203	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3204	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3205	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3206	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3207	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3208	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3209
3210	/* HC - R3 and (maybe) R0: */
3211
3212	/* RZ & R3: */
3213	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3214	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3215	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3216	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3217	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3218	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3219	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3220	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3221	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3222	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3223	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3224	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3225	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3226	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3227	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3228	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3229	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3230	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3231	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3232	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3233	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3234	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3235	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3236	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3237	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3238	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3239	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3240	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3241	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3242	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3243	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3244	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3245	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3246	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3247	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3248	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3249	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3250	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3251	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3252	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3253	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3254	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3255	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3256	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3257	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3258	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3259	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3260
3261	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3262	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3263	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3264	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3265	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3266	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3267	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3268	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3269	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3270	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3271	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3272	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3273	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3274	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3275	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3276	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3277	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3278	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3279	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3280	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3281	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3282	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3283	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3284	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3285	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3286	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3287	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3288	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3289	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3290	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3291	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3292	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3293	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3294	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3295	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3296	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3297	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3298	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3299	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3300	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3301	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3302	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3303	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3304	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3305	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3306	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3307	/** @} */
3308	#endif /* VBOX_WITH_STATISTICS */
3309	} PGMCPU;
3310	/** Pointer to the per-cpu PGM data. */
3311	typedef PGMCPU *PPGMCPU;
3312
3313
3314	/** @name PGM::fSyncFlags Flags
3315	* @{
3316	*/
3317	/** Updates the virtual access handler state bit in PGMPAGE. */
3318	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3319	/** Always sync CR3. */
3320	#define PGM_SYNC_ALWAYS RT_BIT(1)
3321	/** Check monitoring on next CR3 (re)load and invalidate page.
3322	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3323	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3324	/** Check guest mapping in SyncCR3. */
3325	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3326	/** Clear the page pool (a light weight flush). */
3327	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3328	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3329	/** @} */
3330
3331
3332	RT_C_DECLS_BEGIN
3333
3334	int pgmLock(PVM pVM);
3335	void pgmUnlock(PVM pVM);
3336
3337	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3338	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3339	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3340	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3341	int pgmMapResolveConflicts(PVM pVM);
3342	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3343
3344	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3345	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3346	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3347	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
3348	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3349	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
3350	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3351	#else
3352	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3353	#endif
3354	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3355	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3356
3357	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3358	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3359	int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3360	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3361	int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3362	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3363	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3364	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3365	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3366	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3367	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3368	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3369	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3370	VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3371	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3372	#ifdef IN_RING3
3373	void pgmR3PhysRelinkRamRanges(PVM pVM);
3374	int pgmR3PhysRamPreAllocate(PVM pVM);
3375	int pgmR3PhysRamReset(PVM pVM);
3376	int pgmR3PhysRomReset(PVM pVM);
3377	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3378	int pgmR3PhysRamTerm(PVM pVM);
3379
3380	int pgmR3PoolInit(PVM pVM);
3381	void pgmR3PoolRelocate(PVM pVM);
3382	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3383	void pgmR3PoolReset(PVM pVM);
3384	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3385	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3386
3387	#endif /* IN_RING3 */
3388	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3389	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3390	#endif
3391	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3392
3393	DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3394	{
3395	return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3396	}
3397
3398	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3399	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3400	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3401	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3402	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3403	int pgmPoolSyncCR3(PVMCPU pVCpu);
3404	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3405	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3406	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3407	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3408	DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3409	{
3410	return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3411	}
3412
3413	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3414	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3415	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3416	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3417	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3418
3419	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3420	void pgmPoolResetDirtyPages(PVM pVM);
3421
3422	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3423	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3424
3425	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3426	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3427	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3428	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3429
3430	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3431	#ifndef IN_RC
3432	int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3433	#endif
3434	int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD);
3435
3436	PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3437	PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3438	PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3439	PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3440
3441	RT_C_DECLS_END
3442
3443	/** @} */
3444
3445	#endif
3446

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 30326

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