VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 30045

Last change on this file since 30045 was 29646, checked in by vboxsync, 15 years ago

Proper shared page cleanup when terminating the VM
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1/* $Id: PGMInternal.h 29646 2010-05-18 15:44:08Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/stam.h>
25#include <VBox/param.h>
26#include <VBox/vmm.h>
27#include <VBox/mm.h>
28#include <VBox/pdmcritsect.h>
29#include <VBox/pdmapi.h>
30#include <VBox/dis.h>
31#include <VBox/dbgf.h>
32#include <VBox/log.h>
33#include <VBox/gmm.h>
34#include <VBox/hwaccm.h>
35#include <iprt/asm.h>
36#include <iprt/assert.h>
37#include <iprt/avl.h>
38#include <iprt/critsect.h>
39#include <iprt/sha.h>
40
41
42
43/** @defgroup grp_pgm_int Internals
44 * @ingroup grp_pgm
45 * @internal
46 * @{
47 */
48
49
50/** @name PGM Compile Time Config
51 * @{
52 */
53
54/**
55 * Indicates that there are no guest mappings to care about.
56 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
57 */
58#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
59# define PGM_WITHOUT_MAPPINGS
60#endif
61
62/**
63 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
64 * Comment it if it will break something.
65 */
66#define PGM_OUT_OF_SYNC_IN_GC
67
68/**
69 * Check and skip global PDEs for non-global flushes
70 */
71#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
72
73/**
74 * Optimization for PAE page tables that are modified often
75 */
76//#if 0 /* disabled again while debugging */
77#ifndef IN_RC
78# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
79#endif
80//#endif
81
82/**
83 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
84 */
85#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
86# define PGM_WITH_LARGE_PAGES
87#endif
88
89/**
90 * Sync N pages instead of a whole page table
91 */
92#define PGM_SYNC_N_PAGES
93
94/**
95 * Number of pages to sync during a page fault
96 *
97 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
98 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
99 *
100 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
101 * world switch overhead, so let's sync more.
102 */
103# ifdef IN_RING0
104/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
105 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
106 * but ~5% fewer faults.
107 */
108# define PGM_SYNC_NR_PAGES 32
109#else
110# define PGM_SYNC_NR_PAGES 8
111#endif
112
113/**
114 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
115 */
116#define PGM_MAX_PHYSCACHE_ENTRIES 64
117#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
118
119
120/** @def PGMPOOL_CFG_MAX_GROW
121 * The maximum number of pages to add to the pool in one go.
122 */
123#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
124
125/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
126 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
127 */
128#ifdef VBOX_STRICT
129# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
130#endif
131
132/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
133 * Enables the experimental lazy page allocation code. */
134/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
135
136/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
137 * Enables real write monitoring of pages, i.e. mapping them read-only and
138 * only making them writable when getting a write access #PF. */
139#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
140
141/** @} */
142
143
144/** @name PDPT and PML4 flags.
145 * These are placed in the three bits available for system programs in
146 * the PDPT and PML4 entries.
147 * @{ */
148/** The entry is a permanent one and it's must always be present.
149 * Never free such an entry. */
150#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
151/** Mapping (hypervisor allocated pagetable). */
152#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
153/** @} */
154
155/** @name Page directory flags.
156 * These are placed in the three bits available for system programs in
157 * the page directory entries.
158 * @{ */
159/** Mapping (hypervisor allocated pagetable). */
160#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
161/** Made read-only to facilitate dirty bit tracking. */
162#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
163/** @} */
164
165/** @name Page flags.
166 * These are placed in the three bits available for system programs in
167 * the page entries.
168 * @{ */
169/** Made read-only to facilitate dirty bit tracking. */
170#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
171
172#ifndef PGM_PTFLAGS_CSAM_VALIDATED
173/** Scanned and approved by CSAM (tm).
174 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
175 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
176#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
177#endif
178
179/** @} */
180
181/** @name Defines used to indicate the shadow and guest paging in the templates.
182 * @{ */
183#define PGM_TYPE_REAL 1
184#define PGM_TYPE_PROT 2
185#define PGM_TYPE_32BIT 3
186#define PGM_TYPE_PAE 4
187#define PGM_TYPE_AMD64 5
188#define PGM_TYPE_NESTED 6
189#define PGM_TYPE_EPT 7
190#define PGM_TYPE_MAX PGM_TYPE_EPT
191/** @} */
192
193/** Macro for checking if the guest is using paging.
194 * @param uGstType PGM_TYPE_*
195 * @param uShwType PGM_TYPE_*
196 * @remark ASSUMES certain order of the PGM_TYPE_* values.
197 */
198#define PGM_WITH_PAGING(uGstType, uShwType) \
199 ( (uGstType) >= PGM_TYPE_32BIT \
200 && (uShwType) != PGM_TYPE_NESTED \
201 && (uShwType) != PGM_TYPE_EPT)
202
203/** Macro for checking if the guest supports the NX bit.
204 * @param uGstType PGM_TYPE_*
205 * @param uShwType PGM_TYPE_*
206 * @remark ASSUMES certain order of the PGM_TYPE_* values.
207 */
208#define PGM_WITH_NX(uGstType, uShwType) \
209 ( (uGstType) >= PGM_TYPE_PAE \
210 && (uShwType) != PGM_TYPE_NESTED \
211 && (uShwType) != PGM_TYPE_EPT)
212
213
214/** @def PGM_HCPHYS_2_PTR
215 * Maps a HC physical page pool address to a virtual address.
216 *
217 * @returns VBox status code.
218 * @param pVM The VM handle.
219 * @param HCPhys The HC physical address to map to a virtual one.
220 * @param ppv Where to store the virtual address. No need to cast this.
221 *
222 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
223 * small page window employeed by that function. Be careful.
224 * @remark There is no need to assert on the result.
225 */
226#ifdef IN_RC
227# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
228 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
229#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
230# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
231 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
232#else
233# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
234 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
235#endif
236
237/** @def PGM_HCPHYS_2_PTR_BY_PGM
238 * Maps a HC physical page pool address to a virtual address.
239 *
240 * @returns VBox status code.
241 * @param pPGM The PGM instance data.
242 * @param HCPhys The HC physical address to map to a virtual one.
243 * @param ppv Where to store the virtual address. No need to cast this.
244 *
245 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
246 * small page window employeed by that function. Be careful.
247 * @remark There is no need to assert on the result.
248 */
249#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
250# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
251 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
252#else
253# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
254 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
255#endif
256
257/** @def PGM_GCPHYS_2_PTR
258 * Maps a GC physical page address to a virtual address.
259 *
260 * @returns VBox status code.
261 * @param pVM The VM handle.
262 * @param GCPhys The GC physical address to map to a virtual one.
263 * @param ppv Where to store the virtual address. No need to cast this.
264 *
265 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
266 * small page window employeed by that function. Be careful.
267 * @remark There is no need to assert on the result.
268 */
269#ifdef IN_RC
270# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
271 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
272#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
273# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
274 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
275#else
276# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
277 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
278#endif
279
280/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
281 * Maps a GC physical page address to a virtual address.
282 *
283 * @returns VBox status code.
284 * @param pPGM Pointer to the PGM instance data.
285 * @param GCPhys The GC physical address to map to a virtual one.
286 * @param ppv Where to store the virtual address. No need to cast this.
287 *
288 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
289 * small page window employeed by that function. Be careful.
290 * @remark There is no need to assert on the result.
291 */
292#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
293# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
294 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
295#else
296# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
297 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
298#endif
299
300/** @def PGM_GCPHYS_2_PTR_EX
301 * Maps a unaligned GC physical page address to a virtual address.
302 *
303 * @returns VBox status code.
304 * @param pVM The VM handle.
305 * @param GCPhys The GC physical address to map to a virtual one.
306 * @param ppv Where to store the virtual address. No need to cast this.
307 *
308 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
309 * small page window employeed by that function. Be careful.
310 * @remark There is no need to assert on the result.
311 */
312#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
315#else
316# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
317 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
318#endif
319
320/** @def PGM_INVL_PG
321 * Invalidates a page.
322 *
323 * @param pVCpu The VMCPU handle.
324 * @param GCVirt The virtual address of the page to invalidate.
325 */
326#ifdef IN_RC
327# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
328#elif defined(IN_RING0)
329# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
330#else
331# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
332#endif
333
334/** @def PGM_INVL_PG_ALL_VCPU
335 * Invalidates a page on all VCPUs
336 *
337 * @param pVM The VM handle.
338 * @param GCVirt The virtual address of the page to invalidate.
339 */
340#ifdef IN_RC
341# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
342#elif defined(IN_RING0)
343# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
344#else
345# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
346#endif
347
348/** @def PGM_INVL_BIG_PG
349 * Invalidates a 4MB page directory entry.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address within the page directory to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
356#elif defined(IN_RING0)
357# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
358#else
359# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
360#endif
361
362/** @def PGM_INVL_VCPU_TLBS()
363 * Invalidates the TLBs of the specified VCPU
364 *
365 * @param pVCpu The VMCPU handle.
366 */
367#ifdef IN_RC
368# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
369#elif defined(IN_RING0)
370# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
371#else
372# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
373#endif
374
375/** @def PGM_INVL_ALL_VCPU_TLBS()
376 * Invalidates the TLBs of all VCPUs
377 *
378 * @param pVM The VM handle.
379 */
380#ifdef IN_RC
381# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
382#elif defined(IN_RING0)
383# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
384#else
385# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
386#endif
387
388/** Size of the GCPtrConflict array in PGMMAPPING.
389 * @remarks Must be a power of two. */
390#define PGMMAPPING_CONFLICT_MAX 8
391
392/**
393 * Structure for tracking GC Mappings.
394 *
395 * This structure is used by linked list in both GC and HC.
396 */
397typedef struct PGMMAPPING
398{
399 /** Pointer to next entry. */
400 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
401 /** Pointer to next entry. */
402 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
403 /** Pointer to next entry. */
404 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
405 /** Indicate whether this entry is finalized. */
406 bool fFinalized;
407 /** Start Virtual address. */
408 RTGCPTR GCPtr;
409 /** Last Virtual address (inclusive). */
410 RTGCPTR GCPtrLast;
411 /** Range size (bytes). */
412 RTGCPTR cb;
413 /** Pointer to relocation callback function. */
414 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
415 /** User argument to the callback. */
416 R3PTRTYPE(void *) pvUser;
417 /** Mapping description / name. For easing debugging. */
418 R3PTRTYPE(const char *) pszDesc;
419 /** Last 8 addresses that caused conflicts. */
420 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
421 /** Number of conflicts for this hypervisor mapping. */
422 uint32_t cConflicts;
423 /** Number of page tables. */
424 uint32_t cPTs;
425
426 /** Array of page table mapping data. Each entry
427 * describes one page table. The array can be longer
428 * than the declared length.
429 */
430 struct
431 {
432 /** The HC physical address of the page table. */
433 RTHCPHYS HCPhysPT;
434 /** The HC physical address of the first PAE page table. */
435 RTHCPHYS HCPhysPaePT0;
436 /** The HC physical address of the second PAE page table. */
437 RTHCPHYS HCPhysPaePT1;
438 /** The HC virtual address of the 32-bit page table. */
439 R3PTRTYPE(PX86PT) pPTR3;
440 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
441 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
442 /** The RC virtual address of the 32-bit page table. */
443 RCPTRTYPE(PX86PT) pPTRC;
444 /** The RC virtual address of the two PAE page table. */
445 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
446 /** The R0 virtual address of the 32-bit page table. */
447 R0PTRTYPE(PX86PT) pPTR0;
448 /** The R0 virtual address of the two PAE page table. */
449 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
450 } aPTs[1];
451} PGMMAPPING;
452/** Pointer to structure for tracking GC Mappings. */
453typedef struct PGMMAPPING *PPGMMAPPING;
454
455
456/**
457 * Physical page access handler structure.
458 *
459 * This is used to keep track of physical address ranges
460 * which are being monitored in some kind of way.
461 */
462typedef struct PGMPHYSHANDLER
463{
464 AVLROGCPHYSNODECORE Core;
465 /** Access type. */
466 PGMPHYSHANDLERTYPE enmType;
467 /** Number of pages to update. */
468 uint32_t cPages;
469 /** Pointer to R3 callback function. */
470 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
471 /** User argument for R3 handlers. */
472 R3PTRTYPE(void *) pvUserR3;
473 /** Pointer to R0 callback function. */
474 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
475 /** User argument for R0 handlers. */
476 R0PTRTYPE(void *) pvUserR0;
477 /** Pointer to RC callback function. */
478 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
479 /** User argument for RC handlers. */
480 RCPTRTYPE(void *) pvUserRC;
481 /** Description / Name. For easing debugging. */
482 R3PTRTYPE(const char *) pszDesc;
483#ifdef VBOX_WITH_STATISTICS
484 /** Profiling of this handler. */
485 STAMPROFILE Stat;
486#endif
487} PGMPHYSHANDLER;
488/** Pointer to a physical page access handler structure. */
489typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
490
491
492/**
493 * Cache node for the physical addresses covered by a virtual handler.
494 */
495typedef struct PGMPHYS2VIRTHANDLER
496{
497 /** Core node for the tree based on physical ranges. */
498 AVLROGCPHYSNODECORE Core;
499 /** Offset from this struct to the PGMVIRTHANDLER structure. */
500 int32_t offVirtHandler;
501 /** Offset of the next alias relative to this one.
502 * Bit 0 is used for indicating whether we're in the tree.
503 * Bit 1 is used for indicating that we're the head node.
504 */
505 int32_t offNextAlias;
506} PGMPHYS2VIRTHANDLER;
507/** Pointer to a phys to virtual handler structure. */
508typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
509
510/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
511 * node is in the tree. */
512#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
513/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
514 * node is in the head of an alias chain.
515 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
516#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
517/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
518#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
519
520
521/**
522 * Virtual page access handler structure.
523 *
524 * This is used to keep track of virtual address ranges
525 * which are being monitored in some kind of way.
526 */
527typedef struct PGMVIRTHANDLER
528{
529 /** Core node for the tree based on virtual ranges. */
530 AVLROGCPTRNODECORE Core;
531 /** Size of the range (in bytes). */
532 RTGCPTR cb;
533 /** Number of cache pages. */
534 uint32_t cPages;
535 /** Access type. */
536 PGMVIRTHANDLERTYPE enmType;
537 /** Pointer to the RC callback function. */
538 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
539#if HC_ARCH_BITS == 64
540 RTRCPTR padding;
541#endif
542 /** Pointer to the R3 callback function for invalidation. */
543 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
544 /** Pointer to the R3 callback function. */
545 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
546 /** Description / Name. For easing debugging. */
547 R3PTRTYPE(const char *) pszDesc;
548#ifdef VBOX_WITH_STATISTICS
549 /** Profiling of this handler. */
550 STAMPROFILE Stat;
551#endif
552 /** Array of cached physical addresses for the monitored ranged. */
553 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
554} PGMVIRTHANDLER;
555/** Pointer to a virtual page access handler structure. */
556typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
557
558
559/**
560 * Page type.
561 *
562 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
563 * @remarks This is used in the saved state, so changes to it requires bumping
564 * the saved state version.
565 * @todo So, convert to \#defines!
566 */
567typedef enum PGMPAGETYPE
568{
569 /** The usual invalid zero entry. */
570 PGMPAGETYPE_INVALID = 0,
571 /** RAM page. (RWX) */
572 PGMPAGETYPE_RAM,
573 /** MMIO2 page. (RWX) */
574 PGMPAGETYPE_MMIO2,
575 /** MMIO2 page aliased over an MMIO page. (RWX)
576 * See PGMHandlerPhysicalPageAlias(). */
577 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
578 /** Shadowed ROM. (RWX) */
579 PGMPAGETYPE_ROM_SHADOW,
580 /** ROM page. (R-X) */
581 PGMPAGETYPE_ROM,
582 /** MMIO page. (---) */
583 PGMPAGETYPE_MMIO,
584 /** End of valid entries. */
585 PGMPAGETYPE_END
586} PGMPAGETYPE;
587AssertCompile(PGMPAGETYPE_END <= 7);
588
589/** @name Page type predicates.
590 * @{ */
591#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
592#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
593#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
594#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
595#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
596/** @} */
597
598
599/**
600 * A Physical Guest Page tracking structure.
601 *
602 * The format of this structure is complicated because we have to fit a lot
603 * of information into as few bits as possible. The format is also subject
604 * to change (there is one comming up soon). Which means that for we'll be
605 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
606 * accesses to the structure.
607 */
608typedef struct PGMPAGE
609{
610 /** The physical address and the Page ID. */
611 RTHCPHYS HCPhysAndPageID;
612 /** Combination of:
613 * - [0-7]: u2HandlerPhysStateY - the physical handler state
614 * (PGM_PAGE_HNDL_PHYS_STATE_*).
615 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
616 * (PGM_PAGE_HNDL_VIRT_STATE_*).
617 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
618 * - [15]: fWrittenToY - flag indicating that a write monitored page was
619 * written to when set.
620 * - [10-13]: 4 unused bits.
621 * @remarks Warning! All accesses to the bits are hardcoded.
622 *
623 * @todo Change this to a union with both bitfields, u8 and u accessors.
624 * That'll help deal with some of the hardcoded accesses.
625 *
626 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
627 * will make it possible to turn some of the 16-bit accesses into
628 * 32-bit ones, which may be efficient (stalls).
629 */
630 RTUINT16U u16MiscY;
631 /** The page state.
632 * Only 3 bits are really needed for this. */
633 uint16_t uStateY : 3;
634 /** The page type (PGMPAGETYPE).
635 * Only 3 bits are really needed for this. */
636 uint16_t uTypeY : 3;
637 /** PTE index for usage tracking (page pool). */
638 uint16_t uPteIdx : 10;
639 /** Usage tracking (page pool). */
640 uint16_t u16TrackingY;
641 /** The number of read locks on this page. */
642 uint8_t cReadLocksY;
643 /** The number of write locks on this page. */
644 uint8_t cWriteLocksY;
645} PGMPAGE;
646AssertCompileSize(PGMPAGE, 16);
647/** Pointer to a physical guest page. */
648typedef PGMPAGE *PPGMPAGE;
649/** Pointer to a const physical guest page. */
650typedef const PGMPAGE *PCPGMPAGE;
651/** Pointer to a physical guest page pointer. */
652typedef PPGMPAGE *PPPGMPAGE;
653
654
655/**
656 * Clears the page structure.
657 * @param pPage Pointer to the physical guest page tracking structure.
658 */
659#define PGM_PAGE_CLEAR(pPage) \
660 do { \
661 (pPage)->HCPhysAndPageID = 0; \
662 (pPage)->uStateY = 0; \
663 (pPage)->uTypeY = 0; \
664 (pPage)->uPteIdx = 0; \
665 (pPage)->u16MiscY.u = 0; \
666 (pPage)->u16TrackingY = 0; \
667 (pPage)->cReadLocksY = 0; \
668 (pPage)->cWriteLocksY = 0; \
669 } while (0)
670
671/**
672 * Initializes the page structure.
673 * @param pPage Pointer to the physical guest page tracking structure.
674 */
675#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
676 do { \
677 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
678 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
679 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
680 (pPage)->uStateY = (_uState); \
681 (pPage)->uTypeY = (_uType); \
682 (pPage)->uPteIdx = 0; \
683 (pPage)->u16MiscY.u = 0; \
684 (pPage)->u16TrackingY = 0; \
685 (pPage)->cReadLocksY = 0; \
686 (pPage)->cWriteLocksY = 0; \
687 } while (0)
688
689/**
690 * Initializes the page structure of a ZERO page.
691 * @param pPage Pointer to the physical guest page tracking structure.
692 * @param pVM The VM handle (for getting the zero page address).
693 * @param uType The page type (PGMPAGETYPE).
694 */
695#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
696 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
697
698
699/** @name The Page state, PGMPAGE::uStateY.
700 * @{ */
701/** The zero page.
702 * This is a per-VM page that's never ever mapped writable. */
703#define PGM_PAGE_STATE_ZERO 0
704/** A allocated page.
705 * This is a per-VM page allocated from the page pool (or wherever
706 * we get MMIO2 pages from if the type is MMIO2).
707 */
708#define PGM_PAGE_STATE_ALLOCATED 1
709/** A allocated page that's being monitored for writes.
710 * The shadow page table mappings are read-only. When a write occurs, the
711 * fWrittenTo member is set, the page remapped as read-write and the state
712 * moved back to allocated. */
713#define PGM_PAGE_STATE_WRITE_MONITORED 2
714/** The page is shared, aka. copy-on-write.
715 * This is a page that's shared with other VMs. */
716#define PGM_PAGE_STATE_SHARED 3
717/** The page is ballooned, so no longer available for this VM. */
718#define PGM_PAGE_STATE_BALLOONED 4
719/** @} */
720
721
722/**
723 * Gets the page state.
724 * @returns page state (PGM_PAGE_STATE_*).
725 * @param pPage Pointer to the physical guest page tracking structure.
726 */
727#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
728
729/**
730 * Sets the page state.
731 * @param pPage Pointer to the physical guest page tracking structure.
732 * @param _uState The new page state.
733 */
734#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
735
736
737/**
738 * Gets the host physical address of the guest page.
739 * @returns host physical address (RTHCPHYS).
740 * @param pPage Pointer to the physical guest page tracking structure.
741 */
742#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
743
744/**
745 * Sets the host physical address of the guest page.
746 * @param pPage Pointer to the physical guest page tracking structure.
747 * @param _HCPhys The new host physical address.
748 */
749#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
750 do { \
751 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
752 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
753 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
754 | (SetHCPhysTmp << (28-12)); \
755 } while (0)
756
757/**
758 * Get the Page ID.
759 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
760 * @param pPage Pointer to the physical guest page tracking structure.
761 */
762#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
763
764/**
765 * Sets the Page ID.
766 * @param pPage Pointer to the physical guest page tracking structure.
767 */
768#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
769 do { \
770 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
771 | ((_idPage) & UINT32_C(0x0fffffff)); \
772 } while (0)
773
774/**
775 * Get the Chunk ID.
776 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
777 * @param pPage Pointer to the physical guest page tracking structure.
778 */
779#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
780
781/**
782 * Get the index of the page within the allocation chunk.
783 * @returns The page index.
784 * @param pPage Pointer to the physical guest page tracking structure.
785 */
786#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
787
788/**
789 * Gets the page type.
790 * @returns The page type.
791 * @param pPage Pointer to the physical guest page tracking structure.
792 */
793#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
794
795/**
796 * Sets the page type.
797 * @param pPage Pointer to the physical guest page tracking structure.
798 * @param _enmType The new page type (PGMPAGETYPE).
799 */
800#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
801
802/**
803 * Gets the page table index
804 * @returns The page table index.
805 * @param pPage Pointer to the physical guest page tracking structure.
806 */
807#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
808
809/**
810 * Sets the page table index
811 * @param pPage Pointer to the physical guest page tracking structure.
812 * @param iPte New page table index.
813 */
814#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
815
816/**
817 * Checks if the page is marked for MMIO.
818 * @returns true/false.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
822
823/**
824 * Checks if the page is backed by the ZERO page.
825 * @returns true/false.
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
829
830/**
831 * Checks if the page is backed by a SHARED page.
832 * @returns true/false.
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
836
837/**
838 * Checks if the page is ballooned.
839 * @returns true/false.
840 * @param pPage Pointer to the physical guest page tracking structure.
841 */
842#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
843
844/**
845 * Marks the page as written to (for GMM change monitoring).
846 * @param pPage Pointer to the physical guest page tracking structure.
847 */
848#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
849
850/**
851 * Clears the written-to indicator.
852 * @param pPage Pointer to the physical guest page tracking structure.
853 */
854#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
855
856/**
857 * Checks if the page was marked as written-to.
858 * @returns true/false.
859 * @param pPage Pointer to the physical guest page tracking structure.
860 */
861#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
862
863/** @name PT usage values (PGMPAGE::u2PDEType).
864 *
865 * @{ */
866/** Either as a PT or PDE. */
867#define PGM_PAGE_PDE_TYPE_DONTCARE 0
868/** Must use a page table to map the range. */
869#define PGM_PAGE_PDE_TYPE_PT 1
870/** Can use a page directory entry to map the continous range. */
871#define PGM_PAGE_PDE_TYPE_PDE 2
872/** Can use a page directory entry to map the continous range - temporarily disabled (by page monitoring). */
873#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
874/** @} */
875
876/**
877 * Set the PDE type of the page
878 * @param pPage Pointer to the physical guest page tracking structure.
879 * @param uType PGM_PAGE_PDE_TYPE_*
880 */
881#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
882 do { \
883 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
884 | (((uType) & UINT8_C(0x03)) << 5); \
885 } while (0)
886
887/**
888 * Checks if the page was marked being part of a large page
889 * @returns true/false.
890 * @param pPage Pointer to the physical guest page tracking structure.
891 */
892#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
893
894/** Enabled optimized access handler tests.
895 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
896 * layout. When enabled, the compiler should normally generate more compact
897 * code.
898 */
899#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
900
901/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
902 *
903 * @remarks The values are assigned in order of priority, so we can calculate
904 * the correct state for a page with different handlers installed.
905 * @{ */
906/** No handler installed. */
907#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
908/** Monitoring is temporarily disabled. */
909#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
910/** Write access is monitored. */
911#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
912/** All access is monitored. */
913#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
914/** @} */
915
916/**
917 * Gets the physical access handler state of a page.
918 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
919 * @param pPage Pointer to the physical guest page tracking structure.
920 */
921#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
922 ( (pPage)->u16MiscY.au8[0] )
923
924/**
925 * Sets the physical access handler state of a page.
926 * @param pPage Pointer to the physical guest page tracking structure.
927 * @param _uState The new state value.
928 */
929#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
930 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
931
932/**
933 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
934 * @returns true/false
935 * @param pPage Pointer to the physical guest page tracking structure.
936 */
937#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
938 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
939
940/**
941 * Checks if the page has any active physical access handlers.
942 * @returns true/false
943 * @param pPage Pointer to the physical guest page tracking structure.
944 */
945#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
946 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
947
948
949/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
950 *
951 * @remarks The values are assigned in order of priority, so we can calculate
952 * the correct state for a page with different handlers installed.
953 * @{ */
954/** No handler installed. */
955#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
956/* 1 is reserved so the lineup is identical with the physical ones. */
957/** Write access is monitored. */
958#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
959/** All access is monitored. */
960#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
961/** @} */
962
963/**
964 * Gets the virtual access handler state of a page.
965 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
966 * @param pPage Pointer to the physical guest page tracking structure.
967 */
968#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
969
970/**
971 * Sets the virtual access handler state of a page.
972 * @param pPage Pointer to the physical guest page tracking structure.
973 * @param _uState The new state value.
974 */
975#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
976 do { \
977 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
978 | ((_uState) & UINT8_C(0x03)); \
979 } while (0)
980
981/**
982 * Checks if the page has any virtual access handlers.
983 * @returns true/false
984 * @param pPage Pointer to the physical guest page tracking structure.
985 */
986#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
987 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
988
989/**
990 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
991 * virtual handlers.
992 * @returns true/false
993 * @param pPage Pointer to the physical guest page tracking structure.
994 */
995#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
996 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
997
998
999/**
1000 * Checks if the page has any access handlers, including temporarily disabled ones.
1001 * @returns true/false
1002 * @param pPage Pointer to the physical guest page tracking structure.
1003 */
1004#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1005# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1006 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1007#else
1008# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1009 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1010 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1011#endif
1012
1013/**
1014 * Checks if the page has any active access handlers.
1015 * @returns true/false
1016 * @param pPage Pointer to the physical guest page tracking structure.
1017 */
1018#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1019# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1020 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1021#else
1022# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1023 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1024 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1025#endif
1026
1027/**
1028 * Checks if the page has any active access handlers catching all accesses.
1029 * @returns true/false
1030 * @param pPage Pointer to the physical guest page tracking structure.
1031 */
1032#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1033# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1034 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1035 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1036#else
1037# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1038 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1039 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1040#endif
1041
1042
1043/** @def PGM_PAGE_GET_TRACKING
1044 * Gets the packed shadow page pool tracking data associated with a guest page.
1045 * @returns uint16_t containing the data.
1046 * @param pPage Pointer to the physical guest page tracking structure.
1047 */
1048#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1049
1050/** @def PGM_PAGE_SET_TRACKING
1051 * Sets the packed shadow page pool tracking data associated with a guest page.
1052 * @param pPage Pointer to the physical guest page tracking structure.
1053 * @param u16TrackingData The tracking data to store.
1054 */
1055#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1056 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1057
1058/** @def PGM_PAGE_GET_TD_CREFS
1059 * Gets the @a cRefs tracking data member.
1060 * @returns cRefs.
1061 * @param pPage Pointer to the physical guest page tracking structure.
1062 */
1063#define PGM_PAGE_GET_TD_CREFS(pPage) \
1064 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1065
1066/** @def PGM_PAGE_GET_TD_IDX
1067 * Gets the @a idx tracking data member.
1068 * @returns idx.
1069 * @param pPage Pointer to the physical guest page tracking structure.
1070 */
1071#define PGM_PAGE_GET_TD_IDX(pPage) \
1072 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1073
1074
1075/** Max number of locks on a page. */
1076#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1077
1078/** Get the read lock count.
1079 * @returns count.
1080 * @param pPage Pointer to the physical guest page tracking structure.
1081 */
1082#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1083
1084/** Get the write lock count.
1085 * @returns count.
1086 * @param pPage Pointer to the physical guest page tracking structure.
1087 */
1088#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1089
1090/** Decrement the read lock counter.
1091 * @param pPage Pointer to the physical guest page tracking structure.
1092 */
1093#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1094
1095/** Decrement the write lock counter.
1096 * @param pPage Pointer to the physical guest page tracking structure.
1097 */
1098#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1099
1100/** Increment the read lock counter.
1101 * @param pPage Pointer to the physical guest page tracking structure.
1102 */
1103#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1104
1105/** Increment the write lock counter.
1106 * @param pPage Pointer to the physical guest page tracking structure.
1107 */
1108#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1109
1110
1111#if 0
1112/** Enables sanity checking of write monitoring using CRC-32. */
1113# define PGMLIVESAVERAMPAGE_WITH_CRC32
1114#endif
1115
1116/**
1117 * Per page live save tracking data.
1118 */
1119typedef struct PGMLIVESAVERAMPAGE
1120{
1121 /** Number of times it has been dirtied. */
1122 uint32_t cDirtied : 24;
1123 /** Whether it is currently dirty. */
1124 uint32_t fDirty : 1;
1125 /** Ignore the page.
1126 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1127 * deal with these after pausing the VM and DevPCI have said it bit about
1128 * remappings. */
1129 uint32_t fIgnore : 1;
1130 /** Was a ZERO page last time around. */
1131 uint32_t fZero : 1;
1132 /** Was a SHARED page last time around. */
1133 uint32_t fShared : 1;
1134 /** Whether the page is/was write monitored in a previous pass. */
1135 uint32_t fWriteMonitored : 1;
1136 /** Whether the page is/was write monitored earlier in this pass. */
1137 uint32_t fWriteMonitoredJustNow : 1;
1138 /** Bits reserved for future use. */
1139 uint32_t u2Reserved : 2;
1140#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1141 /** CRC-32 for the page. This is for internal consistency checks. */
1142 uint32_t u32Crc;
1143#endif
1144} PGMLIVESAVERAMPAGE;
1145#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1146AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1147#else
1148AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1149#endif
1150/** Pointer to the per page live save tracking data. */
1151typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1152
1153/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1154#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1155
1156
1157/**
1158 * Ram range for GC Phys to HC Phys conversion.
1159 *
1160 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1161 * conversions too, but we'll let MM handle that for now.
1162 *
1163 * This structure is used by linked lists in both GC and HC.
1164 */
1165typedef struct PGMRAMRANGE
1166{
1167 /** Start of the range. Page aligned. */
1168 RTGCPHYS GCPhys;
1169 /** Size of the range. (Page aligned of course). */
1170 RTGCPHYS cb;
1171 /** Pointer to the next RAM range - for R3. */
1172 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1173 /** Pointer to the next RAM range - for R0. */
1174 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1175 /** Pointer to the next RAM range - for RC. */
1176 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1177 /** PGM_RAM_RANGE_FLAGS_* flags. */
1178 uint32_t fFlags;
1179 /** Last address in the range (inclusive). Page aligned (-1). */
1180 RTGCPHYS GCPhysLast;
1181 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1182 R3PTRTYPE(void *) pvR3;
1183 /** Live save per page tracking data. */
1184 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1185 /** The range description. */
1186 R3PTRTYPE(const char *) pszDesc;
1187 /** Pointer to self - R0 pointer. */
1188 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1189 /** Pointer to self - RC pointer. */
1190 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1191 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1192 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1193 /** Array of physical guest page tracking structures. */
1194 PGMPAGE aPages[1];
1195} PGMRAMRANGE;
1196/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1197typedef PGMRAMRANGE *PPGMRAMRANGE;
1198
1199/** @name PGMRAMRANGE::fFlags
1200 * @{ */
1201/** The RAM range is floating around as an independent guest mapping. */
1202#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1203/** Ad hoc RAM range for an ROM mapping. */
1204#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1205/** Ad hoc RAM range for an MMIO mapping. */
1206#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1207/** Ad hoc RAM range for an MMIO2 mapping. */
1208#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1209/** @} */
1210
1211/** Tests if a RAM range is an ad hoc one or not.
1212 * @returns true/false.
1213 * @param pRam The RAM range.
1214 */
1215#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1216 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1217
1218
1219/**
1220 * Per page tracking structure for ROM image.
1221 *
1222 * A ROM image may have a shadow page, in which case we may have two pages
1223 * backing it. This structure contains the PGMPAGE for both while
1224 * PGMRAMRANGE have a copy of the active one. It is important that these
1225 * aren't out of sync in any regard other than page pool tracking data.
1226 */
1227typedef struct PGMROMPAGE
1228{
1229 /** The page structure for the virgin ROM page. */
1230 PGMPAGE Virgin;
1231 /** The page structure for the shadow RAM page. */
1232 PGMPAGE Shadow;
1233 /** The current protection setting. */
1234 PGMROMPROT enmProt;
1235 /** Live save status information. Makes use of unused alignment space. */
1236 struct
1237 {
1238 /** The previous protection value. */
1239 uint8_t u8Prot;
1240 /** Written to flag set by the handler. */
1241 bool fWrittenTo;
1242 /** Whether the shadow page is dirty or not. */
1243 bool fDirty;
1244 /** Whether it was dirtied in the recently. */
1245 bool fDirtiedRecently;
1246 } LiveSave;
1247} PGMROMPAGE;
1248AssertCompileSizeAlignment(PGMROMPAGE, 8);
1249/** Pointer to a ROM page tracking structure. */
1250typedef PGMROMPAGE *PPGMROMPAGE;
1251
1252
1253/**
1254 * A registered ROM image.
1255 *
1256 * This is needed to keep track of ROM image since they generally intrude
1257 * into a PGMRAMRANGE. It also keeps track of additional info like the
1258 * two page sets (read-only virgin and read-write shadow), the current
1259 * state of each page.
1260 *
1261 * Because access handlers cannot easily be executed in a different
1262 * context, the ROM ranges needs to be accessible and in all contexts.
1263 */
1264typedef struct PGMROMRANGE
1265{
1266 /** Pointer to the next range - R3. */
1267 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1268 /** Pointer to the next range - R0. */
1269 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1270 /** Pointer to the next range - RC. */
1271 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1272 /** Pointer alignment */
1273 RTRCPTR RCPtrAlignment;
1274 /** Address of the range. */
1275 RTGCPHYS GCPhys;
1276 /** Address of the last byte in the range. */
1277 RTGCPHYS GCPhysLast;
1278 /** Size of the range. */
1279 RTGCPHYS cb;
1280 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1281 uint32_t fFlags;
1282 /** The saved state range ID. */
1283 uint8_t idSavedState;
1284 /** Alignment padding. */
1285 uint8_t au8Alignment[3];
1286 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1287 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 6 : 2];
1288 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1289 * This is used for strictness checks. */
1290 R3PTRTYPE(const void *) pvOriginal;
1291 /** The ROM description. */
1292 R3PTRTYPE(const char *) pszDesc;
1293 /** The per page tracking structures. */
1294 PGMROMPAGE aPages[1];
1295} PGMROMRANGE;
1296/** Pointer to a ROM range. */
1297typedef PGMROMRANGE *PPGMROMRANGE;
1298
1299
1300/**
1301 * Live save per page data for an MMIO2 page.
1302 *
1303 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1304 * of MMIO2 pages. The current approach is using some optimisitic SHA-1 +
1305 * CRC-32 for detecting changes as well as special handling of zero pages. This
1306 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1307 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1308 * because of speed (2.5x and 6x slower).)
1309 *
1310 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1311 * save but normally is disabled. Since we can write monitore guest
1312 * accesses on our own, we only need this for host accesses. Shouldn't be
1313 * too difficult for DevVGA, VMMDev might be doable, the planned
1314 * networking fun will be fun since it involves ring-0.
1315 */
1316typedef struct PGMLIVESAVEMMIO2PAGE
1317{
1318 /** Set if the page is considered dirty. */
1319 bool fDirty;
1320 /** The number of scans this page has remained unchanged for.
1321 * Only updated for dirty pages. */
1322 uint8_t cUnchangedScans;
1323 /** Whether this page was zero at the last scan. */
1324 bool fZero;
1325 /** Alignment padding. */
1326 bool fReserved;
1327 /** CRC-32 for the first half of the page.
1328 * This is used together with u32CrcH2 to quickly detect changes in the page
1329 * during the non-final passes. */
1330 uint32_t u32CrcH1;
1331 /** CRC-32 for the second half of the page. */
1332 uint32_t u32CrcH2;
1333 /** SHA-1 for the saved page.
1334 * This is used in the final pass to skip pages without changes. */
1335 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1336} PGMLIVESAVEMMIO2PAGE;
1337/** Pointer to a live save status data for an MMIO2 page. */
1338typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1339
1340/**
1341 * A registered MMIO2 (= Device RAM) range.
1342 *
1343 * There are a few reason why we need to keep track of these
1344 * registrations. One of them is the deregistration & cleanup stuff,
1345 * while another is that the PGMRAMRANGE associated with such a region may
1346 * have to be removed from the ram range list.
1347 *
1348 * Overlapping with a RAM range has to be 100% or none at all. The pages
1349 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1350 * will be raised if a partial overlap or an overlap of ROM pages is
1351 * encountered. On an overlap we will free all the existing RAM pages and
1352 * put in the ram range pages instead.
1353 */
1354typedef struct PGMMMIO2RANGE
1355{
1356 /** The owner of the range. (a device) */
1357 PPDMDEVINSR3 pDevInsR3;
1358 /** Pointer to the ring-3 mapping of the allocation. */
1359 RTR3PTR pvR3;
1360 /** Pointer to the next range - R3. */
1361 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1362 /** Whether it's mapped or not. */
1363 bool fMapped;
1364 /** Whether it's overlapping or not. */
1365 bool fOverlapping;
1366 /** The PCI region number.
1367 * @remarks This ASSUMES that nobody will ever really need to have multiple
1368 * PCI devices with matching MMIO region numbers on a single device. */
1369 uint8_t iRegion;
1370 /** The saved state range ID. */
1371 uint8_t idSavedState;
1372 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1373 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1374 /** Live save per page tracking data. */
1375 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1376 /** The associated RAM range. */
1377 PGMRAMRANGE RamRange;
1378} PGMMMIO2RANGE;
1379/** Pointer to a MMIO2 range. */
1380typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1381
1382
1383
1384
1385/**
1386 * PGMPhysRead/Write cache entry
1387 */
1388typedef struct PGMPHYSCACHEENTRY
1389{
1390 /** R3 pointer to physical page. */
1391 R3PTRTYPE(uint8_t *) pbR3;
1392 /** GC Physical address for cache entry */
1393 RTGCPHYS GCPhys;
1394#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1395 RTGCPHYS u32Padding0; /**< alignment padding. */
1396#endif
1397} PGMPHYSCACHEENTRY;
1398
1399/**
1400 * PGMPhysRead/Write cache to reduce REM memory access overhead
1401 */
1402typedef struct PGMPHYSCACHE
1403{
1404 /** Bitmap of valid cache entries */
1405 uint64_t aEntries;
1406 /** Cache entries */
1407 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1408} PGMPHYSCACHE;
1409
1410
1411/** Pointer to an allocation chunk ring-3 mapping. */
1412typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1413/** Pointer to an allocation chunk ring-3 mapping pointer. */
1414typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1415
1416/**
1417 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1418 *
1419 * The primary tree (Core) uses the chunk id as key.
1420 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1421 */
1422typedef struct PGMCHUNKR3MAP
1423{
1424 /** The key is the chunk id. */
1425 AVLU32NODECORE Core;
1426 /** The key is the ageing sequence number. */
1427 AVLLU32NODECORE AgeCore;
1428 /** The current age thingy. */
1429 uint32_t iAge;
1430 /** The current reference count. */
1431 uint32_t volatile cRefs;
1432 /** The current permanent reference count. */
1433 uint32_t volatile cPermRefs;
1434 /** The mapping address. */
1435 void *pv;
1436} PGMCHUNKR3MAP;
1437
1438/**
1439 * Allocation chunk ring-3 mapping TLB entry.
1440 */
1441typedef struct PGMCHUNKR3MAPTLBE
1442{
1443 /** The chunk id. */
1444 uint32_t volatile idChunk;
1445#if HC_ARCH_BITS == 64
1446 uint32_t u32Padding; /**< alignment padding. */
1447#endif
1448 /** The chunk map. */
1449#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1450 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1451#else
1452 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1453#endif
1454} PGMCHUNKR3MAPTLBE;
1455/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1456typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1457
1458/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1459 * @remark Must be a power of two value. */
1460#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1461
1462/**
1463 * Allocation chunk ring-3 mapping TLB.
1464 *
1465 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1466 * At first glance this might look kinda odd since AVL trees are
1467 * supposed to give the most optimial lookup times of all trees
1468 * due to their balancing. However, take a tree with 1023 nodes
1469 * in it, that's 10 levels, meaning that most searches has to go
1470 * down 9 levels before they find what they want. This isn't fast
1471 * compared to a TLB hit. There is the factor of cache misses,
1472 * and of course the problem with trees and branch prediction.
1473 * This is why we use TLBs in front of most of the trees.
1474 *
1475 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1476 * difficult when we switch to the new inlined AVL trees (from kStuff).
1477 */
1478typedef struct PGMCHUNKR3MAPTLB
1479{
1480 /** The TLB entries. */
1481 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1482} PGMCHUNKR3MAPTLB;
1483
1484/**
1485 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1486 * @returns Chunk TLB index.
1487 * @param idChunk The Chunk ID.
1488 */
1489#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1490
1491
1492/**
1493 * Ring-3 guest page mapping TLB entry.
1494 * @remarks used in ring-0 as well at the moment.
1495 */
1496typedef struct PGMPAGER3MAPTLBE
1497{
1498 /** Address of the page. */
1499 RTGCPHYS volatile GCPhys;
1500 /** The guest page. */
1501#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1502 R3PTRTYPE(PPGMPAGE) volatile pPage;
1503#else
1504 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1505#endif
1506 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1507#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1508 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1509#else
1510 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1511#endif
1512 /** The address */
1513#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1514 R3PTRTYPE(void *) volatile pv;
1515#else
1516 R3R0PTRTYPE(void *) volatile pv;
1517#endif
1518#if HC_ARCH_BITS == 32
1519 uint32_t u32Padding; /**< alignment padding. */
1520#endif
1521} PGMPAGER3MAPTLBE;
1522/** Pointer to an entry in the HC physical TLB. */
1523typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1524
1525
1526/** The number of entries in the ring-3 guest page mapping TLB.
1527 * @remarks The value must be a power of two. */
1528#define PGM_PAGER3MAPTLB_ENTRIES 256
1529
1530/**
1531 * Ring-3 guest page mapping TLB.
1532 * @remarks used in ring-0 as well at the moment.
1533 */
1534typedef struct PGMPAGER3MAPTLB
1535{
1536 /** The TLB entries. */
1537 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1538} PGMPAGER3MAPTLB;
1539/** Pointer to the ring-3 guest page mapping TLB. */
1540typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1541
1542/**
1543 * Calculates the index of the TLB entry for the specified guest page.
1544 * @returns Physical TLB index.
1545 * @param GCPhys The guest physical address.
1546 */
1547#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1548
1549
1550/**
1551 * Mapping cache usage set entry.
1552 *
1553 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1554 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1555 * cache. If it's extended to include ring-3, well, then something will
1556 * have be changed here...
1557 */
1558typedef struct PGMMAPSETENTRY
1559{
1560 /** The mapping cache index. */
1561 uint16_t iPage;
1562 /** The number of references.
1563 * The max is UINT16_MAX - 1. */
1564 uint16_t cRefs;
1565#if HC_ARCH_BITS == 64
1566 uint32_t alignment;
1567#endif
1568 /** Pointer to the page. */
1569 RTR0PTR pvPage;
1570 /** The physical address for this entry. */
1571 RTHCPHYS HCPhys;
1572} PGMMAPSETENTRY;
1573/** Pointer to a mapping cache usage set entry. */
1574typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1575
1576/**
1577 * Mapping cache usage set.
1578 *
1579 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1580 * done during exits / traps. The set is
1581 */
1582typedef struct PGMMAPSET
1583{
1584 /** The number of occupied entries.
1585 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1586 * dynamic mappings. */
1587 uint32_t cEntries;
1588 /** The start of the current subset.
1589 * This is UINT32_MAX if no subset is currently open. */
1590 uint32_t iSubset;
1591 /** The index of the current CPU, only valid if the set is open. */
1592 int32_t iCpu;
1593 uint32_t alignment;
1594 /** The entries. */
1595 PGMMAPSETENTRY aEntries[64];
1596 /** HCPhys -> iEntry fast lookup table.
1597 * Use PGMMAPSET_HASH for hashing.
1598 * The entries may or may not be valid, check against cEntries. */
1599 uint8_t aiHashTable[128];
1600} PGMMAPSET;
1601AssertCompileSizeAlignment(PGMMAPSET, 8);
1602/** Pointer to the mapping cache set. */
1603typedef PGMMAPSET *PPGMMAPSET;
1604
1605/** PGMMAPSET::cEntries value for a closed set. */
1606#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1607
1608/** Hash function for aiHashTable. */
1609#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1610
1611/** The max fill size (strict builds). */
1612#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1613
1614
1615/** @name Context neutrual page mapper TLB.
1616 *
1617 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1618 * code is writting in a kind of context neutrual way. Time will show whether
1619 * this actually makes sense or not...
1620 *
1621 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1622 * context ends up using a global mapping cache on some platforms
1623 * (darwin).
1624 *
1625 * @{ */
1626/** @typedef PPGMPAGEMAPTLB
1627 * The page mapper TLB pointer type for the current context. */
1628/** @typedef PPGMPAGEMAPTLB
1629 * The page mapper TLB entry pointer type for the current context. */
1630/** @typedef PPGMPAGEMAPTLB
1631 * The page mapper TLB entry pointer pointer type for the current context. */
1632/** @def PGM_PAGEMAPTLB_ENTRIES
1633 * The number of TLB entries in the page mapper TLB for the current context. */
1634/** @def PGM_PAGEMAPTLB_IDX
1635 * Calculate the TLB index for a guest physical address.
1636 * @returns The TLB index.
1637 * @param GCPhys The guest physical address. */
1638/** @typedef PPGMPAGEMAP
1639 * Pointer to a page mapper unit for current context. */
1640/** @typedef PPPGMPAGEMAP
1641 * Pointer to a page mapper unit pointer for current context. */
1642#ifdef IN_RC
1643// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1644// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1645// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1646# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1647# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1648 typedef void * PPGMPAGEMAP;
1649 typedef void ** PPPGMPAGEMAP;
1650//#elif IN_RING0
1651// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1652// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1653// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1654//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1655//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1656// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1657// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1658#else
1659 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1660 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1661 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1662# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1663# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1664 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1665 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1666#endif
1667/** @} */
1668
1669
1670/** @name PGM Pool Indexes.
1671 * Aka. the unique shadow page identifier.
1672 * @{ */
1673/** NIL page pool IDX. */
1674#define NIL_PGMPOOL_IDX 0
1675/** The first normal index. */
1676#define PGMPOOL_IDX_FIRST_SPECIAL 1
1677/** Page directory (32-bit root). */
1678#define PGMPOOL_IDX_PD 1
1679/** Page Directory Pointer Table (PAE root). */
1680#define PGMPOOL_IDX_PDPT 2
1681/** AMD64 CR3 level index.*/
1682#define PGMPOOL_IDX_AMD64_CR3 3
1683/** Nested paging root.*/
1684#define PGMPOOL_IDX_NESTED_ROOT 4
1685/** The first normal index. */
1686#define PGMPOOL_IDX_FIRST 5
1687/** The last valid index. (inclusive, 14 bits) */
1688#define PGMPOOL_IDX_LAST 0x3fff
1689/** @} */
1690
1691/** The NIL index for the parent chain. */
1692#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1693#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1694
1695/**
1696 * Node in the chain linking a shadowed page to it's parent (user).
1697 */
1698#pragma pack(1)
1699typedef struct PGMPOOLUSER
1700{
1701 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1702 uint16_t iNext;
1703 /** The user page index. */
1704 uint16_t iUser;
1705 /** Index into the user table. */
1706 uint32_t iUserTable;
1707} PGMPOOLUSER, *PPGMPOOLUSER;
1708typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1709#pragma pack()
1710
1711
1712/** The NIL index for the phys ext chain. */
1713#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1714/** The NIL pte index for a phys ext chain slot. */
1715#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1716
1717/**
1718 * Node in the chain of physical cross reference extents.
1719 * @todo Calling this an 'extent' is not quite right, find a better name.
1720 * @todo find out the optimal size of the aidx array
1721 */
1722#pragma pack(1)
1723typedef struct PGMPOOLPHYSEXT
1724{
1725 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1726 uint16_t iNext;
1727 /** Alignment. */
1728 uint16_t u16Align;
1729 /** The user page index. */
1730 uint16_t aidx[3];
1731 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1732 uint16_t apte[3];
1733} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1734typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1735#pragma pack()
1736
1737
1738/**
1739 * The kind of page that's being shadowed.
1740 */
1741typedef enum PGMPOOLKIND
1742{
1743 /** The virtual invalid 0 entry. */
1744 PGMPOOLKIND_INVALID = 0,
1745 /** The entry is free (=unused). */
1746 PGMPOOLKIND_FREE,
1747
1748 /** Shw: 32-bit page table; Gst: no paging */
1749 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1750 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1751 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1752 /** Shw: 32-bit page table; Gst: 4MB page. */
1753 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1754 /** Shw: PAE page table; Gst: no paging */
1755 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1756 /** Shw: PAE page table; Gst: 32-bit page table. */
1757 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1758 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1759 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1760 /** Shw: PAE page table; Gst: PAE page table. */
1761 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1762 /** Shw: PAE page table; Gst: 2MB page. */
1763 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1764
1765 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1766 PGMPOOLKIND_32BIT_PD,
1767 /** Shw: 32-bit page directory. Gst: no paging. */
1768 PGMPOOLKIND_32BIT_PD_PHYS,
1769 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1770 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1771 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1772 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1773 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1774 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1775 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1776 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1777 /** Shw: PAE page directory; Gst: PAE page directory. */
1778 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1779 /** Shw: PAE page directory; Gst: no paging. */
1780 PGMPOOLKIND_PAE_PD_PHYS,
1781
1782 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1783 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1784 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1785 PGMPOOLKIND_PAE_PDPT,
1786 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1787 PGMPOOLKIND_PAE_PDPT_PHYS,
1788
1789 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1790 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1791 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1792 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1793 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1794 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1795 /** Shw: 64-bit page directory table; Gst: no paging */
1796 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1797
1798 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1799 PGMPOOLKIND_64BIT_PML4,
1800
1801 /** Shw: EPT page directory pointer table; Gst: no paging */
1802 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1803 /** Shw: EPT page directory table; Gst: no paging */
1804 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1805 /** Shw: EPT page table; Gst: no paging */
1806 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1807
1808 /** Shw: Root Nested paging table. */
1809 PGMPOOLKIND_ROOT_NESTED,
1810
1811 /** The last valid entry. */
1812 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1813} PGMPOOLKIND;
1814
1815/**
1816 * The access attributes of the page; only applies to big pages.
1817 */
1818typedef enum
1819{
1820 PGMPOOLACCESS_DONTCARE = 0,
1821 PGMPOOLACCESS_USER_RW,
1822 PGMPOOLACCESS_USER_R,
1823 PGMPOOLACCESS_USER_RW_NX,
1824 PGMPOOLACCESS_USER_R_NX,
1825 PGMPOOLACCESS_SUPERVISOR_RW,
1826 PGMPOOLACCESS_SUPERVISOR_R,
1827 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1828 PGMPOOLACCESS_SUPERVISOR_R_NX
1829} PGMPOOLACCESS;
1830
1831/**
1832 * The tracking data for a page in the pool.
1833 */
1834typedef struct PGMPOOLPAGE
1835{
1836 /** AVL node code with the (R3) physical address of this page. */
1837 AVLOHCPHYSNODECORE Core;
1838 /** Pointer to the R3 mapping of the page. */
1839#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1840 R3PTRTYPE(void *) pvPageR3;
1841#else
1842 R3R0PTRTYPE(void *) pvPageR3;
1843#endif
1844 /** The guest physical address. */
1845#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1846 uint32_t Alignment0;
1847#endif
1848 RTGCPHYS GCPhys;
1849
1850 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1851 RTGCPTR pvLastAccessHandlerRip;
1852 RTGCPTR pvLastAccessHandlerFault;
1853 uint64_t cLastAccessHandlerCount;
1854
1855 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1856 uint8_t enmKind;
1857 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1858 uint8_t enmAccess;
1859 /** The index of this page. */
1860 uint16_t idx;
1861 /** The next entry in the list this page currently resides in.
1862 * It's either in the free list or in the GCPhys hash. */
1863 uint16_t iNext;
1864 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1865 uint16_t iUserHead;
1866 /** The number of present entries. */
1867 uint16_t cPresent;
1868 /** The first entry in the table which is present. */
1869 uint16_t iFirstPresent;
1870 /** The number of modifications to the monitored page. */
1871 uint16_t cModifications;
1872 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1873 uint16_t iModifiedNext;
1874 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1875 uint16_t iModifiedPrev;
1876 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1877 uint16_t iMonitoredNext;
1878 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1879 uint16_t iMonitoredPrev;
1880 /** The next page in the age list. */
1881 uint16_t iAgeNext;
1882 /** The previous page in the age list. */
1883 uint16_t iAgePrev;
1884 /** Used to indicate that the page is zeroed. */
1885 bool fZeroed;
1886 /** Used to indicate that a PT has non-global entries. */
1887 bool fSeenNonGlobal;
1888 /** Used to indicate that we're monitoring writes to the guest page. */
1889 bool fMonitored;
1890 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1891 * (All pages are in the age list.) */
1892 bool fCached;
1893 /** This is used by the R3 access handlers when invoked by an async thread.
1894 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1895 bool volatile fReusedFlushPending;
1896 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1897 bool fDirty;
1898
1899 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1900 uint32_t cLocked;
1901 uint32_t idxDirty;
1902 RTGCPTR pvDirtyFault;
1903} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1904/** Pointer to a const pool page. */
1905typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1906
1907
1908/** The hash table size. */
1909# define PGMPOOL_HASH_SIZE 0x40
1910/** The hash function. */
1911# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1912
1913
1914/**
1915 * The shadow page pool instance data.
1916 *
1917 * It's all one big allocation made at init time, except for the
1918 * pages that is. The user nodes follows immediatly after the
1919 * page structures.
1920 */
1921typedef struct PGMPOOL
1922{
1923 /** The VM handle - R3 Ptr. */
1924 PVMR3 pVMR3;
1925 /** The VM handle - R0 Ptr. */
1926 PVMR0 pVMR0;
1927 /** The VM handle - RC Ptr. */
1928 PVMRC pVMRC;
1929 /** The max pool size. This includes the special IDs. */
1930 uint16_t cMaxPages;
1931 /** The current pool size. */
1932 uint16_t cCurPages;
1933 /** The head of the free page list. */
1934 uint16_t iFreeHead;
1935 /* Padding. */
1936 uint16_t u16Padding;
1937 /** Head of the chain of free user nodes. */
1938 uint16_t iUserFreeHead;
1939 /** The number of user nodes we've allocated. */
1940 uint16_t cMaxUsers;
1941 /** The number of present page table entries in the entire pool. */
1942 uint32_t cPresent;
1943 /** Pointer to the array of user nodes - RC pointer. */
1944 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1945 /** Pointer to the array of user nodes - R3 pointer. */
1946 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1947 /** Pointer to the array of user nodes - R0 pointer. */
1948 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1949 /** Head of the chain of free phys ext nodes. */
1950 uint16_t iPhysExtFreeHead;
1951 /** The number of user nodes we've allocated. */
1952 uint16_t cMaxPhysExts;
1953 /** Pointer to the array of physical xref extent - RC pointer. */
1954 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1955 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1956 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1957 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1958 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1959 /** Hash table for GCPhys addresses. */
1960 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1961 /** The head of the age list. */
1962 uint16_t iAgeHead;
1963 /** The tail of the age list. */
1964 uint16_t iAgeTail;
1965 /** Set if the cache is enabled. */
1966 bool fCacheEnabled;
1967 /** Alignment padding. */
1968 bool afPadding1[3];
1969 /** Head of the list of modified pages. */
1970 uint16_t iModifiedHead;
1971 /** The current number of modified pages. */
1972 uint16_t cModifiedPages;
1973 /** Access handler, RC. */
1974 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1975 /** Access handler, R0. */
1976 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1977 /** Access handler, R3. */
1978 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1979 /** The access handler description (R3 ptr). */
1980 R3PTRTYPE(const char *) pszAccessHandler;
1981# if HC_ARCH_BITS == 32
1982 /** Alignment padding. */
1983 uint32_t u32Padding2;
1984# endif
1985 /* Next available slot. */
1986 uint32_t idxFreeDirtyPage;
1987 /* Number of active dirty pages. */
1988 uint32_t cDirtyPages;
1989 /* Array of current dirty pgm pool page indices. */
1990 uint16_t aIdxDirtyPages[16];
1991 uint64_t aDirtyPages[16][512];
1992 /** The number of pages currently in use. */
1993 uint16_t cUsedPages;
1994#ifdef VBOX_WITH_STATISTICS
1995 /** The high water mark for cUsedPages. */
1996 uint16_t cUsedPagesHigh;
1997 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1998 /** Profiling pgmPoolAlloc(). */
1999 STAMPROFILEADV StatAlloc;
2000 /** Profiling pgmR3PoolClearDoIt(). */
2001 STAMPROFILE StatClearAll;
2002 /** Profiling pgmR3PoolReset(). */
2003 STAMPROFILE StatR3Reset;
2004 /** Profiling pgmPoolFlushPage(). */
2005 STAMPROFILE StatFlushPage;
2006 /** Profiling pgmPoolFree(). */
2007 STAMPROFILE StatFree;
2008 /** Counting explicit flushes by PGMPoolFlushPage(). */
2009 STAMCOUNTER StatForceFlushPage;
2010 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2011 STAMCOUNTER StatForceFlushDirtyPage;
2012 /** Counting flushes for reused pages. */
2013 STAMCOUNTER StatForceFlushReused;
2014 /** Profiling time spent zeroing pages. */
2015 STAMPROFILE StatZeroPage;
2016 /** Profiling of pgmPoolTrackDeref. */
2017 STAMPROFILE StatTrackDeref;
2018 /** Profiling pgmTrackFlushGCPhysPT. */
2019 STAMPROFILE StatTrackFlushGCPhysPT;
2020 /** Profiling pgmTrackFlushGCPhysPTs. */
2021 STAMPROFILE StatTrackFlushGCPhysPTs;
2022 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2023 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2024 /** Number of times we've been out of user records. */
2025 STAMCOUNTER StatTrackFreeUpOneUser;
2026 /** Nr of flushed entries. */
2027 STAMCOUNTER StatTrackFlushEntry;
2028 /** Nr of updated entries. */
2029 STAMCOUNTER StatTrackFlushEntryKeep;
2030 /** Profiling deref activity related tracking GC physical pages. */
2031 STAMPROFILE StatTrackDerefGCPhys;
2032 /** Number of linear searches for a HCPhys in the ram ranges. */
2033 STAMCOUNTER StatTrackLinearRamSearches;
2034 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2035 STAMCOUNTER StamTrackPhysExtAllocFailures;
2036 /** Profiling the RC/R0 access handler. */
2037 STAMPROFILE StatMonitorRZ;
2038 /** Times we've failed interpreting the instruction. */
2039 STAMCOUNTER StatMonitorRZEmulateInstr;
2040 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2041 STAMPROFILE StatMonitorRZFlushPage;
2042 /* Times we've detected a page table reinit. */
2043 STAMCOUNTER StatMonitorRZFlushReinit;
2044 /** Counting flushes for pages that are modified too often. */
2045 STAMCOUNTER StatMonitorRZFlushModOverflow;
2046 /** Times we've detected fork(). */
2047 STAMCOUNTER StatMonitorRZFork;
2048 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2049 STAMPROFILE StatMonitorRZHandled;
2050 /** Times we've failed interpreting a patch code instruction. */
2051 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2052 /** Times we've failed interpreting a patch code instruction during flushing. */
2053 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2054 /** The number of times we've seen rep prefixes we can't handle. */
2055 STAMCOUNTER StatMonitorRZRepPrefix;
2056 /** Profiling the REP STOSD cases we've handled. */
2057 STAMPROFILE StatMonitorRZRepStosd;
2058 /** Nr of handled PT faults. */
2059 STAMCOUNTER StatMonitorRZFaultPT;
2060 /** Nr of handled PD faults. */
2061 STAMCOUNTER StatMonitorRZFaultPD;
2062 /** Nr of handled PDPT faults. */
2063 STAMCOUNTER StatMonitorRZFaultPDPT;
2064 /** Nr of handled PML4 faults. */
2065 STAMCOUNTER StatMonitorRZFaultPML4;
2066
2067 /** Profiling the R3 access handler. */
2068 STAMPROFILE StatMonitorR3;
2069 /** Times we've failed interpreting the instruction. */
2070 STAMCOUNTER StatMonitorR3EmulateInstr;
2071 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2072 STAMPROFILE StatMonitorR3FlushPage;
2073 /* Times we've detected a page table reinit. */
2074 STAMCOUNTER StatMonitorR3FlushReinit;
2075 /** Counting flushes for pages that are modified too often. */
2076 STAMCOUNTER StatMonitorR3FlushModOverflow;
2077 /** Times we've detected fork(). */
2078 STAMCOUNTER StatMonitorR3Fork;
2079 /** Profiling the R3 access we've handled (except REP STOSD). */
2080 STAMPROFILE StatMonitorR3Handled;
2081 /** The number of times we've seen rep prefixes we can't handle. */
2082 STAMCOUNTER StatMonitorR3RepPrefix;
2083 /** Profiling the REP STOSD cases we've handled. */
2084 STAMPROFILE StatMonitorR3RepStosd;
2085 /** Nr of handled PT faults. */
2086 STAMCOUNTER StatMonitorR3FaultPT;
2087 /** Nr of handled PD faults. */
2088 STAMCOUNTER StatMonitorR3FaultPD;
2089 /** Nr of handled PDPT faults. */
2090 STAMCOUNTER StatMonitorR3FaultPDPT;
2091 /** Nr of handled PML4 faults. */
2092 STAMCOUNTER StatMonitorR3FaultPML4;
2093 /** The number of times we're called in an async thread an need to flush. */
2094 STAMCOUNTER StatMonitorR3Async;
2095 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2096 STAMCOUNTER StatResetDirtyPages;
2097 /** Times we've called pgmPoolAddDirtyPage. */
2098 STAMCOUNTER StatDirtyPage;
2099 /** Times we've had to flush duplicates for dirty page management. */
2100 STAMCOUNTER StatDirtyPageDupFlush;
2101 /** Times we've had to flush because of overflow. */
2102 STAMCOUNTER StatDirtyPageOverFlowFlush;
2103
2104 /** The high wather mark for cModifiedPages. */
2105 uint16_t cModifiedPagesHigh;
2106 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
2107
2108 /** The number of cache hits. */
2109 STAMCOUNTER StatCacheHits;
2110 /** The number of cache misses. */
2111 STAMCOUNTER StatCacheMisses;
2112 /** The number of times we've got a conflict of 'kind' in the cache. */
2113 STAMCOUNTER StatCacheKindMismatches;
2114 /** Number of times we've been out of pages. */
2115 STAMCOUNTER StatCacheFreeUpOne;
2116 /** The number of cacheable allocations. */
2117 STAMCOUNTER StatCacheCacheable;
2118 /** The number of uncacheable allocations. */
2119 STAMCOUNTER StatCacheUncacheable;
2120#else
2121 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
2122#endif
2123 /** The AVL tree for looking up a page by its HC physical address. */
2124 AVLOHCPHYSTREE HCPhysTree;
2125 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
2126 /** Array of pages. (cMaxPages in length)
2127 * The Id is the index into thist array.
2128 */
2129 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2130} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2131AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2132AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2133AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2134#ifdef VBOX_WITH_STATISTICS
2135AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2136#endif
2137AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2138
2139
2140/** @def PGMPOOL_PAGE_2_PTR
2141 * Maps a pool page pool into the current context.
2142 *
2143 * @returns VBox status code.
2144 * @param pVM The VM handle.
2145 * @param pPage The pool page.
2146 *
2147 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2148 * small page window employeed by that function. Be careful.
2149 * @remark There is no need to assert on the result.
2150 */
2151#if defined(IN_RC)
2152# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2153#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2154# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
2155#elif defined(VBOX_STRICT)
2156# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2157DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2158{
2159 Assert(pPage && pPage->pvPageR3);
2160 return pPage->pvPageR3;
2161}
2162#else
2163# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2164#endif
2165
2166/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
2167 * Maps a pool page pool into the current context.
2168 *
2169 * @returns VBox status code.
2170 * @param pPGM Pointer to the PGM instance data.
2171 * @param pPage The pool page.
2172 *
2173 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2174 * small page window employeed by that function. Be careful.
2175 * @remark There is no need to assert on the result.
2176 */
2177#if defined(IN_RC)
2178# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2179#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2180# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
2181#else
2182# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
2183#endif
2184
2185/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
2186 * Maps a pool page pool into the current context.
2187 *
2188 * @returns VBox status code.
2189 * @param pPGM Pointer to the PGMCPU instance data.
2190 * @param pPage The pool page.
2191 *
2192 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2193 * small page window employeed by that function. Be careful.
2194 * @remark There is no need to assert on the result.
2195 */
2196#if defined(IN_RC)
2197# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2198#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2199# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
2200#else
2201# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
2202#endif
2203
2204
2205/** @name Per guest page tracking data.
2206 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2207 * is to use more bits for it and split it up later on. But for now we'll play
2208 * safe and change as little as possible.
2209 *
2210 * The 16-bit word has two parts:
2211 *
2212 * The first 14-bit forms the @a idx field. It is either the index of a page in
2213 * the shadow page pool, or and index into the extent list.
2214 *
2215 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2216 * shadow page pool references to the page. If cRefs equals
2217 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2218 * (misnomer) table and not the shadow page pool.
2219 *
2220 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2221 * the 16-bit word.
2222 *
2223 * @{ */
2224/** The shift count for getting to the cRefs part. */
2225#define PGMPOOL_TD_CREFS_SHIFT 14
2226/** The mask applied after shifting the tracking data down by
2227 * PGMPOOL_TD_CREFS_SHIFT. */
2228#define PGMPOOL_TD_CREFS_MASK 0x3
2229/** The cRef value used to indiciate that the idx is the head of a
2230 * physical cross reference list. */
2231#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2232/** The shift used to get idx. */
2233#define PGMPOOL_TD_IDX_SHIFT 0
2234/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2235#define PGMPOOL_TD_IDX_MASK 0x3fff
2236/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2237 * simply too many mappings of this page. */
2238#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2239
2240/** @def PGMPOOL_TD_MAKE
2241 * Makes a 16-bit tracking data word.
2242 *
2243 * @returns tracking data.
2244 * @param cRefs The @a cRefs field. Must be within bounds!
2245 * @param idx The @a idx field. Must also be within bounds! */
2246#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2247
2248/** @def PGMPOOL_TD_GET_CREFS
2249 * Get the @a cRefs field from a tracking data word.
2250 *
2251 * @returns The @a cRefs field
2252 * @param u16 The tracking data word. */
2253#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2254
2255/** @def PGMPOOL_TD_GET_IDX
2256 * Get the @a idx field from a tracking data word.
2257 *
2258 * @returns The @a idx field
2259 * @param u16 The tracking data word. */
2260#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2261/** @} */
2262
2263
2264/**
2265 * Trees are using self relative offsets as pointers.
2266 * So, all its data, including the root pointer, must be in the heap for HC and GC
2267 * to have the same layout.
2268 */
2269typedef struct PGMTREES
2270{
2271 /** Physical access handlers (AVL range+offsetptr tree). */
2272 AVLROGCPHYSTREE PhysHandlers;
2273 /** Virtual access handlers (AVL range + GC ptr tree). */
2274 AVLROGCPTRTREE VirtHandlers;
2275 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2276 AVLROGCPHYSTREE PhysToVirtHandlers;
2277 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2278 AVLROGCPTRTREE HyperVirtHandlers;
2279} PGMTREES;
2280/** Pointer to PGM trees. */
2281typedef PGMTREES *PPGMTREES;
2282
2283
2284/** @name Paging mode macros
2285 * @{ */
2286#ifdef IN_RC
2287# define PGM_CTX(a,b) a##RC##b
2288# define PGM_CTX_STR(a,b) a "GC" b
2289# define PGM_CTX_DECL(type) VMMRCDECL(type)
2290#else
2291# ifdef IN_RING3
2292# define PGM_CTX(a,b) a##R3##b
2293# define PGM_CTX_STR(a,b) a "R3" b
2294# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2295# else
2296# define PGM_CTX(a,b) a##R0##b
2297# define PGM_CTX_STR(a,b) a "R0" b
2298# define PGM_CTX_DECL(type) VMMDECL(type)
2299# endif
2300#endif
2301
2302#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2303#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2304#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2305#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2306#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2307#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2308#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2309#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2310#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2311#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2312#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2313#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2314#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2315#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2316#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2317#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2318#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2319
2320#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2321#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2322#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2323#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2324#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2325#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2326#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2327#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2328#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2329#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2330#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2331#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2332#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2333#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2334#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2335#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2336#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2337
2338/* Shw_Gst */
2339#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2340#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2341#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2342#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2343#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2344#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2345#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2346#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2347#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2348#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2349#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2350#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2351#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2352#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2353#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2354#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2355#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2356#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2357#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2358
2359#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2360#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2361#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2362#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2363#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2364#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2365#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2366#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2367#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2368#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2369#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2370#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2371#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2372#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2373#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2374#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2375#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2376#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2377#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2378#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2379#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2380#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2381#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2382#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2383#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2384#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2385#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2386#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2387#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2388#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2389#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2390#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2391#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2392#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2393#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2394#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2395#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2396
2397#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2398#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2399/** @} */
2400
2401/**
2402 * Data for each paging mode.
2403 */
2404typedef struct PGMMODEDATA
2405{
2406 /** The guest mode type. */
2407 uint32_t uGstType;
2408 /** The shadow mode type. */
2409 uint32_t uShwType;
2410
2411 /** @name Function pointers for Shadow paging.
2412 * @{
2413 */
2414 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2415 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2416 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2417 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2418
2419 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2420 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2421
2422 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2423 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2424 /** @} */
2425
2426 /** @name Function pointers for Guest paging.
2427 * @{
2428 */
2429 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2430 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2431 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2432 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2433 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2434 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2435 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2436 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2437 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2438 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2439 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2440 /** @} */
2441
2442 /** @name Function pointers for Both Shadow and Guest paging.
2443 * @{
2444 */
2445 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2446 /* no pfnR3BthTrap0eHandler */
2447 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2448 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2449 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2450 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2451 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2452#ifdef VBOX_STRICT
2453 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2454#endif
2455 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2456 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2457
2458 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2459 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2460 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2461 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2462 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2463 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2464#ifdef VBOX_STRICT
2465 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2466#endif
2467 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2468 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2469
2470 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2471 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2472 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2473 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2474 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2475 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2476#ifdef VBOX_STRICT
2477 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2478#endif
2479 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2480 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2481 /** @} */
2482} PGMMODEDATA, *PPGMMODEDATA;
2483
2484
2485
2486/**
2487 * Converts a PGM pointer into a VM pointer.
2488 * @returns Pointer to the VM structure the PGM is part of.
2489 * @param pPGM Pointer to PGM instance data.
2490 */
2491#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2492
2493/**
2494 * PGM Data (part of VM)
2495 */
2496typedef struct PGM
2497{
2498 /** Offset to the VM structure. */
2499 RTINT offVM;
2500 /** Offset of the PGMCPU structure relative to VMCPU. */
2501 RTINT offVCpuPGM;
2502
2503 /** @cfgm{RamPreAlloc, boolean, false}
2504 * Indicates whether the base RAM should all be allocated before starting
2505 * the VM (default), or if it should be allocated when first written to.
2506 */
2507 bool fRamPreAlloc;
2508 /** Indicates whether write monitoring is currently in use.
2509 * This is used to prevent conflicts between live saving and page sharing
2510 * detection. */
2511 bool fPhysWriteMonitoringEngaged;
2512 /** Alignment padding. */
2513 bool afAlignment0[2];
2514
2515 /*
2516 * This will be redefined at least two more times before we're done, I'm sure.
2517 * The current code is only to get on with the coding.
2518 * - 2004-06-10: initial version, bird.
2519 * - 2004-07-02: 1st time, bird.
2520 * - 2004-10-18: 2nd time, bird.
2521 * - 2005-07-xx: 3rd time, bird.
2522 */
2523
2524 /** The host paging mode. (This is what SUPLib reports.) */
2525 SUPPAGINGMODE enmHostMode;
2526
2527 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2528 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2529 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2530 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2531
2532 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2533 RTGCPHYS GCPhys4MBPSEMask;
2534
2535 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2536 * This is sorted by physical address and contains no overlapping ranges. */
2537 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2538 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2539 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2540 /** RC pointer corresponding to PGM::pRamRangesR3. */
2541 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2542 /** Generation ID for the RAM ranges. This member is incremented everytime a RAM
2543 * range is linked or unlinked. */
2544 uint32_t volatile idRamRangesGen;
2545
2546 /** Pointer to the list of ROM ranges - for R3.
2547 * This is sorted by physical address and contains no overlapping ranges. */
2548 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2549 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2550 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2551 /** RC pointer corresponding to PGM::pRomRangesR3. */
2552 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2553#if HC_ARCH_BITS == 64
2554 /** Alignment padding. */
2555 RTRCPTR GCPtrPadding2;
2556#endif
2557
2558 /** Pointer to the list of MMIO2 ranges - for R3.
2559 * Registration order. */
2560 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2561
2562 /** PGM offset based trees - R3 Ptr. */
2563 R3PTRTYPE(PPGMTREES) pTreesR3;
2564 /** PGM offset based trees - R0 Ptr. */
2565 R0PTRTYPE(PPGMTREES) pTreesR0;
2566 /** PGM offset based trees - RC Ptr. */
2567 RCPTRTYPE(PPGMTREES) pTreesRC;
2568
2569 /** Linked list of GC mappings - for RC.
2570 * The list is sorted ascending on address.
2571 */
2572 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2573 /** Linked list of GC mappings - for HC.
2574 * The list is sorted ascending on address.
2575 */
2576 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2577 /** Linked list of GC mappings - for R0.
2578 * The list is sorted ascending on address.
2579 */
2580 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2581
2582 /** Pointer to the 5 page CR3 content mapping.
2583 * The first page is always the CR3 (in some form) while the 4 other pages
2584 * are used of the PDs in PAE mode. */
2585 RTGCPTR GCPtrCR3Mapping;
2586#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2587 uint32_t u32Alignment1;
2588#endif
2589
2590 /** Indicates that PGMR3FinalizeMappings has been called and that further
2591 * PGMR3MapIntermediate calls will be rejected. */
2592 bool fFinalizedMappings;
2593 /** If set no conflict checks are required. */
2594 bool fMappingsFixed;
2595 /** If set if restored as fixed but we were unable to re-fixate at the old
2596 * location because of room or address incompatibilities. */
2597 bool fMappingsFixedRestored;
2598 /** If set, then no mappings are put into the shadow page table.
2599 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2600 bool fMappingsDisabled;
2601 /** Size of fixed mapping.
2602 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2603 uint32_t cbMappingFixed;
2604 /** Base address (GC) of fixed mapping.
2605 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2606 RTGCPTR GCPtrMappingFixed;
2607 /** The address of the previous RAM range mapping. */
2608 RTGCPTR GCPtrPrevRamRangeMapping;
2609
2610 /** @name Intermediate Context
2611 * @{ */
2612 /** Pointer to the intermediate page directory - Normal. */
2613 R3PTRTYPE(PX86PD) pInterPD;
2614 /** Pointer to the intermedate page tables - Normal.
2615 * There are two page tables, one for the identity mapping and one for
2616 * the host context mapping (of the core code). */
2617 R3PTRTYPE(PX86PT) apInterPTs[2];
2618 /** Pointer to the intermedate page tables - PAE. */
2619 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2620 /** Pointer to the intermedate page directory - PAE. */
2621 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2622 /** Pointer to the intermedate page directory - PAE. */
2623 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2624 /** Pointer to the intermedate page-map level 4 - AMD64. */
2625 R3PTRTYPE(PX86PML4) pInterPaePML4;
2626 /** Pointer to the intermedate page directory - AMD64. */
2627 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2628 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2629 RTHCPHYS HCPhysInterPD;
2630 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2631 RTHCPHYS HCPhysInterPaePDPT;
2632 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2633 RTHCPHYS HCPhysInterPaePML4;
2634 /** @} */
2635
2636 /** Base address of the dynamic page mapping area.
2637 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2638 */
2639 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2640 /** The index of the last entry used in the dynamic page mapping area. */
2641 RTUINT iDynPageMapLast;
2642 /** Cache containing the last entries in the dynamic page mapping area.
2643 * The cache size is covering half of the mapping area. */
2644 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2645 /** Keep a lock counter for the full (!) mapping area. */
2646 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2647
2648 /** The address of the ring-0 mapping cache if we're making use of it. */
2649 RTR0PTR pvR0DynMapUsed;
2650#if HC_ARCH_BITS == 32
2651 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2652 uint32_t u32Alignment2;
2653#endif
2654
2655 /** PGM critical section.
2656 * This protects the physical & virtual access handlers, ram ranges,
2657 * and the page flag updating (some of it anyway).
2658 */
2659 PDMCRITSECT CritSect;
2660
2661 /** Pointer to SHW+GST mode data (function pointers).
2662 * The index into this table is made up from */
2663 R3PTRTYPE(PPGMMODEDATA) paModeData;
2664
2665 /** Shadow Page Pool - R3 Ptr. */
2666 R3PTRTYPE(PPGMPOOL) pPoolR3;
2667 /** Shadow Page Pool - R0 Ptr. */
2668 R0PTRTYPE(PPGMPOOL) pPoolR0;
2669 /** Shadow Page Pool - RC Ptr. */
2670 RCPTRTYPE(PPGMPOOL) pPoolRC;
2671
2672 /** We're not in a state which permits writes to guest memory.
2673 * (Only used in strict builds.) */
2674 bool fNoMorePhysWrites;
2675 /** Alignment padding that makes the next member start on a 8 byte boundrary. */
2676 bool afAlignment3[HC_ARCH_BITS == 32 ? 7: 3];
2677
2678 /**
2679 * Data associated with managing the ring-3 mappings of the allocation chunks.
2680 */
2681 struct
2682 {
2683 /** The chunk tree, ordered by chunk id. */
2684#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2685 R3PTRTYPE(PAVLU32NODECORE) pTree;
2686#else
2687 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2688#endif
2689 /** The chunk age tree, ordered by ageing sequence number. */
2690 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2691 /** The chunk mapping TLB. */
2692 PGMCHUNKR3MAPTLB Tlb;
2693 /** The number of mapped chunks. */
2694 uint32_t c;
2695 /** The maximum number of mapped chunks.
2696 * @cfgm PGM/MaxRing3Chunks */
2697 uint32_t cMax;
2698 /** The current time. */
2699 uint32_t iNow;
2700 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2701 uint32_t AgeingCountdown;
2702 } ChunkR3Map;
2703
2704 /**
2705 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2706 */
2707 PGMPAGER3MAPTLB PhysTlbHC;
2708
2709 /** @name The zero page.
2710 * @{ */
2711 /** The host physical address of the zero page. */
2712 RTHCPHYS HCPhysZeroPg;
2713 /** The ring-3 mapping of the zero page. */
2714 RTR3PTR pvZeroPgR3;
2715 /** The ring-0 mapping of the zero page. */
2716 RTR0PTR pvZeroPgR0;
2717 /** The GC mapping of the zero page. */
2718 RTGCPTR pvZeroPgRC;
2719 /** @}*/
2720
2721 /** The number of handy pages. */
2722 uint32_t cHandyPages;
2723
2724 /** The number of large handy pages. */
2725 uint32_t cLargeHandyPages;
2726
2727 /**
2728 * Array of handy pages.
2729 *
2730 * This array is used in a two way communication between pgmPhysAllocPage
2731 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2732 * an intermediary.
2733 *
2734 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2735 * (The current size of 32 pages, means 128 KB of handy memory.)
2736 */
2737 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2738
2739 /**
2740 * Array of large handy pages. (currently size 1)
2741 *
2742 * This array is used in a two way communication between pgmPhysAllocLargePage
2743 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
2744 * an intermediary.
2745 */
2746 GMMPAGEDESC aLargeHandyPage[1];
2747
2748 /**
2749 * Live save data.
2750 */
2751 struct
2752 {
2753 /** Per type statistics. */
2754 struct
2755 {
2756 /** The number of ready pages. */
2757 uint32_t cReadyPages;
2758 /** The number of dirty pages. */
2759 uint32_t cDirtyPages;
2760 /** The number of ready zero pages. */
2761 uint32_t cZeroPages;
2762 /** The number of write monitored pages. */
2763 uint32_t cMonitoredPages;
2764 } Rom,
2765 Mmio2,
2766 Ram;
2767 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
2768 uint32_t cIgnoredPages;
2769 /** Indicates that a live save operation is active. */
2770 bool fActive;
2771 /** Padding. */
2772 bool afReserved[2];
2773 /** The next history index. */
2774 uint8_t iDirtyPagesHistory;
2775 /** History of the total amount of dirty pages. */
2776 uint32_t acDirtyPagesHistory[64];
2777 /** Short term dirty page average. */
2778 uint32_t cDirtyPagesShort;
2779 /** Long term dirty page average. */
2780 uint32_t cDirtyPagesLong;
2781 /** The number of saved pages. This is used to get some kind of estimate of the
2782 * link speed so we can decide when we're done. It is reset after the first
2783 * 7 passes so the speed estimate doesn't get inflated by the initial set of
2784 * zero pages. */
2785 uint64_t cSavedPages;
2786 /** The nanosecond timestamp when cSavedPages was 0. */
2787 uint64_t uSaveStartNS;
2788 /** Pages per second (for statistics). */
2789 uint32_t cPagesPerSecond;
2790 uint32_t cAlignment;
2791 } LiveSave;
2792
2793 /** @name Error injection.
2794 * @{ */
2795 /** Inject handy page allocation errors pretending we're completely out of
2796 * memory. */
2797 bool volatile fErrInjHandyPages;
2798 /** Padding. */
2799 bool afReserved[3];
2800 /** @} */
2801
2802 /** @name Release Statistics
2803 * @{ */
2804 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
2805 uint32_t cPrivatePages; /**< The number of private pages. */
2806 uint32_t cSharedPages; /**< The number of shared pages. */
2807 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
2808 uint32_t cZeroPages; /**< The number of zero backed pages. */
2809 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
2810 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
2811 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
2812 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
2813 uint32_t cReadLockedPages; /**< The number of read locked pages. */
2814 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
2815/* uint32_t aAlignment4[1]; */
2816
2817 /** The number of times we were forced to change the hypervisor region location. */
2818 STAMCOUNTER cRelocations;
2819
2820 STAMCOUNTER StatLargePageAlloc; /**< The number of large pages we've allocated.*/
2821 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
2822 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
2823 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
2824 /** @} */
2825
2826#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2827 /* R3 only: */
2828 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2829 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2830
2831 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2832 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2833 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2834 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2835 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2836 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2837 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2838 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2839 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2840 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2841 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2842 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2843 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2844 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2845 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2846 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2847 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2848 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2849 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2850 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2851/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2852 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2853 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2854/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2855
2856 /* RC only: */
2857 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2858 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2859 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2860 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2861
2862 STAMCOUNTER StatRZPhysRead;
2863 STAMCOUNTER StatRZPhysReadBytes;
2864 STAMCOUNTER StatRZPhysWrite;
2865 STAMCOUNTER StatRZPhysWriteBytes;
2866 STAMCOUNTER StatR3PhysRead;
2867 STAMCOUNTER StatR3PhysReadBytes;
2868 STAMCOUNTER StatR3PhysWrite;
2869 STAMCOUNTER StatR3PhysWriteBytes;
2870 STAMCOUNTER StatRCPhysRead;
2871 STAMCOUNTER StatRCPhysReadBytes;
2872 STAMCOUNTER StatRCPhysWrite;
2873 STAMCOUNTER StatRCPhysWriteBytes;
2874
2875 STAMCOUNTER StatRZPhysSimpleRead;
2876 STAMCOUNTER StatRZPhysSimpleReadBytes;
2877 STAMCOUNTER StatRZPhysSimpleWrite;
2878 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2879 STAMCOUNTER StatR3PhysSimpleRead;
2880 STAMCOUNTER StatR3PhysSimpleReadBytes;
2881 STAMCOUNTER StatR3PhysSimpleWrite;
2882 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2883 STAMCOUNTER StatRCPhysSimpleRead;
2884 STAMCOUNTER StatRCPhysSimpleReadBytes;
2885 STAMCOUNTER StatRCPhysSimpleWrite;
2886 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2887
2888 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2889 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2890 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2891 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2892 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2893 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2894 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2895
2896 /** Time spent by the host OS for large page allocation. */
2897 STAMPROFILE StatAllocLargePage;
2898 /** Time spent clearing the newly allocated large pages. */
2899 STAMPROFILE StatClearLargePage;
2900 /** pgmPhysIsValidLargePage profiling - R3 */
2901 STAMPROFILE StatR3IsValidLargePage;
2902 /** pgmPhysIsValidLargePage profiling - RZ*/
2903 STAMPROFILE StatRZIsValidLargePage;
2904#endif
2905} PGM;
2906#ifndef IN_TSTVMSTRUCTGC /* HACK */
2907AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
2908AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
2909AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
2910AssertCompileMemberAlignment(PGM, aHCPhysDynPageMapCache, 8);
2911AssertCompileMemberAlignment(PGM, CritSect, 8);
2912AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
2913AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
2914AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
2915AssertCompileMemberAlignment(PGM, aHandyPages, 8);
2916AssertCompileMemberAlignment(PGM, cRelocations, 8);
2917#endif /* !IN_TSTVMSTRUCTGC */
2918/** Pointer to the PGM instance data. */
2919typedef PGM *PPGM;
2920
2921
2922/**
2923 * Converts a PGMCPU pointer into a VM pointer.
2924 * @returns Pointer to the VM structure the PGM is part of.
2925 * @param pPGM Pointer to PGMCPU instance data.
2926 */
2927#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2928
2929/**
2930 * Converts a PGMCPU pointer into a PGM pointer.
2931 * @returns Pointer to the VM structure the PGM is part of.
2932 * @param pPGM Pointer to PGMCPU instance data.
2933 */
2934#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2935
2936/**
2937 * PGMCPU Data (part of VMCPU).
2938 */
2939typedef struct PGMCPU
2940{
2941 /** Offset to the VM structure. */
2942 RTINT offVM;
2943 /** Offset to the VMCPU structure. */
2944 RTINT offVCpu;
2945 /** Offset of the PGM structure relative to VMCPU. */
2946 RTINT offPGM;
2947 RTINT uPadding0; /**< structure size alignment. */
2948
2949#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2950 /** Automatically tracked physical memory mapping set.
2951 * Ring-0 and strict raw-mode builds. */
2952 PGMMAPSET AutoSet;
2953#endif
2954
2955 /** A20 gate mask.
2956 * Our current approach to A20 emulation is to let REM do it and don't bother
2957 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2958 * But whould need arrise, we'll subject physical addresses to this mask. */
2959 RTGCPHYS GCPhysA20Mask;
2960 /** A20 gate state - boolean! */
2961 bool fA20Enabled;
2962
2963 /** What needs syncing (PGM_SYNC_*).
2964 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2965 * PGMFlushTLB, and PGMR3Load. */
2966 RTUINT fSyncFlags;
2967
2968 /** The shadow paging mode. */
2969 PGMMODE enmShadowMode;
2970 /** The guest paging mode. */
2971 PGMMODE enmGuestMode;
2972
2973 /** The current physical address representing in the guest CR3 register. */
2974 RTGCPHYS GCPhysCR3;
2975
2976 /** @name 32-bit Guest Paging.
2977 * @{ */
2978 /** The guest's page directory, R3 pointer. */
2979 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2980#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2981 /** The guest's page directory, R0 pointer. */
2982 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2983#endif
2984 /** The guest's page directory, static RC mapping. */
2985 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2986 /** @} */
2987
2988 /** @name PAE Guest Paging.
2989 * @{ */
2990 /** The guest's page directory pointer table, static RC mapping. */
2991 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2992 /** The guest's page directory pointer table, R3 pointer. */
2993 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2994#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2995 /** The guest's page directory pointer table, R0 pointer. */
2996 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2997#endif
2998
2999 /** The guest's page directories, R3 pointers.
3000 * These are individual pointers and don't have to be adjecent.
3001 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3002 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3003 /** The guest's page directories, R0 pointers.
3004 * Same restrictions as apGstPaePDsR3. */
3005#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3006 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3007#endif
3008 /** The guest's page directories, static GC mapping.
3009 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3010 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3011 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3012 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3013 RTGCPHYS aGCPhysGstPaePDs[4];
3014 /** The physical addresses of the monitored guest page directories (PAE). */
3015 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3016 /** @} */
3017
3018 /** @name AMD64 Guest Paging.
3019 * @{ */
3020 /** The guest's page directory pointer table, R3 pointer. */
3021 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3022#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3023 /** The guest's page directory pointer table, R0 pointer. */
3024 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3025#else
3026 RTR0PTR alignment6b; /**< alignment equalizer. */
3027#endif
3028 /** @} */
3029
3030 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3031 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3032 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3033 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3034 /** Pointer to the page of the current active CR3 - RC Ptr. */
3035 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3036 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3037 uint32_t iShwUser;
3038 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3039 uint32_t iShwUserTable;
3040# if HC_ARCH_BITS == 64
3041 RTRCPTR alignment6; /**< structure size alignment. */
3042# endif
3043 /** @} */
3044
3045 /** @name Function pointers for Shadow paging.
3046 * @{
3047 */
3048 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3049 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3050 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3051 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3052
3053 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3054 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3055
3056 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3057 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3058
3059 /** @} */
3060
3061 /** @name Function pointers for Guest paging.
3062 * @{
3063 */
3064 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3065 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3066 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3067 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3068 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3069 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3070 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3071 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3072#if HC_ARCH_BITS == 64
3073 RTRCPTR alignment3; /**< structure size alignment. */
3074#endif
3075
3076 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3077 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3078 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3079 /** @} */
3080
3081 /** @name Function pointers for Both Shadow and Guest paging.
3082 * @{
3083 */
3084 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3085 /* no pfnR3BthTrap0eHandler */
3086 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3087 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3088 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3089 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3090 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3091 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3092 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3093 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3094
3095 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3096 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3097 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3098 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3099 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3100 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3101 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3102 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3103 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3104
3105 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3106 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3107 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3108 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
3109 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3110 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3111 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3112 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3113 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3114 RTRCPTR alignment2; /**< structure size alignment. */
3115 /** @} */
3116
3117 /** For saving stack space, the disassembler state is allocated here instead of
3118 * on the stack.
3119 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3120 union
3121 {
3122 /** The disassembler scratch space. */
3123 DISCPUSTATE DisState;
3124 /** Padding. */
3125 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3126 };
3127
3128 /* Count the number of pgm pool access handler calls. */
3129 uint64_t cPoolAccessHandler;
3130
3131 /** @name Release Statistics
3132 * @{ */
3133 /** The number of times the guest has switched mode since last reset or statistics reset. */
3134 STAMCOUNTER cGuestModeChanges;
3135 /** @} */
3136
3137#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3138 /** @name Statistics
3139 * @{ */
3140 /** RC: Which statistic this \#PF should be attributed to. */
3141 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3142 RTRCPTR padding0;
3143 /** R0: Which statistic this \#PF should be attributed to. */
3144 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3145 RTR0PTR padding1;
3146
3147 /* Common */
3148 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3149 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3150
3151 /* R0 only: */
3152 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
3153 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
3154 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
3155 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3156 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
3157 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
3158 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
3159 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
3160 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
3161 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
3162 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
3163 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
3164 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
3165 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
3166 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
3167 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
3168 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
3169 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
3170 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
3171 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
3172 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
3173 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
3174 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
3175 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
3176 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
3177 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
3178
3179 /* RZ only: */
3180 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3181 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
3182 STAMPROFILE StatRZTrap0eTimeSyncPT;
3183 STAMPROFILE StatRZTrap0eTimeMapping;
3184 STAMPROFILE StatRZTrap0eTimeOutOfSync;
3185 STAMPROFILE StatRZTrap0eTimeHandlers;
3186 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3187 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3188 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3189 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3190 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3191 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3192 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3193 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3194 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3195 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3196 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3197 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3198 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3199 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3200 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3201 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
3202 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3203 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3204 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3205 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3206 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3207 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3208 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3209 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3210 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3211 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3212 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3213 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3214 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3215 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3216 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3217 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3218 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3219 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest \#PF ending up at the end of the \#PF code. */
3220 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3221 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3222 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3223 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3224 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3225 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3226 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3227 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3228 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3229
3230 /* HC - R3 and (maybe) R0: */
3231
3232 /* RZ & R3: */
3233 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3234 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3235 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3236 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3237 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3238 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3239 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3240 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3241 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3242 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3243 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3244 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3245 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3246 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3247 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3248 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3249 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3250 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3251 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3252 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3253 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3254 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3255 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3256 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3257 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3258 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3259 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3260 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3261 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3262 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3263 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3264 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3265 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3266 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3267 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3268 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3269 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3270 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3271 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3272 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3273 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3274 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3275 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3276 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3277 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3278 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3279 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3280
3281 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3282 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3283 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3284 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3285 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3286 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3287 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3288 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3289 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3290 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3291 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3292 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3293 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3294 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3295 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3296 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3297 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3298 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3299 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3300 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3301 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3302 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3303 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3304 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3305 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3306 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3307 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3308 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3309 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3310 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3311 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3312 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3313 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3314 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3315 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3316 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3317 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3318 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3319 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3320 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3321 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3322 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3323 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3324 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3325 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3326 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3327 /** @} */
3328#endif /* VBOX_WITH_STATISTICS */
3329} PGMCPU;
3330/** Pointer to the per-cpu PGM data. */
3331typedef PGMCPU *PPGMCPU;
3332
3333
3334/** @name PGM::fSyncFlags Flags
3335 * @{
3336 */
3337/** Updates the virtual access handler state bit in PGMPAGE. */
3338#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3339/** Always sync CR3. */
3340#define PGM_SYNC_ALWAYS RT_BIT(1)
3341/** Check monitoring on next CR3 (re)load and invalidate page.
3342 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3343#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3344/** Check guest mapping in SyncCR3. */
3345#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3346/** Clear the page pool (a light weight flush). */
3347#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3348#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3349/** @} */
3350
3351
3352RT_C_DECLS_BEGIN
3353
3354int pgmLock(PVM pVM);
3355void pgmUnlock(PVM pVM);
3356
3357int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3358int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3359int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3360PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3361int pgmMapResolveConflicts(PVM pVM);
3362DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3363
3364void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3365bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3366void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3367int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3368DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3369#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3370void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3371#else
3372# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3373#endif
3374DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3375int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3376
3377int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3378int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3379int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3380int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3381int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3382void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3383int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3384int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3385int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3386int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3387int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3388int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3389int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3390VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3391VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3392#ifdef IN_RING3
3393void pgmR3PhysRelinkRamRanges(PVM pVM);
3394int pgmR3PhysRamPreAllocate(PVM pVM);
3395int pgmR3PhysRamReset(PVM pVM);
3396int pgmR3PhysRomReset(PVM pVM);
3397int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3398int pgmR3PhysRamTerm(PVM pVM);
3399
3400int pgmR3PoolInit(PVM pVM);
3401void pgmR3PoolRelocate(PVM pVM);
3402void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3403void pgmR3PoolReset(PVM pVM);
3404void pgmR3PoolClearAll(PVM pVM);
3405DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser);
3406
3407#endif /* IN_RING3 */
3408#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3409int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3410#endif
3411int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3412
3413DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3414{
3415 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3416}
3417
3418void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3419void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3420int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3421void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3422PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3423int pgmPoolSyncCR3(PVMCPU pVCpu);
3424bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3425int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3426void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3427void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3428DECLINLINE(int) pgmPoolTrackFlushGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3429{
3430 return pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPhysPage, true /* flush PTEs */, pfFlushTLBs);
3431}
3432
3433uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3434void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3435void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3436int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3437void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3438
3439void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3440void pgmPoolResetDirtyPages(PVM pVM);
3441
3442int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3443int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3444
3445void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3446void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3447int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3448int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3449
3450int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3451#ifndef IN_RC
3452int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3453#endif
3454int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3455
3456PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3457PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3458PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3459PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3460
3461RT_C_DECLS_END
3462
3463/** @} */
3464
3465#endif
3466
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