VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 22346

Last change on this file since 22346 was 22343, checked in by vboxsync, 15 years ago

Attempt to detect full page table initialization early on.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 189.9 KB
Line 
1/* $Id: PGMInternal.h 22343 2009-08-19 12:40:16Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/critsect.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59 * Comment it if it will break something.
60 */
61#define PGM_OUT_OF_SYNC_IN_GC
62
63/**
64 * Check and skip global PDEs for non-global flushes
65 */
66#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68/**
69 * Sync N pages instead of a whole page table
70 */
71#define PGM_SYNC_N_PAGES
72
73/**
74 * Number of pages to sync during a page fault
75 *
76 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
77 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
78 */
79#define PGM_SYNC_NR_PAGES 8
80
81/**
82 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
83 */
84#define PGM_MAX_PHYSCACHE_ENTRIES 64
85#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
86
87/** @def PGMPOOL_WITH_CACHE
88 * Enable agressive caching using the page pool.
89 *
90 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
91 */
92#define PGMPOOL_WITH_CACHE
93
94/** @def PGMPOOL_WITH_MIXED_PT_CR3
95 * When defined, we'll deal with 'uncachable' pages.
96 */
97#ifdef PGMPOOL_WITH_CACHE
98# define PGMPOOL_WITH_MIXED_PT_CR3
99#endif
100
101/** @def PGMPOOL_WITH_MONITORING
102 * Monitor the guest pages which are shadowed.
103 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
104 * be enabled as well.
105 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
106 */
107#ifdef PGMPOOL_WITH_CACHE
108# define PGMPOOL_WITH_MONITORING
109#endif
110
111/** @def PGMPOOL_WITH_GCPHYS_TRACKING
112 * Tracking the of shadow pages mapping guest physical pages.
113 *
114 * This is very expensive, the current cache prototype is trying to figure out
115 * whether it will be acceptable with an agressive caching policy.
116 */
117#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
118# define PGMPOOL_WITH_GCPHYS_TRACKING
119#endif
120
121/** @def PGMPOOL_WITH_USER_TRACKING
122 * Tracking users of shadow pages. This is required for the linking of shadow page
123 * tables and physical guest addresses.
124 */
125#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
126# define PGMPOOL_WITH_USER_TRACKING
127#endif
128
129/** @def PGMPOOL_CFG_MAX_GROW
130 * The maximum number of pages to add to the pool in one go.
131 */
132#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
133
134/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
135 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
136 */
137#ifdef VBOX_STRICT
138# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
139#endif
140
141/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
142 * Enables the experimental lazy page allocation code. */
143/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
144
145/** @} */
146
147
148/** @name PDPT and PML4 flags.
149 * These are placed in the three bits available for system programs in
150 * the PDPT and PML4 entries.
151 * @{ */
152/** The entry is a permanent one and it's must always be present.
153 * Never free such an entry. */
154#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
155/** Mapping (hypervisor allocated pagetable). */
156#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
157/** @} */
158
159/** @name Page directory flags.
160 * These are placed in the three bits available for system programs in
161 * the page directory entries.
162 * @{ */
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
165/** Made read-only to facilitate dirty bit tracking. */
166#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
167/** @} */
168
169/** @name Page flags.
170 * These are placed in the three bits available for system programs in
171 * the page entries.
172 * @{ */
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
175
176#ifndef PGM_PTFLAGS_CSAM_VALIDATED
177/** Scanned and approved by CSAM (tm).
178 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
179 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
180#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
181#endif
182
183/** @} */
184
185/** @name Defines used to indicate the shadow and guest paging in the templates.
186 * @{ */
187#define PGM_TYPE_REAL 1
188#define PGM_TYPE_PROT 2
189#define PGM_TYPE_32BIT 3
190#define PGM_TYPE_PAE 4
191#define PGM_TYPE_AMD64 5
192#define PGM_TYPE_NESTED 6
193#define PGM_TYPE_EPT 7
194#define PGM_TYPE_MAX PGM_TYPE_EPT
195/** @} */
196
197/** Macro for checking if the guest is using paging.
198 * @param uGstType PGM_TYPE_*
199 * @param uShwType PGM_TYPE_*
200 * @remark ASSUMES certain order of the PGM_TYPE_* values.
201 */
202#define PGM_WITH_PAGING(uGstType, uShwType) \
203 ( (uGstType) >= PGM_TYPE_32BIT \
204 && (uShwType) != PGM_TYPE_NESTED \
205 && (uShwType) != PGM_TYPE_EPT)
206
207/** Macro for checking if the guest supports the NX bit.
208 * @param uGstType PGM_TYPE_*
209 * @param uShwType PGM_TYPE_*
210 * @remark ASSUMES certain order of the PGM_TYPE_* values.
211 */
212#define PGM_WITH_NX(uGstType, uShwType) \
213 ( (uGstType) >= PGM_TYPE_PAE \
214 && (uShwType) != PGM_TYPE_NESTED \
215 && (uShwType) != PGM_TYPE_EPT)
216
217
218/** @def PGM_HCPHYS_2_PTR
219 * Maps a HC physical page pool address to a virtual address.
220 *
221 * @returns VBox status code.
222 * @param pVM The VM handle.
223 * @param HCPhys The HC physical address to map to a virtual one.
224 * @param ppv Where to store the virtual address. No need to cast this.
225 *
226 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
227 * small page window employeed by that function. Be careful.
228 * @remark There is no need to assert on the result.
229 */
230#ifdef IN_RC
231# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
232 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
233#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
234# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
235 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
236#else
237# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
238 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
239#endif
240
241/** @def PGM_HCPHYS_2_PTR_BY_PGM
242 * Maps a HC physical page pool address to a virtual address.
243 *
244 * @returns VBox status code.
245 * @param pPGM The PGM instance data.
246 * @param HCPhys The HC physical address to map to a virtual one.
247 * @param ppv Where to store the virtual address. No need to cast this.
248 *
249 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
250 * small page window employeed by that function. Be careful.
251 * @remark There is no need to assert on the result.
252 */
253#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
254# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
255 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
256#else
257# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
258 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
259#endif
260
261/** @def PGM_GCPHYS_2_PTR
262 * Maps a GC physical page address to a virtual address.
263 *
264 * @returns VBox status code.
265 * @param pVM The VM handle.
266 * @param GCPhys The GC physical address to map to a virtual one.
267 * @param ppv Where to store the virtual address. No need to cast this.
268 *
269 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
270 * small page window employeed by that function. Be careful.
271 * @remark There is no need to assert on the result.
272 */
273#ifdef IN_RC
274# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
275 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
276#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
277# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
278 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
279#else
280# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
281 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
282#endif
283
284/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
285 * Maps a GC physical page address to a virtual address.
286 *
287 * @returns VBox status code.
288 * @param pPGM Pointer to the PGM instance data.
289 * @param GCPhys The GC physical address to map to a virtual one.
290 * @param ppv Where to store the virtual address. No need to cast this.
291 *
292 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
293 * small page window employeed by that function. Be careful.
294 * @remark There is no need to assert on the result.
295 */
296#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
297# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
298 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
299#else
300# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
301 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
302#endif
303
304/** @def PGM_GCPHYS_2_PTR_EX
305 * Maps a unaligned GC physical page address to a virtual address.
306 *
307 * @returns VBox status code.
308 * @param pVM The VM handle.
309 * @param GCPhys The GC physical address to map to a virtual one.
310 * @param ppv Where to store the virtual address. No need to cast this.
311 *
312 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
313 * small page window employeed by that function. Be careful.
314 * @remark There is no need to assert on the result.
315 */
316#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
317# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
318 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
319#else
320# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
321 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
322#endif
323
324/** @def PGM_INVL_PG
325 * Invalidates a page.
326 *
327 * @param pVCpu The VMCPU handle.
328 * @param GCVirt The virtual address of the page to invalidate.
329 */
330#ifdef IN_RC
331# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
332#elif defined(IN_RING0)
333# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
334#else
335# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
336#endif
337
338/** @def PGM_INVL_PG
339 * Invalidates a page on all VCPUs
340 *
341 * @param pVM The VM handle.
342 * @param GCVirt The virtual address of the page to invalidate.
343 */
344#ifdef IN_RC
345# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
346#elif defined(IN_RING0)
347# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
348#else
349# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
350#endif
351
352/** @def PGM_INVL_BIG_PG
353 * Invalidates a 4MB page directory entry.
354 *
355 * @param pVCpu The VMCPU handle.
356 * @param GCVirt The virtual address within the page directory to invalidate.
357 */
358#ifdef IN_RC
359# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
360#elif defined(IN_RING0)
361# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
362#else
363# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
364#endif
365
366/** @def PGM_INVL_VCPU_TLBS()
367 * Invalidates the TLBs of the specified VCPU
368 *
369 * @param pVCpu The VMCPU handle.
370 */
371#ifdef IN_RC
372# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
373#elif defined(IN_RING0)
374# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
375#else
376# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
377#endif
378
379/** @def PGM_INVL_ALL_VCPU_TLBS()
380 * Invalidates the TLBs of all VCPUs
381 *
382 * @param pVM The VM handle.
383 */
384#ifdef IN_RC
385# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
386#elif defined(IN_RING0)
387# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
388#else
389# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
390#endif
391
392/** Size of the GCPtrConflict array in PGMMAPPING.
393 * @remarks Must be a power of two. */
394#define PGMMAPPING_CONFLICT_MAX 8
395
396/**
397 * Structure for tracking GC Mappings.
398 *
399 * This structure is used by linked list in both GC and HC.
400 */
401typedef struct PGMMAPPING
402{
403 /** Pointer to next entry. */
404 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
405 /** Pointer to next entry. */
406 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
407 /** Pointer to next entry. */
408 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
409 /** Indicate whether this entry is finalized. */
410 bool fFinalized;
411 /** Start Virtual address. */
412 RTGCPTR GCPtr;
413 /** Last Virtual address (inclusive). */
414 RTGCPTR GCPtrLast;
415 /** Range size (bytes). */
416 RTGCPTR cb;
417 /** Pointer to relocation callback function. */
418 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
419 /** User argument to the callback. */
420 R3PTRTYPE(void *) pvUser;
421 /** Mapping description / name. For easing debugging. */
422 R3PTRTYPE(const char *) pszDesc;
423 /** Last 8 addresses that caused conflicts. */
424 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
425 /** Number of conflicts for this hypervisor mapping. */
426 uint32_t cConflicts;
427 /** Number of page tables. */
428 uint32_t cPTs;
429
430 /** Array of page table mapping data. Each entry
431 * describes one page table. The array can be longer
432 * than the declared length.
433 */
434 struct
435 {
436 /** The HC physical address of the page table. */
437 RTHCPHYS HCPhysPT;
438 /** The HC physical address of the first PAE page table. */
439 RTHCPHYS HCPhysPaePT0;
440 /** The HC physical address of the second PAE page table. */
441 RTHCPHYS HCPhysPaePT1;
442 /** The HC virtual address of the 32-bit page table. */
443 R3PTRTYPE(PX86PT) pPTR3;
444 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
445 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
446 /** The RC virtual address of the 32-bit page table. */
447 RCPTRTYPE(PX86PT) pPTRC;
448 /** The RC virtual address of the two PAE page table. */
449 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
450 /** The R0 virtual address of the 32-bit page table. */
451 R0PTRTYPE(PX86PT) pPTR0;
452 /** The R0 virtual address of the two PAE page table. */
453 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
454 } aPTs[1];
455} PGMMAPPING;
456/** Pointer to structure for tracking GC Mappings. */
457typedef struct PGMMAPPING *PPGMMAPPING;
458
459
460/**
461 * Physical page access handler structure.
462 *
463 * This is used to keep track of physical address ranges
464 * which are being monitored in some kind of way.
465 */
466typedef struct PGMPHYSHANDLER
467{
468 AVLROGCPHYSNODECORE Core;
469 /** Access type. */
470 PGMPHYSHANDLERTYPE enmType;
471 /** Number of pages to update. */
472 uint32_t cPages;
473 /** Pointer to R3 callback function. */
474 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
475 /** User argument for R3 handlers. */
476 R3PTRTYPE(void *) pvUserR3;
477 /** Pointer to R0 callback function. */
478 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
479 /** User argument for R0 handlers. */
480 R0PTRTYPE(void *) pvUserR0;
481 /** Pointer to RC callback function. */
482 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
483 /** User argument for RC handlers. */
484 RCPTRTYPE(void *) pvUserRC;
485 /** Description / Name. For easing debugging. */
486 R3PTRTYPE(const char *) pszDesc;
487#ifdef VBOX_WITH_STATISTICS
488 /** Profiling of this handler. */
489 STAMPROFILE Stat;
490#endif
491} PGMPHYSHANDLER;
492/** Pointer to a physical page access handler structure. */
493typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
494
495
496/**
497 * Cache node for the physical addresses covered by a virtual handler.
498 */
499typedef struct PGMPHYS2VIRTHANDLER
500{
501 /** Core node for the tree based on physical ranges. */
502 AVLROGCPHYSNODECORE Core;
503 /** Offset from this struct to the PGMVIRTHANDLER structure. */
504 int32_t offVirtHandler;
505 /** Offset of the next alias relative to this one.
506 * Bit 0 is used for indicating whether we're in the tree.
507 * Bit 1 is used for indicating that we're the head node.
508 */
509 int32_t offNextAlias;
510} PGMPHYS2VIRTHANDLER;
511/** Pointer to a phys to virtual handler structure. */
512typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
513
514/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
515 * node is in the tree. */
516#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
517/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
518 * node is in the head of an alias chain.
519 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
520#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
521/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
522#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
523
524
525/**
526 * Virtual page access handler structure.
527 *
528 * This is used to keep track of virtual address ranges
529 * which are being monitored in some kind of way.
530 */
531typedef struct PGMVIRTHANDLER
532{
533 /** Core node for the tree based on virtual ranges. */
534 AVLROGCPTRNODECORE Core;
535 /** Size of the range (in bytes). */
536 RTGCPTR cb;
537 /** Number of cache pages. */
538 uint32_t cPages;
539 /** Access type. */
540 PGMVIRTHANDLERTYPE enmType;
541 /** Pointer to the RC callback function. */
542 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
543#if HC_ARCH_BITS == 64
544 RTRCPTR padding;
545#endif
546 /** Pointer to the R3 callback function for invalidation. */
547 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
548 /** Pointer to the R3 callback function. */
549 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
550 /** Description / Name. For easing debugging. */
551 R3PTRTYPE(const char *) pszDesc;
552#ifdef VBOX_WITH_STATISTICS
553 /** Profiling of this handler. */
554 STAMPROFILE Stat;
555#endif
556 /** Array of cached physical addresses for the monitored ranged. */
557 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
558} PGMVIRTHANDLER;
559/** Pointer to a virtual page access handler structure. */
560typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
561
562
563/**
564 * Page type.
565 *
566 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
567 * @remarks This is used in the saved state, so changes to it requires bumping
568 * the saved state version.
569 * @todo So, convert to \#defines!
570 */
571typedef enum PGMPAGETYPE
572{
573 /** The usual invalid zero entry. */
574 PGMPAGETYPE_INVALID = 0,
575 /** RAM page. (RWX) */
576 PGMPAGETYPE_RAM,
577 /** MMIO2 page. (RWX) */
578 PGMPAGETYPE_MMIO2,
579 /** MMIO2 page aliased over an MMIO page. (RWX)
580 * See PGMHandlerPhysicalPageAlias(). */
581 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
582 /** Shadowed ROM. (RWX) */
583 PGMPAGETYPE_ROM_SHADOW,
584 /** ROM page. (R-X) */
585 PGMPAGETYPE_ROM,
586 /** MMIO page. (---) */
587 PGMPAGETYPE_MMIO,
588 /** End of valid entries. */
589 PGMPAGETYPE_END
590} PGMPAGETYPE;
591AssertCompile(PGMPAGETYPE_END <= 7);
592
593/** @name Page type predicates.
594 * @{ */
595#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
596#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
597#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
598#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
599#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
600/** @} */
601
602
603/**
604 * A Physical Guest Page tracking structure.
605 *
606 * The format of this structure is complicated because we have to fit a lot
607 * of information into as few bits as possible. The format is also subject
608 * to change (there is one comming up soon). Which means that for we'll be
609 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
610 * accessess to the structure.
611 */
612typedef struct PGMPAGE
613{
614 /** The physical address and a whole lot of other stuff. All bits are used! */
615 RTHCPHYS HCPhysX;
616 /** The page state. */
617 uint32_t u2StateX : 2;
618 /** Flag indicating that a write monitored page was written to when set. */
619 uint32_t fWrittenToX : 1;
620 /** For later. */
621 uint32_t fSomethingElse : 1;
622 /** The Page ID.
623 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
624 * The HCPhysX will then be 100% static. */
625 uint32_t idPageX : 28;
626 /** The page type (PGMPAGETYPE). */
627 uint32_t u3Type : 3;
628 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
629 uint32_t u2HandlerPhysStateX : 2;
630 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
631 uint32_t u2HandlerVirtStateX : 2;
632 uint32_t u29B : 25;
633} PGMPAGE;
634AssertCompileSize(PGMPAGE, 16);
635/** Pointer to a physical guest page. */
636typedef PGMPAGE *PPGMPAGE;
637/** Pointer to a const physical guest page. */
638typedef const PGMPAGE *PCPGMPAGE;
639/** Pointer to a physical guest page pointer. */
640typedef PPGMPAGE *PPPGMPAGE;
641
642
643/**
644 * Clears the page structure.
645 * @param pPage Pointer to the physical guest page tracking structure.
646 */
647#define PGM_PAGE_CLEAR(pPage) \
648 do { \
649 (pPage)->HCPhysX = 0; \
650 (pPage)->u2StateX = 0; \
651 (pPage)->fWrittenToX = 0; \
652 (pPage)->fSomethingElse = 0; \
653 (pPage)->idPageX = 0; \
654 (pPage)->u3Type = 0; \
655 (pPage)->u29B = 0; \
656 } while (0)
657
658/**
659 * Initializes the page structure.
660 * @param pPage Pointer to the physical guest page tracking structure.
661 */
662#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
663 do { \
664 (pPage)->HCPhysX = (_HCPhys); \
665 (pPage)->u2StateX = (_uState); \
666 (pPage)->fWrittenToX = 0; \
667 (pPage)->fSomethingElse = 0; \
668 (pPage)->idPageX = (_idPage); \
669 /*(pPage)->u3Type = (_uType); - later */ \
670 PGM_PAGE_SET_TYPE(pPage, _uType); \
671 (pPage)->u29B = 0; \
672 } while (0)
673
674/**
675 * Initializes the page structure of a ZERO page.
676 * @param pPage Pointer to the physical guest page tracking structure.
677 */
678#define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
679 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
680/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
681# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
682 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
683
684
685/** @name The Page state, PGMPAGE::u2StateX.
686 * @{ */
687/** The zero page.
688 * This is a per-VM page that's never ever mapped writable. */
689#define PGM_PAGE_STATE_ZERO 0
690/** A allocated page.
691 * This is a per-VM page allocated from the page pool (or wherever
692 * we get MMIO2 pages from if the type is MMIO2).
693 */
694#define PGM_PAGE_STATE_ALLOCATED 1
695/** A allocated page that's being monitored for writes.
696 * The shadow page table mappings are read-only. When a write occurs, the
697 * fWrittenTo member is set, the page remapped as read-write and the state
698 * moved back to allocated. */
699#define PGM_PAGE_STATE_WRITE_MONITORED 2
700/** The page is shared, aka. copy-on-write.
701 * This is a page that's shared with other VMs. */
702#define PGM_PAGE_STATE_SHARED 3
703/** @} */
704
705
706/**
707 * Gets the page state.
708 * @returns page state (PGM_PAGE_STATE_*).
709 * @param pPage Pointer to the physical guest page tracking structure.
710 */
711#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
712
713/**
714 * Sets the page state.
715 * @param pPage Pointer to the physical guest page tracking structure.
716 * @param _uState The new page state.
717 */
718#define PGM_PAGE_SET_STATE(pPage, _uState) \
719 do { (pPage)->u2StateX = (_uState); } while (0)
720
721
722/**
723 * Gets the host physical address of the guest page.
724 * @returns host physical address (RTHCPHYS).
725 * @param pPage Pointer to the physical guest page tracking structure.
726 */
727#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
728
729/**
730 * Sets the host physical address of the guest page.
731 * @param pPage Pointer to the physical guest page tracking structure.
732 * @param _HCPhys The new host physical address.
733 */
734#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
735 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
736 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
737
738/**
739 * Get the Page ID.
740 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
741 * @param pPage Pointer to the physical guest page tracking structure.
742 */
743#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
744/* later:
745#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
746 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
747*/
748/**
749 * Sets the Page ID.
750 * @param pPage Pointer to the physical guest page tracking structure.
751 */
752#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
753/* later:
754#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
755 | ((_idPage) & 0xfff) \
756 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
757*/
758
759/**
760 * Get the Chunk ID.
761 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
762 * @param pPage Pointer to the physical guest page tracking structure.
763 */
764#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
765/* later:
766#if GMM_CHUNKID_SHIFT == 12
767# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
768#elif GMM_CHUNKID_SHIFT > 12
769# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
770#elif GMM_CHUNKID_SHIFT < 12
771# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
772 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
773#else
774# error "GMM_CHUNKID_SHIFT isn't defined or something."
775#endif
776*/
777
778/**
779 * Get the index of the page within the allocaiton chunk.
780 * @returns The page index.
781 * @param pPage Pointer to the physical guest page tracking structure.
782 */
783#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
784/* later:
785#if GMM_CHUNKID_SHIFT <= 12
786# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
787#else
788# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
789 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
790#endif
791*/
792
793
794/**
795 * Gets the page type.
796 * @returns The page type.
797 * @param pPage Pointer to the physical guest page tracking structure.
798 */
799#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
800
801/**
802 * Sets the page type.
803 * @param pPage Pointer to the physical guest page tracking structure.
804 * @param _enmType The new page type (PGMPAGETYPE).
805 */
806#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
807 do { (pPage)->u3Type = (_enmType); } while (0)
808
809/**
810 * Checks if the page is marked for MMIO.
811 * @returns true/false.
812 * @param pPage Pointer to the physical guest page tracking structure.
813 */
814#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
815
816/**
817 * Checks if the page is backed by the ZERO page.
818 * @returns true/false.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
822
823/**
824 * Checks if the page is backed by a SHARED page.
825 * @returns true/false.
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
829
830
831/**
832 * Marks the paget as written to (for GMM change monitoring).
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
836
837/**
838 * Clears the written-to indicator.
839 * @param pPage Pointer to the physical guest page tracking structure.
840 */
841#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
842
843/**
844 * Checks if the page was marked as written-to.
845 * @returns true/false.
846 * @param pPage Pointer to the physical guest page tracking structure.
847 */
848#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
849
850
851/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
852 *
853 * @remarks The values are assigned in order of priority, so we can calculate
854 * the correct state for a page with different handlers installed.
855 * @{ */
856/** No handler installed. */
857#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
858/** Monitoring is temporarily disabled. */
859#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
860/** Write access is monitored. */
861#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
862/** All access is monitored. */
863#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
864/** @} */
865
866/**
867 * Gets the physical access handler state of a page.
868 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
869 * @param pPage Pointer to the physical guest page tracking structure.
870 */
871#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
872
873/**
874 * Sets the physical access handler state of a page.
875 * @param pPage Pointer to the physical guest page tracking structure.
876 * @param _uState The new state value.
877 */
878#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
879 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
880
881/**
882 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
883 * @returns true/false
884 * @param pPage Pointer to the physical guest page tracking structure.
885 */
886#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
887
888/**
889 * Checks if the page has any active physical access handlers.
890 * @returns true/false
891 * @param pPage Pointer to the physical guest page tracking structure.
892 */
893#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
894
895
896/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
897 *
898 * @remarks The values are assigned in order of priority, so we can calculate
899 * the correct state for a page with different handlers installed.
900 * @{ */
901/** No handler installed. */
902#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
903/* 1 is reserved so the lineup is identical with the physical ones. */
904/** Write access is monitored. */
905#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
906/** All access is monitored. */
907#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
908/** @} */
909
910/**
911 * Gets the virtual access handler state of a page.
912 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
913 * @param pPage Pointer to the physical guest page tracking structure.
914 */
915#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
916
917/**
918 * Sets the virtual access handler state of a page.
919 * @param pPage Pointer to the physical guest page tracking structure.
920 * @param _uState The new state value.
921 */
922#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
923 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
924
925/**
926 * Checks if the page has any virtual access handlers.
927 * @returns true/false
928 * @param pPage Pointer to the physical guest page tracking structure.
929 */
930#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
931
932/**
933 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
934 * virtual handlers.
935 * @returns true/false
936 * @param pPage Pointer to the physical guest page tracking structure.
937 */
938#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
939
940
941
942/**
943 * Checks if the page has any access handlers, including temporarily disabled ones.
944 * @returns true/false
945 * @param pPage Pointer to the physical guest page tracking structure.
946 */
947#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
948 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
949 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
950
951/**
952 * Checks if the page has any active access handlers.
953 * @returns true/false
954 * @param pPage Pointer to the physical guest page tracking structure.
955 */
956#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
957 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
958 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
959
960/**
961 * Checks if the page has any active access handlers catching all accesses.
962 * @returns true/false
963 * @param pPage Pointer to the physical guest page tracking structure.
964 */
965#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
966 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
967 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
968
969
970
971
972/** @def PGM_PAGE_GET_TRACKING
973 * Gets the packed shadow page pool tracking data associated with a guest page.
974 * @returns uint16_t containing the data.
975 * @param pPage Pointer to the physical guest page tracking structure.
976 */
977#define PGM_PAGE_GET_TRACKING(pPage) \
978 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
979
980/** @def PGM_PAGE_SET_TRACKING
981 * Sets the packed shadow page pool tracking data associated with a guest page.
982 * @param pPage Pointer to the physical guest page tracking structure.
983 * @param u16TrackingData The tracking data to store.
984 */
985#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
986 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
987
988/** @def PGM_PAGE_GET_TD_CREFS
989 * Gets the @a cRefs tracking data member.
990 * @returns cRefs.
991 * @param pPage Pointer to the physical guest page tracking structure.
992 */
993#define PGM_PAGE_GET_TD_CREFS(pPage) \
994 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
995
996#define PGM_PAGE_GET_TD_IDX(pPage) \
997 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
998
999/**
1000 * Ram range for GC Phys to HC Phys conversion.
1001 *
1002 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1003 * conversions too, but we'll let MM handle that for now.
1004 *
1005 * This structure is used by linked lists in both GC and HC.
1006 */
1007typedef struct PGMRAMRANGE
1008{
1009 /** Start of the range. Page aligned. */
1010 RTGCPHYS GCPhys;
1011 /** Size of the range. (Page aligned of course). */
1012 RTGCPHYS cb;
1013 /** Pointer to the next RAM range - for R3. */
1014 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1015 /** Pointer to the next RAM range - for R0. */
1016 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1017 /** Pointer to the next RAM range - for RC. */
1018 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1019 /** PGM_RAM_RANGE_FLAGS_* flags. */
1020 uint32_t fFlags;
1021 /** Last address in the range (inclusive). Page aligned (-1). */
1022 RTGCPHYS GCPhysLast;
1023 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1024 R3PTRTYPE(void *) pvR3;
1025 /** The range description. */
1026 R3PTRTYPE(const char *) pszDesc;
1027 /** Pointer to self - R0 pointer. */
1028 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1029 /** Pointer to self - RC pointer. */
1030 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1031 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1032 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 1];
1033 /** Array of physical guest page tracking structures. */
1034 PGMPAGE aPages[1];
1035} PGMRAMRANGE;
1036/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1037typedef PGMRAMRANGE *PPGMRAMRANGE;
1038
1039/** @name PGMRAMRANGE::fFlags
1040 * @{ */
1041/** The RAM range is floating around as an independent guest mapping. */
1042#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1043/** @} */
1044
1045
1046/**
1047 * Per page tracking structure for ROM image.
1048 *
1049 * A ROM image may have a shadow page, in which case we may have
1050 * two pages backing it. This structure contains the PGMPAGE for
1051 * both while PGMRAMRANGE have a copy of the active one. It is
1052 * important that these aren't out of sync in any regard other
1053 * than page pool tracking data.
1054 */
1055typedef struct PGMROMPAGE
1056{
1057 /** The page structure for the virgin ROM page. */
1058 PGMPAGE Virgin;
1059 /** The page structure for the shadow RAM page. */
1060 PGMPAGE Shadow;
1061 /** The current protection setting. */
1062 PGMROMPROT enmProt;
1063 /** Pad the structure size to a multiple of 8. */
1064 uint32_t u32Padding;
1065} PGMROMPAGE;
1066/** Pointer to a ROM page tracking structure. */
1067typedef PGMROMPAGE *PPGMROMPAGE;
1068
1069
1070/**
1071 * A registered ROM image.
1072 *
1073 * This is needed to keep track of ROM image since they generally
1074 * intrude into a PGMRAMRANGE. It also keeps track of additional
1075 * info like the two page sets (read-only virgin and read-write shadow),
1076 * the current state of each page.
1077 *
1078 * Because access handlers cannot easily be executed in a different
1079 * context, the ROM ranges needs to be accessible and in all contexts.
1080 */
1081typedef struct PGMROMRANGE
1082{
1083 /** Pointer to the next range - R3. */
1084 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1085 /** Pointer to the next range - R0. */
1086 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1087 /** Pointer to the next range - RC. */
1088 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1089 /** Pointer alignment */
1090 RTRCPTR GCPtrAlignment;
1091 /** Address of the range. */
1092 RTGCPHYS GCPhys;
1093 /** Address of the last byte in the range. */
1094 RTGCPHYS GCPhysLast;
1095 /** Size of the range. */
1096 RTGCPHYS cb;
1097 /** The flags (PGMPHYS_ROM_FLAG_*). */
1098 uint32_t fFlags;
1099 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1100 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1101 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1102 * This is used for strictness checks. */
1103 R3PTRTYPE(const void *) pvOriginal;
1104 /** The ROM description. */
1105 R3PTRTYPE(const char *) pszDesc;
1106 /** The per page tracking structures. */
1107 PGMROMPAGE aPages[1];
1108} PGMROMRANGE;
1109/** Pointer to a ROM range. */
1110typedef PGMROMRANGE *PPGMROMRANGE;
1111
1112
1113/**
1114 * A registered MMIO2 (= Device RAM) range.
1115 *
1116 * There are a few reason why we need to keep track of these
1117 * registrations. One of them is the deregistration & cleanup
1118 * stuff, while another is that the PGMRAMRANGE associated with
1119 * such a region may have to be removed from the ram range list.
1120 *
1121 * Overlapping with a RAM range has to be 100% or none at all. The
1122 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1123 * meditation will be raised if a partial overlap or an overlap of
1124 * ROM pages is encountered. On an overlap we will free all the
1125 * existing RAM pages and put in the ram range pages instead.
1126 */
1127typedef struct PGMMMIO2RANGE
1128{
1129 /** The owner of the range. (a device) */
1130 PPDMDEVINSR3 pDevInsR3;
1131 /** Pointer to the ring-3 mapping of the allocation. */
1132 RTR3PTR pvR3;
1133 /** Pointer to the next range - R3. */
1134 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1135 /** Whether it's mapped or not. */
1136 bool fMapped;
1137 /** Whether it's overlapping or not. */
1138 bool fOverlapping;
1139 /** The PCI region number.
1140 * @remarks This ASSUMES that nobody will ever really need to have multiple
1141 * PCI devices with matching MMIO region numbers on a single device. */
1142 uint8_t iRegion;
1143 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1144 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1145 /** The associated RAM range. */
1146 PGMRAMRANGE RamRange;
1147} PGMMMIO2RANGE;
1148/** Pointer to a MMIO2 range. */
1149typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1150
1151
1152
1153
1154/**
1155 * PGMPhysRead/Write cache entry
1156 */
1157typedef struct PGMPHYSCACHEENTRY
1158{
1159 /** R3 pointer to physical page. */
1160 R3PTRTYPE(uint8_t *) pbR3;
1161 /** GC Physical address for cache entry */
1162 RTGCPHYS GCPhys;
1163#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1164 RTGCPHYS u32Padding0; /**< alignment padding. */
1165#endif
1166} PGMPHYSCACHEENTRY;
1167
1168/**
1169 * PGMPhysRead/Write cache to reduce REM memory access overhead
1170 */
1171typedef struct PGMPHYSCACHE
1172{
1173 /** Bitmap of valid cache entries */
1174 uint64_t aEntries;
1175 /** Cache entries */
1176 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1177} PGMPHYSCACHE;
1178
1179
1180/** Pointer to an allocation chunk ring-3 mapping. */
1181typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1182/** Pointer to an allocation chunk ring-3 mapping pointer. */
1183typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1184
1185/**
1186 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1187 *
1188 * The primary tree (Core) uses the chunk id as key.
1189 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1190 */
1191typedef struct PGMCHUNKR3MAP
1192{
1193 /** The key is the chunk id. */
1194 AVLU32NODECORE Core;
1195 /** The key is the ageing sequence number. */
1196 AVLLU32NODECORE AgeCore;
1197 /** The current age thingy. */
1198 uint32_t iAge;
1199 /** The current reference count. */
1200 uint32_t volatile cRefs;
1201 /** The current permanent reference count. */
1202 uint32_t volatile cPermRefs;
1203 /** The mapping address. */
1204 void *pv;
1205} PGMCHUNKR3MAP;
1206
1207/**
1208 * Allocation chunk ring-3 mapping TLB entry.
1209 */
1210typedef struct PGMCHUNKR3MAPTLBE
1211{
1212 /** The chunk id. */
1213 uint32_t volatile idChunk;
1214#if HC_ARCH_BITS == 64
1215 uint32_t u32Padding; /**< alignment padding. */
1216#endif
1217 /** The chunk map. */
1218#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1219 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1220#else
1221 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1222#endif
1223} PGMCHUNKR3MAPTLBE;
1224/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1225typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1226
1227/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1228 * @remark Must be a power of two value. */
1229#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1230
1231/**
1232 * Allocation chunk ring-3 mapping TLB.
1233 *
1234 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1235 * At first glance this might look kinda odd since AVL trees are
1236 * supposed to give the most optimial lookup times of all trees
1237 * due to their balancing. However, take a tree with 1023 nodes
1238 * in it, that's 10 levels, meaning that most searches has to go
1239 * down 9 levels before they find what they want. This isn't fast
1240 * compared to a TLB hit. There is the factor of cache misses,
1241 * and of course the problem with trees and branch prediction.
1242 * This is why we use TLBs in front of most of the trees.
1243 *
1244 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1245 * difficult when we switch to the new inlined AVL trees (from kStuff).
1246 */
1247typedef struct PGMCHUNKR3MAPTLB
1248{
1249 /** The TLB entries. */
1250 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1251} PGMCHUNKR3MAPTLB;
1252
1253/**
1254 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1255 * @returns Chunk TLB index.
1256 * @param idChunk The Chunk ID.
1257 */
1258#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1259
1260
1261/**
1262 * Ring-3 guest page mapping TLB entry.
1263 * @remarks used in ring-0 as well at the moment.
1264 */
1265typedef struct PGMPAGER3MAPTLBE
1266{
1267 /** Address of the page. */
1268 RTGCPHYS volatile GCPhys;
1269 /** The guest page. */
1270#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1271 R3PTRTYPE(PPGMPAGE) volatile pPage;
1272#else
1273 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1274#endif
1275 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1276#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1277 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1278#else
1279 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1280#endif
1281 /** The address */
1282#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1283 R3PTRTYPE(void *) volatile pv;
1284#else
1285 R3R0PTRTYPE(void *) volatile pv;
1286#endif
1287#if HC_ARCH_BITS == 32
1288 uint32_t u32Padding; /**< alignment padding. */
1289#endif
1290} PGMPAGER3MAPTLBE;
1291/** Pointer to an entry in the HC physical TLB. */
1292typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1293
1294
1295/** The number of entries in the ring-3 guest page mapping TLB.
1296 * @remarks The value must be a power of two. */
1297#define PGM_PAGER3MAPTLB_ENTRIES 64
1298
1299/**
1300 * Ring-3 guest page mapping TLB.
1301 * @remarks used in ring-0 as well at the moment.
1302 */
1303typedef struct PGMPAGER3MAPTLB
1304{
1305 /** The TLB entries. */
1306 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1307} PGMPAGER3MAPTLB;
1308/** Pointer to the ring-3 guest page mapping TLB. */
1309typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1310
1311/**
1312 * Calculates the index of the TLB entry for the specified guest page.
1313 * @returns Physical TLB index.
1314 * @param GCPhys The guest physical address.
1315 */
1316#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1317
1318
1319/**
1320 * Mapping cache usage set entry.
1321 *
1322 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1323 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1324 * cache. If it's extended to include ring-3, well, then something will
1325 * have be changed here...
1326 */
1327typedef struct PGMMAPSETENTRY
1328{
1329 /** The mapping cache index. */
1330 uint16_t iPage;
1331 /** The number of references.
1332 * The max is UINT16_MAX - 1. */
1333 uint16_t cRefs;
1334#if HC_ARCH_BITS == 64
1335 uint32_t alignment;
1336#endif
1337 /** Pointer to the page. */
1338 RTR0PTR pvPage;
1339 /** The physical address for this entry. */
1340 RTHCPHYS HCPhys;
1341} PGMMAPSETENTRY;
1342/** Pointer to a mapping cache usage set entry. */
1343typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1344
1345/**
1346 * Mapping cache usage set.
1347 *
1348 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1349 * done during exits / traps. The set is
1350 */
1351typedef struct PGMMAPSET
1352{
1353 /** The number of occupied entries.
1354 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1355 * dynamic mappings. */
1356 uint32_t cEntries;
1357 /** The start of the current subset.
1358 * This is UINT32_MAX if no subset is currently open. */
1359 uint32_t iSubset;
1360 /** The index of the current CPU, only valid if the set is open. */
1361 int32_t iCpu;
1362#if HC_ARCH_BITS == 64
1363 uint32_t alignment;
1364#endif
1365 /** The entries. */
1366 PGMMAPSETENTRY aEntries[64];
1367 /** HCPhys -> iEntry fast lookup table.
1368 * Use PGMMAPSET_HASH for hashing.
1369 * The entries may or may not be valid, check against cEntries. */
1370 uint8_t aiHashTable[128];
1371} PGMMAPSET;
1372/** Pointer to the mapping cache set. */
1373typedef PGMMAPSET *PPGMMAPSET;
1374
1375/** PGMMAPSET::cEntries value for a closed set. */
1376#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1377
1378/** Hash function for aiHashTable. */
1379#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1380
1381/** The max fill size (strict builds). */
1382#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1383
1384
1385/** @name Context neutrual page mapper TLB.
1386 *
1387 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1388 * code is writting in a kind of context neutrual way. Time will show whether
1389 * this actually makes sense or not...
1390 *
1391 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1392 * context ends up using a global mapping cache on some platforms
1393 * (darwin).
1394 *
1395 * @{ */
1396/** @typedef PPGMPAGEMAPTLB
1397 * The page mapper TLB pointer type for the current context. */
1398/** @typedef PPGMPAGEMAPTLB
1399 * The page mapper TLB entry pointer type for the current context. */
1400/** @typedef PPGMPAGEMAPTLB
1401 * The page mapper TLB entry pointer pointer type for the current context. */
1402/** @def PGM_PAGEMAPTLB_ENTRIES
1403 * The number of TLB entries in the page mapper TLB for the current context. */
1404/** @def PGM_PAGEMAPTLB_IDX
1405 * Calculate the TLB index for a guest physical address.
1406 * @returns The TLB index.
1407 * @param GCPhys The guest physical address. */
1408/** @typedef PPGMPAGEMAP
1409 * Pointer to a page mapper unit for current context. */
1410/** @typedef PPPGMPAGEMAP
1411 * Pointer to a page mapper unit pointer for current context. */
1412#ifdef IN_RC
1413// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1414// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1415// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1416# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1417# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1418 typedef void * PPGMPAGEMAP;
1419 typedef void ** PPPGMPAGEMAP;
1420//#elif IN_RING0
1421// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1422// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1423// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1424//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1425//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1426// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1427// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1428#else
1429 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1430 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1431 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1432# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1433# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1434 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1435 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1436#endif
1437/** @} */
1438
1439
1440/** @name PGM Pool Indexes.
1441 * Aka. the unique shadow page identifier.
1442 * @{ */
1443/** NIL page pool IDX. */
1444#define NIL_PGMPOOL_IDX 0
1445/** The first normal index. */
1446#define PGMPOOL_IDX_FIRST_SPECIAL 1
1447/** Page directory (32-bit root). */
1448#define PGMPOOL_IDX_PD 1
1449/** Page Directory Pointer Table (PAE root). */
1450#define PGMPOOL_IDX_PDPT 2
1451/** AMD64 CR3 level index.*/
1452#define PGMPOOL_IDX_AMD64_CR3 3
1453/** Nested paging root.*/
1454#define PGMPOOL_IDX_NESTED_ROOT 4
1455/** The first normal index. */
1456#define PGMPOOL_IDX_FIRST 5
1457/** The last valid index. (inclusive, 14 bits) */
1458#define PGMPOOL_IDX_LAST 0x3fff
1459/** @} */
1460
1461/** The NIL index for the parent chain. */
1462#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1463
1464/**
1465 * Node in the chain linking a shadowed page to it's parent (user).
1466 */
1467#pragma pack(1)
1468typedef struct PGMPOOLUSER
1469{
1470 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1471 uint16_t iNext;
1472 /** The user page index. */
1473 uint16_t iUser;
1474 /** Index into the user table. */
1475 uint32_t iUserTable;
1476} PGMPOOLUSER, *PPGMPOOLUSER;
1477typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1478#pragma pack()
1479
1480
1481/** The NIL index for the phys ext chain. */
1482#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1483
1484/**
1485 * Node in the chain of physical cross reference extents.
1486 * @todo Calling this an 'extent' is not quite right, find a better name.
1487 */
1488#pragma pack(1)
1489typedef struct PGMPOOLPHYSEXT
1490{
1491 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1492 uint16_t iNext;
1493 /** The user page index. */
1494 uint16_t aidx[3];
1495} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1496typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1497#pragma pack()
1498
1499
1500/**
1501 * The kind of page that's being shadowed.
1502 */
1503typedef enum PGMPOOLKIND
1504{
1505 /** The virtual invalid 0 entry. */
1506 PGMPOOLKIND_INVALID = 0,
1507 /** The entry is free (=unused). */
1508 PGMPOOLKIND_FREE,
1509
1510 /** Shw: 32-bit page table; Gst: no paging */
1511 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1512 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1513 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1514 /** Shw: 32-bit page table; Gst: 4MB page. */
1515 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1516 /** Shw: PAE page table; Gst: no paging */
1517 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1518 /** Shw: PAE page table; Gst: 32-bit page table. */
1519 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1520 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1521 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1522 /** Shw: PAE page table; Gst: PAE page table. */
1523 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1524 /** Shw: PAE page table; Gst: 2MB page. */
1525 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1526
1527 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1528 PGMPOOLKIND_32BIT_PD,
1529 /** Shw: 32-bit page directory. Gst: no paging. */
1530 PGMPOOLKIND_32BIT_PD_PHYS,
1531 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1532 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1533 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1534 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1535 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1536 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1537 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1538 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1539 /** Shw: PAE page directory; Gst: PAE page directory. */
1540 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1541 /** Shw: PAE page directory; Gst: no paging. */
1542 PGMPOOLKIND_PAE_PD_PHYS,
1543
1544 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1545 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1546 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1547 PGMPOOLKIND_PAE_PDPT,
1548 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1549 PGMPOOLKIND_PAE_PDPT_PHYS,
1550
1551 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1552 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1553 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1554 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1555 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1556 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1557 /** Shw: 64-bit page directory table; Gst: no paging */
1558 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1559
1560 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1561 PGMPOOLKIND_64BIT_PML4,
1562
1563 /** Shw: EPT page directory pointer table; Gst: no paging */
1564 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1565 /** Shw: EPT page directory table; Gst: no paging */
1566 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1567 /** Shw: EPT page table; Gst: no paging */
1568 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1569
1570 /** Shw: Root Nested paging table. */
1571 PGMPOOLKIND_ROOT_NESTED,
1572
1573 /** The last valid entry. */
1574 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1575} PGMPOOLKIND;
1576
1577/**
1578 * The access attributes of the page; only applies to big pages.
1579 */
1580typedef enum
1581{
1582 PGMPOOLACCESS_DONTCARE = 0,
1583 PGMPOOLACCESS_USER_RW,
1584 PGMPOOLACCESS_USER_R,
1585 PGMPOOLACCESS_USER_RW_NX,
1586 PGMPOOLACCESS_USER_R_NX,
1587 PGMPOOLACCESS_SUPERVISOR_RW,
1588 PGMPOOLACCESS_SUPERVISOR_R,
1589 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1590 PGMPOOLACCESS_SUPERVISOR_R_NX
1591} PGMPOOLACCESS;
1592
1593/**
1594 * The tracking data for a page in the pool.
1595 */
1596typedef struct PGMPOOLPAGE
1597{
1598 /** AVL node code with the (R3) physical address of this page. */
1599 AVLOHCPHYSNODECORE Core;
1600 /** Pointer to the R3 mapping of the page. */
1601#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1602 R3PTRTYPE(void *) pvPageR3;
1603#else
1604 R3R0PTRTYPE(void *) pvPageR3;
1605#endif
1606 /** The guest physical address. */
1607#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1608 uint32_t Alignment0;
1609#endif
1610 RTGCPHYS GCPhys;
1611
1612 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1613 RTGCPTR pvLastAccessHandlerRip;
1614 RTGCPTR pvLastAccessHandlerFault;
1615 uint64_t cLastAccessHandlerCount;
1616
1617 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1618 uint8_t enmKind;
1619 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1620 uint8_t enmAccess;
1621 /** The index of this page. */
1622 uint16_t idx;
1623 /** The next entry in the list this page currently resides in.
1624 * It's either in the free list or in the GCPhys hash. */
1625 uint16_t iNext;
1626#ifdef PGMPOOL_WITH_USER_TRACKING
1627 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1628 uint16_t iUserHead;
1629 /** The number of present entries. */
1630 uint16_t cPresent;
1631 /** The first entry in the table which is present. */
1632 uint16_t iFirstPresent;
1633#endif
1634#ifdef PGMPOOL_WITH_MONITORING
1635 /** The number of modifications to the monitored page. */
1636 uint16_t cModifications;
1637 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1638 uint16_t iModifiedNext;
1639 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1640 uint16_t iModifiedPrev;
1641 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1642 uint16_t iMonitoredNext;
1643 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1644 uint16_t iMonitoredPrev;
1645#endif
1646#ifdef PGMPOOL_WITH_CACHE
1647 /** The next page in the age list. */
1648 uint16_t iAgeNext;
1649 /** The previous page in the age list. */
1650 uint16_t iAgePrev;
1651#endif /* PGMPOOL_WITH_CACHE */
1652 /** Used to indicate that the page is zeroed. */
1653 bool fZeroed;
1654 /** Used to indicate that a PT has non-global entries. */
1655 bool fSeenNonGlobal;
1656 /** Used to indicate that we're monitoring writes to the guest page. */
1657 bool fMonitored;
1658 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1659 * (All pages are in the age list.) */
1660 bool fCached;
1661 /** This is used by the R3 access handlers when invoked by an async thread.
1662 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1663 bool volatile fReusedFlushPending;
1664 bool bPadding1;
1665
1666 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1667 uint32_t cLocked;
1668 uint32_t bPadding2;
1669} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1670/** Pointer to a const pool page. */
1671typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1672
1673
1674#ifdef PGMPOOL_WITH_CACHE
1675/** The hash table size. */
1676# define PGMPOOL_HASH_SIZE 0x40
1677/** The hash function. */
1678# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1679#endif
1680
1681
1682/**
1683 * The shadow page pool instance data.
1684 *
1685 * It's all one big allocation made at init time, except for the
1686 * pages that is. The user nodes follows immediatly after the
1687 * page structures.
1688 */
1689typedef struct PGMPOOL
1690{
1691 /** The VM handle - R3 Ptr. */
1692 PVMR3 pVMR3;
1693 /** The VM handle - R0 Ptr. */
1694 PVMR0 pVMR0;
1695 /** The VM handle - RC Ptr. */
1696 PVMRC pVMRC;
1697 /** The max pool size. This includes the special IDs. */
1698 uint16_t cMaxPages;
1699 /** The current pool size. */
1700 uint16_t cCurPages;
1701 /** The head of the free page list. */
1702 uint16_t iFreeHead;
1703 /* Padding. */
1704 uint16_t u16Padding;
1705#ifdef PGMPOOL_WITH_USER_TRACKING
1706 /** Head of the chain of free user nodes. */
1707 uint16_t iUserFreeHead;
1708 /** The number of user nodes we've allocated. */
1709 uint16_t cMaxUsers;
1710 /** The number of present page table entries in the entire pool. */
1711 uint32_t cPresent;
1712 /** Pointer to the array of user nodes - RC pointer. */
1713 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1714 /** Pointer to the array of user nodes - R3 pointer. */
1715 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1716 /** Pointer to the array of user nodes - R0 pointer. */
1717 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1718#endif /* PGMPOOL_WITH_USER_TRACKING */
1719#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1720 /** Head of the chain of free phys ext nodes. */
1721 uint16_t iPhysExtFreeHead;
1722 /** The number of user nodes we've allocated. */
1723 uint16_t cMaxPhysExts;
1724 /** Pointer to the array of physical xref extent - RC pointer. */
1725 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1726 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1727 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1728 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1729 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1730#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1731#ifdef PGMPOOL_WITH_CACHE
1732 /** Hash table for GCPhys addresses. */
1733 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1734 /** The head of the age list. */
1735 uint16_t iAgeHead;
1736 /** The tail of the age list. */
1737 uint16_t iAgeTail;
1738 /** Set if the cache is enabled. */
1739 bool fCacheEnabled;
1740#endif /* PGMPOOL_WITH_CACHE */
1741#ifdef PGMPOOL_WITH_MONITORING
1742 /** Head of the list of modified pages. */
1743 uint16_t iModifiedHead;
1744 /** The current number of modified pages. */
1745 uint16_t cModifiedPages;
1746 /** Access handler, RC. */
1747 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1748 /** Access handler, R0. */
1749 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1750 /** Access handler, R3. */
1751 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1752 /** The access handler description (HC ptr). */
1753 R3PTRTYPE(const char *) pszAccessHandler;
1754#endif /* PGMPOOL_WITH_MONITORING */
1755 /** The number of pages currently in use. */
1756 uint16_t cUsedPages;
1757#ifdef VBOX_WITH_STATISTICS
1758 /** The high wather mark for cUsedPages. */
1759 uint16_t cUsedPagesHigh;
1760 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1761 /** Profiling pgmPoolAlloc(). */
1762 STAMPROFILEADV StatAlloc;
1763 /** Profiling pgmPoolClearAll(). */
1764 STAMPROFILE StatClearAll;
1765 /** Profiling pgmPoolFlushAllInt(). */
1766 STAMPROFILE StatFlushAllInt;
1767 /** Profiling pgmPoolFlushPage(). */
1768 STAMPROFILE StatFlushPage;
1769 /** Profiling pgmPoolFree(). */
1770 STAMPROFILE StatFree;
1771 /** Profiling time spent zeroing pages. */
1772 STAMPROFILE StatZeroPage;
1773# ifdef PGMPOOL_WITH_USER_TRACKING
1774 /** Profiling of pgmPoolTrackDeref. */
1775 STAMPROFILE StatTrackDeref;
1776 /** Profiling pgmTrackFlushGCPhysPT. */
1777 STAMPROFILE StatTrackFlushGCPhysPT;
1778 /** Profiling pgmTrackFlushGCPhysPTs. */
1779 STAMPROFILE StatTrackFlushGCPhysPTs;
1780 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1781 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1782 /** Number of times we've been out of user records. */
1783 STAMCOUNTER StatTrackFreeUpOneUser;
1784# endif
1785# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1786 /** Profiling deref activity related tracking GC physical pages. */
1787 STAMPROFILE StatTrackDerefGCPhys;
1788 /** Number of linear searches for a HCPhys in the ram ranges. */
1789 STAMCOUNTER StatTrackLinearRamSearches;
1790 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1791 STAMCOUNTER StamTrackPhysExtAllocFailures;
1792# endif
1793# ifdef PGMPOOL_WITH_MONITORING
1794 /** Profiling the RC/R0 access handler. */
1795 STAMPROFILE StatMonitorRZ;
1796 /** Times we've failed interpreting the instruction. */
1797 STAMCOUNTER StatMonitorRZEmulateInstr;
1798 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1799 STAMPROFILE StatMonitorRZFlushPage;
1800 /* Times we've detected a page table reinit. */
1801 STAMCOUNTER StatMonitorRZFlushReinit;
1802 /** Times we've detected fork(). */
1803 STAMCOUNTER StatMonitorRZFork;
1804 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1805 STAMPROFILE StatMonitorRZHandled;
1806 /** Times we've failed interpreting a patch code instruction. */
1807 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1808 /** Times we've failed interpreting a patch code instruction during flushing. */
1809 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1810 /** The number of times we've seen rep prefixes we can't handle. */
1811 STAMCOUNTER StatMonitorRZRepPrefix;
1812 /** Profiling the REP STOSD cases we've handled. */
1813 STAMPROFILE StatMonitorRZRepStosd;
1814
1815 /** Profiling the R3 access handler. */
1816 STAMPROFILE StatMonitorR3;
1817 /** Times we've failed interpreting the instruction. */
1818 STAMCOUNTER StatMonitorR3EmulateInstr;
1819 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1820 STAMPROFILE StatMonitorR3FlushPage;
1821 /* Times we've detected a page table reinit. */
1822 STAMCOUNTER StatMonitorR3FlushReinit;
1823 /** Times we've detected fork(). */
1824 STAMCOUNTER StatMonitorR3Fork;
1825 /** Profiling the R3 access we've handled (except REP STOSD). */
1826 STAMPROFILE StatMonitorR3Handled;
1827 /** The number of times we've seen rep prefixes we can't handle. */
1828 STAMCOUNTER StatMonitorR3RepPrefix;
1829 /** Profiling the REP STOSD cases we've handled. */
1830 STAMPROFILE StatMonitorR3RepStosd;
1831 /** The number of times we're called in an async thread an need to flush. */
1832 STAMCOUNTER StatMonitorR3Async;
1833 /** The high wather mark for cModifiedPages. */
1834 uint16_t cModifiedPagesHigh;
1835 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1836# endif
1837# ifdef PGMPOOL_WITH_CACHE
1838 /** The number of cache hits. */
1839 STAMCOUNTER StatCacheHits;
1840 /** The number of cache misses. */
1841 STAMCOUNTER StatCacheMisses;
1842 /** The number of times we've got a conflict of 'kind' in the cache. */
1843 STAMCOUNTER StatCacheKindMismatches;
1844 /** Number of times we've been out of pages. */
1845 STAMCOUNTER StatCacheFreeUpOne;
1846 /** The number of cacheable allocations. */
1847 STAMCOUNTER StatCacheCacheable;
1848 /** The number of uncacheable allocations. */
1849 STAMCOUNTER StatCacheUncacheable;
1850# endif
1851#elif HC_ARCH_BITS == 64
1852 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1853#endif
1854 /** The AVL tree for looking up a page by its HC physical address. */
1855 AVLOHCPHYSTREE HCPhysTree;
1856 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1857 /** Array of pages. (cMaxPages in length)
1858 * The Id is the index into thist array.
1859 */
1860 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1861} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1862
1863
1864/** @def PGMPOOL_PAGE_2_PTR
1865 * Maps a pool page pool into the current context.
1866 *
1867 * @returns VBox status code.
1868 * @param pVM The VM handle.
1869 * @param pPage The pool page.
1870 *
1871 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1872 * small page window employeed by that function. Be careful.
1873 * @remark There is no need to assert on the result.
1874 */
1875#if defined(IN_RC)
1876# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1877#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1878# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1879#elif defined(VBOX_STRICT)
1880# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1881DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1882{
1883 Assert(pPage && pPage->pvPageR3);
1884 return pPage->pvPageR3;
1885}
1886#else
1887# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1888#endif
1889
1890/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1891 * Maps a pool page pool into the current context.
1892 *
1893 * @returns VBox status code.
1894 * @param pPGM Pointer to the PGM instance data.
1895 * @param pPage The pool page.
1896 *
1897 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1898 * small page window employeed by that function. Be careful.
1899 * @remark There is no need to assert on the result.
1900 */
1901#if defined(IN_RC)
1902# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1903#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1904# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1905#else
1906# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1907#endif
1908
1909/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
1910 * Maps a pool page pool into the current context.
1911 *
1912 * @returns VBox status code.
1913 * @param pPGM Pointer to the PGMCPU instance data.
1914 * @param pPage The pool page.
1915 *
1916 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1917 * small page window employeed by that function. Be careful.
1918 * @remark There is no need to assert on the result.
1919 */
1920#if defined(IN_RC)
1921# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1922#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1923# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1924#else
1925# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
1926#endif
1927
1928
1929/** @name Per guest page tracking data.
1930 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1931 * is to use more bits for it and split it up later on. But for now we'll play
1932 * safe and change as little as possible.
1933 *
1934 * The 16-bit word has two parts:
1935 *
1936 * The first 14-bit forms the @a idx field. It is either the index of a page in
1937 * the shadow page pool, or and index into the extent list.
1938 *
1939 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1940 * shadow page pool references to the page. If cRefs equals
1941 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1942 * (misnomer) table and not the shadow page pool.
1943 *
1944 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1945 * the 16-bit word.
1946 *
1947 * @{ */
1948/** The shift count for getting to the cRefs part. */
1949#define PGMPOOL_TD_CREFS_SHIFT 14
1950/** The mask applied after shifting the tracking data down by
1951 * PGMPOOL_TD_CREFS_SHIFT. */
1952#define PGMPOOL_TD_CREFS_MASK 0x3
1953/** The cRef value used to indiciate that the idx is the head of a
1954 * physical cross reference list. */
1955#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1956/** The shift used to get idx. */
1957#define PGMPOOL_TD_IDX_SHIFT 0
1958/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1959#define PGMPOOL_TD_IDX_MASK 0x3fff
1960/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1961 * simply too many mappings of this page. */
1962#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1963
1964/** @def PGMPOOL_TD_MAKE
1965 * Makes a 16-bit tracking data word.
1966 *
1967 * @returns tracking data.
1968 * @param cRefs The @a cRefs field. Must be within bounds!
1969 * @param idx The @a idx field. Must also be within bounds! */
1970#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
1971
1972/** @def PGMPOOL_TD_GET_CREFS
1973 * Get the @a cRefs field from a tracking data word.
1974 *
1975 * @returns The @a cRefs field
1976 * @param u16 The tracking data word. */
1977#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1978
1979/** @def PGMPOOL_TD_GET_IDX
1980 * Get the @a idx field from a tracking data word.
1981 *
1982 * @returns The @a idx field
1983 * @param u16 The tracking data word. */
1984#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1985/** @} */
1986
1987
1988/**
1989 * Trees are using self relative offsets as pointers.
1990 * So, all its data, including the root pointer, must be in the heap for HC and GC
1991 * to have the same layout.
1992 */
1993typedef struct PGMTREES
1994{
1995 /** Physical access handlers (AVL range+offsetptr tree). */
1996 AVLROGCPHYSTREE PhysHandlers;
1997 /** Virtual access handlers (AVL range + GC ptr tree). */
1998 AVLROGCPTRTREE VirtHandlers;
1999 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2000 AVLROGCPHYSTREE PhysToVirtHandlers;
2001 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2002 AVLROGCPTRTREE HyperVirtHandlers;
2003} PGMTREES;
2004/** Pointer to PGM trees. */
2005typedef PGMTREES *PPGMTREES;
2006
2007
2008/** @name Paging mode macros
2009 * @{ */
2010#ifdef IN_RC
2011# define PGM_CTX(a,b) a##RC##b
2012# define PGM_CTX_STR(a,b) a "GC" b
2013# define PGM_CTX_DECL(type) VMMRCDECL(type)
2014#else
2015# ifdef IN_RING3
2016# define PGM_CTX(a,b) a##R3##b
2017# define PGM_CTX_STR(a,b) a "R3" b
2018# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2019# else
2020# define PGM_CTX(a,b) a##R0##b
2021# define PGM_CTX_STR(a,b) a "R0" b
2022# define PGM_CTX_DECL(type) VMMDECL(type)
2023# endif
2024#endif
2025
2026#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2027#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2028#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2029#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2030#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2031#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2032#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2033#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2034#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2035#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2036#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2037#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2038#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2039#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2040#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2041#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2042#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2043
2044#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2045#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2046#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2047#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2048#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2049#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2050#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2051#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2052#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2053#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2054#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2055#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2056#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2057#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2058#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2059#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2060#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2061
2062/* Shw_Gst */
2063#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2064#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2065#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2066#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2067#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2068#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2069#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2070#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2071#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2072#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2073#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2074#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2075#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2076#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2077#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2078#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2079#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2080#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2081#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2082
2083#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2084#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2085#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2086#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2087#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2088#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2089#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2090#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2091#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2092#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2093#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2094#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2095#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2096#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2097#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2098#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2099#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2100#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2101#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2102#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2103#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2104#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2105#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2106#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2107#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2108#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2109#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2110#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2111#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2112#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2113#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2114#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2115#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2116#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2117#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2118#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2119#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2120
2121#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2122#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2123/** @} */
2124
2125/**
2126 * Data for each paging mode.
2127 */
2128typedef struct PGMMODEDATA
2129{
2130 /** The guest mode type. */
2131 uint32_t uGstType;
2132 /** The shadow mode type. */
2133 uint32_t uShwType;
2134
2135 /** @name Function pointers for Shadow paging.
2136 * @{
2137 */
2138 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2139 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2140 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2141 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2142
2143 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2144 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2145
2146 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2147 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2148 /** @} */
2149
2150 /** @name Function pointers for Guest paging.
2151 * @{
2152 */
2153 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2154 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2155 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2156 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2157 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2158 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2159 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2160 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2161 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2162 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2163 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2164 /** @} */
2165
2166 /** @name Function pointers for Both Shadow and Guest paging.
2167 * @{
2168 */
2169 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2170 /* no pfnR3BthTrap0eHandler */
2171 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2172 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2173 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2174 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2175 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2176#ifdef VBOX_STRICT
2177 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2178#endif
2179 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2180 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2181
2182 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2183 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2184 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2185 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2186 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2187 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2188#ifdef VBOX_STRICT
2189 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2190#endif
2191 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2192 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2193
2194 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2195 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2196 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2197 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2198 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2199 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2200#ifdef VBOX_STRICT
2201 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2202#endif
2203 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2204 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2205 /** @} */
2206} PGMMODEDATA, *PPGMMODEDATA;
2207
2208
2209
2210/**
2211 * Converts a PGM pointer into a VM pointer.
2212 * @returns Pointer to the VM structure the PGM is part of.
2213 * @param pPGM Pointer to PGM instance data.
2214 */
2215#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2216
2217/**
2218 * PGM Data (part of VM)
2219 */
2220typedef struct PGM
2221{
2222 /** Offset to the VM structure. */
2223 RTINT offVM;
2224 /** Offset of the PGMCPU structure relative to VMCPU. */
2225 RTINT offVCpuPGM;
2226
2227 /** @cfgm{RamPreAlloc, boolean, false}
2228 * Indicates whether the base RAM should all be allocated before starting
2229 * the VM (default), or if it should be allocated when first written to.
2230 */
2231 bool fRamPreAlloc;
2232 /** Alignment padding. */
2233 bool afAlignment0[11];
2234
2235 /*
2236 * This will be redefined at least two more times before we're done, I'm sure.
2237 * The current code is only to get on with the coding.
2238 * - 2004-06-10: initial version, bird.
2239 * - 2004-07-02: 1st time, bird.
2240 * - 2004-10-18: 2nd time, bird.
2241 * - 2005-07-xx: 3rd time, bird.
2242 */
2243
2244 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2245 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2246 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2247 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2248
2249 /** The host paging mode. (This is what SUPLib reports.) */
2250 SUPPAGINGMODE enmHostMode;
2251
2252 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2253 RTGCPHYS GCPhys4MBPSEMask;
2254
2255 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2256 * This is sorted by physical address and contains no overlapping ranges. */
2257 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2258 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2259 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2260 /** RC pointer corresponding to PGM::pRamRangesR3. */
2261 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2262 RTRCPTR alignment4; /**< structure alignment. */
2263
2264 /** Pointer to the list of ROM ranges - for R3.
2265 * This is sorted by physical address and contains no overlapping ranges. */
2266 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2267 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2268 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2269 /** RC pointer corresponding to PGM::pRomRangesR3. */
2270 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2271 /** Alignment padding. */
2272 RTRCPTR GCPtrPadding2;
2273
2274 /** Pointer to the list of MMIO2 ranges - for R3.
2275 * Registration order. */
2276 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2277
2278 /** PGM offset based trees - R3 Ptr. */
2279 R3PTRTYPE(PPGMTREES) pTreesR3;
2280 /** PGM offset based trees - R0 Ptr. */
2281 R0PTRTYPE(PPGMTREES) pTreesR0;
2282 /** PGM offset based trees - RC Ptr. */
2283 RCPTRTYPE(PPGMTREES) pTreesRC;
2284
2285 /** Linked list of GC mappings - for RC.
2286 * The list is sorted ascending on address.
2287 */
2288 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2289 /** Linked list of GC mappings - for HC.
2290 * The list is sorted ascending on address.
2291 */
2292 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2293 /** Linked list of GC mappings - for R0.
2294 * The list is sorted ascending on address.
2295 */
2296 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2297
2298 /** Pointer to the 5 page CR3 content mapping.
2299 * The first page is always the CR3 (in some form) while the 4 other pages
2300 * are used of the PDs in PAE mode. */
2301 RTGCPTR GCPtrCR3Mapping;
2302#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2303 uint32_t u32Alignment;
2304#endif
2305
2306 /** Indicates that PGMR3FinalizeMappings has been called and that further
2307 * PGMR3MapIntermediate calls will be rejected. */
2308 bool fFinalizedMappings;
2309 /** If set no conflict checks are required. (boolean) */
2310 bool fMappingsFixed;
2311 /** If set, then no mappings are put into the shadow page table. (boolean) */
2312 bool fDisableMappings;
2313 /** Size of fixed mapping */
2314 uint32_t cbMappingFixed;
2315 /** Base address (GC) of fixed mapping */
2316 RTGCPTR GCPtrMappingFixed;
2317 /** The address of the previous RAM range mapping. */
2318 RTGCPTR GCPtrPrevRamRangeMapping;
2319
2320 /** @name Intermediate Context
2321 * @{ */
2322 /** Pointer to the intermediate page directory - Normal. */
2323 R3PTRTYPE(PX86PD) pInterPD;
2324 /** Pointer to the intermedate page tables - Normal.
2325 * There are two page tables, one for the identity mapping and one for
2326 * the host context mapping (of the core code). */
2327 R3PTRTYPE(PX86PT) apInterPTs[2];
2328 /** Pointer to the intermedate page tables - PAE. */
2329 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2330 /** Pointer to the intermedate page directory - PAE. */
2331 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2332 /** Pointer to the intermedate page directory - PAE. */
2333 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2334 /** Pointer to the intermedate page-map level 4 - AMD64. */
2335 R3PTRTYPE(PX86PML4) pInterPaePML4;
2336 /** Pointer to the intermedate page directory - AMD64. */
2337 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2338 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2339 RTHCPHYS HCPhysInterPD;
2340 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2341 RTHCPHYS HCPhysInterPaePDPT;
2342 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2343 RTHCPHYS HCPhysInterPaePML4;
2344 /** @} */
2345
2346 /** Base address of the dynamic page mapping area.
2347 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2348 */
2349 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2350 /** The index of the last entry used in the dynamic page mapping area. */
2351 RTUINT iDynPageMapLast;
2352 /** Cache containing the last entries in the dynamic page mapping area.
2353 * The cache size is covering half of the mapping area. */
2354 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2355 /** Keep a lock counter for the full (!) mapping area. */
2356 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2357
2358 /** The address of the ring-0 mapping cache if we're making use of it. */
2359 RTR0PTR pvR0DynMapUsed;
2360
2361 /** PGM critical section.
2362 * This protects the physical & virtual access handlers, ram ranges,
2363 * and the page flag updating (some of it anyway).
2364 */
2365 PDMCRITSECT CritSect;
2366
2367 /** Pointer to SHW+GST mode data (function pointers).
2368 * The index into this table is made up from */
2369 R3PTRTYPE(PPGMMODEDATA) paModeData;
2370
2371 /** Shadow Page Pool - R3 Ptr. */
2372 R3PTRTYPE(PPGMPOOL) pPoolR3;
2373 /** Shadow Page Pool - R0 Ptr. */
2374 R0PTRTYPE(PPGMPOOL) pPoolR0;
2375 /** Shadow Page Pool - RC Ptr. */
2376 RCPTRTYPE(PPGMPOOL) pPoolRC;
2377
2378 /** We're not in a state which permits writes to guest memory.
2379 * (Only used in strict builds.) */
2380 bool fNoMorePhysWrites;
2381
2382 /**
2383 * Data associated with managing the ring-3 mappings of the allocation chunks.
2384 */
2385 struct
2386 {
2387 /** The chunk tree, ordered by chunk id. */
2388#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2389 R3PTRTYPE(PAVLU32NODECORE) pTree;
2390#else
2391 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2392#endif
2393 /** The chunk mapping TLB. */
2394 PGMCHUNKR3MAPTLB Tlb;
2395 /** The number of mapped chunks. */
2396 uint32_t c;
2397 /** The maximum number of mapped chunks.
2398 * @cfgm PGM/MaxRing3Chunks */
2399 uint32_t cMax;
2400 /** The chunk age tree, ordered by ageing sequence number. */
2401 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2402 /** The current time. */
2403 uint32_t iNow;
2404 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2405 uint32_t AgeingCountdown;
2406 } ChunkR3Map;
2407
2408 /**
2409 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2410 */
2411 PGMPAGER3MAPTLB PhysTlbHC;
2412
2413 /** @name The zero page.
2414 * @{ */
2415 /** The host physical address of the zero page. */
2416 RTHCPHYS HCPhysZeroPg;
2417 /** The ring-3 mapping of the zero page. */
2418 RTR3PTR pvZeroPgR3;
2419 /** The ring-0 mapping of the zero page. */
2420 RTR0PTR pvZeroPgR0;
2421 /** The GC mapping of the zero page. */
2422 RTGCPTR pvZeroPgRC;
2423#if GC_ARCH_BITS != 32
2424 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2425#endif
2426 /** @}*/
2427
2428 /** The number of handy pages. */
2429 uint32_t cHandyPages;
2430 /**
2431 * Array of handy pages.
2432 *
2433 * This array is used in a two way communication between pgmPhysAllocPage
2434 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2435 * an intermediary.
2436 *
2437 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2438 * (The current size of 32 pages, means 128 KB of handy memory.)
2439 */
2440 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2441
2442 /** @name Error injection.
2443 * @{ */
2444 /** Inject handy page allocation errors pretending we're completely out of
2445 * memory. */
2446 bool volatile fErrInjHandyPages;
2447 /** Padding. */
2448 bool afReserved[7];
2449 /** @} */
2450
2451 /** @name Release Statistics
2452 * @{ */
2453 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2454 uint32_t cPrivatePages; /**< The number of private pages. */
2455 uint32_t cSharedPages; /**< The number of shared pages. */
2456 uint32_t cZeroPages; /**< The number of zero backed pages. */
2457
2458 /** The number of times we were forced to change the hypervisor region location. */
2459 STAMCOUNTER cRelocations;
2460 /** @} */
2461
2462#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2463 /* R3 only: */
2464 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2465 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2466
2467 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2468 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2469 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2470 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2471 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2472 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2473 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2474 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2475 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2476 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2477 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2478 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2479 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2480 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2481 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2482 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2483 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2484 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2485/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2486 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2487 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2488/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2489
2490 /* RC only: */
2491 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2492 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2493 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2494 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2495
2496 STAMCOUNTER StatRZPhysRead;
2497 STAMCOUNTER StatRZPhysReadBytes;
2498 STAMCOUNTER StatRZPhysWrite;
2499 STAMCOUNTER StatRZPhysWriteBytes;
2500 STAMCOUNTER StatR3PhysRead;
2501 STAMCOUNTER StatR3PhysReadBytes;
2502 STAMCOUNTER StatR3PhysWrite;
2503 STAMCOUNTER StatR3PhysWriteBytes;
2504 STAMCOUNTER StatRCPhysRead;
2505 STAMCOUNTER StatRCPhysReadBytes;
2506 STAMCOUNTER StatRCPhysWrite;
2507 STAMCOUNTER StatRCPhysWriteBytes;
2508
2509 STAMCOUNTER StatRZPhysSimpleRead;
2510 STAMCOUNTER StatRZPhysSimpleReadBytes;
2511 STAMCOUNTER StatRZPhysSimpleWrite;
2512 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2513 STAMCOUNTER StatR3PhysSimpleRead;
2514 STAMCOUNTER StatR3PhysSimpleReadBytes;
2515 STAMCOUNTER StatR3PhysSimpleWrite;
2516 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2517 STAMCOUNTER StatRCPhysSimpleRead;
2518 STAMCOUNTER StatRCPhysSimpleReadBytes;
2519 STAMCOUNTER StatRCPhysSimpleWrite;
2520 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2521
2522# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2523 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2524 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2525 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2526 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2527 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2528 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2529# endif
2530#endif
2531} PGM;
2532/** Pointer to the PGM instance data. */
2533typedef PGM *PPGM;
2534
2535
2536/**
2537 * Converts a PGMCPU pointer into a VM pointer.
2538 * @returns Pointer to the VM structure the PGM is part of.
2539 * @param pPGM Pointer to PGMCPU instance data.
2540 */
2541#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2542
2543/**
2544 * Converts a PGMCPU pointer into a PGM pointer.
2545 * @returns Pointer to the VM structure the PGM is part of.
2546 * @param pPGM Pointer to PGMCPU instance data.
2547 */
2548#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2549
2550/**
2551 * PGMCPU Data (part of VMCPU).
2552 */
2553typedef struct PGMCPU
2554{
2555 /** Offset to the VM structure. */
2556 RTINT offVM;
2557 /** Offset to the VMCPU structure. */
2558 RTINT offVCpu;
2559 /** Offset of the PGM structure relative to VMCPU. */
2560 RTINT offPGM;
2561 RTINT uPadding0; /**< structure size alignment. */
2562
2563#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2564 /** Automatically tracked physical memory mapping set.
2565 * Ring-0 and strict raw-mode builds. */
2566 PGMMAPSET AutoSet;
2567#endif
2568
2569 /** A20 gate mask.
2570 * Our current approach to A20 emulation is to let REM do it and don't bother
2571 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2572 * But whould need arrise, we'll subject physical addresses to this mask. */
2573 RTGCPHYS GCPhysA20Mask;
2574 /** A20 gate state - boolean! */
2575 bool fA20Enabled;
2576
2577 /** What needs syncing (PGM_SYNC_*).
2578 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2579 * PGMFlushTLB, and PGMR3Load. */
2580 RTUINT fSyncFlags;
2581
2582 /** The shadow paging mode. */
2583 PGMMODE enmShadowMode;
2584 /** The guest paging mode. */
2585 PGMMODE enmGuestMode;
2586
2587 /** The current physical address representing in the guest CR3 register. */
2588 RTGCPHYS GCPhysCR3;
2589
2590 /** @name 32-bit Guest Paging.
2591 * @{ */
2592 /** The guest's page directory, R3 pointer. */
2593 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2594#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2595 /** The guest's page directory, R0 pointer. */
2596 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2597#endif
2598 /** The guest's page directory, static RC mapping. */
2599 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2600 /** @} */
2601
2602 /** @name PAE Guest Paging.
2603 * @{ */
2604 /** The guest's page directory pointer table, static RC mapping. */
2605 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2606 /** The guest's page directory pointer table, R3 pointer. */
2607 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2608#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2609 /** The guest's page directory pointer table, R0 pointer. */
2610 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2611#endif
2612
2613 /** The guest's page directories, R3 pointers.
2614 * These are individual pointers and don't have to be adjecent.
2615 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2616 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2617 /** The guest's page directories, R0 pointers.
2618 * Same restrictions as apGstPaePDsR3. */
2619#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2620 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2621#endif
2622 /** The guest's page directories, static GC mapping.
2623 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2624 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2625 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2626 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2627 RTGCPHYS aGCPhysGstPaePDs[4];
2628 /** The physical addresses of the monitored guest page directories (PAE). */
2629 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2630 /** @} */
2631
2632 /** @name AMD64 Guest Paging.
2633 * @{ */
2634 /** The guest's page directory pointer table, R3 pointer. */
2635 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2636#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2637 /** The guest's page directory pointer table, R0 pointer. */
2638 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2639#endif
2640 /** @} */
2641
2642 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2643 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2644 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2645 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2646 /** Pointer to the page of the current active CR3 - RC Ptr. */
2647 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2648 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2649 uint32_t iShwUser;
2650 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2651 uint32_t iShwUserTable;
2652# if HC_ARCH_BITS == 64
2653 RTRCPTR alignment6; /**< structure size alignment. */
2654# endif
2655 /** @} */
2656
2657 /** @name Function pointers for Shadow paging.
2658 * @{
2659 */
2660 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2661 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2662 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2663 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2664
2665 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2666 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2667
2668 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2669 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2670
2671 /** @} */
2672
2673 /** @name Function pointers for Guest paging.
2674 * @{
2675 */
2676 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2677 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2678 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2679 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2680 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2681 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2682 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2683 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2684#if HC_ARCH_BITS == 64
2685 RTRCPTR alignment3; /**< structure size alignment. */
2686#endif
2687
2688 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2689 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2690 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2691 /** @} */
2692
2693 /** @name Function pointers for Both Shadow and Guest paging.
2694 * @{
2695 */
2696 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2697 /* no pfnR3BthTrap0eHandler */
2698 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2699 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2700 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2701 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2702 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2703 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2704 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2705 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2706
2707 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2708 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2709 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2710 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2711 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2712 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2713 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2714 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2715 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2716
2717 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2718 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2719 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2720 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2721 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2722 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2723 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2724 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2725 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2726#if HC_ARCH_BITS == 64
2727 RTRCPTR alignment2; /**< structure size alignment. */
2728#endif
2729 /** @} */
2730
2731 /** For saving stack space, the disassembler state is allocated here instead of
2732 * on the stack.
2733 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
2734 union
2735 {
2736 /** The disassembler scratch space. */
2737 DISCPUSTATE DisState;
2738 /** Padding. */
2739 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
2740 };
2741
2742 /* Count the number of pgm pool access handler calls. */
2743 uint64_t cPoolAccessHandler;
2744
2745 /** @name Release Statistics
2746 * @{ */
2747 /** The number of times the guest has switched mode since last reset or statistics reset. */
2748 STAMCOUNTER cGuestModeChanges;
2749 /** @} */
2750
2751#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2752 /** @name Statistics
2753 * @{ */
2754 /** RC: Which statistic this \#PF should be attributed to. */
2755 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2756 RTRCPTR padding0;
2757 /** R0: Which statistic this \#PF should be attributed to. */
2758 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2759 RTR0PTR padding1;
2760
2761 /* Common */
2762 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2763 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2764
2765 /* R0 only: */
2766 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2767 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2768 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2769 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2770 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2771 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2772 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2773 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2774 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2775 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2776 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2777 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2778 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2779 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2780 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2781 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2782 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2783 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2784 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2785 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2786 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2787 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2788 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2789 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2790 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2791 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2792
2793 /* RZ only: */
2794 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2795 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2796 STAMPROFILE StatRZTrap0eTimeSyncPT;
2797 STAMPROFILE StatRZTrap0eTimeMapping;
2798 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2799 STAMPROFILE StatRZTrap0eTimeHandlers;
2800 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2801 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2802 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2803 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2804 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2805 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2806 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2807 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2808 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2809 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2810 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2811 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2812 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2813 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2814 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2815 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2816 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2817 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2818 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2819 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2820 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2821 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2822 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2823 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2824 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2825 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2826 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2827 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2828 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2829 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2830 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2831 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2832 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2833 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2834 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2835 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2836 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2837 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2838 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2839 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2840 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2841 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2842 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2843
2844 /* HC - R3 and (maybe) R0: */
2845
2846 /* RZ & R3: */
2847 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2848 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2849 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2850 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2851 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2852 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2853 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2854 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2855 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2856 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2857 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2858 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2859 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2860 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2861 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2862 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2863 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2864 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2865 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2866 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2867 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2868 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2869 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
2870 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2871 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2872 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2873 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2874 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2875 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2876 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2877 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2878 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2879 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2880 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2881 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2882 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2883 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2884 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2885 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2886 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2887 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2888 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2889 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2890 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2891
2892 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2893 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2894 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2895 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2896 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2897 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2898 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2899 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2900 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2901 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2902 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2903 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2904 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2905 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2906 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2907 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2908 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2909 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2910 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2911 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2912 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2913 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2914 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2915 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2916 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2917 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2918 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2919 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2920 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2921 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2922 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2923 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2924 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2925 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2926 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2927 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2928 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2929 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2930 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2931 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2932 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2933 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2934 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2935 /** @} */
2936#endif /* VBOX_WITH_STATISTICS */
2937} PGMCPU;
2938/** Pointer to the per-cpu PGM data. */
2939typedef PGMCPU *PPGMCPU;
2940
2941
2942/** @name PGM::fSyncFlags Flags
2943 * @{
2944 */
2945/** Updates the virtual access handler state bit in PGMPAGE. */
2946#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2947/** Always sync CR3. */
2948#define PGM_SYNC_ALWAYS RT_BIT(1)
2949/** Check monitoring on next CR3 (re)load and invalidate page.
2950 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
2951#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2952/** Check guest mapping in SyncCR3. */
2953#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2954/** Clear the page pool (a light weight flush). */
2955#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
2956#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
2957/** @} */
2958
2959
2960RT_C_DECLS_BEGIN
2961
2962int pgmLock(PVM pVM);
2963void pgmUnlock(PVM pVM);
2964
2965int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2966int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2967PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2968void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2969DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2970
2971void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2972bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2973void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
2974int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2975DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2976#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2977void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2978#else
2979# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2980#endif
2981DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2982
2983
2984int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2985int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2986int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2987int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2988int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2989int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2990int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
2991int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
2992int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
2993VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2994#ifdef IN_RING3
2995void pgmR3PhysRelinkRamRanges(PVM pVM);
2996int pgmR3PhysRamPreAllocate(PVM pVM);
2997int pgmR3PhysRamReset(PVM pVM);
2998int pgmR3PhysRomReset(PVM pVM);
2999int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3000
3001int pgmR3PoolInit(PVM pVM);
3002void pgmR3PoolRelocate(PVM pVM);
3003void pgmR3PoolReset(PVM pVM);
3004
3005#endif /* IN_RING3 */
3006#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3007int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3008#endif
3009int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3010
3011DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3012{
3013 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3014}
3015
3016void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3017void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3018int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3019void pgmPoolClearAll(PVM pVM);
3020PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3021int pgmPoolSyncCR3(PVMCPU pVCpu);
3022int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
3023uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3024void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3025#ifdef PGMPOOL_WITH_MONITORING
3026void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3027int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3028void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3029#endif
3030
3031int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3032int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3033
3034void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3035void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3036int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3037int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3038
3039int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3040#ifndef IN_RC
3041int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3042#endif
3043int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3044
3045PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3046PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3047PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3048PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3049
3050RT_C_DECLS_END
3051
3052
3053/**
3054 * Gets the PGMRAMRANGE structure for a guest page.
3055 *
3056 * @returns Pointer to the RAM range on success.
3057 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3058 *
3059 * @param pPGM PGM handle.
3060 * @param GCPhys The GC physical address.
3061 */
3062DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3063{
3064 /*
3065 * Optimize for the first range.
3066 */
3067 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3068 RTGCPHYS off = GCPhys - pRam->GCPhys;
3069 if (RT_UNLIKELY(off >= pRam->cb))
3070 {
3071 do
3072 {
3073 pRam = pRam->CTX_SUFF(pNext);
3074 if (RT_UNLIKELY(!pRam))
3075 break;
3076 off = GCPhys - pRam->GCPhys;
3077 } while (off >= pRam->cb);
3078 }
3079 return pRam;
3080}
3081
3082
3083/**
3084 * Gets the PGMPAGE structure for a guest page.
3085 *
3086 * @returns Pointer to the page on success.
3087 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3088 *
3089 * @param pPGM PGM handle.
3090 * @param GCPhys The GC physical address.
3091 */
3092DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3093{
3094 /*
3095 * Optimize for the first range.
3096 */
3097 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3098 RTGCPHYS off = GCPhys - pRam->GCPhys;
3099 if (RT_UNLIKELY(off >= pRam->cb))
3100 {
3101 do
3102 {
3103 pRam = pRam->CTX_SUFF(pNext);
3104 if (RT_UNLIKELY(!pRam))
3105 return NULL;
3106 off = GCPhys - pRam->GCPhys;
3107 } while (off >= pRam->cb);
3108 }
3109 return &pRam->aPages[off >> PAGE_SHIFT];
3110}
3111
3112
3113/**
3114 * Gets the PGMPAGE structure for a guest page.
3115 *
3116 * Old Phys code: Will make sure the page is present.
3117 *
3118 * @returns VBox status code.
3119 * @retval VINF_SUCCESS and a valid *ppPage on success.
3120 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3121 *
3122 * @param pPGM PGM handle.
3123 * @param GCPhys The GC physical address.
3124 * @param ppPage Where to store the page poitner on success.
3125 */
3126DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3127{
3128 /*
3129 * Optimize for the first range.
3130 */
3131 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3132 RTGCPHYS off = GCPhys - pRam->GCPhys;
3133 if (RT_UNLIKELY(off >= pRam->cb))
3134 {
3135 do
3136 {
3137 pRam = pRam->CTX_SUFF(pNext);
3138 if (RT_UNLIKELY(!pRam))
3139 {
3140 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3141 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3142 }
3143 off = GCPhys - pRam->GCPhys;
3144 } while (off >= pRam->cb);
3145 }
3146 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3147 return VINF_SUCCESS;
3148}
3149
3150
3151
3152
3153/**
3154 * Gets the PGMPAGE structure for a guest page.
3155 *
3156 * Old Phys code: Will make sure the page is present.
3157 *
3158 * @returns VBox status code.
3159 * @retval VINF_SUCCESS and a valid *ppPage on success.
3160 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3161 *
3162 * @param pPGM PGM handle.
3163 * @param GCPhys The GC physical address.
3164 * @param ppPage Where to store the page poitner on success.
3165 * @param ppRamHint Where to read and store the ram list hint.
3166 * The caller initializes this to NULL before the call.
3167 */
3168DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3169{
3170 RTGCPHYS off;
3171 PPGMRAMRANGE pRam = *ppRamHint;
3172 if ( !pRam
3173 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3174 {
3175 pRam = pPGM->CTX_SUFF(pRamRanges);
3176 off = GCPhys - pRam->GCPhys;
3177 if (RT_UNLIKELY(off >= pRam->cb))
3178 {
3179 do
3180 {
3181 pRam = pRam->CTX_SUFF(pNext);
3182 if (RT_UNLIKELY(!pRam))
3183 {
3184 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3185 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3186 }
3187 off = GCPhys - pRam->GCPhys;
3188 } while (off >= pRam->cb);
3189 }
3190 *ppRamHint = pRam;
3191 }
3192 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3193 return VINF_SUCCESS;
3194}
3195
3196
3197/**
3198 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3199 *
3200 * @returns Pointer to the page on success.
3201 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3202 *
3203 * @param pPGM PGM handle.
3204 * @param GCPhys The GC physical address.
3205 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3206 */
3207DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3208{
3209 /*
3210 * Optimize for the first range.
3211 */
3212 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3213 RTGCPHYS off = GCPhys - pRam->GCPhys;
3214 if (RT_UNLIKELY(off >= pRam->cb))
3215 {
3216 do
3217 {
3218 pRam = pRam->CTX_SUFF(pNext);
3219 if (RT_UNLIKELY(!pRam))
3220 return NULL;
3221 off = GCPhys - pRam->GCPhys;
3222 } while (off >= pRam->cb);
3223 }
3224 *ppRam = pRam;
3225 return &pRam->aPages[off >> PAGE_SHIFT];
3226}
3227
3228
3229/**
3230 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3231 *
3232 * @returns Pointer to the page on success.
3233 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3234 *
3235 * @param pPGM PGM handle.
3236 * @param GCPhys The GC physical address.
3237 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3238 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3239 */
3240DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3241{
3242 /*
3243 * Optimize for the first range.
3244 */
3245 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3246 RTGCPHYS off = GCPhys - pRam->GCPhys;
3247 if (RT_UNLIKELY(off >= pRam->cb))
3248 {
3249 do
3250 {
3251 pRam = pRam->CTX_SUFF(pNext);
3252 if (RT_UNLIKELY(!pRam))
3253 {
3254 *ppRam = NULL; /* Shut up silly GCC warnings. */
3255 *ppPage = NULL; /* ditto */
3256 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3257 }
3258 off = GCPhys - pRam->GCPhys;
3259 } while (off >= pRam->cb);
3260 }
3261 *ppRam = pRam;
3262 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3263 return VINF_SUCCESS;
3264}
3265
3266
3267/**
3268 * Convert GC Phys to HC Phys.
3269 *
3270 * @returns VBox status.
3271 * @param pPGM PGM handle.
3272 * @param GCPhys The GC physical address.
3273 * @param pHCPhys Where to store the corresponding HC physical address.
3274 *
3275 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3276 * Avoid when writing new code!
3277 */
3278DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3279{
3280 PPGMPAGE pPage;
3281 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3282 if (RT_FAILURE(rc))
3283 return rc;
3284 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3285 return VINF_SUCCESS;
3286}
3287
3288#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3289
3290/**
3291 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3292 * optimizes access to pages already in the set.
3293 *
3294 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3295 * @param pPGM Pointer to the PVM instance data.
3296 * @param HCPhys The physical address of the page.
3297 * @param ppv Where to store the mapping address.
3298 */
3299DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3300{
3301 PVM pVM = PGM2VM(pPGM);
3302 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3303 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3304
3305 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3306 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3307 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3308
3309 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3310 unsigned iEntry = pSet->aiHashTable[iHash];
3311 if ( iEntry < pSet->cEntries
3312 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3313 {
3314 *ppv = pSet->aEntries[iEntry].pvPage;
3315 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3316 }
3317 else
3318 {
3319 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3320 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3321 }
3322
3323 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3324 return VINF_SUCCESS;
3325}
3326
3327
3328/**
3329 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3330 * access to pages already in the set.
3331 *
3332 * @returns See PGMDynMapGCPage.
3333 * @param pPGM Pointer to the PVM instance data.
3334 * @param HCPhys The physical address of the page.
3335 * @param ppv Where to store the mapping address.
3336 */
3337DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3338{
3339 PVM pVM = PGM2VM(pPGM);
3340 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3341
3342 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3343 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3344
3345 /*
3346 * Get the ram range.
3347 */
3348 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3349 RTGCPHYS off = GCPhys - pRam->GCPhys;
3350 if (RT_UNLIKELY(off >= pRam->cb
3351 /** @todo || page state stuff */))
3352 {
3353 /* This case is not counted into StatR0DynMapGCPageInl. */
3354 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3355 return PGMDynMapGCPage(pVM, GCPhys, ppv);
3356 }
3357
3358 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3359 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3360
3361 /*
3362 * pgmR0DynMapHCPageInlined with out stats.
3363 */
3364 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3365 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3366 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3367
3368 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3369 unsigned iEntry = pSet->aiHashTable[iHash];
3370 if ( iEntry < pSet->cEntries
3371 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3372 {
3373 *ppv = pSet->aEntries[iEntry].pvPage;
3374 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3375 }
3376 else
3377 {
3378 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3379 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3380 }
3381
3382 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3383 return VINF_SUCCESS;
3384}
3385
3386
3387/**
3388 * Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3389 * access to pages already in the set.
3390 *
3391 * @returns See PGMDynMapGCPage.
3392 * @param pPGM Pointer to the PVM instance data.
3393 * @param HCPhys The physical address of the page.
3394 * @param ppv Where to store the mapping address.
3395 */
3396DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3397{
3398 PVM pVM = PGM2VM(pPGM);
3399 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3400
3401 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3402
3403 /*
3404 * Get the ram range.
3405 */
3406 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3407 RTGCPHYS off = GCPhys - pRam->GCPhys;
3408 if (RT_UNLIKELY(off >= pRam->cb
3409 /** @todo || page state stuff */))
3410 {
3411 /* This case is not counted into StatR0DynMapGCPageInl. */
3412 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3413 return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3414 }
3415
3416 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3417 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3418
3419 /*
3420 * pgmR0DynMapHCPageInlined with out stats.
3421 */
3422 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3423 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3424 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3425
3426 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3427 unsigned iEntry = pSet->aiHashTable[iHash];
3428 if ( iEntry < pSet->cEntries
3429 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3430 {
3431 *ppv = (void *)((uintptr_t)pSet->aEntries[iEntry].pvPage | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3432 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3433 }
3434 else
3435 {
3436 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3437 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3438 *ppv = (void *)((uintptr_t)*ppv | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3439 }
3440
3441 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3442 return VINF_SUCCESS;
3443}
3444
3445#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3446#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3447
3448/**
3449 * Maps the page into current context (RC and maybe R0).
3450 *
3451 * @returns pointer to the mapping.
3452 * @param pVM Pointer to the PGM instance data.
3453 * @param pPage The page.
3454 */
3455DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3456{
3457 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3458 {
3459 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3460 void *pv;
3461# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3462 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3463# else
3464 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3465# endif
3466 return pv;
3467 }
3468 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3469}
3470
3471/**
3472 * Temporarily maps one host page specified by HC physical address, returning
3473 * pointer within the page.
3474 *
3475 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3476 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3477 *
3478 * @returns The address corresponding to HCPhys.
3479 * @param pPGM Pointer to the PVM instance data.
3480 * @param HCPhys HC Physical address of the page.
3481 */
3482DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3483{
3484 void *pv;
3485# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3486 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3487# else
3488 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3489# endif
3490 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3491 return pv;
3492}
3493
3494#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3495#ifndef IN_RC
3496
3497/**
3498 * Queries the Physical TLB entry for a physical guest page,
3499 * attempting to load the TLB entry if necessary.
3500 *
3501 * @returns VBox status code.
3502 * @retval VINF_SUCCESS on success
3503 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3504 *
3505 * @param pPGM The PGM instance handle.
3506 * @param GCPhys The address of the guest page.
3507 * @param ppTlbe Where to store the pointer to the TLB entry.
3508 */
3509DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3510{
3511 int rc;
3512 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3513 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3514 {
3515 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3516 rc = VINF_SUCCESS;
3517 }
3518 else
3519 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3520 *ppTlbe = pTlbe;
3521 return rc;
3522}
3523
3524
3525/**
3526 * Queries the Physical TLB entry for a physical guest page,
3527 * attempting to load the TLB entry if necessary.
3528 *
3529 * @returns VBox status code.
3530 * @retval VINF_SUCCESS on success
3531 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3532 *
3533 * @param pPGM The PGM instance handle.
3534 * @param pPage Pointer to the PGMPAGE structure corresponding to
3535 * GCPhys.
3536 * @param GCPhys The address of the guest page.
3537 * @param ppTlbe Where to store the pointer to the TLB entry.
3538 */
3539DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3540{
3541 int rc;
3542 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3543 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3544 {
3545 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3546 rc = VINF_SUCCESS;
3547 }
3548 else
3549 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3550 *ppTlbe = pTlbe;
3551 return rc;
3552}
3553
3554#endif /* !IN_RC */
3555
3556/**
3557 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3558 * Takes PSE-36 into account.
3559 *
3560 * @returns guest physical address
3561 * @param pPGM Pointer to the PGM instance data.
3562 * @param Pde Guest Pde
3563 */
3564DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3565{
3566 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3567 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3568
3569 return GCPhys & pPGM->GCPhys4MBPSEMask;
3570}
3571
3572
3573/**
3574 * Gets the page directory entry for the specified address (32-bit paging).
3575 *
3576 * @returns The page directory entry in question.
3577 * @param pPGM Pointer to the PGM instance data.
3578 * @param GCPtr The address.
3579 */
3580DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3581{
3582#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3583 PCX86PD pGuestPD = NULL;
3584 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3585 if (RT_FAILURE(rc))
3586 {
3587 X86PDE ZeroPde = {0};
3588 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3589 }
3590#else
3591 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3592# ifdef IN_RING3
3593 if (!pGuestPD)
3594 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3595# endif
3596#endif
3597 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3598}
3599
3600
3601/**
3602 * Gets the address of a specific page directory entry (32-bit paging).
3603 *
3604 * @returns Pointer the page directory entry in question.
3605 * @param pPGM Pointer to the PGM instance data.
3606 * @param GCPtr The address.
3607 */
3608DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3609{
3610#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3611 PX86PD pGuestPD = NULL;
3612 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3613 AssertRCReturn(rc, NULL);
3614#else
3615 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3616# ifdef IN_RING3
3617 if (!pGuestPD)
3618 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3619# endif
3620#endif
3621 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3622}
3623
3624
3625/**
3626 * Gets the address the guest page directory (32-bit paging).
3627 *
3628 * @returns Pointer the page directory entry in question.
3629 * @param pPGM Pointer to the PGM instance data.
3630 */
3631DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3632{
3633#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3634 PX86PD pGuestPD = NULL;
3635 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3636 AssertRCReturn(rc, NULL);
3637#else
3638 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3639# ifdef IN_RING3
3640 if (!pGuestPD)
3641 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3642# endif
3643#endif
3644 return pGuestPD;
3645}
3646
3647
3648/**
3649 * Gets the guest page directory pointer table.
3650 *
3651 * @returns Pointer to the page directory in question.
3652 * @returns NULL if the page directory is not present or on an invalid page.
3653 * @param pPGM Pointer to the PGM instance data.
3654 */
3655DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3656{
3657#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3658 PX86PDPT pGuestPDPT = NULL;
3659 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3660 AssertRCReturn(rc, NULL);
3661#else
3662 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3663# ifdef IN_RING3
3664 if (!pGuestPDPT)
3665 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3666# endif
3667#endif
3668 return pGuestPDPT;
3669}
3670
3671
3672/**
3673 * Gets the guest page directory pointer table entry for the specified address.
3674 *
3675 * @returns Pointer to the page directory in question.
3676 * @returns NULL if the page directory is not present or on an invalid page.
3677 * @param pPGM Pointer to the PGM instance data.
3678 * @param GCPtr The address.
3679 */
3680DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3681{
3682 AssertGCPtr32(GCPtr);
3683
3684#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3685 PX86PDPT pGuestPDPT = 0;
3686 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3687 AssertRCReturn(rc, 0);
3688#else
3689 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3690# ifdef IN_RING3
3691 if (!pGuestPDPT)
3692 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3693# endif
3694#endif
3695 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3696}
3697
3698
3699/**
3700 * Gets the page directory for the specified address.
3701 *
3702 * @returns Pointer to the page directory in question.
3703 * @returns NULL if the page directory is not present or on an invalid page.
3704 * @param pPGM Pointer to the PGM instance data.
3705 * @param GCPtr The address.
3706 */
3707DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
3708{
3709 AssertGCPtr32(GCPtr);
3710
3711 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3712 AssertReturn(pGuestPDPT, NULL);
3713 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3714 if (pGuestPDPT->a[iPdpt].n.u1Present)
3715 {
3716#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3717 PX86PDPAE pGuestPD = NULL;
3718 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3719 AssertRCReturn(rc, NULL);
3720#else
3721 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3722 if ( !pGuestPD
3723 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3724 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3725#endif
3726 return pGuestPD;
3727 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3728 }
3729 return NULL;
3730}
3731
3732
3733/**
3734 * Gets the page directory entry for the specified address.
3735 *
3736 * @returns Pointer to the page directory entry in question.
3737 * @returns NULL if the page directory is not present or on an invalid page.
3738 * @param pPGM Pointer to the PGM instance data.
3739 * @param GCPtr The address.
3740 */
3741DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3742{
3743 AssertGCPtr32(GCPtr);
3744
3745 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3746 AssertReturn(pGuestPDPT, NULL);
3747 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3748 if (pGuestPDPT->a[iPdpt].n.u1Present)
3749 {
3750 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3751#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3752 PX86PDPAE pGuestPD = NULL;
3753 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3754 AssertRCReturn(rc, NULL);
3755#else
3756 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3757 if ( !pGuestPD
3758 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3759 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3760#endif
3761 return &pGuestPD->a[iPD];
3762 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3763 }
3764 return NULL;
3765}
3766
3767
3768/**
3769 * Gets the page directory entry for the specified address.
3770 *
3771 * @returns The page directory entry in question.
3772 * @returns A non-present entry if the page directory is not present or on an invalid page.
3773 * @param pPGM Pointer to the PGM instance data.
3774 * @param GCPtr The address.
3775 */
3776DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3777{
3778 AssertGCPtr32(GCPtr);
3779 X86PDEPAE ZeroPde = {0};
3780 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3781 if (RT_LIKELY(pGuestPDPT))
3782 {
3783 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3784 if (pGuestPDPT->a[iPdpt].n.u1Present)
3785 {
3786 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3787#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3788 PX86PDPAE pGuestPD = NULL;
3789 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3790 AssertRCReturn(rc, ZeroPde);
3791#else
3792 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3793 if ( !pGuestPD
3794 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3795 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3796#endif
3797 return pGuestPD->a[iPD];
3798 }
3799 }
3800 return ZeroPde;
3801}
3802
3803
3804/**
3805 * Gets the page directory pointer table entry for the specified address
3806 * and returns the index into the page directory
3807 *
3808 * @returns Pointer to the page directory in question.
3809 * @returns NULL if the page directory is not present or on an invalid page.
3810 * @param pPGM Pointer to the PGM instance data.
3811 * @param GCPtr The address.
3812 * @param piPD Receives the index into the returned page directory
3813 * @param pPdpe Receives the page directory pointer entry. Optional.
3814 */
3815DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3816{
3817 AssertGCPtr32(GCPtr);
3818
3819 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3820 AssertReturn(pGuestPDPT, NULL);
3821 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3822 if (pPdpe)
3823 *pPdpe = pGuestPDPT->a[iPdpt];
3824 if (pGuestPDPT->a[iPdpt].n.u1Present)
3825 {
3826 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3827#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3828 PX86PDPAE pGuestPD = NULL;
3829 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3830 AssertRCReturn(rc, NULL);
3831#else
3832 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3833 if ( !pGuestPD
3834 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3835 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3836#endif
3837 *piPD = iPD;
3838 return pGuestPD;
3839 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3840 }
3841 return NULL;
3842}
3843
3844#ifndef IN_RC
3845
3846/**
3847 * Gets the page map level-4 pointer for the guest.
3848 *
3849 * @returns Pointer to the PML4 page.
3850 * @param pPGM Pointer to the PGM instance data.
3851 */
3852DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
3853{
3854#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3855 PX86PML4 pGuestPml4;
3856 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3857 AssertRCReturn(rc, NULL);
3858#else
3859 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3860# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3861 if (!pGuestPml4)
3862 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3863# endif
3864 Assert(pGuestPml4);
3865#endif
3866 return pGuestPml4;
3867}
3868
3869
3870/**
3871 * Gets the pointer to a page map level-4 entry.
3872 *
3873 * @returns Pointer to the PML4 entry.
3874 * @param pPGM Pointer to the PGM instance data.
3875 * @param iPml4 The index.
3876 */
3877DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
3878{
3879#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3880 PX86PML4 pGuestPml4;
3881 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3882 AssertRCReturn(rc, NULL);
3883#else
3884 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3885# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3886 if (!pGuestPml4)
3887 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3888# endif
3889 Assert(pGuestPml4);
3890#endif
3891 return &pGuestPml4->a[iPml4];
3892}
3893
3894
3895/**
3896 * Gets a page map level-4 entry.
3897 *
3898 * @returns The PML4 entry.
3899 * @param pPGM Pointer to the PGM instance data.
3900 * @param iPml4 The index.
3901 */
3902DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
3903{
3904#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3905 PX86PML4 pGuestPml4;
3906 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3907 if (RT_FAILURE(rc))
3908 {
3909 X86PML4E ZeroPml4e = {0};
3910 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3911 }
3912#else
3913 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3914# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3915 if (!pGuestPml4)
3916 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3917# endif
3918 Assert(pGuestPml4);
3919#endif
3920 return pGuestPml4->a[iPml4];
3921}
3922
3923
3924/**
3925 * Gets the page directory pointer entry for the specified address.
3926 *
3927 * @returns Pointer to the page directory pointer entry in question.
3928 * @returns NULL if the page directory is not present or on an invalid page.
3929 * @param pPGM Pointer to the PGM instance data.
3930 * @param GCPtr The address.
3931 * @param ppPml4e Page Map Level-4 Entry (out)
3932 */
3933DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3934{
3935 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3936 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3937 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3938 if (pPml4e->n.u1Present)
3939 {
3940 PX86PDPT pPdpt;
3941 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3942 AssertRCReturn(rc, NULL);
3943
3944 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3945 return &pPdpt->a[iPdpt];
3946 }
3947 return NULL;
3948}
3949
3950
3951/**
3952 * Gets the page directory entry for the specified address.
3953 *
3954 * @returns The page directory entry in question.
3955 * @returns A non-present entry if the page directory is not present or on an invalid page.
3956 * @param pPGM Pointer to the PGM instance data.
3957 * @param GCPtr The address.
3958 * @param ppPml4e Page Map Level-4 Entry (out)
3959 * @param pPdpe Page directory pointer table entry (out)
3960 */
3961DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3962{
3963 X86PDEPAE ZeroPde = {0};
3964 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3965 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3966 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3967 if (pPml4e->n.u1Present)
3968 {
3969 PCX86PDPT pPdptTemp;
3970 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3971 AssertRCReturn(rc, ZeroPde);
3972
3973 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3974 *pPdpe = pPdptTemp->a[iPdpt];
3975 if (pPdptTemp->a[iPdpt].n.u1Present)
3976 {
3977 PCX86PDPAE pPD;
3978 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3979 AssertRCReturn(rc, ZeroPde);
3980
3981 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3982 return pPD->a[iPD];
3983 }
3984 }
3985
3986 return ZeroPde;
3987}
3988
3989
3990/**
3991 * Gets the page directory entry for the specified address.
3992 *
3993 * @returns The page directory entry in question.
3994 * @returns A non-present entry if the page directory is not present or on an invalid page.
3995 * @param pPGM Pointer to the PGM instance data.
3996 * @param GCPtr The address.
3997 */
3998DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
3999{
4000 X86PDEPAE ZeroPde = {0};
4001 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4002 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4003 if (pGuestPml4->a[iPml4].n.u1Present)
4004 {
4005 PCX86PDPT pPdptTemp;
4006 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4007 AssertRCReturn(rc, ZeroPde);
4008
4009 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4010 if (pPdptTemp->a[iPdpt].n.u1Present)
4011 {
4012 PCX86PDPAE pPD;
4013 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4014 AssertRCReturn(rc, ZeroPde);
4015
4016 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4017 return pPD->a[iPD];
4018 }
4019 }
4020 return ZeroPde;
4021}
4022
4023
4024/**
4025 * Gets the page directory entry for the specified address.
4026 *
4027 * @returns Pointer to the page directory entry in question.
4028 * @returns NULL if the page directory is not present or on an invalid page.
4029 * @param pPGM Pointer to the PGM instance data.
4030 * @param GCPtr The address.
4031 */
4032DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4033{
4034 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4035 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4036 if (pGuestPml4->a[iPml4].n.u1Present)
4037 {
4038 PCX86PDPT pPdptTemp;
4039 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4040 AssertRCReturn(rc, NULL);
4041
4042 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4043 if (pPdptTemp->a[iPdpt].n.u1Present)
4044 {
4045 PX86PDPAE pPD;
4046 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4047 AssertRCReturn(rc, NULL);
4048
4049 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4050 return &pPD->a[iPD];
4051 }
4052 }
4053 return NULL;
4054}
4055
4056
4057/**
4058 * Gets the GUEST page directory pointer for the specified address.
4059 *
4060 * @returns The page directory in question.
4061 * @returns NULL if the page directory is not present or on an invalid page.
4062 * @param pPGM Pointer to the PGM instance data.
4063 * @param GCPtr The address.
4064 * @param ppPml4e Page Map Level-4 Entry (out)
4065 * @param pPdpe Page directory pointer table entry (out)
4066 * @param piPD Receives the index into the returned page directory
4067 */
4068DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4069{
4070 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4071 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4072 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4073 if (pPml4e->n.u1Present)
4074 {
4075 PCX86PDPT pPdptTemp;
4076 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4077 AssertRCReturn(rc, NULL);
4078
4079 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4080 *pPdpe = pPdptTemp->a[iPdpt];
4081 if (pPdptTemp->a[iPdpt].n.u1Present)
4082 {
4083 PX86PDPAE pPD;
4084 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4085 AssertRCReturn(rc, NULL);
4086
4087 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4088 return pPD;
4089 }
4090 }
4091 return 0;
4092}
4093
4094#endif /* !IN_RC */
4095
4096/**
4097 * Gets the shadow page directory, 32-bit.
4098 *
4099 * @returns Pointer to the shadow 32-bit PD.
4100 * @param pPGM Pointer to the PGM instance data.
4101 */
4102DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4103{
4104 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4105}
4106
4107
4108/**
4109 * Gets the shadow page directory entry for the specified address, 32-bit.
4110 *
4111 * @returns Shadow 32-bit PDE.
4112 * @param pPGM Pointer to the PGM instance data.
4113 * @param GCPtr The address.
4114 */
4115DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4116{
4117 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4118
4119 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4120 if (!pShwPde)
4121 {
4122 X86PDE ZeroPde = {0};
4123 return ZeroPde;
4124 }
4125 return pShwPde->a[iPd];
4126}
4127
4128
4129/**
4130 * Gets the pointer to the shadow page directory entry for the specified
4131 * address, 32-bit.
4132 *
4133 * @returns Pointer to the shadow 32-bit PDE.
4134 * @param pPGM Pointer to the PGM instance data.
4135 * @param GCPtr The address.
4136 */
4137DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4138{
4139 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4140
4141 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4142 AssertReturn(pPde, NULL);
4143 return &pPde->a[iPd];
4144}
4145
4146
4147/**
4148 * Gets the shadow page pointer table, PAE.
4149 *
4150 * @returns Pointer to the shadow PAE PDPT.
4151 * @param pPGM Pointer to the PGM instance data.
4152 */
4153DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4154{
4155 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4156}
4157
4158
4159/**
4160 * Gets the shadow page directory for the specified address, PAE.
4161 *
4162 * @returns Pointer to the shadow PD.
4163 * @param pPGM Pointer to the PGM instance data.
4164 * @param GCPtr The address.
4165 */
4166DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4167{
4168 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4169 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4170
4171 if (!pPdpt->a[iPdpt].n.u1Present)
4172 return NULL;
4173
4174 /* Fetch the pgm pool shadow descriptor. */
4175 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4176 AssertReturn(pShwPde, NULL);
4177
4178 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4179}
4180
4181
4182/**
4183 * Gets the shadow page directory for the specified address, PAE.
4184 *
4185 * @returns Pointer to the shadow PD.
4186 * @param pPGM Pointer to the PGM instance data.
4187 * @param GCPtr The address.
4188 */
4189DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4190{
4191 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4192
4193 if (!pPdpt->a[iPdpt].n.u1Present)
4194 return NULL;
4195
4196 /* Fetch the pgm pool shadow descriptor. */
4197 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4198 AssertReturn(pShwPde, NULL);
4199
4200 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4201}
4202
4203
4204/**
4205 * Gets the shadow page directory entry, PAE.
4206 *
4207 * @returns PDE.
4208 * @param pPGM Pointer to the PGM instance data.
4209 * @param GCPtr The address.
4210 */
4211DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4212{
4213 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4214
4215 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4216 if (!pShwPde)
4217 {
4218 X86PDEPAE ZeroPde = {0};
4219 return ZeroPde;
4220 }
4221 return pShwPde->a[iPd];
4222}
4223
4224
4225/**
4226 * Gets the pointer to the shadow page directory entry for an address, PAE.
4227 *
4228 * @returns Pointer to the PDE.
4229 * @param pPGM Pointer to the PGM instance data.
4230 * @param GCPtr The address.
4231 */
4232DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4233{
4234 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4235
4236 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4237 AssertReturn(pPde, NULL);
4238 return &pPde->a[iPd];
4239}
4240
4241#ifndef IN_RC
4242
4243/**
4244 * Gets the shadow page map level-4 pointer.
4245 *
4246 * @returns Pointer to the shadow PML4.
4247 * @param pPGM Pointer to the PGM instance data.
4248 */
4249DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4250{
4251 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4252}
4253
4254
4255/**
4256 * Gets the shadow page map level-4 entry for the specified address.
4257 *
4258 * @returns The entry.
4259 * @param pPGM Pointer to the PGM instance data.
4260 * @param GCPtr The address.
4261 */
4262DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4263{
4264 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4265 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4266
4267 if (!pShwPml4)
4268 {
4269 X86PML4E ZeroPml4e = {0};
4270 return ZeroPml4e;
4271 }
4272 return pShwPml4->a[iPml4];
4273}
4274
4275
4276/**
4277 * Gets the pointer to the specified shadow page map level-4 entry.
4278 *
4279 * @returns The entry.
4280 * @param pPGM Pointer to the PGM instance data.
4281 * @param iPml4 The PML4 index.
4282 */
4283DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4284{
4285 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4286 if (!pShwPml4)
4287 return NULL;
4288 return &pShwPml4->a[iPml4];
4289}
4290
4291
4292/**
4293 * Gets the GUEST page directory pointer for the specified address.
4294 *
4295 * @returns The page directory in question.
4296 * @returns NULL if the page directory is not present or on an invalid page.
4297 * @param pPGM Pointer to the PGM instance data.
4298 * @param GCPtr The address.
4299 * @param piPD Receives the index into the returned page directory
4300 */
4301DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4302{
4303 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4304 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4305 if (pGuestPml4->a[iPml4].n.u1Present)
4306 {
4307 PCX86PDPT pPdptTemp;
4308 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4309 AssertRCReturn(rc, NULL);
4310
4311 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4312 if (pPdptTemp->a[iPdpt].n.u1Present)
4313 {
4314 PX86PDPAE pPD;
4315 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4316 AssertRCReturn(rc, NULL);
4317
4318 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4319 return pPD;
4320 }
4321 }
4322 return NULL;
4323}
4324
4325#endif /* !IN_RC */
4326
4327/**
4328 * Gets the page state for a physical handler.
4329 *
4330 * @returns The physical handler page state.
4331 * @param pCur The physical handler in question.
4332 */
4333DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4334{
4335 switch (pCur->enmType)
4336 {
4337 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4338 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4339
4340 case PGMPHYSHANDLERTYPE_MMIO:
4341 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4342 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4343
4344 default:
4345 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4346 }
4347}
4348
4349
4350/**
4351 * Gets the page state for a virtual handler.
4352 *
4353 * @returns The virtual handler page state.
4354 * @param pCur The virtual handler in question.
4355 * @remarks This should never be used on a hypervisor access handler.
4356 */
4357DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4358{
4359 switch (pCur->enmType)
4360 {
4361 case PGMVIRTHANDLERTYPE_WRITE:
4362 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4363 case PGMVIRTHANDLERTYPE_ALL:
4364 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4365 default:
4366 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4367 }
4368}
4369
4370
4371/**
4372 * Clears one physical page of a virtual handler
4373 *
4374 * @param pPGM Pointer to the PGM instance.
4375 * @param pCur Virtual handler structure
4376 * @param iPage Physical page index
4377 *
4378 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4379 * need to care about other handlers in the same page.
4380 */
4381DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4382{
4383 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4384
4385 /*
4386 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4387 */
4388#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4389 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4390 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4391 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4392#endif
4393 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4394 {
4395 /* We're the head of the alias chain. */
4396 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4397#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4398 AssertReleaseMsg(pRemove != NULL,
4399 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4400 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4401 AssertReleaseMsg(pRemove == pPhys2Virt,
4402 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4403 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4404 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4405 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4406#endif
4407 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4408 {
4409 /* Insert the next list in the alias chain into the tree. */
4410 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4411#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4412 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4413 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4414 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4415#endif
4416 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4417 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4418 AssertRelease(fRc);
4419 }
4420 }
4421 else
4422 {
4423 /* Locate the previous node in the alias chain. */
4424 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4425#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4426 AssertReleaseMsg(pPrev != pPhys2Virt,
4427 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4428 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4429#endif
4430 for (;;)
4431 {
4432 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4433 if (pNext == pPhys2Virt)
4434 {
4435 /* unlink. */
4436 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4437 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4438 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4439 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4440 else
4441 {
4442 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4443 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4444 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4445 }
4446 break;
4447 }
4448
4449 /* next */
4450 if (pNext == pPrev)
4451 {
4452#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4453 AssertReleaseMsg(pNext != pPrev,
4454 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4455 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4456#endif
4457 break;
4458 }
4459 pPrev = pNext;
4460 }
4461 }
4462 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4463 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4464 pPhys2Virt->offNextAlias = 0;
4465 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4466
4467 /*
4468 * Clear the ram flags for this page.
4469 */
4470 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4471 AssertReturnVoid(pPage);
4472 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4473}
4474
4475
4476/**
4477 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4478 *
4479 * @returns Pointer to the shadow page structure.
4480 * @param pPool The pool.
4481 * @param idx The pool page index.
4482 */
4483DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4484{
4485 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4486 return &pPool->aPages[idx];
4487}
4488
4489
4490#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4491/**
4492 * Clear references to guest physical memory.
4493 *
4494 * @param pPool The pool.
4495 * @param pPoolPage The pool page.
4496 * @param pPhysPage The physical guest page tracking structure.
4497 */
4498DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4499{
4500 /*
4501 * Just deal with the simple case here.
4502 */
4503# ifdef LOG_ENABLED
4504 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4505# endif
4506 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4507 if (cRefs == 1)
4508 {
4509 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4510 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4511 }
4512 else
4513 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4514 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4515}
4516#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4517
4518
4519#ifdef PGMPOOL_WITH_CACHE
4520/**
4521 * Moves the page to the head of the age list.
4522 *
4523 * This is done when the cached page is used in one way or another.
4524 *
4525 * @param pPool The pool.
4526 * @param pPage The cached page.
4527 */
4528DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4529{
4530 PVM pVM = pPool->CTX_SUFF(pVM);
4531 pgmLock(pVM);
4532
4533 /*
4534 * Move to the head of the age list.
4535 */
4536 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4537 {
4538 /* unlink */
4539 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4540 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4541 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4542 else
4543 pPool->iAgeTail = pPage->iAgePrev;
4544
4545 /* insert at head */
4546 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4547 pPage->iAgeNext = pPool->iAgeHead;
4548 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4549 pPool->iAgeHead = pPage->idx;
4550 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4551 }
4552 pgmUnlock(pVM);
4553}
4554#endif /* PGMPOOL_WITH_CACHE */
4555
4556/**
4557 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4558 *
4559 * @param pVM VM Handle.
4560 * @param pPage PGM pool page
4561 */
4562DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4563{
4564 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4565 ASMAtomicIncU32(&pPage->cLocked);
4566}
4567
4568
4569/**
4570 * Unlocks a page to allow flushing again
4571 *
4572 * @param pVM VM Handle.
4573 * @param pPage PGM pool page
4574 */
4575DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4576{
4577 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4578 Assert(pPage->cLocked);
4579 ASMAtomicDecU32(&pPage->cLocked);
4580}
4581
4582
4583/**
4584 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4585 *
4586 * @returns VBox status code.
4587 * @param pPage PGM pool page
4588 */
4589DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4590{
4591 if (pPage->cLocked)
4592 {
4593 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4594 if (pPage->cModifications)
4595 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4596 return true;
4597 }
4598 return false;
4599}
4600
4601/**
4602 * Tells if mappings are to be put into the shadow page table or not
4603 *
4604 * @returns boolean result
4605 * @param pVM VM handle.
4606 */
4607DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4608{
4609#ifdef IN_RING0
4610 /* There are no mappings in VT-x and AMD-V mode. */
4611 Assert(pPGM->fDisableMappings);
4612 return false;
4613#else
4614 return !pPGM->fDisableMappings;
4615#endif
4616}
4617
4618/** @} */
4619
4620#endif
4621
4622
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette