VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 20062

Last change on this file since 20062 was 20062, checked in by vboxsync, 15 years ago

Attempt to fix alignment issues
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File size: 185.8 KB
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1/* $Id: PGMInternal.h 20062 2009-05-27 10:01:51Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/critsect.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59 * Comment it if it will break something.
60 */
61#define PGM_OUT_OF_SYNC_IN_GC
62
63/**
64 * Check and skip global PDEs for non-global flushes
65 */
66#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68/**
69 * Sync N pages instead of a whole page table
70 */
71#define PGM_SYNC_N_PAGES
72
73/**
74 * Number of pages to sync during a page fault
75 *
76 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
77 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
78 */
79#define PGM_SYNC_NR_PAGES 8
80
81/**
82 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
83 */
84#define PGM_MAX_PHYSCACHE_ENTRIES 64
85#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
86
87/**
88 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
89 */
90#define PGM_PHYSMEMACCESS_CACHING
91
92/** @def PGMPOOL_WITH_CACHE
93 * Enable agressive caching using the page pool.
94 *
95 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
96 */
97#define PGMPOOL_WITH_CACHE
98
99/** @def PGMPOOL_WITH_MIXED_PT_CR3
100 * When defined, we'll deal with 'uncachable' pages.
101 */
102#ifdef PGMPOOL_WITH_CACHE
103# define PGMPOOL_WITH_MIXED_PT_CR3
104#endif
105
106/** @def PGMPOOL_WITH_MONITORING
107 * Monitor the guest pages which are shadowed.
108 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
109 * be enabled as well.
110 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
111 */
112#ifdef PGMPOOL_WITH_CACHE
113# define PGMPOOL_WITH_MONITORING
114#endif
115
116/** @def PGMPOOL_WITH_GCPHYS_TRACKING
117 * Tracking the of shadow pages mapping guest physical pages.
118 *
119 * This is very expensive, the current cache prototype is trying to figure out
120 * whether it will be acceptable with an agressive caching policy.
121 */
122#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
123# define PGMPOOL_WITH_GCPHYS_TRACKING
124#endif
125
126/** @def PGMPOOL_WITH_USER_TRACKING
127 * Tracking users of shadow pages. This is required for the linking of shadow page
128 * tables and physical guest addresses.
129 */
130#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
131# define PGMPOOL_WITH_USER_TRACKING
132#endif
133
134/** @def PGMPOOL_CFG_MAX_GROW
135 * The maximum number of pages to add to the pool in one go.
136 */
137#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
138
139/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
140 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
141 */
142#ifdef VBOX_STRICT
143# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
144#endif
145
146/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
147 * Enables the experimental lazy page allocation code. */
148/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
149
150/** @} */
151
152
153/** @name PDPT and PML4 flags.
154 * These are placed in the three bits available for system programs in
155 * the PDPT and PML4 entries.
156 * @{ */
157/** The entry is a permanent one and it's must always be present.
158 * Never free such an entry. */
159#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
160/** Mapping (hypervisor allocated pagetable). */
161#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
162/** @} */
163
164/** @name Page directory flags.
165 * These are placed in the three bits available for system programs in
166 * the page directory entries.
167 * @{ */
168/** Mapping (hypervisor allocated pagetable). */
169#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
170/** Made read-only to facilitate dirty bit tracking. */
171#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
172/** @} */
173
174/** @name Page flags.
175 * These are placed in the three bits available for system programs in
176 * the page entries.
177 * @{ */
178/** Made read-only to facilitate dirty bit tracking. */
179#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
180
181#ifndef PGM_PTFLAGS_CSAM_VALIDATED
182/** Scanned and approved by CSAM (tm).
183 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
184 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
185#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
186#endif
187
188/** @} */
189
190/** @name Defines used to indicate the shadow and guest paging in the templates.
191 * @{ */
192#define PGM_TYPE_REAL 1
193#define PGM_TYPE_PROT 2
194#define PGM_TYPE_32BIT 3
195#define PGM_TYPE_PAE 4
196#define PGM_TYPE_AMD64 5
197#define PGM_TYPE_NESTED 6
198#define PGM_TYPE_EPT 7
199#define PGM_TYPE_MAX PGM_TYPE_EPT
200/** @} */
201
202/** Macro for checking if the guest is using paging.
203 * @param uGstType PGM_TYPE_*
204 * @param uShwType PGM_TYPE_*
205 * @remark ASSUMES certain order of the PGM_TYPE_* values.
206 */
207#define PGM_WITH_PAGING(uGstType, uShwType) \
208 ( (uGstType) >= PGM_TYPE_32BIT \
209 && (uShwType) != PGM_TYPE_NESTED \
210 && (uShwType) != PGM_TYPE_EPT)
211
212/** Macro for checking if the guest supports the NX bit.
213 * @param uGstType PGM_TYPE_*
214 * @param uShwType PGM_TYPE_*
215 * @remark ASSUMES certain order of the PGM_TYPE_* values.
216 */
217#define PGM_WITH_NX(uGstType, uShwType) \
218 ( (uGstType) >= PGM_TYPE_PAE \
219 && (uShwType) != PGM_TYPE_NESTED \
220 && (uShwType) != PGM_TYPE_EPT)
221
222
223/** @def PGM_HCPHYS_2_PTR
224 * Maps a HC physical page pool address to a virtual address.
225 *
226 * @returns VBox status code.
227 * @param pVM The VM handle.
228 * @param HCPhys The HC physical address to map to a virtual one.
229 * @param ppv Where to store the virtual address. No need to cast this.
230 *
231 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
232 * small page window employeed by that function. Be careful.
233 * @remark There is no need to assert on the result.
234 */
235#ifdef IN_RC
236# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
237 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
238#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
239# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
240 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
241#else
242# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
243 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
244#endif
245
246/** @def PGM_HCPHYS_2_PTR_BY_PGM
247 * Maps a HC physical page pool address to a virtual address.
248 *
249 * @returns VBox status code.
250 * @param pPGM The PGM instance data.
251 * @param HCPhys The HC physical address to map to a virtual one.
252 * @param ppv Where to store the virtual address. No need to cast this.
253 *
254 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
255 * small page window employeed by that function. Be careful.
256 * @remark There is no need to assert on the result.
257 */
258#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
259# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
260 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
261#else
262# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
263 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
264#endif
265
266/** @def PGM_GCPHYS_2_PTR
267 * Maps a GC physical page address to a virtual address.
268 *
269 * @returns VBox status code.
270 * @param pVM The VM handle.
271 * @param GCPhys The GC physical address to map to a virtual one.
272 * @param ppv Where to store the virtual address. No need to cast this.
273 *
274 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
275 * small page window employeed by that function. Be careful.
276 * @remark There is no need to assert on the result.
277 */
278#ifdef IN_RC
279# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
280 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
281#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
282# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
283 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
284#else
285# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
286 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
287#endif
288
289/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
290 * Maps a GC physical page address to a virtual address.
291 *
292 * @returns VBox status code.
293 * @param pPGM Pointer to the PGM instance data.
294 * @param GCPhys The GC physical address to map to a virtual one.
295 * @param ppv Where to store the virtual address. No need to cast this.
296 *
297 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
298 * small page window employeed by that function. Be careful.
299 * @remark There is no need to assert on the result.
300 */
301#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
302# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
303 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
304#else
305# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
306 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
307#endif
308
309/** @def PGM_GCPHYS_2_PTR_EX
310 * Maps a unaligned GC physical page address to a virtual address.
311 *
312 * @returns VBox status code.
313 * @param pVM The VM handle.
314 * @param GCPhys The GC physical address to map to a virtual one.
315 * @param ppv Where to store the virtual address. No need to cast this.
316 *
317 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
318 * small page window employeed by that function. Be careful.
319 * @remark There is no need to assert on the result.
320 */
321#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
322# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
323 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
324#else
325# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
326 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
327#endif
328
329/** @def PGM_INVL_PG
330 * Invalidates a page.
331 *
332 * @param pVCpu The VMCPU handle.
333 * @param GCVirt The virtual address of the page to invalidate.
334 */
335#ifdef IN_RC
336# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
337#elif defined(IN_RING0)
338# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
339#else
340# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
341#endif
342
343/** @def PGM_INVL_PG
344 * Invalidates a page on all VCPUs
345 *
346 * @param pVM The VM handle.
347 * @param GCVirt The virtual address of the page to invalidate.
348 */
349#ifdef IN_RC
350# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
351#elif defined(IN_RING0)
352# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
353#else
354# define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
355#endif
356
357/** @def PGM_INVL_BIG_PG
358 * Invalidates a 4MB page directory entry.
359 *
360 * @param pVCpu The VMCPU handle.
361 * @param GCVirt The virtual address within the page directory to invalidate.
362 */
363#ifdef IN_RC
364# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
365#elif defined(IN_RING0)
366# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
367#else
368# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
369#endif
370
371/** @def PGM_INVL_VCPU_TLBS()
372 * Invalidates the TLBs of the specified VCPU
373 *
374 * @param pVCpu The VMCPU handle.
375 */
376#ifdef IN_RC
377# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
378#elif defined(IN_RING0)
379# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
380#else
381# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
382#endif
383
384/** @def PGM_INVL_ALL_VCPU_TLBS()
385 * Invalidates the TLBs of all VCPUs
386 *
387 * @param pVM The VM handle.
388 */
389#ifdef IN_RC
390# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
391#elif defined(IN_RING0)
392# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
393#else
394# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
395#endif
396
397/** Size of the GCPtrConflict array in PGMMAPPING.
398 * @remarks Must be a power of two. */
399#define PGMMAPPING_CONFLICT_MAX 8
400
401/**
402 * Structure for tracking GC Mappings.
403 *
404 * This structure is used by linked list in both GC and HC.
405 */
406typedef struct PGMMAPPING
407{
408 /** Pointer to next entry. */
409 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
410 /** Pointer to next entry. */
411 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
412 /** Pointer to next entry. */
413 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
414 /** Indicate whether this entry is finalized. */
415 bool fFinalized;
416 /** Start Virtual address. */
417 RTGCPTR GCPtr;
418 /** Last Virtual address (inclusive). */
419 RTGCPTR GCPtrLast;
420 /** Range size (bytes). */
421 RTGCPTR cb;
422 /** Pointer to relocation callback function. */
423 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
424 /** User argument to the callback. */
425 R3PTRTYPE(void *) pvUser;
426 /** Mapping description / name. For easing debugging. */
427 R3PTRTYPE(const char *) pszDesc;
428 /** Last 8 addresses that caused conflicts. */
429 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
430 /** Number of conflicts for this hypervisor mapping. */
431 uint32_t cConflicts;
432 /** Number of page tables. */
433 uint32_t cPTs;
434
435 /** Array of page table mapping data. Each entry
436 * describes one page table. The array can be longer
437 * than the declared length.
438 */
439 struct
440 {
441 /** The HC physical address of the page table. */
442 RTHCPHYS HCPhysPT;
443 /** The HC physical address of the first PAE page table. */
444 RTHCPHYS HCPhysPaePT0;
445 /** The HC physical address of the second PAE page table. */
446 RTHCPHYS HCPhysPaePT1;
447 /** The HC virtual address of the 32-bit page table. */
448 R3PTRTYPE(PX86PT) pPTR3;
449 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
450 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
451 /** The GC virtual address of the 32-bit page table. */
452 RCPTRTYPE(PX86PT) pPTRC;
453 /** The GC virtual address of the two PAE page table. */
454 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
455 /** The GC virtual address of the 32-bit page table. */
456 R0PTRTYPE(PX86PT) pPTR0;
457 /** The GC virtual address of the two PAE page table. */
458 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
459 } aPTs[1];
460} PGMMAPPING;
461/** Pointer to structure for tracking GC Mappings. */
462typedef struct PGMMAPPING *PPGMMAPPING;
463
464
465/**
466 * Physical page access handler structure.
467 *
468 * This is used to keep track of physical address ranges
469 * which are being monitored in some kind of way.
470 */
471typedef struct PGMPHYSHANDLER
472{
473 AVLROGCPHYSNODECORE Core;
474 /** Access type. */
475 PGMPHYSHANDLERTYPE enmType;
476 /** Number of pages to update. */
477 uint32_t cPages;
478 /** Pointer to R3 callback function. */
479 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
480 /** User argument for R3 handlers. */
481 R3PTRTYPE(void *) pvUserR3;
482 /** Pointer to R0 callback function. */
483 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
484 /** User argument for R0 handlers. */
485 R0PTRTYPE(void *) pvUserR0;
486 /** Pointer to GC callback function. */
487 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
488 /** User argument for RC handlers. */
489 RCPTRTYPE(void *) pvUserRC;
490 /** Description / Name. For easing debugging. */
491 R3PTRTYPE(const char *) pszDesc;
492#ifdef VBOX_WITH_STATISTICS
493 /** Profiling of this handler. */
494 STAMPROFILE Stat;
495#endif
496} PGMPHYSHANDLER;
497/** Pointer to a physical page access handler structure. */
498typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
499
500
501/**
502 * Cache node for the physical addresses covered by a virtual handler.
503 */
504typedef struct PGMPHYS2VIRTHANDLER
505{
506 /** Core node for the tree based on physical ranges. */
507 AVLROGCPHYSNODECORE Core;
508 /** Offset from this struct to the PGMVIRTHANDLER structure. */
509 int32_t offVirtHandler;
510 /** Offset of the next alias relative to this one.
511 * Bit 0 is used for indicating whether we're in the tree.
512 * Bit 1 is used for indicating that we're the head node.
513 */
514 int32_t offNextAlias;
515} PGMPHYS2VIRTHANDLER;
516/** Pointer to a phys to virtual handler structure. */
517typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
518
519/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
520 * node is in the tree. */
521#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
522/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
523 * node is in the head of an alias chain.
524 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
525#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
526/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
527#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
528
529
530/**
531 * Virtual page access handler structure.
532 *
533 * This is used to keep track of virtual address ranges
534 * which are being monitored in some kind of way.
535 */
536typedef struct PGMVIRTHANDLER
537{
538 /** Core node for the tree based on virtual ranges. */
539 AVLROGCPTRNODECORE Core;
540 /** Size of the range (in bytes). */
541 RTGCPTR cb;
542 /** Number of cache pages. */
543 uint32_t cPages;
544 /** Access type. */
545 PGMVIRTHANDLERTYPE enmType;
546 /** Pointer to the RC callback function. */
547 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
548#if HC_ARCH_BITS == 64
549 RTRCPTR padding;
550#endif
551 /** Pointer to the R3 callback function for invalidation. */
552 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
553 /** Pointer to the R3 callback function. */
554 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
555 /** Description / Name. For easing debugging. */
556 R3PTRTYPE(const char *) pszDesc;
557#ifdef VBOX_WITH_STATISTICS
558 /** Profiling of this handler. */
559 STAMPROFILE Stat;
560#endif
561 /** Array of cached physical addresses for the monitored ranged. */
562 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
563} PGMVIRTHANDLER;
564/** Pointer to a virtual page access handler structure. */
565typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
566
567
568/**
569 * Page type.
570 *
571 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
572 * @remarks This is used in the saved state, so changes to it requires bumping
573 * the saved state version.
574 * @todo So, convert to \#defines!
575 */
576typedef enum PGMPAGETYPE
577{
578 /** The usual invalid zero entry. */
579 PGMPAGETYPE_INVALID = 0,
580 /** RAM page. (RWX) */
581 PGMPAGETYPE_RAM,
582 /** MMIO2 page. (RWX) */
583 PGMPAGETYPE_MMIO2,
584 /** MMIO2 page aliased over an MMIO page. (RWX)
585 * See PGMHandlerPhysicalPageAlias(). */
586 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
587 /** Shadowed ROM. (RWX) */
588 PGMPAGETYPE_ROM_SHADOW,
589 /** ROM page. (R-X) */
590 PGMPAGETYPE_ROM,
591 /** MMIO page. (---) */
592 PGMPAGETYPE_MMIO,
593 /** End of valid entries. */
594 PGMPAGETYPE_END
595} PGMPAGETYPE;
596AssertCompile(PGMPAGETYPE_END <= 7);
597
598/** @name Page type predicates.
599 * @{ */
600#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
601#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
602#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
603#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
604#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
605/** @} */
606
607
608/**
609 * A Physical Guest Page tracking structure.
610 *
611 * The format of this structure is complicated because we have to fit a lot
612 * of information into as few bits as possible. The format is also subject
613 * to change (there is one comming up soon). Which means that for we'll be
614 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
615 * accessess to the structure.
616 */
617typedef struct PGMPAGE
618{
619 /** The physical address and a whole lot of other stuff. All bits are used! */
620 RTHCPHYS HCPhysX;
621 /** The page state. */
622 uint32_t u2StateX : 2;
623 /** Flag indicating that a write monitored page was written to when set. */
624 uint32_t fWrittenToX : 1;
625 /** For later. */
626 uint32_t fSomethingElse : 1;
627 /** The Page ID.
628 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
629 * The HCPhysX will then be 100% static. */
630 uint32_t idPageX : 28;
631 /** The page type (PGMPAGETYPE). */
632 uint32_t u3Type : 3;
633 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
634 uint32_t u2HandlerPhysStateX : 2;
635 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
636 uint32_t u2HandlerVirtStateX : 2;
637 uint32_t u29B : 25;
638} PGMPAGE;
639AssertCompileSize(PGMPAGE, 16);
640/** Pointer to a physical guest page. */
641typedef PGMPAGE *PPGMPAGE;
642/** Pointer to a const physical guest page. */
643typedef const PGMPAGE *PCPGMPAGE;
644/** Pointer to a physical guest page pointer. */
645typedef PPGMPAGE *PPPGMPAGE;
646
647
648/**
649 * Clears the page structure.
650 * @param pPage Pointer to the physical guest page tracking structure.
651 */
652#define PGM_PAGE_CLEAR(pPage) \
653 do { \
654 (pPage)->HCPhysX = 0; \
655 (pPage)->u2StateX = 0; \
656 (pPage)->fWrittenToX = 0; \
657 (pPage)->fSomethingElse = 0; \
658 (pPage)->idPageX = 0; \
659 (pPage)->u3Type = 0; \
660 (pPage)->u29B = 0; \
661 } while (0)
662
663/**
664 * Initializes the page structure.
665 * @param pPage Pointer to the physical guest page tracking structure.
666 */
667#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
668 do { \
669 (pPage)->HCPhysX = (_HCPhys); \
670 (pPage)->u2StateX = (_uState); \
671 (pPage)->fWrittenToX = 0; \
672 (pPage)->fSomethingElse = 0; \
673 (pPage)->idPageX = (_idPage); \
674 /*(pPage)->u3Type = (_uType); - later */ \
675 PGM_PAGE_SET_TYPE(pPage, _uType); \
676 (pPage)->u29B = 0; \
677 } while (0)
678
679/**
680 * Initializes the page structure of a ZERO page.
681 * @param pPage Pointer to the physical guest page tracking structure.
682 */
683#define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
684 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
685/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
686# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
687 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
688
689
690/** @name The Page state, PGMPAGE::u2StateX.
691 * @{ */
692/** The zero page.
693 * This is a per-VM page that's never ever mapped writable. */
694#define PGM_PAGE_STATE_ZERO 0
695/** A allocated page.
696 * This is a per-VM page allocated from the page pool (or wherever
697 * we get MMIO2 pages from if the type is MMIO2).
698 */
699#define PGM_PAGE_STATE_ALLOCATED 1
700/** A allocated page that's being monitored for writes.
701 * The shadow page table mappings are read-only. When a write occurs, the
702 * fWrittenTo member is set, the page remapped as read-write and the state
703 * moved back to allocated. */
704#define PGM_PAGE_STATE_WRITE_MONITORED 2
705/** The page is shared, aka. copy-on-write.
706 * This is a page that's shared with other VMs. */
707#define PGM_PAGE_STATE_SHARED 3
708/** @} */
709
710
711/**
712 * Gets the page state.
713 * @returns page state (PGM_PAGE_STATE_*).
714 * @param pPage Pointer to the physical guest page tracking structure.
715 */
716#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
717
718/**
719 * Sets the page state.
720 * @param pPage Pointer to the physical guest page tracking structure.
721 * @param _uState The new page state.
722 */
723#define PGM_PAGE_SET_STATE(pPage, _uState) \
724 do { (pPage)->u2StateX = (_uState); } while (0)
725
726
727/**
728 * Gets the host physical address of the guest page.
729 * @returns host physical address (RTHCPHYS).
730 * @param pPage Pointer to the physical guest page tracking structure.
731 */
732#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
733
734/**
735 * Sets the host physical address of the guest page.
736 * @param pPage Pointer to the physical guest page tracking structure.
737 * @param _HCPhys The new host physical address.
738 */
739#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
740 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
741 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
742
743/**
744 * Get the Page ID.
745 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
746 * @param pPage Pointer to the physical guest page tracking structure.
747 */
748#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
749/* later:
750#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
751 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
752*/
753/**
754 * Sets the Page ID.
755 * @param pPage Pointer to the physical guest page tracking structure.
756 */
757#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
758/* later:
759#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
760 | ((_idPage) & 0xfff) \
761 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
762*/
763
764/**
765 * Get the Chunk ID.
766 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
767 * @param pPage Pointer to the physical guest page tracking structure.
768 */
769#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
770/* later:
771#if GMM_CHUNKID_SHIFT == 12
772# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
773#elif GMM_CHUNKID_SHIFT > 12
774# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
775#elif GMM_CHUNKID_SHIFT < 12
776# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
777 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
778#else
779# error "GMM_CHUNKID_SHIFT isn't defined or something."
780#endif
781*/
782
783/**
784 * Get the index of the page within the allocaiton chunk.
785 * @returns The page index.
786 * @param pPage Pointer to the physical guest page tracking structure.
787 */
788#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
789/* later:
790#if GMM_CHUNKID_SHIFT <= 12
791# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
792#else
793# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
794 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
795#endif
796*/
797
798
799/**
800 * Gets the page type.
801 * @returns The page type.
802 * @param pPage Pointer to the physical guest page tracking structure.
803 */
804#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
805
806/**
807 * Sets the page type.
808 * @param pPage Pointer to the physical guest page tracking structure.
809 * @param _enmType The new page type (PGMPAGETYPE).
810 */
811#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
812 do { (pPage)->u3Type = (_enmType); } while (0)
813
814/**
815 * Checks if the page is marked for MMIO.
816 * @returns true/false.
817 * @param pPage Pointer to the physical guest page tracking structure.
818 */
819#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
820
821/**
822 * Checks if the page is backed by the ZERO page.
823 * @returns true/false.
824 * @param pPage Pointer to the physical guest page tracking structure.
825 */
826#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
827
828/**
829 * Checks if the page is backed by a SHARED page.
830 * @returns true/false.
831 * @param pPage Pointer to the physical guest page tracking structure.
832 */
833#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
834
835
836/**
837 * Marks the paget as written to (for GMM change monitoring).
838 * @param pPage Pointer to the physical guest page tracking structure.
839 */
840#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
841
842/**
843 * Clears the written-to indicator.
844 * @param pPage Pointer to the physical guest page tracking structure.
845 */
846#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
847
848/**
849 * Checks if the page was marked as written-to.
850 * @returns true/false.
851 * @param pPage Pointer to the physical guest page tracking structure.
852 */
853#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
854
855
856/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
857 *
858 * @remarks The values are assigned in order of priority, so we can calculate
859 * the correct state for a page with different handlers installed.
860 * @{ */
861/** No handler installed. */
862#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
863/** Monitoring is temporarily disabled. */
864#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
865/** Write access is monitored. */
866#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
867/** All access is monitored. */
868#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
869/** @} */
870
871/**
872 * Gets the physical access handler state of a page.
873 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
874 * @param pPage Pointer to the physical guest page tracking structure.
875 */
876#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
877
878/**
879 * Sets the physical access handler state of a page.
880 * @param pPage Pointer to the physical guest page tracking structure.
881 * @param _uState The new state value.
882 */
883#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
884 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
885
886/**
887 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
888 * @returns true/false
889 * @param pPage Pointer to the physical guest page tracking structure.
890 */
891#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
892
893/**
894 * Checks if the page has any active physical access handlers.
895 * @returns true/false
896 * @param pPage Pointer to the physical guest page tracking structure.
897 */
898#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
899
900
901/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
902 *
903 * @remarks The values are assigned in order of priority, so we can calculate
904 * the correct state for a page with different handlers installed.
905 * @{ */
906/** No handler installed. */
907#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
908/* 1 is reserved so the lineup is identical with the physical ones. */
909/** Write access is monitored. */
910#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
911/** All access is monitored. */
912#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
913/** @} */
914
915/**
916 * Gets the virtual access handler state of a page.
917 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
918 * @param pPage Pointer to the physical guest page tracking structure.
919 */
920#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
921
922/**
923 * Sets the virtual access handler state of a page.
924 * @param pPage Pointer to the physical guest page tracking structure.
925 * @param _uState The new state value.
926 */
927#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
928 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
929
930/**
931 * Checks if the page has any virtual access handlers.
932 * @returns true/false
933 * @param pPage Pointer to the physical guest page tracking structure.
934 */
935#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
936
937/**
938 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
939 * virtual handlers.
940 * @returns true/false
941 * @param pPage Pointer to the physical guest page tracking structure.
942 */
943#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
944
945
946
947/**
948 * Checks if the page has any access handlers, including temporarily disabled ones.
949 * @returns true/false
950 * @param pPage Pointer to the physical guest page tracking structure.
951 */
952#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
953 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
954 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
955
956/**
957 * Checks if the page has any active access handlers.
958 * @returns true/false
959 * @param pPage Pointer to the physical guest page tracking structure.
960 */
961#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
962 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
963 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
964
965/**
966 * Checks if the page has any active access handlers catching all accesses.
967 * @returns true/false
968 * @param pPage Pointer to the physical guest page tracking structure.
969 */
970#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
971 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
972 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
973
974
975
976
977/** @def PGM_PAGE_GET_TRACKING
978 * Gets the packed shadow page pool tracking data associated with a guest page.
979 * @returns uint16_t containing the data.
980 * @param pPage Pointer to the physical guest page tracking structure.
981 */
982#define PGM_PAGE_GET_TRACKING(pPage) \
983 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
984
985/** @def PGM_PAGE_SET_TRACKING
986 * Sets the packed shadow page pool tracking data associated with a guest page.
987 * @param pPage Pointer to the physical guest page tracking structure.
988 * @param u16TrackingData The tracking data to store.
989 */
990#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
991 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
992
993/** @def PGM_PAGE_GET_TD_CREFS
994 * Gets the @a cRefs tracking data member.
995 * @returns cRefs.
996 * @param pPage Pointer to the physical guest page tracking structure.
997 */
998#define PGM_PAGE_GET_TD_CREFS(pPage) \
999 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1000
1001#define PGM_PAGE_GET_TD_IDX(pPage) \
1002 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1003
1004/**
1005 * Ram range for GC Phys to HC Phys conversion.
1006 *
1007 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1008 * conversions too, but we'll let MM handle that for now.
1009 *
1010 * This structure is used by linked lists in both GC and HC.
1011 */
1012typedef struct PGMRAMRANGE
1013{
1014 /** Start of the range. Page aligned. */
1015 RTGCPHYS GCPhys;
1016 /** Size of the range. (Page aligned of course). */
1017 RTGCPHYS cb;
1018 /** Pointer to the next RAM range - for R3. */
1019 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1020 /** Pointer to the next RAM range - for R0. */
1021 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1022 /** Pointer to the next RAM range - for RC. */
1023 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1024 /** PGM_RAM_RANGE_FLAGS_* flags. */
1025 uint32_t fFlags;
1026 /** Last address in the range (inclusive). Page aligned (-1). */
1027 RTGCPHYS GCPhysLast;
1028 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1029 R3PTRTYPE(void *) pvR3;
1030 /** The range description. */
1031 R3PTRTYPE(const char *) pszDesc;
1032 /** Pointer to self - R0 pointer. */
1033 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1034 /** Pointer to self - RC pointer. */
1035 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1036 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1037 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 1];
1038 /** Array of physical guest page tracking structures. */
1039 PGMPAGE aPages[1];
1040} PGMRAMRANGE;
1041/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1042typedef PGMRAMRANGE *PPGMRAMRANGE;
1043
1044/** @name PGMRAMRANGE::fFlags
1045 * @{ */
1046/** The RAM range is floating around as an independent guest mapping. */
1047#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1048/** @} */
1049
1050
1051/**
1052 * Per page tracking structure for ROM image.
1053 *
1054 * A ROM image may have a shadow page, in which case we may have
1055 * two pages backing it. This structure contains the PGMPAGE for
1056 * both while PGMRAMRANGE have a copy of the active one. It is
1057 * important that these aren't out of sync in any regard other
1058 * than page pool tracking data.
1059 */
1060typedef struct PGMROMPAGE
1061{
1062 /** The page structure for the virgin ROM page. */
1063 PGMPAGE Virgin;
1064 /** The page structure for the shadow RAM page. */
1065 PGMPAGE Shadow;
1066 /** The current protection setting. */
1067 PGMROMPROT enmProt;
1068 /** Pad the structure size to a multiple of 8. */
1069 uint32_t u32Padding;
1070} PGMROMPAGE;
1071/** Pointer to a ROM page tracking structure. */
1072typedef PGMROMPAGE *PPGMROMPAGE;
1073
1074
1075/**
1076 * A registered ROM image.
1077 *
1078 * This is needed to keep track of ROM image since they generally
1079 * intrude into a PGMRAMRANGE. It also keeps track of additional
1080 * info like the two page sets (read-only virgin and read-write shadow),
1081 * the current state of each page.
1082 *
1083 * Because access handlers cannot easily be executed in a different
1084 * context, the ROM ranges needs to be accessible and in all contexts.
1085 */
1086typedef struct PGMROMRANGE
1087{
1088 /** Pointer to the next range - R3. */
1089 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1090 /** Pointer to the next range - R0. */
1091 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1092 /** Pointer to the next range - RC. */
1093 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1094 /** Pointer alignment */
1095 RTRCPTR GCPtrAlignment;
1096 /** Address of the range. */
1097 RTGCPHYS GCPhys;
1098 /** Address of the last byte in the range. */
1099 RTGCPHYS GCPhysLast;
1100 /** Size of the range. */
1101 RTGCPHYS cb;
1102 /** The flags (PGMPHYS_ROM_FLAG_*). */
1103 uint32_t fFlags;
1104 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1105 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1106 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1107 * This is used for strictness checks. */
1108 R3PTRTYPE(const void *) pvOriginal;
1109 /** The ROM description. */
1110 R3PTRTYPE(const char *) pszDesc;
1111 /** The per page tracking structures. */
1112 PGMROMPAGE aPages[1];
1113} PGMROMRANGE;
1114/** Pointer to a ROM range. */
1115typedef PGMROMRANGE *PPGMROMRANGE;
1116
1117
1118/**
1119 * A registered MMIO2 (= Device RAM) range.
1120 *
1121 * There are a few reason why we need to keep track of these
1122 * registrations. One of them is the deregistration & cleanup
1123 * stuff, while another is that the PGMRAMRANGE associated with
1124 * such a region may have to be removed from the ram range list.
1125 *
1126 * Overlapping with a RAM range has to be 100% or none at all. The
1127 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1128 * meditation will be raised if a partial overlap or an overlap of
1129 * ROM pages is encountered. On an overlap we will free all the
1130 * existing RAM pages and put in the ram range pages instead.
1131 */
1132typedef struct PGMMMIO2RANGE
1133{
1134 /** The owner of the range. (a device) */
1135 PPDMDEVINSR3 pDevInsR3;
1136 /** Pointer to the ring-3 mapping of the allocation. */
1137 RTR3PTR pvR3;
1138 /** Pointer to the next range - R3. */
1139 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1140 /** Whether it's mapped or not. */
1141 bool fMapped;
1142 /** Whether it's overlapping or not. */
1143 bool fOverlapping;
1144 /** The PCI region number.
1145 * @remarks This ASSUMES that nobody will ever really need to have multiple
1146 * PCI devices with matching MMIO region numbers on a single device. */
1147 uint8_t iRegion;
1148 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1149 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1150 /** The associated RAM range. */
1151 PGMRAMRANGE RamRange;
1152} PGMMMIO2RANGE;
1153/** Pointer to a MMIO2 range. */
1154typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1155
1156
1157
1158
1159/**
1160 * PGMPhysRead/Write cache entry
1161 */
1162typedef struct PGMPHYSCACHEENTRY
1163{
1164 /** R3 pointer to physical page. */
1165 R3PTRTYPE(uint8_t *) pbR3;
1166 /** GC Physical address for cache entry */
1167 RTGCPHYS GCPhys;
1168#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1169 RTGCPHYS u32Padding0; /**< alignment padding. */
1170#endif
1171} PGMPHYSCACHEENTRY;
1172
1173/**
1174 * PGMPhysRead/Write cache to reduce REM memory access overhead
1175 */
1176typedef struct PGMPHYSCACHE
1177{
1178 /** Bitmap of valid cache entries */
1179 uint64_t aEntries;
1180 /** Cache entries */
1181 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1182} PGMPHYSCACHE;
1183
1184
1185/** Pointer to an allocation chunk ring-3 mapping. */
1186typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1187/** Pointer to an allocation chunk ring-3 mapping pointer. */
1188typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1189
1190/**
1191 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1192 *
1193 * The primary tree (Core) uses the chunk id as key.
1194 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1195 */
1196typedef struct PGMCHUNKR3MAP
1197{
1198 /** The key is the chunk id. */
1199 AVLU32NODECORE Core;
1200 /** The key is the ageing sequence number. */
1201 AVLLU32NODECORE AgeCore;
1202 /** The current age thingy. */
1203 uint32_t iAge;
1204 /** The current reference count. */
1205 uint32_t volatile cRefs;
1206 /** The current permanent reference count. */
1207 uint32_t volatile cPermRefs;
1208 /** The mapping address. */
1209 void *pv;
1210} PGMCHUNKR3MAP;
1211
1212/**
1213 * Allocation chunk ring-3 mapping TLB entry.
1214 */
1215typedef struct PGMCHUNKR3MAPTLBE
1216{
1217 /** The chunk id. */
1218 uint32_t volatile idChunk;
1219#if HC_ARCH_BITS == 64
1220 uint32_t u32Padding; /**< alignment padding. */
1221#endif
1222 /** The chunk map. */
1223#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1224 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1225#else
1226 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1227#endif
1228} PGMCHUNKR3MAPTLBE;
1229/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1230typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1231
1232/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1233 * @remark Must be a power of two value. */
1234#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1235
1236/**
1237 * Allocation chunk ring-3 mapping TLB.
1238 *
1239 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1240 * At first glance this might look kinda odd since AVL trees are
1241 * supposed to give the most optimial lookup times of all trees
1242 * due to their balancing. However, take a tree with 1023 nodes
1243 * in it, that's 10 levels, meaning that most searches has to go
1244 * down 9 levels before they find what they want. This isn't fast
1245 * compared to a TLB hit. There is the factor of cache misses,
1246 * and of course the problem with trees and branch prediction.
1247 * This is why we use TLBs in front of most of the trees.
1248 *
1249 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1250 * difficult when we switch to the new inlined AVL trees (from kStuff).
1251 */
1252typedef struct PGMCHUNKR3MAPTLB
1253{
1254 /** The TLB entries. */
1255 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1256} PGMCHUNKR3MAPTLB;
1257
1258/**
1259 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1260 * @returns Chunk TLB index.
1261 * @param idChunk The Chunk ID.
1262 */
1263#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1264
1265
1266/**
1267 * Ring-3 guest page mapping TLB entry.
1268 * @remarks used in ring-0 as well at the moment.
1269 */
1270typedef struct PGMPAGER3MAPTLBE
1271{
1272 /** Address of the page. */
1273 RTGCPHYS volatile GCPhys;
1274 /** The guest page. */
1275#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1276 R3PTRTYPE(PPGMPAGE) volatile pPage;
1277#else
1278 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1279#endif
1280 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1281#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1282 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1283#else
1284 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1285#endif
1286 /** The address */
1287#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1288 R3PTRTYPE(void *) volatile pv;
1289#else
1290 R3R0PTRTYPE(void *) volatile pv;
1291#endif
1292#if HC_ARCH_BITS == 32
1293 uint32_t u32Padding; /**< alignment padding. */
1294#endif
1295} PGMPAGER3MAPTLBE;
1296/** Pointer to an entry in the HC physical TLB. */
1297typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1298
1299
1300/** The number of entries in the ring-3 guest page mapping TLB.
1301 * @remarks The value must be a power of two. */
1302#define PGM_PAGER3MAPTLB_ENTRIES 64
1303
1304/**
1305 * Ring-3 guest page mapping TLB.
1306 * @remarks used in ring-0 as well at the moment.
1307 */
1308typedef struct PGMPAGER3MAPTLB
1309{
1310 /** The TLB entries. */
1311 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1312} PGMPAGER3MAPTLB;
1313/** Pointer to the ring-3 guest page mapping TLB. */
1314typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1315
1316/**
1317 * Calculates the index of the TLB entry for the specified guest page.
1318 * @returns Physical TLB index.
1319 * @param GCPhys The guest physical address.
1320 */
1321#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1322
1323
1324/**
1325 * Mapping cache usage set entry.
1326 *
1327 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1328 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1329 * cache. If it's extended to include ring-3, well, then something will
1330 * have be changed here...
1331 */
1332typedef struct PGMMAPSETENTRY
1333{
1334 /** The mapping cache index. */
1335 uint16_t iPage;
1336 /** The number of references.
1337 * The max is UINT16_MAX - 1. */
1338 uint16_t cRefs;
1339#if HC_ARCH_BITS == 64
1340 uint32_t alignment;
1341#endif
1342 /** Pointer to the page. */
1343 RTR0PTR pvPage;
1344 /** The physical address for this entry. */
1345 RTHCPHYS HCPhys;
1346} PGMMAPSETENTRY;
1347/** Pointer to a mapping cache usage set entry. */
1348typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1349
1350/**
1351 * Mapping cache usage set.
1352 *
1353 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1354 * done during exits / traps. The set is
1355 */
1356typedef struct PGMMAPSET
1357{
1358 /** The number of occupied entries.
1359 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1360 * dynamic mappings. */
1361 uint32_t cEntries;
1362 /** The start of the current subset.
1363 * This is UINT32_MAX if no subset is currently open. */
1364 uint32_t iSubset;
1365 /** The index of the current CPU, only valid if the set is open. */
1366 int32_t iCpu;
1367#if HC_ARCH_BITS == 64
1368 uint32_t alignment;
1369#endif
1370 /** The entries. */
1371 PGMMAPSETENTRY aEntries[64];
1372 /** HCPhys -> iEntry fast lookup table.
1373 * Use PGMMAPSET_HASH for hashing.
1374 * The entries may or may not be valid, check against cEntries. */
1375 uint8_t aiHashTable[128];
1376} PGMMAPSET;
1377/** Pointer to the mapping cache set. */
1378typedef PGMMAPSET *PPGMMAPSET;
1379
1380/** PGMMAPSET::cEntries value for a closed set. */
1381#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1382
1383/** Hash function for aiHashTable. */
1384#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1385
1386/** The max fill size (strict builds). */
1387#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1388
1389
1390/** @name Context neutrual page mapper TLB.
1391 *
1392 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1393 * code is writting in a kind of context neutrual way. Time will show whether
1394 * this actually makes sense or not...
1395 *
1396 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1397 * context ends up using a global mapping cache on some platforms
1398 * (darwin).
1399 *
1400 * @{ */
1401/** @typedef PPGMPAGEMAPTLB
1402 * The page mapper TLB pointer type for the current context. */
1403/** @typedef PPGMPAGEMAPTLB
1404 * The page mapper TLB entry pointer type for the current context. */
1405/** @typedef PPGMPAGEMAPTLB
1406 * The page mapper TLB entry pointer pointer type for the current context. */
1407/** @def PGM_PAGEMAPTLB_ENTRIES
1408 * The number of TLB entries in the page mapper TLB for the current context. */
1409/** @def PGM_PAGEMAPTLB_IDX
1410 * Calculate the TLB index for a guest physical address.
1411 * @returns The TLB index.
1412 * @param GCPhys The guest physical address. */
1413/** @typedef PPGMPAGEMAP
1414 * Pointer to a page mapper unit for current context. */
1415/** @typedef PPPGMPAGEMAP
1416 * Pointer to a page mapper unit pointer for current context. */
1417#ifdef IN_RC
1418// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1419// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1420// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1421# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1422# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1423 typedef void * PPGMPAGEMAP;
1424 typedef void ** PPPGMPAGEMAP;
1425//#elif IN_RING0
1426// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1427// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1428// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1429//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1430//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1431// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1432// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1433#else
1434 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1435 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1436 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1437# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1438# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1439 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1440 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1441#endif
1442/** @} */
1443
1444
1445/** @name PGM Pool Indexes.
1446 * Aka. the unique shadow page identifier.
1447 * @{ */
1448/** NIL page pool IDX. */
1449#define NIL_PGMPOOL_IDX 0
1450/** The first normal index. */
1451#define PGMPOOL_IDX_FIRST_SPECIAL 1
1452/** Page directory (32-bit root). */
1453#define PGMPOOL_IDX_PD 1
1454/** Page Directory Pointer Table (PAE root). */
1455#define PGMPOOL_IDX_PDPT 2
1456/** AMD64 CR3 level index.*/
1457#define PGMPOOL_IDX_AMD64_CR3 3
1458/** Nested paging root.*/
1459#define PGMPOOL_IDX_NESTED_ROOT 4
1460/** The first normal index. */
1461#define PGMPOOL_IDX_FIRST 5
1462/** The last valid index. (inclusive, 14 bits) */
1463#define PGMPOOL_IDX_LAST 0x3fff
1464/** @} */
1465
1466/** The NIL index for the parent chain. */
1467#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1468
1469/**
1470 * Node in the chain linking a shadowed page to it's parent (user).
1471 */
1472#pragma pack(1)
1473typedef struct PGMPOOLUSER
1474{
1475 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1476 uint16_t iNext;
1477 /** The user page index. */
1478 uint16_t iUser;
1479 /** Index into the user table. */
1480 uint32_t iUserTable;
1481} PGMPOOLUSER, *PPGMPOOLUSER;
1482typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1483#pragma pack()
1484
1485
1486/** The NIL index for the phys ext chain. */
1487#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1488
1489/**
1490 * Node in the chain of physical cross reference extents.
1491 * @todo Calling this an 'extent' is not quite right, find a better name.
1492 */
1493#pragma pack(1)
1494typedef struct PGMPOOLPHYSEXT
1495{
1496 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1497 uint16_t iNext;
1498 /** The user page index. */
1499 uint16_t aidx[3];
1500} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1501typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1502#pragma pack()
1503
1504
1505/**
1506 * The kind of page that's being shadowed.
1507 */
1508typedef enum PGMPOOLKIND
1509{
1510 /** The virtual invalid 0 entry. */
1511 PGMPOOLKIND_INVALID = 0,
1512 /** The entry is free (=unused). */
1513 PGMPOOLKIND_FREE,
1514
1515 /** Shw: 32-bit page table; Gst: no paging */
1516 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1517 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1518 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1519 /** Shw: 32-bit page table; Gst: 4MB page. */
1520 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1521 /** Shw: PAE page table; Gst: no paging */
1522 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1523 /** Shw: PAE page table; Gst: 32-bit page table. */
1524 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1525 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1526 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1527 /** Shw: PAE page table; Gst: PAE page table. */
1528 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1529 /** Shw: PAE page table; Gst: 2MB page. */
1530 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1531
1532 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1533 PGMPOOLKIND_32BIT_PD,
1534 /** Shw: 32-bit page directory. Gst: no paging. */
1535 PGMPOOLKIND_32BIT_PD_PHYS,
1536 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1537 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1538 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1539 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1540 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1541 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1542 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1543 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1544 /** Shw: PAE page directory; Gst: PAE page directory. */
1545 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1546 /** Shw: PAE page directory; Gst: no paging. */
1547 PGMPOOLKIND_PAE_PD_PHYS,
1548
1549 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1550 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1551 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1552 PGMPOOLKIND_PAE_PDPT,
1553 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1554 PGMPOOLKIND_PAE_PDPT_PHYS,
1555
1556 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1557 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1558 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1559 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1560 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1561 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1562 /** Shw: 64-bit page directory table; Gst: no paging */
1563 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1564
1565 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1566 PGMPOOLKIND_64BIT_PML4,
1567
1568 /** Shw: EPT page directory pointer table; Gst: no paging */
1569 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1570 /** Shw: EPT page directory table; Gst: no paging */
1571 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1572 /** Shw: EPT page table; Gst: no paging */
1573 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1574
1575 /** Shw: Root Nested paging table. */
1576 PGMPOOLKIND_ROOT_NESTED,
1577
1578 /** The last valid entry. */
1579 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1580} PGMPOOLKIND;
1581
1582
1583/**
1584 * The tracking data for a page in the pool.
1585 */
1586typedef struct PGMPOOLPAGE
1587{
1588 /** AVL node code with the (R3) physical address of this page. */
1589 AVLOHCPHYSNODECORE Core;
1590 /** Pointer to the R3 mapping of the page. */
1591#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1592 R3PTRTYPE(void *) pvPageR3;
1593#else
1594 R3R0PTRTYPE(void *) pvPageR3;
1595#endif
1596 /** The guest physical address. */
1597#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1598 uint32_t Alignment0;
1599#endif
1600 RTGCPHYS GCPhys;
1601 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1602 uint8_t enmKind;
1603 uint8_t bPadding;
1604 /** The index of this page. */
1605 uint16_t idx;
1606 /** The next entry in the list this page currently resides in.
1607 * It's either in the free list or in the GCPhys hash. */
1608 uint16_t iNext;
1609#ifdef PGMPOOL_WITH_USER_TRACKING
1610 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1611 uint16_t iUserHead;
1612 /** The number of present entries. */
1613 uint16_t cPresent;
1614 /** The first entry in the table which is present. */
1615 uint16_t iFirstPresent;
1616#endif
1617#ifdef PGMPOOL_WITH_MONITORING
1618 /** The number of modifications to the monitored page. */
1619 uint16_t cModifications;
1620 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1621 uint16_t iModifiedNext;
1622 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1623 uint16_t iModifiedPrev;
1624 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1625 uint16_t iMonitoredNext;
1626 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1627 uint16_t iMonitoredPrev;
1628#endif
1629#ifdef PGMPOOL_WITH_CACHE
1630 /** The next page in the age list. */
1631 uint16_t iAgeNext;
1632 /** The previous page in the age list. */
1633 uint16_t iAgePrev;
1634#endif /* PGMPOOL_WITH_CACHE */
1635 /** Used to indicate that the page is zeroed. */
1636 bool fZeroed;
1637 /** Used to indicate that a PT has non-global entries. */
1638 bool fSeenNonGlobal;
1639 /** Used to indicate that we're monitoring writes to the guest page. */
1640 bool fMonitored;
1641 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1642 * (All pages are in the age list.) */
1643 bool fCached;
1644 /** This is used by the R3 access handlers when invoked by an async thread.
1645 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1646 bool volatile fReusedFlushPending;
1647 bool bPadding1;
1648
1649 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1650 uint32_t cLocked;
1651 uint32_t bPadding2;
1652} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1653/** Pointer to a const pool page. */
1654typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1655
1656
1657#ifdef PGMPOOL_WITH_CACHE
1658/** The hash table size. */
1659# define PGMPOOL_HASH_SIZE 0x40
1660/** The hash function. */
1661# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1662#endif
1663
1664
1665/**
1666 * The shadow page pool instance data.
1667 *
1668 * It's all one big allocation made at init time, except for the
1669 * pages that is. The user nodes follows immediatly after the
1670 * page structures.
1671 */
1672typedef struct PGMPOOL
1673{
1674 /** The VM handle - R3 Ptr. */
1675 PVMR3 pVMR3;
1676 /** The VM handle - R0 Ptr. */
1677 PVMR0 pVMR0;
1678 /** The VM handle - RC Ptr. */
1679 PVMRC pVMRC;
1680 /** The max pool size. This includes the special IDs. */
1681 uint16_t cMaxPages;
1682 /** The current pool size. */
1683 uint16_t cCurPages;
1684 /** The head of the free page list. */
1685 uint16_t iFreeHead;
1686 /* Padding. */
1687 uint16_t u16Padding;
1688#ifdef PGMPOOL_WITH_USER_TRACKING
1689 /** Head of the chain of free user nodes. */
1690 uint16_t iUserFreeHead;
1691 /** The number of user nodes we've allocated. */
1692 uint16_t cMaxUsers;
1693 /** The number of present page table entries in the entire pool. */
1694 uint32_t cPresent;
1695 /** Pointer to the array of user nodes - RC pointer. */
1696 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1697 /** Pointer to the array of user nodes - R3 pointer. */
1698 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1699 /** Pointer to the array of user nodes - R0 pointer. */
1700 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1701#endif /* PGMPOOL_WITH_USER_TRACKING */
1702#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1703 /** Head of the chain of free phys ext nodes. */
1704 uint16_t iPhysExtFreeHead;
1705 /** The number of user nodes we've allocated. */
1706 uint16_t cMaxPhysExts;
1707 /** Pointer to the array of physical xref extent - RC pointer. */
1708 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1709 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1710 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1711 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1712 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1713#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1714#ifdef PGMPOOL_WITH_CACHE
1715 /** Hash table for GCPhys addresses. */
1716 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1717 /** The head of the age list. */
1718 uint16_t iAgeHead;
1719 /** The tail of the age list. */
1720 uint16_t iAgeTail;
1721 /** Set if the cache is enabled. */
1722 bool fCacheEnabled;
1723#endif /* PGMPOOL_WITH_CACHE */
1724#ifdef PGMPOOL_WITH_MONITORING
1725 /** Head of the list of modified pages. */
1726 uint16_t iModifiedHead;
1727 /** The current number of modified pages. */
1728 uint16_t cModifiedPages;
1729 /** Access handler, RC. */
1730 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1731 /** Access handler, R0. */
1732 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1733 /** Access handler, R3. */
1734 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1735 /** The access handler description (HC ptr). */
1736 R3PTRTYPE(const char *) pszAccessHandler;
1737#endif /* PGMPOOL_WITH_MONITORING */
1738 /** The number of pages currently in use. */
1739 uint16_t cUsedPages;
1740#ifdef VBOX_WITH_STATISTICS
1741 /** The high wather mark for cUsedPages. */
1742 uint16_t cUsedPagesHigh;
1743 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1744 /** Profiling pgmPoolAlloc(). */
1745 STAMPROFILEADV StatAlloc;
1746 /** Profiling pgmPoolClearAll(). */
1747 STAMPROFILE StatClearAll;
1748 /** Profiling pgmPoolFlushAllInt(). */
1749 STAMPROFILE StatFlushAllInt;
1750 /** Profiling pgmPoolFlushPage(). */
1751 STAMPROFILE StatFlushPage;
1752 /** Profiling pgmPoolFree(). */
1753 STAMPROFILE StatFree;
1754 /** Profiling time spent zeroing pages. */
1755 STAMPROFILE StatZeroPage;
1756# ifdef PGMPOOL_WITH_USER_TRACKING
1757 /** Profiling of pgmPoolTrackDeref. */
1758 STAMPROFILE StatTrackDeref;
1759 /** Profiling pgmTrackFlushGCPhysPT. */
1760 STAMPROFILE StatTrackFlushGCPhysPT;
1761 /** Profiling pgmTrackFlushGCPhysPTs. */
1762 STAMPROFILE StatTrackFlushGCPhysPTs;
1763 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1764 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1765 /** Number of times we've been out of user records. */
1766 STAMCOUNTER StatTrackFreeUpOneUser;
1767# endif
1768# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1769 /** Profiling deref activity related tracking GC physical pages. */
1770 STAMPROFILE StatTrackDerefGCPhys;
1771 /** Number of linear searches for a HCPhys in the ram ranges. */
1772 STAMCOUNTER StatTrackLinearRamSearches;
1773 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1774 STAMCOUNTER StamTrackPhysExtAllocFailures;
1775# endif
1776# ifdef PGMPOOL_WITH_MONITORING
1777 /** Profiling the RC/R0 access handler. */
1778 STAMPROFILE StatMonitorRZ;
1779 /** Times we've failed interpreting the instruction. */
1780 STAMCOUNTER StatMonitorRZEmulateInstr;
1781 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1782 STAMPROFILE StatMonitorRZFlushPage;
1783 /** Times we've detected fork(). */
1784 STAMCOUNTER StatMonitorRZFork;
1785 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1786 STAMPROFILE StatMonitorRZHandled;
1787 /** Times we've failed interpreting a patch code instruction. */
1788 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1789 /** Times we've failed interpreting a patch code instruction during flushing. */
1790 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1791 /** The number of times we've seen rep prefixes we can't handle. */
1792 STAMCOUNTER StatMonitorRZRepPrefix;
1793 /** Profiling the REP STOSD cases we've handled. */
1794 STAMPROFILE StatMonitorRZRepStosd;
1795
1796 /** Profiling the R3 access handler. */
1797 STAMPROFILE StatMonitorR3;
1798 /** Times we've failed interpreting the instruction. */
1799 STAMCOUNTER StatMonitorR3EmulateInstr;
1800 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1801 STAMPROFILE StatMonitorR3FlushPage;
1802 /** Times we've detected fork(). */
1803 STAMCOUNTER StatMonitorR3Fork;
1804 /** Profiling the R3 access we've handled (except REP STOSD). */
1805 STAMPROFILE StatMonitorR3Handled;
1806 /** The number of times we've seen rep prefixes we can't handle. */
1807 STAMCOUNTER StatMonitorR3RepPrefix;
1808 /** Profiling the REP STOSD cases we've handled. */
1809 STAMPROFILE StatMonitorR3RepStosd;
1810 /** The number of times we're called in an async thread an need to flush. */
1811 STAMCOUNTER StatMonitorR3Async;
1812 /** The high wather mark for cModifiedPages. */
1813 uint16_t cModifiedPagesHigh;
1814 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1815# endif
1816# ifdef PGMPOOL_WITH_CACHE
1817 /** The number of cache hits. */
1818 STAMCOUNTER StatCacheHits;
1819 /** The number of cache misses. */
1820 STAMCOUNTER StatCacheMisses;
1821 /** The number of times we've got a conflict of 'kind' in the cache. */
1822 STAMCOUNTER StatCacheKindMismatches;
1823 /** Number of times we've been out of pages. */
1824 STAMCOUNTER StatCacheFreeUpOne;
1825 /** The number of cacheable allocations. */
1826 STAMCOUNTER StatCacheCacheable;
1827 /** The number of uncacheable allocations. */
1828 STAMCOUNTER StatCacheUncacheable;
1829# endif
1830#elif HC_ARCH_BITS == 64
1831 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1832#endif
1833 /** The AVL tree for looking up a page by its HC physical address. */
1834 AVLOHCPHYSTREE HCPhysTree;
1835 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1836 /** Array of pages. (cMaxPages in length)
1837 * The Id is the index into thist array.
1838 */
1839 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1840} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1841
1842
1843/** @def PGMPOOL_PAGE_2_PTR
1844 * Maps a pool page pool into the current context.
1845 *
1846 * @returns VBox status code.
1847 * @param pVM The VM handle.
1848 * @param pPage The pool page.
1849 *
1850 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1851 * small page window employeed by that function. Be careful.
1852 * @remark There is no need to assert on the result.
1853 */
1854#if defined(IN_RC)
1855# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1856#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1857# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1858#elif defined(VBOX_STRICT)
1859# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1860DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1861{
1862 Assert(pPage && pPage->pvPageR3);
1863 return pPage->pvPageR3;
1864}
1865#else
1866# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1867#endif
1868
1869/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1870 * Maps a pool page pool into the current context.
1871 *
1872 * @returns VBox status code.
1873 * @param pPGM Pointer to the PGM instance data.
1874 * @param pPage The pool page.
1875 *
1876 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1877 * small page window employeed by that function. Be careful.
1878 * @remark There is no need to assert on the result.
1879 */
1880#if defined(IN_RC)
1881# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1882#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1883# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1884#else
1885# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1886#endif
1887
1888/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
1889 * Maps a pool page pool into the current context.
1890 *
1891 * @returns VBox status code.
1892 * @param pPGM Pointer to the PGMCPU instance data.
1893 * @param pPage The pool page.
1894 *
1895 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1896 * small page window employeed by that function. Be careful.
1897 * @remark There is no need to assert on the result.
1898 */
1899#if defined(IN_RC)
1900# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1901#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1902# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1903#else
1904# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
1905#endif
1906
1907
1908/** @name Per guest page tracking data.
1909 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1910 * is to use more bits for it and split it up later on. But for now we'll play
1911 * safe and change as little as possible.
1912 *
1913 * The 16-bit word has two parts:
1914 *
1915 * The first 14-bit forms the @a idx field. It is either the index of a page in
1916 * the shadow page pool, or and index into the extent list.
1917 *
1918 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1919 * shadow page pool references to the page. If cRefs equals
1920 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1921 * (misnomer) table and not the shadow page pool.
1922 *
1923 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1924 * the 16-bit word.
1925 *
1926 * @{ */
1927/** The shift count for getting to the cRefs part. */
1928#define PGMPOOL_TD_CREFS_SHIFT 14
1929/** The mask applied after shifting the tracking data down by
1930 * PGMPOOL_TD_CREFS_SHIFT. */
1931#define PGMPOOL_TD_CREFS_MASK 0x3
1932/** The cRef value used to indiciate that the idx is the head of a
1933 * physical cross reference list. */
1934#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1935/** The shift used to get idx. */
1936#define PGMPOOL_TD_IDX_SHIFT 0
1937/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1938#define PGMPOOL_TD_IDX_MASK 0x3fff
1939/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1940 * simply too many mappings of this page. */
1941#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1942
1943/** @def PGMPOOL_TD_MAKE
1944 * Makes a 16-bit tracking data word.
1945 *
1946 * @returns tracking data.
1947 * @param cRefs The @a cRefs field. Must be within bounds!
1948 * @param idx The @a idx field. Must also be within bounds! */
1949#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
1950
1951/** @def PGMPOOL_TD_GET_CREFS
1952 * Get the @a cRefs field from a tracking data word.
1953 *
1954 * @returns The @a cRefs field
1955 * @param u16 The tracking data word. */
1956#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1957
1958/** @def PGMPOOL_TD_GET_IDX
1959 * Get the @a idx field from a tracking data word.
1960 *
1961 * @returns The @a idx field
1962 * @param u16 The tracking data word. */
1963#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1964/** @} */
1965
1966
1967/**
1968 * Trees are using self relative offsets as pointers.
1969 * So, all its data, including the root pointer, must be in the heap for HC and GC
1970 * to have the same layout.
1971 */
1972typedef struct PGMTREES
1973{
1974 /** Physical access handlers (AVL range+offsetptr tree). */
1975 AVLROGCPHYSTREE PhysHandlers;
1976 /** Virtual access handlers (AVL range + GC ptr tree). */
1977 AVLROGCPTRTREE VirtHandlers;
1978 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1979 AVLROGCPHYSTREE PhysToVirtHandlers;
1980 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1981 AVLROGCPTRTREE HyperVirtHandlers;
1982} PGMTREES;
1983/** Pointer to PGM trees. */
1984typedef PGMTREES *PPGMTREES;
1985
1986
1987/** @name Paging mode macros
1988 * @{ */
1989#ifdef IN_RC
1990# define PGM_CTX(a,b) a##RC##b
1991# define PGM_CTX_STR(a,b) a "GC" b
1992# define PGM_CTX_DECL(type) VMMRCDECL(type)
1993#else
1994# ifdef IN_RING3
1995# define PGM_CTX(a,b) a##R3##b
1996# define PGM_CTX_STR(a,b) a "R3" b
1997# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1998# else
1999# define PGM_CTX(a,b) a##R0##b
2000# define PGM_CTX_STR(a,b) a "R0" b
2001# define PGM_CTX_DECL(type) VMMDECL(type)
2002# endif
2003#endif
2004
2005#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2006#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2007#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2008#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2009#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2010#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2011#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2012#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2013#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2014#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2015#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2016#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2017#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2018#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2019#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2020#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2021#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2022
2023#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2024#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2025#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2026#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2027#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2028#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2029#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2030#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2031#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2032#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2033#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2034#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2035#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2036#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2037#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2038#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2039#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2040
2041/* Shw_Gst */
2042#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2043#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2044#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2045#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2046#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2047#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2048#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2049#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2050#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2051#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2052#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2053#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2054#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2055#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2056#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2057#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2058#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2059#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2060#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2061
2062#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2063#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2064#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2065#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2066#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2067#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2068#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2069#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2070#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2071#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2072#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2073#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2074#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2075#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2076#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2077#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2078#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2079#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2080#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2081#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2082#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2083#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2084#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2085#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2086#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2087#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2088#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2089#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2090#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2091#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2092#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2093#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2094#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2095#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2096#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2097#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2098#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2099
2100#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2101#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2102/** @} */
2103
2104/**
2105 * Data for each paging mode.
2106 */
2107typedef struct PGMMODEDATA
2108{
2109 /** The guest mode type. */
2110 uint32_t uGstType;
2111 /** The shadow mode type. */
2112 uint32_t uShwType;
2113
2114 /** @name Function pointers for Shadow paging.
2115 * @{
2116 */
2117 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2118 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2119 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2120 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2121
2122 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2123 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2124
2125 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2126 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2127 /** @} */
2128
2129 /** @name Function pointers for Guest paging.
2130 * @{
2131 */
2132 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2133 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2134 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2135 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2136 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2137 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2138 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2139 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2140 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2141 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2142 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2143 /** @} */
2144
2145 /** @name Function pointers for Both Shadow and Guest paging.
2146 * @{
2147 */
2148 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2149 /* no pfnR3BthTrap0eHandler */
2150 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2151 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2152 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2153 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2154 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2155#ifdef VBOX_STRICT
2156 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2157#endif
2158 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2159 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2160
2161 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2162 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2163 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2164 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2165 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2166 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2167#ifdef VBOX_STRICT
2168 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2169#endif
2170 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2171 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2172
2173 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2174 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2175 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2176 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2177 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2178 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2179#ifdef VBOX_STRICT
2180 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2181#endif
2182 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2183 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2184 /** @} */
2185} PGMMODEDATA, *PPGMMODEDATA;
2186
2187
2188
2189/**
2190 * Converts a PGM pointer into a VM pointer.
2191 * @returns Pointer to the VM structure the PGM is part of.
2192 * @param pPGM Pointer to PGM instance data.
2193 */
2194#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2195
2196/**
2197 * PGM Data (part of VM)
2198 */
2199typedef struct PGM
2200{
2201 /** Offset to the VM structure. */
2202 RTINT offVM;
2203 /** Offset of the PGMCPU structure relative to VMCPU. */
2204 RTINT offVCpuPGM;
2205
2206 /** @cfgm{RamPreAlloc, boolean, false}
2207 * Indicates whether the base RAM should all be allocated before starting
2208 * the VM (default), or if it should be allocated when first written to.
2209 */
2210 bool fRamPreAlloc;
2211 /** Alignment padding. */
2212 bool afAlignment0[7];
2213
2214 /** What needs syncing (PGM_SYNC_*).
2215 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2216 * PGMFlushTLB, and PGMR3Load. */
2217 RTUINT fGlobalSyncFlags;
2218
2219 /*
2220 * This will be redefined at least two more times before we're done, I'm sure.
2221 * The current code is only to get on with the coding.
2222 * - 2004-06-10: initial version, bird.
2223 * - 2004-07-02: 1st time, bird.
2224 * - 2004-10-18: 2nd time, bird.
2225 * - 2005-07-xx: 3rd time, bird.
2226 */
2227
2228 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2229 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2230 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2231 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2232
2233 /** The host paging mode. (This is what SUPLib reports.) */
2234 SUPPAGINGMODE enmHostMode;
2235
2236 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2237 RTGCPHYS GCPhys4MBPSEMask;
2238
2239 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2240 * This is sorted by physical address and contains no overlapping ranges. */
2241 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2242 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2243 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2244 /** RC pointer corresponding to PGM::pRamRangesR3. */
2245 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2246 RTRCPTR alignment4; /**< structure alignment. */
2247
2248 /** Pointer to the list of ROM ranges - for R3.
2249 * This is sorted by physical address and contains no overlapping ranges. */
2250 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2251 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2252 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2253 /** RC pointer corresponding to PGM::pRomRangesR3. */
2254 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2255 /** Alignment padding. */
2256 RTRCPTR GCPtrPadding2;
2257
2258 /** Pointer to the list of MMIO2 ranges - for R3.
2259 * Registration order. */
2260 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2261
2262 /** PGM offset based trees - R3 Ptr. */
2263 R3PTRTYPE(PPGMTREES) pTreesR3;
2264 /** PGM offset based trees - R0 Ptr. */
2265 R0PTRTYPE(PPGMTREES) pTreesR0;
2266 /** PGM offset based trees - RC Ptr. */
2267 RCPTRTYPE(PPGMTREES) pTreesRC;
2268
2269 /** Linked list of GC mappings - for RC.
2270 * The list is sorted ascending on address.
2271 */
2272 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2273 /** Linked list of GC mappings - for HC.
2274 * The list is sorted ascending on address.
2275 */
2276 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2277 /** Linked list of GC mappings - for R0.
2278 * The list is sorted ascending on address.
2279 */
2280 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2281
2282 /** Pointer to the 5 page CR3 content mapping.
2283 * The first page is always the CR3 (in some form) while the 4 other pages
2284 * are used of the PDs in PAE mode. */
2285 RTGCPTR GCPtrCR3Mapping;
2286#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2287 uint32_t u32Alignment;
2288#endif
2289
2290 /** Indicates that PGMR3FinalizeMappings has been called and that further
2291 * PGMR3MapIntermediate calls will be rejected. */
2292 bool fFinalizedMappings;
2293 /** If set no conflict checks are required. (boolean) */
2294 bool fMappingsFixed;
2295 /** If set, then no mappings are put into the shadow page table. (boolean) */
2296 bool fDisableMappings;
2297 /** Size of fixed mapping */
2298 uint32_t cbMappingFixed;
2299 /** Base address (GC) of fixed mapping */
2300 RTGCPTR GCPtrMappingFixed;
2301 /** The address of the previous RAM range mapping. */
2302 RTGCPTR GCPtrPrevRamRangeMapping;
2303
2304 /** @name Intermediate Context
2305 * @{ */
2306 /** Pointer to the intermediate page directory - Normal. */
2307 R3PTRTYPE(PX86PD) pInterPD;
2308 /** Pointer to the intermedate page tables - Normal.
2309 * There are two page tables, one for the identity mapping and one for
2310 * the host context mapping (of the core code). */
2311 R3PTRTYPE(PX86PT) apInterPTs[2];
2312 /** Pointer to the intermedate page tables - PAE. */
2313 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2314 /** Pointer to the intermedate page directory - PAE. */
2315 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2316 /** Pointer to the intermedate page directory - PAE. */
2317 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2318 /** Pointer to the intermedate page-map level 4 - AMD64. */
2319 R3PTRTYPE(PX86PML4) pInterPaePML4;
2320 /** Pointer to the intermedate page directory - AMD64. */
2321 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2322 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2323 RTHCPHYS HCPhysInterPD;
2324 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2325 RTHCPHYS HCPhysInterPaePDPT;
2326 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2327 RTHCPHYS HCPhysInterPaePML4;
2328 /** @} */
2329
2330 /** Base address of the dynamic page mapping area.
2331 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2332 */
2333 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2334 /** The index of the last entry used in the dynamic page mapping area. */
2335 RTUINT iDynPageMapLast;
2336 /** Cache containing the last entries in the dynamic page mapping area.
2337 * The cache size is covering half of the mapping area. */
2338 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2339 /** Keep a lock counter for the full (!) mapping area. */
2340 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2341
2342 /** The address of the ring-0 mapping cache if we're making use of it. */
2343 RTR0PTR pvR0DynMapUsed;
2344
2345 /** PGM critical section.
2346 * This protects the physical & virtual access handlers, ram ranges,
2347 * and the page flag updating (some of it anyway).
2348 */
2349 PDMCRITSECT CritSect;
2350
2351 /** Pointer to SHW+GST mode data (function pointers).
2352 * The index into this table is made up from */
2353 R3PTRTYPE(PPGMMODEDATA) paModeData;
2354
2355 /** Shadow Page Pool - R3 Ptr. */
2356 R3PTRTYPE(PPGMPOOL) pPoolR3;
2357 /** Shadow Page Pool - R0 Ptr. */
2358 R0PTRTYPE(PPGMPOOL) pPoolR0;
2359 /** Shadow Page Pool - RC Ptr. */
2360 RCPTRTYPE(PPGMPOOL) pPoolRC;
2361
2362 /** We're not in a state which permits writes to guest memory.
2363 * (Only used in strict builds.) */
2364 bool fNoMorePhysWrites;
2365
2366 /** Flush the cache on the next access. */
2367 bool fPhysCacheFlushPending;
2368/** @todo r=bird: Fix member names!*/
2369 /** PGMPhysRead cache */
2370 PGMPHYSCACHE pgmphysreadcache;
2371 /** PGMPhysWrite cache */
2372 PGMPHYSCACHE pgmphyswritecache;
2373
2374 /**
2375 * Data associated with managing the ring-3 mappings of the allocation chunks.
2376 */
2377 struct
2378 {
2379 /** The chunk tree, ordered by chunk id. */
2380#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2381 R3PTRTYPE(PAVLU32NODECORE) pTree;
2382#else
2383 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2384#endif
2385 /** The chunk mapping TLB. */
2386 PGMCHUNKR3MAPTLB Tlb;
2387 /** The number of mapped chunks. */
2388 uint32_t c;
2389 /** The maximum number of mapped chunks.
2390 * @cfgm PGM/MaxRing3Chunks */
2391 uint32_t cMax;
2392 /** The chunk age tree, ordered by ageing sequence number. */
2393 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2394 /** The current time. */
2395 uint32_t iNow;
2396 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2397 uint32_t AgeingCountdown;
2398 } ChunkR3Map;
2399
2400 /**
2401 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2402 */
2403 PGMPAGER3MAPTLB PhysTlbHC;
2404
2405 /** @name The zero page.
2406 * @{ */
2407 /** The host physical address of the zero page. */
2408 RTHCPHYS HCPhysZeroPg;
2409 /** The ring-3 mapping of the zero page. */
2410 RTR3PTR pvZeroPgR3;
2411 /** The ring-0 mapping of the zero page. */
2412 RTR0PTR pvZeroPgR0;
2413 /** The GC mapping of the zero page. */
2414 RTGCPTR pvZeroPgRC;
2415#if GC_ARCH_BITS != 32
2416 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2417#endif
2418 /** @}*/
2419
2420 /** The number of handy pages. */
2421 uint32_t cHandyPages;
2422 /**
2423 * Array of handy pages.
2424 *
2425 * This array is used in a two way communication between pgmPhysAllocPage
2426 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2427 * an intermediary.
2428 *
2429 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2430 * (The current size of 32 pages, means 128 KB of handy memory.)
2431 */
2432 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2433
2434 /** @name Error injection.
2435 * @{ */
2436 /** Inject handy page allocation errors pretending we're completely out of
2437 * memory. */
2438 bool volatile fErrInjHandyPages;
2439 /** Padding. */
2440 bool afReserved[7];
2441 /** @} */
2442
2443 /** @name Release Statistics
2444 * @{ */
2445 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2446 uint32_t cPrivatePages; /**< The number of private pages. */
2447 uint32_t cSharedPages; /**< The number of shared pages. */
2448 uint32_t cZeroPages; /**< The number of zero backed pages. */
2449
2450 /** The number of times we were forced to change the hypervisor region location. */
2451 STAMCOUNTER cRelocations;
2452 /** @} */
2453
2454#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2455 /* R3 only: */
2456 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2457 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2458
2459 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2460 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2461 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2462 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2463 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2464 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2465 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2466 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2467 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2468 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2469 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2470 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2471 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2472 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2473 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2474 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2475 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2476 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2477/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2478 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2479 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2480/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2481
2482 /* RC only: */
2483 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2484 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2485 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2486 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2487
2488# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2489 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2490 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2491 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2492 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2493 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2494 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2495# endif
2496#endif
2497} PGM;
2498/** Pointer to the PGM instance data. */
2499typedef PGM *PPGM;
2500
2501
2502/**
2503 * Converts a PGMCPU pointer into a VM pointer.
2504 * @returns Pointer to the VM structure the PGM is part of.
2505 * @param pPGM Pointer to PGMCPU instance data.
2506 */
2507#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2508
2509/**
2510 * Converts a PGMCPU pointer into a PGM pointer.
2511 * @returns Pointer to the VM structure the PGM is part of.
2512 * @param pPGM Pointer to PGMCPU instance data.
2513 */
2514#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2515
2516/**
2517 * PGMCPU Data (part of VMCPU).
2518 */
2519typedef struct PGMCPU
2520{
2521 /** Offset to the VM structure. */
2522 RTINT offVM;
2523 /** Offset to the VMCPU structure. */
2524 RTINT offVCpu;
2525 /** Offset of the PGM structure relative to VMCPU. */
2526 RTINT offPGM;
2527 RTINT uPadding0; /**< structure size alignment. */
2528
2529#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2530 /** Automatically tracked physical memory mapping set.
2531 * Ring-0 and strict raw-mode builds. */
2532 PGMMAPSET AutoSet;
2533#endif
2534
2535 /** A20 gate mask.
2536 * Our current approach to A20 emulation is to let REM do it and don't bother
2537 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2538 * But whould need arrise, we'll subject physical addresses to this mask. */
2539 RTGCPHYS GCPhysA20Mask;
2540 /** A20 gate state - boolean! */
2541 bool fA20Enabled;
2542
2543 /** What needs syncing (PGM_SYNC_*).
2544 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2545 * PGMFlushTLB, and PGMR3Load. */
2546 RTUINT fSyncFlags;
2547
2548 /** The shadow paging mode. */
2549 PGMMODE enmShadowMode;
2550 /** The guest paging mode. */
2551 PGMMODE enmGuestMode;
2552
2553 /** The current physical address representing in the guest CR3 register. */
2554 RTGCPHYS GCPhysCR3;
2555
2556 /** @name 32-bit Guest Paging.
2557 * @{ */
2558 /** The guest's page directory, R3 pointer. */
2559 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2560#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2561 /** The guest's page directory, R0 pointer. */
2562 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2563#endif
2564 /** The guest's page directory, static RC mapping. */
2565 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2566 /** @} */
2567
2568 /** @name PAE Guest Paging.
2569 * @{ */
2570 /** The guest's page directory pointer table, static RC mapping. */
2571 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2572 /** The guest's page directory pointer table, R3 pointer. */
2573 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2574#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2575 /** The guest's page directory pointer table, R0 pointer. */
2576 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2577#endif
2578
2579 /** The guest's page directories, R3 pointers.
2580 * These are individual pointers and don't have to be adjecent.
2581 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2582 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2583 /** The guest's page directories, R0 pointers.
2584 * Same restrictions as apGstPaePDsR3. */
2585#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2586 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2587#endif
2588 /** The guest's page directories, static GC mapping.
2589 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2590 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2591 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2592 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2593 RTGCPHYS aGCPhysGstPaePDs[4];
2594 /** The physical addresses of the monitored guest page directories (PAE). */
2595 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2596 /** @} */
2597
2598 /** @name AMD64 Guest Paging.
2599 * @{ */
2600 /** The guest's page directory pointer table, R3 pointer. */
2601 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2602#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2603 /** The guest's page directory pointer table, R0 pointer. */
2604 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2605#endif
2606 /** @} */
2607
2608 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2609 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2610 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2611 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2612 /** Pointer to the page of the current active CR3 - RC Ptr. */
2613 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2614 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2615 uint32_t iShwUser;
2616 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2617 uint32_t iShwUserTable;
2618# if HC_ARCH_BITS == 64
2619 RTRCPTR alignment6; /**< structure size alignment. */
2620# endif
2621 /** @} */
2622
2623 /** @name Function pointers for Shadow paging.
2624 * @{
2625 */
2626 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2627 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2628 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2629 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2630
2631 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2632 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2633
2634 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2635 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2636
2637 /** @} */
2638
2639 /** @name Function pointers for Guest paging.
2640 * @{
2641 */
2642 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2643 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2644 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2645 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2646 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2647 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2648 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2649 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2650#if HC_ARCH_BITS == 64
2651 RTRCPTR alignment3; /**< structure size alignment. */
2652#endif
2653
2654 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2655 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2656 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2657 /** @} */
2658
2659 /** @name Function pointers for Both Shadow and Guest paging.
2660 * @{
2661 */
2662 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2663 /* no pfnR3BthTrap0eHandler */
2664 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2665 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2666 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2667 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2668 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2669 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2670 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2671 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2672
2673 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2674 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2675 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2676 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2677 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2678 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2679 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2680 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2681 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2682
2683 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2684 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2685 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2686 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2687 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2688 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2689 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2690 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2691 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2692#if HC_ARCH_BITS == 64
2693 RTRCPTR alignment2; /**< structure size alignment. */
2694#endif
2695 /** @} */
2696
2697 /** @name Release Statistics
2698 * @{ */
2699 /** The number of times the guest has switched mode since last reset or statistics reset. */
2700 STAMCOUNTER cGuestModeChanges;
2701 /** @} */
2702
2703#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2704 /** @name Statistics
2705 * @{ */
2706 /** RC: Which statistic this \#PF should be attributed to. */
2707 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2708 RTRCPTR padding0;
2709 /** R0: Which statistic this \#PF should be attributed to. */
2710 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2711 RTR0PTR padding1;
2712
2713 /* Common */
2714 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2715 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2716
2717 /* R0 only: */
2718 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2719 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2720 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2721 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2722 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2723 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2724 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2725 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2726 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2727 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2728 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2729 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2730 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2731 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2732 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2733 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2734 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2735 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2736 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2737 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2738 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2739 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2740 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2741 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2742 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2743 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2744
2745 /* RZ only: */
2746 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2747 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2748 STAMPROFILE StatRZTrap0eTimeSyncPT;
2749 STAMPROFILE StatRZTrap0eTimeMapping;
2750 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2751 STAMPROFILE StatRZTrap0eTimeHandlers;
2752 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2753 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2754 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2755 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2756 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2757 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2758 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2759 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2760 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2761 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2762 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2763 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2764 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2765 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2766 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2767 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2768 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2769 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2770 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2771 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2772 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2773 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2774 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2775 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2776 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2777 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2778 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2779 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2780 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2781 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2782 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2783 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2784 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2785 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2786 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2787 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2788 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2789 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2790 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2791 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2792 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2793 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2794 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2795
2796 /* HC - R3 and (maybe) R0: */
2797
2798 /* RZ & R3: */
2799 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2800 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2801 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2802 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2803 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2804 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2805 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2806 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2807 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2808 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2809 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2810 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2811 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2812 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2813 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2814 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2815 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2816 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2817 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2818 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2819 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2820 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2821 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
2822 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2823 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2824 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2825 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2826 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2827 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2828 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2829 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2830 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2831 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2832 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2833 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2834 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2835 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2836 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2837 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2838 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2839 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2840 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2841 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2842 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2843
2844 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2845 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2846 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2847 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2848 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2849 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2850 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2851 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2852 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2853 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2854 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2855 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2856 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2857 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2858 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2859 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2860 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2861 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2862 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2863 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2864 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2865 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2866 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2867 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2868 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2869 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2870 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2871 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2872 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2873 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2874 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2875 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2876 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2877 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2878 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2879 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2880 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2881 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2882 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2883 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2884 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2885 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2886 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2887 /** @} */
2888#endif /* VBOX_WITH_STATISTICS */
2889} PGMCPU;
2890/** Pointer to the per-cpu PGM data. */
2891typedef PGMCPU *PPGMCPU;
2892
2893
2894/** @name PGM::fSyncFlags Flags
2895 * @{
2896 */
2897/** Updates the virtual access handler state bit in PGMPAGE. */
2898#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2899/** Always sync CR3. */
2900#define PGM_SYNC_ALWAYS RT_BIT(1)
2901/** Check monitoring on next CR3 (re)load and invalidate page.
2902 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
2903#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2904/** Check guest mapping in SyncCR3. */
2905#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2906/** Clear the page pool (a light weight flush). */
2907#define PGM_GLOBAL_SYNC_CLEAR_PGM_POOL_BIT 8
2908#define PGM_GLOBAL_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_GLOBAL_SYNC_CLEAR_PGM_POOL_BIT)
2909/** @} */
2910
2911
2912__BEGIN_DECLS
2913
2914int pgmLock(PVM pVM);
2915void pgmUnlock(PVM pVM);
2916
2917int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2918int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2919PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2920void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2921DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2922
2923void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2924bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
2925void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
2926int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2927DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2928#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2929void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2930#else
2931# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2932#endif
2933DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2934
2935
2936int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2937int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2938int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2939int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2940int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2941int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2942int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
2943int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
2944int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
2945VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2946#ifdef IN_RING3
2947void pgmR3PhysRelinkRamRanges(PVM pVM);
2948int pgmR3PhysRamPreAllocate(PVM pVM);
2949int pgmR3PhysRamReset(PVM pVM);
2950int pgmR3PhysRomReset(PVM pVM);
2951int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2952
2953int pgmR3PoolInit(PVM pVM);
2954void pgmR3PoolRelocate(PVM pVM);
2955void pgmR3PoolReset(PVM pVM);
2956
2957#endif /* IN_RING3 */
2958#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2959int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2960#endif
2961int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2962void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2963void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2964int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2965void pgmPoolClearAll(PVM pVM);
2966PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
2967int pgmPoolSyncCR3(PVM pVM);
2968int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
2969uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2970void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2971#ifdef PGMPOOL_WITH_MONITORING
2972void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
2973int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2974void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2975#endif
2976
2977int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
2978int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
2979
2980void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
2981void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
2982int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2983int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
2984
2985int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2986#ifndef IN_RC
2987int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
2988#endif
2989int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
2990
2991PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
2992PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
2993PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
2994PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
2995
2996__END_DECLS
2997
2998
2999/**
3000 * Gets the PGMRAMRANGE structure for a guest page.
3001 *
3002 * @returns Pointer to the RAM range on success.
3003 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3004 *
3005 * @param pPGM PGM handle.
3006 * @param GCPhys The GC physical address.
3007 */
3008DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3009{
3010 /*
3011 * Optimize for the first range.
3012 */
3013 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3014 RTGCPHYS off = GCPhys - pRam->GCPhys;
3015 if (RT_UNLIKELY(off >= pRam->cb))
3016 {
3017 do
3018 {
3019 pRam = pRam->CTX_SUFF(pNext);
3020 if (RT_UNLIKELY(!pRam))
3021 break;
3022 off = GCPhys - pRam->GCPhys;
3023 } while (off >= pRam->cb);
3024 }
3025 return pRam;
3026}
3027
3028
3029/**
3030 * Gets the PGMPAGE structure for a guest page.
3031 *
3032 * @returns Pointer to the page on success.
3033 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3034 *
3035 * @param pPGM PGM handle.
3036 * @param GCPhys The GC physical address.
3037 */
3038DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3039{
3040 /*
3041 * Optimize for the first range.
3042 */
3043 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3044 RTGCPHYS off = GCPhys - pRam->GCPhys;
3045 if (RT_UNLIKELY(off >= pRam->cb))
3046 {
3047 do
3048 {
3049 pRam = pRam->CTX_SUFF(pNext);
3050 if (RT_UNLIKELY(!pRam))
3051 return NULL;
3052 off = GCPhys - pRam->GCPhys;
3053 } while (off >= pRam->cb);
3054 }
3055 return &pRam->aPages[off >> PAGE_SHIFT];
3056}
3057
3058
3059/**
3060 * Gets the PGMPAGE structure for a guest page.
3061 *
3062 * Old Phys code: Will make sure the page is present.
3063 *
3064 * @returns VBox status code.
3065 * @retval VINF_SUCCESS and a valid *ppPage on success.
3066 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3067 *
3068 * @param pPGM PGM handle.
3069 * @param GCPhys The GC physical address.
3070 * @param ppPage Where to store the page poitner on success.
3071 */
3072DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3073{
3074 /*
3075 * Optimize for the first range.
3076 */
3077 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3078 RTGCPHYS off = GCPhys - pRam->GCPhys;
3079 if (RT_UNLIKELY(off >= pRam->cb))
3080 {
3081 do
3082 {
3083 pRam = pRam->CTX_SUFF(pNext);
3084 if (RT_UNLIKELY(!pRam))
3085 {
3086 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3087 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3088 }
3089 off = GCPhys - pRam->GCPhys;
3090 } while (off >= pRam->cb);
3091 }
3092 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3093 return VINF_SUCCESS;
3094}
3095
3096
3097
3098
3099/**
3100 * Gets the PGMPAGE structure for a guest page.
3101 *
3102 * Old Phys code: Will make sure the page is present.
3103 *
3104 * @returns VBox status code.
3105 * @retval VINF_SUCCESS and a valid *ppPage on success.
3106 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3107 *
3108 * @param pPGM PGM handle.
3109 * @param GCPhys The GC physical address.
3110 * @param ppPage Where to store the page poitner on success.
3111 * @param ppRamHint Where to read and store the ram list hint.
3112 * The caller initializes this to NULL before the call.
3113 */
3114DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3115{
3116 RTGCPHYS off;
3117 PPGMRAMRANGE pRam = *ppRamHint;
3118 if ( !pRam
3119 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3120 {
3121 pRam = pPGM->CTX_SUFF(pRamRanges);
3122 off = GCPhys - pRam->GCPhys;
3123 if (RT_UNLIKELY(off >= pRam->cb))
3124 {
3125 do
3126 {
3127 pRam = pRam->CTX_SUFF(pNext);
3128 if (RT_UNLIKELY(!pRam))
3129 {
3130 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3131 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3132 }
3133 off = GCPhys - pRam->GCPhys;
3134 } while (off >= pRam->cb);
3135 }
3136 *ppRamHint = pRam;
3137 }
3138 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3139 return VINF_SUCCESS;
3140}
3141
3142
3143/**
3144 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3145 *
3146 * @returns Pointer to the page on success.
3147 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3148 *
3149 * @param pPGM PGM handle.
3150 * @param GCPhys The GC physical address.
3151 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3152 */
3153DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3154{
3155 /*
3156 * Optimize for the first range.
3157 */
3158 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3159 RTGCPHYS off = GCPhys - pRam->GCPhys;
3160 if (RT_UNLIKELY(off >= pRam->cb))
3161 {
3162 do
3163 {
3164 pRam = pRam->CTX_SUFF(pNext);
3165 if (RT_UNLIKELY(!pRam))
3166 return NULL;
3167 off = GCPhys - pRam->GCPhys;
3168 } while (off >= pRam->cb);
3169 }
3170 *ppRam = pRam;
3171 return &pRam->aPages[off >> PAGE_SHIFT];
3172}
3173
3174
3175/**
3176 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3177 *
3178 * @returns Pointer to the page on success.
3179 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3180 *
3181 * @param pPGM PGM handle.
3182 * @param GCPhys The GC physical address.
3183 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3184 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3185 */
3186DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3187{
3188 /*
3189 * Optimize for the first range.
3190 */
3191 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3192 RTGCPHYS off = GCPhys - pRam->GCPhys;
3193 if (RT_UNLIKELY(off >= pRam->cb))
3194 {
3195 do
3196 {
3197 pRam = pRam->CTX_SUFF(pNext);
3198 if (RT_UNLIKELY(!pRam))
3199 {
3200 *ppRam = NULL; /* Shut up silly GCC warnings. */
3201 *ppPage = NULL; /* ditto */
3202 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3203 }
3204 off = GCPhys - pRam->GCPhys;
3205 } while (off >= pRam->cb);
3206 }
3207 *ppRam = pRam;
3208 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3209 return VINF_SUCCESS;
3210}
3211
3212
3213/**
3214 * Convert GC Phys to HC Phys.
3215 *
3216 * @returns VBox status.
3217 * @param pPGM PGM handle.
3218 * @param GCPhys The GC physical address.
3219 * @param pHCPhys Where to store the corresponding HC physical address.
3220 *
3221 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3222 * Avoid when writing new code!
3223 */
3224DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3225{
3226 PPGMPAGE pPage;
3227 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3228 if (RT_FAILURE(rc))
3229 return rc;
3230 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3231 return VINF_SUCCESS;
3232}
3233
3234#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3235
3236/**
3237 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3238 * optimizes access to pages already in the set.
3239 *
3240 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3241 * @param pPGM Pointer to the PVM instance data.
3242 * @param HCPhys The physical address of the page.
3243 * @param ppv Where to store the mapping address.
3244 */
3245DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3246{
3247 PVM pVM = PGM2VM(pPGM);
3248 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3249 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3250
3251 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3252 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3253 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3254
3255 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3256 unsigned iEntry = pSet->aiHashTable[iHash];
3257 if ( iEntry < pSet->cEntries
3258 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3259 {
3260 *ppv = pSet->aEntries[iEntry].pvPage;
3261 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3262 }
3263 else
3264 {
3265 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3266 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3267 }
3268
3269 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3270 return VINF_SUCCESS;
3271}
3272
3273
3274/**
3275 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3276 * access to pages already in the set.
3277 *
3278 * @returns See PGMDynMapGCPage.
3279 * @param pPGM Pointer to the PVM instance data.
3280 * @param HCPhys The physical address of the page.
3281 * @param ppv Where to store the mapping address.
3282 */
3283DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3284{
3285 PVM pVM = PGM2VM(pPGM);
3286 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3287
3288 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3289 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3290
3291 /*
3292 * Get the ram range.
3293 */
3294 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3295 RTGCPHYS off = GCPhys - pRam->GCPhys;
3296 if (RT_UNLIKELY(off >= pRam->cb
3297 /** @todo || page state stuff */))
3298 {
3299 /* This case is not counted into StatR0DynMapGCPageInl. */
3300 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3301 return PGMDynMapGCPage(pVM, GCPhys, ppv);
3302 }
3303
3304 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3305 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3306
3307 /*
3308 * pgmR0DynMapHCPageInlined with out stats.
3309 */
3310 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3311 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3312 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3313
3314 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3315 unsigned iEntry = pSet->aiHashTable[iHash];
3316 if ( iEntry < pSet->cEntries
3317 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3318 {
3319 *ppv = pSet->aEntries[iEntry].pvPage;
3320 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3321 }
3322 else
3323 {
3324 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3325 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3326 }
3327
3328 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3329 return VINF_SUCCESS;
3330}
3331
3332#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3333#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3334
3335/**
3336 * Maps the page into current context (RC and maybe R0).
3337 *
3338 * @returns pointer to the mapping.
3339 * @param pVM Pointer to the PGM instance data.
3340 * @param pPage The page.
3341 */
3342DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3343{
3344 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3345 {
3346 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3347 void *pv;
3348# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3349 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3350# else
3351 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3352# endif
3353 return pv;
3354 }
3355 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3356}
3357
3358/**
3359 * Temporarily maps one host page specified by HC physical address, returning
3360 * pointer within the page.
3361 *
3362 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3363 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3364 *
3365 * @returns The address corresponding to HCPhys.
3366 * @param pPGM Pointer to the PVM instance data.
3367 * @param HCPhys HC Physical address of the page.
3368 */
3369DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3370{
3371 void *pv;
3372# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3373 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3374# else
3375 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3376# endif
3377 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3378 return pv;
3379}
3380
3381#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3382#ifndef IN_RC
3383
3384/**
3385 * Queries the Physical TLB entry for a physical guest page,
3386 * attempting to load the TLB entry if necessary.
3387 *
3388 * @returns VBox status code.
3389 * @retval VINF_SUCCESS on success
3390 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3391 *
3392 * @param pPGM The PGM instance handle.
3393 * @param GCPhys The address of the guest page.
3394 * @param ppTlbe Where to store the pointer to the TLB entry.
3395 */
3396DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3397{
3398 int rc;
3399 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3400 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3401 {
3402 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3403 rc = VINF_SUCCESS;
3404 }
3405 else
3406 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3407 *ppTlbe = pTlbe;
3408 return rc;
3409}
3410
3411
3412/**
3413 * Queries the Physical TLB entry for a physical guest page,
3414 * attempting to load the TLB entry if necessary.
3415 *
3416 * @returns VBox status code.
3417 * @retval VINF_SUCCESS on success
3418 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3419 *
3420 * @param pPGM The PGM instance handle.
3421 * @param pPage Pointer to the PGMPAGE structure corresponding to
3422 * GCPhys.
3423 * @param GCPhys The address of the guest page.
3424 * @param ppTlbe Where to store the pointer to the TLB entry.
3425 */
3426DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3427{
3428 int rc;
3429 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3430 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3431 {
3432 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3433 rc = VINF_SUCCESS;
3434 }
3435 else
3436 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3437 *ppTlbe = pTlbe;
3438 return rc;
3439}
3440
3441#endif /* !IN_RC */
3442
3443/**
3444 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3445 * Takes PSE-36 into account.
3446 *
3447 * @returns guest physical address
3448 * @param pPGM Pointer to the PGM instance data.
3449 * @param Pde Guest Pde
3450 */
3451DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3452{
3453 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3454 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3455
3456 return GCPhys & pPGM->GCPhys4MBPSEMask;
3457}
3458
3459
3460/**
3461 * Gets the page directory entry for the specified address (32-bit paging).
3462 *
3463 * @returns The page directory entry in question.
3464 * @param pPGM Pointer to the PGM instance data.
3465 * @param GCPtr The address.
3466 */
3467DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3468{
3469#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3470 PCX86PD pGuestPD = NULL;
3471 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3472 if (RT_FAILURE(rc))
3473 {
3474 X86PDE ZeroPde = {0};
3475 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3476 }
3477#else
3478 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3479# ifdef IN_RING3
3480 if (!pGuestPD)
3481 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3482# endif
3483#endif
3484 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3485}
3486
3487
3488/**
3489 * Gets the address of a specific page directory entry (32-bit paging).
3490 *
3491 * @returns Pointer the page directory entry in question.
3492 * @param pPGM Pointer to the PGM instance data.
3493 * @param GCPtr The address.
3494 */
3495DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3496{
3497#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3498 PX86PD pGuestPD = NULL;
3499 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3500 AssertRCReturn(rc, NULL);
3501#else
3502 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3503# ifdef IN_RING3
3504 if (!pGuestPD)
3505 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3506# endif
3507#endif
3508 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3509}
3510
3511
3512/**
3513 * Gets the address the guest page directory (32-bit paging).
3514 *
3515 * @returns Pointer the page directory entry in question.
3516 * @param pPGM Pointer to the PGM instance data.
3517 */
3518DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3519{
3520#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3521 PX86PD pGuestPD = NULL;
3522 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3523 AssertRCReturn(rc, NULL);
3524#else
3525 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3526# ifdef IN_RING3
3527 if (!pGuestPD)
3528 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3529# endif
3530#endif
3531 return pGuestPD;
3532}
3533
3534
3535/**
3536 * Gets the guest page directory pointer table.
3537 *
3538 * @returns Pointer to the page directory in question.
3539 * @returns NULL if the page directory is not present or on an invalid page.
3540 * @param pPGM Pointer to the PGM instance data.
3541 */
3542DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3543{
3544#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3545 PX86PDPT pGuestPDPT = NULL;
3546 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3547 AssertRCReturn(rc, NULL);
3548#else
3549 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3550# ifdef IN_RING3
3551 if (!pGuestPDPT)
3552 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3553# endif
3554#endif
3555 return pGuestPDPT;
3556}
3557
3558
3559/**
3560 * Gets the guest page directory pointer table entry for the specified address.
3561 *
3562 * @returns Pointer to the page directory in question.
3563 * @returns NULL if the page directory is not present or on an invalid page.
3564 * @param pPGM Pointer to the PGM instance data.
3565 * @param GCPtr The address.
3566 */
3567DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3568{
3569 AssertGCPtr32(GCPtr);
3570
3571#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3572 PX86PDPT pGuestPDPT = 0;
3573 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3574 AssertRCReturn(rc, 0);
3575#else
3576 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3577# ifdef IN_RING3
3578 if (!pGuestPDPT)
3579 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3580# endif
3581#endif
3582 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3583}
3584
3585
3586/**
3587 * Gets the page directory for the specified address.
3588 *
3589 * @returns Pointer to the page directory in question.
3590 * @returns NULL if the page directory is not present or on an invalid page.
3591 * @param pPGM Pointer to the PGM instance data.
3592 * @param GCPtr The address.
3593 */
3594DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
3595{
3596 AssertGCPtr32(GCPtr);
3597
3598 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3599 AssertReturn(pGuestPDPT, NULL);
3600 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3601 if (pGuestPDPT->a[iPdpt].n.u1Present)
3602 {
3603#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3604 PX86PDPAE pGuestPD = NULL;
3605 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3606 AssertRCReturn(rc, NULL);
3607#else
3608 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3609 if ( !pGuestPD
3610 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3611 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3612#endif
3613 return pGuestPD;
3614 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3615 }
3616 return NULL;
3617}
3618
3619
3620/**
3621 * Gets the page directory entry for the specified address.
3622 *
3623 * @returns Pointer to the page directory entry in question.
3624 * @returns NULL if the page directory is not present or on an invalid page.
3625 * @param pPGM Pointer to the PGM instance data.
3626 * @param GCPtr The address.
3627 */
3628DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3629{
3630 AssertGCPtr32(GCPtr);
3631
3632 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3633 AssertReturn(pGuestPDPT, NULL);
3634 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3635 if (pGuestPDPT->a[iPdpt].n.u1Present)
3636 {
3637 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3638#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3639 PX86PDPAE pGuestPD = NULL;
3640 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3641 AssertRCReturn(rc, NULL);
3642#else
3643 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3644 if ( !pGuestPD
3645 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3646 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3647#endif
3648 return &pGuestPD->a[iPD];
3649 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3650 }
3651 return NULL;
3652}
3653
3654
3655/**
3656 * Gets the page directory entry for the specified address.
3657 *
3658 * @returns The page directory entry in question.
3659 * @returns A non-present entry if the page directory is not present or on an invalid page.
3660 * @param pPGM Pointer to the PGM instance data.
3661 * @param GCPtr The address.
3662 */
3663DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3664{
3665 AssertGCPtr32(GCPtr);
3666 X86PDEPAE ZeroPde = {0};
3667 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3668 if (RT_LIKELY(pGuestPDPT))
3669 {
3670 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3671 if (pGuestPDPT->a[iPdpt].n.u1Present)
3672 {
3673 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3674#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3675 PX86PDPAE pGuestPD = NULL;
3676 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3677 AssertRCReturn(rc, ZeroPde);
3678#else
3679 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3680 if ( !pGuestPD
3681 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3682 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3683#endif
3684 return pGuestPD->a[iPD];
3685 }
3686 }
3687 return ZeroPde;
3688}
3689
3690
3691/**
3692 * Gets the page directory pointer table entry for the specified address
3693 * and returns the index into the page directory
3694 *
3695 * @returns Pointer to the page directory in question.
3696 * @returns NULL if the page directory is not present or on an invalid page.
3697 * @param pPGM Pointer to the PGM instance data.
3698 * @param GCPtr The address.
3699 * @param piPD Receives the index into the returned page directory
3700 * @param pPdpe Receives the page directory pointer entry. Optional.
3701 */
3702DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3703{
3704 AssertGCPtr32(GCPtr);
3705
3706 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3707 AssertReturn(pGuestPDPT, NULL);
3708 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3709 if (pPdpe)
3710 *pPdpe = pGuestPDPT->a[iPdpt];
3711 if (pGuestPDPT->a[iPdpt].n.u1Present)
3712 {
3713 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3714#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3715 PX86PDPAE pGuestPD = NULL;
3716 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3717 AssertRCReturn(rc, NULL);
3718#else
3719 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3720 if ( !pGuestPD
3721 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3722 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3723#endif
3724 *piPD = iPD;
3725 return pGuestPD;
3726 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3727 }
3728 return NULL;
3729}
3730
3731#ifndef IN_RC
3732
3733/**
3734 * Gets the page map level-4 pointer for the guest.
3735 *
3736 * @returns Pointer to the PML4 page.
3737 * @param pPGM Pointer to the PGM instance data.
3738 */
3739DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
3740{
3741#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3742 PX86PML4 pGuestPml4;
3743 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3744 AssertRCReturn(rc, NULL);
3745#else
3746 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3747# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3748 if (!pGuestPml4)
3749 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3750# endif
3751 Assert(pGuestPml4);
3752#endif
3753 return pGuestPml4;
3754}
3755
3756
3757/**
3758 * Gets the pointer to a page map level-4 entry.
3759 *
3760 * @returns Pointer to the PML4 entry.
3761 * @param pPGM Pointer to the PGM instance data.
3762 * @param iPml4 The index.
3763 */
3764DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
3765{
3766#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3767 PX86PML4 pGuestPml4;
3768 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3769 AssertRCReturn(rc, NULL);
3770#else
3771 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3772# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3773 if (!pGuestPml4)
3774 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3775# endif
3776 Assert(pGuestPml4);
3777#endif
3778 return &pGuestPml4->a[iPml4];
3779}
3780
3781
3782/**
3783 * Gets a page map level-4 entry.
3784 *
3785 * @returns The PML4 entry.
3786 * @param pPGM Pointer to the PGM instance data.
3787 * @param iPml4 The index.
3788 */
3789DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
3790{
3791#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3792 PX86PML4 pGuestPml4;
3793 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3794 if (RT_FAILURE(rc))
3795 {
3796 X86PML4E ZeroPml4e = {0};
3797 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3798 }
3799#else
3800 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3801# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3802 if (!pGuestPml4)
3803 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3804# endif
3805 Assert(pGuestPml4);
3806#endif
3807 return pGuestPml4->a[iPml4];
3808}
3809
3810
3811/**
3812 * Gets the page directory pointer entry for the specified address.
3813 *
3814 * @returns Pointer to the page directory pointer entry in question.
3815 * @returns NULL if the page directory is not present or on an invalid page.
3816 * @param pPGM Pointer to the PGM instance data.
3817 * @param GCPtr The address.
3818 * @param ppPml4e Page Map Level-4 Entry (out)
3819 */
3820DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3821{
3822 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3823 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3824 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3825 if (pPml4e->n.u1Present)
3826 {
3827 PX86PDPT pPdpt;
3828 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3829 AssertRCReturn(rc, NULL);
3830
3831 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3832 return &pPdpt->a[iPdpt];
3833 }
3834 return NULL;
3835}
3836
3837
3838/**
3839 * Gets the page directory entry for the specified address.
3840 *
3841 * @returns The page directory entry in question.
3842 * @returns A non-present entry if the page directory is not present or on an invalid page.
3843 * @param pPGM Pointer to the PGM instance data.
3844 * @param GCPtr The address.
3845 * @param ppPml4e Page Map Level-4 Entry (out)
3846 * @param pPdpe Page directory pointer table entry (out)
3847 */
3848DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3849{
3850 X86PDEPAE ZeroPde = {0};
3851 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3852 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3853 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3854 if (pPml4e->n.u1Present)
3855 {
3856 PCX86PDPT pPdptTemp;
3857 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3858 AssertRCReturn(rc, ZeroPde);
3859
3860 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3861 *pPdpe = pPdptTemp->a[iPdpt];
3862 if (pPdptTemp->a[iPdpt].n.u1Present)
3863 {
3864 PCX86PDPAE pPD;
3865 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3866 AssertRCReturn(rc, ZeroPde);
3867
3868 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3869 return pPD->a[iPD];
3870 }
3871 }
3872
3873 return ZeroPde;
3874}
3875
3876
3877/**
3878 * Gets the page directory entry for the specified address.
3879 *
3880 * @returns The page directory entry in question.
3881 * @returns A non-present entry if the page directory is not present or on an invalid page.
3882 * @param pPGM Pointer to the PGM instance data.
3883 * @param GCPtr The address.
3884 */
3885DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
3886{
3887 X86PDEPAE ZeroPde = {0};
3888 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3889 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3890 if (pGuestPml4->a[iPml4].n.u1Present)
3891 {
3892 PCX86PDPT pPdptTemp;
3893 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3894 AssertRCReturn(rc, ZeroPde);
3895
3896 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3897 if (pPdptTemp->a[iPdpt].n.u1Present)
3898 {
3899 PCX86PDPAE pPD;
3900 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3901 AssertRCReturn(rc, ZeroPde);
3902
3903 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3904 return pPD->a[iPD];
3905 }
3906 }
3907 return ZeroPde;
3908}
3909
3910
3911/**
3912 * Gets the page directory entry for the specified address.
3913 *
3914 * @returns Pointer to the page directory entry in question.
3915 * @returns NULL if the page directory is not present or on an invalid page.
3916 * @param pPGM Pointer to the PGM instance data.
3917 * @param GCPtr The address.
3918 */
3919DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
3920{
3921 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3922 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3923 if (pGuestPml4->a[iPml4].n.u1Present)
3924 {
3925 PCX86PDPT pPdptTemp;
3926 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
3927 AssertRCReturn(rc, NULL);
3928
3929 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3930 if (pPdptTemp->a[iPdpt].n.u1Present)
3931 {
3932 PX86PDPAE pPD;
3933 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3934 AssertRCReturn(rc, NULL);
3935
3936 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3937 return &pPD->a[iPD];
3938 }
3939 }
3940 return NULL;
3941}
3942
3943
3944/**
3945 * Gets the GUEST page directory pointer for the specified address.
3946 *
3947 * @returns The page directory in question.
3948 * @returns NULL if the page directory is not present or on an invalid page.
3949 * @param pPGM Pointer to the PGM instance data.
3950 * @param GCPtr The address.
3951 * @param ppPml4e Page Map Level-4 Entry (out)
3952 * @param pPdpe Page directory pointer table entry (out)
3953 * @param piPD Receives the index into the returned page directory
3954 */
3955DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
3956{
3957 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3958 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3959 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3960 if (pPml4e->n.u1Present)
3961 {
3962 PCX86PDPT pPdptTemp;
3963 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3964 AssertRCReturn(rc, NULL);
3965
3966 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3967 *pPdpe = pPdptTemp->a[iPdpt];
3968 if (pPdptTemp->a[iPdpt].n.u1Present)
3969 {
3970 PX86PDPAE pPD;
3971 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
3972 AssertRCReturn(rc, NULL);
3973
3974 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3975 return pPD;
3976 }
3977 }
3978 return 0;
3979}
3980
3981#endif /* !IN_RC */
3982
3983/**
3984 * Gets the shadow page directory, 32-bit.
3985 *
3986 * @returns Pointer to the shadow 32-bit PD.
3987 * @param pPGM Pointer to the PGM instance data.
3988 */
3989DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
3990{
3991 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
3992}
3993
3994
3995/**
3996 * Gets the shadow page directory entry for the specified address, 32-bit.
3997 *
3998 * @returns Shadow 32-bit PDE.
3999 * @param pPGM Pointer to the PGM instance data.
4000 * @param GCPtr The address.
4001 */
4002DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4003{
4004 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4005
4006 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4007 if (!pShwPde)
4008 {
4009 X86PDE ZeroPde = {0};
4010 return ZeroPde;
4011 }
4012 return pShwPde->a[iPd];
4013}
4014
4015
4016/**
4017 * Gets the pointer to the shadow page directory entry for the specified
4018 * address, 32-bit.
4019 *
4020 * @returns Pointer to the shadow 32-bit PDE.
4021 * @param pPGM Pointer to the PGM instance data.
4022 * @param GCPtr The address.
4023 */
4024DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4025{
4026 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4027
4028 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4029 AssertReturn(pPde, NULL);
4030 return &pPde->a[iPd];
4031}
4032
4033
4034/**
4035 * Gets the shadow page pointer table, PAE.
4036 *
4037 * @returns Pointer to the shadow PAE PDPT.
4038 * @param pPGM Pointer to the PGM instance data.
4039 */
4040DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4041{
4042 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4043}
4044
4045
4046/**
4047 * Gets the shadow page directory for the specified address, PAE.
4048 *
4049 * @returns Pointer to the shadow PD.
4050 * @param pPGM Pointer to the PGM instance data.
4051 * @param GCPtr The address.
4052 */
4053DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4054{
4055 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4056 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4057
4058 if (!pPdpt->a[iPdpt].n.u1Present)
4059 return NULL;
4060
4061 /* Fetch the pgm pool shadow descriptor. */
4062 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4063 AssertReturn(pShwPde, NULL);
4064
4065 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4066}
4067
4068
4069/**
4070 * Gets the shadow page directory for the specified address, PAE.
4071 *
4072 * @returns Pointer to the shadow PD.
4073 * @param pPGM Pointer to the PGM instance data.
4074 * @param GCPtr The address.
4075 */
4076DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4077{
4078 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4079
4080 if (!pPdpt->a[iPdpt].n.u1Present)
4081 return NULL;
4082
4083 /* Fetch the pgm pool shadow descriptor. */
4084 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4085 AssertReturn(pShwPde, NULL);
4086
4087 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4088}
4089
4090
4091/**
4092 * Gets the shadow page directory entry, PAE.
4093 *
4094 * @returns PDE.
4095 * @param pPGM Pointer to the PGM instance data.
4096 * @param GCPtr The address.
4097 */
4098DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4099{
4100 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4101
4102 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4103 if (!pShwPde)
4104 {
4105 X86PDEPAE ZeroPde = {0};
4106 return ZeroPde;
4107 }
4108 return pShwPde->a[iPd];
4109}
4110
4111
4112/**
4113 * Gets the pointer to the shadow page directory entry for an address, PAE.
4114 *
4115 * @returns Pointer to the PDE.
4116 * @param pPGM Pointer to the PGM instance data.
4117 * @param GCPtr The address.
4118 */
4119DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4120{
4121 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4122
4123 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4124 AssertReturn(pPde, NULL);
4125 return &pPde->a[iPd];
4126}
4127
4128#ifndef IN_RC
4129
4130/**
4131 * Gets the shadow page map level-4 pointer.
4132 *
4133 * @returns Pointer to the shadow PML4.
4134 * @param pPGM Pointer to the PGM instance data.
4135 */
4136DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4137{
4138 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4139}
4140
4141
4142/**
4143 * Gets the shadow page map level-4 entry for the specified address.
4144 *
4145 * @returns The entry.
4146 * @param pPGM Pointer to the PGM instance data.
4147 * @param GCPtr The address.
4148 */
4149DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4150{
4151 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4152 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4153
4154 if (!pShwPml4)
4155 {
4156 X86PML4E ZeroPml4e = {0};
4157 return ZeroPml4e;
4158 }
4159 return pShwPml4->a[iPml4];
4160}
4161
4162
4163/**
4164 * Gets the pointer to the specified shadow page map level-4 entry.
4165 *
4166 * @returns The entry.
4167 * @param pPGM Pointer to the PGM instance data.
4168 * @param iPml4 The PML4 index.
4169 */
4170DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4171{
4172 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4173 if (!pShwPml4)
4174 return NULL;
4175 return &pShwPml4->a[iPml4];
4176}
4177
4178
4179/**
4180 * Gets the GUEST page directory pointer for the specified address.
4181 *
4182 * @returns The page directory in question.
4183 * @returns NULL if the page directory is not present or on an invalid page.
4184 * @param pPGM Pointer to the PGM instance data.
4185 * @param GCPtr The address.
4186 * @param piPD Receives the index into the returned page directory
4187 */
4188DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4189{
4190 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4191 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4192 if (pGuestPml4->a[iPml4].n.u1Present)
4193 {
4194 PCX86PDPT pPdptTemp;
4195 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4196 AssertRCReturn(rc, NULL);
4197
4198 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4199 if (pPdptTemp->a[iPdpt].n.u1Present)
4200 {
4201 PX86PDPAE pPD;
4202 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4203 AssertRCReturn(rc, NULL);
4204
4205 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4206 return pPD;
4207 }
4208 }
4209 return NULL;
4210}
4211
4212#endif /* !IN_RC */
4213
4214/**
4215 * Gets the page state for a physical handler.
4216 *
4217 * @returns The physical handler page state.
4218 * @param pCur The physical handler in question.
4219 */
4220DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4221{
4222 switch (pCur->enmType)
4223 {
4224 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4225 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4226
4227 case PGMPHYSHANDLERTYPE_MMIO:
4228 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4229 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4230
4231 default:
4232 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4233 }
4234}
4235
4236
4237/**
4238 * Gets the page state for a virtual handler.
4239 *
4240 * @returns The virtual handler page state.
4241 * @param pCur The virtual handler in question.
4242 * @remarks This should never be used on a hypervisor access handler.
4243 */
4244DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4245{
4246 switch (pCur->enmType)
4247 {
4248 case PGMVIRTHANDLERTYPE_WRITE:
4249 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4250 case PGMVIRTHANDLERTYPE_ALL:
4251 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4252 default:
4253 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4254 }
4255}
4256
4257
4258/**
4259 * Clears one physical page of a virtual handler
4260 *
4261 * @param pPGM Pointer to the PGM instance.
4262 * @param pCur Virtual handler structure
4263 * @param iPage Physical page index
4264 *
4265 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4266 * need to care about other handlers in the same page.
4267 */
4268DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4269{
4270 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4271
4272 /*
4273 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4274 */
4275#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4276 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4277 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4278 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4279#endif
4280 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4281 {
4282 /* We're the head of the alias chain. */
4283 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4284#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4285 AssertReleaseMsg(pRemove != NULL,
4286 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4287 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4288 AssertReleaseMsg(pRemove == pPhys2Virt,
4289 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4290 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4291 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4292 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4293#endif
4294 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4295 {
4296 /* Insert the next list in the alias chain into the tree. */
4297 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4298#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4299 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4300 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4301 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4302#endif
4303 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4304 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4305 AssertRelease(fRc);
4306 }
4307 }
4308 else
4309 {
4310 /* Locate the previous node in the alias chain. */
4311 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4312#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4313 AssertReleaseMsg(pPrev != pPhys2Virt,
4314 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4315 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4316#endif
4317 for (;;)
4318 {
4319 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4320 if (pNext == pPhys2Virt)
4321 {
4322 /* unlink. */
4323 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4324 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4325 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4326 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4327 else
4328 {
4329 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4330 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4331 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4332 }
4333 break;
4334 }
4335
4336 /* next */
4337 if (pNext == pPrev)
4338 {
4339#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4340 AssertReleaseMsg(pNext != pPrev,
4341 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4342 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4343#endif
4344 break;
4345 }
4346 pPrev = pNext;
4347 }
4348 }
4349 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4350 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4351 pPhys2Virt->offNextAlias = 0;
4352 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4353
4354 /*
4355 * Clear the ram flags for this page.
4356 */
4357 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4358 AssertReturnVoid(pPage);
4359 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4360}
4361
4362
4363/**
4364 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4365 *
4366 * @returns Pointer to the shadow page structure.
4367 * @param pPool The pool.
4368 * @param idx The pool page index.
4369 */
4370DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4371{
4372 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4373 return &pPool->aPages[idx];
4374}
4375
4376
4377#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4378/**
4379 * Clear references to guest physical memory.
4380 *
4381 * @param pPool The pool.
4382 * @param pPoolPage The pool page.
4383 * @param pPhysPage The physical guest page tracking structure.
4384 */
4385DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4386{
4387 /*
4388 * Just deal with the simple case here.
4389 */
4390# ifdef LOG_ENABLED
4391 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4392# endif
4393 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4394 if (cRefs == 1)
4395 {
4396 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4397 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4398 }
4399 else
4400 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4401 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4402}
4403#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4404
4405
4406#ifdef PGMPOOL_WITH_CACHE
4407/**
4408 * Moves the page to the head of the age list.
4409 *
4410 * This is done when the cached page is used in one way or another.
4411 *
4412 * @param pPool The pool.
4413 * @param pPage The cached page.
4414 */
4415DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4416{
4417 PVM pVM = pPool->CTX_SUFF(pVM);
4418 pgmLock(pVM);
4419
4420 /*
4421 * Move to the head of the age list.
4422 */
4423 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4424 {
4425 /* unlink */
4426 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4427 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4428 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4429 else
4430 pPool->iAgeTail = pPage->iAgePrev;
4431
4432 /* insert at head */
4433 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4434 pPage->iAgeNext = pPool->iAgeHead;
4435 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4436 pPool->iAgeHead = pPage->idx;
4437 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4438 }
4439 pgmUnlock(pVM);
4440}
4441#endif /* PGMPOOL_WITH_CACHE */
4442
4443/**
4444 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4445 *
4446 * @param pVM VM Handle.
4447 * @param pPage PGM pool page
4448 */
4449DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4450{
4451 ASMAtomicIncU32(&pPage->cLocked);
4452}
4453
4454
4455/**
4456 * Unlocks a page to allow flushing again
4457 *
4458 * @param pVM VM Handle.
4459 * @param pPage PGM pool page
4460 */
4461DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4462{
4463 Assert(pPage->cLocked);
4464 ASMAtomicDecU32(&pPage->cLocked);
4465}
4466
4467
4468/**
4469 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4470 *
4471 * @returns VBox status code.
4472 * @param pPage PGM pool page
4473 */
4474DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4475{
4476 if (pPage->cLocked)
4477 {
4478 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4479 if (pPage->cModifications)
4480 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4481 return true;
4482 }
4483 return false;
4484}
4485
4486/**
4487 * Tells if mappings are to be put into the shadow page table or not
4488 *
4489 * @returns boolean result
4490 * @param pVM VM handle.
4491 */
4492DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4493{
4494#ifdef IN_RING0
4495 /* There are no mappings in VT-x and AMD-V mode. */
4496 Assert(pPGM->fDisableMappings);
4497 return false;
4498#else
4499 return !pPGM->fDisableMappings;
4500#endif
4501}
4502
4503/** @} */
4504
4505#endif
4506
4507
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