VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 17417

Last change on this file since 17417 was 17371, checked in by vboxsync, 16 years ago

PGM,GMM: Hacking on the new phys code.
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1/* $Id: PGMInternal.h 17371 2009-03-05 01:37:58Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42
43
44
45/** @defgroup grp_pgm_int Internals
46 * @ingroup grp_pgm
47 * @internal
48 * @{
49 */
50
51
52/** @name PGM Compile Time Config
53 * @{
54 */
55
56/*
57 * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
58 */
59#define VBOX_WITH_PGMPOOL_PAGING_ONLY
60
61/**
62 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
63 * Comment it if it will break something.
64 */
65#define PGM_OUT_OF_SYNC_IN_GC
66
67/**
68 * Check and skip global PDEs for non-global flushes
69 */
70#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
71
72/**
73 * Sync N pages instead of a whole page table
74 */
75#define PGM_SYNC_N_PAGES
76
77/**
78 * Number of pages to sync during a page fault
79 *
80 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
81 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
82 */
83#define PGM_SYNC_NR_PAGES 8
84
85/**
86 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
87 */
88#define PGM_MAX_PHYSCACHE_ENTRIES 64
89#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
90
91/**
92 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
93 */
94#define PGM_PHYSMEMACCESS_CACHING
95
96/** @def PGMPOOL_WITH_CACHE
97 * Enable agressive caching using the page pool.
98 *
99 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
100 */
101#define PGMPOOL_WITH_CACHE
102
103/** @def PGMPOOL_WITH_MIXED_PT_CR3
104 * When defined, we'll deal with 'uncachable' pages.
105 */
106#ifdef PGMPOOL_WITH_CACHE
107# define PGMPOOL_WITH_MIXED_PT_CR3
108#endif
109
110/** @def PGMPOOL_WITH_MONITORING
111 * Monitor the guest pages which are shadowed.
112 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
113 * be enabled as well.
114 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
115 */
116#ifdef PGMPOOL_WITH_CACHE
117# define PGMPOOL_WITH_MONITORING
118#endif
119
120/** @def PGMPOOL_WITH_GCPHYS_TRACKING
121 * Tracking the of shadow pages mapping guest physical pages.
122 *
123 * This is very expensive, the current cache prototype is trying to figure out
124 * whether it will be acceptable with an agressive caching policy.
125 */
126#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
127# define PGMPOOL_WITH_GCPHYS_TRACKING
128#endif
129
130/** @def PGMPOOL_WITH_USER_TRACKING
131 * Tracking users of shadow pages. This is required for the linking of shadow page
132 * tables and physical guest addresses.
133 */
134#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
135# define PGMPOOL_WITH_USER_TRACKING
136#endif
137
138/** @def PGMPOOL_CFG_MAX_GROW
139 * The maximum number of pages to add to the pool in one go.
140 */
141#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
142
143/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
144 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
145 */
146#ifdef VBOX_STRICT
147# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
148#endif
149/** @} */
150
151
152/** @name PDPT and PML4 flags.
153 * These are placed in the three bits available for system programs in
154 * the PDPT and PML4 entries.
155 * @{ */
156/** The entry is a permanent one and it's must always be present.
157 * Never free such an entry. */
158#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
159/** Mapping (hypervisor allocated pagetable). */
160#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
161/** @} */
162
163/** @name Page directory flags.
164 * These are placed in the three bits available for system programs in
165 * the page directory entries.
166 * @{ */
167/** Mapping (hypervisor allocated pagetable). */
168#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
169/** Made read-only to facilitate dirty bit tracking. */
170#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
171/** @} */
172
173/** @name Page flags.
174 * These are placed in the three bits available for system programs in
175 * the page entries.
176 * @{ */
177/** Made read-only to facilitate dirty bit tracking. */
178#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
179
180#ifndef PGM_PTFLAGS_CSAM_VALIDATED
181/** Scanned and approved by CSAM (tm).
182 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
183 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
184#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
185#endif
186
187/** Mark a dynamic map entry (PGMDynMapHCPage) as locked. */
188#define PGM_PTFLAGS_DYN_LOCKED RT_BIT(9)
189
190/** @} */
191
192/** @name Defines used to indicate the shadow and guest paging in the templates.
193 * @{ */
194#define PGM_TYPE_REAL 1
195#define PGM_TYPE_PROT 2
196#define PGM_TYPE_32BIT 3
197#define PGM_TYPE_PAE 4
198#define PGM_TYPE_AMD64 5
199#define PGM_TYPE_NESTED 6
200#define PGM_TYPE_EPT 7
201#define PGM_TYPE_MAX PGM_TYPE_EPT
202/** @} */
203
204/** Macro for checking if the guest is using paging.
205 * @param uGstType PGM_TYPE_*
206 * @param uShwType PGM_TYPE_*
207 * @remark ASSUMES certain order of the PGM_TYPE_* values.
208 */
209#define PGM_WITH_PAGING(uGstType, uShwType) \
210 ( (uGstType) >= PGM_TYPE_32BIT \
211 && (uShwType) != PGM_TYPE_NESTED \
212 && (uShwType) != PGM_TYPE_EPT)
213
214/** Macro for checking if the guest supports the NX bit.
215 * @param uGstType PGM_TYPE_*
216 * @param uShwType PGM_TYPE_*
217 * @remark ASSUMES certain order of the PGM_TYPE_* values.
218 */
219#define PGM_WITH_NX(uGstType, uShwType) \
220 ( (uGstType) >= PGM_TYPE_PAE \
221 && (uShwType) != PGM_TYPE_NESTED \
222 && (uShwType) != PGM_TYPE_EPT)
223
224
225/** @def PGM_HCPHYS_2_PTR
226 * Maps a HC physical page pool address to a virtual address.
227 *
228 * @returns VBox status code.
229 * @param pVM The VM handle.
230 * @param HCPhys The HC physical address to map to a virtual one.
231 * @param ppv Where to store the virtual address. No need to cast this.
232 *
233 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
234 * small page window employeed by that function. Be careful.
235 * @remark There is no need to assert on the result.
236 */
237#ifdef IN_RC
238# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
240#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
243#else
244# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_HCPHYS_2_PTR_BY_PGM
249 * Maps a HC physical page pool address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pPGM The PGM instance data.
253 * @param HCPhys The HC physical address to map to a virtual one.
254 * @param ppv Where to store the virtual address. No need to cast this.
255 *
256 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
257 * small page window employeed by that function. Be careful.
258 * @remark There is no need to assert on the result.
259 */
260#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
261# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
263#else
264# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
265 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
266#endif
267
268/** @def PGM_GCPHYS_2_PTR
269 * Maps a GC physical page address to a virtual address.
270 *
271 * @returns VBox status code.
272 * @param pVM The VM handle.
273 * @param GCPhys The GC physical address to map to a virtual one.
274 * @param ppv Where to store the virtual address. No need to cast this.
275 *
276 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
277 * small page window employeed by that function. Be careful.
278 * @remark There is no need to assert on the result.
279 */
280#ifdef IN_RC
281# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
283#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
286#else
287# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
288 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
289#endif
290
291/** @def PGM_GCPHYS_2_PTR_BY_PGM
292 * Maps a GC physical page address to a virtual address.
293 *
294 * @returns VBox status code.
295 * @param pPGM Pointer to the PGM instance data.
296 * @param GCPhys The GC physical address to map to a virtual one.
297 * @param ppv Where to store the virtual address. No need to cast this.
298 *
299 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
300 * small page window employeed by that function. Be careful.
301 * @remark There is no need to assert on the result.
302 */
303#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
304# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
305 pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
306#else
307# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
308 PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
309#endif
310
311/** @def PGM_GCPHYS_2_PTR_EX
312 * Maps a unaligned GC physical page address to a virtual address.
313 *
314 * @returns VBox status code.
315 * @param pVM The VM handle.
316 * @param GCPhys The GC physical address to map to a virtual one.
317 * @param ppv Where to store the virtual address. No need to cast this.
318 *
319 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
320 * small page window employeed by that function. Be careful.
321 * @remark There is no need to assert on the result.
322 */
323#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
324# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
326#else
327# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
328 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
329#endif
330
331/** @def PGM_INVL_PG
332 * Invalidates a page when in GC does nothing in HC.
333 *
334 * @param GCVirt The virtual address of the page to invalidate.
335 */
336#ifdef IN_RC
337# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
338#elif defined(IN_RING0)
339# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
340#else
341# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
342#endif
343
344/** @def PGM_INVL_BIG_PG
345 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
346 *
347 * @param GCVirt The virtual address within the page directory to invalidate.
348 */
349#ifdef IN_RC
350# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
351#elif defined(IN_RING0)
352# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
353#else
354# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
355#endif
356
357/** @def PGM_INVL_GUEST_TLBS()
358 * Invalidates all guest TLBs.
359 */
360#ifdef IN_RC
361# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
362#elif defined(IN_RING0)
363# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
364#else
365# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
366#endif
367
368
369/**
370 * Structure for tracking GC Mappings.
371 *
372 * This structure is used by linked list in both GC and HC.
373 */
374typedef struct PGMMAPPING
375{
376 /** Pointer to next entry. */
377 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
378 /** Pointer to next entry. */
379 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
380 /** Pointer to next entry. */
381 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
382 /** Indicate whether this entry is finalized. */
383 bool fFinalized;
384 /** Start Virtual address. */
385 RTGCPTR GCPtr;
386 /** Last Virtual address (inclusive). */
387 RTGCPTR GCPtrLast;
388 /** Range size (bytes). */
389 RTGCPTR cb;
390 /** Pointer to relocation callback function. */
391 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
392 /** User argument to the callback. */
393 R3PTRTYPE(void *) pvUser;
394 /** Mapping description / name. For easing debugging. */
395 R3PTRTYPE(const char *) pszDesc;
396 /** Number of page tables. */
397 uint32_t cPTs;
398#if HC_ARCH_BITS != GC_ARCH_BITS || GC_ARCH_BITS == 64
399 uint32_t uPadding1; /**< Alignment padding. */
400#endif
401 /** Array of page table mapping data. Each entry
402 * describes one page table. The array can be longer
403 * than the declared length.
404 */
405 struct
406 {
407 /** The HC physical address of the page table. */
408 RTHCPHYS HCPhysPT;
409 /** The HC physical address of the first PAE page table. */
410 RTHCPHYS HCPhysPaePT0;
411 /** The HC physical address of the second PAE page table. */
412 RTHCPHYS HCPhysPaePT1;
413 /** The HC virtual address of the 32-bit page table. */
414 R3PTRTYPE(PX86PT) pPTR3;
415 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
416 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
417 /** The GC virtual address of the 32-bit page table. */
418 RCPTRTYPE(PX86PT) pPTRC;
419 /** The GC virtual address of the two PAE page table. */
420 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
421 /** The GC virtual address of the 32-bit page table. */
422 R0PTRTYPE(PX86PT) pPTR0;
423 /** The GC virtual address of the two PAE page table. */
424 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
425 } aPTs[1];
426} PGMMAPPING;
427/** Pointer to structure for tracking GC Mappings. */
428typedef struct PGMMAPPING *PPGMMAPPING;
429
430
431/**
432 * Physical page access handler structure.
433 *
434 * This is used to keep track of physical address ranges
435 * which are being monitored in some kind of way.
436 */
437typedef struct PGMPHYSHANDLER
438{
439 AVLROGCPHYSNODECORE Core;
440 /** Access type. */
441 PGMPHYSHANDLERTYPE enmType;
442 /** Number of pages to update. */
443 uint32_t cPages;
444 /** Pointer to R3 callback function. */
445 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
446 /** User argument for R3 handlers. */
447 R3PTRTYPE(void *) pvUserR3;
448 /** Pointer to R0 callback function. */
449 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
450 /** User argument for R0 handlers. */
451 R0PTRTYPE(void *) pvUserR0;
452 /** Pointer to GC callback function. */
453 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
454 /** User argument for RC handlers. */
455 RCPTRTYPE(void *) pvUserRC;
456 /** Description / Name. For easing debugging. */
457 R3PTRTYPE(const char *) pszDesc;
458#ifdef VBOX_WITH_STATISTICS
459 /** Profiling of this handler. */
460 STAMPROFILE Stat;
461#endif
462} PGMPHYSHANDLER;
463/** Pointer to a physical page access handler structure. */
464typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
465
466
467/**
468 * Cache node for the physical addresses covered by a virtual handler.
469 */
470typedef struct PGMPHYS2VIRTHANDLER
471{
472 /** Core node for the tree based on physical ranges. */
473 AVLROGCPHYSNODECORE Core;
474 /** Offset from this struct to the PGMVIRTHANDLER structure. */
475 int32_t offVirtHandler;
476 /** Offset of the next alias relative to this one.
477 * Bit 0 is used for indicating whether we're in the tree.
478 * Bit 1 is used for indicating that we're the head node.
479 */
480 int32_t offNextAlias;
481} PGMPHYS2VIRTHANDLER;
482/** Pointer to a phys to virtual handler structure. */
483typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
484
485/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
486 * node is in the tree. */
487#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
488/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
489 * node is in the head of an alias chain.
490 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
491#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
492/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
493#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
494
495
496/**
497 * Virtual page access handler structure.
498 *
499 * This is used to keep track of virtual address ranges
500 * which are being monitored in some kind of way.
501 */
502typedef struct PGMVIRTHANDLER
503{
504 /** Core node for the tree based on virtual ranges. */
505 AVLROGCPTRNODECORE Core;
506 /** Size of the range (in bytes). */
507 RTGCPTR cb;
508 /** Number of cache pages. */
509 uint32_t cPages;
510 /** Access type. */
511 PGMVIRTHANDLERTYPE enmType;
512 /** Pointer to the RC callback function. */
513 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
514#if HC_ARCH_BITS == 64
515 RTRCPTR padding;
516#endif
517 /** Pointer to the R3 callback function for invalidation. */
518 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
519 /** Pointer to the R3 callback function. */
520 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
521 /** Description / Name. For easing debugging. */
522 R3PTRTYPE(const char *) pszDesc;
523#ifdef VBOX_WITH_STATISTICS
524 /** Profiling of this handler. */
525 STAMPROFILE Stat;
526#endif
527 /** Array of cached physical addresses for the monitored ranged. */
528 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
529} PGMVIRTHANDLER;
530/** Pointer to a virtual page access handler structure. */
531typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
532
533
534/**
535 * Page type.
536 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
537 * @todo convert to \#defines.
538 */
539typedef enum PGMPAGETYPE
540{
541 /** The usual invalid zero entry. */
542 PGMPAGETYPE_INVALID = 0,
543 /** RAM page. (RWX) */
544 PGMPAGETYPE_RAM,
545 /** MMIO2 page. (RWX) */
546 PGMPAGETYPE_MMIO2,
547 /** MMIO2 page aliased over an MMIO page. (RWX)
548 * See PGMHandlerPhysicalPageAlias(). */
549 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
550 /** Shadowed ROM. (RWX) */
551 PGMPAGETYPE_ROM_SHADOW,
552 /** ROM page. (R-X) */
553 PGMPAGETYPE_ROM,
554 /** MMIO page. (---) */
555 PGMPAGETYPE_MMIO,
556 /** End of valid entries. */
557 PGMPAGETYPE_END
558} PGMPAGETYPE;
559AssertCompile(PGMPAGETYPE_END <= 7);
560
561/** @name Page type predicates.
562 * @{ */
563#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
564#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
565#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
566#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
567#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
568/** @} */
569
570
571/**
572 * A Physical Guest Page tracking structure.
573 *
574 * The format of this structure is complicated because we have to fit a lot
575 * of information into as few bits as possible. The format is also subject
576 * to change (there is one comming up soon). Which means that for we'll be
577 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
578 * accessess to the structure.
579 */
580typedef struct PGMPAGE
581{
582 /** The physical address and a whole lot of other stuff. All bits are used! */
583#ifdef VBOX_WITH_NEW_PHYS_CODE
584 RTHCPHYS HCPhysX;
585#else
586 RTHCPHYS HCPhys;
587#define HCPhysX HCPhys /**< Temporary while in the process of eliminating direct access to PGMPAGE::HCPhys. */
588#endif
589 /** The page state. */
590 uint32_t u2StateX : 2;
591 /** Flag indicating that a write monitored page was written to when set. */
592 uint32_t fWrittenToX : 1;
593 /** For later. */
594 uint32_t fSomethingElse : 1;
595 /** The Page ID.
596 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
597 * The HCPhysX will then be 100% static. */
598 uint32_t idPageX : 28;
599 /** The page type (PGMPAGETYPE). */
600 uint32_t u3Type : 3;
601 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
602 uint32_t u2HandlerPhysStateX : 2;
603 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
604 uint32_t u2HandlerVirtStateX : 2;
605 uint32_t u29B : 25;
606} PGMPAGE;
607AssertCompileSize(PGMPAGE, 16);
608/** Pointer to a physical guest page. */
609typedef PGMPAGE *PPGMPAGE;
610/** Pointer to a const physical guest page. */
611typedef const PGMPAGE *PCPGMPAGE;
612/** Pointer to a physical guest page pointer. */
613typedef PPGMPAGE *PPPGMPAGE;
614
615
616/**
617 * Clears the page structure.
618 * @param pPage Pointer to the physical guest page tracking structure.
619 */
620#define PGM_PAGE_CLEAR(pPage) \
621 do { \
622 (pPage)->HCPhysX = 0; \
623 (pPage)->u2StateX = 0; \
624 (pPage)->fWrittenToX = 0; \
625 (pPage)->fSomethingElse = 0; \
626 (pPage)->idPageX = 0; \
627 (pPage)->u3Type = 0; \
628 (pPage)->u29B = 0; \
629 } while (0)
630
631/**
632 * Initializes the page structure.
633 * @param pPage Pointer to the physical guest page tracking structure.
634 */
635#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
636 do { \
637 (pPage)->HCPhysX = (_HCPhys); \
638 (pPage)->u2StateX = (_uState); \
639 (pPage)->fWrittenToX = 0; \
640 (pPage)->fSomethingElse = 0; \
641 (pPage)->idPageX = (_idPage); \
642 /*(pPage)->u3Type = (_uType); - later */ \
643 PGM_PAGE_SET_TYPE(pPage, _uType); \
644 (pPage)->u29B = 0; \
645 } while (0)
646
647/**
648 * Initializes the page structure of a ZERO page.
649 * @param pPage Pointer to the physical guest page tracking structure.
650 */
651#ifdef VBOX_WITH_NEW_PHYS_CODE
652# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
653 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
654#else
655# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
656 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
657#endif
658/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
659# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
660 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
661
662
663/** @name The Page state, PGMPAGE::u2StateX.
664 * @{ */
665/** The zero page.
666 * This is a per-VM page that's never ever mapped writable. */
667#define PGM_PAGE_STATE_ZERO 0
668/** A allocated page.
669 * This is a per-VM page allocated from the page pool (or wherever
670 * we get MMIO2 pages from if the type is MMIO2).
671 */
672#define PGM_PAGE_STATE_ALLOCATED 1
673/** A allocated page that's being monitored for writes.
674 * The shadow page table mappings are read-only. When a write occurs, the
675 * fWrittenTo member is set, the page remapped as read-write and the state
676 * moved back to allocated. */
677#define PGM_PAGE_STATE_WRITE_MONITORED 2
678/** The page is shared, aka. copy-on-write.
679 * This is a page that's shared with other VMs. */
680#define PGM_PAGE_STATE_SHARED 3
681/** @} */
682
683
684/**
685 * Gets the page state.
686 * @returns page state (PGM_PAGE_STATE_*).
687 * @param pPage Pointer to the physical guest page tracking structure.
688 */
689#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
690
691/**
692 * Sets the page state.
693 * @param pPage Pointer to the physical guest page tracking structure.
694 * @param _uState The new page state.
695 */
696#define PGM_PAGE_SET_STATE(pPage, _uState) \
697 do { (pPage)->u2StateX = (_uState); } while (0)
698
699
700/**
701 * Gets the host physical address of the guest page.
702 * @returns host physical address (RTHCPHYS).
703 * @param pPage Pointer to the physical guest page tracking structure.
704 */
705#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
706
707/**
708 * Sets the host physical address of the guest page.
709 * @param pPage Pointer to the physical guest page tracking structure.
710 * @param _HCPhys The new host physical address.
711 */
712#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
713 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
714 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
715
716/**
717 * Get the Page ID.
718 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
719 * @param pPage Pointer to the physical guest page tracking structure.
720 */
721#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
722/* later:
723#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
724 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
725*/
726/**
727 * Sets the Page ID.
728 * @param pPage Pointer to the physical guest page tracking structure.
729 */
730#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
731/* later:
732#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
733 | ((_idPage) & 0xfff) \
734 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
735*/
736
737/**
738 * Get the Chunk ID.
739 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
740 * @param pPage Pointer to the physical guest page tracking structure.
741 */
742#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
743/* later:
744#if GMM_CHUNKID_SHIFT == 12
745# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
746#elif GMM_CHUNKID_SHIFT > 12
747# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
748#elif GMM_CHUNKID_SHIFT < 12
749# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
750 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
751#else
752# error "GMM_CHUNKID_SHIFT isn't defined or something."
753#endif
754*/
755
756/**
757 * Get the index of the page within the allocaiton chunk.
758 * @returns The page index.
759 * @param pPage Pointer to the physical guest page tracking structure.
760 */
761#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
762/* later:
763#if GMM_CHUNKID_SHIFT <= 12
764# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
765#else
766# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
767 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
768#endif
769*/
770
771
772/**
773 * Gets the page type.
774 * @returns The page type.
775 * @param pPage Pointer to the physical guest page tracking structure.
776 */
777#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
778
779/**
780 * Sets the page type.
781 * @param pPage Pointer to the physical guest page tracking structure.
782 * @param _enmType The new page type (PGMPAGETYPE).
783 */
784#ifdef VBOX_WITH_NEW_PHYS_CODE
785#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
786 do { (pPage)->u3Type = (_enmType); } while (0)
787#else
788#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
789 do { \
790 (pPage)->u3Type = (_enmType); \
791 if ((_enmType) == PGMPAGETYPE_ROM) \
792 (pPage)->HCPhysX |= MM_RAM_FLAGS_ROM; \
793 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
794 (pPage)->HCPhysX |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
795 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
796 (pPage)->HCPhysX |= MM_RAM_FLAGS_MMIO2; \
797 } while (0)
798#endif
799
800
801/**
802 * Checks if the page is 'reserved'.
803 * @returns true/false.
804 * @param pPage Pointer to the physical guest page tracking structure.
805 */
806#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_RESERVED) )
807
808/**
809 * Checks if the page is marked for MMIO.
810 * @returns true/false.
811 * @param pPage Pointer to the physical guest page tracking structure.
812 */
813#ifdef VBOX_WITH_NEW_PHYS_CODE
814# define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
815#else
816# define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhysX & MM_RAM_FLAGS_MMIO) )
817#endif
818
819/**
820 * Checks if the page is backed by the ZERO page.
821 * @returns true/false.
822 * @param pPage Pointer to the physical guest page tracking structure.
823 */
824#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
825
826/**
827 * Checks if the page is backed by a SHARED page.
828 * @returns true/false.
829 * @param pPage Pointer to the physical guest page tracking structure.
830 */
831#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
832
833
834/**
835 * Marks the paget as written to (for GMM change monitoring).
836 * @param pPage Pointer to the physical guest page tracking structure.
837 */
838#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
839
840/**
841 * Clears the written-to indicator.
842 * @param pPage Pointer to the physical guest page tracking structure.
843 */
844#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
845
846/**
847 * Checks if the page was marked as written-to.
848 * @returns true/false.
849 * @param pPage Pointer to the physical guest page tracking structure.
850 */
851#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
852
853
854/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
855 *
856 * @remarks The values are assigned in order of priority, so we can calculate
857 * the correct state for a page with different handlers installed.
858 * @{ */
859/** No handler installed. */
860#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
861/** Monitoring is temporarily disabled. */
862#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
863/** Write access is monitored. */
864#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
865/** All access is monitored. */
866#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
867/** @} */
868
869/**
870 * Gets the physical access handler state of a page.
871 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
872 * @param pPage Pointer to the physical guest page tracking structure.
873 */
874#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
875
876/**
877 * Sets the physical access handler state of a page.
878 * @param pPage Pointer to the physical guest page tracking structure.
879 * @param _uState The new state value.
880 */
881#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
882 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
883
884/**
885 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
886 * @returns true/false
887 * @param pPage Pointer to the physical guest page tracking structure.
888 */
889#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
890
891/**
892 * Checks if the page has any active physical access handlers.
893 * @returns true/false
894 * @param pPage Pointer to the physical guest page tracking structure.
895 */
896#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
897
898
899/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
900 *
901 * @remarks The values are assigned in order of priority, so we can calculate
902 * the correct state for a page with different handlers installed.
903 * @{ */
904/** No handler installed. */
905#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
906/* 1 is reserved so the lineup is identical with the physical ones. */
907/** Write access is monitored. */
908#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
909/** All access is monitored. */
910#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
911/** @} */
912
913/**
914 * Gets the virtual access handler state of a page.
915 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
916 * @param pPage Pointer to the physical guest page tracking structure.
917 */
918#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
919
920/**
921 * Sets the virtual access handler state of a page.
922 * @param pPage Pointer to the physical guest page tracking structure.
923 * @param _uState The new state value.
924 */
925#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
926 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
927
928/**
929 * Checks if the page has any virtual access handlers.
930 * @returns true/false
931 * @param pPage Pointer to the physical guest page tracking structure.
932 */
933#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
934
935/**
936 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
937 * virtual handlers.
938 * @returns true/false
939 * @param pPage Pointer to the physical guest page tracking structure.
940 */
941#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
942
943
944
945/**
946 * Checks if the page has any access handlers, including temporarily disabled ones.
947 * @returns true/false
948 * @param pPage Pointer to the physical guest page tracking structure.
949 */
950#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
951 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
952 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
953
954/**
955 * Checks if the page has any active access handlers.
956 * @returns true/false
957 * @param pPage Pointer to the physical guest page tracking structure.
958 */
959#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
960 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
961 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
962
963/**
964 * Checks if the page has any active access handlers catching all accesses.
965 * @returns true/false
966 * @param pPage Pointer to the physical guest page tracking structure.
967 */
968#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
969 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
970 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
971
972
973
974
975/** @def PGM_PAGE_GET_TRACKING
976 * Gets the packed shadow page pool tracking data associated with a guest page.
977 * @returns uint16_t containing the data.
978 * @param pPage Pointer to the physical guest page tracking structure.
979 */
980#define PGM_PAGE_GET_TRACKING(pPage) \
981 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
982
983/** @def PGM_PAGE_SET_TRACKING
984 * Sets the packed shadow page pool tracking data associated with a guest page.
985 * @param pPage Pointer to the physical guest page tracking structure.
986 * @param u16TrackingData The tracking data to store.
987 */
988#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
989 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
990
991/** @def PGM_PAGE_GET_TD_CREFS
992 * Gets the @a cRefs tracking data member.
993 * @returns cRefs.
994 * @param pPage Pointer to the physical guest page tracking structure.
995 */
996#define PGM_PAGE_GET_TD_CREFS(pPage) \
997 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
998
999#define PGM_PAGE_GET_TD_IDX(pPage) \
1000 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1001
1002/**
1003 * Ram range for GC Phys to HC Phys conversion.
1004 *
1005 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1006 * conversions too, but we'll let MM handle that for now.
1007 *
1008 * This structure is used by linked lists in both GC and HC.
1009 */
1010typedef struct PGMRAMRANGE
1011{
1012 /** Pointer to the next RAM range - for R3. */
1013 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1014 /** Pointer to the next RAM range - for R0. */
1015 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1016 /** Pointer to the next RAM range - for RC. */
1017 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1018 /** Pointer alignment. */
1019 RTRCPTR RCPtrAlignment;
1020 /** Start of the range. Page aligned. */
1021 RTGCPHYS GCPhys;
1022 /** Last address in the range (inclusive). Page aligned (-1). */
1023 RTGCPHYS GCPhysLast;
1024 /** Size of the range. (Page aligned of course). */
1025 RTGCPHYS cb;
1026 /** MM_RAM_* flags */
1027 uint32_t fFlags;
1028 uint32_t u32Alignment; /**< alignment. */
1029#ifndef VBOX_WITH_NEW_PHYS_CODE
1030 /** R3 virtual lookup ranges for chunks.
1031 * Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
1032 * @remarks This is occationally accessed from ring-0!! (not darwin) */
1033# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1034 R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1035# else
1036 R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
1037# endif
1038#endif
1039 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1040 R3PTRTYPE(void *) pvR3;
1041 /** The range description. */
1042 R3PTRTYPE(const char *) pszDesc;
1043
1044 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1045#ifdef VBOX_WITH_NEW_PHYS_CODE
1046 uint32_t au32Reserved[2];
1047#elif HC_ARCH_BITS == 32
1048 uint32_t au32Reserved[1];
1049#endif
1050
1051 /** Array of physical guest page tracking structures. */
1052 PGMPAGE aPages[1];
1053} PGMRAMRANGE;
1054/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1055typedef PGMRAMRANGE *PPGMRAMRANGE;
1056
1057/** Return hc ptr corresponding to the ram range and physical offset */
1058#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1059 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1060 : (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1061
1062/**
1063 * Per page tracking structure for ROM image.
1064 *
1065 * A ROM image may have a shadow page, in which case we may have
1066 * two pages backing it. This structure contains the PGMPAGE for
1067 * both while PGMRAMRANGE have a copy of the active one. It is
1068 * important that these aren't out of sync in any regard other
1069 * than page pool tracking data.
1070 */
1071typedef struct PGMROMPAGE
1072{
1073 /** The page structure for the virgin ROM page. */
1074 PGMPAGE Virgin;
1075 /** The page structure for the shadow RAM page. */
1076 PGMPAGE Shadow;
1077 /** The current protection setting. */
1078 PGMROMPROT enmProt;
1079 /** Pad the structure size to a multiple of 8. */
1080 uint32_t u32Padding;
1081} PGMROMPAGE;
1082/** Pointer to a ROM page tracking structure. */
1083typedef PGMROMPAGE *PPGMROMPAGE;
1084
1085
1086/**
1087 * A registered ROM image.
1088 *
1089 * This is needed to keep track of ROM image since they generally
1090 * intrude into a PGMRAMRANGE. It also keeps track of additional
1091 * info like the two page sets (read-only virgin and read-write shadow),
1092 * the current state of each page.
1093 *
1094 * Because access handlers cannot easily be executed in a different
1095 * context, the ROM ranges needs to be accessible and in all contexts.
1096 */
1097typedef struct PGMROMRANGE
1098{
1099 /** Pointer to the next range - R3. */
1100 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1101 /** Pointer to the next range - R0. */
1102 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1103 /** Pointer to the next range - RC. */
1104 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1105 /** Pointer alignment */
1106 RTRCPTR GCPtrAlignment;
1107 /** Address of the range. */
1108 RTGCPHYS GCPhys;
1109 /** Address of the last byte in the range. */
1110 RTGCPHYS GCPhysLast;
1111 /** Size of the range. */
1112 RTGCPHYS cb;
1113 /** The flags (PGMPHYS_ROM_FLAG_*). */
1114 uint32_t fFlags;
1115 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1116 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1117 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1118 * This is used for strictness checks. */
1119 R3PTRTYPE(const void *) pvOriginal;
1120 /** The ROM description. */
1121 R3PTRTYPE(const char *) pszDesc;
1122 /** The per page tracking structures. */
1123 PGMROMPAGE aPages[1];
1124} PGMROMRANGE;
1125/** Pointer to a ROM range. */
1126typedef PGMROMRANGE *PPGMROMRANGE;
1127
1128
1129/**
1130 * A registered MMIO2 (= Device RAM) range.
1131 *
1132 * There are a few reason why we need to keep track of these
1133 * registrations. One of them is the deregistration & cleanup
1134 * stuff, while another is that the PGMRAMRANGE associated with
1135 * such a region may have to be removed from the ram range list.
1136 *
1137 * Overlapping with a RAM range has to be 100% or none at all. The
1138 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1139 * meditation will be raised if a partial overlap or an overlap of
1140 * ROM pages is encountered. On an overlap we will free all the
1141 * existing RAM pages and put in the ram range pages instead.
1142 */
1143typedef struct PGMMMIO2RANGE
1144{
1145 /** The owner of the range. (a device) */
1146 PPDMDEVINSR3 pDevInsR3;
1147 /** Pointer to the ring-3 mapping of the allocation. */
1148 RTR3PTR pvR3;
1149 /** Pointer to the next range - R3. */
1150 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1151 /** Whether it's mapped or not. */
1152 bool fMapped;
1153 /** Whether it's overlapping or not. */
1154 bool fOverlapping;
1155 /** The PCI region number.
1156 * @remarks This ASSUMES that nobody will ever really need to have multiple
1157 * PCI devices with matching MMIO region numbers on a single device. */
1158 uint8_t iRegion;
1159 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1160 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1161 /** The associated RAM range. */
1162 PGMRAMRANGE RamRange;
1163} PGMMMIO2RANGE;
1164/** Pointer to a MMIO2 range. */
1165typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1166
1167
1168
1169
1170/**
1171 * PGMPhysRead/Write cache entry
1172 */
1173typedef struct PGMPHYSCACHEENTRY
1174{
1175 /** R3 pointer to physical page. */
1176 R3PTRTYPE(uint8_t *) pbR3;
1177 /** GC Physical address for cache entry */
1178 RTGCPHYS GCPhys;
1179#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1180 RTGCPHYS u32Padding0; /**< alignment padding. */
1181#endif
1182} PGMPHYSCACHEENTRY;
1183
1184/**
1185 * PGMPhysRead/Write cache to reduce REM memory access overhead
1186 */
1187typedef struct PGMPHYSCACHE
1188{
1189 /** Bitmap of valid cache entries */
1190 uint64_t aEntries;
1191 /** Cache entries */
1192 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1193} PGMPHYSCACHE;
1194
1195
1196/** Pointer to an allocation chunk ring-3 mapping. */
1197typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1198/** Pointer to an allocation chunk ring-3 mapping pointer. */
1199typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1200
1201/**
1202 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1203 *
1204 * The primary tree (Core) uses the chunk id as key.
1205 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1206 */
1207typedef struct PGMCHUNKR3MAP
1208{
1209 /** The key is the chunk id. */
1210 AVLU32NODECORE Core;
1211 /** The key is the ageing sequence number. */
1212 AVLLU32NODECORE AgeCore;
1213 /** The current age thingy. */
1214 uint32_t iAge;
1215 /** The current reference count. */
1216 uint32_t volatile cRefs;
1217 /** The current permanent reference count. */
1218 uint32_t volatile cPermRefs;
1219 /** The mapping address. */
1220 void *pv;
1221} PGMCHUNKR3MAP;
1222
1223/**
1224 * Allocation chunk ring-3 mapping TLB entry.
1225 */
1226typedef struct PGMCHUNKR3MAPTLBE
1227{
1228 /** The chunk id. */
1229 uint32_t volatile idChunk;
1230#if HC_ARCH_BITS == 64
1231 uint32_t u32Padding; /**< alignment padding. */
1232#endif
1233 /** The chunk map. */
1234#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1235 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1236#else
1237 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1238#endif
1239} PGMCHUNKR3MAPTLBE;
1240/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1241typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1242
1243/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1244 * @remark Must be a power of two value. */
1245#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1246
1247/**
1248 * Allocation chunk ring-3 mapping TLB.
1249 *
1250 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1251 * At first glance this might look kinda odd since AVL trees are
1252 * supposed to give the most optimial lookup times of all trees
1253 * due to their balancing. However, take a tree with 1023 nodes
1254 * in it, that's 10 levels, meaning that most searches has to go
1255 * down 9 levels before they find what they want. This isn't fast
1256 * compared to a TLB hit. There is the factor of cache misses,
1257 * and of course the problem with trees and branch prediction.
1258 * This is why we use TLBs in front of most of the trees.
1259 *
1260 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1261 * difficult when we switch to the new inlined AVL trees (from kStuff).
1262 */
1263typedef struct PGMCHUNKR3MAPTLB
1264{
1265 /** The TLB entries. */
1266 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1267} PGMCHUNKR3MAPTLB;
1268
1269/**
1270 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1271 * @returns Chunk TLB index.
1272 * @param idChunk The Chunk ID.
1273 */
1274#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1275
1276
1277/**
1278 * Ring-3 guest page mapping TLB entry.
1279 * @remarks used in ring-0 as well at the moment.
1280 */
1281typedef struct PGMPAGER3MAPTLBE
1282{
1283 /** Address of the page. */
1284 RTGCPHYS volatile GCPhys;
1285 /** The guest page. */
1286#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1287 R3PTRTYPE(PPGMPAGE) volatile pPage;
1288#else
1289 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1290#endif
1291 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1292#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1293 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1294#else
1295 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1296#endif
1297 /** The address */
1298#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1299 R3PTRTYPE(void *) volatile pv;
1300#else
1301 R3R0PTRTYPE(void *) volatile pv;
1302#endif
1303#if HC_ARCH_BITS == 32
1304 uint32_t u32Padding; /**< alignment padding. */
1305#endif
1306} PGMPAGER3MAPTLBE;
1307/** Pointer to an entry in the HC physical TLB. */
1308typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1309
1310
1311/** The number of entries in the ring-3 guest page mapping TLB.
1312 * @remarks The value must be a power of two. */
1313#define PGM_PAGER3MAPTLB_ENTRIES 64
1314
1315/**
1316 * Ring-3 guest page mapping TLB.
1317 * @remarks used in ring-0 as well at the moment.
1318 */
1319typedef struct PGMPAGER3MAPTLB
1320{
1321 /** The TLB entries. */
1322 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1323} PGMPAGER3MAPTLB;
1324/** Pointer to the ring-3 guest page mapping TLB. */
1325typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1326
1327/**
1328 * Calculates the index of the TLB entry for the specified guest page.
1329 * @returns Physical TLB index.
1330 * @param GCPhys The guest physical address.
1331 */
1332#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1333
1334
1335/**
1336 * Mapping cache usage set entry.
1337 *
1338 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1339 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1340 * cache. If it's extended to include ring-3, well, then something will
1341 * have be changed here...
1342 */
1343typedef struct PGMMAPSETENTRY
1344{
1345 /** The mapping cache index. */
1346 uint16_t iPage;
1347 /** The number of references.
1348 * The max is UINT16_MAX - 1. */
1349 uint16_t cRefs;
1350 /** Pointer to the page. */
1351 RTR0PTR pvPage;
1352 /** The physical address for this entry. */
1353 RTHCPHYS HCPhys;
1354} PGMMAPSETENTRY;
1355/** Pointer to a mapping cache usage set entry. */
1356typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1357
1358/**
1359 * Mapping cache usage set.
1360 *
1361 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1362 * done during exits / traps. The set is
1363 */
1364typedef struct PGMMAPSET
1365{
1366 /** The number of occupied entries.
1367 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1368 * dynamic mappings. */
1369 uint32_t cEntries;
1370 /** The start of the current subset.
1371 * This is UINT32_MAX if no subset is currently open. */
1372 uint32_t iSubset;
1373 /** The index of the current CPU, only valid if the set is open. */
1374 int32_t iCpu;
1375 /** The entries. */
1376 PGMMAPSETENTRY aEntries[64];
1377 /** HCPhys -> iEntry fast lookup table.
1378 * Use PGMMAPSET_HASH for hashing.
1379 * The entries may or may not be valid, check against cEntries. */
1380 uint8_t aiHashTable[128];
1381} PGMMAPSET;
1382/** Pointer to the mapping cache set. */
1383typedef PGMMAPSET *PPGMMAPSET;
1384
1385/** PGMMAPSET::cEntries value for a closed set. */
1386#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1387
1388/** Hash function for aiHashTable. */
1389#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1390
1391/** The max fill size (strict builds). */
1392#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1393
1394
1395/** @name Context neutrual page mapper TLB.
1396 *
1397 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1398 * code is writting in a kind of context neutrual way. Time will show whether
1399 * this actually makes sense or not...
1400 *
1401 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1402 * context ends up using a global mapping cache on some platforms
1403 * (darwin).
1404 *
1405 * @{ */
1406/** @typedef PPGMPAGEMAPTLB
1407 * The page mapper TLB pointer type for the current context. */
1408/** @typedef PPGMPAGEMAPTLB
1409 * The page mapper TLB entry pointer type for the current context. */
1410/** @typedef PPGMPAGEMAPTLB
1411 * The page mapper TLB entry pointer pointer type for the current context. */
1412/** @def PGM_PAGEMAPTLB_ENTRIES
1413 * The number of TLB entries in the page mapper TLB for the current context. */
1414/** @def PGM_PAGEMAPTLB_IDX
1415 * Calculate the TLB index for a guest physical address.
1416 * @returns The TLB index.
1417 * @param GCPhys The guest physical address. */
1418/** @typedef PPGMPAGEMAP
1419 * Pointer to a page mapper unit for current context. */
1420/** @typedef PPPGMPAGEMAP
1421 * Pointer to a page mapper unit pointer for current context. */
1422#ifdef IN_RC
1423// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1424// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1425// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1426# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1427# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1428 typedef void * PPGMPAGEMAP;
1429 typedef void ** PPPGMPAGEMAP;
1430//#elif IN_RING0
1431// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1432// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1433// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1434//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1435//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1436// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1437// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1438#else
1439 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1440 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1441 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1442# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1443# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1444 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1445 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1446#endif
1447/** @} */
1448
1449
1450/** @name PGM Pool Indexes.
1451 * Aka. the unique shadow page identifier.
1452 * @{ */
1453/** NIL page pool IDX. */
1454#define NIL_PGMPOOL_IDX 0
1455/** The first normal index. */
1456#define PGMPOOL_IDX_FIRST_SPECIAL 1
1457#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1458/** Page directory (32-bit root). */
1459#define PGMPOOL_IDX_PD 1
1460/** Page Directory Pointer Table (PAE root). */
1461#define PGMPOOL_IDX_PDPT 2
1462/** AMD64 CR3 level index.*/
1463#define PGMPOOL_IDX_AMD64_CR3 3
1464/** Nested paging root.*/
1465#define PGMPOOL_IDX_NESTED_ROOT 4
1466/** The first normal index. */
1467#define PGMPOOL_IDX_FIRST 5
1468#else
1469/** Page directory (32-bit root). */
1470#define PGMPOOL_IDX_PD 1
1471/** The extended PAE page directory (2048 entries, works as root currently). */
1472#define PGMPOOL_IDX_PAE_PD 2
1473/** PAE Page Directory Table 0. */
1474#define PGMPOOL_IDX_PAE_PD_0 3
1475/** PAE Page Directory Table 1. */
1476#define PGMPOOL_IDX_PAE_PD_1 4
1477/** PAE Page Directory Table 2. */
1478#define PGMPOOL_IDX_PAE_PD_2 5
1479/** PAE Page Directory Table 3. */
1480#define PGMPOOL_IDX_PAE_PD_3 6
1481/** Page Directory Pointer Table (PAE root, not currently used). */
1482#define PGMPOOL_IDX_PDPT 7
1483/** AMD64 CR3 level index.*/
1484#define PGMPOOL_IDX_AMD64_CR3 8
1485/** Nested paging root.*/
1486#define PGMPOOL_IDX_NESTED_ROOT 9
1487/** The first normal index. */
1488#define PGMPOOL_IDX_FIRST 10
1489#endif
1490/** The last valid index. (inclusive, 14 bits) */
1491#define PGMPOOL_IDX_LAST 0x3fff
1492/** @} */
1493
1494/** The NIL index for the parent chain. */
1495#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1496
1497/**
1498 * Node in the chain linking a shadowed page to it's parent (user).
1499 */
1500#pragma pack(1)
1501typedef struct PGMPOOLUSER
1502{
1503 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1504 uint16_t iNext;
1505 /** The user page index. */
1506 uint16_t iUser;
1507 /** Index into the user table. */
1508 uint32_t iUserTable;
1509} PGMPOOLUSER, *PPGMPOOLUSER;
1510typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1511#pragma pack()
1512
1513
1514/** The NIL index for the phys ext chain. */
1515#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1516
1517/**
1518 * Node in the chain of physical cross reference extents.
1519 * @todo Calling this an 'extent' is not quite right, find a better name.
1520 */
1521#pragma pack(1)
1522typedef struct PGMPOOLPHYSEXT
1523{
1524 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1525 uint16_t iNext;
1526 /** The user page index. */
1527 uint16_t aidx[3];
1528} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1529typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1530#pragma pack()
1531
1532
1533/**
1534 * The kind of page that's being shadowed.
1535 */
1536typedef enum PGMPOOLKIND
1537{
1538 /** The virtual invalid 0 entry. */
1539 PGMPOOLKIND_INVALID = 0,
1540 /** The entry is free (=unused). */
1541 PGMPOOLKIND_FREE,
1542
1543 /** Shw: 32-bit page table; Gst: no paging */
1544 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1545 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1546 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1547 /** Shw: 32-bit page table; Gst: 4MB page. */
1548 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1549 /** Shw: PAE page table; Gst: no paging */
1550 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1551 /** Shw: PAE page table; Gst: 32-bit page table. */
1552 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1553 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1554 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1555 /** Shw: PAE page table; Gst: PAE page table. */
1556 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1557 /** Shw: PAE page table; Gst: 2MB page. */
1558 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1559
1560 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1561 PGMPOOLKIND_32BIT_PD,
1562 /** Shw: 32-bit page directory. Gst: no paging. */
1563 PGMPOOLKIND_32BIT_PD_PHYS,
1564 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1565 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1566 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1567 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1568 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1569 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1570 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1571 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1572 /** Shw: PAE page directory; Gst: PAE page directory. */
1573 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1574 /** Shw: PAE page directory; Gst: no paging. */
1575 PGMPOOLKIND_PAE_PD_PHYS,
1576
1577 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1578 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1579 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1580 PGMPOOLKIND_PAE_PDPT,
1581 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1582 PGMPOOLKIND_PAE_PDPT_PHYS,
1583
1584 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1585 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1586 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1587 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1588 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1589 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1590 /** Shw: 64-bit page directory table; Gst: no paging */
1591 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1592
1593 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1594 PGMPOOLKIND_64BIT_PML4,
1595
1596 /** Shw: EPT page directory pointer table; Gst: no paging */
1597 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1598 /** Shw: EPT page directory table; Gst: no paging */
1599 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1600 /** Shw: EPT page table; Gst: no paging */
1601 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1602
1603#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1604 /** Shw: Root 32-bit page directory. */
1605 PGMPOOLKIND_ROOT_32BIT_PD,
1606 /** Shw: Root PAE page directory */
1607 PGMPOOLKIND_ROOT_PAE_PD,
1608 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1609 PGMPOOLKIND_ROOT_PDPT,
1610#endif
1611 /** Shw: Root Nested paging table. */
1612 PGMPOOLKIND_ROOT_NESTED,
1613
1614 /** The last valid entry. */
1615 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1616} PGMPOOLKIND;
1617
1618
1619/**
1620 * The tracking data for a page in the pool.
1621 */
1622typedef struct PGMPOOLPAGE
1623{
1624 /** AVL node code with the (R3) physical address of this page. */
1625 AVLOHCPHYSNODECORE Core;
1626 /** Pointer to the R3 mapping of the page. */
1627#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1628 R3PTRTYPE(void *) pvPageR3;
1629#else
1630 R3R0PTRTYPE(void *) pvPageR3;
1631#endif
1632 /** The guest physical address. */
1633#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1634 uint32_t Alignment0;
1635#endif
1636 RTGCPHYS GCPhys;
1637 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1638 uint8_t enmKind;
1639 uint8_t bPadding;
1640 /** The index of this page. */
1641 uint16_t idx;
1642 /** The next entry in the list this page currently resides in.
1643 * It's either in the free list or in the GCPhys hash. */
1644 uint16_t iNext;
1645#ifdef PGMPOOL_WITH_USER_TRACKING
1646 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1647 uint16_t iUserHead;
1648 /** The number of present entries. */
1649 uint16_t cPresent;
1650 /** The first entry in the table which is present. */
1651 uint16_t iFirstPresent;
1652#endif
1653#ifdef PGMPOOL_WITH_MONITORING
1654 /** The number of modifications to the monitored page. */
1655 uint16_t cModifications;
1656 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1657 uint16_t iModifiedNext;
1658 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1659 uint16_t iModifiedPrev;
1660 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1661 uint16_t iMonitoredNext;
1662 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1663 uint16_t iMonitoredPrev;
1664#endif
1665#ifdef PGMPOOL_WITH_CACHE
1666 /** The next page in the age list. */
1667 uint16_t iAgeNext;
1668 /** The previous page in the age list. */
1669 uint16_t iAgePrev;
1670#endif /* PGMPOOL_WITH_CACHE */
1671 /** Used to indicate that the page is zeroed. */
1672 bool fZeroed;
1673 /** Used to indicate that a PT has non-global entries. */
1674 bool fSeenNonGlobal;
1675 /** Used to indicate that we're monitoring writes to the guest page. */
1676 bool fMonitored;
1677 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1678 * (All pages are in the age list.) */
1679 bool fCached;
1680 /** This is used by the R3 access handlers when invoked by an async thread.
1681 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1682 bool volatile fReusedFlushPending;
1683#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1684 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1685 bool fLocked;
1686#else
1687 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1688 * In these cases the access handler acts differently and will check
1689 * for mapping conflicts like the normal CR3 handler.
1690 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1691 * replaced by a list of pages which share access handler.
1692 */
1693 bool fCR3Mix;
1694#endif
1695} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1696
1697
1698#ifdef PGMPOOL_WITH_CACHE
1699/** The hash table size. */
1700# define PGMPOOL_HASH_SIZE 0x40
1701/** The hash function. */
1702# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1703#endif
1704
1705
1706/**
1707 * The shadow page pool instance data.
1708 *
1709 * It's all one big allocation made at init time, except for the
1710 * pages that is. The user nodes follows immediatly after the
1711 * page structures.
1712 */
1713typedef struct PGMPOOL
1714{
1715 /** The VM handle - R3 Ptr. */
1716 PVMR3 pVMR3;
1717 /** The VM handle - R0 Ptr. */
1718 PVMR0 pVMR0;
1719 /** The VM handle - RC Ptr. */
1720 PVMRC pVMRC;
1721 /** The max pool size. This includes the special IDs. */
1722 uint16_t cMaxPages;
1723 /** The current pool size. */
1724 uint16_t cCurPages;
1725 /** The head of the free page list. */
1726 uint16_t iFreeHead;
1727 /* Padding. */
1728 uint16_t u16Padding;
1729#ifdef PGMPOOL_WITH_USER_TRACKING
1730 /** Head of the chain of free user nodes. */
1731 uint16_t iUserFreeHead;
1732 /** The number of user nodes we've allocated. */
1733 uint16_t cMaxUsers;
1734 /** The number of present page table entries in the entire pool. */
1735 uint32_t cPresent;
1736 /** Pointer to the array of user nodes - RC pointer. */
1737 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1738 /** Pointer to the array of user nodes - R3 pointer. */
1739 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1740 /** Pointer to the array of user nodes - R0 pointer. */
1741 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1742#endif /* PGMPOOL_WITH_USER_TRACKING */
1743#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1744 /** Head of the chain of free phys ext nodes. */
1745 uint16_t iPhysExtFreeHead;
1746 /** The number of user nodes we've allocated. */
1747 uint16_t cMaxPhysExts;
1748 /** Pointer to the array of physical xref extent - RC pointer. */
1749 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1750 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1751 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1752 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1753 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1754#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1755#ifdef PGMPOOL_WITH_CACHE
1756 /** Hash table for GCPhys addresses. */
1757 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1758 /** The head of the age list. */
1759 uint16_t iAgeHead;
1760 /** The tail of the age list. */
1761 uint16_t iAgeTail;
1762 /** Set if the cache is enabled. */
1763 bool fCacheEnabled;
1764#endif /* PGMPOOL_WITH_CACHE */
1765#ifdef PGMPOOL_WITH_MONITORING
1766 /** Head of the list of modified pages. */
1767 uint16_t iModifiedHead;
1768 /** The current number of modified pages. */
1769 uint16_t cModifiedPages;
1770 /** Access handler, RC. */
1771 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1772 /** Access handler, R0. */
1773 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1774 /** Access handler, R3. */
1775 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1776 /** The access handler description (HC ptr). */
1777 R3PTRTYPE(const char *) pszAccessHandler;
1778#endif /* PGMPOOL_WITH_MONITORING */
1779 /** The number of pages currently in use. */
1780 uint16_t cUsedPages;
1781#ifdef VBOX_WITH_STATISTICS
1782 /** The high wather mark for cUsedPages. */
1783 uint16_t cUsedPagesHigh;
1784 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1785 /** Profiling pgmPoolAlloc(). */
1786 STAMPROFILEADV StatAlloc;
1787 /** Profiling pgmPoolClearAll(). */
1788 STAMPROFILE StatClearAll;
1789 /** Profiling pgmPoolFlushAllInt(). */
1790 STAMPROFILE StatFlushAllInt;
1791 /** Profiling pgmPoolFlushPage(). */
1792 STAMPROFILE StatFlushPage;
1793 /** Profiling pgmPoolFree(). */
1794 STAMPROFILE StatFree;
1795 /** Profiling time spent zeroing pages. */
1796 STAMPROFILE StatZeroPage;
1797# ifdef PGMPOOL_WITH_USER_TRACKING
1798 /** Profiling of pgmPoolTrackDeref. */
1799 STAMPROFILE StatTrackDeref;
1800 /** Profiling pgmTrackFlushGCPhysPT. */
1801 STAMPROFILE StatTrackFlushGCPhysPT;
1802 /** Profiling pgmTrackFlushGCPhysPTs. */
1803 STAMPROFILE StatTrackFlushGCPhysPTs;
1804 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1805 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1806 /** Number of times we've been out of user records. */
1807 STAMCOUNTER StatTrackFreeUpOneUser;
1808# endif
1809# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1810 /** Profiling deref activity related tracking GC physical pages. */
1811 STAMPROFILE StatTrackDerefGCPhys;
1812 /** Number of linear searches for a HCPhys in the ram ranges. */
1813 STAMCOUNTER StatTrackLinearRamSearches;
1814 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1815 STAMCOUNTER StamTrackPhysExtAllocFailures;
1816# endif
1817# ifdef PGMPOOL_WITH_MONITORING
1818 /** Profiling the RC/R0 access handler. */
1819 STAMPROFILE StatMonitorRZ;
1820 /** Times we've failed interpreting the instruction. */
1821 STAMCOUNTER StatMonitorRZEmulateInstr;
1822 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1823 STAMPROFILE StatMonitorRZFlushPage;
1824 /** Times we've detected fork(). */
1825 STAMCOUNTER StatMonitorRZFork;
1826 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1827 STAMPROFILE StatMonitorRZHandled;
1828 /** Times we've failed interpreting a patch code instruction. */
1829 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1830 /** Times we've failed interpreting a patch code instruction during flushing. */
1831 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1832 /** The number of times we've seen rep prefixes we can't handle. */
1833 STAMCOUNTER StatMonitorRZRepPrefix;
1834 /** Profiling the REP STOSD cases we've handled. */
1835 STAMPROFILE StatMonitorRZRepStosd;
1836
1837 /** Profiling the R3 access handler. */
1838 STAMPROFILE StatMonitorR3;
1839 /** Times we've failed interpreting the instruction. */
1840 STAMCOUNTER StatMonitorR3EmulateInstr;
1841 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1842 STAMPROFILE StatMonitorR3FlushPage;
1843 /** Times we've detected fork(). */
1844 STAMCOUNTER StatMonitorR3Fork;
1845 /** Profiling the R3 access we've handled (except REP STOSD). */
1846 STAMPROFILE StatMonitorR3Handled;
1847 /** The number of times we've seen rep prefixes we can't handle. */
1848 STAMCOUNTER StatMonitorR3RepPrefix;
1849 /** Profiling the REP STOSD cases we've handled. */
1850 STAMPROFILE StatMonitorR3RepStosd;
1851 /** The number of times we're called in an async thread an need to flush. */
1852 STAMCOUNTER StatMonitorR3Async;
1853 /** The high wather mark for cModifiedPages. */
1854 uint16_t cModifiedPagesHigh;
1855 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1856# endif
1857# ifdef PGMPOOL_WITH_CACHE
1858 /** The number of cache hits. */
1859 STAMCOUNTER StatCacheHits;
1860 /** The number of cache misses. */
1861 STAMCOUNTER StatCacheMisses;
1862 /** The number of times we've got a conflict of 'kind' in the cache. */
1863 STAMCOUNTER StatCacheKindMismatches;
1864 /** Number of times we've been out of pages. */
1865 STAMCOUNTER StatCacheFreeUpOne;
1866 /** The number of cacheable allocations. */
1867 STAMCOUNTER StatCacheCacheable;
1868 /** The number of uncacheable allocations. */
1869 STAMCOUNTER StatCacheUncacheable;
1870# endif
1871#elif HC_ARCH_BITS == 64
1872 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1873#endif
1874 /** The AVL tree for looking up a page by its HC physical address. */
1875 AVLOHCPHYSTREE HCPhysTree;
1876 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1877 /** Array of pages. (cMaxPages in length)
1878 * The Id is the index into thist array.
1879 */
1880 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1881} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1882
1883
1884/** @def PGMPOOL_PAGE_2_PTR
1885 * Maps a pool page pool into the current context.
1886 *
1887 * @returns VBox status code.
1888 * @param pVM The VM handle.
1889 * @param pPage The pool page.
1890 *
1891 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1892 * small page window employeed by that function. Be careful.
1893 * @remark There is no need to assert on the result.
1894 */
1895#if defined(IN_RC)
1896# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1897#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1898# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1899#elif defined(VBOX_STRICT)
1900# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1901DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1902{
1903 Assert(pPage->pvPageR3);
1904 return pPage->pvPageR3;
1905}
1906#else
1907# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1908#endif
1909
1910/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1911 * Maps a pool page pool into the current context.
1912 *
1913 * @returns VBox status code.
1914 * @param pPGM Pointer to the PGM instance data.
1915 * @param pPage The pool page.
1916 *
1917 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1918 * small page window employeed by that function. Be careful.
1919 * @remark There is no need to assert on the result.
1920 */
1921#if defined(IN_RC)
1922# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1923#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1924# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage))
1925#else
1926# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1927#endif
1928
1929
1930/** @name Per guest page tracking data.
1931 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1932 * is to use more bits for it and split it up later on. But for now we'll play
1933 * safe and change as little as possible.
1934 *
1935 * The 16-bit word has two parts:
1936 *
1937 * The first 14-bit forms the @a idx field. It is either the index of a page in
1938 * the shadow page pool, or and index into the extent list.
1939 *
1940 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1941 * shadow page pool references to the page. If cRefs equals
1942 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1943 * (misnomer) table and not the shadow page pool.
1944 *
1945 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1946 * the 16-bit word.
1947 *
1948 * @{ */
1949/** The shift count for getting to the cRefs part. */
1950#define PGMPOOL_TD_CREFS_SHIFT 14
1951/** The mask applied after shifting the tracking data down by
1952 * PGMPOOL_TD_CREFS_SHIFT. */
1953#define PGMPOOL_TD_CREFS_MASK 0x3
1954/** The cRef value used to indiciate that the idx is the head of a
1955 * physical cross reference list. */
1956#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1957/** The shift used to get idx. */
1958#define PGMPOOL_TD_IDX_SHIFT 0
1959/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1960#define PGMPOOL_TD_IDX_MASK 0x3fff
1961/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1962 * simply too many mappings of this page. */
1963#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1964
1965/** @def PGMPOOL_TD_MAKE
1966 * Makes a 16-bit tracking data word.
1967 *
1968 * @returns tracking data.
1969 * @param cRefs The @a cRefs field. Must be within bounds!
1970 * @param idx The @a idx field. Must also be within bounds! */
1971#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
1972
1973/** @def PGMPOOL_TD_GET_CREFS
1974 * Get the @a cRefs field from a tracking data word.
1975 *
1976 * @returns The @a cRefs field
1977 * @param u16 The tracking data word. */
1978#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
1979
1980/** @def PGMPOOL_TD_GET_IDX
1981 * Get the @a idx field from a tracking data word.
1982 *
1983 * @returns The @a idx field
1984 * @param u16 The tracking data word. */
1985#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
1986/** @} */
1987
1988
1989/**
1990 * Trees are using self relative offsets as pointers.
1991 * So, all its data, including the root pointer, must be in the heap for HC and GC
1992 * to have the same layout.
1993 */
1994typedef struct PGMTREES
1995{
1996 /** Physical access handlers (AVL range+offsetptr tree). */
1997 AVLROGCPHYSTREE PhysHandlers;
1998 /** Virtual access handlers (AVL range + GC ptr tree). */
1999 AVLROGCPTRTREE VirtHandlers;
2000 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2001 AVLROGCPHYSTREE PhysToVirtHandlers;
2002 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2003 AVLROGCPTRTREE HyperVirtHandlers;
2004} PGMTREES;
2005/** Pointer to PGM trees. */
2006typedef PGMTREES *PPGMTREES;
2007
2008
2009/** @name Paging mode macros
2010 * @{ */
2011#ifdef IN_RC
2012# define PGM_CTX(a,b) a##RC##b
2013# define PGM_CTX_STR(a,b) a "GC" b
2014# define PGM_CTX_DECL(type) VMMRCDECL(type)
2015#else
2016# ifdef IN_RING3
2017# define PGM_CTX(a,b) a##R3##b
2018# define PGM_CTX_STR(a,b) a "R3" b
2019# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2020# else
2021# define PGM_CTX(a,b) a##R0##b
2022# define PGM_CTX_STR(a,b) a "R0" b
2023# define PGM_CTX_DECL(type) VMMDECL(type)
2024# endif
2025#endif
2026
2027#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2028#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2029#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2030#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2031#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2032#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2033#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2034#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2035#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2036#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2037#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2038#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2039#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2040#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2041#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2042#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
2043#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2044
2045#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2046#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2047#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2048#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2049#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2050#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2051#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2052#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2053#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2054#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2055#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2056#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2057#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2058#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2059#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2060#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2061#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
2062
2063/* Shw_Gst */
2064#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2065#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2066#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2067#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2068#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2069#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2070#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2071#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2072#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2073#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2074#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2075#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2076#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2077#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2078#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2079#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2080#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2081#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2082#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2083
2084#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2085#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2086#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2087#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2088#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2089#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2090#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2091#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2092#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2093#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2094#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2095#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2096#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2097#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2098#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2099#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2100#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2101#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2102#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2103#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2104#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2105#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2106#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2107#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2108#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2109#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2110#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2111#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2112#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2113#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2114#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2115#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2116#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2117#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2118#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2119#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2120#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2121
2122#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2123#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2124/** @} */
2125
2126/**
2127 * Data for each paging mode.
2128 */
2129typedef struct PGMMODEDATA
2130{
2131 /** The guest mode type. */
2132 uint32_t uGstType;
2133 /** The shadow mode type. */
2134 uint32_t uShwType;
2135
2136 /** @name Function pointers for Shadow paging.
2137 * @{
2138 */
2139 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2140 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2141 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2142 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2143
2144 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2145 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2146
2147 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2148 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2149 /** @} */
2150
2151 /** @name Function pointers for Guest paging.
2152 * @{
2153 */
2154 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2155 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2156 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2157 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2158 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2159#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2160 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2161 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2162#endif
2163#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2164 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2165 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2166 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2167 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2168#endif
2169 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2170 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2171 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2172#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2173 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2174 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2175#endif
2176#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2177 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2178 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2179#endif
2180 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2181 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2182 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2183#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2184 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2185 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2186#endif
2187#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2188 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2189 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2190#endif
2191 /** @} */
2192
2193 /** @name Function pointers for Both Shadow and Guest paging.
2194 * @{
2195 */
2196 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2197 /* no pfnR3BthTrap0eHandler */
2198 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2199 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2200 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2201 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2202 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2203#ifdef VBOX_STRICT
2204 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2205#endif
2206 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2207 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2208
2209 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2210 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2211 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2212 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2213 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2214 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2215#ifdef VBOX_STRICT
2216 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2217#endif
2218 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2219 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2220
2221 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2222 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2223 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2224 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2225 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2226 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2227#ifdef VBOX_STRICT
2228 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2229#endif
2230 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2231 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2232 /** @} */
2233} PGMMODEDATA, *PPGMMODEDATA;
2234
2235
2236
2237/**
2238 * Converts a PGM pointer into a VM pointer.
2239 * @returns Pointer to the VM structure the PGM is part of.
2240 * @param pPGM Pointer to PGM instance data.
2241 */
2242#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2243
2244/**
2245 * PGM Data (part of VM)
2246 */
2247typedef struct PGM
2248{
2249 /** Offset to the VM structure. */
2250 RTINT offVM;
2251 /** Offset of the PGMCPU structure relative to VMCPU. */
2252 int32_t offVCpu;
2253 /** @cfgm{PGM/RamPreAlloc, bool, false}
2254 * Whether to preallocate all the guest RAM or not. */
2255 bool fRamPreAlloc;
2256 /** Alignment padding. */
2257 bool afAlignment0[3];
2258
2259
2260 /*
2261 * This will be redefined at least two more times before we're done, I'm sure.
2262 * The current code is only to get on with the coding.
2263 * - 2004-06-10: initial version, bird.
2264 * - 2004-07-02: 1st time, bird.
2265 * - 2004-10-18: 2nd time, bird.
2266 * - 2005-07-xx: 3rd time, bird.
2267 */
2268
2269 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2270 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2271 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2272 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2273
2274 /** The host paging mode. (This is what SUPLib reports.) */
2275 SUPPAGINGMODE enmHostMode;
2276 /** The shadow paging mode. */
2277 PGMMODE enmShadowMode;
2278 /** The guest paging mode. */
2279 PGMMODE enmGuestMode;
2280
2281 /** The current physical address representing in the guest CR3 register. */
2282 RTGCPHYS GCPhysCR3;
2283 /** Pointer to the 5 page CR3 content mapping.
2284 * The first page is always the CR3 (in some form) while the 4 other pages
2285 * are used of the PDs in PAE mode. */
2286 RTGCPTR GCPtrCR3Mapping;
2287#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2288 uint32_t u32Alignment;
2289#endif
2290#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2291 /** The physical address of the currently monitored guest CR3 page.
2292 * When this value is NIL_RTGCPHYS no page is being monitored. */
2293 RTGCPHYS GCPhysGstCR3Monitored;
2294#endif
2295 /** @name 32-bit Guest Paging.
2296 * @{ */
2297 /** The guest's page directory, R3 pointer. */
2298 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2299#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2300 /** The guest's page directory, R0 pointer. */
2301 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2302#endif
2303 /** The guest's page directory, static RC mapping. */
2304 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2305 /** @} */
2306
2307 /** @name PAE Guest Paging.
2308 * @{ */
2309 /** The guest's page directory pointer table, static RC mapping. */
2310 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2311 /** The guest's page directory pointer table, R3 pointer. */
2312 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2313#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2314 /** The guest's page directory pointer table, R0 pointer. */
2315 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2316#endif
2317
2318 /** The guest's page directories, R3 pointers.
2319 * These are individual pointers and don't have to be adjecent.
2320 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2321 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2322 /** The guest's page directories, R0 pointers.
2323 * Same restrictions as apGstPaePDsR3. */
2324#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2325 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2326#endif
2327 /** The guest's page directories, static GC mapping.
2328 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2329 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2330 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2331 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2332 RTGCPHYS aGCPhysGstPaePDs[4];
2333 /** The physical addresses of the monitored guest page directories (PAE). */
2334 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2335 /** @} */
2336
2337 /** @name AMD64 Guest Paging.
2338 * @{ */
2339 /** The guest's page directory pointer table, R3 pointer. */
2340 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2341#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2342 /** The guest's page directory pointer table, R0 pointer. */
2343 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2344#endif
2345 /** @} */
2346
2347 /** @name Shadow paging
2348 * @{ */
2349 /** The root page table - R3 Ptr. */
2350 R3PTRTYPE(void *) pShwRootR3;
2351# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2352 /** The root page table - R0 Ptr. */
2353 R0PTRTYPE(void *) pShwRootR0;
2354# endif
2355 /** The root page table - RC Ptr. */
2356 RCPTRTYPE(void *) pShwRootRC;
2357# if HC_ARCH_BITS == 64
2358 uint32_t u32Padding1; /**< alignment padding. */
2359# endif
2360 /** The Physical Address (HC) of the current active shadow CR3. */
2361 RTHCPHYS HCPhysShwCR3;
2362 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2363 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2364 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2365 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2366 /** Pointer to the page of the current active CR3 - RC Ptr. */
2367 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2368 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2369 uint32_t iShwUser;
2370 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2371 uint32_t iShwUserTable;
2372# if HC_ARCH_BITS == 64
2373 RTRCPTR alignment6; /**< structure size alignment. */
2374# endif
2375 /** @} */
2376#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2377 /** @name 32-bit Shadow Paging
2378 * @{ */
2379 /** The 32-Bit PD - R3 Ptr. */
2380 R3PTRTYPE(PX86PD) pShw32BitPdR3;
2381 /** The 32-Bit PD - R0 Ptr. */
2382 R0PTRTYPE(PX86PD) pShw32BitPdR0;
2383 /** The 32-Bit PD - RC Ptr. */
2384 RCPTRTYPE(PX86PD) pShw32BitPdRC;
2385# if HC_ARCH_BITS == 64
2386 uint32_t u32Padding10; /**< alignment padding. */
2387# endif
2388 /** The Physical Address (HC) of the 32-Bit PD. */
2389 RTHCPHYS HCPhysShw32BitPD;
2390 /** @} */
2391
2392 /** @name PAE Shadow Paging
2393 * @{ */
2394 /** The four PDs for the low 4GB - R3 Ptr.
2395 * Even though these are 4 pointers, what they point at is a single table.
2396 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2397 R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2398# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2399 /** The four PDs for the low 4GB - R0 Ptr.
2400 * Same kind of mapping as apHCPaePDs. */
2401 R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2402# endif
2403 /** The four PDs for the low 4GB - RC Ptr.
2404 * Same kind of mapping as apHCPaePDs. */
2405 RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2406 /** The Physical Address (HC) of the four PDs for the low 4GB.
2407 * These are *NOT* 4 contiguous pages. */
2408 RTHCPHYS aHCPhysPaePDs[4];
2409 /** The Physical Address (HC) of the PAE PDPT. */
2410 RTHCPHYS HCPhysShwPaePdpt;
2411 /** The PAE PDPT - R3 Ptr. */
2412 R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2413 /** The PAE PDPT - R0 Ptr. */
2414 R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2415 /** The PAE PDPT - RC Ptr. */
2416 RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2417 /** @} */
2418# if HC_ARCH_BITS == 64
2419 RTRCPTR alignment5; /**< structure size alignment. */
2420# endif
2421#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
2422 /** @name Nested Shadow Paging
2423 * @{ */
2424 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2425 RTR3PTR pShwNestedRootR3;
2426# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2427 /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2428 RTR0PTR pShwNestedRootR0;
2429# endif
2430 /** The Physical Address (HC) of the nested paging root. */
2431 RTHCPHYS HCPhysShwNestedRoot;
2432 /** @} */
2433
2434 /** @name Function pointers for Shadow paging.
2435 * @{
2436 */
2437 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2438 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2439 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2440 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2441
2442 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2443 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2444
2445 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2446 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2447
2448 /** @} */
2449
2450 /** @name Function pointers for Guest paging.
2451 * @{
2452 */
2453 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2454 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2455 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2456 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2457 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2458#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2459 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2460 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2461#endif
2462#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2463 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2464 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2465 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2466 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2467#endif
2468 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2469 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2470 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2471#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2472 DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2473 DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2474#endif
2475#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2476 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2477 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2478#endif
2479#if HC_ARCH_BITS == 64
2480 RTRCPTR alignment3; /**< structure size alignment. */
2481#endif
2482
2483 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2484 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2485 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2486#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2487 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2488 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2489#endif
2490#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2491 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2492 R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2493#endif
2494 /** @} */
2495
2496 /** @name Function pointers for Both Shadow and Guest paging.
2497 * @{
2498 */
2499 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2500 /* no pfnR3BthTrap0eHandler */
2501 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2502 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2503 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2504 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2505 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2506 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2507 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2508 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVM pVM));
2509
2510 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2511 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2512 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2513 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2514 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2515 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2516 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2517 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2518 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVM pVM));
2519
2520 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2521 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2522 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2523 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2524 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2525 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2526 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2527 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2528 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVM pVM));
2529#if HC_ARCH_BITS == 64
2530 RTRCPTR alignment2; /**< structure size alignment. */
2531#endif
2532 /** @} */
2533
2534 /** Pointer to SHW+GST mode data (function pointers).
2535 * The index into this table is made up from */
2536 R3PTRTYPE(PPGMMODEDATA) paModeData;
2537
2538 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2539 * This is sorted by physical address and contains no overlapping ranges. */
2540 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2541 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2542 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2543 /** RC pointer corresponding to PGM::pRamRangesR3. */
2544 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2545 /** The configured RAM size. */
2546 RTUINT cbRamSize;
2547
2548 /** Pointer to the list of ROM ranges - for R3.
2549 * This is sorted by physical address and contains no overlapping ranges. */
2550 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2551 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2552 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2553 /** RC pointer corresponding to PGM::pRomRangesR3. */
2554 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2555 /** Alignment padding. */
2556 RTRCPTR GCPtrPadding2;
2557
2558 /** Pointer to the list of MMIO2 ranges - for R3.
2559 * Registration order. */
2560 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2561
2562 /** PGM offset based trees - R3 Ptr. */
2563 R3PTRTYPE(PPGMTREES) pTreesR3;
2564 /** PGM offset based trees - R0 Ptr. */
2565 R0PTRTYPE(PPGMTREES) pTreesR0;
2566 /** PGM offset based trees - RC Ptr. */
2567 RCPTRTYPE(PPGMTREES) pTreesRC;
2568
2569 /** Linked list of GC mappings - for RC.
2570 * The list is sorted ascending on address.
2571 */
2572 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2573 /** Linked list of GC mappings - for HC.
2574 * The list is sorted ascending on address.
2575 */
2576 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2577 /** Linked list of GC mappings - for R0.
2578 * The list is sorted ascending on address.
2579 */
2580 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2581
2582 /** Indicates that PGMR3FinalizeMappings has been called and that further
2583 * PGMR3MapIntermediate calls will be rejected. */
2584 bool fFinalizedMappings;
2585 /** If set no conflict checks are required. (boolean) */
2586 bool fMappingsFixed;
2587 /** If set, then no mappings are put into the shadow page table. (boolean) */
2588 bool fDisableMappings;
2589 /** Size of fixed mapping */
2590 uint32_t cbMappingFixed;
2591 /** Base address (GC) of fixed mapping */
2592 RTGCPTR GCPtrMappingFixed;
2593#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2594 uint32_t u32Padding0; /**< alignment padding. */
2595#endif
2596
2597
2598 /** @name Intermediate Context
2599 * @{ */
2600 /** Pointer to the intermediate page directory - Normal. */
2601 R3PTRTYPE(PX86PD) pInterPD;
2602 /** Pointer to the intermedate page tables - Normal.
2603 * There are two page tables, one for the identity mapping and one for
2604 * the host context mapping (of the core code). */
2605 R3PTRTYPE(PX86PT) apInterPTs[2];
2606 /** Pointer to the intermedate page tables - PAE. */
2607 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2608 /** Pointer to the intermedate page directory - PAE. */
2609 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2610 /** Pointer to the intermedate page directory - PAE. */
2611 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2612 /** Pointer to the intermedate page-map level 4 - AMD64. */
2613 R3PTRTYPE(PX86PML4) pInterPaePML4;
2614 /** Pointer to the intermedate page directory - AMD64. */
2615 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2616 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2617 RTHCPHYS HCPhysInterPD;
2618 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2619 RTHCPHYS HCPhysInterPaePDPT;
2620 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2621 RTHCPHYS HCPhysInterPaePML4;
2622 /** @} */
2623
2624 /** Base address of the dynamic page mapping area.
2625 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2626 */
2627 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2628 /** The index of the last entry used in the dynamic page mapping area. */
2629 RTUINT iDynPageMapLast;
2630 /** Cache containing the last entries in the dynamic page mapping area.
2631 * The cache size is covering half of the mapping area. */
2632 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2633
2634 /** The address of the ring-0 mapping cache if we're making use of it. */
2635 RTR0PTR pvR0DynMapUsed;
2636#if HC_ARCH_BITS == 32
2637 RTR0PTR R0PtrPadding0; /**< Alignment. */
2638#endif
2639
2640
2641 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2642 RTGCPHYS GCPhys4MBPSEMask;
2643
2644 /** A20 gate mask.
2645 * Our current approach to A20 emulation is to let REM do it and don't bother
2646 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2647 * But whould need arrise, we'll subject physical addresses to this mask. */
2648 RTGCPHYS GCPhysA20Mask;
2649 /** A20 gate state - boolean! */
2650 RTUINT fA20Enabled;
2651
2652 /** What needs syncing (PGM_SYNC_*).
2653 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2654 * PGMFlushTLB, and PGMR3Load. */
2655 RTUINT fSyncFlags;
2656
2657 /** PGM critical section.
2658 * This protects the physical & virtual access handlers, ram ranges,
2659 * and the page flag updating (some of it anyway).
2660 */
2661 PDMCRITSECT CritSect;
2662
2663 /** Shadow Page Pool - R3 Ptr. */
2664 R3PTRTYPE(PPGMPOOL) pPoolR3;
2665 /** Shadow Page Pool - R0 Ptr. */
2666 R0PTRTYPE(PPGMPOOL) pPoolR0;
2667 /** Shadow Page Pool - RC Ptr. */
2668 RCPTRTYPE(PPGMPOOL) pPoolRC;
2669
2670 /** We're not in a state which permits writes to guest memory.
2671 * (Only used in strict builds.) */
2672 bool fNoMorePhysWrites;
2673
2674 /** Flush the cache on the next access. */
2675 bool fPhysCacheFlushPending;
2676/** @todo r=bird: Fix member names!*/
2677 /** PGMPhysRead cache */
2678 PGMPHYSCACHE pgmphysreadcache;
2679 /** PGMPhysWrite cache */
2680 PGMPHYSCACHE pgmphyswritecache;
2681
2682 /**
2683 * Data associated with managing the ring-3 mappings of the allocation chunks.
2684 */
2685 struct
2686 {
2687 /** The chunk tree, ordered by chunk id. */
2688#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2689 R3PTRTYPE(PAVLU32NODECORE) pTree;
2690#else
2691 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2692#endif
2693 /** The chunk mapping TLB. */
2694 PGMCHUNKR3MAPTLB Tlb;
2695 /** The number of mapped chunks. */
2696 uint32_t c;
2697 /** The maximum number of mapped chunks.
2698 * @cfgm PGM/MaxRing3Chunks */
2699 uint32_t cMax;
2700 /** The chunk age tree, ordered by ageing sequence number. */
2701 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2702 /** The current time. */
2703 uint32_t iNow;
2704 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2705 uint32_t AgeingCountdown;
2706 } ChunkR3Map;
2707
2708 /**
2709 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2710 */
2711 PGMPAGER3MAPTLB PhysTlbHC;
2712
2713 /** @name The zero page.
2714 * @{ */
2715 /** The host physical address of the zero page. */
2716 RTHCPHYS HCPhysZeroPg;
2717 /** The ring-3 mapping of the zero page. */
2718 RTR3PTR pvZeroPgR3;
2719 /** The ring-0 mapping of the zero page. */
2720 RTR0PTR pvZeroPgR0;
2721 /** The GC mapping of the zero page. */
2722 RTGCPTR pvZeroPgGC;
2723#if GC_ARCH_BITS != 32
2724 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2725#endif
2726 /** @}*/
2727
2728 /** The number of handy pages. */
2729 uint32_t cHandyPages;
2730 /**
2731 * Array of handy pages.
2732 *
2733 * This array is used in a two way communication between pgmPhysAllocPage
2734 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2735 * an intermediary.
2736 *
2737 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2738 * (The current size of 32 pages, means 128 KB of handy memory.)
2739 */
2740 GMMPAGEDESC aHandyPages[32];
2741
2742 /** @name Release Statistics
2743 * @{ */
2744 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2745 uint32_t cPrivatePages; /**< The number of private pages. */
2746 uint32_t cSharedPages; /**< The number of shared pages. */
2747 uint32_t cZeroPages; /**< The number of zero backed pages. */
2748 /** The number of times the guest has switched mode since last reset or statistics reset. */
2749 STAMCOUNTER cGuestModeChanges;
2750 /** The number of times we were forced to change the hypervisor region location. */
2751 STAMCOUNTER cRelocations;
2752 /** @} */
2753
2754#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2755 /** RC: Which statistic this \#PF should be attributed to. */
2756 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2757 RTRCPTR padding0;
2758 /** R0: Which statistic this \#PF should be attributed to. */
2759 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2760 RTR0PTR padding1;
2761
2762 /* Common */
2763# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2764 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2765 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2766 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2767 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2768 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2769 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2770# endif
2771 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2772 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2773
2774 /* R3 only: */
2775 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2776 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2777 STAMCOUNTER StatR3GuestPDWrite; /**< R3: The total number of times pgmHCGuestPDWriteHandler() was called. */
2778 STAMCOUNTER StatR3GuestPDWriteConflict; /**< R3: The number of times GuestPDWriteContlict() detected a conflict. */
2779 STAMCOUNTER StatR3DynRamTotal; /**< R3: Allocated MBs of guest ram */
2780 STAMCOUNTER StatR3DynRamGrow; /**< R3: Nr of pgmr3PhysGrowRange calls. */
2781
2782 /* R0 only: */
2783 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2784 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2785 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2786 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2787 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2788 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2789 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2790 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2791 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2792 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2793 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2794 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2795 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2796 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2797 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2798 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2799 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2800 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2801 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2802 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2803 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2804 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2805 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2806 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2807 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2808 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2809
2810 /* RC only: */
2811 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache hits */
2812 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache misses */
2813 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2814 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2815
2816 /* RZ only: */
2817 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2818 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2819 STAMPROFILE StatRZTrap0eTimeSyncPT;
2820 STAMPROFILE StatRZTrap0eTimeMapping;
2821 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2822 STAMPROFILE StatRZTrap0eTimeHandlers;
2823 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2824 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2825 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2826 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2827 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2828 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2829 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2830 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2831 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2832 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2833 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2834 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2835 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2836 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2837 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2838 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2839 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2840 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2841 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2842 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2843 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2844 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2845 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2846 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2847 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2848 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2849 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2850 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2851 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2852 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2853 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2854 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2855 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2856 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2857 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2858 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2859 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2860 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2861 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2862 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2863 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2864 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2865 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2866
2867 /* HC - R3 and (maybe) R0: */
2868
2869 /* RZ & R3: */
2870 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2871 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2872 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2873 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2874 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2875 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2876 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2877 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2878 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2879 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2880 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2881 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2882 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2883 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2884 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2885 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2886 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2887 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2888 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2889 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2890 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2891 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2892 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2893 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2894 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2895 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2896 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2897 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2898 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2899 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2900 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2901 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2902 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2903 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2904 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2905 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2906 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2907 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2908 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2909 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2910 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2911 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2912 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2913 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2914 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2915 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2916 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2917/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2918 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2919 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2920 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2921 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2922 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2923 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2924
2925 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2926 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2927 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2928 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2929 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2930 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2931 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2932 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2933 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2934 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2935 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2936 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2937 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2938 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2939 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2940 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2941 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2942 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2943 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2944 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2945 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2946 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2947 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2948 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2949 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2950 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2951 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2952 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2953 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2954 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2955 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2956 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2957 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2958 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2959 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2960 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2961 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2962 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2963 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2964 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2965 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2966 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2967 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2968 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2969 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2970 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2971 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2972/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2973 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2974 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2975 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2976 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2977 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2978 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2979#endif /* VBOX_WITH_STATISTICS */
2980} PGM;
2981/** Pointer to the PGM instance data. */
2982typedef PGM *PPGM;
2983
2984
2985/**
2986 * PGMCPU Data (part of VMCPU).
2987 */
2988typedef struct PGMCPU
2989{
2990 /** Offset to the VMCPU structure. */
2991 RTINT offVMCPU;
2992 /** Automatically tracked physical memory mapping set.
2993 * Ring-0 and strict raw-mode builds. */
2994 PGMMAPSET AutoSet;
2995} PGMCPU;
2996/** Pointer to the per-cpu PGM data. */
2997typedef PGMCPU *PPGMCPU;
2998
2999
3000/** @name PGM::fSyncFlags Flags
3001 * @{
3002 */
3003/** Updates the virtual access handler state bit in PGMPAGE. */
3004#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3005/** Always sync CR3. */
3006#define PGM_SYNC_ALWAYS RT_BIT(1)
3007/** Check monitoring on next CR3 (re)load and invalidate page. */
3008#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3009/** Check guest mapping in SyncCR3. */
3010#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3011/** Clear the page pool (a light weight flush). */
3012#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
3013/** @} */
3014
3015
3016__BEGIN_DECLS
3017
3018int pgmLock(PVM pVM);
3019void pgmUnlock(PVM pVM);
3020
3021VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3022VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3023
3024int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3025int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3026PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3027void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3028DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3029
3030void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3031bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3032int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3033DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3034#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3035void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3036#else
3037# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3038#endif
3039DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3040
3041
3042void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3043int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3044int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3045int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3046int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
3047int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3048int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3049#ifdef IN_RING3
3050int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3051int pgmR3PhysRamReset(PVM pVM);
3052int pgmR3PhysRomReset(PVM pVM);
3053# ifndef VBOX_WITH_NEW_PHYS_CODE
3054int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
3055# endif
3056
3057int pgmR3PoolInit(PVM pVM);
3058void pgmR3PoolRelocate(PVM pVM);
3059void pgmR3PoolReset(PVM pVM);
3060
3061#endif /* IN_RING3 */
3062#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3063int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3064#endif
3065#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3066void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
3067#endif
3068int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
3069PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
3070void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3071void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3072int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3073void pgmPoolFlushAll(PVM pVM);
3074void pgmPoolClearAll(PVM pVM);
3075int pgmPoolSyncCR3(PVM pVM);
3076void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
3077void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
3078int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
3079PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
3080void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
3081void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
3082uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3083void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3084#ifdef PGMPOOL_WITH_MONITORING
3085void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3086int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3087void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3088void pgmPoolMonitorModifiedClearAll(PVM pVM);
3089int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
3090int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
3091#endif
3092
3093#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3094void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
3095void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3096int pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3097#endif
3098int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3099int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3100
3101#ifndef IN_RC
3102int pgmShwSyncLongModePDPtr(PVM pVM, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3103#endif
3104int pgmShwGetEPTPDPtr(PVM pVM, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3105
3106__END_DECLS
3107
3108
3109/**
3110 * Gets the PGMRAMRANGE structure for a guest page.
3111 *
3112 * @returns Pointer to the RAM range on success.
3113 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3114 *
3115 * @param pPGM PGM handle.
3116 * @param GCPhys The GC physical address.
3117 */
3118DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3119{
3120 /*
3121 * Optimize for the first range.
3122 */
3123 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3124 RTGCPHYS off = GCPhys - pRam->GCPhys;
3125 if (RT_UNLIKELY(off >= pRam->cb))
3126 {
3127 do
3128 {
3129 pRam = pRam->CTX_SUFF(pNext);
3130 if (RT_UNLIKELY(!pRam))
3131 break;
3132 off = GCPhys - pRam->GCPhys;
3133 } while (off >= pRam->cb);
3134 }
3135 return pRam;
3136}
3137
3138
3139/**
3140 * Gets the PGMPAGE structure for a guest page.
3141 *
3142 * @returns Pointer to the page on success.
3143 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3144 *
3145 * @param pPGM PGM handle.
3146 * @param GCPhys The GC physical address.
3147 */
3148DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3149{
3150 /*
3151 * Optimize for the first range.
3152 */
3153 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3154 RTGCPHYS off = GCPhys - pRam->GCPhys;
3155 if (RT_UNLIKELY(off >= pRam->cb))
3156 {
3157 do
3158 {
3159 pRam = pRam->CTX_SUFF(pNext);
3160 if (RT_UNLIKELY(!pRam))
3161 return NULL;
3162 off = GCPhys - pRam->GCPhys;
3163 } while (off >= pRam->cb);
3164 }
3165 return &pRam->aPages[off >> PAGE_SHIFT];
3166}
3167
3168
3169/**
3170 * Gets the PGMPAGE structure for a guest page.
3171 *
3172 * Old Phys code: Will make sure the page is present.
3173 *
3174 * @returns VBox status code.
3175 * @retval VINF_SUCCESS and a valid *ppPage on success.
3176 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3177 *
3178 * @param pPGM PGM handle.
3179 * @param GCPhys The GC physical address.
3180 * @param ppPage Where to store the page poitner on success.
3181 */
3182DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3183{
3184 /*
3185 * Optimize for the first range.
3186 */
3187 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3188 RTGCPHYS off = GCPhys - pRam->GCPhys;
3189 if (RT_UNLIKELY(off >= pRam->cb))
3190 {
3191 do
3192 {
3193 pRam = pRam->CTX_SUFF(pNext);
3194 if (RT_UNLIKELY(!pRam))
3195 {
3196 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3197 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3198 }
3199 off = GCPhys - pRam->GCPhys;
3200 } while (off >= pRam->cb);
3201 }
3202 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3203#ifndef VBOX_WITH_NEW_PHYS_CODE
3204
3205 /*
3206 * Make sure it's present.
3207 */
3208 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3209 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3210 {
3211#ifdef IN_RING3
3212 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3213#else
3214 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3215#endif
3216 if (RT_FAILURE(rc))
3217 {
3218 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3219 return rc;
3220 }
3221 Assert(rc == VINF_SUCCESS);
3222 }
3223#endif
3224 return VINF_SUCCESS;
3225}
3226
3227
3228
3229
3230/**
3231 * Gets the PGMPAGE structure for a guest page.
3232 *
3233 * Old Phys code: Will make sure the page is present.
3234 *
3235 * @returns VBox status code.
3236 * @retval VINF_SUCCESS and a valid *ppPage on success.
3237 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3238 *
3239 * @param pPGM PGM handle.
3240 * @param GCPhys The GC physical address.
3241 * @param ppPage Where to store the page poitner on success.
3242 * @param ppRamHint Where to read and store the ram list hint.
3243 * The caller initializes this to NULL before the call.
3244 */
3245DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3246{
3247 RTGCPHYS off;
3248 PPGMRAMRANGE pRam = *ppRamHint;
3249 if ( !pRam
3250 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3251 {
3252 pRam = pPGM->CTX_SUFF(pRamRanges);
3253 off = GCPhys - pRam->GCPhys;
3254 if (RT_UNLIKELY(off >= pRam->cb))
3255 {
3256 do
3257 {
3258 pRam = pRam->CTX_SUFF(pNext);
3259 if (RT_UNLIKELY(!pRam))
3260 {
3261 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3262 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3263 }
3264 off = GCPhys - pRam->GCPhys;
3265 } while (off >= pRam->cb);
3266 }
3267 *ppRamHint = pRam;
3268 }
3269 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3270#ifndef VBOX_WITH_NEW_PHYS_CODE
3271
3272 /*
3273 * Make sure it's present.
3274 */
3275 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3276 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3277 {
3278#ifdef IN_RING3
3279 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3280#else
3281 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3282#endif
3283 if (RT_FAILURE(rc))
3284 {
3285 *ppPage = NULL; /* Shut up annoying smart ass. */
3286 return rc;
3287 }
3288 Assert(rc == VINF_SUCCESS);
3289 }
3290#endif
3291 return VINF_SUCCESS;
3292}
3293
3294
3295/**
3296 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3297 *
3298 * @returns Pointer to the page on success.
3299 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3300 *
3301 * @param pPGM PGM handle.
3302 * @param GCPhys The GC physical address.
3303 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3304 */
3305DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3306{
3307 /*
3308 * Optimize for the first range.
3309 */
3310 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3311 RTGCPHYS off = GCPhys - pRam->GCPhys;
3312 if (RT_UNLIKELY(off >= pRam->cb))
3313 {
3314 do
3315 {
3316 pRam = pRam->CTX_SUFF(pNext);
3317 if (RT_UNLIKELY(!pRam))
3318 return NULL;
3319 off = GCPhys - pRam->GCPhys;
3320 } while (off >= pRam->cb);
3321 }
3322 *ppRam = pRam;
3323 return &pRam->aPages[off >> PAGE_SHIFT];
3324}
3325
3326
3327/**
3328 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3329 *
3330 * @returns Pointer to the page on success.
3331 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3332 *
3333 * @param pPGM PGM handle.
3334 * @param GCPhys The GC physical address.
3335 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3336 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3337 */
3338DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3339{
3340 /*
3341 * Optimize for the first range.
3342 */
3343 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3344 RTGCPHYS off = GCPhys - pRam->GCPhys;
3345 if (RT_UNLIKELY(off >= pRam->cb))
3346 {
3347 do
3348 {
3349 pRam = pRam->CTX_SUFF(pNext);
3350 if (RT_UNLIKELY(!pRam))
3351 {
3352 *ppRam = NULL; /* Shut up silly GCC warnings. */
3353 *ppPage = NULL; /* ditto */
3354 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3355 }
3356 off = GCPhys - pRam->GCPhys;
3357 } while (off >= pRam->cb);
3358 }
3359 *ppRam = pRam;
3360 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3361#ifndef VBOX_WITH_NEW_PHYS_CODE
3362
3363 /*
3364 * Make sure it's present.
3365 */
3366 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3367 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3368 {
3369#ifdef IN_RING3
3370 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3371#else
3372 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3373#endif
3374 if (RT_FAILURE(rc))
3375 {
3376 *ppPage = NULL; /* Shut up silly GCC warnings. */
3377 *ppPage = NULL; /* ditto */
3378 return rc;
3379 }
3380 Assert(rc == VINF_SUCCESS);
3381
3382 }
3383#endif
3384 return VINF_SUCCESS;
3385}
3386
3387
3388/**
3389 * Convert GC Phys to HC Phys.
3390 *
3391 * @returns VBox status.
3392 * @param pPGM PGM handle.
3393 * @param GCPhys The GC physical address.
3394 * @param pHCPhys Where to store the corresponding HC physical address.
3395 *
3396 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3397 * Avoid when writing new code!
3398 */
3399DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3400{
3401 PPGMPAGE pPage;
3402 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3403 if (RT_FAILURE(rc))
3404 return rc;
3405 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3406 return VINF_SUCCESS;
3407}
3408
3409#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3410
3411/**
3412 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3413 * optimizes access to pages already in the set.
3414 *
3415 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3416 * @param pPGM Pointer to the PVM instance data.
3417 * @param HCPhys The physical address of the page.
3418 * @param ppv Where to store the mapping address.
3419 */
3420DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3421{
3422 STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3423 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3424 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3425 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3426
3427 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3428 unsigned iEntry = pSet->aiHashTable[iHash];
3429 if ( iEntry < pSet->cEntries
3430 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3431 {
3432 *ppv = pSet->aEntries[iEntry].pvPage;
3433 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3434 }
3435 else
3436 {
3437 STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3438 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3439 }
3440
3441 STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3442 return VINF_SUCCESS;
3443}
3444
3445
3446/**
3447 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3448 * access to pages already in the set.
3449 *
3450 * @returns See PGMDynMapGCPage.
3451 * @param pPGM Pointer to the PVM instance data.
3452 * @param HCPhys The physical address of the page.
3453 * @param ppv Where to store the mapping address.
3454 */
3455DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3456{
3457 STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3458 Assert(!(GCPhys & PAGE_OFFSET_MASK));
3459
3460 /*
3461 * Get the ram range.
3462 */
3463 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3464 RTGCPHYS off = GCPhys - pRam->GCPhys;
3465 if (RT_UNLIKELY(off >= pRam->cb
3466 /** @todo || page state stuff */))
3467 {
3468 /* This case is not counted into StatR0DynMapGCPageInl. */
3469 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3470 return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3471 }
3472
3473 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3474 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3475
3476 /*
3477 * pgmR0DynMapHCPageInlined with out stats.
3478 */
3479 PPGMMAPSET pSet = &((PPGMCPU)((uint8_t *)VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; /* very pretty ;-) */
3480 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3481 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3482
3483 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3484 unsigned iEntry = pSet->aiHashTable[iHash];
3485 if ( iEntry < pSet->cEntries
3486 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3487 {
3488 *ppv = pSet->aEntries[iEntry].pvPage;
3489 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3490 }
3491 else
3492 {
3493 STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3494 pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3495 }
3496
3497 STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3498 return VINF_SUCCESS;
3499}
3500
3501#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3502#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3503
3504/**
3505 * Maps the page into current context (RC and maybe R0).
3506 *
3507 * @returns pointer to the mapping.
3508 * @param pVM Pointer to the PGM instance data.
3509 * @param pPage The page.
3510 */
3511DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3512{
3513 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3514 {
3515 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3516 void *pv;
3517# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3518 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3519# else
3520 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3521# endif
3522 return pv;
3523 }
3524 return pgmPoolMapPageFallback(pPGM, pPage);
3525}
3526
3527/**
3528 * Temporarily maps one host page specified by HC physical address, returning
3529 * pointer within the page.
3530 *
3531 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3532 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3533 *
3534 * @returns The address corresponding to HCPhys.
3535 * @param pPGM Pointer to the PVM instance data.
3536 * @param HCPhys HC Physical address of the page.
3537 */
3538DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3539{
3540 void *pv;
3541# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3542 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3543# else
3544 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3545# endif
3546 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3547 return pv;
3548}
3549
3550#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3551
3552#ifndef IN_RC
3553/**
3554 * Queries the Physical TLB entry for a physical guest page,
3555 * attemting to load the TLB entry if necessary.
3556 *
3557 * @returns VBox status code.
3558 * @retval VINF_SUCCESS on success
3559 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3560 *
3561 * @param pPGM The PGM instance handle.
3562 * @param GCPhys The address of the guest page.
3563 * @param ppTlbe Where to store the pointer to the TLB entry.
3564 */
3565DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3566{
3567 int rc;
3568 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3569 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3570 {
3571 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3572 rc = VINF_SUCCESS;
3573 }
3574 else
3575 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3576 *ppTlbe = pTlbe;
3577 return rc;
3578}
3579
3580
3581/**
3582 * Queries the Physical TLB entry for a physical guest page,
3583 * attemting to load the TLB entry if necessary.
3584 *
3585 * @returns VBox status code.
3586 * @retval VINF_SUCCESS on success
3587 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3588 *
3589 * @param pPGM The PGM instance handle.
3590 * @param pPage Pointer to the PGMPAGE structure corresponding to
3591 * GCPhys.
3592 * @param GCPhys The address of the guest page.
3593 * @param ppTlbe Where to store the pointer to the TLB entry.
3594 */
3595DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3596{
3597 int rc;
3598 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3599 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3600 {
3601 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3602 rc = VINF_SUCCESS;
3603 }
3604 else
3605 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3606 *ppTlbe = pTlbe;
3607 return rc;
3608}
3609#endif /* !IN_RC */
3610
3611
3612#ifndef VBOX_WITH_NEW_PHYS_CODE
3613/**
3614 * Convert GC Phys to HC Virt and HC Phys.
3615 *
3616 * @returns VBox status.
3617 * @param pPGM PGM handle.
3618 * @param GCPhys The GC physical address.
3619 * @param pHCPtr Where to store the corresponding HC virtual address.
3620 * @param pHCPhys Where to store the HC Physical address and its flags.
3621 *
3622 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3623 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3624 * Either way, we have to make sure the page is writable in MapCR3.
3625 */
3626DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3627{
3628 PPGMRAMRANGE pRam;
3629 PPGMPAGE pPage;
3630 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3631 if (RT_FAILURE(rc))
3632 {
3633 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3634 *pHCPhys = 0; /* ditto */
3635 return rc;
3636 }
3637 RTGCPHYS off = GCPhys - pRam->GCPhys;
3638
3639 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3640 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3641 {
3642 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3643#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3644 PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3645 *pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3646#else
3647 *pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3648#endif
3649 return VINF_SUCCESS;
3650 }
3651 if (pRam->pvR3)
3652 {
3653 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3654 return VINF_SUCCESS;
3655 }
3656 *pHCPtr = 0;
3657 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3658}
3659#endif /* VBOX_WITH_NEW_PHYS_CODE */
3660
3661
3662/**
3663 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3664 * Takes PSE-36 into account.
3665 *
3666 * @returns guest physical address
3667 * @param pPGM Pointer to the PGM instance data.
3668 * @param Pde Guest Pde
3669 */
3670DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3671{
3672 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3673 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3674
3675 return GCPhys & pPGM->GCPhys4MBPSEMask;
3676}
3677
3678
3679/**
3680 * Gets the page directory entry for the specified address (32-bit paging).
3681 *
3682 * @returns The page directory entry in question.
3683 * @param pPGM Pointer to the PGM instance data.
3684 * @param GCPtr The address.
3685 */
3686DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3687{
3688#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3689 PCX86PD pGuestPD = 0;
3690 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3691 if (RT_FAILURE(rc))
3692 {
3693 X86PDE ZeroPde = {0};
3694 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3695 }
3696 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3697#else
3698 return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3699#endif
3700}
3701
3702
3703/**
3704 * Gets the address of a specific page directory entry (32-bit paging).
3705 *
3706 * @returns Pointer the page directory entry in question.
3707 * @param pPGM Pointer to the PGM instance data.
3708 * @param GCPtr The address.
3709 */
3710DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3711{
3712#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3713 PX86PD pGuestPD = 0;
3714 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3715 AssertRCReturn(rc, 0);
3716 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3717#else
3718 return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3719#endif
3720}
3721
3722
3723/**
3724 * Gets the address the guest page directory (32-bit paging).
3725 *
3726 * @returns Pointer the page directory entry in question.
3727 * @param pPGM Pointer to the PGM instance data.
3728 */
3729DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3730{
3731#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3732 PX86PD pGuestPD = 0;
3733 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3734 AssertRCReturn(rc, 0);
3735 return pGuestPD;
3736#else
3737 return pPGM->CTX_SUFF(pGst32BitPd);
3738#endif
3739}
3740
3741
3742/**
3743 * Gets the guest page directory pointer table.
3744 *
3745 * @returns Pointer to the page directory in question.
3746 * @returns NULL if the page directory is not present or on an invalid page.
3747 * @param pPGM Pointer to the PGM instance data.
3748 */
3749DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3750{
3751#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3752 PX86PDPT pGuestPDPT = 0;
3753 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3754 AssertRCReturn(rc, 0);
3755 return pGuestPDPT;
3756#else
3757 return pPGM->CTX_SUFF(pGstPaePdpt);
3758#endif
3759}
3760
3761
3762/**
3763 * Gets the guest page directory pointer table entry for the specified address.
3764 *
3765 * @returns Pointer to the page directory in question.
3766 * @returns NULL if the page directory is not present or on an invalid page.
3767 * @param pPGM Pointer to the PGM instance data.
3768 * @param GCPtr The address.
3769 */
3770DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3771{
3772 AssertGCPtr32(GCPtr);
3773
3774#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3775 PX86PDPT pGuestPDPT = 0;
3776 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3777 AssertRCReturn(rc, 0);
3778 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3779#else
3780 return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3781#endif
3782}
3783
3784
3785/**
3786 * Gets the page directory for the specified address.
3787 *
3788 * @returns Pointer to the page directory in question.
3789 * @returns NULL if the page directory is not present or on an invalid page.
3790 * @param pPGM Pointer to the PGM instance data.
3791 * @param GCPtr The address.
3792 */
3793DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3794{
3795 AssertGCPtr32(GCPtr);
3796
3797#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3798 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3799 AssertReturn(pGuestPDPT, 0);
3800#else
3801 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3802#endif
3803 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3804 if (pGuestPDPT->a[iPdPt].n.u1Present)
3805 {
3806#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3807 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3808 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3809#endif
3810
3811 /* cache is out-of-sync. */
3812 PX86PDPAE pPD;
3813 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3814 if (RT_SUCCESS(rc))
3815 return pPD;
3816 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3817 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3818 }
3819 return NULL;
3820}
3821
3822
3823/**
3824 * Gets the page directory entry for the specified address.
3825 *
3826 * @returns Pointer to the page directory entry in question.
3827 * @returns NULL if the page directory is not present or on an invalid page.
3828 * @param pPGM Pointer to the PGM instance data.
3829 * @param GCPtr The address.
3830 */
3831DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3832{
3833 AssertGCPtr32(GCPtr);
3834
3835#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3836 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3837 AssertReturn(pGuestPDPT, 0);
3838#else
3839 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3840#endif
3841 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3842 if (pGuestPDPT->a[iPdPt].n.u1Present)
3843 {
3844 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3845#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3846 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3847 return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3848#endif
3849
3850 /* The cache is out-of-sync. */
3851 PX86PDPAE pPD;
3852 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3853 if (RT_SUCCESS(rc))
3854 return &pPD->a[iPD];
3855 AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3856 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3857 }
3858 return NULL;
3859}
3860
3861
3862/**
3863 * Gets the page directory entry for the specified address.
3864 *
3865 * @returns The page directory entry in question.
3866 * @returns A non-present entry if the page directory is not present or on an invalid page.
3867 * @param pPGM Pointer to the PGM instance data.
3868 * @param GCPtr The address.
3869 */
3870DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3871{
3872 AssertGCPtr32(GCPtr);
3873
3874#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3875 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3876 if (RT_LIKELY(pGuestPDPT))
3877#else
3878 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3879#endif
3880 {
3881 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3882 if (pGuestPDPT->a[iPdPt].n.u1Present)
3883 {
3884 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3885#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3886 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3887 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3888#endif
3889
3890 /* cache is out-of-sync. */
3891 PX86PDPAE pPD;
3892 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3893 if (RT_SUCCESS(rc))
3894 return pPD->a[iPD];
3895 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3896 }
3897 }
3898 X86PDEPAE ZeroPde = {0};
3899 return ZeroPde;
3900}
3901
3902
3903/**
3904 * Gets the page directory pointer table entry for the specified address
3905 * and returns the index into the page directory
3906 *
3907 * @returns Pointer to the page directory in question.
3908 * @returns NULL if the page directory is not present or on an invalid page.
3909 * @param pPGM Pointer to the PGM instance data.
3910 * @param GCPtr The address.
3911 * @param piPD Receives the index into the returned page directory
3912 * @param pPdpe Receives the page directory pointer entry. Optional.
3913 */
3914DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3915{
3916 AssertGCPtr32(GCPtr);
3917
3918#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3919 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3920 AssertReturn(pGuestPDPT, 0);
3921#else
3922 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3923#endif
3924 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3925 if (pPdpe)
3926 *pPdpe = pGuestPDPT->a[iPdPt];
3927 if (pGuestPDPT->a[iPdPt].n.u1Present)
3928 {
3929 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3930#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3931 if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3932 {
3933 *piPD = iPD;
3934 return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3935 }
3936#endif
3937
3938 /* cache is out-of-sync. */
3939 PX86PDPAE pPD;
3940 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3941 if (RT_SUCCESS(rc))
3942 {
3943 *piPD = iPD;
3944 return pPD;
3945 }
3946 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3947 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3948 }
3949 return NULL;
3950}
3951
3952#ifndef IN_RC
3953
3954/**
3955 * Gets the page map level-4 pointer for the guest.
3956 *
3957 * @returns Pointer to the PML4 page.
3958 * @param pPGM Pointer to the PGM instance data.
3959 */
3960DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3961{
3962#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3963 PX86PML4 pGuestPml4;
3964 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3965 AssertRCReturn(rc, NULL);
3966 return pGuestPml4;
3967#else
3968 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3969 return pPGM->CTX_SUFF(pGstAmd64Pml4);
3970#endif
3971}
3972
3973
3974/**
3975 * Gets the pointer to a page map level-4 entry.
3976 *
3977 * @returns Pointer to the PML4 entry.
3978 * @param pPGM Pointer to the PGM instance data.
3979 * @param iPml4 The index.
3980 */
3981DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3982{
3983#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3984 PX86PML4 pGuestPml4;
3985 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3986 AssertRCReturn(rc, NULL);
3987 return &pGuestPml4->a[iPml4];
3988#else
3989 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3990 return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3991#endif
3992}
3993
3994
3995/**
3996 * Gets a page map level-4 entry.
3997 *
3998 * @returns The PML4 entry.
3999 * @param pPGM Pointer to the PGM instance data.
4000 * @param iPml4 The index.
4001 */
4002DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
4003{
4004#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4005 PX86PML4 pGuestPml4;
4006 int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
4007 if (RT_FAILURE(rc))
4008 {
4009 X86PML4E ZeroPml4e = {0};
4010 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
4011 }
4012 return pGuestPml4->a[iPml4];
4013#else
4014 Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
4015 return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
4016#endif
4017}
4018
4019
4020/**
4021 * Gets the page directory pointer entry for the specified address.
4022 *
4023 * @returns Pointer to the page directory pointer entry in question.
4024 * @returns NULL if the page directory is not present or on an invalid page.
4025 * @param pPGM Pointer to the PGM instance data.
4026 * @param GCPtr The address.
4027 * @param ppPml4e Page Map Level-4 Entry (out)
4028 */
4029DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
4030{
4031 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4032 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4033 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4034 if (pPml4e->n.u1Present)
4035 {
4036 PX86PDPT pPdpt;
4037 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
4038 AssertRCReturn(rc, NULL);
4039
4040 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4041 return &pPdpt->a[iPdPt];
4042 }
4043 return NULL;
4044}
4045
4046
4047/**
4048 * Gets the page directory entry for the specified address.
4049 *
4050 * @returns The page directory entry in question.
4051 * @returns A non-present entry if the page directory is not present or on an invalid page.
4052 * @param pPGM Pointer to the PGM instance data.
4053 * @param GCPtr The address.
4054 * @param ppPml4e Page Map Level-4 Entry (out)
4055 * @param pPdpe Page directory pointer table entry (out)
4056 */
4057DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
4058{
4059 X86PDEPAE ZeroPde = {0};
4060 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4061 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4062 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4063 if (pPml4e->n.u1Present)
4064 {
4065 PCX86PDPT pPdptTemp;
4066 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4067 AssertRCReturn(rc, ZeroPde);
4068
4069 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4070 *pPdpe = pPdptTemp->a[iPdPt];
4071 if (pPdptTemp->a[iPdPt].n.u1Present)
4072 {
4073 PCX86PDPAE pPD;
4074 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4075 AssertRCReturn(rc, ZeroPde);
4076
4077 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4078 return pPD->a[iPD];
4079 }
4080 }
4081
4082 return ZeroPde;
4083}
4084
4085
4086/**
4087 * Gets the page directory entry for the specified address.
4088 *
4089 * @returns The page directory entry in question.
4090 * @returns A non-present entry if the page directory is not present or on an invalid page.
4091 * @param pPGM Pointer to the PGM instance data.
4092 * @param GCPtr The address.
4093 */
4094DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4095{
4096 X86PDEPAE ZeroPde = {0};
4097 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4098 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4099 if (pGuestPml4->a[iPml4].n.u1Present)
4100 {
4101 PCX86PDPT pPdptTemp;
4102 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4103 AssertRCReturn(rc, ZeroPde);
4104
4105 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4106 if (pPdptTemp->a[iPdPt].n.u1Present)
4107 {
4108 PCX86PDPAE pPD;
4109 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4110 AssertRCReturn(rc, ZeroPde);
4111
4112 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4113 return pPD->a[iPD];
4114 }
4115 }
4116 return ZeroPde;
4117}
4118
4119
4120/**
4121 * Gets the page directory entry for the specified address.
4122 *
4123 * @returns Pointer to the page directory entry in question.
4124 * @returns NULL if the page directory is not present or on an invalid page.
4125 * @param pPGM Pointer to the PGM instance data.
4126 * @param GCPtr The address.
4127 */
4128DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4129{
4130 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4131 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4132 if (pGuestPml4->a[iPml4].n.u1Present)
4133 {
4134 PCX86PDPT pPdptTemp;
4135 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4136 AssertRCReturn(rc, NULL);
4137
4138 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4139 if (pPdptTemp->a[iPdPt].n.u1Present)
4140 {
4141 PX86PDPAE pPD;
4142 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4143 AssertRCReturn(rc, NULL);
4144
4145 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4146 return &pPD->a[iPD];
4147 }
4148 }
4149 return NULL;
4150}
4151
4152
4153/**
4154 * Gets the GUEST page directory pointer for the specified address.
4155 *
4156 * @returns The page directory in question.
4157 * @returns NULL if the page directory is not present or on an invalid page.
4158 * @param pPGM Pointer to the PGM instance data.
4159 * @param GCPtr The address.
4160 * @param ppPml4e Page Map Level-4 Entry (out)
4161 * @param pPdpe Page directory pointer table entry (out)
4162 * @param piPD Receives the index into the returned page directory
4163 */
4164DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4165{
4166 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4167 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4168 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4169 if (pPml4e->n.u1Present)
4170 {
4171 PCX86PDPT pPdptTemp;
4172 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4173 AssertRCReturn(rc, NULL);
4174
4175 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4176 *pPdpe = pPdptTemp->a[iPdPt];
4177 if (pPdptTemp->a[iPdPt].n.u1Present)
4178 {
4179 PX86PDPAE pPD;
4180 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4181 AssertRCReturn(rc, NULL);
4182
4183 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4184 return pPD;
4185 }
4186 }
4187 return 0;
4188}
4189
4190#endif /* !IN_RC */
4191
4192/**
4193 * Gets the shadow page directory, 32-bit.
4194 *
4195 * @returns Pointer to the shadow 32-bit PD.
4196 * @param pPGM Pointer to the PGM instance data.
4197 */
4198DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4199{
4200#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4201 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4202#else
4203# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4204 PX86PD pShwPd;
4205 Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4206 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4207 AssertRCReturn(rc, NULL);
4208 return pShwPd;
4209# else
4210 return pPGM->CTX_SUFF(pShw32BitPd);
4211# endif
4212#endif
4213}
4214
4215
4216/**
4217 * Gets the shadow page directory entry for the specified address, 32-bit.
4218 *
4219 * @returns Shadow 32-bit PDE.
4220 * @param pPGM Pointer to the PGM instance data.
4221 * @param GCPtr The address.
4222 */
4223DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4224{
4225 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4226
4227 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4228 if (!pShwPde)
4229 {
4230 X86PDE ZeroPde = {0};
4231 return ZeroPde;
4232 }
4233 return pShwPde->a[iPd];
4234}
4235
4236
4237/**
4238 * Gets the pointer to the shadow page directory entry for the specified
4239 * address, 32-bit.
4240 *
4241 * @returns Pointer to the shadow 32-bit PDE.
4242 * @param pPGM Pointer to the PGM instance data.
4243 * @param GCPtr The address.
4244 */
4245DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4246{
4247 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4248
4249 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4250 AssertReturn(pPde, NULL);
4251 return &pPde->a[iPd];
4252}
4253
4254
4255/**
4256 * Gets the shadow page pointer table, PAE.
4257 *
4258 * @returns Pointer to the shadow PAE PDPT.
4259 * @param pPGM Pointer to the PGM instance data.
4260 */
4261DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4262{
4263#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4264 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4265#else
4266# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4267 PX86PDPT pShwPdpt;
4268 Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4269 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4270 AssertRCReturn(rc, 0);
4271 return pShwPdpt;
4272# else
4273 return pPGM->CTX_SUFF(pShwPaePdpt);
4274# endif
4275#endif
4276}
4277
4278
4279/**
4280 * Gets the shadow page directory for the specified address, PAE.
4281 *
4282 * @returns Pointer to the shadow PD.
4283 * @param pPGM Pointer to the PGM instance data.
4284 * @param GCPtr The address.
4285 */
4286DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4287{
4288#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4289 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4290 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4291
4292 if (!pPdpt->a[iPdpt].n.u1Present)
4293 return NULL;
4294
4295 /* Fetch the pgm pool shadow descriptor. */
4296 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4297 AssertReturn(pShwPde, NULL);
4298
4299 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4300#else
4301 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4302# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4303 PX86PDPAE pPD;
4304 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4305 AssertRCReturn(rc, 0);
4306 return pPD;
4307# else
4308 PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4309 Assert(pPD);
4310 return pPD;
4311# endif
4312#endif
4313}
4314
4315
4316/**
4317 * Gets the shadow page directory for the specified address, PAE.
4318 *
4319 * @returns Pointer to the shadow PD.
4320 * @param pPGM Pointer to the PGM instance data.
4321 * @param GCPtr The address.
4322 */
4323DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4324{
4325#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4326 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4327
4328 if (!pPdpt->a[iPdpt].n.u1Present)
4329 return NULL;
4330
4331 /* Fetch the pgm pool shadow descriptor. */
4332 PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4333 AssertReturn(pShwPde, NULL);
4334
4335 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4336#else
4337 AssertFailed();
4338 return NULL;
4339#endif
4340}
4341
4342
4343/**
4344 * Gets the shadow page directory entry, PAE.
4345 *
4346 * @returns PDE.
4347 * @param pPGM Pointer to the PGM instance data.
4348 * @param GCPtr The address.
4349 */
4350DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4351{
4352 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4353
4354 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4355 if (!pShwPde)
4356 {
4357 X86PDEPAE ZeroPde = {0};
4358 return ZeroPde;
4359 }
4360 return pShwPde->a[iPd];
4361}
4362
4363
4364/**
4365 * Gets the pointer to the shadow page directory entry for an address, PAE.
4366 *
4367 * @returns Pointer to the PDE.
4368 * @param pPGM Pointer to the PGM instance data.
4369 * @param GCPtr The address.
4370 */
4371DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4372{
4373 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4374
4375 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4376 AssertReturn(pPde, NULL);
4377 return &pPde->a[iPd];
4378}
4379
4380#ifndef IN_RC
4381
4382/**
4383 * Gets the shadow page map level-4 pointer.
4384 *
4385 * @returns Pointer to the shadow PML4.
4386 * @param pPGM Pointer to the PGM instance data.
4387 */
4388DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4389{
4390#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4391 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4392#else
4393# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4394 PX86PML4 pShwPml4;
4395 Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
4396 int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
4397 AssertRCReturn(rc, 0);
4398 return pShwPml4;
4399# else
4400 Assert(pPGM->CTX_SUFF(pShwRoot));
4401 return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
4402# endif
4403#endif
4404}
4405
4406
4407/**
4408 * Gets the shadow page map level-4 entry for the specified address.
4409 *
4410 * @returns The entry.
4411 * @param pPGM Pointer to the PGM instance data.
4412 * @param GCPtr The address.
4413 */
4414DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4415{
4416 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4417 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4418
4419 if (!pShwPml4)
4420 {
4421 X86PML4E ZeroPml4e = {0};
4422 return ZeroPml4e;
4423 }
4424 return pShwPml4->a[iPml4];
4425}
4426
4427
4428/**
4429 * Gets the pointer to the specified shadow page map level-4 entry.
4430 *
4431 * @returns The entry.
4432 * @param pPGM Pointer to the PGM instance data.
4433 * @param iPml4 The PML4 index.
4434 */
4435DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4436{
4437 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4438 if (!pShwPml4)
4439 return NULL;
4440 return &pShwPml4->a[iPml4];
4441}
4442
4443
4444/**
4445 * Gets the GUEST page directory pointer for the specified address.
4446 *
4447 * @returns The page directory in question.
4448 * @returns NULL if the page directory is not present or on an invalid page.
4449 * @param pPGM Pointer to the PGM instance data.
4450 * @param GCPtr The address.
4451 * @param piPD Receives the index into the returned page directory
4452 */
4453DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4454{
4455 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4456 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4457 if (pGuestPml4->a[iPml4].n.u1Present)
4458 {
4459 PCX86PDPT pPdptTemp;
4460 int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4461 AssertRCReturn(rc, NULL);
4462
4463 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4464 if (pPdptTemp->a[iPdPt].n.u1Present)
4465 {
4466 PX86PDPAE pPD;
4467 rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4468 AssertRCReturn(rc, NULL);
4469
4470 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4471 return pPD;
4472 }
4473 }
4474 return NULL;
4475}
4476
4477#endif /* !IN_RC */
4478
4479/**
4480 * Gets the page state for a physical handler.
4481 *
4482 * @returns The physical handler page state.
4483 * @param pCur The physical handler in question.
4484 */
4485DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4486{
4487 switch (pCur->enmType)
4488 {
4489 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4490 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4491
4492 case PGMPHYSHANDLERTYPE_MMIO:
4493 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4494 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4495
4496 default:
4497 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4498 }
4499}
4500
4501
4502/**
4503 * Gets the page state for a virtual handler.
4504 *
4505 * @returns The virtual handler page state.
4506 * @param pCur The virtual handler in question.
4507 * @remarks This should never be used on a hypervisor access handler.
4508 */
4509DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4510{
4511 switch (pCur->enmType)
4512 {
4513 case PGMVIRTHANDLERTYPE_WRITE:
4514 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4515 case PGMVIRTHANDLERTYPE_ALL:
4516 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4517 default:
4518 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4519 }
4520}
4521
4522
4523/**
4524 * Clears one physical page of a virtual handler
4525 *
4526 * @param pPGM Pointer to the PGM instance.
4527 * @param pCur Virtual handler structure
4528 * @param iPage Physical page index
4529 *
4530 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4531 * need to care about other handlers in the same page.
4532 */
4533DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4534{
4535 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4536
4537 /*
4538 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4539 */
4540#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4541 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4542 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4543 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4544#endif
4545 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4546 {
4547 /* We're the head of the alias chain. */
4548 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4549#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4550 AssertReleaseMsg(pRemove != NULL,
4551 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4552 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4553 AssertReleaseMsg(pRemove == pPhys2Virt,
4554 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4555 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4556 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4557 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4558#endif
4559 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4560 {
4561 /* Insert the next list in the alias chain into the tree. */
4562 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4563#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4564 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4565 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4566 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4567#endif
4568 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4569 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4570 AssertRelease(fRc);
4571 }
4572 }
4573 else
4574 {
4575 /* Locate the previous node in the alias chain. */
4576 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4577#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4578 AssertReleaseMsg(pPrev != pPhys2Virt,
4579 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4580 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4581#endif
4582 for (;;)
4583 {
4584 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4585 if (pNext == pPhys2Virt)
4586 {
4587 /* unlink. */
4588 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4589 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4590 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4591 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4592 else
4593 {
4594 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4595 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4596 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4597 }
4598 break;
4599 }
4600
4601 /* next */
4602 if (pNext == pPrev)
4603 {
4604#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4605 AssertReleaseMsg(pNext != pPrev,
4606 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4607 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4608#endif
4609 break;
4610 }
4611 pPrev = pNext;
4612 }
4613 }
4614 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4615 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4616 pPhys2Virt->offNextAlias = 0;
4617 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4618
4619 /*
4620 * Clear the ram flags for this page.
4621 */
4622 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4623 AssertReturnVoid(pPage);
4624 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4625}
4626
4627
4628/**
4629 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4630 *
4631 * @returns Pointer to the shadow page structure.
4632 * @param pPool The pool.
4633 * @param HCPhys The HC physical address of the shadow page.
4634 */
4635DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4636{
4637 /*
4638 * Look up the page.
4639 */
4640 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4641 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4642 return pPage;
4643}
4644
4645
4646/**
4647 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4648 *
4649 * @returns Pointer to the shadow page structure.
4650 * @param pPool The pool.
4651 * @param idx The pool page index.
4652 */
4653DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4654{
4655 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4656 return &pPool->aPages[idx];
4657}
4658
4659
4660#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4661/**
4662 * Clear references to guest physical memory.
4663 *
4664 * @param pPool The pool.
4665 * @param pPoolPage The pool page.
4666 * @param pPhysPage The physical guest page tracking structure.
4667 */
4668DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4669{
4670 /*
4671 * Just deal with the simple case here.
4672 */
4673# ifdef LOG_ENABLED
4674 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4675# endif
4676 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4677 if (cRefs == 1)
4678 {
4679 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4680 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4681 }
4682 else
4683 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4684 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4685}
4686#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4687
4688
4689#ifdef PGMPOOL_WITH_CACHE
4690/**
4691 * Moves the page to the head of the age list.
4692 *
4693 * This is done when the cached page is used in one way or another.
4694 *
4695 * @param pPool The pool.
4696 * @param pPage The cached page.
4697 * @todo inline in PGMInternal.h!
4698 */
4699DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4700{
4701 /*
4702 * Move to the head of the age list.
4703 */
4704 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4705 {
4706 /* unlink */
4707 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4708 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4709 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4710 else
4711 pPool->iAgeTail = pPage->iAgePrev;
4712
4713 /* insert at head */
4714 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4715 pPage->iAgeNext = pPool->iAgeHead;
4716 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4717 pPool->iAgeHead = pPage->idx;
4718 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4719 }
4720}
4721#endif /* PGMPOOL_WITH_CACHE */
4722
4723#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4724
4725/**
4726 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4727 *
4728 * @returns VBox status code.
4729 * @param pVM VM Handle.
4730 * @param pPage PGM pool page
4731 */
4732DECLINLINE(int) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4733{
4734 Assert(!pPage->fLocked);
4735 pPage->fLocked = true;
4736 return VINF_SUCCESS;
4737}
4738
4739
4740/**
4741 * Unlocks a page to allow flushing again
4742 *
4743 * @returns VBox status code.
4744 * @param pVM VM Handle.
4745 * @param pPage PGM pool page
4746 */
4747DECLINLINE(int) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4748{
4749 Assert(pPage->fLocked);
4750 pPage->fLocked = false;
4751 return VINF_SUCCESS;
4752}
4753
4754
4755/**
4756 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4757 *
4758 * @returns VBox status code.
4759 * @param pPage PGM pool page
4760 */
4761DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4762{
4763 if (pPage->fLocked)
4764 {
4765 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4766 if (pPage->cModifications)
4767 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4768 return true;
4769 }
4770 return false;
4771}
4772
4773#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
4774
4775/**
4776 * Tells if mappings are to be put into the shadow page table or not
4777 *
4778 * @returns boolean result
4779 * @param pVM VM handle.
4780 */
4781DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4782{
4783#ifdef IN_RING0
4784 /* There are no mappings in VT-x and AMD-V mode. */
4785 Assert(pPGM->fDisableMappings);
4786 return false;
4787#else
4788 return !pPGM->fDisableMappings;
4789#endif
4790}
4791
4792/** @} */
4793
4794#endif
4795
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