PGMInternal.h@ 13373

Last change on this file since 13373 was 13236, checked in by vboxsync, 16 years ago
#1865: More polish.
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1	/* $Id: PGMInternal.h 13236 2008-10-13 21:25:50Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/assert.h>
41	#include <iprt/critsect.h>
42
43
44
45	/** @defgroup grp_pgm_int Internals
46	* @ingroup grp_pgm
47	* @internal
48	* @{
49	*/
50
51
52	/** @name PGM Compile Time Config
53	* @{
54	*/
55
56	/**
57	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58	* Comment it if it will break something.
59	*/
60	#define PGM_OUT_OF_SYNC_IN_GC
61
62	/**
63	* Check and skip global PDEs for non-global flushes
64	*/
65	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67	/**
68	* Sync N pages instead of a whole page table
69	*/
70	#define PGM_SYNC_N_PAGES
71
72	/**
73	* Number of pages to sync during a page fault
74	*
75	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77	*/
78	#define PGM_SYNC_NR_PAGES 8
79
80	/**
81	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82	*/
83	#define PGM_MAX_PHYSCACHE_ENTRIES 64
84	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86	/**
87	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88	*/
89	#define PGM_PHYSMEMACCESS_CACHING
90
91	/** @def PGMPOOL_WITH_CACHE
92	* Enable agressive caching using the page pool.
93	*
94	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95	*/
96	#define PGMPOOL_WITH_CACHE
97
98	/** @def PGMPOOL_WITH_MIXED_PT_CR3
99	* When defined, we'll deal with 'uncachable' pages.
100	*/
101	#ifdef PGMPOOL_WITH_CACHE
102	# define PGMPOOL_WITH_MIXED_PT_CR3
103	#endif
104
105	/** @def PGMPOOL_WITH_MONITORING
106	* Monitor the guest pages which are shadowed.
107	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108	* be enabled as well.
109	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110	*/
111	#ifdef PGMPOOL_WITH_CACHE
112	# define PGMPOOL_WITH_MONITORING
113	#endif
114
115	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116	* Tracking the of shadow pages mapping guest physical pages.
117	*
118	* This is very expensive, the current cache prototype is trying to figure out
119	* whether it will be acceptable with an agressive caching policy.
120	*/
121	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
122	# define PGMPOOL_WITH_GCPHYS_TRACKING
123	#endif
124
125	/** @def PGMPOOL_WITH_USER_TRACKING
126	* Tracking users of shadow pages. This is required for the linking of shadow page
127	* tables and physical guest addresses.
128	*/
129	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
130	# define PGMPOOL_WITH_USER_TRACKING
131	#endif
132
133	/** @def PGMPOOL_CFG_MAX_GROW
134	* The maximum number of pages to add to the pool in one go.
135	*/
136	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
140	*/
141	#ifdef VBOX_STRICT
142	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143	#endif
144	/** @} */
145
146
147	/** @name PDPT and PML4 flags.
148	* These are placed in the three bits available for system programs in
149	* the PDPT and PML4 entries.
150	* @{ */
151	/** The entry is a permanent one and it's must always be present.
152	* Never free such an entry. */
153	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154	/** Mapping (hypervisor allocated pagetable). */
155	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
156	/** @} */
157
158	/** @name Page directory flags.
159	* These are placed in the three bits available for system programs in
160	* the page directory entries.
161	* @{ */
162	/** Mapping (hypervisor allocated pagetable). */
163	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
164	/** Made read-only to facilitate dirty bit tracking. */
165	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
166	/** @} */
167
168	/** @name Page flags.
169	* These are placed in the three bits available for system programs in
170	* the page entries.
171	* @{ */
172	/** Made read-only to facilitate dirty bit tracking. */
173	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
174
175	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
176	/** Scanned and approved by CSAM (tm).
177	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
178	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
179	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
180	#endif
181	/** @} */
182
183	/** @name Defines used to indicate the shadow and guest paging in the templates.
184	* @{ */
185	#define PGM_TYPE_REAL 1
186	#define PGM_TYPE_PROT 2
187	#define PGM_TYPE_32BIT 3
188	#define PGM_TYPE_PAE 4
189	#define PGM_TYPE_AMD64 5
190	#define PGM_TYPE_NESTED 6
191	#define PGM_TYPE_EPT 7
192	#define PGM_TYPE_MAX PGM_TYPE_EPT
193	/** @} */
194
195	/** Macro for checking if the guest is using paging.
196	* @param uGstType PGM_TYPE_*
197	* @param uShwType PGM_TYPE_*
198	* @remark ASSUMES certain order of the PGM_TYPE_* values.
199	*/
200	#define PGM_WITH_PAGING(uGstType, uShwType) \
201	( (uGstType) >= PGM_TYPE_32BIT \
202	&& (uShwType) != PGM_TYPE_NESTED \
203	&& (uShwType) != PGM_TYPE_EPT)
204
205	/** Macro for checking if the guest supports the NX bit.
206	* @param uGstType PGM_TYPE_*
207	* @param uShwType PGM_TYPE_*
208	* @remark ASSUMES certain order of the PGM_TYPE_* values.
209	*/
210	#define PGM_WITH_NX(uGstType, uShwType) \
211	( (uGstType) >= PGM_TYPE_PAE \
212	&& (uShwType) != PGM_TYPE_NESTED \
213	&& (uShwType) != PGM_TYPE_EPT)
214
215
216	/** @def PGM_HCPHYS_2_PTR
217	* Maps a HC physical page pool address to a virtual address.
218	*
219	* @returns VBox status code.
220	* @param pVM The VM handle.
221	* @param HCPhys The HC physical address to map to a virtual one.
222	* @param ppv Where to store the virtual address. No need to cast this.
223	*
224	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
225	* small page window employeed by that function. Be careful.
226	* @remark There is no need to assert on the result.
227	*/
228	#if defined(IN_GC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
229	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
230	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
231	#else
232	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
233	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
234	#endif
235
236	/** @def PGM_GCPHYS_2_PTR
237	* Maps a GC physical page address to a virtual address.
238	*
239	* @returns VBox status code.
240	* @param pVM The VM handle.
241	* @param GCPhys The GC physical address to map to a virtual one.
242	* @param ppv Where to store the virtual address. No need to cast this.
243	*
244	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
245	* small page window employeed by that function. Be careful.
246	* @remark There is no need to assert on the result.
247	*/
248	#if defined(IN_GC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
249	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
250	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
251	#else
252	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
253	PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only /, (void )(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
254	#endif
255
256	/** @def PGM_GCPHYS_2_PTR_EX
257	* Maps a unaligned GC physical page address to a virtual address.
258	*
259	* @returns VBox status code.
260	* @param pVM The VM handle.
261	* @param GCPhys The GC physical address to map to a virtual one.
262	* @param ppv Where to store the virtual address. No need to cast this.
263	*
264	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
265	* small page window employeed by that function. Be careful.
266	* @remark There is no need to assert on the result.
267	*/
268	#if defined(IN_GC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
269	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
270	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
271	#else
272	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
273	PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only /, (void )(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
274	#endif
275
276	/** @def PGM_INVL_PG
277	* Invalidates a page when in GC does nothing in HC.
278	*
279	* @param GCVirt The virtual address of the page to invalidate.
280	*/
281	#ifdef IN_GC
282	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
283	#elif defined(IN_RING0)
284	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
285	#else
286	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
287	#endif
288
289	/** @def PGM_INVL_BIG_PG
290	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
291	*
292	* @param GCVirt The virtual address within the page directory to invalidate.
293	*/
294	#ifdef IN_GC
295	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
296	#elif defined(IN_RING0)
297	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
298	#else
299	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
300	#endif
301
302	/** @def PGM_INVL_GUEST_TLBS()
303	* Invalidates all guest TLBs.
304	*/
305	#ifdef IN_GC
306	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
307	#elif defined(IN_RING0)
308	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
309	#else
310	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
311	#endif
312
313
314	/**
315	* Structure for tracking GC Mappings.
316	*
317	* This structure is used by linked list in both GC and HC.
318	*/
319	typedef struct PGMMAPPING
320	{
321	/** Pointer to next entry. */
322	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
323	/** Pointer to next entry. */
324	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
325	/** Pointer to next entry. */
326	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
327	#if GC_ARCH_BITS == 64
328	RTRCPTR padding0;
329	#endif
330	/** Start Virtual address. */
331	RTGCUINTPTR GCPtr;
332	/** Last Virtual address (inclusive). */
333	RTGCUINTPTR GCPtrLast;
334	/** Range size (bytes). */
335	RTGCUINTPTR cb;
336	/** Pointer to relocation callback function. */
337	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
338	/** User argument to the callback. */
339	R3PTRTYPE(void *) pvUser;
340	/** Mapping description / name. For easing debugging. */
341	R3PTRTYPE(const char *) pszDesc;
342	/** Number of page tables. */
343	RTUINT cPTs;
344	#if HC_ARCH_BITS != GC_ARCH_BITS \|\| GC_ARCH_BITS == 64
345	RTUINT uPadding1; /*< Alignment padding. /
346	#endif
347	/** Array of page table mapping data. Each entry
348	* describes one page table. The array can be longer
349	* than the declared length.
350	*/
351	struct
352	{
353	/** The HC physical address of the page table. */
354	RTHCPHYS HCPhysPT;
355	/** The HC physical address of the first PAE page table. */
356	RTHCPHYS HCPhysPaePT0;
357	/** The HC physical address of the second PAE page table. */
358	RTHCPHYS HCPhysPaePT1;
359	/** The HC virtual address of the 32-bit page table. */
360	R3PTRTYPE(PX86PT) pPTR3;
361	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
362	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
363	/** The GC virtual address of the 32-bit page table. */
364	RCPTRTYPE(PX86PT) pPTRC;
365	/** The GC virtual address of the two PAE page table. */
366	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
367	/** The GC virtual address of the 32-bit page table. */
368	R0PTRTYPE(PX86PT) pPTR0;
369	/** The GC virtual address of the two PAE page table. */
370	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
371	} aPTs[1];
372	} PGMMAPPING;
373	/** Pointer to structure for tracking GC Mappings. */
374	typedef struct PGMMAPPING *PPGMMAPPING;
375
376
377	/**
378	* Physical page access handler structure.
379	*
380	* This is used to keep track of physical address ranges
381	* which are being monitored in some kind of way.
382	*/
383	typedef struct PGMPHYSHANDLER
384	{
385	AVLROGCPHYSNODECORE Core;
386	/** Access type. */
387	PGMPHYSHANDLERTYPE enmType;
388	/** Number of pages to update. */
389	uint32_t cPages;
390	/** Pointer to R3 callback function. */
391	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
392	/** User argument for R3 handlers. */
393	R3PTRTYPE(void *) pvUserR3;
394	/** Pointer to R0 callback function. */
395	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
396	/** User argument for R0 handlers. */
397	R0PTRTYPE(void *) pvUserR0;
398	/** Pointer to GC callback function. */
399	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
400	/** User argument for RC handlers. */
401	RCPTRTYPE(void *) pvUserRC;
402	/** Description / Name. For easing debugging. */
403	R3PTRTYPE(const char *) pszDesc;
404	#ifdef VBOX_WITH_STATISTICS
405	/** Profiling of this handler. */
406	STAMPROFILE Stat;
407	#endif
408	} PGMPHYSHANDLER;
409	/** Pointer to a physical page access handler structure. */
410	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
411
412
413	/**
414	* Cache node for the physical addresses covered by a virtual handler.
415	*/
416	typedef struct PGMPHYS2VIRTHANDLER
417	{
418	/** Core node for the tree based on physical ranges. */
419	AVLROGCPHYSNODECORE Core;
420	/** Offset from this struct to the PGMVIRTHANDLER structure. */
421	int32_t offVirtHandler;
422	/** Offset of the next alias relative to this one.
423	* Bit 0 is used for indicating whether we're in the tree.
424	* Bit 1 is used for indicating that we're the head node.
425	*/
426	int32_t offNextAlias;
427	} PGMPHYS2VIRTHANDLER;
428	/** Pointer to a phys to virtual handler structure. */
429	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
430
431	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
432	* node is in the tree. */
433	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
434	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
435	* node is in the head of an alias chain.
436	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
437	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
438	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
439	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
440
441
442	/**
443	* Virtual page access handler structure.
444	*
445	* This is used to keep track of virtual address ranges
446	* which are being monitored in some kind of way.
447	*/
448	typedef struct PGMVIRTHANDLER
449	{
450	/** Core node for the tree based on virtual ranges. */
451	AVLROGCPTRNODECORE Core;
452	/** Size of the range (in bytes). */
453	RTGCUINTPTR cb;
454	/** Number of cache pages. */
455	uint32_t cPages;
456	/** Access type. */
457	PGMVIRTHANDLERTYPE enmType;
458	/** Pointer to the RC callback function. */
459	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
460	#if HC_ARCH_BITS == 64
461	RTRCPTR padding;
462	#endif
463	/** Pointer to the R3 callback function for invalidation. */
464	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
465	/** Pointer to the R3 callback function. */
466	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
467	/** Description / Name. For easing debugging. */
468	R3PTRTYPE(const char *) pszDesc;
469	#ifdef VBOX_WITH_STATISTICS
470	/** Profiling of this handler. */
471	STAMPROFILE Stat;
472	#endif
473	/** Array of cached physical addresses for the monitored ranged. */
474	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
475	} PGMVIRTHANDLER;
476	/** Pointer to a virtual page access handler structure. */
477	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
478
479
480	/**
481	* Page type.
482	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
483	* @todo convert to \#defines.
484	*/
485	typedef enum PGMPAGETYPE
486	{
487	/** The usual invalid zero entry. */
488	PGMPAGETYPE_INVALID = 0,
489	/** RAM page. (RWX) */
490	PGMPAGETYPE_RAM,
491	/** MMIO2 page. (RWX) */
492	PGMPAGETYPE_MMIO2,
493	/** Shadowed ROM. (RWX) */
494	PGMPAGETYPE_ROM_SHADOW,
495	/** ROM page. (R-X) */
496	PGMPAGETYPE_ROM,
497	/** MMIO page. (---) */
498	PGMPAGETYPE_MMIO,
499	/** End of valid entries. */
500	PGMPAGETYPE_END
501	} PGMPAGETYPE;
502	AssertCompile(PGMPAGETYPE_END < 7);
503
504	/** @name Page type predicates.
505	* @{ */
506	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
507	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
508	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
509	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
510	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
511	/** @} */
512
513
514	/**
515	* A Physical Guest Page tracking structure.
516	*
517	* The format of this structure is complicated because we have to fit a lot
518	* of information into as few bits as possible. The format is also subject
519	* to change (there is one comming up soon). Which means that for we'll be
520	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
521	* accessess to the structure.
522	*/
523	typedef struct PGMPAGE
524	{
525	/** The physical address and a whole lot of other stuff. All bits are used! */
526	RTHCPHYS HCPhys;
527	/** The page state. */
528	uint32_t u2StateX : 2;
529	/** Flag indicating that a write monitored page was written to when set. */
530	uint32_t fWrittenToX : 1;
531	/** For later. */
532	uint32_t fSomethingElse : 1;
533	/** The Page ID.
534	* @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
535	* The HCPhys will be 100% static. */
536	uint32_t idPageX : 28;
537	/** The page type (PGMPAGETYPE). */
538	uint32_t u3Type : 3;
539	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
540	uint32_t u2HandlerPhysStateX : 2;
541	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
542	uint32_t u2HandlerVirtStateX : 2;
543	uint32_t u29B : 25;
544	} PGMPAGE;
545	AssertCompileSize(PGMPAGE, 16);
546	/** Pointer to a physical guest page. */
547	typedef PGMPAGE *PPGMPAGE;
548	/** Pointer to a const physical guest page. */
549	typedef const PGMPAGE *PCPGMPAGE;
550	/** Pointer to a physical guest page pointer. */
551	typedef PPGMPAGE *PPPGMPAGE;
552
553
554	/**
555	* Clears the page structure.
556	* @param pPage Pointer to the physical guest page tracking structure.
557	*/
558	#define PGM_PAGE_CLEAR(pPage) \
559	do { \
560	(pPage)->HCPhys = 0; \
561	(pPage)->u2StateX = 0; \
562	(pPage)->fWrittenToX = 0; \
563	(pPage)->fSomethingElse = 0; \
564	(pPage)->idPageX = 0; \
565	(pPage)->u3Type = 0; \
566	(pPage)->u29B = 0; \
567	} while (0)
568
569	/**
570	* Initializes the page structure.
571	* @param pPage Pointer to the physical guest page tracking structure.
572	*/
573	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
574	do { \
575	(pPage)->HCPhys = (_HCPhys); \
576	(pPage)->u2StateX = (_uState); \
577	(pPage)->fWrittenToX = 0; \
578	(pPage)->fSomethingElse = 0; \
579	(pPage)->idPageX = (_idPage); \
580	/(pPage)->u3Type = (_uType); - later / \
581	PGM_PAGE_SET_TYPE(pPage, _uType); \
582	(pPage)->u29B = 0; \
583	} while (0)
584
585	/**
586	* Initializes the page structure of a ZERO page.
587	* @param pPage Pointer to the physical guest page tracking structure.
588	*/
589	#ifdef VBOX_WITH_NEW_PHYS_CODE
590	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
591	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
592	#else
593	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
594	PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
595	#endif
596	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
597	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
598	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
599
600
601	/** @name The Page state, PGMPAGE::u2StateX.
602	* @{ */
603	/** The zero page.
604	* This is a per-VM page that's never ever mapped writable. */
605	#define PGM_PAGE_STATE_ZERO 0
606	/** A allocated page.
607	* This is a per-VM page allocated from the page pool (or wherever
608	* we get MMIO2 pages from if the type is MMIO2).
609	*/
610	#define PGM_PAGE_STATE_ALLOCATED 1
611	/** A allocated page that's being monitored for writes.
612	* The shadow page table mappings are read-only. When a write occurs, the
613	* fWrittenTo member is set, the page remapped as read-write and the state
614	* moved back to allocated. */
615	#define PGM_PAGE_STATE_WRITE_MONITORED 2
616	/** The page is shared, aka. copy-on-write.
617	* This is a page that's shared with other VMs. */
618	#define PGM_PAGE_STATE_SHARED 3
619	/** @} */
620
621
622	/**
623	* Gets the page state.
624	* @returns page state (PGM_PAGE_STATE_*).
625	* @param pPage Pointer to the physical guest page tracking structure.
626	*/
627	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
628
629	/**
630	* Sets the page state.
631	* @param pPage Pointer to the physical guest page tracking structure.
632	* @param _uState The new page state.
633	*/
634	#define PGM_PAGE_SET_STATE(pPage, _uState) \
635	do { (pPage)->u2StateX = (_uState); } while (0)
636
637
638	/**
639	* Gets the host physical address of the guest page.
640	* @returns host physical address (RTHCPHYS).
641	* @param pPage Pointer to the physical guest page tracking structure.
642	*/
643	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
644
645	/**
646	* Sets the host physical address of the guest page.
647	* @param pPage Pointer to the physical guest page tracking structure.
648	* @param _HCPhys The new host physical address.
649	*/
650	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
651	do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
652	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
653
654	/**
655	* Get the Page ID.
656	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
657	* @param pPage Pointer to the physical guest page tracking structure.
658	*/
659	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
660	/* later:
661	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
662	\| ((uint32_t)(pPage)->HCPhys & 0xfff) )
663	*/
664	/**
665	* Sets the Page ID.
666	* @param pPage Pointer to the physical guest page tracking structure.
667	*/
668	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
669	/* later:
670	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
671	\| ((_idPage) & 0xfff) \
672	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
673	*/
674
675	/**
676	* Get the Chunk ID.
677	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
678	* @param pPage Pointer to the physical guest page tracking structure.
679	*/
680	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
681	/* later:
682	#if GMM_CHUNKID_SHIFT == 12
683	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
684	#elif GMM_CHUNKID_SHIFT > 12
685	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
686	#elif GMM_CHUNKID_SHIFT < 12
687	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
688	\| ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
689	#else
690	# error "GMM_CHUNKID_SHIFT isn't defined or something."
691	#endif
692	*/
693
694	/**
695	* Get the index of the page within the allocaiton chunk.
696	* @returns The page index.
697	* @param pPage Pointer to the physical guest page tracking structure.
698	*/
699	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
700	/* later:
701	#if GMM_CHUNKID_SHIFT <= 12
702	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
703	#else
704	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
705	\| ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
706	#endif
707	*/
708
709
710	/**
711	* Gets the page type.
712	* @returns The page type.
713	* @param pPage Pointer to the physical guest page tracking structure.
714	*/
715	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
716
717	/**
718	* Sets the page type.
719	* @param pPage Pointer to the physical guest page tracking structure.
720	* @param _enmType The new page type (PGMPAGETYPE).
721	*/
722	#ifdef VBOX_WITH_NEW_PHYS_CODE
723	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
724	do { (pPage)->u3Type = (_enmType); } while (0)
725	#else
726	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
727	do { \
728	(pPage)->u3Type = (_enmType); \
729	if ((_enmType) == PGMPAGETYPE_ROM) \
730	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM; \
731	else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
732	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2; \
733	else if ((_enmType) == PGMPAGETYPE_MMIO2) \
734	(pPage)->HCPhys \|= MM_RAM_FLAGS_MMIO2; \
735	} while (0)
736	#endif
737
738
739	/**
740	* Checks if the page is 'reserved'.
741	* @returns true/false.
742	* @param pPage Pointer to the physical guest page tracking structure.
743	*/
744	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
745
746	/**
747	* Checks if the page is marked for MMIO.
748	* @returns true/false.
749	* @param pPage Pointer to the physical guest page tracking structure.
750	*/
751	#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
752
753	/**
754	* Checks if the page is backed by the ZERO page.
755	* @returns true/false.
756	* @param pPage Pointer to the physical guest page tracking structure.
757	*/
758	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
759
760	/**
761	* Checks if the page is backed by a SHARED page.
762	* @returns true/false.
763	* @param pPage Pointer to the physical guest page tracking structure.
764	*/
765	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
766
767
768	/**
769	* Marks the paget as written to (for GMM change monitoring).
770	* @param pPage Pointer to the physical guest page tracking structure.
771	*/
772	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
773
774	/**
775	* Clears the written-to indicator.
776	* @param pPage Pointer to the physical guest page tracking structure.
777	*/
778	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
779
780	/**
781	* Checks if the page was marked as written-to.
782	* @returns true/false.
783	* @param pPage Pointer to the physical guest page tracking structure.
784	*/
785	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
786
787
788	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
789	*
790	* @remarks The values are assigned in order of priority, so we can calculate
791	* the correct state for a page with different handlers installed.
792	* @{ */
793	/** No handler installed. */
794	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
795	/** Monitoring is temporarily disabled. */
796	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
797	/** Write access is monitored. */
798	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
799	/** All access is monitored. */
800	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
801	/** @} */
802
803	/**
804	* Gets the physical access handler state of a page.
805	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
806	* @param pPage Pointer to the physical guest page tracking structure.
807	*/
808	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
809
810	/**
811	* Sets the physical access handler state of a page.
812	* @param pPage Pointer to the physical guest page tracking structure.
813	* @param _uState The new state value.
814	*/
815	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
816	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
817
818	/**
819	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
820	* @returns true/false
821	* @param pPage Pointer to the physical guest page tracking structure.
822	*/
823	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
824
825	/**
826	* Checks if the page has any active physical access handlers.
827	* @returns true/false
828	* @param pPage Pointer to the physical guest page tracking structure.
829	*/
830	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
831
832
833	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
834	*
835	* @remarks The values are assigned in order of priority, so we can calculate
836	* the correct state for a page with different handlers installed.
837	* @{ */
838	/** No handler installed. */
839	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
840	/* 1 is reserved so the lineup is identical with the physical ones. */
841	/** Write access is monitored. */
842	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
843	/** All access is monitored. */
844	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
845	/** @} */
846
847	/**
848	* Gets the virtual access handler state of a page.
849	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
850	* @param pPage Pointer to the physical guest page tracking structure.
851	*/
852	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
853
854	/**
855	* Sets the virtual access handler state of a page.
856	* @param pPage Pointer to the physical guest page tracking structure.
857	* @param _uState The new state value.
858	*/
859	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
860	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
861
862	/**
863	* Checks if the page has any virtual access handlers.
864	* @returns true/false
865	* @param pPage Pointer to the physical guest page tracking structure.
866	*/
867	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
868
869	/**
870	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
871	* virtual handlers.
872	* @returns true/false
873	* @param pPage Pointer to the physical guest page tracking structure.
874	*/
875	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
876
877
878
879	/**
880	* Checks if the page has any access handlers, including temporarily disabled ones.
881	* @returns true/false
882	* @param pPage Pointer to the physical guest page tracking structure.
883	*/
884	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
885	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
886	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
887
888	/**
889	* Checks if the page has any active access handlers.
890	* @returns true/false
891	* @param pPage Pointer to the physical guest page tracking structure.
892	*/
893	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
894	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
895	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
896
897	/**
898	* Checks if the page has any active access handlers catching all accesses.
899	* @returns true/false
900	* @param pPage Pointer to the physical guest page tracking structure.
901	*/
902	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
903	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
904	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
905
906
907	/**
908	* Ram range for GC Phys to HC Phys conversion.
909	*
910	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
911	* conversions too, but we'll let MM handle that for now.
912	*
913	* This structure is used by linked lists in both GC and HC.
914	*/
915	typedef struct PGMRAMRANGE
916	{
917	/** Pointer to the next RAM range - for R3. */
918	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
919	/** Pointer to the next RAM range - for R0. */
920	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
921	/** Pointer to the next RAM range - for RC. */
922	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
923	/** Pointer alignment. */
924	RTRCPTR RCPtrAlignment;
925	/** Start of the range. Page aligned. */
926	RTGCPHYS GCPhys;
927	/** Last address in the range (inclusive). Page aligned (-1). */
928	RTGCPHYS GCPhysLast;
929	/** Size of the range. (Page aligned of course). */
930	RTGCPHYS cb;
931	/** MM_RAM_* flags */
932	uint32_t fFlags;
933	uint32_t u32Alignment; /*< alignment. /
934	#ifndef VBOX_WITH_NEW_PHYS_CODE
935	/** R3 virtual lookup ranges for chunks.
936	* Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
937	* @remarks This is occationally accessed from ring-0!! (not darwin) */
938	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
939	R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
940	# else
941	R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
942	# endif
943	#endif
944	/** Start of the HC mapping of the range. This is only used for MMIO2. */
945	R3PTRTYPE(void *) pvR3;
946	/** The range description. */
947	R3PTRTYPE(const char *) pszDesc;
948
949	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
950	#ifdef VBOX_WITH_NEW_PHYS_CODE
951	uint32_t au32Reserved[2];
952	#elif HC_ARCH_BITS == 32
953	uint32_t au32Reserved[1];
954	#endif
955
956	/** Array of physical guest page tracking structures. */
957	PGMPAGE aPages[1];
958	} PGMRAMRANGE;
959	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
960	typedef PGMRAMRANGE *PPGMRAMRANGE;
961
962	/** Return hc ptr corresponding to the ram range and physical offset */
963	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
964	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
965	: (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
966
967	/**
968	* Per page tracking structure for ROM image.
969	*
970	* A ROM image may have a shadow page, in which case we may have
971	* two pages backing it. This structure contains the PGMPAGE for
972	* both while PGMRAMRANGE have a copy of the active one. It is
973	* important that these aren't out of sync in any regard other
974	* than page pool tracking data.
975	*/
976	typedef struct PGMROMPAGE
977	{
978	/** The page structure for the virgin ROM page. */
979	PGMPAGE Virgin;
980	/** The page structure for the shadow RAM page. */
981	PGMPAGE Shadow;
982	/** The current protection setting. */
983	PGMROMPROT enmProt;
984	/** Pad the structure size to a multiple of 8. */
985	uint32_t u32Padding;
986	} PGMROMPAGE;
987	/** Pointer to a ROM page tracking structure. */
988	typedef PGMROMPAGE *PPGMROMPAGE;
989
990
991	/**
992	* A registered ROM image.
993	*
994	* This is needed to keep track of ROM image since they generally
995	* intrude into a PGMRAMRANGE. It also keeps track of additional
996	* info like the two page sets (read-only virgin and read-write shadow),
997	* the current state of each page.
998	*
999	* Because access handlers cannot easily be executed in a different
1000	* context, the ROM ranges needs to be accessible and in all contexts.
1001	*/
1002	typedef struct PGMROMRANGE
1003	{
1004	/** Pointer to the next range - R3. */
1005	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1006	/** Pointer to the next range - R0. */
1007	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1008	/** Pointer to the next range - RC. */
1009	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1010	/** Pointer alignment */
1011	RTRCPTR GCPtrAlignment;
1012	/** Address of the range. */
1013	RTGCPHYS GCPhys;
1014	/** Address of the last byte in the range. */
1015	RTGCPHYS GCPhysLast;
1016	/** Size of the range. */
1017	RTGCPHYS cb;
1018	/** The flags (PGMPHYS_ROM_FLAG_). /
1019	uint32_t fFlags;
1020	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1021	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1022	/** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1023	* This is used for strictness checks. */
1024	R3PTRTYPE(const void *) pvOriginal;
1025	/** The ROM description. */
1026	R3PTRTYPE(const char *) pszDesc;
1027	/** The per page tracking structures. */
1028	PGMROMPAGE aPages[1];
1029	} PGMROMRANGE;
1030	/** Pointer to a ROM range. */
1031	typedef PGMROMRANGE *PPGMROMRANGE;
1032
1033
1034	/**
1035	* A registered MMIO2 (= Device RAM) range.
1036	*
1037	* There are a few reason why we need to keep track of these
1038	* registrations. One of them is the deregistration & cleanup
1039	* stuff, while another is that the PGMRAMRANGE associated with
1040	* such a region may have to be removed from the ram range list.
1041	*
1042	* Overlapping with a RAM range has to be 100% or none at all. The
1043	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1044	* meditation will be raised if a partial overlap or an overlap of
1045	* ROM pages is encountered. On an overlap we will free all the
1046	* existing RAM pages and put in the ram range pages instead.
1047	*/
1048	typedef struct PGMMMIO2RANGE
1049	{
1050	/** The owner of the range. (a device) */
1051	PPDMDEVINSR3 pDevInsR3;
1052	/** Pointer to the ring-3 mapping of the allocation. */
1053	RTR3PTR pvR3;
1054	/** Pointer to the next range - R3. */
1055	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1056	/** Whether it's mapped or not. */
1057	bool fMapped;
1058	/** Whether it's overlapping or not. */
1059	bool fOverlapping;
1060	/** The PCI region number.
1061	* @remarks This ASSUMES that nobody will ever really need to have multiple
1062	* PCI devices with matching MMIO region numbers on a single device. */
1063	uint8_t iRegion;
1064	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1065	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1066	/** The associated RAM range. */
1067	PGMRAMRANGE RamRange;
1068	} PGMMMIO2RANGE;
1069	/** Pointer to a MMIO2 range. */
1070	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1071
1072
1073
1074
1075	/**
1076	* PGMPhysRead/Write cache entry
1077	*/
1078	typedef struct PGMPHYSCACHEENTRY
1079	{
1080	/** R3 pointer to physical page. */
1081	R3PTRTYPE(uint8_t *) pbR3;
1082	/** GC Physical address for cache entry */
1083	RTGCPHYS GCPhys;
1084	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1085	RTGCPHYS u32Padding0; /*< alignment padding. /
1086	#endif
1087	} PGMPHYSCACHEENTRY;
1088
1089	/**
1090	* PGMPhysRead/Write cache to reduce REM memory access overhead
1091	*/
1092	typedef struct PGMPHYSCACHE
1093	{
1094	/** Bitmap of valid cache entries */
1095	uint64_t aEntries;
1096	/** Cache entries */
1097	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1098	} PGMPHYSCACHE;
1099
1100
1101	/** Pointer to an allocation chunk ring-3 mapping. */
1102	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1103	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1104	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1105
1106	/**
1107	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1108	*
1109	* The primary tree (Core) uses the chunk id as key.
1110	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1111	*/
1112	typedef struct PGMCHUNKR3MAP
1113	{
1114	/** The key is the chunk id. */
1115	AVLU32NODECORE Core;
1116	/** The key is the ageing sequence number. */
1117	AVLLU32NODECORE AgeCore;
1118	/** The current age thingy. */
1119	uint32_t iAge;
1120	/** The current reference count. */
1121	uint32_t volatile cRefs;
1122	/** The current permanent reference count. */
1123	uint32_t volatile cPermRefs;
1124	/** The mapping address. */
1125	void *pv;
1126	} PGMCHUNKR3MAP;
1127
1128	/**
1129	* Allocation chunk ring-3 mapping TLB entry.
1130	*/
1131	typedef struct PGMCHUNKR3MAPTLBE
1132	{
1133	/** The chunk id. */
1134	uint32_t volatile idChunk;
1135	#if HC_ARCH_BITS == 64
1136	uint32_t u32Padding; /*< alignment padding. /
1137	#endif
1138	/** The chunk map. */
1139	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1140	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1141	#else
1142	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1143	#endif
1144	} PGMCHUNKR3MAPTLBE;
1145	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1146	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1147
1148	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1149	* @remark Must be a power of two value. */
1150	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1151
1152	/**
1153	* Allocation chunk ring-3 mapping TLB.
1154	*
1155	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1156	* At first glance this might look kinda odd since AVL trees are
1157	* supposed to give the most optimial lookup times of all trees
1158	* due to their balancing. However, take a tree with 1023 nodes
1159	* in it, that's 10 levels, meaning that most searches has to go
1160	* down 9 levels before they find what they want. This isn't fast
1161	* compared to a TLB hit. There is the factor of cache misses,
1162	* and of course the problem with trees and branch prediction.
1163	* This is why we use TLBs in front of most of the trees.
1164	*
1165	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1166	* difficult when we switch to the new inlined AVL trees (from kStuff).
1167	*/
1168	typedef struct PGMCHUNKR3MAPTLB
1169	{
1170	/** The TLB entries. */
1171	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1172	} PGMCHUNKR3MAPTLB;
1173
1174	/**
1175	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1176	* @returns Chunk TLB index.
1177	* @param idChunk The Chunk ID.
1178	*/
1179	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1180
1181
1182	/**
1183	* Ring-3 guest page mapping TLB entry.
1184	* @remarks used in ring-0 as well at the moment.
1185	*/
1186	typedef struct PGMPAGER3MAPTLBE
1187	{
1188	/** Address of the page. */
1189	RTGCPHYS volatile GCPhys;
1190	/** The guest page. */
1191	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1192	R3PTRTYPE(PPGMPAGE) volatile pPage;
1193	#else
1194	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1195	#endif
1196	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1197	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1198	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1199	#else
1200	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1201	#endif
1202	/** The address */
1203	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1204	R3PTRTYPE(void *) volatile pv;
1205	#else
1206	R3R0PTRTYPE(void *) volatile pv;
1207	#endif
1208	#if HC_ARCH_BITS == 32
1209	uint32_t u32Padding; /*< alignment padding. /
1210	#endif
1211	} PGMPAGER3MAPTLBE;
1212	/** Pointer to an entry in the HC physical TLB. */
1213	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1214
1215
1216	/** The number of entries in the ring-3 guest page mapping TLB.
1217	* @remarks The value must be a power of two. */
1218	#define PGM_PAGER3MAPTLB_ENTRIES 64
1219
1220	/**
1221	* Ring-3 guest page mapping TLB.
1222	* @remarks used in ring-0 as well at the moment.
1223	*/
1224	typedef struct PGMPAGER3MAPTLB
1225	{
1226	/** The TLB entries. */
1227	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1228	} PGMPAGER3MAPTLB;
1229	/** Pointer to the ring-3 guest page mapping TLB. */
1230	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1231
1232	/**
1233	* Calculates the index of the TLB entry for the specified guest page.
1234	* @returns Physical TLB index.
1235	* @param GCPhys The guest physical address.
1236	*/
1237	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1238
1239
1240	/** @name Context neutrual page mapper TLB.
1241	*
1242	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1243	* code is writting in a kind of context neutrual way. Time will show whether
1244	* this actually makes sense or not...
1245	*
1246	* @{ */
1247	/** @typedef PPGMPAGEMAPTLB
1248	* The page mapper TLB pointer type for the current context. */
1249	/** @typedef PPGMPAGEMAPTLB
1250	* The page mapper TLB entry pointer type for the current context. */
1251	/** @typedef PPGMPAGEMAPTLB
1252	* The page mapper TLB entry pointer pointer type for the current context. */
1253	/** @def PGM_PAGEMAPTLB_ENTRIES
1254	* The number of TLB entries in the page mapper TLB for the current context. */
1255	/** @def PGM_PAGEMAPTLB_IDX
1256	* Calculate the TLB index for a guest physical address.
1257	* @returns The TLB index.
1258	* @param GCPhys The guest physical address. */
1259	/** @typedef PPGMPAGEMAP
1260	* Pointer to a page mapper unit for current context. */
1261	/** @typedef PPPGMPAGEMAP
1262	* Pointer to a page mapper unit pointer for current context. */
1263	#ifdef IN_GC
1264	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1265	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1266	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1267	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1268	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1269	typedef void * PPGMPAGEMAP;
1270	typedef void ** PPPGMPAGEMAP;
1271	//#elif IN_RING0
1272	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1273	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1274	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1275	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1276	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1277	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1278	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1279	#else
1280	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1281	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1282	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1283	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1284	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1285	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1286	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1287	#endif
1288	/** @} */
1289
1290
1291	/** @name PGM Pool Indexes.
1292	* Aka. the unique shadow page identifier.
1293	* @{ */
1294	/** NIL page pool IDX. */
1295	#define NIL_PGMPOOL_IDX 0
1296	/** The first normal index. */
1297	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1298	/** Page directory (32-bit root). */
1299	#define PGMPOOL_IDX_PD 1
1300	/** The extended PAE page directory (2048 entries, works as root currently). */
1301	#define PGMPOOL_IDX_PAE_PD 2
1302	/** PAE Page Directory Table 0. */
1303	#define PGMPOOL_IDX_PAE_PD_0 3
1304	/** PAE Page Directory Table 1. */
1305	#define PGMPOOL_IDX_PAE_PD_1 4
1306	/** PAE Page Directory Table 2. */
1307	#define PGMPOOL_IDX_PAE_PD_2 5
1308	/** PAE Page Directory Table 3. */
1309	#define PGMPOOL_IDX_PAE_PD_3 6
1310	/** Page Directory Pointer Table (PAE root, not currently used). */
1311	#define PGMPOOL_IDX_PDPT 7
1312	/** AMD64 CR3 level index.*/
1313	#define PGMPOOL_IDX_AMD64_CR3 8
1314	/** Nested paging root.*/
1315	#define PGMPOOL_IDX_NESTED_ROOT 9
1316	/** The first normal index. */
1317	#define PGMPOOL_IDX_FIRST 10
1318	/** The last valid index. (inclusive, 14 bits) */
1319	#define PGMPOOL_IDX_LAST 0x3fff
1320	/** @} */
1321
1322	/** The NIL index for the parent chain. */
1323	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1324
1325	/**
1326	* Node in the chain linking a shadowed page to it's parent (user).
1327	*/
1328	#pragma pack(1)
1329	typedef struct PGMPOOLUSER
1330	{
1331	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1332	uint16_t iNext;
1333	/** The user page index. */
1334	uint16_t iUser;
1335	/** Index into the user table. */
1336	uint32_t iUserTable;
1337	} PGMPOOLUSER, *PPGMPOOLUSER;
1338	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1339	#pragma pack()
1340
1341
1342	/** The NIL index for the phys ext chain. */
1343	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1344
1345	/**
1346	* Node in the chain of physical cross reference extents.
1347	*/
1348	#pragma pack(1)
1349	typedef struct PGMPOOLPHYSEXT
1350	{
1351	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1352	uint16_t iNext;
1353	/** The user page index. */
1354	uint16_t aidx[3];
1355	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1356	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1357	#pragma pack()
1358
1359
1360	/**
1361	* The kind of page that's being shadowed.
1362	*/
1363	typedef enum PGMPOOLKIND
1364	{
1365	/** The virtual invalid 0 entry. */
1366	PGMPOOLKIND_INVALID = 0,
1367	/** The entry is free (=unused). */
1368	PGMPOOLKIND_FREE,
1369
1370	/** Shw: 32-bit page table; Gst: no paging */
1371	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1372	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1373	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1374	/** Shw: 32-bit page table; Gst: 4MB page. */
1375	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1376	/** Shw: PAE page table; Gst: no paging */
1377	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1378	/** Shw: PAE page table; Gst: 32-bit page table. */
1379	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1380	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1381	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1382	/** Shw: PAE page table; Gst: PAE page table. */
1383	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1384	/** Shw: PAE page table; Gst: 2MB page. */
1385	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1386
1387	/** Shw: PAE page directory; Gst: 32-bit page directory. */
1388	PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1389	/** Shw: PAE page directory; Gst: PAE page directory. */
1390	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1391
1392	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1393	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1394	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1395	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1396	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1397	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1398	/** Shw: 64-bit page directory table; Gst: no paging */
1399	PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1400
1401	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1402	PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1403
1404	/** Shw: EPT page directory pointer table; Gst: no paging */
1405	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1406	/** Shw: EPT page directory table; Gst: no paging */
1407	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1408	/** Shw: EPT page table; Gst: no paging */
1409	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1410
1411	/** Shw: Root 32-bit page directory. */
1412	PGMPOOLKIND_ROOT_32BIT_PD,
1413	/** Shw: Root PAE page directory */
1414	PGMPOOLKIND_ROOT_PAE_PD,
1415	/** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1416	PGMPOOLKIND_ROOT_PDPT,
1417	/** Shw: Root Nested paging table. */
1418	PGMPOOLKIND_ROOT_NESTED,
1419
1420	/** The last valid entry. */
1421	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1422	} PGMPOOLKIND;
1423
1424
1425	/**
1426	* The tracking data for a page in the pool.
1427	*/
1428	typedef struct PGMPOOLPAGE
1429	{
1430	/** AVL node code with the (R3) physical address of this page. */
1431	AVLOHCPHYSNODECORE Core;
1432	/** Pointer to the R3 mapping of the page. */
1433	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1434	R3PTRTYPE(void *) pvPageR3;
1435	#else
1436	R3R0PTRTYPE(void *) pvPageR3;
1437	#endif
1438	/** The guest physical address. */
1439	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1440	uint32_t Alignment0;
1441	#endif
1442	RTGCPHYS GCPhys;
1443	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1444	uint8_t enmKind;
1445	uint8_t bPadding;
1446	/** The index of this page. */
1447	uint16_t idx;
1448	/** The next entry in the list this page currently resides in.
1449	* It's either in the free list or in the GCPhys hash. */
1450	uint16_t iNext;
1451	#ifdef PGMPOOL_WITH_USER_TRACKING
1452	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1453	uint16_t iUserHead;
1454	/** The number of present entries. */
1455	uint16_t cPresent;
1456	/** The first entry in the table which is present. */
1457	uint16_t iFirstPresent;
1458	#endif
1459	#ifdef PGMPOOL_WITH_MONITORING
1460	/** The number of modifications to the monitored page. */
1461	uint16_t cModifications;
1462	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1463	uint16_t iModifiedNext;
1464	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1465	uint16_t iModifiedPrev;
1466	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1467	uint16_t iMonitoredNext;
1468	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1469	uint16_t iMonitoredPrev;
1470	#endif
1471	#ifdef PGMPOOL_WITH_CACHE
1472	/** The next page in the age list. */
1473	uint16_t iAgeNext;
1474	/** The previous page in the age list. */
1475	uint16_t iAgePrev;
1476	#endif /* PGMPOOL_WITH_CACHE */
1477	/** Used to indicate that the page is zeroed. */
1478	bool fZeroed;
1479	/** Used to indicate that a PT has non-global entries. */
1480	bool fSeenNonGlobal;
1481	/** Used to indicate that we're monitoring writes to the guest page. */
1482	bool fMonitored;
1483	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1484	* (All pages are in the age list.) */
1485	bool fCached;
1486	/** This is used by the R3 access handlers when invoked by an async thread.
1487	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1488	bool volatile fReusedFlushPending;
1489	/** Used to indicate that the guest is mapping the page is also used as a CR3.
1490	* In these cases the access handler acts differently and will check
1491	* for mapping conflicts like the normal CR3 handler.
1492	* @todo When we change the CR3 shadowing to use pool pages, this flag can be
1493	* replaced by a list of pages which share access handler.
1494	*/
1495	bool fCR3Mix;
1496	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1497
1498
1499	#ifdef PGMPOOL_WITH_CACHE
1500	/** The hash table size. */
1501	# define PGMPOOL_HASH_SIZE 0x40
1502	/** The hash function. */
1503	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1504	#endif
1505
1506
1507	/**
1508	* The shadow page pool instance data.
1509	*
1510	* It's all one big allocation made at init time, except for the
1511	* pages that is. The user nodes follows immediatly after the
1512	* page structures.
1513	*/
1514	typedef struct PGMPOOL
1515	{
1516	/** The VM handle - R3 Ptr. */
1517	PVMR3 pVMR3;
1518	/** The VM handle - R0 Ptr. */
1519	PVMR0 pVMR0;
1520	/** The VM handle - RC Ptr. */
1521	PVMRC pVMRC;
1522	/** The max pool size. This includes the special IDs. */
1523	uint16_t cMaxPages;
1524	/** The current pool size. */
1525	uint16_t cCurPages;
1526	/** The head of the free page list. */
1527	uint16_t iFreeHead;
1528	/* Padding. */
1529	uint16_t u16Padding;
1530	#ifdef PGMPOOL_WITH_USER_TRACKING
1531	/** Head of the chain of free user nodes. */
1532	uint16_t iUserFreeHead;
1533	/** The number of user nodes we've allocated. */
1534	uint16_t cMaxUsers;
1535	/** The number of present page table entries in the entire pool. */
1536	uint32_t cPresent;
1537	/** Pointer to the array of user nodes - RC pointer. */
1538	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1539	/** Pointer to the array of user nodes - R3 pointer. */
1540	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1541	/** Pointer to the array of user nodes - R0 pointer. */
1542	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1543	#endif /* PGMPOOL_WITH_USER_TRACKING */
1544	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1545	/** Head of the chain of free phys ext nodes. */
1546	uint16_t iPhysExtFreeHead;
1547	/** The number of user nodes we've allocated. */
1548	uint16_t cMaxPhysExts;
1549	/** Pointer to the array of physical xref extent - RC pointer. */
1550	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1551	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1552	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1553	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1554	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1555	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1556	#ifdef PGMPOOL_WITH_CACHE
1557	/** Hash table for GCPhys addresses. */
1558	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1559	/** The head of the age list. */
1560	uint16_t iAgeHead;
1561	/** The tail of the age list. */
1562	uint16_t iAgeTail;
1563	/** Set if the cache is enabled. */
1564	bool fCacheEnabled;
1565	#endif /* PGMPOOL_WITH_CACHE */
1566	#ifdef PGMPOOL_WITH_MONITORING
1567	/** Head of the list of modified pages. */
1568	uint16_t iModifiedHead;
1569	/** The current number of modified pages. */
1570	uint16_t cModifiedPages;
1571	/** Access handler, RC. */
1572	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1573	/** Access handler, R0. */
1574	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1575	/** Access handler, R3. */
1576	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1577	/** The access handler description (HC ptr). */
1578	R3PTRTYPE(const char *) pszAccessHandler;
1579	#endif /* PGMPOOL_WITH_MONITORING */
1580	/** The number of pages currently in use. */
1581	uint16_t cUsedPages;
1582	#ifdef VBOX_WITH_STATISTICS
1583	/** The high wather mark for cUsedPages. */
1584	uint16_t cUsedPagesHigh;
1585	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1586	/** Profiling pgmPoolAlloc(). */
1587	STAMPROFILEADV StatAlloc;
1588	/** Profiling pgmPoolClearAll(). */
1589	STAMPROFILE StatClearAll;
1590	/** Profiling pgmPoolFlushAllInt(). */
1591	STAMPROFILE StatFlushAllInt;
1592	/** Profiling pgmPoolFlushPage(). */
1593	STAMPROFILE StatFlushPage;
1594	/** Profiling pgmPoolFree(). */
1595	STAMPROFILE StatFree;
1596	/** Profiling time spent zeroing pages. */
1597	STAMPROFILE StatZeroPage;
1598	# ifdef PGMPOOL_WITH_USER_TRACKING
1599	/** Profiling of pgmPoolTrackDeref. */
1600	STAMPROFILE StatTrackDeref;
1601	/** Profiling pgmTrackFlushGCPhysPT. */
1602	STAMPROFILE StatTrackFlushGCPhysPT;
1603	/** Profiling pgmTrackFlushGCPhysPTs. */
1604	STAMPROFILE StatTrackFlushGCPhysPTs;
1605	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1606	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1607	/** Number of times we've been out of user records. */
1608	STAMCOUNTER StatTrackFreeUpOneUser;
1609	# endif
1610	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1611	/** Profiling deref activity related tracking GC physical pages. */
1612	STAMPROFILE StatTrackDerefGCPhys;
1613	/** Number of linear searches for a HCPhys in the ram ranges. */
1614	STAMCOUNTER StatTrackLinearRamSearches;
1615	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1616	STAMCOUNTER StamTrackPhysExtAllocFailures;
1617	# endif
1618	# ifdef PGMPOOL_WITH_MONITORING
1619	/** Profiling the RC/R0 access handler. */
1620	STAMPROFILE StatMonitorRZ;
1621	/** Times we've failed interpreting the instruction. */
1622	STAMCOUNTER StatMonitorRZEmulateInstr;
1623	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1624	STAMPROFILE StatMonitorRZFlushPage;
1625	/** Times we've detected fork(). */
1626	STAMCOUNTER StatMonitorRZFork;
1627	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
1628	STAMPROFILE StatMonitorRZHandled;
1629	/** Times we've failed interpreting a patch code instruction. */
1630	STAMCOUNTER StatMonitorRZIntrFailPatch1;
1631	/** Times we've failed interpreting a patch code instruction during flushing. */
1632	STAMCOUNTER StatMonitorRZIntrFailPatch2;
1633	/** The number of times we've seen rep prefixes we can't handle. */
1634	STAMCOUNTER StatMonitorRZRepPrefix;
1635	/** Profiling the REP STOSD cases we've handled. */
1636	STAMPROFILE StatMonitorRZRepStosd;
1637
1638	/** Profiling the R3 access handler. */
1639	STAMPROFILE StatMonitorR3;
1640	/** Times we've failed interpreting the instruction. */
1641	STAMCOUNTER StatMonitorR3EmulateInstr;
1642	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1643	STAMPROFILE StatMonitorR3FlushPage;
1644	/** Times we've detected fork(). */
1645	STAMCOUNTER StatMonitorR3Fork;
1646	/** Profiling the R3 access we've handled (except REP STOSD). */
1647	STAMPROFILE StatMonitorR3Handled;
1648	/** The number of times we've seen rep prefixes we can't handle. */
1649	STAMCOUNTER StatMonitorR3RepPrefix;
1650	/** Profiling the REP STOSD cases we've handled. */
1651	STAMPROFILE StatMonitorR3RepStosd;
1652	/** The number of times we're called in an async thread an need to flush. */
1653	STAMCOUNTER StatMonitorR3Async;
1654	/** The high wather mark for cModifiedPages. */
1655	uint16_t cModifiedPagesHigh;
1656	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1657	# endif
1658	# ifdef PGMPOOL_WITH_CACHE
1659	/** The number of cache hits. */
1660	STAMCOUNTER StatCacheHits;
1661	/** The number of cache misses. */
1662	STAMCOUNTER StatCacheMisses;
1663	/** The number of times we've got a conflict of 'kind' in the cache. */
1664	STAMCOUNTER StatCacheKindMismatches;
1665	/** Number of times we've been out of pages. */
1666	STAMCOUNTER StatCacheFreeUpOne;
1667	/** The number of cacheable allocations. */
1668	STAMCOUNTER StatCacheCacheable;
1669	/** The number of uncacheable allocations. */
1670	STAMCOUNTER StatCacheUncacheable;
1671	# endif
1672	#elif HC_ARCH_BITS == 64
1673	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1674	#endif
1675	/** The AVL tree for looking up a page by its HC physical address. */
1676	AVLOHCPHYSTREE HCPhysTree;
1677	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1678	/** Array of pages. (cMaxPages in length)
1679	* The Id is the index into thist array.
1680	*/
1681	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1682	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1683
1684
1685	/** @def PGMPOOL_PAGE_2_PTR
1686	* Maps a pool page pool into the current context.
1687	*
1688	* @returns VBox status code.
1689	* @param pVM The VM handle.
1690	* @param pPage The pool page.
1691	*
1692	* @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1693	* small page window employeed by that function. Be careful.
1694	* @remark There is no need to assert on the result.
1695	*/
1696	#if defined(IN_GC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1697	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPage((pVM), (pPage))
1698	#else
1699	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1700	#endif
1701
1702
1703	/**
1704	* Trees are using self relative offsets as pointers.
1705	* So, all its data, including the root pointer, must be in the heap for HC and GC
1706	* to have the same layout.
1707	*/
1708	typedef struct PGMTREES
1709	{
1710	/** Physical access handlers (AVL range+offsetptr tree). */
1711	AVLROGCPHYSTREE PhysHandlers;
1712	/** Virtual access handlers (AVL range + GC ptr tree). */
1713	AVLROGCPTRTREE VirtHandlers;
1714	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1715	AVLROGCPHYSTREE PhysToVirtHandlers;
1716	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1717	AVLROGCPTRTREE HyperVirtHandlers;
1718	} PGMTREES;
1719	/** Pointer to PGM trees. */
1720	typedef PGMTREES *PPGMTREES;
1721
1722
1723	/** @name Paging mode macros
1724	* @{ */
1725	#ifdef IN_GC
1726	# define PGM_CTX(a,b) a##RC##b
1727	# define PGM_CTX_STR(a,b) a "GC" b
1728	# define PGM_CTX_DECL(type) VMMRCDECL(type)
1729	#else
1730	# ifdef IN_RING3
1731	# define PGM_CTX(a,b) a##R3##b
1732	# define PGM_CTX_STR(a,b) a "R3" b
1733	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1734	# else
1735	# define PGM_CTX(a,b) a##R0##b
1736	# define PGM_CTX_STR(a,b) a "R0" b
1737	# define PGM_CTX_DECL(type) VMMDECL(type)
1738	# endif
1739	#endif
1740
1741	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1742	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1743	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1744	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1745	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1746	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1747	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1748	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1749	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1750	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1751	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1752	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1753	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1754	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1755	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1756	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1757	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1758
1759	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1760	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1761	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1762	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1763	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1764	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1765	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1766	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1767	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1768	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1769	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1770	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1771	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1772	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1773	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1774	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1775	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1776
1777	/* Shw_Gst */
1778	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1779	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1780	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1781	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1782	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1783	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1784	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1785	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1786	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1787	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1788	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1789	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1790	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1791	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1792	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1793	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1794	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1795	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1796	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1797
1798	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1799	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1800	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1801	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1802	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1803	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1804	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1805	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1806	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1807	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1808	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1809	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1810	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1811	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1812	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1813	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1814	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1815	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1816	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1817	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1818	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1819	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1820	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1821	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1822	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1823	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1824	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1825	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1826	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1827	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1828	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1829	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1830	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
1831	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
1832	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
1833	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
1834	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
1835
1836	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1837	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1838	/** @} */
1839
1840	/**
1841	* Data for each paging mode.
1842	*/
1843	typedef struct PGMMODEDATA
1844	{
1845	/** The guest mode type. */
1846	uint32_t uGstType;
1847	/** The shadow mode type. */
1848	uint32_t uShwType;
1849
1850	/** @name Function pointers for Shadow paging.
1851	* @{
1852	*/
1853	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1854	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1855	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1856	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1857
1858	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1859	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1860
1861	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1862	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1863	/** @} */
1864
1865	/** @name Function pointers for Guest paging.
1866	* @{
1867	*/
1868	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1869	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1870	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1871	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1872	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1873	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1874	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1875	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1876	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1877	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1878	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1879	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1880	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1881
1882	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1883	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1884	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1885	DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1886	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
1887	DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1888	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
1889	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
1890	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
1891
1892	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1893	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1894	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1895	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1896	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1897	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1898	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1899	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1900	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1901	/** @} */
1902
1903	/** @name Function pointers for Both Shadow and Guest paging.
1904	* @{
1905	*/
1906	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1907	/* no pfnR3BthTrap0eHandler */
1908	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1909	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1910	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1911	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1912	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1913	#ifdef VBOX_STRICT
1914	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1915	#endif
1916
1917	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1918	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1919	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1920	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1921	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1922	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1923	#ifdef VBOX_STRICT
1924	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1925	#endif
1926
1927	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1928	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1929	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1930	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1931	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1932	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1933	#ifdef VBOX_STRICT
1934	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1935	#endif
1936	/** @} */
1937	} PGMMODEDATA, *PPGMMODEDATA;
1938
1939
1940
1941	/**
1942	* Converts a PGM pointer into a VM pointer.
1943	* @returns Pointer to the VM structure the PGM is part of.
1944	* @param pPGM Pointer to PGM instance data.
1945	*/
1946	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1947
1948	/**
1949	* PGM Data (part of VM)
1950	*/
1951	typedef struct PGM
1952	{
1953	/** Offset to the VM structure. */
1954	RTINT offVM;
1955
1956	/*
1957	* This will be redefined at least two more times before we're done, I'm sure.
1958	* The current code is only to get on with the coding.
1959	* - 2004-06-10: initial version, bird.
1960	* - 2004-07-02: 1st time, bird.
1961	* - 2004-10-18: 2nd time, bird.
1962	* - 2005-07-xx: 3rd time, bird.
1963	*/
1964
1965	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1966	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1967	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1968	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1969
1970	/** The host paging mode. (This is what SUPLib reports.) */
1971	SUPPAGINGMODE enmHostMode;
1972	/** The shadow paging mode. */
1973	PGMMODE enmShadowMode;
1974	/** The guest paging mode. */
1975	PGMMODE enmGuestMode;
1976
1977	/** The current physical address representing in the guest CR3 register. */
1978	RTGCPHYS GCPhysCR3;
1979	/** Pointer to the 5 page CR3 content mapping.
1980	* The first page is always the CR3 (in some form) while the 4 other pages
1981	* are used of the PDs in PAE mode. */
1982	RTGCPTR GCPtrCR3Mapping;
1983	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1984	uint32_t u32Alignment;
1985	#endif
1986	/** The physical address of the currently monitored guest CR3 page.
1987	* When this value is NIL_RTGCPHYS no page is being monitored. */
1988	RTGCPHYS GCPhysGstCR3Monitored;
1989
1990	/** @name 32-bit Guest Paging.
1991	* @{ */
1992	/** The guest's page directory, HC pointer. */
1993	#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
1994	R3PTRTYPE(PX86PD) pGuestPDHC;
1995	#else
1996	R3R0PTRTYPE(PX86PD) pGuestPDHC;
1997	#endif
1998	/** The guest's page directory, static GC mapping. */
1999	RCPTRTYPE(PX86PD) pGuestPDGC;
2000	/** @} */
2001
2002	/** @name PAE Guest Paging.
2003	* @{ */
2004	/** The guest's page directory pointer table, static GC mapping. */
2005	RCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
2006	/** The guest's page directory pointer table, HC pointer. */
2007	#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2008	R3PTRTYPE(PX86PDPT) pGstPaePDPTHC;
2009	#else
2010	R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
2011	#endif
2012	/** The guest's page directories, HC pointers.
2013	* These are individual pointers and don't have to be adjecent.
2014	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2015	#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2016	R3PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
2017	#else
2018	R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
2019	#endif
2020	/** The guest's page directories, static GC mapping.
2021	* Unlike the HC array the first entry can be accessed as a 2048 entry PD.
2022	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2023	RCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
2024	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2025	RTGCPHYS aGCPhysGstPaePDs[4];
2026	/** The physical addresses of the monitored guest page directories (PAE). */
2027	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2028	/** @} */
2029
2030	/** @name AMD64 Guest Paging.
2031	* @{ */
2032	/** The guest's page directory pointer table, HC pointer. */
2033	#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2034	R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
2035	#else
2036	R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
2037	#endif
2038	/** @} */
2039
2040	/** @name 32-bit Shadow Paging
2041	* @{ */
2042	/** The 32-Bit PD - HC Ptr. */
2043	#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2044	R3PTRTYPE(PX86PD) pHC32BitPD;
2045	#else
2046	R3R0PTRTYPE(PX86PD) pHC32BitPD;
2047	#endif
2048	/** The 32-Bit PD - GC Ptr. */
2049	RCPTRTYPE(PX86PD) pGC32BitPD;
2050	#if HC_ARCH_BITS == 64
2051	uint32_t u32Padding1; /*< alignment padding. /
2052	#endif
2053	/** The Physical Address (HC) of the 32-Bit PD. */
2054	RTHCPHYS HCPhys32BitPD;
2055	/** @} */
2056
2057	/** @name PAE Shadow Paging
2058	* @{ */
2059	/** The four PDs for the low 4GB - HC Ptr.
2060	* Even though these are 4 pointers, what they point at is a single table.
2061	* Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2062	#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2063	R3PTRTYPE(PX86PDPAE) apHCPaePDs[4];
2064	#else
2065	R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
2066	#endif
2067	/** The four PDs for the low 4GB - GC Ptr.
2068	* Same kind of mapping as apHCPaePDs. */
2069	RCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
2070	/** The Physical Address (HC) of the four PDs for the low 4GB.
2071	* These are NOT 4 contiguous pages. */
2072	RTHCPHYS aHCPhysPaePDs[4];
2073	/** The PAE PDP - HC Ptr. */
2074	R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
2075	/** The Physical Address (HC) of the PAE PDPT. */
2076	RTHCPHYS HCPhysPaePDPT;
2077	/** The PAE PDPT - GC Ptr. */
2078	RCPTRTYPE(PX86PDPT) pGCPaePDPT;
2079	/** @} */
2080
2081	/** @name AMD64 Shadow Paging
2082	* Extends PAE Paging.
2083	* @{ */
2084	#if HC_ARCH_BITS == 64
2085	RTRCPTR alignment5; /*< structure size alignment. /
2086	#endif
2087	/** The Page Map Level 4 table - HC Ptr. */
2088	#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2089	R3PTRTYPE(PX86PML4) pHCPaePML4;
2090	#else
2091	R3R0PTRTYPE(PX86PML4) pHCPaePML4;
2092	#endif
2093	/** The Physical Address (HC) of the Page Map Level 4 table. */
2094	RTHCPHYS HCPhysPaePML4;
2095	/** The pgm pool page descriptor for the current active CR3. */
2096	#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2097	R3PTRTYPE(PPGMPOOLPAGE) pHCShwAmd64CR3;
2098	#else
2099	R3R0PTRTYPE(PPGMPOOLPAGE) pHCShwAmd64CR3;
2100	#endif
2101
2102	/** @}*/
2103
2104	/** @name Nested Shadow Paging
2105	* @{ */
2106	/** Root table; format depends on the host paging mode (AMD-V) or EPT */
2107	#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2108	R3PTRTYPE(void *) pHCNestedRoot;
2109	#else
2110	R3R0PTRTYPE(void *) pHCNestedRoot;
2111	#endif
2112	/** The Physical Address (HC) of the nested paging root. */
2113	RTHCPHYS HCPhysNestedRoot;
2114
2115	/** @name Function pointers for Shadow paging.
2116	* @{
2117	*/
2118	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2119	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2120	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2121	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2122
2123	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2124	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2125
2126	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2127	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2128
2129	/** @} */
2130
2131	/** @name Function pointers for Guest paging.
2132	* @{
2133	*/
2134	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2135	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2136	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2137	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2138	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2139	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2140	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2141	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2142	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2143	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2144	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2145	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2146	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2147
2148	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2149	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2150	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2151	DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2152	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2153	DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2154	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2155	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2156	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2157	#if HC_ARCH_BITS == 64
2158	RTRCPTR alignment3; /*< structure size alignment. /
2159	#endif
2160
2161	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2162	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2163	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2164	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2165	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2166	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2167	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2168	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2169	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2170	/** @} */
2171
2172	/** @name Function pointers for Both Shadow and Guest paging.
2173	* @{
2174	*/
2175	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2176	/* no pfnR3BthTrap0eHandler */
2177	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2178	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2179	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2180	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2181	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2182	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2183
2184	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2185	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2186	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2187	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2188	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2189	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2190	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2191
2192	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2193	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2194	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2195	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2196	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2197	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2198	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2199	#if HC_ARCH_BITS == 64
2200	RTRCPTR alignment2; /*< structure size alignment. /
2201	#endif
2202	/** @} */
2203
2204	/** Pointer to SHW+GST mode data (function pointers).
2205	* The index into this table is made up from */
2206	R3PTRTYPE(PPGMMODEDATA) paModeData;
2207
2208	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2209	* This is sorted by physical address and contains no overlapping ranges. */
2210	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2211	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2212	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2213	/** RC pointer corresponding to PGM::pRamRangesR3. */
2214	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2215	/** The configured RAM size. */
2216	RTUINT cbRamSize;
2217
2218	/** Pointer to the list of ROM ranges - for R3.
2219	* This is sorted by physical address and contains no overlapping ranges. */
2220	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2221	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2222	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2223	/** RC pointer corresponding to PGM::pRomRangesR3. */
2224	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2225	/** Alignment padding. */
2226	RTRCPTR GCPtrPadding2;
2227
2228	/** Pointer to the list of MMIO2 ranges - for R3.
2229	* Registration order. */
2230	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2231
2232	/** PGM offset based trees - R3 Ptr. */
2233	R3PTRTYPE(PPGMTREES) pTreesR3;
2234	/** PGM offset based trees - R0 Ptr. */
2235	R0PTRTYPE(PPGMTREES) pTreesR0;
2236	/** PGM offset based trees - RC Ptr. */
2237	RCPTRTYPE(PPGMTREES) pTreesRC;
2238
2239	/** Linked list of GC mappings - for RC.
2240	* The list is sorted ascending on address.
2241	*/
2242	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2243	/** Linked list of GC mappings - for HC.
2244	* The list is sorted ascending on address.
2245	*/
2246	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2247	/** Linked list of GC mappings - for R0.
2248	* The list is sorted ascending on address.
2249	*/
2250	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2251
2252	/** If set no conflict checks are required. (boolean) */
2253	bool fMappingsFixed;
2254	/** If set, then no mappings are put into the shadow page table. (boolean) */
2255	bool fDisableMappings;
2256	/** Size of fixed mapping */
2257	uint32_t cbMappingFixed;
2258	/** Base address (GC) of fixed mapping */
2259	RTGCPTR GCPtrMappingFixed;
2260	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2261	uint32_t u32Padding0; /*< alignment padding. /
2262	#endif
2263
2264
2265	/** @name Intermediate Context
2266	* @{ */
2267	/** Pointer to the intermediate page directory - Normal. */
2268	R3PTRTYPE(PX86PD) pInterPD;
2269	/** Pointer to the intermedate page tables - Normal.
2270	* There are two page tables, one for the identity mapping and one for
2271	* the host context mapping (of the core code). */
2272	R3PTRTYPE(PX86PT) apInterPTs[2];
2273	/** Pointer to the intermedate page tables - PAE. */
2274	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2275	/** Pointer to the intermedate page directory - PAE. */
2276	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2277	/** Pointer to the intermedate page directory - PAE. */
2278	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2279	/** Pointer to the intermedate page-map level 4 - AMD64. */
2280	R3PTRTYPE(PX86PML4) pInterPaePML4;
2281	/** Pointer to the intermedate page directory - AMD64. */
2282	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2283	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2284	RTHCPHYS HCPhysInterPD;
2285	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2286	RTHCPHYS HCPhysInterPaePDPT;
2287	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2288	RTHCPHYS HCPhysInterPaePML4;
2289	/** @} */
2290
2291	/** Base address of the dynamic page mapping area.
2292	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2293	*/
2294	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2295	/** The index of the last entry used in the dynamic page mapping area. */
2296	RTUINT iDynPageMapLast;
2297	/** Cache containing the last entries in the dynamic page mapping area.
2298	* The cache size is covering half of the mapping area. */
2299	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2300
2301	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2302	RTGCPHYS GCPhys4MBPSEMask;
2303
2304	/** A20 gate mask.
2305	* Our current approach to A20 emulation is to let REM do it and don't bother
2306	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2307	* But whould need arrise, we'll subject physical addresses to this mask. */
2308	RTGCPHYS GCPhysA20Mask;
2309	/** A20 gate state - boolean! */
2310	RTUINT fA20Enabled;
2311
2312	/** What needs syncing (PGM_SYNC_*).
2313	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2314	* PGMFlushTLB, and PGMR3Load. */
2315	RTUINT fSyncFlags;
2316
2317	/** PGM critical section.
2318	* This protects the physical & virtual access handlers, ram ranges,
2319	* and the page flag updating (some of it anyway).
2320	*/
2321	PDMCRITSECT CritSect;
2322
2323	/** Shadow Page Pool - R3 Ptr. */
2324	R3PTRTYPE(PPGMPOOL) pPoolR3;
2325	/** Shadow Page Pool - R0 Ptr. */
2326	R0PTRTYPE(PPGMPOOL) pPoolR0;
2327	/** Shadow Page Pool - RC Ptr. */
2328	RCPTRTYPE(PPGMPOOL) pPoolRC;
2329
2330	/** We're not in a state which permits writes to guest memory.
2331	* (Only used in strict builds.) */
2332	bool fNoMorePhysWrites;
2333
2334	/** Flush the cache on the next access. */
2335	bool fPhysCacheFlushPending;
2336	/** @todo r=bird: Fix member names!*/
2337	/** PGMPhysRead cache */
2338	PGMPHYSCACHE pgmphysreadcache;
2339	/** PGMPhysWrite cache */
2340	PGMPHYSCACHE pgmphyswritecache;
2341
2342	/**
2343	* Data associated with managing the ring-3 mappings of the allocation chunks.
2344	*/
2345	struct
2346	{
2347	/** The chunk tree, ordered by chunk id. */
2348	#if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
2349	R3PTRTYPE(PAVLU32NODECORE) pTree;
2350	#else
2351	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2352	#endif
2353	/** The chunk mapping TLB. */
2354	PGMCHUNKR3MAPTLB Tlb;
2355	/** The number of mapped chunks. */
2356	uint32_t c;
2357	/** The maximum number of mapped chunks.
2358	* @cfgm PGM/MaxRing3Chunks */
2359	uint32_t cMax;
2360	/** The chunk age tree, ordered by ageing sequence number. */
2361	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2362	/** The current time. */
2363	uint32_t iNow;
2364	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2365	uint32_t AgeingCountdown;
2366	} ChunkR3Map;
2367
2368	/**
2369	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2370	*/
2371	PGMPAGER3MAPTLB PhysTlbHC;
2372
2373	/** @name The zero page.
2374	* @{ */
2375	/** The host physical address of the zero page. */
2376	RTHCPHYS HCPhysZeroPg;
2377	/** The ring-3 mapping of the zero page. */
2378	RTR3PTR pvZeroPgR3;
2379	/** The ring-0 mapping of the zero page. */
2380	RTR0PTR pvZeroPgR0;
2381	/** The GC mapping of the zero page. */
2382	RTGCPTR pvZeroPgGC;
2383	#if GC_ARCH_BITS != 32
2384	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2385	#endif
2386	/** @}*/
2387
2388	/** The number of handy pages. */
2389	uint32_t cHandyPages;
2390	/**
2391	* Array of handy pages.
2392	*
2393	* This array is used in a two way communication between pgmPhysAllocPage
2394	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2395	* an intermediary.
2396	*
2397	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2398	* (The current size of 32 pages, means 128 KB of handy memory.)
2399	*/
2400	GMMPAGEDESC aHandyPages[32];
2401
2402	/** @name Release Statistics
2403	* @{ */
2404	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2405	uint32_t cPrivatePages; /*< The number of private pages. /
2406	uint32_t cSharedPages; /*< The number of shared pages. /
2407	uint32_t cZeroPages; /*< The number of zero backed pages. /
2408	/** The number of times the guest has switched mode since last reset or statistics reset. */
2409	STAMCOUNTER cGuestModeChanges;
2410	/** @} */
2411
2412	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2413	/** RC: Which statistic this \#PF should be attributed to. */
2414	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2415	RTRCPTR padding0;
2416	/** R0: Which statistic this \#PF should be attributed to. */
2417	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2418	RTR0PTR padding1;
2419
2420	/* Common */
2421	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2422	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2423	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2424	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2425	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2426	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2427	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2428	# endif
2429	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
2430	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
2431
2432	/* R3 only: */
2433	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2434	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2435	STAMCOUNTER StatR3GuestPDWrite; /*< R3: The total number of times pgmHCGuestPDWriteHandler() was called. /
2436	STAMCOUNTER StatR3GuestPDWriteConflict; /*< R3: The number of times GuestPDWriteContlict() detected a conflict. /
2437	STAMCOUNTER StatR3DynRamTotal; /*< R3: Allocated MBs of guest ram /
2438	STAMCOUNTER StatR3DynRamGrow; /*< R3: Nr of pgmr3PhysGrowRange calls. /
2439
2440	/* RC only: */
2441	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache hits /
2442	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache misses /
2443	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2444	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2445
2446	/* RZ only: */
2447	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
2448	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2449	STAMPROFILE StatRZTrap0eTimeSyncPT;
2450	STAMPROFILE StatRZTrap0eTimeMapping;
2451	STAMPROFILE StatRZTrap0eTimeOutOfSync;
2452	STAMPROFILE StatRZTrap0eTimeHandlers;
2453	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
2454	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2455	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
2456	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
2457	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2458	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2459	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
2460	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2461	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2462	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2463	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2464	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2465	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
2466	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
2467	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
2468	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
2469	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
2470	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
2471	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
2472	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
2473	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
2474	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: #PF err kind /
2475	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: #PF err kind /
2476	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: #PF err kind /
2477	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: #PF err kind /
2478	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: #PF err kind /
2479	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: #PF err kind /
2480	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: #PF err kind /
2481	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: #PF err kind /
2482	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: #PF err kind /
2483	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: #PF err kind /
2484	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: #PF err kind /
2485	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest #PFs. /
2486	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest #PF ending up at the end of the #PF code. /
2487	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest #PF to HMA or other mapping. /
2488	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
2489	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
2490	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the #PFs. /
2491	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
2492	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
2493	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
2494	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
2495	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
2496
2497	/* HC - R3 and (maybe) R0: */
2498
2499	/* RZ & R3: */
2500	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
2501	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
2502	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2503	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2504	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
2505	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
2506	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
2507	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
2508	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
2509	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
2510	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
2511	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
2512	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
2513	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
2514	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
2515	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
2516	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2517	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
2518	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
2519	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
2520	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2521	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2522	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
2523	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
2524	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
2525	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
2526	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
2527	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
2528	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
2529	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
2530	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
2531	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2532	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2533	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
2534	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2535	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2536	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2537	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2538	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2539	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2540	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
2541	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2542	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2543	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2544	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2545	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2546	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2547	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2548	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
2549	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2550	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2551	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2552	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2553	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
2554
2555	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
2556	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
2557	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2558	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2559	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
2560	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
2561	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
2562	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
2563	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
2564	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
2565	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
2566	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
2567	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
2568	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
2569	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
2570	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
2571	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2572	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
2573	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
2574	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
2575	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2576	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2577	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
2578	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
2579	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
2580	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
2581	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
2582	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
2583	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
2584	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
2585	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
2586	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2587	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
2588	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2589	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2590	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2591	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2592	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2593	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2594	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2595	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
2596	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2597	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2598	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2599	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2600	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2601	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2602	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2603	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
2604	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2605	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2606	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2607	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2608	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
2609	#endif /* VBOX_WITH_STATISTICS */
2610	} PGM, *PPGM;
2611
2612
2613	/** @name PGM::fSyncFlags Flags
2614	* @{
2615	*/
2616	/** Updates the virtual access handler state bit in PGMPAGE. */
2617	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2618	/** Always sync CR3. */
2619	#define PGM_SYNC_ALWAYS RT_BIT(1)
2620	/** Check monitoring on next CR3 (re)load and invalidate page. */
2621	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2622	/** Clear the page pool (a light weight flush). */
2623	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2624	/** @} */
2625
2626
2627	__BEGIN_DECLS
2628
2629	int pgmLock(PVM pVM);
2630	void pgmUnlock(PVM pVM);
2631
2632	VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2633	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2634
2635	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2636	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2637	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2638	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2639	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2640
2641	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2642	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2643	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2644	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2645	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2646	#else
2647	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2648	#endif
2649	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2650
2651
2652	void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2653	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2654	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2655	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2656	#ifdef IN_RING3
2657	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2658	int pgmR3PhysRamReset(PVM pVM);
2659	int pgmR3PhysRomReset(PVM pVM);
2660	#ifndef VBOX_WITH_NEW_PHYS_CODE
2661	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2662	#endif
2663
2664	int pgmR3PoolInit(PVM pVM);
2665	void pgmR3PoolRelocate(PVM pVM);
2666	void pgmR3PoolReset(PVM pVM);
2667
2668	#endif /* IN_RING3 */
2669	#if defined(IN_GC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2670	void *pgmPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2671	#endif
2672	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2673	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2674	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2675	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2676	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2677	void pgmPoolFlushAll(PVM pVM);
2678	void pgmPoolClearAll(PVM pVM);
2679	int pgmPoolSyncCR3(PVM pVM);
2680	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2681	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2682	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2683	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2684	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2685	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2686	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2687	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2688	#ifdef PGMPOOL_WITH_MONITORING
2689	# ifdef IN_RING3
2690	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2691	# else
2692	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2693	# endif
2694	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2695	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2696	void pgmPoolMonitorModifiedClearAll(PVM pVM);
2697	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2698	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2699	#endif
2700
2701	__END_DECLS
2702
2703
2704	/**
2705	* Gets the PGMRAMRANGE structure for a guest page.
2706	*
2707	* @returns Pointer to the RAM range on success.
2708	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2709	*
2710	* @param pPGM PGM handle.
2711	* @param GCPhys The GC physical address.
2712	*/
2713	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2714	{
2715	/*
2716	* Optimize for the first range.
2717	*/
2718	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2719	RTGCPHYS off = GCPhys - pRam->GCPhys;
2720	if (RT_UNLIKELY(off >= pRam->cb))
2721	{
2722	do
2723	{
2724	pRam = pRam->CTX_SUFF(pNext);
2725	if (RT_UNLIKELY(!pRam))
2726	break;
2727	off = GCPhys - pRam->GCPhys;
2728	} while (off >= pRam->cb);
2729	}
2730	return pRam;
2731	}
2732
2733
2734	/**
2735	* Gets the PGMPAGE structure for a guest page.
2736	*
2737	* @returns Pointer to the page on success.
2738	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2739	*
2740	* @param pPGM PGM handle.
2741	* @param GCPhys The GC physical address.
2742	*/
2743	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2744	{
2745	/*
2746	* Optimize for the first range.
2747	*/
2748	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2749	RTGCPHYS off = GCPhys - pRam->GCPhys;
2750	if (RT_UNLIKELY(off >= pRam->cb))
2751	{
2752	do
2753	{
2754	pRam = pRam->CTX_SUFF(pNext);
2755	if (RT_UNLIKELY(!pRam))
2756	return NULL;
2757	off = GCPhys - pRam->GCPhys;
2758	} while (off >= pRam->cb);
2759	}
2760	return &pRam->aPages[off >> PAGE_SHIFT];
2761	}
2762
2763
2764	/**
2765	* Gets the PGMPAGE structure for a guest page.
2766	*
2767	* Old Phys code: Will make sure the page is present.
2768	*
2769	* @returns VBox status code.
2770	* @retval VINF_SUCCESS and a valid *ppPage on success.
2771	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2772	*
2773	* @param pPGM PGM handle.
2774	* @param GCPhys The GC physical address.
2775	* @param ppPage Where to store the page poitner on success.
2776	*/
2777	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2778	{
2779	/*
2780	* Optimize for the first range.
2781	*/
2782	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2783	RTGCPHYS off = GCPhys - pRam->GCPhys;
2784	if (RT_UNLIKELY(off >= pRam->cb))
2785	{
2786	do
2787	{
2788	pRam = pRam->CTX_SUFF(pNext);
2789	if (RT_UNLIKELY(!pRam))
2790	{
2791	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
2792	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2793	}
2794	off = GCPhys - pRam->GCPhys;
2795	} while (off >= pRam->cb);
2796	}
2797	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2798	#ifndef VBOX_WITH_NEW_PHYS_CODE
2799
2800	/*
2801	* Make sure it's present.
2802	*/
2803	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2804	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2805	{
2806	#ifdef IN_RING3
2807	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2808	#else
2809	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2810	#endif
2811	if (VBOX_FAILURE(rc))
2812	{
2813	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
2814	return rc;
2815	}
2816	Assert(rc == VINF_SUCCESS);
2817	}
2818	#endif
2819	return VINF_SUCCESS;
2820	}
2821
2822
2823
2824
2825	/**
2826	* Gets the PGMPAGE structure for a guest page.
2827	*
2828	* Old Phys code: Will make sure the page is present.
2829	*
2830	* @returns VBox status code.
2831	* @retval VINF_SUCCESS and a valid *ppPage on success.
2832	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2833	*
2834	* @param pPGM PGM handle.
2835	* @param GCPhys The GC physical address.
2836	* @param ppPage Where to store the page poitner on success.
2837	* @param ppRamHint Where to read and store the ram list hint.
2838	* The caller initializes this to NULL before the call.
2839	*/
2840	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2841	{
2842	RTGCPHYS off;
2843	PPGMRAMRANGE pRam = *ppRamHint;
2844	if ( !pRam
2845	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2846	{
2847	pRam = pPGM->CTX_SUFF(pRamRanges);
2848	off = GCPhys - pRam->GCPhys;
2849	if (RT_UNLIKELY(off >= pRam->cb))
2850	{
2851	do
2852	{
2853	pRam = pRam->CTX_SUFF(pNext);
2854	if (RT_UNLIKELY(!pRam))
2855	{
2856	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
2857	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2858	}
2859	off = GCPhys - pRam->GCPhys;
2860	} while (off >= pRam->cb);
2861	}
2862	*ppRamHint = pRam;
2863	}
2864	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2865	#ifndef VBOX_WITH_NEW_PHYS_CODE
2866
2867	/*
2868	* Make sure it's present.
2869	*/
2870	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2871	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2872	{
2873	#ifdef IN_RING3
2874	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2875	#else
2876	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2877	#endif
2878	if (VBOX_FAILURE(rc))
2879	{
2880	ppPage = NULL; / Shut up annoying smart ass. */
2881	return rc;
2882	}
2883	Assert(rc == VINF_SUCCESS);
2884	}
2885	#endif
2886	return VINF_SUCCESS;
2887	}
2888
2889
2890	/**
2891	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2892	*
2893	* @returns Pointer to the page on success.
2894	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2895	*
2896	* @param pPGM PGM handle.
2897	* @param GCPhys The GC physical address.
2898	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
2899	*/
2900	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2901	{
2902	/*
2903	* Optimize for the first range.
2904	*/
2905	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2906	RTGCPHYS off = GCPhys - pRam->GCPhys;
2907	if (RT_UNLIKELY(off >= pRam->cb))
2908	{
2909	do
2910	{
2911	pRam = pRam->CTX_SUFF(pNext);
2912	if (RT_UNLIKELY(!pRam))
2913	return NULL;
2914	off = GCPhys - pRam->GCPhys;
2915	} while (off >= pRam->cb);
2916	}
2917	*ppRam = pRam;
2918	return &pRam->aPages[off >> PAGE_SHIFT];
2919	}
2920
2921
2922	/**
2923	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2924	*
2925	* @returns Pointer to the page on success.
2926	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2927	*
2928	* @param pPGM PGM handle.
2929	* @param GCPhys The GC physical address.
2930	* @param ppPage Where to store the pointer to the PGMPAGE structure.
2931	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2932	*/
2933	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2934	{
2935	/*
2936	* Optimize for the first range.
2937	*/
2938	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2939	RTGCPHYS off = GCPhys - pRam->GCPhys;
2940	if (RT_UNLIKELY(off >= pRam->cb))
2941	{
2942	do
2943	{
2944	pRam = pRam->CTX_SUFF(pNext);
2945	if (RT_UNLIKELY(!pRam))
2946	{
2947	ppRam = NULL; / Shut up silly GCC warnings. */
2948	ppPage = NULL; / ditto */
2949	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2950	}
2951	off = GCPhys - pRam->GCPhys;
2952	} while (off >= pRam->cb);
2953	}
2954	*ppRam = pRam;
2955	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2956	#ifndef VBOX_WITH_NEW_PHYS_CODE
2957
2958	/*
2959	* Make sure it's present.
2960	*/
2961	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2962	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2963	{
2964	#ifdef IN_RING3
2965	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2966	#else
2967	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2968	#endif
2969	if (VBOX_FAILURE(rc))
2970	{
2971	ppPage = NULL; / Shut up silly GCC warnings. */
2972	ppPage = NULL; / ditto */
2973	return rc;
2974	}
2975	Assert(rc == VINF_SUCCESS);
2976
2977	}
2978	#endif
2979	return VINF_SUCCESS;
2980	}
2981
2982
2983	/**
2984	* Convert GC Phys to HC Phys.
2985	*
2986	* @returns VBox status.
2987	* @param pPGM PGM handle.
2988	* @param GCPhys The GC physical address.
2989	* @param pHCPhys Where to store the corresponding HC physical address.
2990	*
2991	* @deprecated Doesn't deal with zero, shared or write monitored pages.
2992	* Avoid when writing new code!
2993	*/
2994	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2995	{
2996	PPGMPAGE pPage;
2997	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2998	if (VBOX_FAILURE(rc))
2999	return rc;
3000	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
3001	return VINF_SUCCESS;
3002	}
3003
3004
3005	#ifndef IN_GC
3006	/**
3007	* Queries the Physical TLB entry for a physical guest page,
3008	* attemting to load the TLB entry if necessary.
3009	*
3010	* @returns VBox status code.
3011	* @retval VINF_SUCCESS on success
3012	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3013	* @param pPGM The PGM instance handle.
3014	* @param GCPhys The address of the guest page.
3015	* @param ppTlbe Where to store the pointer to the TLB entry.
3016	*/
3017
3018	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3019	{
3020	int rc;
3021	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3022	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3023	{
3024	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3025	rc = VINF_SUCCESS;
3026	}
3027	else
3028	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3029	*ppTlbe = pTlbe;
3030	return rc;
3031	}
3032	#endif /* !IN_GC */
3033
3034	#if !defined(IN_GC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3035
3036	# ifndef VBOX_WITH_NEW_PHYS_CODE
3037	/**
3038	* Convert GC Phys to HC Virt.
3039	*
3040	* @returns VBox status.
3041	* @param pPGM PGM handle.
3042	* @param GCPhys The GC physical address.
3043	* @param pHCPtr Where to store the corresponding HC virtual address.
3044	*
3045	* @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
3046	*/
3047	DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3048	{
3049	PPGMRAMRANGE pRam;
3050	PPGMPAGE pPage;
3051	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3052	if (VBOX_FAILURE(rc))
3053	{
3054	pHCPtr = 0; / Shut up silly GCC warnings. */
3055	return rc;
3056	}
3057	RTGCPHYS off = GCPhys - pRam->GCPhys;
3058
3059	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3060	{
3061	unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3062	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3063	return VINF_SUCCESS;
3064	}
3065	if (pRam->pvR3)
3066	{
3067	pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /* @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3068	return VINF_SUCCESS;
3069	}
3070	pHCPtr = 0; / Shut up silly GCC warnings. */
3071	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3072	}
3073	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3074
3075
3076	/**
3077	* Convert GC Phys to HC Virt.
3078	*
3079	* @returns VBox status.
3080	* @param PVM VM handle.
3081	* @param pRam Ram range
3082	* @param GCPhys The GC physical address.
3083	* @param pHCPtr Where to store the corresponding HC virtual address.
3084	*
3085	* @deprecated This will be eliminated. Don't use it.
3086	*/
3087	DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3088	{
3089	RTGCPHYS off = GCPhys - pRam->GCPhys;
3090	Assert(off < pRam->cb);
3091
3092	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3093	{
3094	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3095	/* Physical chunk in dynamically allocated range not present? */
3096	if (RT_UNLIKELY(!pRam->paChunkR3Ptrs[idx]))
3097	{
3098	#ifdef IN_RING3
3099	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3100	#else
3101	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3102	#endif
3103	if (rc != VINF_SUCCESS)
3104	{
3105	pHCPtr = 0; / GCC crap */
3106	return rc;
3107	}
3108	}
3109	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3110	return VINF_SUCCESS;
3111	}
3112	if (pRam->pvR3)
3113	{
3114	pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /* @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3115	return VINF_SUCCESS;
3116	}
3117	pHCPtr = 0; / GCC crap */
3118	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3119	}
3120
3121	#endif /* !IN_GC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3122
3123	/**
3124	* Convert GC Phys to HC Virt and HC Phys.
3125	*
3126	* @returns VBox status.
3127	* @param pPGM PGM handle.
3128	* @param GCPhys The GC physical address.
3129	* @param pHCPtr Where to store the corresponding HC virtual address.
3130	* @param pHCPhys Where to store the HC Physical address and its flags.
3131	*
3132	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3133	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3134	*/
3135	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3136	{
3137	PPGMRAMRANGE pRam;
3138	PPGMPAGE pPage;
3139	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3140	if (VBOX_FAILURE(rc))
3141	{
3142	pHCPtr = 0; / Shut up crappy GCC warnings */
3143	pHCPhys = 0; / ditto */
3144	return rc;
3145	}
3146	RTGCPHYS off = GCPhys - pRam->GCPhys;
3147
3148	pHCPhys = pPage->HCPhys; /* @todo PAGE FLAGS */
3149	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3150	{
3151	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3152	#if defined(IN_GC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3153	PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3154	*pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3155	#else
3156	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3157	#endif
3158	return VINF_SUCCESS;
3159	}
3160	if (pRam->pvR3)
3161	{
3162	pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off); /* @todo @bugref{1865,3202}: Code is converting R3 pointer and maybe using it in R0! */
3163	return VINF_SUCCESS;
3164	}
3165	*pHCPtr = 0;
3166	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3167	}
3168
3169
3170	/**
3171	* Clears flags associated with a RAM address.
3172	*
3173	* @returns VBox status code.
3174	* @param pPGM PGM handle.
3175	* @param GCPhys Guest context physical address.
3176	* @param fFlags fFlags to clear. (Bits 0-11.)
3177	*/
3178	DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3179	{
3180	PPGMPAGE pPage;
3181	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3182	if (VBOX_FAILURE(rc))
3183	return rc;
3184
3185	fFlags &= ~X86_PTE_PAE_PG_MASK;
3186	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3187	return VINF_SUCCESS;
3188	}
3189
3190
3191	/**
3192	* Clears flags associated with a RAM address.
3193	*
3194	* @returns VBox status code.
3195	* @param pPGM PGM handle.
3196	* @param GCPhys Guest context physical address.
3197	* @param fFlags fFlags to clear. (Bits 0-11.)
3198	* @param ppRamHint Where to read and store the ram list hint.
3199	* The caller initializes this to NULL before the call.
3200	*/
3201	DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3202	{
3203	PPGMPAGE pPage;
3204	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3205	if (VBOX_FAILURE(rc))
3206	return rc;
3207
3208	fFlags &= ~X86_PTE_PAE_PG_MASK;
3209	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3210	return VINF_SUCCESS;
3211	}
3212
3213
3214	/**
3215	* Sets (bitwise OR) flags associated with a RAM address.
3216	*
3217	* @returns VBox status code.
3218	* @param pPGM PGM handle.
3219	* @param GCPhys Guest context physical address.
3220	* @param fFlags fFlags to set clear. (Bits 0-11.)
3221	*/
3222	DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3223	{
3224	PPGMPAGE pPage;
3225	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3226	if (VBOX_FAILURE(rc))
3227	return rc;
3228
3229	fFlags &= ~X86_PTE_PAE_PG_MASK;
3230	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3231	return VINF_SUCCESS;
3232	}
3233
3234
3235	/**
3236	* Sets (bitwise OR) flags associated with a RAM address.
3237	*
3238	* @returns VBox status code.
3239	* @param pPGM PGM handle.
3240	* @param GCPhys Guest context physical address.
3241	* @param fFlags fFlags to set clear. (Bits 0-11.)
3242	* @param ppRamHint Where to read and store the ram list hint.
3243	* The caller initializes this to NULL before the call.
3244	*/
3245	DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3246	{
3247	PPGMPAGE pPage;
3248	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3249	if (VBOX_FAILURE(rc))
3250	return rc;
3251
3252	fFlags &= ~X86_PTE_PAE_PG_MASK;
3253	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3254	return VINF_SUCCESS;
3255	}
3256
3257
3258	/**
3259	* Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3260	* Takes PSE-36 into account.
3261	*
3262	* @returns guest physical address
3263	* @param pPGM Pointer to the PGM instance data.
3264	* @param Pde Guest Pde
3265	*/
3266	DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3267	{
3268	RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3269	GCPhys \|= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3270
3271	return GCPhys & pPGM->GCPhys4MBPSEMask;
3272	}
3273
3274
3275	/**
3276	* Gets the page directory for the specified address.
3277	*
3278	* @returns Pointer to the page directory in question.
3279	* @returns NULL if the page directory is not present or on an invalid page.
3280	* @param pPGM Pointer to the PGM instance data.
3281	* @param GCPtr The address.
3282	*/
3283	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3284	{
3285	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3286	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3287	{
3288	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3289	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3290
3291	/* cache is out-of-sync. */
3292	PX86PDPAE pPD;
3293	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3294	if (VBOX_SUCCESS(rc))
3295	return pPD;
3296	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3297	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3298	}
3299	return NULL;
3300	}
3301
3302
3303	/**
3304	* Gets the page directory entry for the specified address.
3305	*
3306	* @returns Pointer to the page directory entry in question.
3307	* @returns NULL if the page directory is not present or on an invalid page.
3308	* @param pPGM Pointer to the PGM instance data.
3309	* @param GCPtr The address.
3310	*/
3311	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3312	{
3313	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3314	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3315	{
3316	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3317	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3318	return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3319
3320	/* The cache is out-of-sync. */
3321	PX86PDPAE pPD;
3322	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3323	if (VBOX_SUCCESS(rc))
3324	return &pPD->a[iPD];
3325	AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3326	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3327	}
3328	return NULL;
3329	}
3330
3331
3332	/**
3333	* Gets the page directory entry for the specified address.
3334	*
3335	* @returns The page directory entry in question.
3336	* @returns A non-present entry if the page directory is not present or on an invalid page.
3337	* @param pPGM Pointer to the PGM instance data.
3338	* @param GCPtr The address.
3339	*/
3340	DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3341	{
3342	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3343	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3344	{
3345	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3346	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3347	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3348
3349	/* cache is out-of-sync. */
3350	PX86PDPAE pPD;
3351	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3352	if (VBOX_SUCCESS(rc))
3353	return pPD->a[iPD].u;
3354	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3355	}
3356	return 0ULL;
3357	}
3358
3359
3360	/**
3361	* Gets the page directory pointer table entry for the specified address
3362	* and returns the index into the page directory
3363	*
3364	* @returns Pointer to the page directory in question.
3365	* @returns NULL if the page directory is not present or on an invalid page.
3366	* @param pPGM Pointer to the PGM instance data.
3367	* @param GCPtr The address.
3368	* @param piPD Receives the index into the returned page directory
3369	*/
3370	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3371	{
3372	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3373	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3374	{
3375	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3376	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3377	{
3378	*piPD = iPD;
3379	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3380	}
3381
3382	/* cache is out-of-sync. */
3383	PX86PDPAE pPD;
3384	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3385	if (VBOX_SUCCESS(rc))
3386	{
3387	*piPD = iPD;
3388	return pPD;
3389	}
3390	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3391	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3392	}
3393	return NULL;
3394	}
3395
3396	#ifndef IN_GC
3397
3398	/**
3399	* Gets the page directory pointer entry for the specified address.
3400	*
3401	* @returns Pointer to the page directory pointer entry in question.
3402	* @returns NULL if the page directory is not present or on an invalid page.
3403	* @param pPGM Pointer to the PGM instance data.
3404	* @param GCPtr The address.
3405	* @param ppPml4e Page Map Level-4 Entry (out)
3406	*/
3407	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
3408	{
3409	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3410
3411	Assert(pPGM->pGstPaePML4HC);
3412	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3413	if ((*ppPml4e)->n.u1Present)
3414	{
3415	PX86PDPT pPdpt;
3416	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
3417	if (VBOX_FAILURE(rc))
3418	{
3419	AssertFailed();
3420	return NULL;
3421	}
3422	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3423	return &pPdpt->a[iPdPt];
3424	}
3425	return NULL;
3426	}
3427
3428
3429	/**
3430	* Gets the page directory entry for the specified address.
3431	*
3432	* @returns The page directory entry in question.
3433	* @returns A non-present entry if the page directory is not present or on an invalid page.
3434	* @param pPGM Pointer to the PGM instance data.
3435	* @param GCPtr The address.
3436	* @param ppPml4e Page Map Level-4 Entry (out)
3437	* @param pPdpe Page directory pointer table entry (out)
3438	*/
3439	DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3440	{
3441	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3442
3443	Assert(pPGM->pGstPaePML4HC);
3444	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3445	if ((*ppPml4e)->n.u1Present)
3446	{
3447	PX86PDPT pPdptTemp;
3448	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3449	if (VBOX_FAILURE(rc))
3450	{
3451	AssertFailed();
3452	return 0ULL;
3453	}
3454
3455	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3456	*pPdpe = pPdptTemp->a[iPdPt];
3457	if (pPdpe->n.u1Present)
3458	{
3459	PX86PDPAE pPD;
3460
3461	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3462	if (VBOX_FAILURE(rc))
3463	{
3464	AssertFailed();
3465	return 0ULL;
3466	}
3467	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3468	return pPD->a[iPD].u;
3469	}
3470	}
3471	return 0ULL;
3472	}
3473
3474
3475	/**
3476	* Gets the page directory entry for the specified address.
3477	*
3478	* @returns The page directory entry in question.
3479	* @returns A non-present entry if the page directory is not present or on an invalid page.
3480	* @param pPGM Pointer to the PGM instance data.
3481	* @param GCPtr The address.
3482	*/
3483	DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3484	{
3485	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3486
3487	Assert(pPGM->pGstPaePML4HC);
3488	if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3489	{
3490	PX86PDPT pPdptTemp;
3491	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3492	if (VBOX_FAILURE(rc))
3493	{
3494	AssertFailed();
3495	return 0ULL;
3496	}
3497
3498	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3499	if (pPdptTemp->a[iPdPt].n.u1Present)
3500	{
3501	PX86PDPAE pPD;
3502
3503	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3504	if (VBOX_FAILURE(rc))
3505	{
3506	AssertFailed();
3507	return 0ULL;
3508	}
3509	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3510	return pPD->a[iPD].u;
3511	}
3512	}
3513	return 0ULL;
3514	}
3515
3516
3517	/**
3518	* Gets the page directory entry for the specified address.
3519	*
3520	* @returns Pointer to the page directory entry in question.
3521	* @returns NULL if the page directory is not present or on an invalid page.
3522	* @param pPGM Pointer to the PGM instance data.
3523	* @param GCPtr The address.
3524	*/
3525	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3526	{
3527	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3528
3529	Assert(pPGM->pGstPaePML4HC);
3530	if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3531	{
3532	PX86PDPT pPdptTemp;
3533	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3534	if (VBOX_FAILURE(rc))
3535	{
3536	AssertFailed();
3537	return NULL;
3538	}
3539
3540	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3541	if (pPdptTemp->a[iPdPt].n.u1Present)
3542	{
3543	PX86PDPAE pPD;
3544
3545	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3546	if (VBOX_FAILURE(rc))
3547	{
3548	AssertFailed();
3549	return NULL;
3550	}
3551	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3552	return &pPD->a[iPD];
3553	}
3554	}
3555	return NULL;
3556	}
3557
3558
3559	/**
3560	* Gets the GUEST page directory pointer for the specified address.
3561	*
3562	* @returns The page directory in question.
3563	* @returns NULL if the page directory is not present or on an invalid page.
3564	* @param pPGM Pointer to the PGM instance data.
3565	* @param GCPtr The address.
3566	* @param ppPml4e Page Map Level-4 Entry (out)
3567	* @param pPdpe Page directory pointer table entry (out)
3568	* @param piPD Receives the index into the returned page directory
3569	*/
3570	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
3571	{
3572	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3573
3574	Assert(pPGM->pGstPaePML4HC);
3575	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3576	if ((*ppPml4e)->n.u1Present)
3577	{
3578	PX86PDPT pPdptTemp;
3579	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3580	if (VBOX_FAILURE(rc))
3581	{
3582	AssertFailed();
3583	return 0ULL;
3584	}
3585
3586	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3587	*pPdpe = pPdptTemp->a[iPdPt];
3588	if (pPdpe->n.u1Present)
3589	{
3590	PX86PDPAE pPD;
3591
3592	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3593	if (VBOX_FAILURE(rc))
3594	{
3595	AssertFailed();
3596	return 0ULL;
3597	}
3598	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3599	return pPD;
3600	}
3601	}
3602	return 0ULL;
3603	}
3604
3605
3606	/**
3607	* Gets the GUEST page directory pointer for the specified address.
3608	*
3609	* @returns The page directory in question.
3610	* @returns NULL if the page directory is not present or on an invalid page.
3611	* @param pPGM Pointer to the PGM instance data.
3612	* @param GCPtr The address.
3613	* @param piPD Receives the index into the returned page directory
3614	*/
3615	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, unsigned *piPD)
3616	{
3617	PX86PML4E pPml4e;
3618	PX86PDPE pPdpe;
3619	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3620
3621	Assert(pPGM->pGstPaePML4HC);
3622	pPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3623	if (pPml4e->n.u1Present)
3624	{
3625	PX86PDPT pPdptTemp;
3626	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3627	if (VBOX_FAILURE(rc))
3628	{
3629	AssertFailed();
3630	return 0ULL;
3631	}
3632
3633	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3634	pPdpe = &pPdptTemp->a[iPdPt];
3635	if (pPdpe->n.u1Present)
3636	{
3637	PX86PDPAE pPD;
3638
3639	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3640	if (VBOX_FAILURE(rc))
3641	{
3642	AssertFailed();
3643	return 0ULL;
3644	}
3645	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3646	return pPD;
3647	}
3648	}
3649	return 0ULL;
3650	}
3651
3652	#endif /* !IN_GC */
3653
3654	/**
3655	* Checks if any of the specified page flags are set for the given page.
3656	*
3657	* @returns true if any of the flags are set.
3658	* @returns false if all the flags are clear.
3659	* @param pPGM PGM handle.
3660	* @param GCPhys The GC physical address.
3661	* @param fFlags The flags to check for.
3662	*/
3663	DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3664	{
3665	PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3666	return pPage
3667	&& (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3668	}
3669
3670
3671	/**
3672	* Gets the page state for a physical handler.
3673	*
3674	* @returns The physical handler page state.
3675	* @param pCur The physical handler in question.
3676	*/
3677	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3678	{
3679	switch (pCur->enmType)
3680	{
3681	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3682	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3683
3684	case PGMPHYSHANDLERTYPE_MMIO:
3685	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3686	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3687
3688	default:
3689	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3690	}
3691	}
3692
3693
3694	/**
3695	* Gets the page state for a virtual handler.
3696	*
3697	* @returns The virtual handler page state.
3698	* @param pCur The virtual handler in question.
3699	* @remarks This should never be used on a hypervisor access handler.
3700	*/
3701	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3702	{
3703	switch (pCur->enmType)
3704	{
3705	case PGMVIRTHANDLERTYPE_WRITE:
3706	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3707	case PGMVIRTHANDLERTYPE_ALL:
3708	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3709	default:
3710	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3711	}
3712	}
3713
3714
3715	/**
3716	* Clears one physical page of a virtual handler
3717	*
3718	* @param pPGM Pointer to the PGM instance.
3719	* @param pCur Virtual handler structure
3720	* @param iPage Physical page index
3721	*
3722	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3723	* need to care about other handlers in the same page.
3724	*/
3725	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3726	{
3727	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3728
3729	/*
3730	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
3731	*/
3732	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3733	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3734	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3735	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3736	#endif
3737	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3738	{
3739	/* We're the head of the alias chain. */
3740	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3741	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3742	AssertReleaseMsg(pRemove != NULL,
3743	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3744	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3745	AssertReleaseMsg(pRemove == pPhys2Virt,
3746	("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3747	" got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3748	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3749	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3750	#endif
3751	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3752	{
3753	/* Insert the next list in the alias chain into the tree. */
3754	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3755	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3756	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3757	("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3758	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3759	#endif
3760	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
3761	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3762	AssertRelease(fRc);
3763	}
3764	}
3765	else
3766	{
3767	/* Locate the previous node in the alias chain. */
3768	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3769	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3770	AssertReleaseMsg(pPrev != pPhys2Virt,
3771	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3772	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3773	#endif
3774	for (;;)
3775	{
3776	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3777	if (pNext == pPhys2Virt)
3778	{
3779	/* unlink. */
3780	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3781	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3782	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3783	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3784	else
3785	{
3786	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3787	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3788	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3789	}
3790	break;
3791	}
3792
3793	/* next */
3794	if (pNext == pPrev)
3795	{
3796	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3797	AssertReleaseMsg(pNext != pPrev,
3798	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3799	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3800	#endif
3801	break;
3802	}
3803	pPrev = pNext;
3804	}
3805	}
3806	Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3807	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
3808	pPhys2Virt->offNextAlias = 0;
3809	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3810
3811	/*
3812	* Clear the ram flags for this page.
3813	*/
3814	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3815	AssertReturnVoid(pPage);
3816	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3817	}
3818
3819
3820	/**
3821	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
3822	*
3823	* @returns Pointer to the shadow page structure.
3824	* @param pPool The pool.
3825	* @param HCPhys The HC physical address of the shadow page.
3826	*/
3827	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3828	{
3829	/*
3830	* Look up the page.
3831	*/
3832	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3833	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3834	return pPage;
3835	}
3836
3837
3838	/**
3839	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
3840	*
3841	* @returns Pointer to the shadow page structure.
3842	* @param pPool The pool.
3843	* @param idx The pool page index.
3844	*/
3845	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3846	{
3847	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3848	return &pPool->aPages[idx];
3849	}
3850
3851
3852	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3853	/**
3854	* Clear references to guest physical memory.
3855	*
3856	* @param pPool The pool.
3857	* @param pPoolPage The pool page.
3858	* @param pPhysPage The physical guest page tracking structure.
3859	*/
3860	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3861	{
3862	/*
3863	* Just deal with the simple case here.
3864	*/
3865	# ifdef LOG_ENABLED
3866	const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3867	# endif
3868	const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3869	if (cRefs == 1)
3870	{
3871	Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3872	pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3873	}
3874	else
3875	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3876	LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3877	}
3878	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3879
3880
3881	#ifdef PGMPOOL_WITH_CACHE
3882	/**
3883	* Moves the page to the head of the age list.
3884	*
3885	* This is done when the cached page is used in one way or another.
3886	*
3887	* @param pPool The pool.
3888	* @param pPage The cached page.
3889	* @todo inline in PGMInternal.h!
3890	*/
3891	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3892	{
3893	/*
3894	* Move to the head of the age list.
3895	*/
3896	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3897	{
3898	/* unlink */
3899	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3900	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3901	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3902	else
3903	pPool->iAgeTail = pPage->iAgePrev;
3904
3905	/* insert at head */
3906	pPage->iAgePrev = NIL_PGMPOOL_IDX;
3907	pPage->iAgeNext = pPool->iAgeHead;
3908	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3909	pPool->iAgeHead = pPage->idx;
3910	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3911	}
3912	}
3913	#endif /* PGMPOOL_WITH_CACHE */
3914
3915	/**
3916	* Tells if mappings are to be put into the shadow page table or not
3917	*
3918	* @returns boolean result
3919	* @param pVM VM handle.
3920	*/
3921
3922	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3923	{
3924	#ifdef IN_RING0
3925	/* There are no mappings in VT-x and AMD-V mode. */
3926	Assert(pPGM->fDisableMappings);
3927	return false;
3928	#else
3929	return !pPGM->fDisableMappings;
3930	#endif
3931	}
3932
3933	/** @} */
3934
3935	#endif
3936

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 13373

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