PGMInternal.h@ 11147

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1	/* $Id: PGMInternal.h 10822 2008-07-23 09:02:58Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/assert.h>
41	#include <iprt/critsect.h>
42
43	#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
44	# error "Not in PGM! This is an internal header!"
45	#endif
46
47
48	/** @defgroup grp_pgm_int Internals
49	* @ingroup grp_pgm
50	* @internal
51	* @{
52	*/
53
54
55	/** @name PGM Compile Time Config
56	* @{
57	*/
58
59	/**
60	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
61	* Comment it if it will break something.
62	*/
63	#define PGM_OUT_OF_SYNC_IN_GC
64
65	/**
66	* Check and skip global PDEs for non-global flushes
67	*/
68	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70	/**
71	* Sync N pages instead of a whole page table
72	*/
73	#define PGM_SYNC_N_PAGES
74
75	/**
76	* Number of pages to sync during a page fault
77	*
78	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
79	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
80	*/
81	#define PGM_SYNC_NR_PAGES 8
82
83	/**
84	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
85	*/
86	#define PGM_MAX_PHYSCACHE_ENTRIES 64
87	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
88
89	/**
90	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
91	*/
92	#define PGM_PHYSMEMACCESS_CACHING
93
94	/** @def PGMPOOL_WITH_CACHE
95	* Enable agressive caching using the page pool.
96	*
97	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
98	*/
99	#define PGMPOOL_WITH_CACHE
100
101	/** @def PGMPOOL_WITH_MIXED_PT_CR3
102	* When defined, we'll deal with 'uncachable' pages.
103	*/
104	#ifdef PGMPOOL_WITH_CACHE
105	# define PGMPOOL_WITH_MIXED_PT_CR3
106	#endif
107
108	/** @def PGMPOOL_WITH_MONITORING
109	* Monitor the guest pages which are shadowed.
110	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
111	* be enabled as well.
112	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
113	*/
114	#ifdef PGMPOOL_WITH_CACHE
115	# define PGMPOOL_WITH_MONITORING
116	#endif
117
118	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
119	* Tracking the of shadow pages mapping guest physical pages.
120	*
121	* This is very expensive, the current cache prototype is trying to figure out
122	* whether it will be acceptable with an agressive caching policy.
123	*/
124	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
125	# define PGMPOOL_WITH_GCPHYS_TRACKING
126	#endif
127
128	/** @def PGMPOOL_WITH_USER_TRACKNG
129	* Tracking users of shadow pages. This is required for the linking of shadow page
130	* tables and physical guest addresses.
131	*/
132	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
133	# define PGMPOOL_WITH_USER_TRACKING
134	#endif
135
136	/** @def PGMPOOL_CFG_MAX_GROW
137	* The maximum number of pages to add to the pool in one go.
138	*/
139	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
140
141	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
142	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
143	*/
144	#ifdef VBOX_STRICT
145	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
146	#endif
147	/** @} */
148
149
150	/** @name PDPT and PML4 flags.
151	* These are placed in the three bits available for system programs in
152	* the PDPT and PML4 entries.
153	* @{ */
154	/** The entry is a permanent one and it's must always be present.
155	* Never free such an entry. */
156	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
157	/** Mapping (hypervisor allocated pagetable). */
158	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
159	/** @} */
160
161	/** @name Page directory flags.
162	* These are placed in the three bits available for system programs in
163	* the page directory entries.
164	* @{ */
165	/** Mapping (hypervisor allocated pagetable). */
166	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
167	/** Made read-only to facilitate dirty bit tracking. */
168	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169	/** @} */
170
171	/** @name Page flags.
172	* These are placed in the three bits available for system programs in
173	* the page entries.
174	* @{ */
175	/** Made read-only to facilitate dirty bit tracking. */
176	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179	/** Scanned and approved by CSAM (tm).
180	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
181	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
182	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183	#endif
184	/** @} */
185
186	/** @name Defines used to indicate the shadow and guest paging in the templates.
187	* @{ */
188	#define PGM_TYPE_REAL 1
189	#define PGM_TYPE_PROT 2
190	#define PGM_TYPE_32BIT 3
191	#define PGM_TYPE_PAE 4
192	#define PGM_TYPE_AMD64 5
193	#define PGM_TYPE_NESTED 6
194	#define PGM_TYPE_EPT 7
195	/** @} */
196
197	/** Macro for checking if the guest is using paging.
198	* @param uType PGM_TYPE_*
199	* @remark ASSUMES certain order of the PGM_TYPE_* values.
200	*/
201	#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT && (uType) != PGM_TYPE_NESTED && (uType) != PGM_TYPE_EPT)
202
203	/** Macro for checking if the guest supports the NX bit.
204	* @param uType PGM_TYPE_*
205	* @remark ASSUMES certain order of the PGM_TYPE_* values.
206	*/
207	#define PGM_WITH_NX(uType) ((uType) >= PGM_TYPE_PAE && (uType) != PGM_TYPE_NESTED && (uType) != PGM_TYPE_EPT)
208
209
210	/** @def PGM_HCPHYS_2_PTR
211	* Maps a HC physical page pool address to a virtual address.
212	*
213	* @returns VBox status code.
214	* @param pVM The VM handle.
215	* @param HCPhys The HC physical address to map to a virtual one.
216	* @param ppv Where to store the virtual address. No need to cast this.
217	*
218	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
219	* small page window employeed by that function. Be careful.
220	* @remark There is no need to assert on the result.
221	*/
222	#ifdef IN_GC
223	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
224	#else
225	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
226	#endif
227
228	/** @def PGM_GCPHYS_2_PTR
229	* Maps a GC physical page address to a virtual address.
230	*
231	* @returns VBox status code.
232	* @param pVM The VM handle.
233	* @param GCPhys The GC physical address to map to a virtual one.
234	* @param ppv Where to store the virtual address. No need to cast this.
235	*
236	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
237	* small page window employeed by that function. Be careful.
238	* @remark There is no need to assert on the result.
239	*/
240	#ifdef IN_GC
241	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
242	#else
243	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only /, (void )(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
244	#endif
245
246	/** @def PGM_GCPHYS_2_PTR_EX
247	* Maps a unaligned GC physical page address to a virtual address.
248	*
249	* @returns VBox status code.
250	* @param pVM The VM handle.
251	* @param GCPhys The GC physical address to map to a virtual one.
252	* @param ppv Where to store the virtual address. No need to cast this.
253	*
254	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
255	* small page window employeed by that function. Be careful.
256	* @remark There is no need to assert on the result.
257	*/
258	#ifdef IN_GC
259	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
260	#else
261	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only /, (void )(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
262	#endif
263
264	/** @def PGM_INVL_PG
265	* Invalidates a page when in GC does nothing in HC.
266	*
267	* @param GCVirt The virtual address of the page to invalidate.
268	*/
269	#ifdef IN_GC
270	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
271	#elif defined(IN_RING0)
272	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
273	#else
274	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
275	#endif
276
277	/** @def PGM_INVL_BIG_PG
278	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
279	*
280	* @param GCVirt The virtual address within the page directory to invalidate.
281	*/
282	#ifdef IN_GC
283	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
284	#elif defined(IN_RING0)
285	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
286	#else
287	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
288	#endif
289
290	/** @def PGM_INVL_GUEST_TLBS()
291	* Invalidates all guest TLBs.
292	*/
293	#ifdef IN_GC
294	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
295	#elif defined(IN_RING0)
296	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
297	#else
298	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
299	#endif
300
301
302	/**
303	* Structure for tracking GC Mappings.
304	*
305	* This structure is used by linked list in both GC and HC.
306	*/
307	typedef struct PGMMAPPING
308	{
309	/** Pointer to next entry. */
310	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
311	/** Pointer to next entry. */
312	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
313	/** Pointer to next entry. */
314	RCPTRTYPE(struct PGMMAPPING *) pNextGC;
315	#if GC_ARCH_BITS == 64
316	RTRCPTR padding0;
317	#endif
318	/** Start Virtual address. */
319	RTGCUINTPTR GCPtr;
320	/** Last Virtual address (inclusive). */
321	RTGCUINTPTR GCPtrLast;
322	/** Range size (bytes). */
323	RTGCUINTPTR cb;
324	/** Pointer to relocation callback function. */
325	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
326	/** User argument to the callback. */
327	R3PTRTYPE(void *) pvUser;
328	/** Mapping description / name. For easing debugging. */
329	R3PTRTYPE(const char *) pszDesc;
330	/** Number of page tables. */
331	RTUINT cPTs;
332	#if HC_ARCH_BITS != GC_ARCH_BITS \|\| GC_ARCH_BITS == 64
333	RTUINT uPadding1; /*< Alignment padding. /
334	#endif
335	/** Array of page table mapping data. Each entry
336	* describes one page table. The array can be longer
337	* than the declared length.
338	*/
339	struct
340	{
341	/** The HC physical address of the page table. */
342	RTHCPHYS HCPhysPT;
343	/** The HC physical address of the first PAE page table. */
344	RTHCPHYS HCPhysPaePT0;
345	/** The HC physical address of the second PAE page table. */
346	RTHCPHYS HCPhysPaePT1;
347	/** The HC virtual address of the 32-bit page table. */
348	R3PTRTYPE(PX86PT) pPTR3;
349	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
350	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
351	/** The GC virtual address of the 32-bit page table. */
352	RCPTRTYPE(PX86PT) pPTGC;
353	/** The GC virtual address of the two PAE page table. */
354	RCPTRTYPE(PX86PTPAE) paPaePTsGC;
355	/** The GC virtual address of the 32-bit page table. */
356	R0PTRTYPE(PX86PT) pPTR0;
357	/** The GC virtual address of the two PAE page table. */
358	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
359	} aPTs[1];
360	} PGMMAPPING;
361	/** Pointer to structure for tracking GC Mappings. */
362	typedef struct PGMMAPPING *PPGMMAPPING;
363
364
365	/**
366	* Physical page access handler structure.
367	*
368	* This is used to keep track of physical address ranges
369	* which are being monitored in some kind of way.
370	*/
371	typedef struct PGMPHYSHANDLER
372	{
373	AVLROGCPHYSNODECORE Core;
374	/** Access type. */
375	PGMPHYSHANDLERTYPE enmType;
376	/** Number of pages to update. */
377	uint32_t cPages;
378	/** Pointer to R3 callback function. */
379	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
380	/** User argument for R3 handlers. */
381	R3PTRTYPE(void *) pvUserR3;
382	/** Pointer to R0 callback function. */
383	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
384	/** User argument for R0 handlers. */
385	R0PTRTYPE(void *) pvUserR0;
386	/** Pointer to GC callback function. */
387	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
388	/** User argument for GC handlers. */
389	RCPTRTYPE(void *) pvUserGC;
390	/** Description / Name. For easing debugging. */
391	R3PTRTYPE(const char *) pszDesc;
392	#ifdef VBOX_WITH_STATISTICS
393	/** Profiling of this handler. */
394	STAMPROFILE Stat;
395	#endif
396	} PGMPHYSHANDLER;
397	/** Pointer to a physical page access handler structure. */
398	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
399
400
401	/**
402	* Cache node for the physical addresses covered by a virtual handler.
403	*/
404	typedef struct PGMPHYS2VIRTHANDLER
405	{
406	/** Core node for the tree based on physical ranges. */
407	AVLROGCPHYSNODECORE Core;
408	/** Offset from this struct to the PGMVIRTHANDLER structure. */
409	int32_t offVirtHandler;
410	/** Offset of the next alias relative to this one.
411	* Bit 0 is used for indicating whether we're in the tree.
412	* Bit 1 is used for indicating that we're the head node.
413	*/
414	int32_t offNextAlias;
415	} PGMPHYS2VIRTHANDLER;
416	/** Pointer to a phys to virtual handler structure. */
417	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
418
419	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
420	* node is in the tree. */
421	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
422	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
423	* node is in the head of an alias chain.
424	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
425	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
426	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
427	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
428
429
430	/**
431	* Virtual page access handler structure.
432	*
433	* This is used to keep track of virtual address ranges
434	* which are being monitored in some kind of way.
435	*/
436	typedef struct PGMVIRTHANDLER
437	{
438	/** Core node for the tree based on virtual ranges. */
439	AVLROGCPTRNODECORE Core;
440	/** Number of cache pages. */
441	uint32_t u32Padding;
442	/** Access type. */
443	PGMVIRTHANDLERTYPE enmType;
444	/** Number of cache pages. */
445	uint32_t cPages;
446	#if GC_ARCH_BITS == 64
447	uint32_t padding0;
448	#endif
449	/** @todo The next two members are redundant. It adds some readability though. */
450	/** Start of the range. */
451	RTGCPTR GCPtr;
452	/** End of the range (exclusive). */
453	RTGCPTR GCPtrLast;
454	/** Size of the range (in bytes). */
455	RTGCUINTPTR cb;
456	/** Pointer to the GC callback function. */
457	RCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
458	#if GC_ARCH_BITS == 64
459	RTRCPTR padding1;
460	#endif
461	/** Pointer to the HC callback function for invalidation. */
462	R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
463	/** Pointer to the HC callback function. */
464	R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
465	/** Description / Name. For easing debugging. */
466	R3PTRTYPE(const char *) pszDesc;
467	#ifdef VBOX_WITH_STATISTICS
468	/** Profiling of this handler. */
469	STAMPROFILE Stat;
470	#endif
471	/** Array of cached physical addresses for the monitored ranged. */
472	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
473	} PGMVIRTHANDLER;
474	/** Pointer to a virtual page access handler structure. */
475	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
476
477
478	/**
479	* Page type.
480	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
481	* @todo convert to \#defines.
482	*/
483	typedef enum PGMPAGETYPE
484	{
485	/** The usual invalid zero entry. */
486	PGMPAGETYPE_INVALID = 0,
487	/** RAM page. (RWX) */
488	PGMPAGETYPE_RAM,
489	/** MMIO2 page. (RWX) */
490	PGMPAGETYPE_MMIO2,
491	/** Shadowed ROM. (RWX) */
492	PGMPAGETYPE_ROM_SHADOW,
493	/** ROM page. (R-X) */
494	PGMPAGETYPE_ROM,
495	/** MMIO page. (---) */
496	PGMPAGETYPE_MMIO,
497	/** End of valid entries. */
498	PGMPAGETYPE_END
499	} PGMPAGETYPE;
500	AssertCompile(PGMPAGETYPE_END < 7);
501
502	/** @name Page type predicates.
503	* @{ */
504	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
505	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
506	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
507	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
508	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
509	/** @} */
510
511
512	/**
513	* A Physical Guest Page tracking structure.
514	*
515	* The format of this structure is complicated because we have to fit a lot
516	* of information into as few bits as possible. The format is also subject
517	* to change (there is one comming up soon). Which means that for we'll be
518	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
519	* accessess to the structure.
520	*/
521	typedef struct PGMPAGE
522	{
523	/** The physical address and a whole lot of other stuff. All bits are used! */
524	RTHCPHYS HCPhys;
525	/** The page state. */
526	uint32_t u2StateX : 2;
527	/** Flag indicating that a write monitored page was written to when set. */
528	uint32_t fWrittenToX : 1;
529	/** For later. */
530	uint32_t fSomethingElse : 1;
531	/** The Page ID.
532	* @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
533	* The HCPhys will be 100% static. */
534	uint32_t idPageX : 28;
535	/** The page type (PGMPAGETYPE). */
536	uint32_t u3Type : 3;
537	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
538	uint32_t u2HandlerPhysStateX : 2;
539	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
540	uint32_t u2HandlerVirtStateX : 2;
541	uint32_t u29B : 25;
542	} PGMPAGE;
543	AssertCompileSize(PGMPAGE, 16);
544	/** Pointer to a physical guest page. */
545	typedef PGMPAGE *PPGMPAGE;
546	/** Pointer to a const physical guest page. */
547	typedef const PGMPAGE *PCPGMPAGE;
548	/** Pointer to a physical guest page pointer. */
549	typedef PPGMPAGE *PPPGMPAGE;
550
551
552	/**
553	* Clears the page structure.
554	* @param pPage Pointer to the physical guest page tracking structure.
555	*/
556	#define PGM_PAGE_CLEAR(pPage) \
557	do { \
558	(pPage)->HCPhys = 0; \
559	(pPage)->u2StateX = 0; \
560	(pPage)->fWrittenToX = 0; \
561	(pPage)->fSomethingElse = 0; \
562	(pPage)->idPageX = 0; \
563	(pPage)->u3Type = 0; \
564	(pPage)->u29B = 0; \
565	} while (0)
566
567	/**
568	* Initializes the page structure.
569	* @param pPage Pointer to the physical guest page tracking structure.
570	*/
571	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
572	do { \
573	(pPage)->HCPhys = (_HCPhys); \
574	(pPage)->u2StateX = (_uState); \
575	(pPage)->fWrittenToX = 0; \
576	(pPage)->fSomethingElse = 0; \
577	(pPage)->idPageX = (_idPage); \
578	/(pPage)->u3Type = (_uType); - later / \
579	PGM_PAGE_SET_TYPE(pPage, _uType); \
580	(pPage)->u29B = 0; \
581	} while (0)
582
583	/**
584	* Initializes the page structure of a ZERO page.
585	* @param pPage Pointer to the physical guest page tracking structure.
586	*/
587	#ifdef VBOX_WITH_NEW_PHYS_CODE
588	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
589	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
590	#else
591	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
592	PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
593	#endif
594	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
595	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
596	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
597
598
599	/** @name The Page state, PGMPAGE::u2StateX.
600	* @{ */
601	/** The zero page.
602	* This is a per-VM page that's never ever mapped writable. */
603	#define PGM_PAGE_STATE_ZERO 0
604	/** A allocated page.
605	* This is a per-VM page allocated from the page pool (or wherever
606	* we get MMIO2 pages from if the type is MMIO2).
607	*/
608	#define PGM_PAGE_STATE_ALLOCATED 1
609	/** A allocated page that's being monitored for writes.
610	* The shadow page table mappings are read-only. When a write occurs, the
611	* fWrittenTo member is set, the page remapped as read-write and the state
612	* moved back to allocated. */
613	#define PGM_PAGE_STATE_WRITE_MONITORED 2
614	/** The page is shared, aka. copy-on-write.
615	* This is a page that's shared with other VMs. */
616	#define PGM_PAGE_STATE_SHARED 3
617	/** @} */
618
619
620	/**
621	* Gets the page state.
622	* @returns page state (PGM_PAGE_STATE_*).
623	* @param pPage Pointer to the physical guest page tracking structure.
624	*/
625	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
626
627	/**
628	* Sets the page state.
629	* @param pPage Pointer to the physical guest page tracking structure.
630	* @param _uState The new page state.
631	*/
632	#define PGM_PAGE_SET_STATE(pPage, _uState) \
633	do { (pPage)->u2StateX = (_uState); } while (0)
634
635
636	/**
637	* Gets the host physical address of the guest page.
638	* @returns host physical address (RTHCPHYS).
639	* @param pPage Pointer to the physical guest page tracking structure.
640	*/
641	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
642
643	/**
644	* Sets the host physical address of the guest page.
645	* @param pPage Pointer to the physical guest page tracking structure.
646	* @param _HCPhys The new host physical address.
647	*/
648	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
649	do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
650	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
651
652	/**
653	* Get the Page ID.
654	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
655	* @param pPage Pointer to the physical guest page tracking structure.
656	*/
657	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
658	/* later:
659	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
660	\| ((uint32_t)(pPage)->HCPhys & 0xfff) )
661	*/
662	/**
663	* Sets the Page ID.
664	* @param pPage Pointer to the physical guest page tracking structure.
665	*/
666	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
667	/* later:
668	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
669	\| ((_idPage) & 0xfff) \
670	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
671	*/
672
673	/**
674	* Get the Chunk ID.
675	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
676	* @param pPage Pointer to the physical guest page tracking structure.
677	*/
678	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
679	/* later:
680	#if GMM_CHUNKID_SHIFT == 12
681	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
682	#elif GMM_CHUNKID_SHIFT > 12
683	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
684	#elif GMM_CHUNKID_SHIFT < 12
685	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
686	\| ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
687	#else
688	# error "GMM_CHUNKID_SHIFT isn't defined or something."
689	#endif
690	*/
691
692	/**
693	* Get the index of the page within the allocaiton chunk.
694	* @returns The page index.
695	* @param pPage Pointer to the physical guest page tracking structure.
696	*/
697	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
698	/* later:
699	#if GMM_CHUNKID_SHIFT <= 12
700	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
701	#else
702	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
703	\| ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
704	#endif
705	*/
706
707
708	/**
709	* Gets the page type.
710	* @returns The page type.
711	* @param pPage Pointer to the physical guest page tracking structure.
712	*/
713	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
714
715	/**
716	* Sets the page type.
717	* @param pPage Pointer to the physical guest page tracking structure.
718	* @param _enmType The new page type (PGMPAGETYPE).
719	*/
720	#ifdef VBOX_WITH_NEW_PHYS_CODE
721	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
722	do { (pPage)->u3Type = (_enmType); } while (0)
723	#else
724	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
725	do { \
726	(pPage)->u3Type = (_enmType); \
727	if ((_enmType) == PGMPAGETYPE_ROM) \
728	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM; \
729	else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
730	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2; \
731	else if ((_enmType) == PGMPAGETYPE_MMIO2) \
732	(pPage)->HCPhys \|= MM_RAM_FLAGS_MMIO2; \
733	} while (0)
734	#endif
735
736
737	/**
738	* Checks if the page is 'reserved'.
739	* @returns true/false.
740	* @param pPage Pointer to the physical guest page tracking structure.
741	*/
742	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
743
744	/**
745	* Checks if the page is marked for MMIO.
746	* @returns true/false.
747	* @param pPage Pointer to the physical guest page tracking structure.
748	*/
749	#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
750
751	/**
752	* Checks if the page is backed by the ZERO page.
753	* @returns true/false.
754	* @param pPage Pointer to the physical guest page tracking structure.
755	*/
756	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
757
758	/**
759	* Checks if the page is backed by a SHARED page.
760	* @returns true/false.
761	* @param pPage Pointer to the physical guest page tracking structure.
762	*/
763	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
764
765
766	/**
767	* Marks the paget as written to (for GMM change monitoring).
768	* @param pPage Pointer to the physical guest page tracking structure.
769	*/
770	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
771
772	/**
773	* Clears the written-to indicator.
774	* @param pPage Pointer to the physical guest page tracking structure.
775	*/
776	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
777
778	/**
779	* Checks if the page was marked as written-to.
780	* @returns true/false.
781	* @param pPage Pointer to the physical guest page tracking structure.
782	*/
783	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
784
785
786	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
787	*
788	* @remarks The values are assigned in order of priority, so we can calculate
789	* the correct state for a page with different handlers installed.
790	* @{ */
791	/** No handler installed. */
792	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
793	/** Monitoring is temporarily disabled. */
794	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
795	/** Write access is monitored. */
796	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
797	/** All access is monitored. */
798	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
799	/** @} */
800
801	/**
802	* Gets the physical access handler state of a page.
803	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
804	* @param pPage Pointer to the physical guest page tracking structure.
805	*/
806	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
807
808	/**
809	* Sets the physical access handler state of a page.
810	* @param pPage Pointer to the physical guest page tracking structure.
811	* @param _uState The new state value.
812	*/
813	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
814	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
815
816	/**
817	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
818	* @returns true/false
819	* @param pPage Pointer to the physical guest page tracking structure.
820	*/
821	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
822
823	/**
824	* Checks if the page has any active physical access handlers.
825	* @returns true/false
826	* @param pPage Pointer to the physical guest page tracking structure.
827	*/
828	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
829
830
831	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
832	*
833	* @remarks The values are assigned in order of priority, so we can calculate
834	* the correct state for a page with different handlers installed.
835	* @{ */
836	/** No handler installed. */
837	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
838	/* 1 is reserved so the lineup is identical with the physical ones. */
839	/** Write access is monitored. */
840	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
841	/** All access is monitored. */
842	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
843	/** @} */
844
845	/**
846	* Gets the virtual access handler state of a page.
847	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
848	* @param pPage Pointer to the physical guest page tracking structure.
849	*/
850	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
851
852	/**
853	* Sets the virtual access handler state of a page.
854	* @param pPage Pointer to the physical guest page tracking structure.
855	* @param _uState The new state value.
856	*/
857	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
858	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
859
860	/**
861	* Checks if the page has any virtual access handlers.
862	* @returns true/false
863	* @param pPage Pointer to the physical guest page tracking structure.
864	*/
865	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
866
867	/**
868	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
869	* virtual handlers.
870	* @returns true/false
871	* @param pPage Pointer to the physical guest page tracking structure.
872	*/
873	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
874
875
876
877	/**
878	* Checks if the page has any access handlers, including temporarily disabled ones.
879	* @returns true/false
880	* @param pPage Pointer to the physical guest page tracking structure.
881	*/
882	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
883	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
884	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
885
886	/**
887	* Checks if the page has any active access handlers.
888	* @returns true/false
889	* @param pPage Pointer to the physical guest page tracking structure.
890	*/
891	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
892	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
893	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
894
895	/**
896	* Checks if the page has any active access handlers catching all accesses.
897	* @returns true/false
898	* @param pPage Pointer to the physical guest page tracking structure.
899	*/
900	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
901	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
902	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
903
904
905	/**
906	* Ram range for GC Phys to HC Phys conversion.
907	*
908	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
909	* conversions too, but we'll let MM handle that for now.
910	*
911	* This structure is used by linked lists in both GC and HC.
912	*/
913	typedef struct PGMRAMRANGE
914	{
915	/** Pointer to the next RAM range - for R3. */
916	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
917	/** Pointer to the next RAM range - for R0. */
918	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
919	/** Pointer to the next RAM range - for GC. */
920	RCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
921	/** Pointer alignment. */
922	RTRCPTR GCPtrAlignment;
923	/** Start of the range. Page aligned. */
924	RTGCPHYS GCPhys;
925	/** Last address in the range (inclusive). Page aligned (-1). */
926	RTGCPHYS GCPhysLast;
927	/** Size of the range. (Page aligned of course). */
928	RTGCPHYS cb;
929	/** MM_RAM_* flags */
930	uint32_t fFlags;
931	#ifdef VBOX_WITH_NEW_PHYS_CODE
932	uint32_t u32Alignment; /*< alignment. /
933	#else
934	/** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
935	RCPTRTYPE(PRTHCPTR) pavHCChunkGC;
936	/** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
937	R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
938	#endif
939	/** Start of the HC mapping of the range. This is only used for MMIO2. */
940	R3PTRTYPE(void *) pvHC;
941	/** The range description. */
942	R3PTRTYPE(const char *) pszDesc;
943
944	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
945	#ifdef VBOX_WITH_NEW_PHYS_CODE
946	uint32_t au32Reserved[2];
947	#elif HC_ARCH_BITS == 32
948	uint32_t au32Reserved[1];
949	#endif
950
951	/** Array of physical guest page tracking structures. */
952	PGMPAGE aPages[1];
953	} PGMRAMRANGE;
954	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
955	typedef PGMRAMRANGE *PPGMRAMRANGE;
956
957	/** Return hc ptr corresponding to the ram range and physical offset */
958	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
959	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
960	: (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
961
962	/**
963	* Per page tracking structure for ROM image.
964	*
965	* A ROM image may have a shadow page, in which case we may have
966	* two pages backing it. This structure contains the PGMPAGE for
967	* both while PGMRAMRANGE have a copy of the active one. It is
968	* important that these aren't out of sync in any regard other
969	* than page pool tracking data.
970	*/
971	typedef struct PGMROMPAGE
972	{
973	/** The page structure for the virgin ROM page. */
974	PGMPAGE Virgin;
975	/** The page structure for the shadow RAM page. */
976	PGMPAGE Shadow;
977	/** The current protection setting. */
978	PGMROMPROT enmProt;
979	/** Pad the structure size to a multiple of 8. */
980	uint32_t u32Padding;
981	} PGMROMPAGE;
982	/** Pointer to a ROM page tracking structure. */
983	typedef PGMROMPAGE *PPGMROMPAGE;
984
985
986	/**
987	* A registered ROM image.
988	*
989	* This is needed to keep track of ROM image since they generally
990	* intrude into a PGMRAMRANGE. It also keeps track of additional
991	* info like the two page sets (read-only virgin and read-write shadow),
992	* the current state of each page.
993	*
994	* Because access handlers cannot easily be executed in a different
995	* context, the ROM ranges needs to be accessible and in all contexts.
996	*/
997	typedef struct PGMROMRANGE
998	{
999	/** Pointer to the next range - R3. */
1000	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1001	/** Pointer to the next range - R0. */
1002	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1003	/** Pointer to the next range - GC. */
1004	RCPTRTYPE(struct PGMROMRANGE *) pNextGC;
1005	/** Pointer alignment */
1006	RTRCPTR GCPtrAlignment;
1007	/** Address of the range. */
1008	RTGCPHYS GCPhys;
1009	/** Address of the last byte in the range. */
1010	RTGCPHYS GCPhysLast;
1011	/** Size of the range. */
1012	RTGCPHYS cb;
1013	/** The flags (PGMPHYS_ROM_FLAG_). /
1014	uint32_t fFlags;
1015	/*< Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. /
1016	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1017	/** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1018	* This is used for strictness checks. */
1019	R3PTRTYPE(const void *) pvOriginal;
1020	/** The ROM description. */
1021	R3PTRTYPE(const char *) pszDesc;
1022	/** The per page tracking structures. */
1023	PGMROMPAGE aPages[1];
1024	} PGMROMRANGE;
1025	/** Pointer to a ROM range. */
1026	typedef PGMROMRANGE *PPGMROMRANGE;
1027
1028
1029	/**
1030	* A registered MMIO2 (= Device RAM) range.
1031	*
1032	* There are a few reason why we need to keep track of these
1033	* registrations. One of them is the deregistration & cleanup
1034	* stuff, while another is that the PGMRAMRANGE associated with
1035	* such a region may have to be removed from the ram range list.
1036	*
1037	* Overlapping with a RAM range has to be 100% or none at all. The
1038	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1039	* meditation will be raised if a partial overlap or an overlap of
1040	* ROM pages is encountered. On an overlap we will free all the
1041	* existing RAM pages and put in the ram range pages instead.
1042	*/
1043	typedef struct PGMMMIO2RANGE
1044	{
1045	/** The owner of the range. (a device) */
1046	PPDMDEVINSR3 pDevInsR3;
1047	/** Pointer to the ring-3 mapping of the allocation. */
1048	RTR3PTR pvR3;
1049	/** Pointer to the next range - R3. */
1050	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1051	/** Whether it's mapped or not. */
1052	bool fMapped;
1053	/** Whether it's overlapping or not. */
1054	bool fOverlapping;
1055	/** The PCI region number.
1056	* @remarks This ASSUMES that nobody will ever really need to have multiple
1057	* PCI devices with matching MMIO region numbers on a single device. */
1058	uint8_t iRegion;
1059	/*< Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. /
1060	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1061	/** The associated RAM range. */
1062	PGMRAMRANGE RamRange;
1063	} PGMMMIO2RANGE;
1064	/** Pointer to a MMIO2 range. */
1065	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1066
1067
1068
1069
1070	/** @todo r=bird: fix typename. */
1071	/**
1072	* PGMPhysRead/Write cache entry
1073	*/
1074	typedef struct PGMPHYSCACHE_ENTRY
1075	{
1076	/** HC pointer to physical page */
1077	R3PTRTYPE(uint8_t *) pbHC;
1078	/** GC Physical address for cache entry */
1079	RTGCPHYS GCPhys;
1080	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1081	RTGCPHYS u32Padding0; /*< alignment padding. /
1082	#endif
1083	} PGMPHYSCACHE_ENTRY;
1084
1085	/**
1086	* PGMPhysRead/Write cache to reduce REM memory access overhead
1087	*/
1088	typedef struct PGMPHYSCACHE
1089	{
1090	/** Bitmap of valid cache entries */
1091	uint64_t aEntries;
1092	/** Cache entries */
1093	PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1094	} PGMPHYSCACHE;
1095
1096
1097	/** Pointer to an allocation chunk ring-3 mapping. */
1098	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1099	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1100	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1101
1102	/**
1103	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1104	*
1105	* The primary tree (Core) uses the chunk id as key.
1106	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1107	*/
1108	typedef struct PGMCHUNKR3MAP
1109	{
1110	/** The key is the chunk id. */
1111	AVLU32NODECORE Core;
1112	/** The key is the ageing sequence number. */
1113	AVLLU32NODECORE AgeCore;
1114	/** The current age thingy. */
1115	uint32_t iAge;
1116	/** The current reference count. */
1117	uint32_t volatile cRefs;
1118	/** The current permanent reference count. */
1119	uint32_t volatile cPermRefs;
1120	/** The mapping address. */
1121	void *pv;
1122	} PGMCHUNKR3MAP;
1123
1124	/**
1125	* Allocation chunk ring-3 mapping TLB entry.
1126	*/
1127	typedef struct PGMCHUNKR3MAPTLBE
1128	{
1129	/** The chunk id. */
1130	uint32_t volatile idChunk;
1131	#if HC_ARCH_BITS == 64
1132	uint32_t u32Padding; /*< alignment padding. /
1133	#endif
1134	/** The chunk map. */
1135	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1136	} PGMCHUNKR3MAPTLBE;
1137	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1138	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1139
1140	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1141	* @remark Must be a power of two value. */
1142	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1143
1144	/**
1145	* Allocation chunk ring-3 mapping TLB.
1146	*
1147	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1148	* At first glance this might look kinda odd since AVL trees are
1149	* supposed to give the most optimial lookup times of all trees
1150	* due to their balancing. However, take a tree with 1023 nodes
1151	* in it, that's 10 levels, meaning that most searches has to go
1152	* down 9 levels before they find what they want. This isn't fast
1153	* compared to a TLB hit. There is the factor of cache misses,
1154	* and of course the problem with trees and branch prediction.
1155	* This is why we use TLBs in front of most of the trees.
1156	*
1157	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1158	* difficult when we switch to inlined AVL trees (from kStuff).
1159	*/
1160	typedef struct PGMCHUNKR3MAPTLB
1161	{
1162	/** The TLB entries. */
1163	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1164	} PGMCHUNKR3MAPTLB;
1165
1166	/**
1167	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1168	* @returns Chunk TLB index.
1169	* @param idChunk The Chunk ID.
1170	*/
1171	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1172
1173
1174	/**
1175	* Ring-3 guest page mapping TLB entry.
1176	* @remarks used in ring-0 as well at the moment.
1177	*/
1178	typedef struct PGMPAGER3MAPTLBE
1179	{
1180	/** Address of the page. */
1181	RTGCPHYS volatile GCPhys;
1182	/** The guest page. */
1183	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1184	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1185	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1186	/** The address */
1187	R3R0PTRTYPE(void *) volatile pv;
1188	#if HC_ARCH_BITS == 32
1189	uint32_t u32Padding; /*< alignment padding. /
1190	#endif
1191	} PGMPAGER3MAPTLBE;
1192	/** Pointer to an entry in the HC physical TLB. */
1193	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1194
1195
1196	/** The number of entries in the ring-3 guest page mapping TLB.
1197	* @remarks The value must be a power of two. */
1198	#define PGM_PAGER3MAPTLB_ENTRIES 64
1199
1200	/**
1201	* Ring-3 guest page mapping TLB.
1202	* @remarks used in ring-0 as well at the moment.
1203	*/
1204	typedef struct PGMPAGER3MAPTLB
1205	{
1206	/** The TLB entries. */
1207	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1208	} PGMPAGER3MAPTLB;
1209	/** Pointer to the ring-3 guest page mapping TLB. */
1210	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1211
1212	/**
1213	* Calculates the index of the TLB entry for the specified guest page.
1214	* @returns Physical TLB index.
1215	* @param GCPhys The guest physical address.
1216	*/
1217	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1218
1219
1220	/** @name Context neutrual page mapper TLB.
1221	*
1222	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1223	* code is writting in a kind of context neutrual way. Time will show whether
1224	* this actually makes sense or not...
1225	*
1226	* @{ */
1227	/** @typedef PPGMPAGEMAPTLB
1228	* The page mapper TLB pointer type for the current context. */
1229	/** @typedef PPGMPAGEMAPTLB
1230	* The page mapper TLB entry pointer type for the current context. */
1231	/** @typedef PPGMPAGEMAPTLB
1232	* The page mapper TLB entry pointer pointer type for the current context. */
1233	/** @def PGMPAGEMAPTLB_ENTRIES
1234	* The number of TLB entries in the page mapper TLB for the current context. */
1235	/** @def PGM_PAGEMAPTLB_IDX
1236	* Calculate the TLB index for a guest physical address.
1237	* @returns The TLB index.
1238	* @param GCPhys The guest physical address. */
1239	/** @typedef PPGMPAGEMAP
1240	* Pointer to a page mapper unit for current context. */
1241	/** @typedef PPPGMPAGEMAP
1242	* Pointer to a page mapper unit pointer for current context. */
1243	#ifdef IN_GC
1244	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1245	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1246	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1247	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1248	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1249	typedef void * PPGMPAGEMAP;
1250	typedef void ** PPPGMPAGEMAP;
1251	//#elif IN_RING0
1252	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1253	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1254	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1255	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1256	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1257	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1258	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1259	#else
1260	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1261	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1262	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1263	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1264	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1265	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1266	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1267	#endif
1268	/** @} */
1269
1270
1271	/** @name PGM Pool Indexes.
1272	* Aka. the unique shadow page identifier.
1273	* @{ */
1274	/** NIL page pool IDX. */
1275	#define NIL_PGMPOOL_IDX 0
1276	/** The first normal index. */
1277	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1278	/** Page directory (32-bit root). */
1279	#define PGMPOOL_IDX_PD 1
1280	/** The extended PAE page directory (2048 entries, works as root currently). */
1281	#define PGMPOOL_IDX_PAE_PD 2
1282	/** PAE Page Directory Table 0. */
1283	#define PGMPOOL_IDX_PAE_PD_0 3
1284	/** PAE Page Directory Table 1. */
1285	#define PGMPOOL_IDX_PAE_PD_1 4
1286	/** PAE Page Directory Table 2. */
1287	#define PGMPOOL_IDX_PAE_PD_2 5
1288	/** PAE Page Directory Table 3. */
1289	#define PGMPOOL_IDX_PAE_PD_3 6
1290	/** Page Directory Pointer Table (PAE root, not currently used). */
1291	#define PGMPOOL_IDX_PDPT 7
1292	/** AMD64 CR3 level index.*/
1293	#define PGMPOOL_IDX_AMD64_CR3 8
1294	/** Nested paging root.*/
1295	#define PGMPOOL_IDX_NESTED_ROOT 9
1296	/** The first normal index. */
1297	#define PGMPOOL_IDX_FIRST 10
1298	/** The last valid index. (inclusive, 14 bits) */
1299	#define PGMPOOL_IDX_LAST 0x3fff
1300	/** @} */
1301
1302	/** The NIL index for the parent chain. */
1303	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1304
1305	/**
1306	* Node in the chain linking a shadowed page to it's parent (user).
1307	*/
1308	#pragma pack(1)
1309	typedef struct PGMPOOLUSER
1310	{
1311	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1312	uint16_t iNext;
1313	/** The user page index. */
1314	uint16_t iUser;
1315	/** Index into the user table. */
1316	uint32_t iUserTable;
1317	} PGMPOOLUSER, *PPGMPOOLUSER;
1318	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1319	#pragma pack()
1320
1321
1322	/** The NIL index for the phys ext chain. */
1323	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1324
1325	/**
1326	* Node in the chain of physical cross reference extents.
1327	*/
1328	#pragma pack(1)
1329	typedef struct PGMPOOLPHYSEXT
1330	{
1331	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1332	uint16_t iNext;
1333	/** The user page index. */
1334	uint16_t aidx[3];
1335	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1336	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1337	#pragma pack()
1338
1339
1340	/**
1341	* The kind of page that's being shadowed.
1342	*/
1343	typedef enum PGMPOOLKIND
1344	{
1345	/** The virtual invalid 0 entry. */
1346	PGMPOOLKIND_INVALID = 0,
1347	/** The entry is free (=unused). */
1348	PGMPOOLKIND_FREE,
1349
1350	/** Shw: 32-bit page table; Gst: no paging */
1351	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1352	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1353	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1354	/** Shw: 32-bit page table; Gst: 4MB page. */
1355	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1356	/** Shw: PAE page table; Gst: no paging */
1357	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1358	/** Shw: PAE page table; Gst: 32-bit page table. */
1359	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1360	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1361	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1362	/** Shw: PAE page table; Gst: PAE page table. */
1363	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1364	/** Shw: PAE page table; Gst: 2MB page. */
1365	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1366
1367	/** Shw: PAE page directory; Gst: 32-bit page directory. */
1368	PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1369	/** Shw: PAE page directory; Gst: PAE page directory. */
1370	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1371
1372	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1373	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1374	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1375	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1376	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1377	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1378	/** Shw: 64-bit page directory table; Gst: no paging */
1379	PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1380
1381	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1382	PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1383
1384	/** Shw: Root 32-bit page directory. */
1385	PGMPOOLKIND_ROOT_32BIT_PD,
1386	/** Shw: Root PAE page directory */
1387	PGMPOOLKIND_ROOT_PAE_PD,
1388	/** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1389	PGMPOOLKIND_ROOT_PDPT,
1390	/** Shw: Root Nested paging table. */
1391	PGMPOOLKIND_ROOT_NESTED,
1392
1393	/** The last valid entry. */
1394	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1395	} PGMPOOLKIND;
1396
1397
1398	/**
1399	* The tracking data for a page in the pool.
1400	*/
1401	typedef struct PGMPOOLPAGE
1402	{
1403	/** AVL node code with the (HC) physical address of this page. */
1404	AVLOHCPHYSNODECORE Core;
1405	/** Pointer to the HC mapping of the page. */
1406	R3R0PTRTYPE(void *) pvPageHC;
1407	/** The guest physical address. */
1408	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1409	uint32_t Alignment0;
1410	#endif
1411	RTGCPHYS GCPhys;
1412	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1413	uint8_t enmKind;
1414	uint8_t bPadding;
1415	/** The index of this page. */
1416	uint16_t idx;
1417	/** The next entry in the list this page currently resides in.
1418	* It's either in the free list or in the GCPhys hash. */
1419	uint16_t iNext;
1420	#ifdef PGMPOOL_WITH_USER_TRACKING
1421	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1422	uint16_t iUserHead;
1423	/** The number of present entries. */
1424	uint16_t cPresent;
1425	/** The first entry in the table which is present. */
1426	uint16_t iFirstPresent;
1427	#endif
1428	#ifdef PGMPOOL_WITH_MONITORING
1429	/** The number of modifications to the monitored page. */
1430	uint16_t cModifications;
1431	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1432	uint16_t iModifiedNext;
1433	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1434	uint16_t iModifiedPrev;
1435	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1436	uint16_t iMonitoredNext;
1437	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1438	uint16_t iMonitoredPrev;
1439	#endif
1440	#ifdef PGMPOOL_WITH_CACHE
1441	/** The next page in the age list. */
1442	uint16_t iAgeNext;
1443	/** The previous page in the age list. */
1444	uint16_t iAgePrev;
1445	#endif /* PGMPOOL_WITH_CACHE */
1446	/** Used to indicate that the page is zeroed. */
1447	bool fZeroed;
1448	/** Used to indicate that a PT has non-global entries. */
1449	bool fSeenNonGlobal;
1450	/** Used to indicate that we're monitoring writes to the guest page. */
1451	bool fMonitored;
1452	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1453	* (All pages are in the age list.) */
1454	bool fCached;
1455	/** This is used by the R3 access handlers when invoked by an async thread.
1456	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1457	bool volatile fReusedFlushPending;
1458	/** Used to indicate that the guest is mapping the page is also used as a CR3.
1459	* In these cases the access handler acts differently and will check
1460	* for mapping conflicts like the normal CR3 handler.
1461	* @todo When we change the CR3 shadowing to use pool pages, this flag can be
1462	* replaced by a list of pages which share access handler.
1463	*/
1464	bool fCR3Mix;
1465	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1466
1467
1468	#ifdef PGMPOOL_WITH_CACHE
1469	/** The hash table size. */
1470	# define PGMPOOL_HASH_SIZE 0x40
1471	/** The hash function. */
1472	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1473	#endif
1474
1475
1476	/**
1477	* The shadow page pool instance data.
1478	*
1479	* It's all one big allocation made at init time, except for the
1480	* pages that is. The user nodes follows immediatly after the
1481	* page structures.
1482	*/
1483	typedef struct PGMPOOL
1484	{
1485	/** The VM handle - HC Ptr. */
1486	R3R0PTRTYPE(PVM) pVMHC;
1487	/** The VM handle - GC Ptr. */
1488	RCPTRTYPE(PVM) pVMGC;
1489	/** The max pool size. This includes the special IDs. */
1490	uint16_t cMaxPages;
1491	/** The current pool size. */
1492	uint16_t cCurPages;
1493	/** The head of the free page list. */
1494	uint16_t iFreeHead;
1495	/* Padding. */
1496	uint16_t u16Padding;
1497	#ifdef PGMPOOL_WITH_USER_TRACKING
1498	/** Head of the chain of free user nodes. */
1499	uint16_t iUserFreeHead;
1500	/** The number of user nodes we've allocated. */
1501	uint16_t cMaxUsers;
1502	/** The number of present page table entries in the entire pool. */
1503	uint32_t cPresent;
1504	/** Pointer to the array of user nodes - GC pointer. */
1505	RCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1506	/** Pointer to the array of user nodes - HC pointer. */
1507	R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1508	#endif /* PGMPOOL_WITH_USER_TRACKING */
1509	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1510	/** Head of the chain of free phys ext nodes. */
1511	uint16_t iPhysExtFreeHead;
1512	/** The number of user nodes we've allocated. */
1513	uint16_t cMaxPhysExts;
1514	/** Pointer to the array of physical xref extent - GC pointer. */
1515	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1516	/** Pointer to the array of physical xref extent nodes - HC pointer. */
1517	R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1518	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1519	#ifdef PGMPOOL_WITH_CACHE
1520	/** Hash table for GCPhys addresses. */
1521	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1522	/** The head of the age list. */
1523	uint16_t iAgeHead;
1524	/** The tail of the age list. */
1525	uint16_t iAgeTail;
1526	/** Set if the cache is enabled. */
1527	bool fCacheEnabled;
1528	#endif /* PGMPOOL_WITH_CACHE */
1529	#ifdef PGMPOOL_WITH_MONITORING
1530	/** Head of the list of modified pages. */
1531	uint16_t iModifiedHead;
1532	/** The current number of modified pages. */
1533	uint16_t cModifiedPages;
1534	/** Access handler, GC. */
1535	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1536	/** Access handler, R0. */
1537	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1538	/** Access handler, R3. */
1539	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1540	/** The access handler description (HC ptr). */
1541	R3PTRTYPE(const char *) pszAccessHandler;
1542	#endif /* PGMPOOL_WITH_MONITORING */
1543	/** The number of pages currently in use. */
1544	uint16_t cUsedPages;
1545	#ifdef VBOX_WITH_STATISTICS
1546	/** The high wather mark for cUsedPages. */
1547	uint16_t cUsedPagesHigh;
1548	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1549	/** Profiling pgmPoolAlloc(). */
1550	STAMPROFILEADV StatAlloc;
1551	/** Profiling pgmPoolClearAll(). */
1552	STAMPROFILE StatClearAll;
1553	/** Profiling pgmPoolFlushAllInt(). */
1554	STAMPROFILE StatFlushAllInt;
1555	/** Profiling pgmPoolFlushPage(). */
1556	STAMPROFILE StatFlushPage;
1557	/** Profiling pgmPoolFree(). */
1558	STAMPROFILE StatFree;
1559	/** Profiling time spent zeroing pages. */
1560	STAMPROFILE StatZeroPage;
1561	# ifdef PGMPOOL_WITH_USER_TRACKING
1562	/** Profiling of pgmPoolTrackDeref. */
1563	STAMPROFILE StatTrackDeref;
1564	/** Profiling pgmTrackFlushGCPhysPT. */
1565	STAMPROFILE StatTrackFlushGCPhysPT;
1566	/** Profiling pgmTrackFlushGCPhysPTs. */
1567	STAMPROFILE StatTrackFlushGCPhysPTs;
1568	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1569	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1570	/** Number of times we've been out of user records. */
1571	STAMCOUNTER StatTrackFreeUpOneUser;
1572	# endif
1573	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1574	/** Profiling deref activity related tracking GC physical pages. */
1575	STAMPROFILE StatTrackDerefGCPhys;
1576	/** Number of linear searches for a HCPhys in the ram ranges. */
1577	STAMCOUNTER StatTrackLinearRamSearches;
1578	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1579	STAMCOUNTER StamTrackPhysExtAllocFailures;
1580	# endif
1581	# ifdef PGMPOOL_WITH_MONITORING
1582	/** Profiling the GC PT access handler. */
1583	STAMPROFILE StatMonitorGC;
1584	/** Times we've failed interpreting the instruction. */
1585	STAMCOUNTER StatMonitorGCEmulateInstr;
1586	/** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1587	STAMPROFILE StatMonitorGCFlushPage;
1588	/** Times we've detected fork(). */
1589	STAMCOUNTER StatMonitorGCFork;
1590	/** Profiling the GC access we've handled (except REP STOSD). */
1591	STAMPROFILE StatMonitorGCHandled;
1592	/** Times we've failed interpreting a patch code instruction. */
1593	STAMCOUNTER StatMonitorGCIntrFailPatch1;
1594	/** Times we've failed interpreting a patch code instruction during flushing. */
1595	STAMCOUNTER StatMonitorGCIntrFailPatch2;
1596	/** The number of times we've seen rep prefixes we can't handle. */
1597	STAMCOUNTER StatMonitorGCRepPrefix;
1598	/** Profiling the REP STOSD cases we've handled. */
1599	STAMPROFILE StatMonitorGCRepStosd;
1600
1601	/** Profiling the HC PT access handler. */
1602	STAMPROFILE StatMonitorHC;
1603	/** Times we've failed interpreting the instruction. */
1604	STAMCOUNTER StatMonitorHCEmulateInstr;
1605	/** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1606	STAMPROFILE StatMonitorHCFlushPage;
1607	/** Times we've detected fork(). */
1608	STAMCOUNTER StatMonitorHCFork;
1609	/** Profiling the HC access we've handled (except REP STOSD). */
1610	STAMPROFILE StatMonitorHCHandled;
1611	/** The number of times we've seen rep prefixes we can't handle. */
1612	STAMCOUNTER StatMonitorHCRepPrefix;
1613	/** Profiling the REP STOSD cases we've handled. */
1614	STAMPROFILE StatMonitorHCRepStosd;
1615	/** The number of times we're called in an async thread an need to flush. */
1616	STAMCOUNTER StatMonitorHCAsync;
1617	/** The high wather mark for cModifiedPages. */
1618	uint16_t cModifiedPagesHigh;
1619	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1620	# endif
1621	# ifdef PGMPOOL_WITH_CACHE
1622	/** The number of cache hits. */
1623	STAMCOUNTER StatCacheHits;
1624	/** The number of cache misses. */
1625	STAMCOUNTER StatCacheMisses;
1626	/** The number of times we've got a conflict of 'kind' in the cache. */
1627	STAMCOUNTER StatCacheKindMismatches;
1628	/** Number of times we've been out of pages. */
1629	STAMCOUNTER StatCacheFreeUpOne;
1630	/** The number of cacheable allocations. */
1631	STAMCOUNTER StatCacheCacheable;
1632	/** The number of uncacheable allocations. */
1633	STAMCOUNTER StatCacheUncacheable;
1634	# endif
1635	#elif HC_ARCH_BITS == 64
1636	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1637	#endif
1638	/** The AVL tree for looking up a page by its HC physical address. */
1639	AVLOHCPHYSTREE HCPhysTree;
1640	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1641	/** Array of pages. (cMaxPages in length)
1642	* The Id is the index into thist array.
1643	*/
1644	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1645	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1646
1647
1648	/** @def PGMPOOL_PAGE_2_PTR
1649	* Maps a pool page pool into the current context.
1650	*
1651	* @returns VBox status code.
1652	* @param pVM The VM handle.
1653	* @param pPage The pool page.
1654	*
1655	* @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1656	* small page window employeed by that function. Be careful.
1657	* @remark There is no need to assert on the result.
1658	*/
1659	#ifdef IN_GC
1660	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1661	#else
1662	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1663	#endif
1664
1665
1666	/**
1667	* Trees are using self relative offsets as pointers.
1668	* So, all its data, including the root pointer, must be in the heap for HC and GC
1669	* to have the same layout.
1670	*/
1671	typedef struct PGMTREES
1672	{
1673	/** Physical access handlers (AVL range+offsetptr tree). */
1674	AVLROGCPHYSTREE PhysHandlers;
1675	/** Virtual access handlers (AVL range + GC ptr tree). */
1676	AVLROGCPTRTREE VirtHandlers;
1677	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1678	AVLROGCPHYSTREE PhysToVirtHandlers;
1679	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1680	AVLROGCPTRTREE HyperVirtHandlers;
1681	} PGMTREES;
1682	/** Pointer to PGM trees. */
1683	typedef PGMTREES *PPGMTREES;
1684
1685
1686	/** @name Paging mode macros
1687	* @{ */
1688	#ifdef IN_GC
1689	# define PGM_CTX(a,b) a##GC##b
1690	# define PGM_CTX_STR(a,b) a "GC" b
1691	# define PGM_CTX_DECL(type) PGMGCDECL(type)
1692	#else
1693	# ifdef IN_RING3
1694	# define PGM_CTX(a,b) a##R3##b
1695	# define PGM_CTX_STR(a,b) a "R3" b
1696	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1697	# else
1698	# define PGM_CTX(a,b) a##R0##b
1699	# define PGM_CTX_STR(a,b) a "R0" b
1700	# define PGM_CTX_DECL(type) PGMDECL(type)
1701	# endif
1702	#endif
1703
1704	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1705	#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1706	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1707	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1708	#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1709	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1710	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1711	#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1712	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1713	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1714	#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1715	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1716	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1717	#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1718	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1719	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1720	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1721
1722	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1723	#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1724	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1725	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1726	#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1727	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1728	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1729	#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1730	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1731	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1732	#define PGM_SHW_NAME_GC_NESTED_STR(name) "pgmGCShwNested" #name
1733	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1734	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1735	#define PGM_SHW_NAME_GC_EPT_STR(name) "pgmGCShwEPT" #name
1736	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1737	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1738	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1739
1740	/* Shw_Gst */
1741	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1742	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1743	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1744	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1745	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1746	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1747	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1748	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1749	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1750	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1751	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1752	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1753	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1754	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1755	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1756	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1757	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1758	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1759	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1760
1761	#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1762	#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1763	#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1764	#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1765	#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1766	#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1767	#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1768	#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1769	#define PGM_BTH_NAME_GC_NESTED_REAL_STR(name) "pgmGCBthNestedReal" #name
1770	#define PGM_BTH_NAME_GC_NESTED_PROT_STR(name) "pgmGCBthNestedProt" #name
1771	#define PGM_BTH_NAME_GC_NESTED_32BIT_STR(name) "pgmGCBthNested32Bit" #name
1772	#define PGM_BTH_NAME_GC_NESTED_PAE_STR(name) "pgmGCBthNestedPAE" #name
1773	#define PGM_BTH_NAME_GC_NESTED_AMD64_STR(name) "pgmGCBthNestedAMD64" #name
1774	#define PGM_BTH_NAME_GC_EPT_REAL_STR(name) "pgmGCBthEPTReal" #name
1775	#define PGM_BTH_NAME_GC_EPT_PROT_STR(name) "pgmGCBthEPTProt" #name
1776	#define PGM_BTH_NAME_GC_EPT_32BIT_STR(name) "pgmGCBthEPT32Bit" #name
1777	#define PGM_BTH_NAME_GC_EPT_PAE_STR(name) "pgmGCBthEPTPAE" #name
1778	#define PGM_BTH_NAME_GC_EPT_AMD64_STR(name) "pgmGCBthEPTAMD64" #name
1779	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1780	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1781	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1782	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1783	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1784	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1785	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1786	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1787	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1788	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1789	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1790	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1791	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1792	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1793	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
1794	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
1795	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
1796	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
1797	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
1798
1799	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1800	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1801	/** @} */
1802
1803	/**
1804	* Data for each paging mode.
1805	*/
1806	typedef struct PGMMODEDATA
1807	{
1808	/** The guest mode type. */
1809	uint32_t uGstType;
1810	/** The shadow mode type. */
1811	uint32_t uShwType;
1812
1813	/** @name Function pointers for Shadow paging.
1814	* @{
1815	*/
1816	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1817	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1818	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1819	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1820
1821	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1822	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1823
1824	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1825	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1826	/** @} */
1827
1828	/** @name Function pointers for Guest paging.
1829	* @{
1830	*/
1831	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1832	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1833	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1834	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1835	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1836	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1837	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1838	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1839	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1840	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1841	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1842	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1843	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1844
1845	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1846	DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1847	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1848	DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1849	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1850	DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1851	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1852	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1853	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1854
1855	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1856	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1857	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1858	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1859	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1860	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1861	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1862	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1863	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1864	/** @} */
1865
1866	/** @name Function pointers for Both Shadow and Guest paging.
1867	* @{
1868	*/
1869	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1870	DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1871	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1872	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1873	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1874	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1875	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1876	#ifdef VBOX_STRICT
1877	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1878	#endif
1879
1880	DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1881	DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1882	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1883	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1884	DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1885	DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1886	#ifdef VBOX_STRICT
1887	DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1888	#endif
1889
1890	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1891	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1892	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1893	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1894	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1895	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1896	#ifdef VBOX_STRICT
1897	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1898	#endif
1899	/** @} */
1900	} PGMMODEDATA, *PPGMMODEDATA;
1901
1902
1903
1904	/**
1905	* Converts a PGM pointer into a VM pointer.
1906	* @returns Pointer to the VM structure the PGM is part of.
1907	* @param pPGM Pointer to PGM instance data.
1908	*/
1909	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1910
1911	/**
1912	* PGM Data (part of VM)
1913	*/
1914	typedef struct PGM
1915	{
1916	/** Offset to the VM structure. */
1917	RTINT offVM;
1918
1919	/*
1920	* This will be redefined at least two more times before we're done, I'm sure.
1921	* The current code is only to get on with the coding.
1922	* - 2004-06-10: initial version, bird.
1923	* - 2004-07-02: 1st time, bird.
1924	* - 2004-10-18: 2nd time, bird.
1925	* - 2005-07-xx: 3rd time, bird.
1926	*/
1927
1928	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1929	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1930	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1931	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1932
1933	/** The host paging mode. (This is what SUPLib reports.) */
1934	SUPPAGINGMODE enmHostMode;
1935	/** The shadow paging mode. */
1936	PGMMODE enmShadowMode;
1937	/** The guest paging mode. */
1938	PGMMODE enmGuestMode;
1939
1940	/** The current physical address representing in the guest CR3 register. */
1941	RTGCPHYS GCPhysCR3;
1942	/** Pointer to the 5 page CR3 content mapping.
1943	* The first page is always the CR3 (in some form) while the 4 other pages
1944	* are used of the PDs in PAE mode. */
1945	RTGCPTR GCPtrCR3Mapping;
1946	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1947	uint32_t u32Alignment;
1948	#endif
1949	/** The physical address of the currently monitored guest CR3 page.
1950	* When this value is NIL_RTGCPHYS no page is being monitored. */
1951	RTGCPHYS GCPhysGstCR3Monitored;
1952
1953	/** @name 32-bit Guest Paging.
1954	* @{ */
1955	/** The guest's page directory, HC pointer. */
1956	R3R0PTRTYPE(PX86PD) pGuestPDHC;
1957	/** The guest's page directory, static GC mapping. */
1958	RCPTRTYPE(PX86PD) pGuestPDGC;
1959	/** @} */
1960
1961	/** @name PAE Guest Paging.
1962	* @{ */
1963	/** The guest's page directory pointer table, static GC mapping. */
1964	RCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1965	/** The guest's page directory pointer table, HC pointer. */
1966	R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1967	/** The guest's page directories, HC pointers.
1968	* These are individual pointers and don't have to be adjecent.
1969	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1970	R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1971	/** The guest's page directories, static GC mapping.
1972	* Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1973	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1974	RCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1975	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1976	RTGCPHYS aGCPhysGstPaePDs[4];
1977	/** The physical addresses of the monitored guest page directories (PAE). */
1978	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1979	/** @} */
1980
1981	/** @name AMD64 Guest Paging.
1982	* @{ */
1983	/** The guest's page directory pointer table, HC pointer. */
1984	R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
1985	/** @} */
1986
1987	/** @name 32-bit Shadow Paging
1988	* @{ */
1989	/** The 32-Bit PD - HC Ptr. */
1990	R3R0PTRTYPE(PX86PD) pHC32BitPD;
1991	/** The 32-Bit PD - GC Ptr. */
1992	RCPTRTYPE(PX86PD) pGC32BitPD;
1993	#if HC_ARCH_BITS == 64
1994	uint32_t u32Padding1; /*< alignment padding. /
1995	#endif
1996	/** The Physical Address (HC) of the 32-Bit PD. */
1997	RTHCPHYS HCPhys32BitPD;
1998	/** @} */
1999
2000	/** @name PAE Shadow Paging
2001	* @{ */
2002	/** The four PDs for the low 4GB - HC Ptr.
2003	* Even though these are 4 pointers, what they point at is a single table.
2004	* Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2005	R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
2006	/** The four PDs for the low 4GB - GC Ptr.
2007	* Same kind of mapping as apHCPaePDs. */
2008	RCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
2009	/** The Physical Address (HC) of the four PDs for the low 4GB.
2010	* These are NOT 4 contiguous pages. */
2011	RTHCPHYS aHCPhysPaePDs[4];
2012	/** The PAE PDP - HC Ptr. */
2013	R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
2014	/** The Physical Address (HC) of the PAE PDPT. */
2015	RTHCPHYS HCPhysPaePDPT;
2016	/** The PAE PDPT - GC Ptr. */
2017	RCPTRTYPE(PX86PDPT) pGCPaePDPT;
2018	/** @} */
2019
2020	/** @name AMD64 Shadow Paging
2021	* Extends PAE Paging.
2022	* @{ */
2023	#if HC_ARCH_BITS == 64
2024	RTRCPTR alignment5; /*< structure size alignment. /
2025	#endif
2026	/** The Page Map Level 4 table - HC Ptr. */
2027	R3R0PTRTYPE(PX86PML4) pHCPaePML4;
2028	/** The Physical Address (HC) of the Page Map Level 4 table. */
2029	RTHCPHYS HCPhysPaePML4;
2030	/** The pgm pool page descriptor for the current active CR3. */
2031	R3R0PTRTYPE(PPGMPOOLPAGE) pHCShwAmd64CR3;
2032
2033	/** @}*/
2034
2035	/** @name Nested Shadow Paging
2036	* @{ */
2037	/** Root table; format depends on the host paging mode (AMD-V) or EPT */
2038	R3R0PTRTYPE(void *) pHCNestedRoot;
2039	/** The Physical Address (HC) of the nested paging root. */
2040	RTHCPHYS HCPhysNestedRoot;
2041
2042	/** @name Function pointers for Shadow paging.
2043	* @{
2044	*/
2045	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2046	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2047	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2048	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2049
2050	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2051	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2052
2053	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2054	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2055
2056	/** @} */
2057
2058	/** @name Function pointers for Guest paging.
2059	* @{
2060	*/
2061	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2062	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2063	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2064	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2065	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2066	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2067	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2068	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2069	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2070	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2071	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2072	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2073	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2074
2075	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2076	DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2077	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2078	DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2079	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
2080	DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2081	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
2082	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
2083	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
2084	#if HC_ARCH_BITS == 64
2085	RTRCPTR alignment3; /*< structure size alignment. /
2086	#endif
2087
2088	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2089	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2090	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2091	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2092	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2093	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2094	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2095	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2096	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2097	/** @} */
2098
2099	/** @name Function pointers for Both Shadow and Guest paging.
2100	* @{
2101	*/
2102	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2103	DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2104	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2105	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2106	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2107	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2108	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2109	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2110
2111	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2112	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2113	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2114	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2115	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2116	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2117	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2118
2119	DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2120	DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2121	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2122	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2123	DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2124	DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2125	DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2126	#if HC_ARCH_BITS == 64
2127	RTRCPTR alignment2; /*< structure size alignment. /
2128	#endif
2129	/** @} */
2130
2131	/** Pointer to SHW+GST mode data (function pointers).
2132	* The index into this table is made up from */
2133	R3PTRTYPE(PPGMMODEDATA) paModeData;
2134
2135	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2136	* This is sorted by physical address and contains no overlapping ranges. */
2137	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2138	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2139	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2140	/** GC pointer corresponding to PGM::pRamRangesR3. */
2141	RCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
2142	/** The configured RAM size. */
2143	RTUINT cbRamSize;
2144
2145	/** Pointer to the list of ROM ranges - for R3.
2146	* This is sorted by physical address and contains no overlapping ranges. */
2147	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2148	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2149	R0PTRTYPE(PPGMRAMRANGE) pRomRangesR0;
2150	/** GC pointer corresponding to PGM::pRomRangesR3. */
2151	RCPTRTYPE(PPGMRAMRANGE) pRomRangesGC;
2152	/** Alignment padding. */
2153	RTRCPTR GCPtrPadding2;
2154
2155	/** Pointer to the list of MMIO2 ranges - for R3.
2156	* Registration order. */
2157	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2158
2159	/** PGM offset based trees - HC Ptr. */
2160	R3R0PTRTYPE(PPGMTREES) pTreesHC;
2161	/** PGM offset based trees - GC Ptr. */
2162	RCPTRTYPE(PPGMTREES) pTreesGC;
2163
2164	/** Linked list of GC mappings - for GC.
2165	* The list is sorted ascending on address.
2166	*/
2167	RCPTRTYPE(PPGMMAPPING) pMappingsGC;
2168	/** Linked list of GC mappings - for HC.
2169	* The list is sorted ascending on address.
2170	*/
2171	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2172	/** Linked list of GC mappings - for R0.
2173	* The list is sorted ascending on address.
2174	*/
2175	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2176
2177	/** If set no conflict checks are required. (boolean) */
2178	bool fMappingsFixed;
2179	/** If set, then no mappings are put into the shadow page table. (boolean) */
2180	bool fDisableMappings;
2181	/** Size of fixed mapping */
2182	uint32_t cbMappingFixed;
2183	/** Base address (GC) of fixed mapping */
2184	RTGCPTR GCPtrMappingFixed;
2185	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2186	uint32_t u32Padding0; /*< alignment padding. /
2187	#endif
2188
2189
2190	/** @name Intermediate Context
2191	* @{ */
2192	/** Pointer to the intermediate page directory - Normal. */
2193	R3PTRTYPE(PX86PD) pInterPD;
2194	/** Pointer to the intermedate page tables - Normal.
2195	* There are two page tables, one for the identity mapping and one for
2196	* the host context mapping (of the core code). */
2197	R3PTRTYPE(PX86PT) apInterPTs[2];
2198	/** Pointer to the intermedate page tables - PAE. */
2199	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2200	/** Pointer to the intermedate page directory - PAE. */
2201	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2202	/** Pointer to the intermedate page directory - PAE. */
2203	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2204	/** Pointer to the intermedate page-map level 4 - AMD64. */
2205	R3PTRTYPE(PX86PML4) pInterPaePML4;
2206	/** Pointer to the intermedate page directory - AMD64. */
2207	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2208	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2209	RTHCPHYS HCPhysInterPD;
2210	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2211	RTHCPHYS HCPhysInterPaePDPT;
2212	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2213	RTHCPHYS HCPhysInterPaePML4;
2214	/** @} */
2215
2216	/** Base address of the dynamic page mapping area.
2217	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2218	*/
2219	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2220	/** The index of the last entry used in the dynamic page mapping area. */
2221	RTUINT iDynPageMapLast;
2222	/** Cache containing the last entries in the dynamic page mapping area.
2223	* The cache size is covering half of the mapping area. */
2224	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2225
2226	/** A20 gate mask.
2227	* Our current approach to A20 emulation is to let REM do it and don't bother
2228	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2229	* But whould need arrise, we'll subject physical addresses to this mask. */
2230	RTGCPHYS GCPhysA20Mask;
2231	/** A20 gate state - boolean! */
2232	RTUINT fA20Enabled;
2233
2234	/** What needs syncing (PGM_SYNC_*).
2235	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2236	* PGMFlushTLB, and PGMR3Load. */
2237	RTUINT fSyncFlags;
2238
2239	/** PGM critical section.
2240	* This protects the physical & virtual access handlers, ram ranges,
2241	* and the page flag updating (some of it anyway).
2242	*/
2243	PDMCRITSECT CritSect;
2244
2245	/** Shadow Page Pool - HC Ptr. */
2246	R3R0PTRTYPE(PPGMPOOL) pPoolHC;
2247	/** Shadow Page Pool - GC Ptr. */
2248	RCPTRTYPE(PPGMPOOL) pPoolGC;
2249
2250	/** We're not in a state which permits writes to guest memory.
2251	* (Only used in strict builds.) */
2252	bool fNoMorePhysWrites;
2253
2254	/** Flush the cache on the next access. */
2255	bool fPhysCacheFlushPending;
2256	/** @todo r=bird: Fix member names!*/
2257	/** PGMPhysRead cache */
2258	PGMPHYSCACHE pgmphysreadcache;
2259	/** PGMPhysWrite cache */
2260	PGMPHYSCACHE pgmphyswritecache;
2261
2262	/**
2263	* Data associated with managing the ring-3 mappings of the allocation chunks.
2264	*/
2265	struct
2266	{
2267	/** The chunk tree, ordered by chunk id. */
2268	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2269	/** The chunk mapping TLB. */
2270	PGMCHUNKR3MAPTLB Tlb;
2271	/** The number of mapped chunks. */
2272	uint32_t c;
2273	/** The maximum number of mapped chunks.
2274	* @cfgm PGM/MaxRing3Chunks */
2275	uint32_t cMax;
2276	/** The chunk age tree, ordered by ageing sequence number. */
2277	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2278	/** The current time. */
2279	uint32_t iNow;
2280	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2281	uint32_t AgeingCountdown;
2282	} ChunkR3Map;
2283
2284	/**
2285	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2286	*/
2287	PGMPAGER3MAPTLB PhysTlbHC;
2288
2289	/** @name The zero page.
2290	* @{ */
2291	/** The host physical address of the zero page. */
2292	RTHCPHYS HCPhysZeroPg;
2293	/** The ring-3 mapping of the zero page. */
2294	RTR3PTR pvZeroPgR3;
2295	/** The ring-0 mapping of the zero page. */
2296	RTR0PTR pvZeroPgR0;
2297	/** The GC mapping of the zero page. */
2298	RTGCPTR pvZeroPgGC;
2299	#if GC_ARCH_BITS != 32
2300	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2301	#endif
2302	/** @}*/
2303
2304	/** The number of handy pages. */
2305	uint32_t cHandyPages;
2306	/**
2307	* Array of handy pages.
2308	*
2309	* This array is used in a two way communication between pgmPhysAllocPage
2310	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2311	* an intermediary.
2312	*
2313	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2314	* (The current size of 32 pages, means 128 KB of handy memory.)
2315	*/
2316	GMMPAGEDESC aHandyPages[32];
2317
2318	/** @name Release Statistics
2319	* @{ */
2320	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2321	uint32_t cPrivatePages; /*< The number of private pages. /
2322	uint32_t cSharedPages; /*< The number of shared pages. /
2323	uint32_t cZeroPages; /*< The number of zero backed pages. /
2324	/** The number of times the guest has switched mode since last reset or statistics reset. */
2325	STAMCOUNTER cGuestModeChanges;
2326	/** @} */
2327
2328	#ifdef VBOX_WITH_STATISTICS
2329	/** GC: Which statistic this \#PF should be attributed to. */
2330	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
2331	RTRCPTR padding0;
2332	/** HC: Which statistic this \#PF should be attributed to. */
2333	R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
2334	RTHCPTR padding1;
2335	STAMPROFILE StatGCTrap0e; /*< GC: PGMGCTrap0eHandler() profiling. /
2336	STAMPROFILE StatTrap0eCSAM; /*< Profiling of the Trap0eHandler body when the cause is CSAM. /
2337	STAMPROFILE StatTrap0eDirtyAndAccessedBits; /*< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2338	STAMPROFILE StatTrap0eGuestTrap; /*< Profiling of the Trap0eHandler body when the cause is a guest trap. /
2339	STAMPROFILE StatTrap0eHndPhys; /*< Profiling of the Trap0eHandler body when the cause is a physical handler. /
2340	STAMPROFILE StatTrap0eHndVirt; /*< Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2341	STAMPROFILE StatTrap0eHndUnhandled; /*< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2342	STAMPROFILE StatTrap0eMisc; /*< Profiling of the Trap0eHandler body when the cause is not known. /
2343	STAMPROFILE StatTrap0eOutOfSync; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2344	STAMPROFILE StatTrap0eOutOfSyncHndPhys; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2345	STAMPROFILE StatTrap0eOutOfSyncHndVirt; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2346	STAMPROFILE StatTrap0eOutOfSyncObsHnd; /*< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2347	STAMPROFILE StatTrap0eSyncPT; /*< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2348
2349	STAMCOUNTER StatTrap0eMapHandler; /*< Number of traps due to access handlers in mappings. /
2350	STAMCOUNTER StatGCTrap0eConflicts; /*< GC: The number of times \#PF was caused by an undetected conflict. /
2351
2352	STAMCOUNTER StatGCTrap0eUSNotPresentRead;
2353	STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
2354	STAMCOUNTER StatGCTrap0eUSWrite;
2355	STAMCOUNTER StatGCTrap0eUSReserved;
2356	STAMCOUNTER StatGCTrap0eUSNXE;
2357	STAMCOUNTER StatGCTrap0eUSRead;
2358
2359	STAMCOUNTER StatGCTrap0eSVNotPresentRead;
2360	STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
2361	STAMCOUNTER StatGCTrap0eSVWrite;
2362	STAMCOUNTER StatGCTrap0eSVReserved;
2363	STAMCOUNTER StatGCTrap0eSNXE;
2364
2365	STAMCOUNTER StatTrap0eWPEmulGC;
2366	STAMCOUNTER StatTrap0eWPEmulR3;
2367
2368	STAMCOUNTER StatGCTrap0eUnhandled;
2369	STAMCOUNTER StatGCTrap0eMap;
2370
2371	/** GC: PGMSyncPT() profiling. */
2372	STAMPROFILE StatGCSyncPT;
2373	/** GC: The number of times PGMSyncPT() needed to allocate page tables. */
2374	STAMCOUNTER StatGCSyncPTAlloc;
2375	/** GC: The number of times PGMSyncPT() detected conflicts. */
2376	STAMCOUNTER StatGCSyncPTConflict;
2377	/** GC: The number of times PGMSyncPT() failed. */
2378	STAMCOUNTER StatGCSyncPTFailed;
2379	/** GC: PGMGCInvalidatePage() profiling. */
2380	STAMPROFILE StatGCInvalidatePage;
2381	/** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
2382	STAMCOUNTER StatGCInvalidatePage4KBPages;
2383	/** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
2384	STAMCOUNTER StatGCInvalidatePage4MBPages;
2385	/** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
2386	STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
2387	/** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
2388	STAMCOUNTER StatGCInvalidatePagePDNAs;
2389	/** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
2390	STAMCOUNTER StatGCInvalidatePagePDNPs;
2391	/** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
2392	STAMCOUNTER StatGCInvalidatePagePDMappings;
2393	/** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2394	STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
2395	/** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2396	STAMCOUNTER StatGCInvalidatePageSkipped;
2397	/** GC: The number of times user page is out of sync was detected in GC. */
2398	STAMCOUNTER StatGCPageOutOfSyncUser;
2399	/** GC: The number of times supervisor page is out of sync was detected in GC. */
2400	STAMCOUNTER StatGCPageOutOfSyncSupervisor;
2401	/** GC: The number of dynamic page mapping cache hits */
2402	STAMCOUNTER StatDynMapCacheMisses;
2403	/** GC: The number of dynamic page mapping cache misses */
2404	STAMCOUNTER StatDynMapCacheHits;
2405	/** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
2406	STAMCOUNTER StatGCGuestCR3WriteHandled;
2407	/** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
2408	STAMCOUNTER StatGCGuestCR3WriteUnhandled;
2409	/** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
2410	STAMCOUNTER StatGCGuestCR3WriteConflict;
2411	/** GC: Number of out-of-sync handled pages. */
2412	STAMCOUNTER StatHandlersOutOfSync;
2413	/** GC: Number of traps due to physical access handlers. */
2414	STAMCOUNTER StatHandlersPhysical;
2415	/** GC: Number of traps due to virtual access handlers. */
2416	STAMCOUNTER StatHandlersVirtual;
2417	/** GC: Number of traps due to virtual access handlers found by physical address. */
2418	STAMCOUNTER StatHandlersVirtualByPhys;
2419	/** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2420	STAMCOUNTER StatHandlersVirtualUnmarked;
2421	/** GC: Number of traps due to access outside range of monitored page(s). */
2422	STAMCOUNTER StatHandlersUnhandled;
2423	/** GC: Number of traps due to access to invalid physical memory. */
2424	STAMCOUNTER StatHandlersInvalid;
2425
2426	/** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
2427	STAMCOUNTER StatGCGuestROMWriteHandled;
2428	/** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
2429	STAMCOUNTER StatGCGuestROMWriteUnhandled;
2430
2431	/** HC: PGMR3InvalidatePage() profiling. */
2432	STAMPROFILE StatHCInvalidatePage;
2433	/** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
2434	STAMCOUNTER StatHCInvalidatePage4KBPages;
2435	/** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2436	STAMCOUNTER StatHCInvalidatePage4MBPages;
2437	/** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2438	STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2439	/** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2440	STAMCOUNTER StatHCInvalidatePagePDNAs;
2441	/** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2442	STAMCOUNTER StatHCInvalidatePagePDNPs;
2443	/** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2444	STAMCOUNTER StatHCInvalidatePagePDMappings;
2445	/** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2446	STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2447	/** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2448	STAMCOUNTER StatHCInvalidatePageSkipped;
2449	/** HC: PGMR3SyncPT() profiling. */
2450	STAMPROFILE StatHCSyncPT;
2451	/** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2452	STAMPROFILE StatHCResolveConflict;
2453	/** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2454	STAMCOUNTER StatHCDetectedConflicts;
2455	/** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2456	STAMCOUNTER StatHCGuestPDWrite;
2457	/** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2458	STAMCOUNTER StatHCGuestPDWriteConflict;
2459
2460	/** HC: The number of pages marked not present for accessed bit emulation. */
2461	STAMCOUNTER StatHCAccessedPage;
2462	/** HC: The number of pages marked read-only for dirty bit tracking. */
2463	STAMCOUNTER StatHCDirtyPage;
2464	/** HC: The number of pages marked read-only for dirty bit tracking. */
2465	STAMCOUNTER StatHCDirtyPageBig;
2466	/** HC: The number of traps generated for dirty bit tracking. */
2467	STAMCOUNTER StatHCDirtyPageTrap;
2468	/** HC: The number of pages already dirty or readonly. */
2469	STAMCOUNTER StatHCDirtyPageSkipped;
2470
2471	/** GC: The number of pages marked not present for accessed bit emulation. */
2472	STAMCOUNTER StatGCAccessedPage;
2473	/** GC: The number of pages marked read-only for dirty bit tracking. */
2474	STAMCOUNTER StatGCDirtyPage;
2475	/** GC: The number of pages marked read-only for dirty bit tracking. */
2476	STAMCOUNTER StatGCDirtyPageBig;
2477	/** GC: The number of traps generated for dirty bit tracking. */
2478	STAMCOUNTER StatGCDirtyPageTrap;
2479	/** GC: The number of pages already dirty or readonly. */
2480	STAMCOUNTER StatGCDirtyPageSkipped;
2481	/** GC: The number of pages marked dirty because of write accesses. */
2482	STAMCOUNTER StatGCDirtiedPage;
2483	/** GC: The number of pages already marked dirty because of write accesses. */
2484	STAMCOUNTER StatGCPageAlreadyDirty;
2485	/** GC: The number of real pages faults during dirty bit tracking. */
2486	STAMCOUNTER StatGCDirtyTrackRealPF;
2487
2488	/** GC: Profiling of the PGMTrackDirtyBit() body */
2489	STAMPROFILE StatGCDirtyBitTracking;
2490	/** HC: Profiling of the PGMTrackDirtyBit() body */
2491	STAMPROFILE StatHCDirtyBitTracking;
2492
2493	/** GC: Profiling of the PGMGstModifyPage() body */
2494	STAMPROFILE StatGCGstModifyPage;
2495	/** HC: Profiling of the PGMGstModifyPage() body */
2496	STAMPROFILE StatHCGstModifyPage;
2497
2498	/** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2499	STAMCOUNTER StatGCSyncPagePDNAs;
2500	/** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2501	STAMCOUNTER StatGCSyncPagePDOutOfSync;
2502	/** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2503	STAMCOUNTER StatHCSyncPagePDNAs;
2504	/** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2505	STAMCOUNTER StatHCSyncPagePDOutOfSync;
2506
2507	STAMCOUNTER StatSynPT4kGC;
2508	STAMCOUNTER StatSynPT4kHC;
2509	STAMCOUNTER StatSynPT4MGC;
2510	STAMCOUNTER StatSynPT4MHC;
2511
2512	/** Profiling of the PGMFlushTLB() body. */
2513	STAMPROFILE StatFlushTLB;
2514	/** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2515	STAMCOUNTER StatFlushTLBNewCR3;
2516	/** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2517	STAMCOUNTER StatFlushTLBNewCR3Global;
2518	/** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2519	STAMCOUNTER StatFlushTLBSameCR3;
2520	/** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2521	STAMCOUNTER StatFlushTLBSameCR3Global;
2522
2523	STAMPROFILE StatGCSyncCR3; /*< GC: PGMSyncCR3() profiling. /
2524	STAMPROFILE StatGCSyncCR3Handlers; /*< GC: Profiling of the PGMSyncCR3() update handler section. /
2525	STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /*< GC: Profiling of the virtual handler resets. /
2526	STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /*< GC: Profiling of the virtual handler updates. /
2527	STAMCOUNTER StatGCSyncCR3Global; /*< GC: The number of global CR3 syncs. /
2528	STAMCOUNTER StatGCSyncCR3NotGlobal; /*< GC: The number of non-global CR3 syncs. /
2529	STAMCOUNTER StatGCSyncCR3DstFreed; /*< GC: The number of times we've had to free a shadow entry. /
2530	STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /*< GC: The number of times we've had to free a shadow entry for which the source entry was not present. /
2531	STAMCOUNTER StatGCSyncCR3DstNotPresent; /*< GC: The number of times we've encountered a not present shadow entry for a present guest entry. /
2532	STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /*< GC: The number of times a global page directory wasn't flushed. /
2533	STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /*< GC: The number of times a page table with only global entries wasn't flushed. /
2534	STAMCOUNTER StatGCSyncCR3DstCacheHit; /*< GC: The number of times we got some kind of cache hit on a page table. /
2535
2536	STAMPROFILE StatHCSyncCR3; /*< HC: PGMSyncCR3() profiling. /
2537	STAMPROFILE StatHCSyncCR3Handlers; /*< HC: Profiling of the PGMSyncCR3() update handler section. /
2538	STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /*< HC: Profiling of the virtual handler resets. /
2539	STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /*< HC: Profiling of the virtual handler updates. /
2540	STAMCOUNTER StatHCSyncCR3Global; /*< HC: The number of global CR3 syncs. /
2541	STAMCOUNTER StatHCSyncCR3NotGlobal; /*< HC: The number of non-global CR3 syncs. /
2542	STAMCOUNTER StatHCSyncCR3DstFreed; /*< HC: The number of times we've had to free a shadow entry. /
2543	STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /*< HC: The number of times we've had to free a shadow entry for which the source entry was not present. /
2544	STAMCOUNTER StatHCSyncCR3DstNotPresent; /*< HC: The number of times we've encountered a not present shadow entry for a present guest entry. /
2545	STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /*< HC: The number of times a global page directory wasn't flushed. /
2546	STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /*< HC: The number of times a page table with only global entries wasn't flushed. /
2547	STAMCOUNTER StatHCSyncCR3DstCacheHit; /*< HC: The number of times we got some kind of cache hit on a page table. /
2548
2549	/** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2550	STAMPROFILE StatVirtHandleSearchByPhysGC;
2551	/** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2552	STAMPROFILE StatVirtHandleSearchByPhysHC;
2553	/** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2554	STAMCOUNTER StatHandlePhysicalReset;
2555
2556	STAMPROFILE StatCheckPageFault;
2557	STAMPROFILE StatLazySyncPT;
2558	STAMPROFILE StatMapping;
2559	STAMPROFILE StatOutOfSync;
2560	STAMPROFILE StatHandlers;
2561	STAMPROFILE StatEIPHandlers;
2562	STAMPROFILE StatHCPrefetch;
2563
2564	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2565	/** The number of first time shadowings. */
2566	STAMCOUNTER StatTrackVirgin;
2567	/** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2568	STAMCOUNTER StatTrackAliased;
2569	/** The number of times we're tracking using cRef2. */
2570	STAMCOUNTER StatTrackAliasedMany;
2571	/** The number of times we're hitting pages which has overflowed cRef2. */
2572	STAMCOUNTER StatTrackAliasedLots;
2573	/** The number of times the extent list grows to long. */
2574	STAMCOUNTER StatTrackOverflows;
2575	/** Profiling of SyncPageWorkerTrackDeref (expensive). */
2576	STAMPROFILE StatTrackDeref;
2577	# endif
2578
2579	/** Ring-3/0 page mapper TLB hits. */
2580	STAMCOUNTER StatPageHCMapTlbHits;
2581	/** Ring-3/0 page mapper TLB misses. */
2582	STAMCOUNTER StatPageHCMapTlbMisses;
2583	/** Ring-3/0 chunk mapper TLB hits. */
2584	STAMCOUNTER StatChunkR3MapTlbHits;
2585	/** Ring-3/0 chunk mapper TLB misses. */
2586	STAMCOUNTER StatChunkR3MapTlbMisses;
2587	/** Times a shared page has been replaced by a private one. */
2588	STAMCOUNTER StatPageReplaceShared;
2589	/** Times the zero page has been replaced by a private one. */
2590	STAMCOUNTER StatPageReplaceZero;
2591	/** The number of times we've executed GMMR3AllocateHandyPages. */
2592	STAMCOUNTER StatPageHandyAllocs;
2593
2594	/** Allocated mbs of guest ram */
2595	STAMCOUNTER StatDynRamTotal;
2596	/** Nr of pgmr3PhysGrowRange calls. */
2597	STAMCOUNTER StatDynRamGrow;
2598
2599	STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2600	STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2601	STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2602	#endif
2603	} PGM, *PPGM;
2604
2605
2606	/** @name PGM::fSyncFlags Flags
2607	* @{
2608	*/
2609	/** Updates the virtual access handler state bit in PGMPAGE. */
2610	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2611	/** Always sync CR3. */
2612	#define PGM_SYNC_ALWAYS RT_BIT(1)
2613	/** Check monitoring on next CR3 (re)load and invalidate page. */
2614	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2615	/** Clear the page pool (a light weight flush). */
2616	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2617	/** @} */
2618
2619
2620	__BEGIN_DECLS
2621
2622	int pgmLock(PVM pVM);
2623	void pgmUnlock(PVM pVM);
2624
2625	PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2626	PGMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2627
2628	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2629	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2630	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2631	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2632	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2633
2634	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2635	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2636	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2637	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2638	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2639	#else
2640	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2641	#endif
2642	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2643
2644
2645	void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2646	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2647	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2648	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2649	#ifdef IN_RING3
2650	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2651	int pgmR3PhysRamReset(PVM pVM);
2652	int pgmR3PhysRomReset(PVM pVM);
2653	#ifndef VBOX_WITH_NEW_PHYS_CODE
2654	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2655	#endif
2656
2657	int pgmR3PoolInit(PVM pVM);
2658	void pgmR3PoolRelocate(PVM pVM);
2659	void pgmR3PoolReset(PVM pVM);
2660
2661	#endif /* IN_RING3 */
2662	#ifdef IN_GC
2663	void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2664	#endif
2665	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2666	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2667	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2668	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2669	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2670	void pgmPoolFlushAll(PVM pVM);
2671	void pgmPoolClearAll(PVM pVM);
2672	int pgmPoolSyncCR3(PVM pVM);
2673	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2674	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2675	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2676	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2677	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2678	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2679	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2680	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2681	#ifdef PGMPOOL_WITH_MONITORING
2682	# ifdef IN_RING3
2683	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2684	# else
2685	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2686	# endif
2687	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2688	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2689	void pgmPoolMonitorModifiedClearAll(PVM pVM);
2690	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2691	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2692	#endif
2693
2694	__END_DECLS
2695
2696
2697	/**
2698	* Gets the PGMRAMRANGE structure for a guest page.
2699	*
2700	* @returns Pointer to the RAM range on success.
2701	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2702	*
2703	* @param pPGM PGM handle.
2704	* @param GCPhys The GC physical address.
2705	*/
2706	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2707	{
2708	/*
2709	* Optimize for the first range.
2710	*/
2711	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2712	RTGCPHYS off = GCPhys - pRam->GCPhys;
2713	if (RT_UNLIKELY(off >= pRam->cb))
2714	{
2715	do
2716	{
2717	pRam = CTXALLSUFF(pRam->pNext);
2718	if (RT_UNLIKELY(!pRam))
2719	break;
2720	off = GCPhys - pRam->GCPhys;
2721	} while (off >= pRam->cb);
2722	}
2723	return pRam;
2724	}
2725
2726
2727	/**
2728	* Gets the PGMPAGE structure for a guest page.
2729	*
2730	* @returns Pointer to the page on success.
2731	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2732	*
2733	* @param pPGM PGM handle.
2734	* @param GCPhys The GC physical address.
2735	*/
2736	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2737	{
2738	/*
2739	* Optimize for the first range.
2740	*/
2741	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2742	RTGCPHYS off = GCPhys - pRam->GCPhys;
2743	if (RT_UNLIKELY(off >= pRam->cb))
2744	{
2745	do
2746	{
2747	pRam = CTXALLSUFF(pRam->pNext);
2748	if (RT_UNLIKELY(!pRam))
2749	return NULL;
2750	off = GCPhys - pRam->GCPhys;
2751	} while (off >= pRam->cb);
2752	}
2753	return &pRam->aPages[off >> PAGE_SHIFT];
2754	}
2755
2756
2757	/**
2758	* Gets the PGMPAGE structure for a guest page.
2759	*
2760	* Old Phys code: Will make sure the page is present.
2761	*
2762	* @returns VBox status code.
2763	* @retval VINF_SUCCESS and a valid *ppPage on success.
2764	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2765	*
2766	* @param pPGM PGM handle.
2767	* @param GCPhys The GC physical address.
2768	* @param ppPage Where to store the page poitner on success.
2769	*/
2770	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2771	{
2772	/*
2773	* Optimize for the first range.
2774	*/
2775	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2776	RTGCPHYS off = GCPhys - pRam->GCPhys;
2777	if (RT_UNLIKELY(off >= pRam->cb))
2778	{
2779	do
2780	{
2781	pRam = CTXALLSUFF(pRam->pNext);
2782	if (RT_UNLIKELY(!pRam))
2783	{
2784	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
2785	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2786	}
2787	off = GCPhys - pRam->GCPhys;
2788	} while (off >= pRam->cb);
2789	}
2790	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2791	#ifndef VBOX_WITH_NEW_PHYS_CODE
2792
2793	/*
2794	* Make sure it's present.
2795	*/
2796	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2797	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2798	{
2799	#ifdef IN_RING3
2800	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2801	#else
2802	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2803	#endif
2804	if (VBOX_FAILURE(rc))
2805	{
2806	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
2807	return rc;
2808	}
2809	Assert(rc == VINF_SUCCESS);
2810	}
2811	#endif
2812	return VINF_SUCCESS;
2813	}
2814
2815
2816
2817
2818	/**
2819	* Gets the PGMPAGE structure for a guest page.
2820	*
2821	* Old Phys code: Will make sure the page is present.
2822	*
2823	* @returns VBox status code.
2824	* @retval VINF_SUCCESS and a valid *ppPage on success.
2825	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2826	*
2827	* @param pPGM PGM handle.
2828	* @param GCPhys The GC physical address.
2829	* @param ppPage Where to store the page poitner on success.
2830	* @param ppRamHint Where to read and store the ram list hint.
2831	* The caller initializes this to NULL before the call.
2832	*/
2833	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2834	{
2835	RTGCPHYS off;
2836	PPGMRAMRANGE pRam = *ppRamHint;
2837	if ( !pRam
2838	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2839	{
2840	pRam = CTXALLSUFF(pPGM->pRamRanges);
2841	off = GCPhys - pRam->GCPhys;
2842	if (RT_UNLIKELY(off >= pRam->cb))
2843	{
2844	do
2845	{
2846	pRam = CTXALLSUFF(pRam->pNext);
2847	if (RT_UNLIKELY(!pRam))
2848	{
2849	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
2850	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2851	}
2852	off = GCPhys - pRam->GCPhys;
2853	} while (off >= pRam->cb);
2854	}
2855	*ppRamHint = pRam;
2856	}
2857	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2858	#ifndef VBOX_WITH_NEW_PHYS_CODE
2859
2860	/*
2861	* Make sure it's present.
2862	*/
2863	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2864	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2865	{
2866	#ifdef IN_RING3
2867	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2868	#else
2869	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2870	#endif
2871	if (VBOX_FAILURE(rc))
2872	{
2873	ppPage = NULL; / Shut up annoying smart ass. */
2874	return rc;
2875	}
2876	Assert(rc == VINF_SUCCESS);
2877	}
2878	#endif
2879	return VINF_SUCCESS;
2880	}
2881
2882
2883	/**
2884	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2885	*
2886	* @returns Pointer to the page on success.
2887	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2888	*
2889	* @param pPGM PGM handle.
2890	* @param GCPhys The GC physical address.
2891	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
2892	*/
2893	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2894	{
2895	/*
2896	* Optimize for the first range.
2897	*/
2898	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2899	RTGCPHYS off = GCPhys - pRam->GCPhys;
2900	if (RT_UNLIKELY(off >= pRam->cb))
2901	{
2902	do
2903	{
2904	pRam = CTXALLSUFF(pRam->pNext);
2905	if (RT_UNLIKELY(!pRam))
2906	return NULL;
2907	off = GCPhys - pRam->GCPhys;
2908	} while (off >= pRam->cb);
2909	}
2910	*ppRam = pRam;
2911	return &pRam->aPages[off >> PAGE_SHIFT];
2912	}
2913
2914
2915
2916
2917	/**
2918	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2919	*
2920	* @returns Pointer to the page on success.
2921	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2922	*
2923	* @param pPGM PGM handle.
2924	* @param GCPhys The GC physical address.
2925	* @param ppPage Where to store the pointer to the PGMPAGE structure.
2926	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2927	*/
2928	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2929	{
2930	/*
2931	* Optimize for the first range.
2932	*/
2933	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2934	RTGCPHYS off = GCPhys - pRam->GCPhys;
2935	if (RT_UNLIKELY(off >= pRam->cb))
2936	{
2937	do
2938	{
2939	pRam = CTXALLSUFF(pRam->pNext);
2940	if (RT_UNLIKELY(!pRam))
2941	{
2942	ppRam = NULL; / Shut up silly GCC warnings. */
2943	ppPage = NULL; / ditto */
2944	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2945	}
2946	off = GCPhys - pRam->GCPhys;
2947	} while (off >= pRam->cb);
2948	}
2949	*ppRam = pRam;
2950	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2951	#ifndef VBOX_WITH_NEW_PHYS_CODE
2952
2953	/*
2954	* Make sure it's present.
2955	*/
2956	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2957	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2958	{
2959	#ifdef IN_RING3
2960	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2961	#else
2962	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2963	#endif
2964	if (VBOX_FAILURE(rc))
2965	{
2966	ppPage = NULL; / Shut up silly GCC warnings. */
2967	ppPage = NULL; / ditto */
2968	return rc;
2969	}
2970	Assert(rc == VINF_SUCCESS);
2971
2972	}
2973	#endif
2974	return VINF_SUCCESS;
2975	}
2976
2977
2978	/**
2979	* Convert GC Phys to HC Phys.
2980	*
2981	* @returns VBox status.
2982	* @param pPGM PGM handle.
2983	* @param GCPhys The GC physical address.
2984	* @param pHCPhys Where to store the corresponding HC physical address.
2985	*
2986	* @deprecated Doesn't deal with zero, shared or write monitored pages.
2987	* Avoid when writing new code!
2988	*/
2989	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2990	{
2991	PPGMPAGE pPage;
2992	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2993	if (VBOX_FAILURE(rc))
2994	return rc;
2995	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
2996	return VINF_SUCCESS;
2997	}
2998
2999
3000	#ifndef IN_GC
3001	/**
3002	* Queries the Physical TLB entry for a physical guest page,
3003	* attemting to load the TLB entry if necessary.
3004	*
3005	* @returns VBox status code.
3006	* @retval VINF_SUCCESS on success
3007	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3008	* @param pPGM The PGM instance handle.
3009	* @param GCPhys The address of the guest page.
3010	* @param ppTlbe Where to store the pointer to the TLB entry.
3011	*/
3012
3013	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3014	{
3015	int rc;
3016	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3017	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3018	{
3019	STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
3020	rc = VINF_SUCCESS;
3021	}
3022	else
3023	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3024	*ppTlbe = pTlbe;
3025	return rc;
3026	}
3027	#endif /* !IN_GC */
3028
3029
3030	#ifndef VBOX_WITH_NEW_PHYS_CODE
3031	/**
3032	* Convert GC Phys to HC Virt.
3033	*
3034	* @returns VBox status.
3035	* @param pPGM PGM handle.
3036	* @param GCPhys The GC physical address.
3037	* @param pHCPtr Where to store the corresponding HC virtual address.
3038	*
3039	* @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
3040	*/
3041	DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3042	{
3043	PPGMRAMRANGE pRam;
3044	PPGMPAGE pPage;
3045	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3046	if (VBOX_FAILURE(rc))
3047	{
3048	pHCPtr = 0; / Shut up silly GCC warnings. */
3049	return rc;
3050	}
3051	RTGCPHYS off = GCPhys - pRam->GCPhys;
3052
3053	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3054	{
3055	unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3056	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3057	return VINF_SUCCESS;
3058	}
3059	if (pRam->pvHC)
3060	{
3061	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3062	return VINF_SUCCESS;
3063	}
3064	pHCPtr = 0; / Shut up silly GCC warnings. */
3065	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3066	}
3067	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3068
3069
3070	/**
3071	* Convert GC Phys to HC Virt.
3072	*
3073	* @returns VBox status.
3074	* @param PVM VM handle.
3075	* @param pRam Ram range
3076	* @param GCPhys The GC physical address.
3077	* @param pHCPtr Where to store the corresponding HC virtual address.
3078	*
3079	* @deprecated This will be eliminated. Don't use it.
3080	*/
3081	DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3082	{
3083	RTGCPHYS off = GCPhys - pRam->GCPhys;
3084	Assert(off < pRam->cb);
3085
3086	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3087	{
3088	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3089	/* Physical chunk in dynamically allocated range not present? */
3090	if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
3091	{
3092	#ifdef IN_RING3
3093	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3094	#else
3095	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3096	#endif
3097	if (rc != VINF_SUCCESS)
3098	{
3099	pHCPtr = 0; / GCC crap */
3100	return rc;
3101	}
3102	}
3103	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3104	return VINF_SUCCESS;
3105	}
3106	if (pRam->pvHC)
3107	{
3108	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3109	return VINF_SUCCESS;
3110	}
3111	pHCPtr = 0; / GCC crap */
3112	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3113	}
3114
3115
3116	/**
3117	* Convert GC Phys to HC Virt and HC Phys.
3118	*
3119	* @returns VBox status.
3120	* @param pPGM PGM handle.
3121	* @param GCPhys The GC physical address.
3122	* @param pHCPtr Where to store the corresponding HC virtual address.
3123	* @param pHCPhys Where to store the HC Physical address and its flags.
3124	*
3125	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3126	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3127	*/
3128	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3129	{
3130	PPGMRAMRANGE pRam;
3131	PPGMPAGE pPage;
3132	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3133	if (VBOX_FAILURE(rc))
3134	{
3135	pHCPtr = 0; / Shut up crappy GCC warnings */
3136	pHCPhys = 0; / ditto */
3137	return rc;
3138	}
3139	RTGCPHYS off = GCPhys - pRam->GCPhys;
3140
3141	pHCPhys = pPage->HCPhys; /* @todo PAGE FLAGS */
3142	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3143	{
3144	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3145	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3146	return VINF_SUCCESS;
3147	}
3148	if (pRam->pvHC)
3149	{
3150	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3151	return VINF_SUCCESS;
3152	}
3153	*pHCPtr = 0;
3154	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3155	}
3156
3157
3158	/**
3159	* Clears flags associated with a RAM address.
3160	*
3161	* @returns VBox status code.
3162	* @param pPGM PGM handle.
3163	* @param GCPhys Guest context physical address.
3164	* @param fFlags fFlags to clear. (Bits 0-11.)
3165	*/
3166	DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3167	{
3168	PPGMPAGE pPage;
3169	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3170	if (VBOX_FAILURE(rc))
3171	return rc;
3172
3173	fFlags &= ~X86_PTE_PAE_PG_MASK;
3174	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3175	return VINF_SUCCESS;
3176	}
3177
3178
3179	/**
3180	* Clears flags associated with a RAM address.
3181	*
3182	* @returns VBox status code.
3183	* @param pPGM PGM handle.
3184	* @param GCPhys Guest context physical address.
3185	* @param fFlags fFlags to clear. (Bits 0-11.)
3186	* @param ppRamHint Where to read and store the ram list hint.
3187	* The caller initializes this to NULL before the call.
3188	*/
3189	DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3190	{
3191	PPGMPAGE pPage;
3192	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3193	if (VBOX_FAILURE(rc))
3194	return rc;
3195
3196	fFlags &= ~X86_PTE_PAE_PG_MASK;
3197	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3198	return VINF_SUCCESS;
3199	}
3200
3201	/**
3202	* Sets (bitwise OR) flags associated with a RAM address.
3203	*
3204	* @returns VBox status code.
3205	* @param pPGM PGM handle.
3206	* @param GCPhys Guest context physical address.
3207	* @param fFlags fFlags to set clear. (Bits 0-11.)
3208	*/
3209	DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3210	{
3211	PPGMPAGE pPage;
3212	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3213	if (VBOX_FAILURE(rc))
3214	return rc;
3215
3216	fFlags &= ~X86_PTE_PAE_PG_MASK;
3217	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3218	return VINF_SUCCESS;
3219	}
3220
3221
3222	/**
3223	* Sets (bitwise OR) flags associated with a RAM address.
3224	*
3225	* @returns VBox status code.
3226	* @param pPGM PGM handle.
3227	* @param GCPhys Guest context physical address.
3228	* @param fFlags fFlags to set clear. (Bits 0-11.)
3229	* @param ppRamHint Where to read and store the ram list hint.
3230	* The caller initializes this to NULL before the call.
3231	*/
3232	DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3233	{
3234	PPGMPAGE pPage;
3235	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3236	if (VBOX_FAILURE(rc))
3237	return rc;
3238
3239	fFlags &= ~X86_PTE_PAE_PG_MASK;
3240	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3241	return VINF_SUCCESS;
3242	}
3243
3244
3245	/**
3246	* Gets the page directory for the specified address.
3247	*
3248	* @returns Pointer to the page directory in question.
3249	* @returns NULL if the page directory is not present or on an invalid page.
3250	* @param pPGM Pointer to the PGM instance data.
3251	* @param GCPtr The address.
3252	*/
3253	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3254	{
3255	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3256	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3257	{
3258	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3259	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3260
3261	/* cache is out-of-sync. */
3262	PX86PDPAE pPD;
3263	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3264	if (VBOX_SUCCESS(rc))
3265	return pPD;
3266	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3267	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3268	}
3269	return NULL;
3270	}
3271
3272
3273	/**
3274	* Gets the page directory entry for the specified address.
3275	*
3276	* @returns Pointer to the page directory entry in question.
3277	* @returns NULL if the page directory is not present or on an invalid page.
3278	* @param pPGM Pointer to the PGM instance data.
3279	* @param GCPtr The address.
3280	*/
3281	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3282	{
3283	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3284	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3285	{
3286	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3287	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3288	return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3289
3290	/* The cache is out-of-sync. */
3291	PX86PDPAE pPD;
3292	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3293	if (VBOX_SUCCESS(rc))
3294	return &pPD->a[iPD];
3295	AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3296	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3297	}
3298	return NULL;
3299	}
3300
3301
3302	/**
3303	* Gets the page directory entry for the specified address.
3304	*
3305	* @returns The page directory entry in question.
3306	* @returns A non-present entry if the page directory is not present or on an invalid page.
3307	* @param pPGM Pointer to the PGM instance data.
3308	* @param GCPtr The address.
3309	*/
3310	DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3311	{
3312	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3313	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3314	{
3315	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3316	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3317	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3318
3319	/* cache is out-of-sync. */
3320	PX86PDPAE pPD;
3321	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3322	if (VBOX_SUCCESS(rc))
3323	return pPD->a[iPD].u;
3324	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3325	}
3326	return 0ULL;
3327	}
3328
3329
3330	/**
3331	* Gets the page directory pointer table entry for the specified address
3332	* and returns the index into the page directory
3333	*
3334	* @returns Pointer to the page directory in question.
3335	* @returns NULL if the page directory is not present or on an invalid page.
3336	* @param pPGM Pointer to the PGM instance data.
3337	* @param GCPtr The address.
3338	* @param piPD Receives the index into the returned page directory
3339	*/
3340	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3341	{
3342	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3343	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3344	{
3345	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3346	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3347	{
3348	*piPD = iPD;
3349	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3350	}
3351
3352	/* cache is out-of-sync. */
3353	PX86PDPAE pPD;
3354	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3355	if (VBOX_SUCCESS(rc))
3356	{
3357	*piPD = iPD;
3358	return pPD;
3359	}
3360	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3361	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3362	}
3363	return NULL;
3364	}
3365
3366	#ifndef IN_GC
3367	/**
3368	* Gets the page directory pointer entry for the specified address.
3369	*
3370	* @returns Pointer to the page directory pointer entry in question.
3371	* @returns NULL if the page directory is not present or on an invalid page.
3372	* @param pPGM Pointer to the PGM instance data.
3373	* @param GCPtr The address.
3374	* @param ppPml4e Page Map Level-4 Entry (out)
3375	*/
3376	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
3377	{
3378	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3379
3380	Assert(pPGM->pGstPaePML4HC);
3381	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3382	if ((*ppPml4e)->n.u1Present)
3383	{
3384	PX86PDPT pPdpt;
3385	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
3386	if (VBOX_FAILURE(rc))
3387	{
3388	AssertFailed();
3389	return NULL;
3390	}
3391	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3392	return &pPdpt->a[iPdPt];
3393	}
3394	return NULL;
3395	}
3396
3397	/**
3398	* Gets the page directory entry for the specified address.
3399	*
3400	* @returns The page directory entry in question.
3401	* @returns A non-present entry if the page directory is not present or on an invalid page.
3402	* @param pPGM Pointer to the PGM instance data.
3403	* @param GCPtr The address.
3404	* @param ppPml4e Page Map Level-4 Entry (out)
3405	* @param pPdpe Page directory pointer table entry (out)
3406	*/
3407	DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3408	{
3409	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3410
3411	Assert(pPGM->pGstPaePML4HC);
3412	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3413	if ((*ppPml4e)->n.u1Present)
3414	{
3415	PX86PDPT pPdptTemp;
3416	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3417	if (VBOX_FAILURE(rc))
3418	{
3419	AssertFailed();
3420	return 0ULL;
3421	}
3422
3423	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3424	*pPdpe = pPdptTemp->a[iPdPt];
3425	if (pPdpe->n.u1Present)
3426	{
3427	PX86PDPAE pPD;
3428
3429	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3430	if (VBOX_FAILURE(rc))
3431	{
3432	AssertFailed();
3433	return 0ULL;
3434	}
3435	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3436	return pPD->a[iPD].u;
3437	}
3438	}
3439	return 0ULL;
3440	}
3441
3442	/**
3443	* Gets the page directory entry for the specified address.
3444	*
3445	* @returns The page directory entry in question.
3446	* @returns A non-present entry if the page directory is not present or on an invalid page.
3447	* @param pPGM Pointer to the PGM instance data.
3448	* @param GCPtr The address.
3449	*/
3450	DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3451	{
3452	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3453
3454	Assert(pPGM->pGstPaePML4HC);
3455	if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3456	{
3457	PX86PDPT pPdptTemp;
3458	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3459	if (VBOX_FAILURE(rc))
3460	{
3461	AssertFailed();
3462	return 0ULL;
3463	}
3464
3465	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3466	if (pPdptTemp->a[iPdPt].n.u1Present)
3467	{
3468	PX86PDPAE pPD;
3469
3470	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3471	if (VBOX_FAILURE(rc))
3472	{
3473	AssertFailed();
3474	return 0ULL;
3475	}
3476	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3477	return pPD->a[iPD].u;
3478	}
3479	}
3480	return 0ULL;
3481	}
3482
3483	/**
3484	* Gets the page directory entry for the specified address.
3485	*
3486	* @returns Pointer to the page directory entry in question.
3487	* @returns NULL if the page directory is not present or on an invalid page.
3488	* @param pPGM Pointer to the PGM instance data.
3489	* @param GCPtr The address.
3490	*/
3491	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3492	{
3493	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3494
3495	Assert(pPGM->pGstPaePML4HC);
3496	if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3497	{
3498	PX86PDPT pPdptTemp;
3499	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3500	if (VBOX_FAILURE(rc))
3501	{
3502	AssertFailed();
3503	return NULL;
3504	}
3505
3506	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3507	if (pPdptTemp->a[iPdPt].n.u1Present)
3508	{
3509	PX86PDPAE pPD;
3510
3511	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3512	if (VBOX_FAILURE(rc))
3513	{
3514	AssertFailed();
3515	return NULL;
3516	}
3517	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3518	return &pPD->a[iPD];
3519	}
3520	}
3521	return NULL;
3522	}
3523
3524
3525	/**
3526	* Gets the GUEST page directory pointer for the specified address.
3527	*
3528	* @returns The page directory in question.
3529	* @returns NULL if the page directory is not present or on an invalid page.
3530	* @param pPGM Pointer to the PGM instance data.
3531	* @param GCPtr The address.
3532	* @param ppPml4e Page Map Level-4 Entry (out)
3533	* @param pPdpe Page directory pointer table entry (out)
3534	* @param piPD Receives the index into the returned page directory
3535	*/
3536	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
3537	{
3538	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3539
3540	Assert(pPGM->pGstPaePML4HC);
3541	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3542	if ((*ppPml4e)->n.u1Present)
3543	{
3544	PX86PDPT pPdptTemp;
3545	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3546	if (VBOX_FAILURE(rc))
3547	{
3548	AssertFailed();
3549	return 0ULL;
3550	}
3551
3552	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3553	*pPdpe = pPdptTemp->a[iPdPt];
3554	if (pPdpe->n.u1Present)
3555	{
3556	PX86PDPAE pPD;
3557
3558	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3559	if (VBOX_FAILURE(rc))
3560	{
3561	AssertFailed();
3562	return 0ULL;
3563	}
3564	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3565	return pPD;
3566	}
3567	}
3568	return 0ULL;
3569	}
3570
3571	/**
3572	* Gets the GUEST page directory pointer for the specified address.
3573	*
3574	* @returns The page directory in question.
3575	* @returns NULL if the page directory is not present or on an invalid page.
3576	* @param pPGM Pointer to the PGM instance data.
3577	* @param GCPtr The address.
3578	* @param piPD Receives the index into the returned page directory
3579	*/
3580	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, unsigned *piPD)
3581	{
3582	PX86PML4E pPml4e;
3583	PX86PDPE pPdpe;
3584	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3585
3586	Assert(pPGM->pGstPaePML4HC);
3587	pPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3588	if (pPml4e->n.u1Present)
3589	{
3590	PX86PDPT pPdptTemp;
3591	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3592	if (VBOX_FAILURE(rc))
3593	{
3594	AssertFailed();
3595	return 0ULL;
3596	}
3597
3598	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3599	pPdpe = &pPdptTemp->a[iPdPt];
3600	if (pPdpe->n.u1Present)
3601	{
3602	PX86PDPAE pPD;
3603
3604	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3605	if (VBOX_FAILURE(rc))
3606	{
3607	AssertFailed();
3608	return 0ULL;
3609	}
3610	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3611	return pPD;
3612	}
3613	}
3614	return 0ULL;
3615	}
3616
3617	#endif /* !IN_GC */
3618
3619	/**
3620	* Checks if any of the specified page flags are set for the given page.
3621	*
3622	* @returns true if any of the flags are set.
3623	* @returns false if all the flags are clear.
3624	* @param pPGM PGM handle.
3625	* @param GCPhys The GC physical address.
3626	* @param fFlags The flags to check for.
3627	*/
3628	DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3629	{
3630	PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3631	return pPage
3632	&& (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3633	}
3634
3635
3636	/**
3637	* Gets the page state for a physical handler.
3638	*
3639	* @returns The physical handler page state.
3640	* @param pCur The physical handler in question.
3641	*/
3642	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3643	{
3644	switch (pCur->enmType)
3645	{
3646	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3647	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3648
3649	case PGMPHYSHANDLERTYPE_MMIO:
3650	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3651	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3652
3653	default:
3654	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3655	}
3656	}
3657
3658
3659	/**
3660	* Gets the page state for a virtual handler.
3661	*
3662	* @returns The virtual handler page state.
3663	* @param pCur The virtual handler in question.
3664	* @remarks This should never be used on a hypervisor access handler.
3665	*/
3666	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3667	{
3668	switch (pCur->enmType)
3669	{
3670	case PGMVIRTHANDLERTYPE_WRITE:
3671	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3672	case PGMVIRTHANDLERTYPE_ALL:
3673	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3674	default:
3675	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3676	}
3677	}
3678
3679
3680	/**
3681	* Clears one physical page of a virtual handler
3682	*
3683	* @param pPGM Pointer to the PGM instance.
3684	* @param pCur Virtual handler structure
3685	* @param iPage Physical page index
3686	*
3687	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3688	* need to care about other handlers in the same page.
3689	*/
3690	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3691	{
3692	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3693
3694	/*
3695	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
3696	*/
3697	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3698	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3699	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3700	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3701	#endif
3702	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3703	{
3704	/* We're the head of the alias chain. */
3705	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3706	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3707	AssertReleaseMsg(pRemove != NULL,
3708	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3709	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3710	AssertReleaseMsg(pRemove == pPhys2Virt,
3711	("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3712	" got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3713	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3714	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3715	#endif
3716	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3717	{
3718	/* Insert the next list in the alias chain into the tree. */
3719	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3720	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3721	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3722	("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3723	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3724	#endif
3725	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
3726	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3727	AssertRelease(fRc);
3728	}
3729	}
3730	else
3731	{
3732	/* Locate the previous node in the alias chain. */
3733	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3734	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3735	AssertReleaseMsg(pPrev != pPhys2Virt,
3736	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3737	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3738	#endif
3739	for (;;)
3740	{
3741	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3742	if (pNext == pPhys2Virt)
3743	{
3744	/* unlink. */
3745	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3746	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3747	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3748	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3749	else
3750	{
3751	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3752	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3753	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3754	}
3755	break;
3756	}
3757
3758	/* next */
3759	if (pNext == pPrev)
3760	{
3761	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3762	AssertReleaseMsg(pNext != pPrev,
3763	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3764	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3765	#endif
3766	break;
3767	}
3768	pPrev = pNext;
3769	}
3770	}
3771	Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3772	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3773	pPhys2Virt->offNextAlias = 0;
3774	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3775
3776	/*
3777	* Clear the ram flags for this page.
3778	*/
3779	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3780	AssertReturnVoid(pPage);
3781	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3782	}
3783
3784
3785	/**
3786	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
3787	*
3788	* @returns Pointer to the shadow page structure.
3789	* @param pPool The pool.
3790	* @param HCPhys The HC physical address of the shadow page.
3791	*/
3792	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3793	{
3794	/*
3795	* Look up the page.
3796	*/
3797	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3798	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3799	return pPage;
3800	}
3801
3802
3803	/**
3804	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
3805	*
3806	* @returns Pointer to the shadow page structure.
3807	* @param pPool The pool.
3808	* @param idx The pool page index.
3809	*/
3810	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3811	{
3812	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3813	return &pPool->aPages[idx];
3814	}
3815
3816
3817	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3818	/**
3819	* Clear references to guest physical memory.
3820	*
3821	* @param pPool The pool.
3822	* @param pPoolPage The pool page.
3823	* @param pPhysPage The physical guest page tracking structure.
3824	*/
3825	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3826	{
3827	/*
3828	* Just deal with the simple case here.
3829	*/
3830	#ifdef LOG_ENABLED
3831	const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3832	#endif
3833	const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3834	if (cRefs == 1)
3835	{
3836	Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3837	pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3838	}
3839	else
3840	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3841	LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3842	}
3843	#endif
3844
3845
3846	#ifdef PGMPOOL_WITH_CACHE
3847	/**
3848	* Moves the page to the head of the age list.
3849	*
3850	* This is done when the cached page is used in one way or another.
3851	*
3852	* @param pPool The pool.
3853	* @param pPage The cached page.
3854	* @todo inline in PGMInternal.h!
3855	*/
3856	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3857	{
3858	/*
3859	* Move to the head of the age list.
3860	*/
3861	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3862	{
3863	/* unlink */
3864	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3865	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3866	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3867	else
3868	pPool->iAgeTail = pPage->iAgePrev;
3869
3870	/* insert at head */
3871	pPage->iAgePrev = NIL_PGMPOOL_IDX;
3872	pPage->iAgeNext = pPool->iAgeHead;
3873	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3874	pPool->iAgeHead = pPage->idx;
3875	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3876	}
3877	}
3878	#endif /* PGMPOOL_WITH_CACHE */
3879
3880	/**
3881	* Tells if mappings are to be put into the shadow page table or not
3882	*
3883	* @returns boolean result
3884	* @param pVM VM handle.
3885	*/
3886
3887	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3888	{
3889	#ifdef IN_RING0
3890	/* There are no mappings in VT-x and AMD-V mode. */
3891	Assert(pPGM->fDisableMappings);
3892	return false;
3893	#else
3894	return !pPGM->fDisableMappings;
3895	#endif
3896	}
3897
3898	/** @} */
3899
3900	#endif

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 11147

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