PGMInternal.h@ 35273

Last change on this file since 35273 was 34163, checked in by vboxsync, 14 years ago
PGMR3PhysRomRegister/PDMDevHlpROMRegister: Added cbBinary argument to allow specifying a binary smaller than the range (no alignment restrictions either). Untested.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 174.7 KB

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1	/* $Id: PGMInternal.h 34163 2010-11-18 12:16:43Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/dbg.h>
25	#include <VBox/stam.h>
26	#include <VBox/param.h>
27	#include <VBox/vmm.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdmcritsect.h>
30	#include <VBox/pdmapi.h>
31	#include <VBox/dis.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/log.h>
34	#include <VBox/gmm.h>
35	#include <VBox/hwaccm.h>
36	#include <VBox/hwacc_vmx.h>
37	#include <include/internal/pgm.h>
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/avl.h>
41	#include <iprt/critsect.h>
42	#include <iprt/sha.h>
43
44
45
46	/** @defgroup grp_pgm_int Internals
47	* @ingroup grp_pgm
48	* @internal
49	* @{
50	*/
51
52
53	/** @name PGM Compile Time Config
54	* @{
55	*/
56
57	/**
58	* Indicates that there are no guest mappings to care about.
59	* Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60	*/
61	#if defined(IN_RING0) \|\| !defined(VBOX_WITH_RAW_MODE)
62	# define PGM_WITHOUT_MAPPINGS
63	#endif
64
65	/**
66	* Check and skip global PDEs for non-global flushes
67	*/
68	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70	/**
71	* Optimization for PAE page tables that are modified often
72	*/
73	//#if 0 /* disabled again while debugging */
74	#ifndef IN_RC
75	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76	#endif
77	//#endif
78
79	/**
80	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
81	*/
82	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83	# define PGM_WITH_LARGE_PAGES
84	#endif
85
86	/**
87	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88	* VMX_EXIT_EPT_MISCONFIG.
89	*/
90	#if 1 /* testing */
91	# define PGM_WITH_MMIO_OPTIMIZATIONS
92	#endif
93
94	/**
95	* Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96	*/
97	#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98	# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99	#endif
100
101	/**
102	* Sync N pages instead of a whole page table
103	*/
104	#define PGM_SYNC_N_PAGES
105
106	/**
107	* Number of pages to sync during a page fault
108	*
109	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111	*
112	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113	* world switch overhead, so let's sync more.
114	*/
115	# ifdef IN_RING0
116	/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118	* but ~5% fewer faults.
119	*/
120	# define PGM_SYNC_NR_PAGES 32
121	#else
122	# define PGM_SYNC_NR_PAGES 8
123	#endif
124
125	/**
126	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127	*/
128	#define PGM_MAX_PHYSCACHE_ENTRIES 64
129	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132	/** @def PGMPOOL_CFG_MAX_GROW
133	* The maximum number of pages to add to the pool in one go.
134	*/
135	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
139	*/
140	#ifdef VBOX_STRICT
141	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142	#endif
143
144	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145	* Enables the experimental lazy page allocation code. */
146	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
147
148	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149	* Enables real write monitoring of pages, i.e. mapping them read-only and
150	* only making them writable when getting a write access #PF. */
151	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153	/** @} */
154
155
156	/** @name PDPT and PML4 flags.
157	* These are placed in the three bits available for system programs in
158	* the PDPT and PML4 entries.
159	* @{ */
160	/** The entry is a permanent one and it's must always be present.
161	* Never free such an entry. */
162	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163	/** Mapping (hypervisor allocated pagetable). */
164	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165	/** @} */
166
167	/** @name Page directory flags.
168	* These are placed in the three bits available for system programs in
169	* the page directory entries.
170	* @{ */
171	/** Mapping (hypervisor allocated pagetable). */
172	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173	/** Made read-only to facilitate dirty bit tracking. */
174	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175	/** @} */
176
177	/** @name Page flags.
178	* These are placed in the three bits available for system programs in
179	* the page entries.
180	* @{ */
181	/** Made read-only to facilitate dirty bit tracking. */
182	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185	/** Scanned and approved by CSAM (tm).
186	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
187	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
188	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189	#endif
190
191	/** @} */
192
193	/** @name Defines used to indicate the shadow and guest paging in the templates.
194	* @{ */
195	#define PGM_TYPE_REAL 1
196	#define PGM_TYPE_PROT 2
197	#define PGM_TYPE_32BIT 3
198	#define PGM_TYPE_PAE 4
199	#define PGM_TYPE_AMD64 5
200	#define PGM_TYPE_NESTED 6
201	#define PGM_TYPE_EPT 7
202	#define PGM_TYPE_MAX PGM_TYPE_EPT
203	/** @} */
204
205	/** Macro for checking if the guest is using paging.
206	* @param uGstType PGM_TYPE_*
207	* @param uShwType PGM_TYPE_*
208	* @remark ASSUMES certain order of the PGM_TYPE_* values.
209	*/
210	#define PGM_WITH_PAGING(uGstType, uShwType) \
211	( (uGstType) >= PGM_TYPE_32BIT \
212	&& (uShwType) != PGM_TYPE_NESTED \
213	&& (uShwType) != PGM_TYPE_EPT)
214
215	/** Macro for checking if the guest supports the NX bit.
216	* @param uGstType PGM_TYPE_*
217	* @param uShwType PGM_TYPE_*
218	* @remark ASSUMES certain order of the PGM_TYPE_* values.
219	*/
220	#define PGM_WITH_NX(uGstType, uShwType) \
221	( (uGstType) >= PGM_TYPE_PAE \
222	&& (uShwType) != PGM_TYPE_NESTED \
223	&& (uShwType) != PGM_TYPE_EPT)
224
225
226	/** @def PGM_HCPHYS_2_PTR
227	* Maps a HC physical page pool address to a virtual address.
228	*
229	* @returns VBox status code.
230	* @param pVM The VM handle.
231	* @param pVCpu The current CPU.
232	* @param HCPhys The HC physical address to map to a virtual one.
233	* @param ppv Where to store the virtual address. No need to cast
234	* this.
235	*
236	* @remark Use with care as we don't have so much dynamic mapping space in
237	* ring-0 on 32-bit darwin and in RC.
238	* @remark There is no need to assert on the result.
239	*/
240	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
241	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243	#else
244	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246	#endif
247
248	/** @def PGM_GCPHYS_2_PTR_V2
249	* Maps a GC physical page address to a virtual address.
250	*
251	* @returns VBox status code.
252	* @param pVM The VM handle.
253	* @param pVCpu The current CPU.
254	* @param GCPhys The GC physical address to map to a virtual one.
255	* @param ppv Where to store the virtual address. No need to cast this.
256	*
257	* @remark Use with care as we don't have so much dynamic mapping space in
258	* ring-0 on 32-bit darwin and in RC.
259	* @remark There is no need to assert on the result.
260	*/
261	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
262	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264	#else
265	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267	#endif
268
269	/** @def PGM_GCPHYS_2_PTR
270	* Maps a GC physical page address to a virtual address.
271	*
272	* @returns VBox status code.
273	* @param pVM The VM handle.
274	* @param GCPhys The GC physical address to map to a virtual one.
275	* @param ppv Where to store the virtual address. No need to cast this.
276	*
277	* @remark Use with care as we don't have so much dynamic mapping space in
278	* ring-0 on 32-bit darwin and in RC.
279	* @remark There is no need to assert on the result.
280	*/
281	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284	* Maps a GC physical page address to a virtual address.
285	*
286	* @returns VBox status code.
287	* @param pVCpu The current CPU.
288	* @param GCPhys The GC physical address to map to a virtual one.
289	* @param ppv Where to store the virtual address. No need to cast this.
290	*
291	* @remark Use with care as we don't have so much dynamic mapping space in
292	* ring-0 on 32-bit darwin and in RC.
293	* @remark There is no need to assert on the result.
294	*/
295	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297	/** @def PGM_GCPHYS_2_PTR_EX
298	* Maps a unaligned GC physical page address to a virtual address.
299	*
300	* @returns VBox status code.
301	* @param pVM The VM handle.
302	* @param GCPhys The GC physical address to map to a virtual one.
303	* @param ppv Where to store the virtual address. No need to cast this.
304	*
305	* @remark Use with care as we don't have so much dynamic mapping space in
306	* ring-0 on 32-bit darwin and in RC.
307	* @remark There is no need to assert on the result.
308	*/
309	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312	#else
313	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315	#endif
316
317	/** @def PGM_DYNMAP_UNUSED_HINT
318	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319	* is no longer used.
320	*
321	* For best effect only apply this to the page that was mapped most recently.
322	*
323	* @param pVCpu The current CPU.
324	* @param pPage The pool page.
325	*/
326	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327	# ifdef LOG_ENABLED
328	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329	# else
330	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331	# endif
332	#else
333	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334	#endif
335
336	/** @def PGM_DYNMAP_UNUSED_HINT_VM
337	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338	* is no longer used.
339	*
340	* For best effect only apply this to the page that was mapped most recently.
341	*
342	* @param pVM The VM handle.
343	* @param pPage The pool page.
344	*/
345	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348	/** @def PGM_INVL_PG
349	* Invalidates a page.
350	*
351	* @param pVCpu The VMCPU handle.
352	* @param GCVirt The virtual address of the page to invalidate.
353	*/
354	#ifdef IN_RC
355	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356	#elif defined(IN_RING0)
357	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358	#else
359	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360	#endif
361
362	/** @def PGM_INVL_PG_ALL_VCPU
363	* Invalidates a page on all VCPUs
364	*
365	* @param pVM The VM handle.
366	* @param GCVirt The virtual address of the page to invalidate.
367	*/
368	#ifdef IN_RC
369	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370	#elif defined(IN_RING0)
371	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372	#else
373	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374	#endif
375
376	/** @def PGM_INVL_BIG_PG
377	* Invalidates a 4MB page directory entry.
378	*
379	* @param pVCpu The VMCPU handle.
380	* @param GCVirt The virtual address within the page directory to invalidate.
381	*/
382	#ifdef IN_RC
383	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384	#elif defined(IN_RING0)
385	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386	#else
387	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388	#endif
389
390	/** @def PGM_INVL_VCPU_TLBS()
391	* Invalidates the TLBs of the specified VCPU
392	*
393	* @param pVCpu The VMCPU handle.
394	*/
395	#ifdef IN_RC
396	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397	#elif defined(IN_RING0)
398	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399	#else
400	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401	#endif
402
403	/** @def PGM_INVL_ALL_VCPU_TLBS()
404	* Invalidates the TLBs of all VCPUs
405	*
406	* @param pVM The VM handle.
407	*/
408	#ifdef IN_RC
409	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410	#elif defined(IN_RING0)
411	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412	#else
413	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414	#endif
415
416
417	/** @name Safer Shadow PAE PT/PTE
418	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419	* present.
420	*
421	* @{
422	*/
423	#if 1
424	/**
425	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
426	* invalid entries for present.
427	* @sa X86PTEPAE.
428	*/
429	typedef union PGMSHWPTEPAE
430	{
431	/** Unsigned integer view */
432	X86PGPAEUINT uCareful;
433	/* Not other views. */
434	} PGMSHWPTEPAE;
435
436	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
443	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
446	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
452
453	/**
454	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
455	* invalid entries for present.
456	* @sa X86PTPAE.
457	*/
458	typedef struct PGMSHWPTPAE
459	{
460	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461	} PGMSHWPTPAE;
462
463	#else
464	typedef X86PTEPAE PGMSHWPTEPAE;
465	typedef X86PTPAE PGMSHWPTPAE;
466	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
473	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
476	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
482
483	#endif
484
485	/** Pointer to a shadow PAE PTE. */
486	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487	/** Pointer to a const shadow PAE PTE. */
488	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490	/** Pointer to a shadow PAE page table. */
491	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492	/** Pointer to a const shadow PAE page table. */
493	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494	/** @} */
495
496
497	/** Size of the GCPtrConflict array in PGMMAPPING.
498	* @remarks Must be a power of two. */
499	#define PGMMAPPING_CONFLICT_MAX 8
500
501	/**
502	* Structure for tracking GC Mappings.
503	*
504	* This structure is used by linked list in both GC and HC.
505	*/
506	typedef struct PGMMAPPING
507	{
508	/** Pointer to next entry. */
509	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510	/** Pointer to next entry. */
511	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512	/** Pointer to next entry. */
513	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514	/** Indicate whether this entry is finalized. */
515	bool fFinalized;
516	/** Start Virtual address. */
517	RTGCPTR GCPtr;
518	/** Last Virtual address (inclusive). */
519	RTGCPTR GCPtrLast;
520	/** Range size (bytes). */
521	RTGCPTR cb;
522	/** Pointer to relocation callback function. */
523	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524	/** User argument to the callback. */
525	R3PTRTYPE(void *) pvUser;
526	/** Mapping description / name. For easing debugging. */
527	R3PTRTYPE(const char *) pszDesc;
528	/** Last 8 addresses that caused conflicts. */
529	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530	/** Number of conflicts for this hypervisor mapping. */
531	uint32_t cConflicts;
532	/** Number of page tables. */
533	uint32_t cPTs;
534
535	/** Array of page table mapping data. Each entry
536	* describes one page table. The array can be longer
537	* than the declared length.
538	*/
539	struct
540	{
541	/** The HC physical address of the page table. */
542	RTHCPHYS HCPhysPT;
543	/** The HC physical address of the first PAE page table. */
544	RTHCPHYS HCPhysPaePT0;
545	/** The HC physical address of the second PAE page table. */
546	RTHCPHYS HCPhysPaePT1;
547	/** The HC virtual address of the 32-bit page table. */
548	R3PTRTYPE(PX86PT) pPTR3;
549	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551	/** The RC virtual address of the 32-bit page table. */
552	RCPTRTYPE(PX86PT) pPTRC;
553	/** The RC virtual address of the two PAE page table. */
554	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555	/** The R0 virtual address of the 32-bit page table. */
556	R0PTRTYPE(PX86PT) pPTR0;
557	/** The R0 virtual address of the two PAE page table. */
558	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559	} aPTs[1];
560	} PGMMAPPING;
561	/** Pointer to structure for tracking GC Mappings. */
562	typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565	/**
566	* Physical page access handler structure.
567	*
568	* This is used to keep track of physical address ranges
569	* which are being monitored in some kind of way.
570	*/
571	typedef struct PGMPHYSHANDLER
572	{
573	AVLROGCPHYSNODECORE Core;
574	/** Access type. */
575	PGMPHYSHANDLERTYPE enmType;
576	/** Number of pages to update. */
577	uint32_t cPages;
578	/** Set if we have pages that have been aliased. */
579	uint32_t cAliasedPages;
580	/** Set if we have pages that have temporarily been disabled. */
581	uint32_t cTmpOffPages;
582	/** Pointer to R3 callback function. */
583	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
584	/** User argument for R3 handlers. */
585	R3PTRTYPE(void *) pvUserR3;
586	/** Pointer to R0 callback function. */
587	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
588	/** User argument for R0 handlers. */
589	R0PTRTYPE(void *) pvUserR0;
590	/** Pointer to RC callback function. */
591	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
592	/** User argument for RC handlers. */
593	RCPTRTYPE(void *) pvUserRC;
594	/** Description / Name. For easing debugging. */
595	R3PTRTYPE(const char *) pszDesc;
596	#ifdef VBOX_WITH_STATISTICS
597	/** Profiling of this handler. */
598	STAMPROFILE Stat;
599	#endif
600	} PGMPHYSHANDLER;
601	/** Pointer to a physical page access handler structure. */
602	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
603
604
605	/**
606	* Cache node for the physical addresses covered by a virtual handler.
607	*/
608	typedef struct PGMPHYS2VIRTHANDLER
609	{
610	/** Core node for the tree based on physical ranges. */
611	AVLROGCPHYSNODECORE Core;
612	/** Offset from this struct to the PGMVIRTHANDLER structure. */
613	int32_t offVirtHandler;
614	/** Offset of the next alias relative to this one.
615	* Bit 0 is used for indicating whether we're in the tree.
616	* Bit 1 is used for indicating that we're the head node.
617	*/
618	int32_t offNextAlias;
619	} PGMPHYS2VIRTHANDLER;
620	/** Pointer to a phys to virtual handler structure. */
621	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
622
623	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
624	* node is in the tree. */
625	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
626	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
627	* node is in the head of an alias chain.
628	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
629	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
630	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
631	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
632
633
634	/**
635	* Virtual page access handler structure.
636	*
637	* This is used to keep track of virtual address ranges
638	* which are being monitored in some kind of way.
639	*/
640	typedef struct PGMVIRTHANDLER
641	{
642	/** Core node for the tree based on virtual ranges. */
643	AVLROGCPTRNODECORE Core;
644	/** Size of the range (in bytes). */
645	RTGCPTR cb;
646	/** Number of cache pages. */
647	uint32_t cPages;
648	/** Access type. */
649	PGMVIRTHANDLERTYPE enmType;
650	/** Pointer to the RC callback function. */
651	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
652	#if HC_ARCH_BITS == 64
653	RTRCPTR padding;
654	#endif
655	/** Pointer to the R3 callback function for invalidation. */
656	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
657	/** Pointer to the R3 callback function. */
658	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
659	/** Description / Name. For easing debugging. */
660	R3PTRTYPE(const char *) pszDesc;
661	#ifdef VBOX_WITH_STATISTICS
662	/** Profiling of this handler. */
663	STAMPROFILE Stat;
664	#endif
665	/** Array of cached physical addresses for the monitored ranged. */
666	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
667	} PGMVIRTHANDLER;
668	/** Pointer to a virtual page access handler structure. */
669	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
670
671
672	/** @name Page type predicates.
673	* @{ */
674	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
675	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
676	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
677	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
678	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
679	/** @} */
680
681
682	/**
683	* A Physical Guest Page tracking structure.
684	*
685	* The format of this structure is complicated because we have to fit a lot
686	* of information into as few bits as possible. The format is also subject
687	* to change (there is one coming up soon). Which means that for we'll be
688	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
689	* accesses to the structure.
690	*/
691	typedef struct PGMPAGE
692	{
693	/** The physical address and the Page ID. */
694	RTHCPHYS HCPhysAndPageID;
695	/** Combination of:
696	* - [0-7]: u2HandlerPhysStateY - the physical handler state
697	* (PGM_PAGE_HNDL_PHYS_STATE_*).
698	* - [8-9]: u2HandlerVirtStateY - the virtual handler state
699	* (PGM_PAGE_HNDL_VIRT_STATE_*).
700	* - [10]: u1FTDirty - indicator of dirty page for fault tolerance tracking
701	* - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
702	* - [15]: fWrittenToY - flag indicating that a write monitored page was
703	* written to when set.
704	* - [11-13]: 3 unused bits.
705	* @remarks Warning! All accesses to the bits are hardcoded.
706	*
707	* @todo Change this to a union with both bitfields, u8 and u accessors.
708	* That'll help deal with some of the hardcoded accesses.
709	*
710	* @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
711	* will make it possible to turn some of the 16-bit accesses into
712	* 32-bit ones, which may be efficient (stalls).
713	*/
714	RTUINT16U u16MiscY;
715	/** The page state.
716	* Only 3 bits are really needed for this. */
717	uint16_t uStateY : 3;
718	/** The page type (PGMPAGETYPE).
719	* Only 3 bits are really needed for this. */
720	uint16_t uTypeY : 3;
721	/** PTE index for usage tracking (page pool). */
722	uint16_t uPteIdx : 10;
723	/** Usage tracking (page pool). */
724	uint16_t u16TrackingY;
725	/** The number of read locks on this page. */
726	uint8_t cReadLocksY;
727	/** The number of write locks on this page. */
728	uint8_t cWriteLocksY;
729	} PGMPAGE;
730	AssertCompileSize(PGMPAGE, 16);
731	/** Pointer to a physical guest page. */
732	typedef PGMPAGE *PPGMPAGE;
733	/** Pointer to a const physical guest page. */
734	typedef const PGMPAGE *PCPGMPAGE;
735	/** Pointer to a physical guest page pointer. */
736	typedef PPGMPAGE *PPPGMPAGE;
737
738
739	/**
740	* Clears the page structure.
741	* @param pPage Pointer to the physical guest page tracking structure.
742	*/
743	#define PGM_PAGE_CLEAR(pPage) \
744	do { \
745	(pPage)->HCPhysAndPageID = 0; \
746	(pPage)->uStateY = 0; \
747	(pPage)->uTypeY = 0; \
748	(pPage)->uPteIdx = 0; \
749	(pPage)->u16MiscY.u = 0; \
750	(pPage)->u16TrackingY = 0; \
751	(pPage)->cReadLocksY = 0; \
752	(pPage)->cWriteLocksY = 0; \
753	} while (0)
754
755	/**
756	* Initializes the page structure.
757	* @param pPage Pointer to the physical guest page tracking structure.
758	*/
759	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
760	do { \
761	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
762	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
763	(pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) \| ((_idPage) & UINT32_C(0x0fffffff)); \
764	(pPage)->uStateY = (_uState); \
765	(pPage)->uTypeY = (_uType); \
766	(pPage)->uPteIdx = 0; \
767	(pPage)->u16MiscY.u = 0; \
768	(pPage)->u16TrackingY = 0; \
769	(pPage)->cReadLocksY = 0; \
770	(pPage)->cWriteLocksY = 0; \
771	} while (0)
772
773	/**
774	* Initializes the page structure of a ZERO page.
775	* @param pPage Pointer to the physical guest page tracking structure.
776	* @param pVM The VM handle (for getting the zero page address).
777	* @param uType The page type (PGMPAGETYPE).
778	*/
779	#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
780	PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
781
782
783	/** @name The Page state, PGMPAGE::uStateY.
784	* @{ */
785	/** The zero page.
786	* This is a per-VM page that's never ever mapped writable. */
787	#define PGM_PAGE_STATE_ZERO 0
788	/** A allocated page.
789	* This is a per-VM page allocated from the page pool (or wherever
790	* we get MMIO2 pages from if the type is MMIO2).
791	*/
792	#define PGM_PAGE_STATE_ALLOCATED 1
793	/** A allocated page that's being monitored for writes.
794	* The shadow page table mappings are read-only. When a write occurs, the
795	* fWrittenTo member is set, the page remapped as read-write and the state
796	* moved back to allocated. */
797	#define PGM_PAGE_STATE_WRITE_MONITORED 2
798	/** The page is shared, aka. copy-on-write.
799	* This is a page that's shared with other VMs. */
800	#define PGM_PAGE_STATE_SHARED 3
801	/** The page is ballooned, so no longer available for this VM. */
802	#define PGM_PAGE_STATE_BALLOONED 4
803	/** @} */
804
805
806	/**
807	* Gets the page state.
808	* @returns page state (PGM_PAGE_STATE_*).
809	* @param pPage Pointer to the physical guest page tracking structure.
810	*/
811	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
812
813	/**
814	* Sets the page state.
815	* @param pPage Pointer to the physical guest page tracking structure.
816	* @param _uState The new page state.
817	*/
818	#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
819
820
821	/**
822	* Gets the host physical address of the guest page.
823	* @returns host physical address (RTHCPHYS).
824	* @param pPage Pointer to the physical guest page tracking structure.
825	*/
826	#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
827
828	/**
829	* Sets the host physical address of the guest page.
830	* @param pPage Pointer to the physical guest page tracking structure.
831	* @param _HCPhys The new host physical address.
832	*/
833	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
834	do { \
835	RTHCPHYS SetHCPhysTmp = (_HCPhys); \
836	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
837	(pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
838	\| (SetHCPhysTmp << (28-12)); \
839	} while (0)
840
841	/**
842	* Get the Page ID.
843	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
844	* @param pPage Pointer to the physical guest page tracking structure.
845	*/
846	#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
847
848	/**
849	* Sets the Page ID.
850	* @param pPage Pointer to the physical guest page tracking structure.
851	*/
852	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
853	do { \
854	(pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
855	\| ((_idPage) & UINT32_C(0x0fffffff)); \
856	} while (0)
857
858	/**
859	* Get the Chunk ID.
860	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
861	* @param pPage Pointer to the physical guest page tracking structure.
862	*/
863	#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
864
865	/**
866	* Get the index of the page within the allocation chunk.
867	* @returns The page index.
868	* @param pPage Pointer to the physical guest page tracking structure.
869	*/
870	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
871
872	/**
873	* Gets the page type.
874	* @returns The page type.
875	* @param pPage Pointer to the physical guest page tracking structure.
876	*/
877	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
878
879	/**
880	* Sets the page type.
881	* @param pPage Pointer to the physical guest page tracking structure.
882	* @param _enmType The new page type (PGMPAGETYPE).
883	*/
884	#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
885
886	/**
887	* Gets the page table index
888	* @returns The page table index.
889	* @param pPage Pointer to the physical guest page tracking structure.
890	*/
891	#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
892
893	/**
894	* Sets the page table index
895	* @param pPage Pointer to the physical guest page tracking structure.
896	* @param iPte New page table index.
897	*/
898	#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
899
900	/**
901	* Checks if the page is marked for MMIO.
902	* @returns true/false.
903	* @param pPage Pointer to the physical guest page tracking structure.
904	*/
905	#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
906
907	/**
908	* Checks if the page is backed by the ZERO page.
909	* @returns true/false.
910	* @param pPage Pointer to the physical guest page tracking structure.
911	*/
912	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
913
914	/**
915	* Checks if the page is backed by a SHARED page.
916	* @returns true/false.
917	* @param pPage Pointer to the physical guest page tracking structure.
918	*/
919	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
920
921	/**
922	* Checks if the page is ballooned.
923	* @returns true/false.
924	* @param pPage Pointer to the physical guest page tracking structure.
925	*/
926	#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
927
928	/**
929	* Marks the page as written to (for GMM change monitoring).
930	* @param pPage Pointer to the physical guest page tracking structure.
931	*/
932	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] \|= UINT8_C(0x80); } while (0)
933
934	/**
935	* Clears the written-to indicator.
936	* @param pPage Pointer to the physical guest page tracking structure.
937	*/
938	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
939
940	/**
941	* Checks if the page was marked as written-to.
942	* @returns true/false.
943	* @param pPage Pointer to the physical guest page tracking structure.
944	*/
945	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
946
947	/**
948	* Marks the page as dirty for FTM
949	* @param pPage Pointer to the physical guest page tracking structure.
950	*/
951	#define PGM_PAGE_SET_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] \|= UINT8_C(0x04); } while (0)
952
953	/**
954	* Clears the FTM dirty indicator
955	* @param pPage Pointer to the physical guest page tracking structure.
956	*/
957	#define PGM_PAGE_CLEAR_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0xfb); } while (0)
958
959	/**
960	* Checks if the page was marked as dirty for FTM
961	* @returns true/false.
962	* @param pPage Pointer to the physical guest page tracking structure.
963	*/
964	#define PGM_PAGE_IS_FT_DIRTY(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x04)) )
965
966
967	/** @name PT usage values (PGMPAGE::u2PDEType).
968	*
969	* @{ */
970	/** Either as a PT or PDE. */
971	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
972	/** Must use a page table to map the range. */
973	#define PGM_PAGE_PDE_TYPE_PT 1
974	/** Can use a page directory entry to map the continuous range. */
975	#define PGM_PAGE_PDE_TYPE_PDE 2
976	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
977	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
978	/** @} */
979
980	/**
981	* Set the PDE type of the page
982	* @param pPage Pointer to the physical guest page tracking structure.
983	* @param uType PGM_PAGE_PDE_TYPE_*
984	*/
985	#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
986	do { \
987	(pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
988	\| (((uType) & UINT8_C(0x03)) << 5); \
989	} while (0)
990
991	/**
992	* Checks if the page was marked being part of a large page
993	* @returns true/false.
994	* @param pPage Pointer to the physical guest page tracking structure.
995	*/
996	#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
997
998	/** Enabled optimized access handler tests.
999	* These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
1000	* layout. When enabled, the compiler should normally generate more compact
1001	* code.
1002	*/
1003	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1004
1005	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1006	*
1007	* @remarks The values are assigned in order of priority, so we can calculate
1008	* the correct state for a page with different handlers installed.
1009	* @{ */
1010	/** No handler installed. */
1011	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1012	/** Monitoring is temporarily disabled. */
1013	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1014	/** Write access is monitored. */
1015	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1016	/** All access is monitored. */
1017	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1018	/** @} */
1019
1020	/**
1021	* Gets the physical access handler state of a page.
1022	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1023	* @param pPage Pointer to the physical guest page tracking structure.
1024	*/
1025	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
1026	( (pPage)->u16MiscY.au8[0] )
1027
1028	/**
1029	* Sets the physical access handler state of a page.
1030	* @param pPage Pointer to the physical guest page tracking structure.
1031	* @param _uState The new state value.
1032	*/
1033	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
1034	do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
1035
1036	/**
1037	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1038	* @returns true/false
1039	* @param pPage Pointer to the physical guest page tracking structure.
1040	*/
1041	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
1042	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1043
1044	/**
1045	* Checks if the page has any active physical access handlers.
1046	* @returns true/false
1047	* @param pPage Pointer to the physical guest page tracking structure.
1048	*/
1049	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
1050	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1051
1052
1053	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1054	*
1055	* @remarks The values are assigned in order of priority, so we can calculate
1056	* the correct state for a page with different handlers installed.
1057	* @{ */
1058	/** No handler installed. */
1059	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1060	/* 1 is reserved so the lineup is identical with the physical ones. */
1061	/** Write access is monitored. */
1062	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1063	/** All access is monitored. */
1064	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1065	/** @} */
1066
1067	/**
1068	* Gets the virtual access handler state of a page.
1069	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1070	* @param pPage Pointer to the physical guest page tracking structure.
1071	*/
1072	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
1073
1074	/**
1075	* Sets the virtual access handler state of a page.
1076	* @param pPage Pointer to the physical guest page tracking structure.
1077	* @param _uState The new state value.
1078	*/
1079	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1080	do { \
1081	(pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1082	\| ((_uState) & UINT8_C(0x03)); \
1083	} while (0)
1084
1085	/**
1086	* Checks if the page has any virtual access handlers.
1087	* @returns true/false
1088	* @param pPage Pointer to the physical guest page tracking structure.
1089	*/
1090	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1091	( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1092
1093	/**
1094	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1095	* virtual handlers.
1096	* @returns true/false
1097	* @param pPage Pointer to the physical guest page tracking structure.
1098	*/
1099	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1100	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1101
1102
1103	/**
1104	* Checks if the page has any access handlers, including temporarily disabled ones.
1105	* @returns true/false
1106	* @param pPage Pointer to the physical guest page tracking structure.
1107	*/
1108	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1109	# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1110	( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1111	#else
1112	# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1113	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1114	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1115	#endif
1116
1117	/**
1118	* Checks if the page has any active access handlers.
1119	* @returns true/false
1120	* @param pPage Pointer to the physical guest page tracking structure.
1121	*/
1122	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1123	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1124	( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1125	#else
1126	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1127	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1128	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1129	#endif
1130
1131	/**
1132	* Checks if the page has any active access handlers catching all accesses.
1133	* @returns true/false
1134	* @param pPage Pointer to the physical guest page tracking structure.
1135	*/
1136	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1137	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1138	( ( ((pPage)->u16MiscY.au8[0] \| (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1139	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1140	#else
1141	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1142	( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1143	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1144	#endif
1145
1146
1147	/** @def PGM_PAGE_GET_TRACKING
1148	* Gets the packed shadow page pool tracking data associated with a guest page.
1149	* @returns uint16_t containing the data.
1150	* @param pPage Pointer to the physical guest page tracking structure.
1151	*/
1152	#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1153
1154	/** @def PGM_PAGE_SET_TRACKING
1155	* Sets the packed shadow page pool tracking data associated with a guest page.
1156	* @param pPage Pointer to the physical guest page tracking structure.
1157	* @param u16TrackingData The tracking data to store.
1158	*/
1159	#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1160	do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1161
1162	/** @def PGM_PAGE_GET_TD_CREFS
1163	* Gets the @a cRefs tracking data member.
1164	* @returns cRefs.
1165	* @param pPage Pointer to the physical guest page tracking structure.
1166	*/
1167	#define PGM_PAGE_GET_TD_CREFS(pPage) \
1168	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1169
1170	/** @def PGM_PAGE_GET_TD_IDX
1171	* Gets the @a idx tracking data member.
1172	* @returns idx.
1173	* @param pPage Pointer to the physical guest page tracking structure.
1174	*/
1175	#define PGM_PAGE_GET_TD_IDX(pPage) \
1176	((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1177
1178
1179	/** Max number of locks on a page. */
1180	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1181
1182	/** Get the read lock count.
1183	* @returns count.
1184	* @param pPage Pointer to the physical guest page tracking structure.
1185	*/
1186	#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1187
1188	/** Get the write lock count.
1189	* @returns count.
1190	* @param pPage Pointer to the physical guest page tracking structure.
1191	*/
1192	#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1193
1194	/** Decrement the read lock counter.
1195	* @param pPage Pointer to the physical guest page tracking structure.
1196	*/
1197	#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1198
1199	/** Decrement the write lock counter.
1200	* @param pPage Pointer to the physical guest page tracking structure.
1201	*/
1202	#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1203
1204	/** Increment the read lock counter.
1205	* @param pPage Pointer to the physical guest page tracking structure.
1206	*/
1207	#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1208
1209	/** Increment the write lock counter.
1210	* @param pPage Pointer to the physical guest page tracking structure.
1211	*/
1212	#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1213
1214
1215	#if 0
1216	/** Enables sanity checking of write monitoring using CRC-32. */
1217	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1218	#endif
1219
1220	/**
1221	* Per page live save tracking data.
1222	*/
1223	typedef struct PGMLIVESAVERAMPAGE
1224	{
1225	/** Number of times it has been dirtied. */
1226	uint32_t cDirtied : 24;
1227	/** Whether it is currently dirty. */
1228	uint32_t fDirty : 1;
1229	/** Ignore the page.
1230	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1231	* deal with these after pausing the VM and DevPCI have said it bit about
1232	* remappings. */
1233	uint32_t fIgnore : 1;
1234	/** Was a ZERO page last time around. */
1235	uint32_t fZero : 1;
1236	/** Was a SHARED page last time around. */
1237	uint32_t fShared : 1;
1238	/** Whether the page is/was write monitored in a previous pass. */
1239	uint32_t fWriteMonitored : 1;
1240	/** Whether the page is/was write monitored earlier in this pass. */
1241	uint32_t fWriteMonitoredJustNow : 1;
1242	/** Bits reserved for future use. */
1243	uint32_t u2Reserved : 2;
1244	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1245	/** CRC-32 for the page. This is for internal consistency checks. */
1246	uint32_t u32Crc;
1247	#endif
1248	} PGMLIVESAVERAMPAGE;
1249	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1250	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1251	#else
1252	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1253	#endif
1254	/** Pointer to the per page live save tracking data. */
1255	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1256
1257	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1258	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1259
1260
1261	/**
1262	* Ram range for GC Phys to HC Phys conversion.
1263	*
1264	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1265	* conversions too, but we'll let MM handle that for now.
1266	*
1267	* This structure is used by linked lists in both GC and HC.
1268	*/
1269	typedef struct PGMRAMRANGE
1270	{
1271	/** Start of the range. Page aligned. */
1272	RTGCPHYS GCPhys;
1273	/** Size of the range. (Page aligned of course). */
1274	RTGCPHYS cb;
1275	/** Pointer to the next RAM range - for R3. */
1276	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1277	/** Pointer to the next RAM range - for R0. */
1278	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1279	/** Pointer to the next RAM range - for RC. */
1280	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1281	/** PGM_RAM_RANGE_FLAGS_* flags. */
1282	uint32_t fFlags;
1283	/** Last address in the range (inclusive). Page aligned (-1). */
1284	RTGCPHYS GCPhysLast;
1285	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1286	R3PTRTYPE(void *) pvR3;
1287	/** Live save per page tracking data. */
1288	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1289	/** The range description. */
1290	R3PTRTYPE(const char *) pszDesc;
1291	/** Pointer to self - R0 pointer. */
1292	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1293	/** Pointer to self - RC pointer. */
1294	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1295	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1296	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1297	/** Array of physical guest page tracking structures. */
1298	PGMPAGE aPages[1];
1299	} PGMRAMRANGE;
1300	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1301	typedef PGMRAMRANGE *PPGMRAMRANGE;
1302
1303	/** @name PGMRAMRANGE::fFlags
1304	* @{ */
1305	/** The RAM range is floating around as an independent guest mapping. */
1306	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1307	/** Ad hoc RAM range for an ROM mapping. */
1308	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1309	/** Ad hoc RAM range for an MMIO mapping. */
1310	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1311	/** Ad hoc RAM range for an MMIO2 mapping. */
1312	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1313	/** @} */
1314
1315	/** Tests if a RAM range is an ad hoc one or not.
1316	* @returns true/false.
1317	* @param pRam The RAM range.
1318	*/
1319	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1320	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1321
1322
1323	/**
1324	* Per page tracking structure for ROM image.
1325	*
1326	* A ROM image may have a shadow page, in which case we may have two pages
1327	* backing it. This structure contains the PGMPAGE for both while
1328	* PGMRAMRANGE have a copy of the active one. It is important that these
1329	* aren't out of sync in any regard other than page pool tracking data.
1330	*/
1331	typedef struct PGMROMPAGE
1332	{
1333	/** The page structure for the virgin ROM page. */
1334	PGMPAGE Virgin;
1335	/** The page structure for the shadow RAM page. */
1336	PGMPAGE Shadow;
1337	/** The current protection setting. */
1338	PGMROMPROT enmProt;
1339	/** Live save status information. Makes use of unused alignment space. */
1340	struct
1341	{
1342	/** The previous protection value. */
1343	uint8_t u8Prot;
1344	/** Written to flag set by the handler. */
1345	bool fWrittenTo;
1346	/** Whether the shadow page is dirty or not. */
1347	bool fDirty;
1348	/** Whether it was dirtied in the recently. */
1349	bool fDirtiedRecently;
1350	} LiveSave;
1351	} PGMROMPAGE;
1352	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1353	/** Pointer to a ROM page tracking structure. */
1354	typedef PGMROMPAGE *PPGMROMPAGE;
1355
1356
1357	/**
1358	* A registered ROM image.
1359	*
1360	* This is needed to keep track of ROM image since they generally intrude
1361	* into a PGMRAMRANGE. It also keeps track of additional info like the
1362	* two page sets (read-only virgin and read-write shadow), the current
1363	* state of each page.
1364	*
1365	* Because access handlers cannot easily be executed in a different
1366	* context, the ROM ranges needs to be accessible and in all contexts.
1367	*/
1368	typedef struct PGMROMRANGE
1369	{
1370	/** Pointer to the next range - R3. */
1371	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1372	/** Pointer to the next range - R0. */
1373	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1374	/** Pointer to the next range - RC. */
1375	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1376	/** Pointer alignment */
1377	RTRCPTR RCPtrAlignment;
1378	/** Address of the range. */
1379	RTGCPHYS GCPhys;
1380	/** Address of the last byte in the range. */
1381	RTGCPHYS GCPhysLast;
1382	/** Size of the range. */
1383	RTGCPHYS cb;
1384	/** The flags (PGMPHYS_ROM_FLAGS_). /
1385	uint32_t fFlags;
1386	/** The saved state range ID. */
1387	uint8_t idSavedState;
1388	/** Alignment padding. */
1389	uint8_t au8Alignment[3];
1390	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1391	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1392	/** The size bits pvOriginal points to. */
1393	uint32_t cbOriginal;
1394	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1395	* This is used for strictness checks. */
1396	R3PTRTYPE(const void *) pvOriginal;
1397	/** The ROM description. */
1398	R3PTRTYPE(const char *) pszDesc;
1399	/** The per page tracking structures. */
1400	PGMROMPAGE aPages[1];
1401	} PGMROMRANGE;
1402	/** Pointer to a ROM range. */
1403	typedef PGMROMRANGE *PPGMROMRANGE;
1404
1405
1406	/**
1407	* Live save per page data for an MMIO2 page.
1408	*
1409	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1410	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1411	* CRC-32 for detecting changes as well as special handling of zero pages. This
1412	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1413	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1414	* because of speed (2.5x and 6x slower).)
1415	*
1416	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1417	* save but normally is disabled. Since we can write monitor guest
1418	* accesses on our own, we only need this for host accesses. Shouldn't be
1419	* too difficult for DevVGA, VMMDev might be doable, the planned
1420	* networking fun will be fun since it involves ring-0.
1421	*/
1422	typedef struct PGMLIVESAVEMMIO2PAGE
1423	{
1424	/** Set if the page is considered dirty. */
1425	bool fDirty;
1426	/** The number of scans this page has remained unchanged for.
1427	* Only updated for dirty pages. */
1428	uint8_t cUnchangedScans;
1429	/** Whether this page was zero at the last scan. */
1430	bool fZero;
1431	/** Alignment padding. */
1432	bool fReserved;
1433	/** CRC-32 for the first half of the page.
1434	* This is used together with u32CrcH2 to quickly detect changes in the page
1435	* during the non-final passes. */
1436	uint32_t u32CrcH1;
1437	/** CRC-32 for the second half of the page. */
1438	uint32_t u32CrcH2;
1439	/** SHA-1 for the saved page.
1440	* This is used in the final pass to skip pages without changes. */
1441	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1442	} PGMLIVESAVEMMIO2PAGE;
1443	/** Pointer to a live save status data for an MMIO2 page. */
1444	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1445
1446	/**
1447	* A registered MMIO2 (= Device RAM) range.
1448	*
1449	* There are a few reason why we need to keep track of these
1450	* registrations. One of them is the deregistration & cleanup stuff,
1451	* while another is that the PGMRAMRANGE associated with such a region may
1452	* have to be removed from the ram range list.
1453	*
1454	* Overlapping with a RAM range has to be 100% or none at all. The pages
1455	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1456	* will be raised if a partial overlap or an overlap of ROM pages is
1457	* encountered. On an overlap we will free all the existing RAM pages and
1458	* put in the ram range pages instead.
1459	*/
1460	typedef struct PGMMMIO2RANGE
1461	{
1462	/** The owner of the range. (a device) */
1463	PPDMDEVINSR3 pDevInsR3;
1464	/** Pointer to the ring-3 mapping of the allocation. */
1465	RTR3PTR pvR3;
1466	/** Pointer to the next range - R3. */
1467	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1468	/** Whether it's mapped or not. */
1469	bool fMapped;
1470	/** Whether it's overlapping or not. */
1471	bool fOverlapping;
1472	/** The PCI region number.
1473	* @remarks This ASSUMES that nobody will ever really need to have multiple
1474	* PCI devices with matching MMIO region numbers on a single device. */
1475	uint8_t iRegion;
1476	/** The saved state range ID. */
1477	uint8_t idSavedState;
1478	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1479	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1480	/** Live save per page tracking data. */
1481	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1482	/** The associated RAM range. */
1483	PGMRAMRANGE RamRange;
1484	} PGMMMIO2RANGE;
1485	/** Pointer to a MMIO2 range. */
1486	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1487
1488
1489
1490
1491	/**
1492	* PGMPhysRead/Write cache entry
1493	*/
1494	typedef struct PGMPHYSCACHEENTRY
1495	{
1496	/** R3 pointer to physical page. */
1497	R3PTRTYPE(uint8_t *) pbR3;
1498	/** GC Physical address for cache entry */
1499	RTGCPHYS GCPhys;
1500	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1501	RTGCPHYS u32Padding0; /*< alignment padding. /
1502	#endif
1503	} PGMPHYSCACHEENTRY;
1504
1505	/**
1506	* PGMPhysRead/Write cache to reduce REM memory access overhead
1507	*/
1508	typedef struct PGMPHYSCACHE
1509	{
1510	/** Bitmap of valid cache entries */
1511	uint64_t aEntries;
1512	/** Cache entries */
1513	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1514	} PGMPHYSCACHE;
1515
1516
1517	/** Pointer to an allocation chunk ring-3 mapping. */
1518	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1519	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1520	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1521
1522	/**
1523	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1524	*
1525	* The primary tree (Core) uses the chunk id as key.
1526	*/
1527	typedef struct PGMCHUNKR3MAP
1528	{
1529	/** The key is the chunk id. */
1530	AVLU32NODECORE Core;
1531	/** The current age thingy. */
1532	uint32_t iAge;
1533	/** The current reference count. */
1534	uint32_t volatile cRefs;
1535	/** The current permanent reference count. */
1536	uint32_t volatile cPermRefs;
1537	/** The mapping address. */
1538	void *pv;
1539	} PGMCHUNKR3MAP;
1540
1541	/**
1542	* Allocation chunk ring-3 mapping TLB entry.
1543	*/
1544	typedef struct PGMCHUNKR3MAPTLBE
1545	{
1546	/** The chunk id. */
1547	uint32_t volatile idChunk;
1548	#if HC_ARCH_BITS == 64
1549	uint32_t u32Padding; /*< alignment padding. /
1550	#endif
1551	/** The chunk map. */
1552	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1553	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1554	#else
1555	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1556	#endif
1557	} PGMCHUNKR3MAPTLBE;
1558	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1559	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1560
1561	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1562	* @remark Must be a power of two value. */
1563	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1564
1565	/**
1566	* Allocation chunk ring-3 mapping TLB.
1567	*
1568	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1569	* At first glance this might look kinda odd since AVL trees are
1570	* supposed to give the most optimal lookup times of all trees
1571	* due to their balancing. However, take a tree with 1023 nodes
1572	* in it, that's 10 levels, meaning that most searches has to go
1573	* down 9 levels before they find what they want. This isn't fast
1574	* compared to a TLB hit. There is the factor of cache misses,
1575	* and of course the problem with trees and branch prediction.
1576	* This is why we use TLBs in front of most of the trees.
1577	*
1578	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1579	* difficult when we switch to the new inlined AVL trees (from kStuff).
1580	*/
1581	typedef struct PGMCHUNKR3MAPTLB
1582	{
1583	/** The TLB entries. */
1584	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1585	} PGMCHUNKR3MAPTLB;
1586
1587	/**
1588	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1589	* @returns Chunk TLB index.
1590	* @param idChunk The Chunk ID.
1591	*/
1592	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1593
1594
1595	/**
1596	* Ring-3 guest page mapping TLB entry.
1597	* @remarks used in ring-0 as well at the moment.
1598	*/
1599	typedef struct PGMPAGER3MAPTLBE
1600	{
1601	/** Address of the page. */
1602	RTGCPHYS volatile GCPhys;
1603	/** The guest page. */
1604	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1605	R3PTRTYPE(PPGMPAGE) volatile pPage;
1606	#else
1607	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1608	#endif
1609	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1610	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1611	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1612	#else
1613	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1614	#endif
1615	/** The address */
1616	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1617	R3PTRTYPE(void *) volatile pv;
1618	#else
1619	R3R0PTRTYPE(void *) volatile pv;
1620	#endif
1621	#if HC_ARCH_BITS == 32
1622	uint32_t u32Padding; /*< alignment padding. /
1623	#endif
1624	} PGMPAGER3MAPTLBE;
1625	/** Pointer to an entry in the HC physical TLB. */
1626	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1627
1628
1629	/** The number of entries in the ring-3 guest page mapping TLB.
1630	* @remarks The value must be a power of two. */
1631	#define PGM_PAGER3MAPTLB_ENTRIES 256
1632
1633	/**
1634	* Ring-3 guest page mapping TLB.
1635	* @remarks used in ring-0 as well at the moment.
1636	*/
1637	typedef struct PGMPAGER3MAPTLB
1638	{
1639	/** The TLB entries. */
1640	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1641	} PGMPAGER3MAPTLB;
1642	/** Pointer to the ring-3 guest page mapping TLB. */
1643	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1644
1645	/**
1646	* Calculates the index of the TLB entry for the specified guest page.
1647	* @returns Physical TLB index.
1648	* @param GCPhys The guest physical address.
1649	*/
1650	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1651
1652
1653	/**
1654	* Raw-mode context dynamic mapping cache entry.
1655	*
1656	* Because of raw-mode context being reloctable and all relocations are applied
1657	* in ring-3, this has to be defined here and be RC specific.
1658	*
1659	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1660	*/
1661	typedef struct PGMRCDYNMAPENTRY
1662	{
1663	/** The physical address of the currently mapped page.
1664	* This is duplicate for three reasons: cache locality, cache policy of the PT
1665	* mappings and sanity checks. */
1666	RTHCPHYS HCPhys;
1667	/** Pointer to the page. */
1668	RTRCPTR pvPage;
1669	/** The number of references. */
1670	int32_t volatile cRefs;
1671	/** PTE pointer union. */
1672	union PGMRCDYNMAPENTRY_PPTE
1673	{
1674	/** PTE pointer, 32-bit legacy version. */
1675	RCPTRTYPE(PX86PTE) pLegacy;
1676	/** PTE pointer, PAE version. */
1677	RCPTRTYPE(PX86PTEPAE) pPae;
1678	/** PTE pointer, the void version. */
1679	RTRCPTR pv;
1680	} uPte;
1681	/** Alignment padding. */
1682	RTRCPTR RCPtrAlignment;
1683	} PGMRCDYNMAPENTRY;
1684	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1685	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1686
1687
1688	/**
1689	* Dynamic mapping cache for the raw-mode context.
1690	*
1691	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1692	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1693	* so that we can perform relocations from PGMR3Relocate. This has the
1694	* consequence that we must have separate ring-0 and raw-mode context versions
1695	* of this struct even if they share the basic elements.
1696	*
1697	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1698	*/
1699	typedef struct PGMRCDYNMAP
1700	{
1701	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1702	uint32_t u32Magic;
1703	/** Array for tracking and managing the pages. */
1704	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1705	/** The cache size given as a number of pages. */
1706	uint32_t cPages;
1707	/** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
1708	bool fLegacyMode;
1709	/** The current load.
1710	* This does not include guard pages. */
1711	uint32_t cLoad;
1712	/** The max load ever.
1713	* This is maintained to get trigger adding of more mapping space. */
1714	uint32_t cMaxLoad;
1715	/** The number of guard pages. */
1716	uint32_t cGuardPages;
1717	/** The number of users (protected by hInitLock). */
1718	uint32_t cUsers;
1719	} PGMRCDYNMAP;
1720	/** Pointer to the dynamic cache for the raw-mode context. */
1721	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1722
1723
1724	/**
1725	* Mapping cache usage set entry.
1726	*
1727	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1728	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1729	* cache. If it's extended to include ring-3, well, then something
1730	* will have be changed here...
1731	*/
1732	typedef struct PGMMAPSETENTRY
1733	{
1734	/** Pointer to the page. */
1735	#ifndef IN_RC
1736	RTR0PTR pvPage;
1737	#else
1738	RTRCPTR pvPage;
1739	# if HC_ARCH_BITS == 64
1740	uint32_t u32Alignment2;
1741	# endif
1742	#endif
1743	/** The mapping cache index. */
1744	uint16_t iPage;
1745	/** The number of references.
1746	* The max is UINT16_MAX - 1. */
1747	uint16_t cRefs;
1748	/** The number inlined references.
1749	* The max is UINT16_MAX - 1. */
1750	uint16_t cInlinedRefs;
1751	/** Unreferences. */
1752	uint16_t cUnrefs;
1753
1754	#if HC_ARCH_BITS == 32
1755	uint32_t u32Alignment1;
1756	#endif
1757	/** The physical address for this entry. */
1758	RTHCPHYS HCPhys;
1759	} PGMMAPSETENTRY;
1760	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1761	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1762	/** Pointer to a mapping cache usage set entry. */
1763	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1764
1765	/**
1766	* Mapping cache usage set.
1767	*
1768	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1769	* done during exits / traps. The set is
1770	*/
1771	typedef struct PGMMAPSET
1772	{
1773	/** The number of occupied entries.
1774	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1775	* dynamic mappings. */
1776	uint32_t cEntries;
1777	/** The start of the current subset.
1778	* This is UINT32_MAX if no subset is currently open. */
1779	uint32_t iSubset;
1780	/** The index of the current CPU, only valid if the set is open. */
1781	int32_t iCpu;
1782	uint32_t alignment;
1783	/** The entries. */
1784	PGMMAPSETENTRY aEntries[64];
1785	/** HCPhys -> iEntry fast lookup table.
1786	* Use PGMMAPSET_HASH for hashing.
1787	* The entries may or may not be valid, check against cEntries. */
1788	uint8_t aiHashTable[128];
1789	} PGMMAPSET;
1790	AssertCompileSizeAlignment(PGMMAPSET, 8);
1791	/** Pointer to the mapping cache set. */
1792	typedef PGMMAPSET *PPGMMAPSET;
1793
1794	/** PGMMAPSET::cEntries value for a closed set. */
1795	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1796
1797	/** Hash function for aiHashTable. */
1798	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1799
1800
1801	/** @name Context neutral page mapper TLB.
1802	*
1803	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1804	* code is writting in a kind of context neutral way. Time will show whether
1805	* this actually makes sense or not...
1806	*
1807	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1808	* context ends up using a global mapping cache on some platforms
1809	* (darwin).
1810	*
1811	* @{ */
1812	/** @typedef PPGMPAGEMAPTLB
1813	* The page mapper TLB pointer type for the current context. */
1814	/** @typedef PPGMPAGEMAPTLB
1815	* The page mapper TLB entry pointer type for the current context. */
1816	/** @typedef PPGMPAGEMAPTLB
1817	* The page mapper TLB entry pointer pointer type for the current context. */
1818	/** @def PGM_PAGEMAPTLB_ENTRIES
1819	* The number of TLB entries in the page mapper TLB for the current context. */
1820	/** @def PGM_PAGEMAPTLB_IDX
1821	* Calculate the TLB index for a guest physical address.
1822	* @returns The TLB index.
1823	* @param GCPhys The guest physical address. */
1824	/** @typedef PPGMPAGEMAP
1825	* Pointer to a page mapper unit for current context. */
1826	/** @typedef PPPGMPAGEMAP
1827	* Pointer to a page mapper unit pointer for current context. */
1828	#ifdef IN_RC
1829	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1830	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1831	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1832	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1833	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1834	typedef void * PPGMPAGEMAP;
1835	typedef void ** PPPGMPAGEMAP;
1836	//#elif IN_RING0
1837	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1838	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1839	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1840	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1841	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1842	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1843	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1844	#else
1845	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1846	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1847	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1848	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1849	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1850	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1851	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1852	#endif
1853	/** @} */
1854
1855
1856	/** @name PGM Pool Indexes.
1857	* Aka. the unique shadow page identifier.
1858	* @{ */
1859	/** NIL page pool IDX. */
1860	#define NIL_PGMPOOL_IDX 0
1861	/** The first normal index. */
1862	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1863	/** Page directory (32-bit root). */
1864	#define PGMPOOL_IDX_PD 1
1865	/** Page Directory Pointer Table (PAE root). */
1866	#define PGMPOOL_IDX_PDPT 2
1867	/** AMD64 CR3 level index.*/
1868	#define PGMPOOL_IDX_AMD64_CR3 3
1869	/** Nested paging root.*/
1870	#define PGMPOOL_IDX_NESTED_ROOT 4
1871	/** The first normal index. */
1872	#define PGMPOOL_IDX_FIRST 5
1873	/** The last valid index. (inclusive, 14 bits) */
1874	#define PGMPOOL_IDX_LAST 0x3fff
1875	/** @} */
1876
1877	/** The NIL index for the parent chain. */
1878	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1879	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1880
1881	/**
1882	* Node in the chain linking a shadowed page to it's parent (user).
1883	*/
1884	#pragma pack(1)
1885	typedef struct PGMPOOLUSER
1886	{
1887	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1888	uint16_t iNext;
1889	/** The user page index. */
1890	uint16_t iUser;
1891	/** Index into the user table. */
1892	uint32_t iUserTable;
1893	} PGMPOOLUSER, *PPGMPOOLUSER;
1894	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1895	#pragma pack()
1896
1897
1898	/** The NIL index for the phys ext chain. */
1899	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1900	/** The NIL pte index for a phys ext chain slot. */
1901	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1902
1903	/**
1904	* Node in the chain of physical cross reference extents.
1905	* @todo Calling this an 'extent' is not quite right, find a better name.
1906	* @todo find out the optimal size of the aidx array
1907	*/
1908	#pragma pack(1)
1909	typedef struct PGMPOOLPHYSEXT
1910	{
1911	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1912	uint16_t iNext;
1913	/** Alignment. */
1914	uint16_t u16Align;
1915	/** The user page index. */
1916	uint16_t aidx[3];
1917	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1918	uint16_t apte[3];
1919	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1920	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1921	#pragma pack()
1922
1923
1924	/**
1925	* The kind of page that's being shadowed.
1926	*/
1927	typedef enum PGMPOOLKIND
1928	{
1929	/** The virtual invalid 0 entry. */
1930	PGMPOOLKIND_INVALID = 0,
1931	/** The entry is free (=unused). */
1932	PGMPOOLKIND_FREE,
1933
1934	/** Shw: 32-bit page table; Gst: no paging */
1935	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1936	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1937	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1938	/** Shw: 32-bit page table; Gst: 4MB page. */
1939	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1940	/** Shw: PAE page table; Gst: no paging */
1941	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1942	/** Shw: PAE page table; Gst: 32-bit page table. */
1943	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1944	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1945	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1946	/** Shw: PAE page table; Gst: PAE page table. */
1947	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1948	/** Shw: PAE page table; Gst: 2MB page. */
1949	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1950
1951	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1952	PGMPOOLKIND_32BIT_PD,
1953	/** Shw: 32-bit page directory. Gst: no paging. */
1954	PGMPOOLKIND_32BIT_PD_PHYS,
1955	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1956	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1957	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1958	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1959	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1960	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1961	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1962	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1963	/** Shw: PAE page directory; Gst: PAE page directory. */
1964	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1965	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1966	PGMPOOLKIND_PAE_PD_PHYS,
1967
1968	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1969	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1970	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1971	PGMPOOLKIND_PAE_PDPT,
1972	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1973	PGMPOOLKIND_PAE_PDPT_PHYS,
1974
1975	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1976	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1977	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1978	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1979	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1980	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1981	/** Shw: 64-bit page directory table; Gst: no paging */
1982	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1983
1984	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1985	PGMPOOLKIND_64BIT_PML4,
1986
1987	/** Shw: EPT page directory pointer table; Gst: no paging */
1988	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1989	/** Shw: EPT page directory table; Gst: no paging */
1990	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1991	/** Shw: EPT page table; Gst: no paging */
1992	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1993
1994	/** Shw: Root Nested paging table. */
1995	PGMPOOLKIND_ROOT_NESTED,
1996
1997	/** The last valid entry. */
1998	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1999	} PGMPOOLKIND;
2000
2001	/**
2002	* The access attributes of the page; only applies to big pages.
2003	*/
2004	typedef enum
2005	{
2006	PGMPOOLACCESS_DONTCARE = 0,
2007	PGMPOOLACCESS_USER_RW,
2008	PGMPOOLACCESS_USER_R,
2009	PGMPOOLACCESS_USER_RW_NX,
2010	PGMPOOLACCESS_USER_R_NX,
2011	PGMPOOLACCESS_SUPERVISOR_RW,
2012	PGMPOOLACCESS_SUPERVISOR_R,
2013	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2014	PGMPOOLACCESS_SUPERVISOR_R_NX
2015	} PGMPOOLACCESS;
2016
2017	/**
2018	* The tracking data for a page in the pool.
2019	*/
2020	typedef struct PGMPOOLPAGE
2021	{
2022	/** AVL node code with the (R3) physical address of this page. */
2023	AVLOHCPHYSNODECORE Core;
2024	/** Pointer to the R3 mapping of the page. */
2025	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2026	R3PTRTYPE(void *) pvPageR3;
2027	#else
2028	R3R0PTRTYPE(void *) pvPageR3;
2029	#endif
2030	/** The guest physical address. */
2031	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2032	uint32_t Alignment0;
2033	#endif
2034	RTGCPHYS GCPhys;
2035
2036	/** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2037	RTGCPTR pvLastAccessHandlerRip;
2038	RTGCPTR pvLastAccessHandlerFault;
2039	uint64_t cLastAccessHandlerCount;
2040
2041	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2042	uint8_t enmKind;
2043	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2044	uint8_t enmAccess;
2045	/** The index of this page. */
2046	uint16_t idx;
2047	/** The next entry in the list this page currently resides in.
2048	* It's either in the free list or in the GCPhys hash. */
2049	uint16_t iNext;
2050	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2051	uint16_t iUserHead;
2052	/** The number of present entries. */
2053	uint16_t cPresent;
2054	/** The first entry in the table which is present. */
2055	uint16_t iFirstPresent;
2056	/** The number of modifications to the monitored page. */
2057	uint16_t cModifications;
2058	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2059	uint16_t iModifiedNext;
2060	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2061	uint16_t iModifiedPrev;
2062	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2063	uint16_t iMonitoredNext;
2064	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2065	uint16_t iMonitoredPrev;
2066	/** The next page in the age list. */
2067	uint16_t iAgeNext;
2068	/** The previous page in the age list. */
2069	uint16_t iAgePrev;
2070	/** Used to indicate that the page is zeroed. */
2071	bool fZeroed;
2072	/** Used to indicate that a PT has non-global entries. */
2073	bool fSeenNonGlobal;
2074	/** Used to indicate that we're monitoring writes to the guest page. */
2075	bool fMonitored;
2076	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2077	* (All pages are in the age list.) */
2078	bool fCached;
2079	/** This is used by the R3 access handlers when invoked by an async thread.
2080	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2081	bool volatile fReusedFlushPending;
2082	/** Used to mark the page as dirty (write monitoring is temporarily
2083	* off). */
2084	bool fDirty;
2085
2086	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2087	uint32_t cLocked;
2088	uint32_t idxDirty;
2089	RTGCPTR pvDirtyFault;
2090	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
2091	/** Pointer to a const pool page. */
2092	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2093
2094
2095	/** The hash table size. */
2096	# define PGMPOOL_HASH_SIZE 0x40
2097	/** The hash function. */
2098	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2099
2100
2101	/**
2102	* The shadow page pool instance data.
2103	*
2104	* It's all one big allocation made at init time, except for the
2105	* pages that is. The user nodes follows immediately after the
2106	* page structures.
2107	*/
2108	typedef struct PGMPOOL
2109	{
2110	/** The VM handle - R3 Ptr. */
2111	PVMR3 pVMR3;
2112	/** The VM handle - R0 Ptr. */
2113	PVMR0 pVMR0;
2114	/** The VM handle - RC Ptr. */
2115	PVMRC pVMRC;
2116	/** The max pool size. This includes the special IDs. */
2117	uint16_t cMaxPages;
2118	/** The current pool size. */
2119	uint16_t cCurPages;
2120	/** The head of the free page list. */
2121	uint16_t iFreeHead;
2122	/* Padding. */
2123	uint16_t u16Padding;
2124	/** Head of the chain of free user nodes. */
2125	uint16_t iUserFreeHead;
2126	/** The number of user nodes we've allocated. */
2127	uint16_t cMaxUsers;
2128	/** The number of present page table entries in the entire pool. */
2129	uint32_t cPresent;
2130	/** Pointer to the array of user nodes - RC pointer. */
2131	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2132	/** Pointer to the array of user nodes - R3 pointer. */
2133	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2134	/** Pointer to the array of user nodes - R0 pointer. */
2135	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2136	/** Head of the chain of free phys ext nodes. */
2137	uint16_t iPhysExtFreeHead;
2138	/** The number of user nodes we've allocated. */
2139	uint16_t cMaxPhysExts;
2140	/** Pointer to the array of physical xref extent - RC pointer. */
2141	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2142	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2143	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2144	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2145	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2146	/** Hash table for GCPhys addresses. */
2147	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2148	/** The head of the age list. */
2149	uint16_t iAgeHead;
2150	/** The tail of the age list. */
2151	uint16_t iAgeTail;
2152	/** Set if the cache is enabled. */
2153	bool fCacheEnabled;
2154	/** Alignment padding. */
2155	bool afPadding1[3];
2156	/** Head of the list of modified pages. */
2157	uint16_t iModifiedHead;
2158	/** The current number of modified pages. */
2159	uint16_t cModifiedPages;
2160	/** Access handler, RC. */
2161	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2162	/** Access handler, R0. */
2163	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2164	/** Access handler, R3. */
2165	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2166	/** The access handler description (R3 ptr). */
2167	R3PTRTYPE(const char *) pszAccessHandler;
2168	# if HC_ARCH_BITS == 32
2169	/** Alignment padding. */
2170	uint32_t u32Padding2;
2171	# endif
2172	/* Next available slot. */
2173	uint32_t idxFreeDirtyPage;
2174	/* Number of active dirty pages. */
2175	uint32_t cDirtyPages;
2176	/* Array of current dirty pgm pool page indices. */
2177	struct
2178	{
2179	uint16_t uIdx;
2180	uint16_t Alignment[3];
2181	uint64_t aPage[512];
2182	} aDirtyPages[16];
2183	/** The number of pages currently in use. */
2184	uint16_t cUsedPages;
2185	#ifdef VBOX_WITH_STATISTICS
2186	/** The high water mark for cUsedPages. */
2187	uint16_t cUsedPagesHigh;
2188	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2189	/** Profiling pgmPoolAlloc(). */
2190	STAMPROFILEADV StatAlloc;
2191	/** Profiling pgmR3PoolClearDoIt(). */
2192	STAMPROFILE StatClearAll;
2193	/** Profiling pgmR3PoolReset(). */
2194	STAMPROFILE StatR3Reset;
2195	/** Profiling pgmPoolFlushPage(). */
2196	STAMPROFILE StatFlushPage;
2197	/** Profiling pgmPoolFree(). */
2198	STAMPROFILE StatFree;
2199	/** Counting explicit flushes by PGMPoolFlushPage(). */
2200	STAMCOUNTER StatForceFlushPage;
2201	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2202	STAMCOUNTER StatForceFlushDirtyPage;
2203	/** Counting flushes for reused pages. */
2204	STAMCOUNTER StatForceFlushReused;
2205	/** Profiling time spent zeroing pages. */
2206	STAMPROFILE StatZeroPage;
2207	/** Profiling of pgmPoolTrackDeref. */
2208	STAMPROFILE StatTrackDeref;
2209	/** Profiling pgmTrackFlushGCPhysPT. */
2210	STAMPROFILE StatTrackFlushGCPhysPT;
2211	/** Profiling pgmTrackFlushGCPhysPTs. */
2212	STAMPROFILE StatTrackFlushGCPhysPTs;
2213	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2214	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2215	/** Number of times we've been out of user records. */
2216	STAMCOUNTER StatTrackFreeUpOneUser;
2217	/** Nr of flushed entries. */
2218	STAMCOUNTER StatTrackFlushEntry;
2219	/** Nr of updated entries. */
2220	STAMCOUNTER StatTrackFlushEntryKeep;
2221	/** Profiling deref activity related tracking GC physical pages. */
2222	STAMPROFILE StatTrackDerefGCPhys;
2223	/** Number of linear searches for a HCPhys in the ram ranges. */
2224	STAMCOUNTER StatTrackLinearRamSearches;
2225	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2226	STAMCOUNTER StamTrackPhysExtAllocFailures;
2227	/** Profiling the RC/R0 access handler. */
2228	STAMPROFILE StatMonitorRZ;
2229	/** Times we've failed interpreting the instruction. */
2230	STAMCOUNTER StatMonitorRZEmulateInstr;
2231	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2232	STAMPROFILE StatMonitorRZFlushPage;
2233	/* Times we've detected a page table reinit. */
2234	STAMCOUNTER StatMonitorRZFlushReinit;
2235	/** Counting flushes for pages that are modified too often. */
2236	STAMCOUNTER StatMonitorRZFlushModOverflow;
2237	/** Times we've detected fork(). */
2238	STAMCOUNTER StatMonitorRZFork;
2239	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2240	STAMPROFILE StatMonitorRZHandled;
2241	/** Times we've failed interpreting a patch code instruction. */
2242	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2243	/** Times we've failed interpreting a patch code instruction during flushing. */
2244	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2245	/** The number of times we've seen rep prefixes we can't handle. */
2246	STAMCOUNTER StatMonitorRZRepPrefix;
2247	/** Profiling the REP STOSD cases we've handled. */
2248	STAMPROFILE StatMonitorRZRepStosd;
2249	/** Nr of handled PT faults. */
2250	STAMCOUNTER StatMonitorRZFaultPT;
2251	/** Nr of handled PD faults. */
2252	STAMCOUNTER StatMonitorRZFaultPD;
2253	/** Nr of handled PDPT faults. */
2254	STAMCOUNTER StatMonitorRZFaultPDPT;
2255	/** Nr of handled PML4 faults. */
2256	STAMCOUNTER StatMonitorRZFaultPML4;
2257
2258	/** Profiling the R3 access handler. */
2259	STAMPROFILE StatMonitorR3;
2260	/** Times we've failed interpreting the instruction. */
2261	STAMCOUNTER StatMonitorR3EmulateInstr;
2262	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2263	STAMPROFILE StatMonitorR3FlushPage;
2264	/* Times we've detected a page table reinit. */
2265	STAMCOUNTER StatMonitorR3FlushReinit;
2266	/** Counting flushes for pages that are modified too often. */
2267	STAMCOUNTER StatMonitorR3FlushModOverflow;
2268	/** Times we've detected fork(). */
2269	STAMCOUNTER StatMonitorR3Fork;
2270	/** Profiling the R3 access we've handled (except REP STOSD). */
2271	STAMPROFILE StatMonitorR3Handled;
2272	/** The number of times we've seen rep prefixes we can't handle. */
2273	STAMCOUNTER StatMonitorR3RepPrefix;
2274	/** Profiling the REP STOSD cases we've handled. */
2275	STAMPROFILE StatMonitorR3RepStosd;
2276	/** Nr of handled PT faults. */
2277	STAMCOUNTER StatMonitorR3FaultPT;
2278	/** Nr of handled PD faults. */
2279	STAMCOUNTER StatMonitorR3FaultPD;
2280	/** Nr of handled PDPT faults. */
2281	STAMCOUNTER StatMonitorR3FaultPDPT;
2282	/** Nr of handled PML4 faults. */
2283	STAMCOUNTER StatMonitorR3FaultPML4;
2284	/** The number of times we're called in an async thread an need to flush. */
2285	STAMCOUNTER StatMonitorR3Async;
2286	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2287	STAMCOUNTER StatResetDirtyPages;
2288	/** Times we've called pgmPoolAddDirtyPage. */
2289	STAMCOUNTER StatDirtyPage;
2290	/** Times we've had to flush duplicates for dirty page management. */
2291	STAMCOUNTER StatDirtyPageDupFlush;
2292	/** Times we've had to flush because of overflow. */
2293	STAMCOUNTER StatDirtyPageOverFlowFlush;
2294
2295	/** The high water mark for cModifiedPages. */
2296	uint16_t cModifiedPagesHigh;
2297	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2298
2299	/** The number of cache hits. */
2300	STAMCOUNTER StatCacheHits;
2301	/** The number of cache misses. */
2302	STAMCOUNTER StatCacheMisses;
2303	/** The number of times we've got a conflict of 'kind' in the cache. */
2304	STAMCOUNTER StatCacheKindMismatches;
2305	/** Number of times we've been out of pages. */
2306	STAMCOUNTER StatCacheFreeUpOne;
2307	/** The number of cacheable allocations. */
2308	STAMCOUNTER StatCacheCacheable;
2309	/** The number of uncacheable allocations. */
2310	STAMCOUNTER StatCacheUncacheable;
2311	#else
2312	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2313	#endif
2314	/** The AVL tree for looking up a page by its HC physical address. */
2315	AVLOHCPHYSTREE HCPhysTree;
2316	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2317	/** Array of pages. (cMaxPages in length)
2318	* The Id is the index into thist array.
2319	*/
2320	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2321	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2322	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2323	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2324	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2325	#ifdef VBOX_WITH_STATISTICS
2326	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2327	#endif
2328	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2329
2330
2331	/** @def PGMPOOL_PAGE_2_PTR
2332	* Maps a pool page pool into the current context.
2333	*
2334	* @returns VBox status code.
2335	* @param pVM The VM handle.
2336	* @param pPage The pool page.
2337	*
2338	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2339	* small page window employeed by that function. Be careful.
2340	* @remark There is no need to assert on the result.
2341	*/
2342	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2343	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2344	#elif defined(VBOX_STRICT)
2345	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2346	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2347	{
2348	Assert(pPage && pPage->pvPageR3);
2349	return pPage->pvPageR3;
2350	}
2351	#else
2352	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2353	#endif
2354
2355
2356	/** @def PGMPOOL_PAGE_2_PTR_V2
2357	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2358	*
2359	* @returns VBox status code.
2360	* @param pVM The VM handle.
2361	* @param pVCpu The current CPU.
2362	* @param pPage The pool page.
2363	*
2364	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2365	* small page window employeed by that function. Be careful.
2366	* @remark There is no need to assert on the result.
2367	*/
2368	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2369	# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2370	#else
2371	# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2372	#endif
2373
2374
2375	/** @name Per guest page tracking data.
2376	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2377	* is to use more bits for it and split it up later on. But for now we'll play
2378	* safe and change as little as possible.
2379	*
2380	* The 16-bit word has two parts:
2381	*
2382	* The first 14-bit forms the @a idx field. It is either the index of a page in
2383	* the shadow page pool, or and index into the extent list.
2384	*
2385	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2386	* shadow page pool references to the page. If cRefs equals
2387	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2388	* (misnomer) table and not the shadow page pool.
2389	*
2390	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2391	* the 16-bit word.
2392	*
2393	* @{ */
2394	/** The shift count for getting to the cRefs part. */
2395	#define PGMPOOL_TD_CREFS_SHIFT 14
2396	/** The mask applied after shifting the tracking data down by
2397	* PGMPOOL_TD_CREFS_SHIFT. */
2398	#define PGMPOOL_TD_CREFS_MASK 0x3
2399	/** The cRefs value used to indicate that the idx is the head of a
2400	* physical cross reference list. */
2401	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2402	/** The shift used to get idx. */
2403	#define PGMPOOL_TD_IDX_SHIFT 0
2404	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2405	#define PGMPOOL_TD_IDX_MASK 0x3fff
2406	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2407	* simply too many mappings of this page. */
2408	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2409
2410	/** @def PGMPOOL_TD_MAKE
2411	* Makes a 16-bit tracking data word.
2412	*
2413	* @returns tracking data.
2414	* @param cRefs The @a cRefs field. Must be within bounds!
2415	* @param idx The @a idx field. Must also be within bounds! */
2416	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2417
2418	/** @def PGMPOOL_TD_GET_CREFS
2419	* Get the @a cRefs field from a tracking data word.
2420	*
2421	* @returns The @a cRefs field
2422	* @param u16 The tracking data word.
2423	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2424	* non-zero @a u16. */
2425	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2426
2427	/** @def PGMPOOL_TD_GET_IDX
2428	* Get the @a idx field from a tracking data word.
2429	*
2430	* @returns The @a idx field
2431	* @param u16 The tracking data word. */
2432	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2433	/** @} */
2434
2435
2436	/**
2437	* Trees are using self relative offsets as pointers.
2438	* So, all its data, including the root pointer, must be in the heap for HC and GC
2439	* to have the same layout.
2440	*/
2441	typedef struct PGMTREES
2442	{
2443	/** Physical access handlers (AVL range+offsetptr tree). */
2444	AVLROGCPHYSTREE PhysHandlers;
2445	/** Virtual access handlers (AVL range + GC ptr tree). */
2446	AVLROGCPTRTREE VirtHandlers;
2447	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2448	AVLROGCPHYSTREE PhysToVirtHandlers;
2449	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2450	AVLROGCPTRTREE HyperVirtHandlers;
2451	} PGMTREES;
2452	/** Pointer to PGM trees. */
2453	typedef PGMTREES *PPGMTREES;
2454
2455
2456	/**
2457	* Page fault guest state for the AMD64 paging mode.
2458	*/
2459	typedef struct PGMPTWALKCORE
2460	{
2461	/** The guest virtual address that is being resolved by the walk
2462	* (input). */
2463	RTGCPTR GCPtr;
2464
2465	/** The guest physical address that is the result of the walk.
2466	* @remarks only valid if fSucceeded is set. */
2467	RTGCPHYS GCPhys;
2468
2469	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2470	bool fSucceeded;
2471	/** The level problem arrised at.
2472	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2473	* level 8. This is 0 on success. */
2474	uint8_t uLevel;
2475	/** Set if the page isn't present. */
2476	bool fNotPresent;
2477	/** Encountered a bad physical address. */
2478	bool fBadPhysAddr;
2479	/** Set if there was reserved bit violations. */
2480	bool fRsvdError;
2481	/** Set if it involves a big page (2/4 MB). */
2482	bool fBigPage;
2483	/** Set if it involves a gigantic page (1 GB). */
2484	bool fGigantPage;
2485	/** The effect X86_PTE_US flag for the address. */
2486	bool fEffectiveUS;
2487	/** The effect X86_PTE_RW flag for the address. */
2488	bool fEffectiveRW;
2489	/** The effect X86_PTE_NX flag for the address. */
2490	bool fEffectiveNX;
2491	} PGMPTWALKCORE;
2492
2493
2494	/**
2495	* Guest page table walk for the AMD64 mode.
2496	*/
2497	typedef struct PGMPTWALKGSTAMD64
2498	{
2499	/** The common core. */
2500	PGMPTWALKCORE Core;
2501
2502	PX86PML4 pPml4;
2503	PX86PML4E pPml4e;
2504	X86PML4E Pml4e;
2505
2506	PX86PDPT pPdpt;
2507	PX86PDPE pPdpe;
2508	X86PDPE Pdpe;
2509
2510	PX86PDPAE pPd;
2511	PX86PDEPAE pPde;
2512	X86PDEPAE Pde;
2513
2514	PX86PTPAE pPt;
2515	PX86PTEPAE pPte;
2516	X86PTEPAE Pte;
2517	} PGMPTWALKGSTAMD64;
2518	/** Pointer to a AMD64 guest page table walk. */
2519	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2520	/** Pointer to a const AMD64 guest page table walk. */
2521	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2522
2523	/**
2524	* Guest page table walk for the PAE mode.
2525	*/
2526	typedef struct PGMPTWALKGSTPAE
2527	{
2528	/** The common core. */
2529	PGMPTWALKCORE Core;
2530
2531	PX86PDPT pPdpt;
2532	PX86PDPE pPdpe;
2533	X86PDPE Pdpe;
2534
2535	PX86PDPAE pPd;
2536	PX86PDEPAE pPde;
2537	X86PDEPAE Pde;
2538
2539	PX86PTPAE pPt;
2540	PX86PTEPAE pPte;
2541	X86PTEPAE Pte;
2542	} PGMPTWALKGSTPAE;
2543	/** Pointer to a PAE guest page table walk. */
2544	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2545	/** Pointer to a const AMD64 guest page table walk. */
2546	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2547
2548	/**
2549	* Guest page table walk for the 32-bit mode.
2550	*/
2551	typedef struct PGMPTWALKGST32BIT
2552	{
2553	/** The common core. */
2554	PGMPTWALKCORE Core;
2555
2556	PX86PD pPd;
2557	PX86PDE pPde;
2558	X86PDE Pde;
2559
2560	PX86PT pPt;
2561	PX86PTE pPte;
2562	X86PTE Pte;
2563	} PGMPTWALKGST32BIT;
2564	/** Pointer to a 32-bit guest page table walk. */
2565	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2566	/** Pointer to a const 32-bit guest page table walk. */
2567	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2568
2569
2570	/** @name Paging mode macros
2571	* @{
2572	*/
2573	#ifdef IN_RC
2574	# define PGM_CTX(a,b) a##RC##b
2575	# define PGM_CTX_STR(a,b) a "GC" b
2576	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2577	#else
2578	# ifdef IN_RING3
2579	# define PGM_CTX(a,b) a##R3##b
2580	# define PGM_CTX_STR(a,b) a "R3" b
2581	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2582	# else
2583	# define PGM_CTX(a,b) a##R0##b
2584	# define PGM_CTX_STR(a,b) a "R0" b
2585	# define PGM_CTX_DECL(type) VMMDECL(type)
2586	# endif
2587	#endif
2588
2589	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2590	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2591	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2592	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2593	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2594	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2595	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2596	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2597	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2598	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2599	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2600	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2601	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2602	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2603	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2604	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2605	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2606
2607	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2608	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2609	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2610	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2611	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2612	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2613	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2614	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2615	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2616	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2617	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2618	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2619	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2620	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2621	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2622	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2623	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2624
2625	/* Shw_Gst */
2626	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2627	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2628	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2629	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2630	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2631	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2632	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2633	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2634	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2635	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2636	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2637	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2638	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2639	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2640	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2641	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2642	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2643	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2644	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2645
2646	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2647	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2648	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2649	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2650	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2651	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2652	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2653	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2654	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2655	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2656	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2657	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2658	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2659	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2660	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2661	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2662	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2663	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2664	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2665	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2666	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2667	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2668	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2669	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2670	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2671	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2672	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2673	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2674	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2675	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2676	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2677	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2678	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2679	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2680	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2681	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2682	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2683
2684	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2685	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2686	/** @} */
2687
2688	/**
2689	* Data for each paging mode.
2690	*/
2691	typedef struct PGMMODEDATA
2692	{
2693	/** The guest mode type. */
2694	uint32_t uGstType;
2695	/** The shadow mode type. */
2696	uint32_t uShwType;
2697
2698	/** @name Function pointers for Shadow paging.
2699	* @{
2700	*/
2701	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2702	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2703	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2704	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2705
2706	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2707	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2708
2709	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2710	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2711	/** @} */
2712
2713	/** @name Function pointers for Guest paging.
2714	* @{
2715	*/
2716	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2717	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2718	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2719	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2720	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2721	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2722	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2723	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2724	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2725	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2726	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2727	/** @} */
2728
2729	/** @name Function pointers for Both Shadow and Guest paging.
2730	* @{
2731	*/
2732	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2733	/* no pfnR3BthTrap0eHandler */
2734	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2735	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2736	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2737	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2738	#ifdef VBOX_STRICT
2739	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2740	#endif
2741	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2742	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2743
2744	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2745	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2746	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2747	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2748	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2749	#ifdef VBOX_STRICT
2750	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2751	#endif
2752	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2753	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2754
2755	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2756	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2757	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2758	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2759	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2760	#ifdef VBOX_STRICT
2761	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2762	#endif
2763	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2764	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2765	/** @} */
2766	} PGMMODEDATA, *PPGMMODEDATA;
2767
2768
2769	#ifdef VBOX_WITH_STATISTICS
2770	/**
2771	* PGM statistics.
2772	*
2773	* These lives on the heap when compiled in as they would otherwise waste
2774	* unnecessary space in release builds.
2775	*/
2776	typedef struct PGMSTATS
2777	{
2778	/* R3 only: */
2779	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2780	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2781
2782	/* R3+RZ */
2783	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2784	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2785	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2786	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2787	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2788	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2789	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2790	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2791	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2792	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2793	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2794	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2795	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2796	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2797	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2798	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2799	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2800	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2801	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2802	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2803	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2804	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2805	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2806	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2807	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2808	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2809	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2810	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2811
2812	/* RC only: */
2813	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2814	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2815
2816	STAMCOUNTER StatRZPhysRead;
2817	STAMCOUNTER StatRZPhysReadBytes;
2818	STAMCOUNTER StatRZPhysWrite;
2819	STAMCOUNTER StatRZPhysWriteBytes;
2820	STAMCOUNTER StatR3PhysRead;
2821	STAMCOUNTER StatR3PhysReadBytes;
2822	STAMCOUNTER StatR3PhysWrite;
2823	STAMCOUNTER StatR3PhysWriteBytes;
2824	STAMCOUNTER StatRCPhysRead;
2825	STAMCOUNTER StatRCPhysReadBytes;
2826	STAMCOUNTER StatRCPhysWrite;
2827	STAMCOUNTER StatRCPhysWriteBytes;
2828
2829	STAMCOUNTER StatRZPhysSimpleRead;
2830	STAMCOUNTER StatRZPhysSimpleReadBytes;
2831	STAMCOUNTER StatRZPhysSimpleWrite;
2832	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2833	STAMCOUNTER StatR3PhysSimpleRead;
2834	STAMCOUNTER StatR3PhysSimpleReadBytes;
2835	STAMCOUNTER StatR3PhysSimpleWrite;
2836	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2837	STAMCOUNTER StatRCPhysSimpleRead;
2838	STAMCOUNTER StatRCPhysSimpleReadBytes;
2839	STAMCOUNTER StatRCPhysSimpleWrite;
2840	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2841
2842	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2843	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2844	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2845	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2846	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2847	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2848	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2849
2850	/** Time spent by the host OS for large page allocation. */
2851	STAMPROFILE StatAllocLargePage;
2852	/** Time spent clearing the newly allocated large pages. */
2853	STAMPROFILE StatClearLargePage;
2854	/** The number of times allocating a large pages takes more than the allowed period. */
2855	STAMCOUNTER StatLargePageOverflow;
2856	/** pgmPhysIsValidLargePage profiling - R3 */
2857	STAMPROFILE StatR3IsValidLargePage;
2858	/** pgmPhysIsValidLargePage profiling - RZ*/
2859	STAMPROFILE StatRZIsValidLargePage;
2860
2861	STAMPROFILE StatChunkAging;
2862	STAMPROFILE StatChunkFindCandidate;
2863	STAMPROFILE StatChunkUnmap;
2864	STAMPROFILE StatChunkMap;
2865	} PGMSTATS;
2866	#endif /* VBOX_WITH_STATISTICS */
2867
2868
2869	/**
2870	* Converts a PGM pointer into a VM pointer.
2871	* @returns Pointer to the VM structure the PGM is part of.
2872	* @param pPGM Pointer to PGM instance data.
2873	*/
2874	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2875
2876	/**
2877	* PGM Data (part of VM)
2878	*/
2879	typedef struct PGM
2880	{
2881	/** Offset to the VM structure. */
2882	int32_t offVM;
2883	/** Offset of the PGMCPU structure relative to VMCPU. */
2884	int32_t offVCpuPGM;
2885
2886	/** @cfgm{RamPreAlloc, boolean, false}
2887	* Indicates whether the base RAM should all be allocated before starting
2888	* the VM (default), or if it should be allocated when first written to.
2889	*/
2890	bool fRamPreAlloc;
2891	/** Indicates whether write monitoring is currently in use.
2892	* This is used to prevent conflicts between live saving and page sharing
2893	* detection. */
2894	bool fPhysWriteMonitoringEngaged;
2895	/** Set if the CPU has less than 52-bit physical address width.
2896	* This is used */
2897	bool fLessThan52PhysicalAddressBits;
2898	/** Set when nested paging is active.
2899	* This is meant to save calls to HWACCMIsNestedPagingActive and let the
2900	* compilers optimize the code better. Whether we use nested paging or
2901	* not is something we find out during VMM initialization and we won't
2902	* change this later on. */
2903	bool fNestedPaging;
2904	/** The host paging mode. (This is what SUPLib reports.) */
2905	SUPPAGINGMODE enmHostMode;
2906	/** We're not in a state which permits writes to guest memory.
2907	* (Only used in strict builds.) */
2908	bool fNoMorePhysWrites;
2909	/** Alignment padding that makes the next member start on a 8 byte boundary. */
2910	bool afAlignment1[3];
2911
2912	/** Indicates that PGMR3FinalizeMappings has been called and that further
2913	* PGMR3MapIntermediate calls will be rejected. */
2914	bool fFinalizedMappings;
2915	/** If set no conflict checks are required. */
2916	bool fMappingsFixed;
2917	/** If set if restored as fixed but we were unable to re-fixate at the old
2918	* location because of room or address incompatibilities. */
2919	bool fMappingsFixedRestored;
2920	/** If set, then no mappings are put into the shadow page table.
2921	* Use pgmMapAreMappingsEnabled() instead of direct access. */
2922	bool fMappingsDisabled;
2923	/** Size of fixed mapping.
2924	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2925	uint32_t cbMappingFixed;
2926	/** Generation ID for the RAM ranges. This member is incremented everytime
2927	* a RAM range is linked or unlinked. */
2928	uint32_t volatile idRamRangesGen;
2929
2930	/** Base address (GC) of fixed mapping.
2931	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2932	RTGCPTR GCPtrMappingFixed;
2933	/** The address of the previous RAM range mapping. */
2934	RTGCPTR GCPtrPrevRamRangeMapping;
2935
2936	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2937	RTGCPHYS GCPhys4MBPSEMask;
2938	/** Mask containing the invalid bits of a guest physical address.
2939	* @remarks this does not stop at bit 52. */
2940	RTGCPHYS GCPhysInvAddrMask;
2941
2942
2943	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2944	* This is sorted by physical address and contains no overlapping ranges. */
2945	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2946	/** PGM offset based trees - R3 Ptr. */
2947	R3PTRTYPE(PPGMTREES) pTreesR3;
2948	/** Caching the last physical handler we looked up in R3. */
2949	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2950	/** Shadow Page Pool - R3 Ptr. */
2951	R3PTRTYPE(PPGMPOOL) pPoolR3;
2952	/** Linked list of GC mappings - for HC.
2953	* The list is sorted ascending on address. */
2954	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2955	/** Pointer to the list of ROM ranges - for R3.
2956	* This is sorted by physical address and contains no overlapping ranges. */
2957	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2958	/** Pointer to the list of MMIO2 ranges - for R3.
2959	* Registration order. */
2960	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2961	/** Pointer to SHW+GST mode data (function pointers).
2962	* The index into this table is made up from */
2963	R3PTRTYPE(PPGMMODEDATA) paModeData;
2964	/RTR3PTR R3PtrAlignment0;/
2965
2966
2967	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2968	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2969	/** PGM offset based trees - R0 Ptr. */
2970	R0PTRTYPE(PPGMTREES) pTreesR0;
2971	/** Caching the last physical handler we looked up in R0. */
2972	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2973	/** Shadow Page Pool - R0 Ptr. */
2974	R0PTRTYPE(PPGMPOOL) pPoolR0;
2975	/** Linked list of GC mappings - for R0.
2976	* The list is sorted ascending on address. */
2977	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2978	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2979	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2980	/RTR0PTR R0PtrAlignment0;/
2981
2982
2983	/** RC pointer corresponding to PGM::pRamRangesR3. */
2984	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2985	/** PGM offset based trees - RC Ptr. */
2986	RCPTRTYPE(PPGMTREES) pTreesRC;
2987	/** Caching the last physical handler we looked up in RC. */
2988	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
2989	/** Shadow Page Pool - RC Ptr. */
2990	RCPTRTYPE(PPGMPOOL) pPoolRC;
2991	/** Linked list of GC mappings - for RC.
2992	* The list is sorted ascending on address. */
2993	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2994	/** RC pointer corresponding to PGM::pRomRangesR3. */
2995	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2996	/RTRCPTR RCPtrAlignment0;/
2997	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2998	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2999	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3000	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3001
3002
3003	/** Pointer to the 5 page CR3 content mapping.
3004	* The first page is always the CR3 (in some form) while the 4 other pages
3005	* are used of the PDs in PAE mode. */
3006	RTGCPTR GCPtrCR3Mapping;
3007
3008	/** @name Intermediate Context
3009	* @{ */
3010	/** Pointer to the intermediate page directory - Normal. */
3011	R3PTRTYPE(PX86PD) pInterPD;
3012	/** Pointer to the intermediate page tables - Normal.
3013	* There are two page tables, one for the identity mapping and one for
3014	* the host context mapping (of the core code). */
3015	R3PTRTYPE(PX86PT) apInterPTs[2];
3016	/** Pointer to the intermediate page tables - PAE. */
3017	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3018	/** Pointer to the intermediate page directory - PAE. */
3019	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3020	/** Pointer to the intermediate page directory - PAE. */
3021	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3022	/** Pointer to the intermediate page-map level 4 - AMD64. */
3023	R3PTRTYPE(PX86PML4) pInterPaePML4;
3024	/** Pointer to the intermediate page directory - AMD64. */
3025	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3026	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3027	RTHCPHYS HCPhysInterPD;
3028	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3029	RTHCPHYS HCPhysInterPaePDPT;
3030	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3031	RTHCPHYS HCPhysInterPaePML4;
3032	/** @} */
3033
3034	/** Base address of the dynamic page mapping area.
3035	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3036	*
3037	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3038	* work out. Some cleaning up of the initialization that would
3039	* remove this memory is yet to be done...
3040	*/
3041	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3042	/** The address of the raw-mode context mapping cache. */
3043	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3044	/** The address of the ring-0 mapping cache if we're making use of it. */
3045	RTR0PTR pvR0DynMapUsed;
3046	#if HC_ARCH_BITS == 32
3047	/** Alignment padding that makes the next member start on a 8 byte boundary. */
3048	uint32_t u32Alignment2;
3049	#endif
3050
3051	/** PGM critical section.
3052	* This protects the physical & virtual access handlers, ram ranges,
3053	* and the page flag updating (some of it anyway).
3054	*/
3055	PDMCRITSECT CritSect;
3056
3057	/**
3058	* Data associated with managing the ring-3 mappings of the allocation chunks.
3059	*/
3060	struct
3061	{
3062	/** The chunk tree, ordered by chunk id. */
3063	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3064	R3PTRTYPE(PAVLU32NODECORE) pTree;
3065	#else
3066	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3067	#endif
3068	#if HC_ARCH_BITS == 32
3069	uint32_t u32Alignment;
3070	#endif
3071	/** The chunk mapping TLB. */
3072	PGMCHUNKR3MAPTLB Tlb;
3073	/** The number of mapped chunks. */
3074	uint32_t c;
3075	/** The maximum number of mapped chunks.
3076	* @cfgm PGM/MaxRing3Chunks */
3077	uint32_t cMax;
3078	/** The current time. */
3079	uint32_t iNow;
3080	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3081	uint32_t AgeingCountdown;
3082	} ChunkR3Map;
3083
3084	/**
3085	* The page mapping TLB for ring-3 and (for the time being) ring-0.
3086	*/
3087	PGMPAGER3MAPTLB PhysTlbHC;
3088
3089	/** @name The zero page.
3090	* @{ */
3091	/** The host physical address of the zero page. */
3092	RTHCPHYS HCPhysZeroPg;
3093	/** The ring-3 mapping of the zero page. */
3094	RTR3PTR pvZeroPgR3;
3095	/** The ring-0 mapping of the zero page. */
3096	RTR0PTR pvZeroPgR0;
3097	/** The GC mapping of the zero page. */
3098	RTRCPTR pvZeroPgRC;
3099	RTRCPTR RCPtrAlignment3;
3100	/** @}*/
3101
3102	/** @name The Invalid MMIO page.
3103	* This page is filled with 0xfeedface.
3104	* @{ */
3105	/** The host physical address of the invalid MMIO page. */
3106	RTHCPHYS HCPhysMmioPg;
3107	/** The host pysical address of the invalid MMIO page plus all invalid
3108	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3109	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3110	RTHCPHYS HCPhysInvMmioPg;
3111	/** The ring-3 mapping of the invalid MMIO page. */
3112	RTR3PTR pvMmioPgR3;
3113	#if HC_ARCH_BITS == 32
3114	RTR3PTR R3PtrAlignment4;
3115	#endif
3116	/** @} */
3117
3118
3119	/** The number of handy pages. */
3120	uint32_t cHandyPages;
3121
3122	/** The number of large handy pages. */
3123	uint32_t cLargeHandyPages;
3124
3125	/**
3126	* Array of handy pages.
3127	*
3128	* This array is used in a two way communication between pgmPhysAllocPage
3129	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3130	* an intermediary.
3131	*
3132	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3133	* (The current size of 32 pages, means 128 KB of handy memory.)
3134	*/
3135	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3136
3137	/**
3138	* Array of large handy pages. (currently size 1)
3139	*
3140	* This array is used in a two way communication between pgmPhysAllocLargePage
3141	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3142	* an intermediary.
3143	*/
3144	GMMPAGEDESC aLargeHandyPage[1];
3145
3146	/**
3147	* Live save data.
3148	*/
3149	struct
3150	{
3151	/** Per type statistics. */
3152	struct
3153	{
3154	/** The number of ready pages. */
3155	uint32_t cReadyPages;
3156	/** The number of dirty pages. */
3157	uint32_t cDirtyPages;
3158	/** The number of ready zero pages. */
3159	uint32_t cZeroPages;
3160	/** The number of write monitored pages. */
3161	uint32_t cMonitoredPages;
3162	} Rom,
3163	Mmio2,
3164	Ram;
3165	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3166	uint32_t cIgnoredPages;
3167	/** Indicates that a live save operation is active. */
3168	bool fActive;
3169	/** Padding. */
3170	bool afReserved[2];
3171	/** The next history index. */
3172	uint8_t iDirtyPagesHistory;
3173	/** History of the total amount of dirty pages. */
3174	uint32_t acDirtyPagesHistory[64];
3175	/** Short term dirty page average. */
3176	uint32_t cDirtyPagesShort;
3177	/** Long term dirty page average. */
3178	uint32_t cDirtyPagesLong;
3179	/** The number of saved pages. This is used to get some kind of estimate of the
3180	* link speed so we can decide when we're done. It is reset after the first
3181	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3182	* zero pages. */
3183	uint64_t cSavedPages;
3184	/** The nanosecond timestamp when cSavedPages was 0. */
3185	uint64_t uSaveStartNS;
3186	/** Pages per second (for statistics). */
3187	uint32_t cPagesPerSecond;
3188	uint32_t cAlignment;
3189	} LiveSave;
3190
3191	/** @name Error injection.
3192	* @{ */
3193	/** Inject handy page allocation errors pretending we're completely out of
3194	* memory. */
3195	bool volatile fErrInjHandyPages;
3196	/** Padding. */
3197	bool afReserved[3];
3198	/** @} */
3199
3200	/** @name Release Statistics
3201	* @{ */
3202	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3203	uint32_t cPrivatePages; /*< The number of private pages. /
3204	uint32_t cSharedPages; /*< The number of shared pages. /
3205	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3206	uint32_t cZeroPages; /*< The number of zero backed pages. /
3207	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3208	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3209	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3210	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3211	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3212	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3213	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3214	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3215	/* uint32_t aAlignment4[1]; */
3216
3217	/** The number of times we were forced to change the hypervisor region location. */
3218	STAMCOUNTER cRelocations;
3219
3220	STAMCOUNTER StatLargePageAlloc; /*< The number of large pages we've allocated./
3221	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3222	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3223	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3224	/** @} */
3225
3226	#ifdef VBOX_WITH_STATISTICS
3227	/** @name Statistics on the heap.
3228	* @{ */
3229	R3PTRTYPE(PGMSTATS *) pStatsR3;
3230	R0PTRTYPE(PGMSTATS *) pStatsR0;
3231	RCPTRTYPE(PGMSTATS *) pStatsRC;
3232	RTRCPTR RCPtrAlignment;
3233	/** @} */
3234	#endif
3235	} PGM;
3236	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3237	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3238	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3239	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3240	AssertCompileMemberAlignment(PGM, CritSect, 8);
3241	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3242	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3243	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3244	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3245	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3246	#endif /* !IN_TSTVMSTRUCTGC */
3247	/** Pointer to the PGM instance data. */
3248	typedef PGM *PPGM;
3249
3250
3251
3252	typedef struct PGMCPUSTATS
3253	{
3254	/* Common */
3255	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3256	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3257
3258	/* R0 only: */
3259	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3260	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3261
3262	/* RZ only: */
3263	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3264	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3265	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3266	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3267	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3268	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3269	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3270	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3271	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3272	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3273	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3274	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3275	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3276	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3277	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3278	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3279	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3280	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3281	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3282	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3283	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3284	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3285	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3286	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3287	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3288	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3289	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3290	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3291	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3292	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3293	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3294	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3295	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3296	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3297	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3298	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3299	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3300	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3301	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3302	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3303	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3304	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3305	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3306	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3307	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3308	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3309	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3310	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3311	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3312	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3313	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3314	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3315	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3316	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3317	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3318	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3319	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3320	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3321	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3322	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3323	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3324	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3325	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3326	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3327	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3328	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3329	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3330	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3331	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3332	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3333	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3334	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3335	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3336	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3337	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3338	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3339
3340	/* HC - R3 and (maybe) R0: */
3341
3342	/* RZ & R3: */
3343	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3344	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3345	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3346	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3347	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3348	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3349	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3350	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3351	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3352	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3353	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3354	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3355	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3356	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3357	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3358	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3359	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3360	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3361	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3362	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3363	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3364	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3365	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3366	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3367	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3368	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3369	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3370	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3371	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3372	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3373	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3374	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3375	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3376	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3377	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3378	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3379	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3380	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3381	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3382	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3383	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3384	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3385	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3386	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3387	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3388	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3389	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3390
3391	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3392	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3393	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3394	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3395	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3396	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3397	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3398	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3399	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3400	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3401	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3402	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3403	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3404	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3405	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3406	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3407	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3408	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3409	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3410	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3411	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3412	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3413	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3414	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3415	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3416	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3417	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3418	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3419	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3420	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3421	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3422	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3423	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3424	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3425	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3426	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3427	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3428	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3429	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3430	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3431	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3432	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3433	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3434	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3435	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3436	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3437	/** @} */
3438	} PGMCPUSTATS;
3439
3440
3441	/**
3442	* Converts a PGMCPU pointer into a VM pointer.
3443	* @returns Pointer to the VM structure the PGM is part of.
3444	* @param pPGM Pointer to PGMCPU instance data.
3445	*/
3446	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3447
3448	/**
3449	* Converts a PGMCPU pointer into a PGM pointer.
3450	* @returns Pointer to the VM structure the PGM is part of.
3451	* @param pPGM Pointer to PGMCPU instance data.
3452	*/
3453	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3454
3455	/**
3456	* PGMCPU Data (part of VMCPU).
3457	*/
3458	typedef struct PGMCPU
3459	{
3460	/** Offset to the VM structure. */
3461	int32_t offVM;
3462	/** Offset to the VMCPU structure. */
3463	int32_t offVCpu;
3464	/** Offset of the PGM structure relative to VMCPU. */
3465	int32_t offPGM;
3466	uint32_t uPadding0; /*< structure size alignment. /
3467
3468	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3469	/** Automatically tracked physical memory mapping set.
3470	* Ring-0 and strict raw-mode builds. */
3471	PGMMAPSET AutoSet;
3472	#endif
3473
3474	/** A20 gate mask.
3475	* Our current approach to A20 emulation is to let REM do it and don't bother
3476	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3477	* But whould need arrise, we'll subject physical addresses to this mask. */
3478	RTGCPHYS GCPhysA20Mask;
3479	/** A20 gate state - boolean! */
3480	bool fA20Enabled;
3481	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3482	bool fNoExecuteEnabled;
3483	/** Unused bits. */
3484	bool afUnused[2];
3485
3486	/** What needs syncing (PGM_SYNC_*).
3487	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3488	* PGMFlushTLB, and PGMR3Load. */
3489	RTUINT fSyncFlags;
3490
3491	/** The shadow paging mode. */
3492	PGMMODE enmShadowMode;
3493	/** The guest paging mode. */
3494	PGMMODE enmGuestMode;
3495
3496	/** The current physical address representing in the guest CR3 register. */
3497	RTGCPHYS GCPhysCR3;
3498
3499	/** @name 32-bit Guest Paging.
3500	* @{ */
3501	/** The guest's page directory, R3 pointer. */
3502	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3503	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3504	/** The guest's page directory, R0 pointer. */
3505	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3506	#endif
3507	/** The guest's page directory, static RC mapping. */
3508	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3509	/** Mask containing the MBZ bits of a big page PDE. */
3510	uint32_t fGst32BitMbzBigPdeMask;
3511	/** Set if the page size extension (PSE) is enabled. */
3512	bool fGst32BitPageSizeExtension;
3513	/** Alignment padding. */
3514	bool afAlignment2[3];
3515	/** @} */
3516
3517	/** @name PAE Guest Paging.
3518	* @{ */
3519	/** The guest's page directory pointer table, static RC mapping. */
3520	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3521	/** The guest's page directory pointer table, R3 pointer. */
3522	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3523	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3524	/** The guest's page directory pointer table, R0 pointer. */
3525	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3526	#endif
3527
3528	/** The guest's page directories, R3 pointers.
3529	* These are individual pointers and don't have to be adjacent.
3530	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3531	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3532	/** The guest's page directories, R0 pointers.
3533	* Same restrictions as apGstPaePDsR3. */
3534	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3535	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3536	#endif
3537	/** The guest's page directories, static GC mapping.
3538	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3539	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3540	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3541	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3542	RTGCPHYS aGCPhysGstPaePDs[4];
3543	/** The physical addresses of the monitored guest page directories (PAE). */
3544	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3545	/** Mask containing the MBZ PTE bits. */
3546	uint64_t fGstPaeMbzPteMask;
3547	/** Mask containing the MBZ PDE bits. */
3548	uint64_t fGstPaeMbzPdeMask;
3549	/** Mask containing the MBZ big page PDE bits. */
3550	uint64_t fGstPaeMbzBigPdeMask;
3551	/** Mask containing the MBZ PDPE bits. */
3552	uint64_t fGstPaeMbzPdpeMask;
3553	/** @} */
3554
3555	/** @name AMD64 Guest Paging.
3556	* @{ */
3557	/** The guest's page directory pointer table, R3 pointer. */
3558	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3559	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3560	/** The guest's page directory pointer table, R0 pointer. */
3561	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3562	#else
3563	RTR0PTR alignment6b; /*< alignment equalizer. /
3564	#endif
3565	/** Mask containing the MBZ PTE bits. */
3566	uint64_t fGstAmd64MbzPteMask;
3567	/** Mask containing the MBZ PDE bits. */
3568	uint64_t fGstAmd64MbzPdeMask;
3569	/** Mask containing the MBZ big page PDE bits. */
3570	uint64_t fGstAmd64MbzBigPdeMask;
3571	/** Mask containing the MBZ PDPE bits. */
3572	uint64_t fGstAmd64MbzPdpeMask;
3573	/** Mask containing the MBZ big page PDPE bits. */
3574	uint64_t fGstAmd64MbzBigPdpeMask;
3575	/** Mask containing the MBZ PML4E bits. */
3576	uint64_t fGstAmd64MbzPml4eMask;
3577	/** Mask containing the PDPE bits that we shadow. */
3578	uint64_t fGstAmd64ShadowedPdpeMask;
3579	/** Mask containing the PML4E bits that we shadow. */
3580	uint64_t fGstAmd64ShadowedPml4eMask;
3581	/** @} */
3582
3583	/** @name PAE and AMD64 Guest Paging.
3584	* @{ */
3585	/** Mask containing the PTE bits that we shadow. */
3586	uint64_t fGst64ShadowedPteMask;
3587	/** Mask containing the PDE bits that we shadow. */
3588	uint64_t fGst64ShadowedPdeMask;
3589	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3590	uint64_t fGst64ShadowedBigPdeMask;
3591	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3592	uint64_t fGst64ShadowedBigPde4PteMask;
3593	/** @} */
3594
3595	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3596	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3597	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3598	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3599	/** Pointer to the page of the current active CR3 - RC Ptr. */
3600	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3601	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3602	uint32_t iShwUser;
3603	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3604	uint32_t iShwUserTable;
3605	# if HC_ARCH_BITS == 64
3606	RTRCPTR alignment6; /*< structure size alignment. /
3607	# endif
3608	/** @} */
3609
3610	/** @name Function pointers for Shadow paging.
3611	* @{
3612	*/
3613	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3614	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3615	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3616	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3617
3618	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3619	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3620
3621	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3622	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3623
3624	/** @} */
3625
3626	/** @name Function pointers for Guest paging.
3627	* @{
3628	*/
3629	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3630	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3631	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3632	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3633	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3634	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3635	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3636	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3637	#if HC_ARCH_BITS == 64
3638	RTRCPTR alignment3; /*< structure size alignment. /
3639	#endif
3640
3641	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3642	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3643	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3644	/** @} */
3645
3646	/** @name Function pointers for Both Shadow and Guest paging.
3647	* @{
3648	*/
3649	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3650	/* no pfnR3BthTrap0eHandler */
3651	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3652	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3653	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3654	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3655	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3656	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3657	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3658
3659	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3660	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3661	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3662	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3663	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3664	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3665	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3666	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3667
3668	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3669	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3670	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3671	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3672	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3673	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3674	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3675	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3676	#if 0
3677	RTRCPTR alignment2; /*< structure size alignment. /
3678	#endif
3679	/** @} */
3680
3681	/** For saving stack space, the disassembler state is allocated here instead of
3682	* on the stack.
3683	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3684	union
3685	{
3686	/** The disassembler scratch space. */
3687	DISCPUSTATE DisState;
3688	/** Padding. */
3689	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3690	};
3691
3692	/** Count the number of pgm pool access handler calls. */
3693	uint64_t cPoolAccessHandler;
3694
3695	/** @name Release Statistics
3696	* @{ */
3697	/** The number of times the guest has switched mode since last reset or statistics reset. */
3698	STAMCOUNTER cGuestModeChanges;
3699	/** @} */
3700
3701	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3702	/** @name Statistics
3703	* @{ */
3704	/** RC: Pointer to the statistics. */
3705	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3706	/** RC: Which statistic this \#PF should be attributed to. */
3707	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3708	/** R0: Pointer to the statistics. */
3709	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3710	/** R0: Which statistic this \#PF should be attributed to. */
3711	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3712	/** R3: Pointer to the statistics. */
3713	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3714	/** Alignment padding. */
3715	RTR3PTR pPaddingR3;
3716	/** @} */
3717	#endif /* VBOX_WITH_STATISTICS */
3718	} PGMCPU;
3719	/** Pointer to the per-cpu PGM data. */
3720	typedef PGMCPU *PPGMCPU;
3721
3722
3723	/** @name PGM::fSyncFlags Flags
3724	* @{
3725	*/
3726	/** Updates the virtual access handler state bit in PGMPAGE. */
3727	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3728	/** Always sync CR3. */
3729	#define PGM_SYNC_ALWAYS RT_BIT(1)
3730	/** Check monitoring on next CR3 (re)load and invalidate page.
3731	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3732	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3733	/** Check guest mapping in SyncCR3. */
3734	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3735	/** Clear the page pool (a light weight flush). */
3736	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3737	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3738	/** @} */
3739
3740
3741	RT_C_DECLS_BEGIN
3742
3743	int pgmLock(PVM pVM);
3744	void pgmUnlock(PVM pVM);
3745
3746	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3747	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3748	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3749	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3750	int pgmMapResolveConflicts(PVM pVM);
3751	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3752
3753	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3754	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3755	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3756	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
3757	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3758	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
3759	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3760	#else
3761	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3762	#endif
3763	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3764	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3765
3766	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3767	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3768	int pgmPhysIsValidLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3769	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3770	int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3771	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3772	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3773	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3774	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3775	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3776	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3777	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3778	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3779	VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3780	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3781	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3782
3783	#ifdef IN_RING3
3784	void pgmR3PhysRelinkRamRanges(PVM pVM);
3785	int pgmR3PhysRamPreAllocate(PVM pVM);
3786	int pgmR3PhysRamReset(PVM pVM);
3787	int pgmR3PhysRomReset(PVM pVM);
3788	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3789	int pgmR3PhysRamTerm(PVM pVM);
3790	void pgmR3PhysRomTerm(PVM pVM);
3791
3792	int pgmR3PoolInit(PVM pVM);
3793	void pgmR3PoolRelocate(PVM pVM);
3794	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3795	void pgmR3PoolReset(PVM pVM);
3796	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3797	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3798	void pgmR3PoolWriteProtectPages(PVM pVM);
3799
3800	#endif /* IN_RING3 */
3801	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
3802	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3803	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3804	# ifdef LOG_ENABLED
3805	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3806	# else
3807	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3808	# endif
3809	#endif
3810	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3811	uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3812
3813	DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3814	PPPGMPOOLPAGE ppPage)
3815	{
3816	return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3817	}
3818
3819	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3820	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3821	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3822	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3823	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3824	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3825	int pgmPoolSyncCR3(PVMCPU pVCpu);
3826	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3827	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3828	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3829	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3830	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3831	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3832	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3833	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3834	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3835
3836	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3837	void pgmPoolResetDirtyPages(PVM pVM);
3838	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
3839
3840	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3841	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3842
3843	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3844	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3845	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3846	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3847
3848	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3849	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3850
3851	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3852	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3853	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3854	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3855
3856	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3857	DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3858	DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
3859	# endif
3860
3861	RT_C_DECLS_END
3862
3863	/** @} */
3864
3865	#endif
3866

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 35273

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