VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 22621

Last change on this file since 22621 was 22600, checked in by vboxsync, 15 years ago

Removed unnecessary EPT invlpg calls.
Invalidate the page who's R/W attribute was changed.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 191.4 KB
Line 
1/* $Id: PGMInternal.h 22600 2009-08-31 12:19:56Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <VBox/hwaccm.h>
39#include <iprt/avl.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/critsect.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
59 * Comment it if it will break something.
60 */
61#define PGM_OUT_OF_SYNC_IN_GC
62
63/**
64 * Check and skip global PDEs for non-global flushes
65 */
66#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
67
68/**
69 * Optimization for PAE page tables that are modified often
70 */
71#ifndef IN_RC
72////# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
73#endif
74
75/**
76 * Sync N pages instead of a whole page table
77 */
78#define PGM_SYNC_N_PAGES
79
80/**
81 * Number of pages to sync during a page fault
82 *
83 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
84 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
85 */
86#define PGM_SYNC_NR_PAGES 8
87
88/**
89 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
90 */
91#define PGM_MAX_PHYSCACHE_ENTRIES 64
92#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
93
94/** @def PGMPOOL_WITH_CACHE
95 * Enable agressive caching using the page pool.
96 *
97 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
98 */
99#define PGMPOOL_WITH_CACHE
100
101/** @def PGMPOOL_WITH_MIXED_PT_CR3
102 * When defined, we'll deal with 'uncachable' pages.
103 */
104#ifdef PGMPOOL_WITH_CACHE
105# define PGMPOOL_WITH_MIXED_PT_CR3
106#endif
107
108/** @def PGMPOOL_WITH_MONITORING
109 * Monitor the guest pages which are shadowed.
110 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
111 * be enabled as well.
112 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
113 */
114#ifdef PGMPOOL_WITH_CACHE
115# define PGMPOOL_WITH_MONITORING
116#endif
117
118/** @def PGMPOOL_WITH_GCPHYS_TRACKING
119 * Tracking the of shadow pages mapping guest physical pages.
120 *
121 * This is very expensive, the current cache prototype is trying to figure out
122 * whether it will be acceptable with an agressive caching policy.
123 */
124#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
125# define PGMPOOL_WITH_GCPHYS_TRACKING
126#endif
127
128/** @def PGMPOOL_WITH_USER_TRACKING
129 * Tracking users of shadow pages. This is required for the linking of shadow page
130 * tables and physical guest addresses.
131 */
132#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
133# define PGMPOOL_WITH_USER_TRACKING
134#endif
135
136/** @def PGMPOOL_CFG_MAX_GROW
137 * The maximum number of pages to add to the pool in one go.
138 */
139#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
140
141/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
142 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
143 */
144#ifdef VBOX_STRICT
145# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
146#endif
147
148/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
149 * Enables the experimental lazy page allocation code. */
150/*# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
151
152/** @} */
153
154
155/** @name PDPT and PML4 flags.
156 * These are placed in the three bits available for system programs in
157 * the PDPT and PML4 entries.
158 * @{ */
159/** The entry is a permanent one and it's must always be present.
160 * Never free such an entry. */
161#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
162/** Mapping (hypervisor allocated pagetable). */
163#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
164/** @} */
165
166/** @name Page directory flags.
167 * These are placed in the three bits available for system programs in
168 * the page directory entries.
169 * @{ */
170/** Mapping (hypervisor allocated pagetable). */
171#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
172/** Made read-only to facilitate dirty bit tracking. */
173#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
174/** @} */
175
176/** @name Page flags.
177 * These are placed in the three bits available for system programs in
178 * the page entries.
179 * @{ */
180/** Made read-only to facilitate dirty bit tracking. */
181#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
182
183#ifndef PGM_PTFLAGS_CSAM_VALIDATED
184/** Scanned and approved by CSAM (tm).
185 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
186 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
187#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
188#endif
189
190/** @} */
191
192/** @name Defines used to indicate the shadow and guest paging in the templates.
193 * @{ */
194#define PGM_TYPE_REAL 1
195#define PGM_TYPE_PROT 2
196#define PGM_TYPE_32BIT 3
197#define PGM_TYPE_PAE 4
198#define PGM_TYPE_AMD64 5
199#define PGM_TYPE_NESTED 6
200#define PGM_TYPE_EPT 7
201#define PGM_TYPE_MAX PGM_TYPE_EPT
202/** @} */
203
204/** Macro for checking if the guest is using paging.
205 * @param uGstType PGM_TYPE_*
206 * @param uShwType PGM_TYPE_*
207 * @remark ASSUMES certain order of the PGM_TYPE_* values.
208 */
209#define PGM_WITH_PAGING(uGstType, uShwType) \
210 ( (uGstType) >= PGM_TYPE_32BIT \
211 && (uShwType) != PGM_TYPE_NESTED \
212 && (uShwType) != PGM_TYPE_EPT)
213
214/** Macro for checking if the guest supports the NX bit.
215 * @param uGstType PGM_TYPE_*
216 * @param uShwType PGM_TYPE_*
217 * @remark ASSUMES certain order of the PGM_TYPE_* values.
218 */
219#define PGM_WITH_NX(uGstType, uShwType) \
220 ( (uGstType) >= PGM_TYPE_PAE \
221 && (uShwType) != PGM_TYPE_NESTED \
222 && (uShwType) != PGM_TYPE_EPT)
223
224
225/** @def PGM_HCPHYS_2_PTR
226 * Maps a HC physical page pool address to a virtual address.
227 *
228 * @returns VBox status code.
229 * @param pVM The VM handle.
230 * @param HCPhys The HC physical address to map to a virtual one.
231 * @param ppv Where to store the virtual address. No need to cast this.
232 *
233 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
234 * small page window employeed by that function. Be careful.
235 * @remark There is no need to assert on the result.
236 */
237#ifdef IN_RC
238# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
239 PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
240#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
241# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
242 pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
243#else
244# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_HCPHYS_2_PTR_BY_PGM
249 * Maps a HC physical page pool address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pPGM The PGM instance data.
253 * @param HCPhys The HC physical address to map to a virtual one.
254 * @param ppv Where to store the virtual address. No need to cast this.
255 *
256 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
257 * small page window employeed by that function. Be careful.
258 * @remark There is no need to assert on the result.
259 */
260#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
261# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
262 pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
263#else
264# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
265 PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
266#endif
267
268/** @def PGM_GCPHYS_2_PTR
269 * Maps a GC physical page address to a virtual address.
270 *
271 * @returns VBox status code.
272 * @param pVM The VM handle.
273 * @param GCPhys The GC physical address to map to a virtual one.
274 * @param ppv Where to store the virtual address. No need to cast this.
275 *
276 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
277 * small page window employeed by that function. Be careful.
278 * @remark There is no need to assert on the result.
279 */
280#ifdef IN_RC
281# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
282 PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
283#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
284# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
285 pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
286#else
287# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
288 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
289#endif
290
291/** @def PGM_GCPHYS_2_PTR_BY_PGMCPU
292 * Maps a GC physical page address to a virtual address.
293 *
294 * @returns VBox status code.
295 * @param pPGM Pointer to the PGM instance data.
296 * @param GCPhys The GC physical address to map to a virtual one.
297 * @param ppv Where to store the virtual address. No need to cast this.
298 *
299 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
300 * small page window employeed by that function. Be careful.
301 * @remark There is no need to assert on the result.
302 */
303#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
304# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
305 pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), GCPhys, (void **)(ppv))
306#else
307# define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv) \
308 PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
309#endif
310
311/** @def PGM_GCPHYS_2_PTR_EX
312 * Maps a unaligned GC physical page address to a virtual address.
313 *
314 * @returns VBox status code.
315 * @param pVM The VM handle.
316 * @param GCPhys The GC physical address to map to a virtual one.
317 * @param ppv Where to store the virtual address. No need to cast this.
318 *
319 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
320 * small page window employeed by that function. Be careful.
321 * @remark There is no need to assert on the result.
322 */
323#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
324# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325 PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
326#else
327# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
328 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
329#endif
330
331/** @def PGM_INVL_PG
332 * Invalidates a page.
333 *
334 * @param pVCpu The VMCPU handle.
335 * @param GCVirt The virtual address of the page to invalidate.
336 */
337#ifdef IN_RC
338# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt))
339#elif defined(IN_RING0)
340# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
341#else
342# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
343#endif
344
345/** @def PGM_INVL_PG_ALL_VCPU
346 * Invalidates a page on all VCPUs
347 *
348 * @param pVM The VM handle.
349 * @param GCVirt The virtual address of the page to invalidate.
350 */
351#ifdef IN_RC
352# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(GCVirt))
353#elif defined(IN_RING0)
354# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
355#else
356# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
357#endif
358
359/** @def PGM_INVL_BIG_PG
360 * Invalidates a 4MB page directory entry.
361 *
362 * @param pVCpu The VMCPU handle.
363 * @param GCVirt The virtual address within the page directory to invalidate.
364 */
365#ifdef IN_RC
366# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
367#elif defined(IN_RING0)
368# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
369#else
370# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
371#endif
372
373/** @def PGM_INVL_VCPU_TLBS()
374 * Invalidates the TLBs of the specified VCPU
375 *
376 * @param pVCpu The VMCPU handle.
377 */
378#ifdef IN_RC
379# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
380#elif defined(IN_RING0)
381# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
382#else
383# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
384#endif
385
386/** @def PGM_INVL_ALL_VCPU_TLBS()
387 * Invalidates the TLBs of all VCPUs
388 *
389 * @param pVM The VM handle.
390 */
391#ifdef IN_RC
392# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
393#elif defined(IN_RING0)
394# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
395#else
396# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
397#endif
398
399/** Size of the GCPtrConflict array in PGMMAPPING.
400 * @remarks Must be a power of two. */
401#define PGMMAPPING_CONFLICT_MAX 8
402
403/**
404 * Structure for tracking GC Mappings.
405 *
406 * This structure is used by linked list in both GC and HC.
407 */
408typedef struct PGMMAPPING
409{
410 /** Pointer to next entry. */
411 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
412 /** Pointer to next entry. */
413 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
414 /** Pointer to next entry. */
415 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
416 /** Indicate whether this entry is finalized. */
417 bool fFinalized;
418 /** Start Virtual address. */
419 RTGCPTR GCPtr;
420 /** Last Virtual address (inclusive). */
421 RTGCPTR GCPtrLast;
422 /** Range size (bytes). */
423 RTGCPTR cb;
424 /** Pointer to relocation callback function. */
425 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
426 /** User argument to the callback. */
427 R3PTRTYPE(void *) pvUser;
428 /** Mapping description / name. For easing debugging. */
429 R3PTRTYPE(const char *) pszDesc;
430 /** Last 8 addresses that caused conflicts. */
431 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
432 /** Number of conflicts for this hypervisor mapping. */
433 uint32_t cConflicts;
434 /** Number of page tables. */
435 uint32_t cPTs;
436
437 /** Array of page table mapping data. Each entry
438 * describes one page table. The array can be longer
439 * than the declared length.
440 */
441 struct
442 {
443 /** The HC physical address of the page table. */
444 RTHCPHYS HCPhysPT;
445 /** The HC physical address of the first PAE page table. */
446 RTHCPHYS HCPhysPaePT0;
447 /** The HC physical address of the second PAE page table. */
448 RTHCPHYS HCPhysPaePT1;
449 /** The HC virtual address of the 32-bit page table. */
450 R3PTRTYPE(PX86PT) pPTR3;
451 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
452 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
453 /** The RC virtual address of the 32-bit page table. */
454 RCPTRTYPE(PX86PT) pPTRC;
455 /** The RC virtual address of the two PAE page table. */
456 RCPTRTYPE(PX86PTPAE) paPaePTsRC;
457 /** The R0 virtual address of the 32-bit page table. */
458 R0PTRTYPE(PX86PT) pPTR0;
459 /** The R0 virtual address of the two PAE page table. */
460 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
461 } aPTs[1];
462} PGMMAPPING;
463/** Pointer to structure for tracking GC Mappings. */
464typedef struct PGMMAPPING *PPGMMAPPING;
465
466
467/**
468 * Physical page access handler structure.
469 *
470 * This is used to keep track of physical address ranges
471 * which are being monitored in some kind of way.
472 */
473typedef struct PGMPHYSHANDLER
474{
475 AVLROGCPHYSNODECORE Core;
476 /** Access type. */
477 PGMPHYSHANDLERTYPE enmType;
478 /** Number of pages to update. */
479 uint32_t cPages;
480 /** Pointer to R3 callback function. */
481 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
482 /** User argument for R3 handlers. */
483 R3PTRTYPE(void *) pvUserR3;
484 /** Pointer to R0 callback function. */
485 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
486 /** User argument for R0 handlers. */
487 R0PTRTYPE(void *) pvUserR0;
488 /** Pointer to RC callback function. */
489 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
490 /** User argument for RC handlers. */
491 RCPTRTYPE(void *) pvUserRC;
492 /** Description / Name. For easing debugging. */
493 R3PTRTYPE(const char *) pszDesc;
494#ifdef VBOX_WITH_STATISTICS
495 /** Profiling of this handler. */
496 STAMPROFILE Stat;
497#endif
498} PGMPHYSHANDLER;
499/** Pointer to a physical page access handler structure. */
500typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
501
502
503/**
504 * Cache node for the physical addresses covered by a virtual handler.
505 */
506typedef struct PGMPHYS2VIRTHANDLER
507{
508 /** Core node for the tree based on physical ranges. */
509 AVLROGCPHYSNODECORE Core;
510 /** Offset from this struct to the PGMVIRTHANDLER structure. */
511 int32_t offVirtHandler;
512 /** Offset of the next alias relative to this one.
513 * Bit 0 is used for indicating whether we're in the tree.
514 * Bit 1 is used for indicating that we're the head node.
515 */
516 int32_t offNextAlias;
517} PGMPHYS2VIRTHANDLER;
518/** Pointer to a phys to virtual handler structure. */
519typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
520
521/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
522 * node is in the tree. */
523#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
524/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
525 * node is in the head of an alias chain.
526 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
527#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
528/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
529#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
530
531
532/**
533 * Virtual page access handler structure.
534 *
535 * This is used to keep track of virtual address ranges
536 * which are being monitored in some kind of way.
537 */
538typedef struct PGMVIRTHANDLER
539{
540 /** Core node for the tree based on virtual ranges. */
541 AVLROGCPTRNODECORE Core;
542 /** Size of the range (in bytes). */
543 RTGCPTR cb;
544 /** Number of cache pages. */
545 uint32_t cPages;
546 /** Access type. */
547 PGMVIRTHANDLERTYPE enmType;
548 /** Pointer to the RC callback function. */
549 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
550#if HC_ARCH_BITS == 64
551 RTRCPTR padding;
552#endif
553 /** Pointer to the R3 callback function for invalidation. */
554 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
555 /** Pointer to the R3 callback function. */
556 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
557 /** Description / Name. For easing debugging. */
558 R3PTRTYPE(const char *) pszDesc;
559#ifdef VBOX_WITH_STATISTICS
560 /** Profiling of this handler. */
561 STAMPROFILE Stat;
562#endif
563 /** Array of cached physical addresses for the monitored ranged. */
564 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
565} PGMVIRTHANDLER;
566/** Pointer to a virtual page access handler structure. */
567typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
568
569
570/**
571 * Page type.
572 *
573 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
574 * @remarks This is used in the saved state, so changes to it requires bumping
575 * the saved state version.
576 * @todo So, convert to \#defines!
577 */
578typedef enum PGMPAGETYPE
579{
580 /** The usual invalid zero entry. */
581 PGMPAGETYPE_INVALID = 0,
582 /** RAM page. (RWX) */
583 PGMPAGETYPE_RAM,
584 /** MMIO2 page. (RWX) */
585 PGMPAGETYPE_MMIO2,
586 /** MMIO2 page aliased over an MMIO page. (RWX)
587 * See PGMHandlerPhysicalPageAlias(). */
588 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
589 /** Shadowed ROM. (RWX) */
590 PGMPAGETYPE_ROM_SHADOW,
591 /** ROM page. (R-X) */
592 PGMPAGETYPE_ROM,
593 /** MMIO page. (---) */
594 PGMPAGETYPE_MMIO,
595 /** End of valid entries. */
596 PGMPAGETYPE_END
597} PGMPAGETYPE;
598AssertCompile(PGMPAGETYPE_END <= 7);
599
600/** @name Page type predicates.
601 * @{ */
602#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
603#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
604#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
605#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
606#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
607/** @} */
608
609
610/**
611 * A Physical Guest Page tracking structure.
612 *
613 * The format of this structure is complicated because we have to fit a lot
614 * of information into as few bits as possible. The format is also subject
615 * to change (there is one comming up soon). Which means that for we'll be
616 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
617 * accessess to the structure.
618 */
619typedef struct PGMPAGE
620{
621 /** The physical address and a whole lot of other stuff. All bits are used! */
622 RTHCPHYS HCPhysX;
623 /** The page state. */
624 uint32_t u2StateX : 2;
625 /** Flag indicating that a write monitored page was written to when set. */
626 uint32_t fWrittenToX : 1;
627 /** For later. */
628 uint32_t fSomethingElse : 1;
629 /** The Page ID.
630 * @todo Merge with HCPhysX once we've liberated HCPhysX of its stuff.
631 * The HCPhysX will then be 100% static. */
632 uint32_t idPageX : 28;
633 /** The page type (PGMPAGETYPE). */
634 uint32_t u3Type : 3;
635 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
636 uint32_t u2HandlerPhysStateX : 2;
637 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
638 uint32_t u2HandlerVirtStateX : 2;
639 uint32_t u29B : 25;
640} PGMPAGE;
641AssertCompileSize(PGMPAGE, 16);
642/** Pointer to a physical guest page. */
643typedef PGMPAGE *PPGMPAGE;
644/** Pointer to a const physical guest page. */
645typedef const PGMPAGE *PCPGMPAGE;
646/** Pointer to a physical guest page pointer. */
647typedef PPGMPAGE *PPPGMPAGE;
648
649
650/**
651 * Clears the page structure.
652 * @param pPage Pointer to the physical guest page tracking structure.
653 */
654#define PGM_PAGE_CLEAR(pPage) \
655 do { \
656 (pPage)->HCPhysX = 0; \
657 (pPage)->u2StateX = 0; \
658 (pPage)->fWrittenToX = 0; \
659 (pPage)->fSomethingElse = 0; \
660 (pPage)->idPageX = 0; \
661 (pPage)->u3Type = 0; \
662 (pPage)->u29B = 0; \
663 } while (0)
664
665/**
666 * Initializes the page structure.
667 * @param pPage Pointer to the physical guest page tracking structure.
668 */
669#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
670 do { \
671 (pPage)->HCPhysX = (_HCPhys); \
672 (pPage)->u2StateX = (_uState); \
673 (pPage)->fWrittenToX = 0; \
674 (pPage)->fSomethingElse = 0; \
675 (pPage)->idPageX = (_idPage); \
676 /*(pPage)->u3Type = (_uType); - later */ \
677 PGM_PAGE_SET_TYPE(pPage, _uType); \
678 (pPage)->u29B = 0; \
679 } while (0)
680
681/**
682 * Initializes the page structure of a ZERO page.
683 * @param pPage Pointer to the physical guest page tracking structure.
684 */
685#define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
686 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
687/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
688# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
689 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
690
691
692/** @name The Page state, PGMPAGE::u2StateX.
693 * @{ */
694/** The zero page.
695 * This is a per-VM page that's never ever mapped writable. */
696#define PGM_PAGE_STATE_ZERO 0
697/** A allocated page.
698 * This is a per-VM page allocated from the page pool (or wherever
699 * we get MMIO2 pages from if the type is MMIO2).
700 */
701#define PGM_PAGE_STATE_ALLOCATED 1
702/** A allocated page that's being monitored for writes.
703 * The shadow page table mappings are read-only. When a write occurs, the
704 * fWrittenTo member is set, the page remapped as read-write and the state
705 * moved back to allocated. */
706#define PGM_PAGE_STATE_WRITE_MONITORED 2
707/** The page is shared, aka. copy-on-write.
708 * This is a page that's shared with other VMs. */
709#define PGM_PAGE_STATE_SHARED 3
710/** @} */
711
712
713/**
714 * Gets the page state.
715 * @returns page state (PGM_PAGE_STATE_*).
716 * @param pPage Pointer to the physical guest page tracking structure.
717 */
718#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
719
720/**
721 * Sets the page state.
722 * @param pPage Pointer to the physical guest page tracking structure.
723 * @param _uState The new page state.
724 */
725#define PGM_PAGE_SET_STATE(pPage, _uState) \
726 do { (pPage)->u2StateX = (_uState); } while (0)
727
728
729/**
730 * Gets the host physical address of the guest page.
731 * @returns host physical address (RTHCPHYS).
732 * @param pPage Pointer to the physical guest page tracking structure.
733 */
734#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
735
736/**
737 * Sets the host physical address of the guest page.
738 * @param pPage Pointer to the physical guest page tracking structure.
739 * @param _HCPhys The new host physical address.
740 */
741#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
742 do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0xffff000000000fff)) \
743 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
744
745/**
746 * Get the Page ID.
747 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
748 * @param pPage Pointer to the physical guest page tracking structure.
749 */
750#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
751/* later:
752#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhysX >> (48 - 12))
753 | ((uint32_t)(pPage)->HCPhysX & 0xfff) )
754*/
755/**
756 * Sets the Page ID.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
760/* later:
761#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhysX = (((pPage)->HCPhysX) & UINT64_C(0x0000fffffffff000)) \
762 | ((_idPage) & 0xfff) \
763 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
764*/
765
766/**
767 * Get the Chunk ID.
768 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
769 * @param pPage Pointer to the physical guest page tracking structure.
770 */
771#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
772/* later:
773#if GMM_CHUNKID_SHIFT == 12
774# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> 48) )
775#elif GMM_CHUNKID_SHIFT > 12
776# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhysX >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
777#elif GMM_CHUNKID_SHIFT < 12
778# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhysX >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
779 | ( (uint32_t)((pPage)->HCPhysX & 0xfff) >> GMM_CHUNKID_SHIFT ) )
780#else
781# error "GMM_CHUNKID_SHIFT isn't defined or something."
782#endif
783*/
784
785/**
786 * Get the index of the page within the allocaiton chunk.
787 * @returns The page index.
788 * @param pPage Pointer to the physical guest page tracking structure.
789 */
790#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
791/* later:
792#if GMM_CHUNKID_SHIFT <= 12
793# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & GMM_PAGEID_IDX_MASK) )
794#else
795# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysX & 0xfff) \
796 | ( (uint32_t)((pPage)->HCPhysX >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
797#endif
798*/
799
800
801/**
802 * Gets the page type.
803 * @returns The page type.
804 * @param pPage Pointer to the physical guest page tracking structure.
805 */
806#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
807
808/**
809 * Sets the page type.
810 * @param pPage Pointer to the physical guest page tracking structure.
811 * @param _enmType The new page type (PGMPAGETYPE).
812 */
813#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
814 do { (pPage)->u3Type = (_enmType); } while (0)
815
816/**
817 * Checks if the page is marked for MMIO.
818 * @returns true/false.
819 * @param pPage Pointer to the physical guest page tracking structure.
820 */
821#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
822
823/**
824 * Checks if the page is backed by the ZERO page.
825 * @returns true/false.
826 * @param pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
829
830/**
831 * Checks if the page is backed by a SHARED page.
832 * @returns true/false.
833 * @param pPage Pointer to the physical guest page tracking structure.
834 */
835#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
836
837
838/**
839 * Marks the paget as written to (for GMM change monitoring).
840 * @param pPage Pointer to the physical guest page tracking structure.
841 */
842#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
843
844/**
845 * Clears the written-to indicator.
846 * @param pPage Pointer to the physical guest page tracking structure.
847 */
848#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
849
850/**
851 * Checks if the page was marked as written-to.
852 * @returns true/false.
853 * @param pPage Pointer to the physical guest page tracking structure.
854 */
855#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
856
857
858/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
859 *
860 * @remarks The values are assigned in order of priority, so we can calculate
861 * the correct state for a page with different handlers installed.
862 * @{ */
863/** No handler installed. */
864#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
865/** Monitoring is temporarily disabled. */
866#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
867/** Write access is monitored. */
868#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
869/** All access is monitored. */
870#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
871/** @} */
872
873/**
874 * Gets the physical access handler state of a page.
875 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
876 * @param pPage Pointer to the physical guest page tracking structure.
877 */
878#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
879
880/**
881 * Sets the physical access handler state of a page.
882 * @param pPage Pointer to the physical guest page tracking structure.
883 * @param _uState The new state value.
884 */
885#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
886 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
887
888/**
889 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
890 * @returns true/false
891 * @param pPage Pointer to the physical guest page tracking structure.
892 */
893#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
894
895/**
896 * Checks if the page has any active physical access handlers.
897 * @returns true/false
898 * @param pPage Pointer to the physical guest page tracking structure.
899 */
900#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
901
902
903/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
904 *
905 * @remarks The values are assigned in order of priority, so we can calculate
906 * the correct state for a page with different handlers installed.
907 * @{ */
908/** No handler installed. */
909#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
910/* 1 is reserved so the lineup is identical with the physical ones. */
911/** Write access is monitored. */
912#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
913/** All access is monitored. */
914#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
915/** @} */
916
917/**
918 * Gets the virtual access handler state of a page.
919 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
920 * @param pPage Pointer to the physical guest page tracking structure.
921 */
922#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
923
924/**
925 * Sets the virtual access handler state of a page.
926 * @param pPage Pointer to the physical guest page tracking structure.
927 * @param _uState The new state value.
928 */
929#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
930 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
931
932/**
933 * Checks if the page has any virtual access handlers.
934 * @returns true/false
935 * @param pPage Pointer to the physical guest page tracking structure.
936 */
937#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
938
939/**
940 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
941 * virtual handlers.
942 * @returns true/false
943 * @param pPage Pointer to the physical guest page tracking structure.
944 */
945#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
946
947
948
949/**
950 * Checks if the page has any access handlers, including temporarily disabled ones.
951 * @returns true/false
952 * @param pPage Pointer to the physical guest page tracking structure.
953 */
954#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
955 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
956 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
957
958/**
959 * Checks if the page has any active access handlers.
960 * @returns true/false
961 * @param pPage Pointer to the physical guest page tracking structure.
962 */
963#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
964 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
965 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
966
967/**
968 * Checks if the page has any active access handlers catching all accesses.
969 * @returns true/false
970 * @param pPage Pointer to the physical guest page tracking structure.
971 */
972#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
973 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
974 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
975
976
977
978
979/** @def PGM_PAGE_GET_TRACKING
980 * Gets the packed shadow page pool tracking data associated with a guest page.
981 * @returns uint16_t containing the data.
982 * @param pPage Pointer to the physical guest page tracking structure.
983 */
984#define PGM_PAGE_GET_TRACKING(pPage) \
985 ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
986
987/** @def PGM_PAGE_SET_TRACKING
988 * Sets the packed shadow page pool tracking data associated with a guest page.
989 * @param pPage Pointer to the physical guest page tracking structure.
990 * @param u16TrackingData The tracking data to store.
991 */
992#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
993 do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
994
995/** @def PGM_PAGE_GET_TD_CREFS
996 * Gets the @a cRefs tracking data member.
997 * @returns cRefs.
998 * @param pPage Pointer to the physical guest page tracking structure.
999 */
1000#define PGM_PAGE_GET_TD_CREFS(pPage) \
1001 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1002
1003#define PGM_PAGE_GET_TD_IDX(pPage) \
1004 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1005
1006/**
1007 * Ram range for GC Phys to HC Phys conversion.
1008 *
1009 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1010 * conversions too, but we'll let MM handle that for now.
1011 *
1012 * This structure is used by linked lists in both GC and HC.
1013 */
1014typedef struct PGMRAMRANGE
1015{
1016 /** Start of the range. Page aligned. */
1017 RTGCPHYS GCPhys;
1018 /** Size of the range. (Page aligned of course). */
1019 RTGCPHYS cb;
1020 /** Pointer to the next RAM range - for R3. */
1021 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1022 /** Pointer to the next RAM range - for R0. */
1023 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1024 /** Pointer to the next RAM range - for RC. */
1025 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1026 /** PGM_RAM_RANGE_FLAGS_* flags. */
1027 uint32_t fFlags;
1028 /** Last address in the range (inclusive). Page aligned (-1). */
1029 RTGCPHYS GCPhysLast;
1030 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1031 R3PTRTYPE(void *) pvR3;
1032 /** The range description. */
1033 R3PTRTYPE(const char *) pszDesc;
1034 /** Pointer to self - R0 pointer. */
1035 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1036 /** Pointer to self - RC pointer. */
1037 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1038 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1039 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 1];
1040 /** Array of physical guest page tracking structures. */
1041 PGMPAGE aPages[1];
1042} PGMRAMRANGE;
1043/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1044typedef PGMRAMRANGE *PPGMRAMRANGE;
1045
1046/** @name PGMRAMRANGE::fFlags
1047 * @{ */
1048/** The RAM range is floating around as an independent guest mapping. */
1049#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1050/** @} */
1051
1052
1053/**
1054 * Per page tracking structure for ROM image.
1055 *
1056 * A ROM image may have a shadow page, in which case we may have
1057 * two pages backing it. This structure contains the PGMPAGE for
1058 * both while PGMRAMRANGE have a copy of the active one. It is
1059 * important that these aren't out of sync in any regard other
1060 * than page pool tracking data.
1061 */
1062typedef struct PGMROMPAGE
1063{
1064 /** The page structure for the virgin ROM page. */
1065 PGMPAGE Virgin;
1066 /** The page structure for the shadow RAM page. */
1067 PGMPAGE Shadow;
1068 /** The current protection setting. */
1069 PGMROMPROT enmProt;
1070 /** Pad the structure size to a multiple of 8. */
1071 uint32_t u32Padding;
1072} PGMROMPAGE;
1073/** Pointer to a ROM page tracking structure. */
1074typedef PGMROMPAGE *PPGMROMPAGE;
1075
1076
1077/**
1078 * A registered ROM image.
1079 *
1080 * This is needed to keep track of ROM image since they generally
1081 * intrude into a PGMRAMRANGE. It also keeps track of additional
1082 * info like the two page sets (read-only virgin and read-write shadow),
1083 * the current state of each page.
1084 *
1085 * Because access handlers cannot easily be executed in a different
1086 * context, the ROM ranges needs to be accessible and in all contexts.
1087 */
1088typedef struct PGMROMRANGE
1089{
1090 /** Pointer to the next range - R3. */
1091 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1092 /** Pointer to the next range - R0. */
1093 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1094 /** Pointer to the next range - RC. */
1095 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1096 /** Pointer alignment */
1097 RTRCPTR GCPtrAlignment;
1098 /** Address of the range. */
1099 RTGCPHYS GCPhys;
1100 /** Address of the last byte in the range. */
1101 RTGCPHYS GCPhysLast;
1102 /** Size of the range. */
1103 RTGCPHYS cb;
1104 /** The flags (PGMPHYS_ROM_FLAG_*). */
1105 uint32_t fFlags;
1106 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1107 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1108 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1109 * This is used for strictness checks. */
1110 R3PTRTYPE(const void *) pvOriginal;
1111 /** The ROM description. */
1112 R3PTRTYPE(const char *) pszDesc;
1113 /** The per page tracking structures. */
1114 PGMROMPAGE aPages[1];
1115} PGMROMRANGE;
1116/** Pointer to a ROM range. */
1117typedef PGMROMRANGE *PPGMROMRANGE;
1118
1119
1120/**
1121 * A registered MMIO2 (= Device RAM) range.
1122 *
1123 * There are a few reason why we need to keep track of these
1124 * registrations. One of them is the deregistration & cleanup
1125 * stuff, while another is that the PGMRAMRANGE associated with
1126 * such a region may have to be removed from the ram range list.
1127 *
1128 * Overlapping with a RAM range has to be 100% or none at all. The
1129 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1130 * meditation will be raised if a partial overlap or an overlap of
1131 * ROM pages is encountered. On an overlap we will free all the
1132 * existing RAM pages and put in the ram range pages instead.
1133 */
1134typedef struct PGMMMIO2RANGE
1135{
1136 /** The owner of the range. (a device) */
1137 PPDMDEVINSR3 pDevInsR3;
1138 /** Pointer to the ring-3 mapping of the allocation. */
1139 RTR3PTR pvR3;
1140 /** Pointer to the next range - R3. */
1141 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1142 /** Whether it's mapped or not. */
1143 bool fMapped;
1144 /** Whether it's overlapping or not. */
1145 bool fOverlapping;
1146 /** The PCI region number.
1147 * @remarks This ASSUMES that nobody will ever really need to have multiple
1148 * PCI devices with matching MMIO region numbers on a single device. */
1149 uint8_t iRegion;
1150 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1151 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1152 /** The associated RAM range. */
1153 PGMRAMRANGE RamRange;
1154} PGMMMIO2RANGE;
1155/** Pointer to a MMIO2 range. */
1156typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1157
1158
1159
1160
1161/**
1162 * PGMPhysRead/Write cache entry
1163 */
1164typedef struct PGMPHYSCACHEENTRY
1165{
1166 /** R3 pointer to physical page. */
1167 R3PTRTYPE(uint8_t *) pbR3;
1168 /** GC Physical address for cache entry */
1169 RTGCPHYS GCPhys;
1170#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1171 RTGCPHYS u32Padding0; /**< alignment padding. */
1172#endif
1173} PGMPHYSCACHEENTRY;
1174
1175/**
1176 * PGMPhysRead/Write cache to reduce REM memory access overhead
1177 */
1178typedef struct PGMPHYSCACHE
1179{
1180 /** Bitmap of valid cache entries */
1181 uint64_t aEntries;
1182 /** Cache entries */
1183 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1184} PGMPHYSCACHE;
1185
1186
1187/** Pointer to an allocation chunk ring-3 mapping. */
1188typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1189/** Pointer to an allocation chunk ring-3 mapping pointer. */
1190typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1191
1192/**
1193 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1194 *
1195 * The primary tree (Core) uses the chunk id as key.
1196 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1197 */
1198typedef struct PGMCHUNKR3MAP
1199{
1200 /** The key is the chunk id. */
1201 AVLU32NODECORE Core;
1202 /** The key is the ageing sequence number. */
1203 AVLLU32NODECORE AgeCore;
1204 /** The current age thingy. */
1205 uint32_t iAge;
1206 /** The current reference count. */
1207 uint32_t volatile cRefs;
1208 /** The current permanent reference count. */
1209 uint32_t volatile cPermRefs;
1210 /** The mapping address. */
1211 void *pv;
1212} PGMCHUNKR3MAP;
1213
1214/**
1215 * Allocation chunk ring-3 mapping TLB entry.
1216 */
1217typedef struct PGMCHUNKR3MAPTLBE
1218{
1219 /** The chunk id. */
1220 uint32_t volatile idChunk;
1221#if HC_ARCH_BITS == 64
1222 uint32_t u32Padding; /**< alignment padding. */
1223#endif
1224 /** The chunk map. */
1225#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1226 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1227#else
1228 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1229#endif
1230} PGMCHUNKR3MAPTLBE;
1231/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1232typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1233
1234/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1235 * @remark Must be a power of two value. */
1236#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1237
1238/**
1239 * Allocation chunk ring-3 mapping TLB.
1240 *
1241 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1242 * At first glance this might look kinda odd since AVL trees are
1243 * supposed to give the most optimial lookup times of all trees
1244 * due to their balancing. However, take a tree with 1023 nodes
1245 * in it, that's 10 levels, meaning that most searches has to go
1246 * down 9 levels before they find what they want. This isn't fast
1247 * compared to a TLB hit. There is the factor of cache misses,
1248 * and of course the problem with trees and branch prediction.
1249 * This is why we use TLBs in front of most of the trees.
1250 *
1251 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1252 * difficult when we switch to the new inlined AVL trees (from kStuff).
1253 */
1254typedef struct PGMCHUNKR3MAPTLB
1255{
1256 /** The TLB entries. */
1257 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1258} PGMCHUNKR3MAPTLB;
1259
1260/**
1261 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1262 * @returns Chunk TLB index.
1263 * @param idChunk The Chunk ID.
1264 */
1265#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1266
1267
1268/**
1269 * Ring-3 guest page mapping TLB entry.
1270 * @remarks used in ring-0 as well at the moment.
1271 */
1272typedef struct PGMPAGER3MAPTLBE
1273{
1274 /** Address of the page. */
1275 RTGCPHYS volatile GCPhys;
1276 /** The guest page. */
1277#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1278 R3PTRTYPE(PPGMPAGE) volatile pPage;
1279#else
1280 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1281#endif
1282 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1283#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1284 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1285#else
1286 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1287#endif
1288 /** The address */
1289#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1290 R3PTRTYPE(void *) volatile pv;
1291#else
1292 R3R0PTRTYPE(void *) volatile pv;
1293#endif
1294#if HC_ARCH_BITS == 32
1295 uint32_t u32Padding; /**< alignment padding. */
1296#endif
1297} PGMPAGER3MAPTLBE;
1298/** Pointer to an entry in the HC physical TLB. */
1299typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1300
1301
1302/** The number of entries in the ring-3 guest page mapping TLB.
1303 * @remarks The value must be a power of two. */
1304#define PGM_PAGER3MAPTLB_ENTRIES 64
1305
1306/**
1307 * Ring-3 guest page mapping TLB.
1308 * @remarks used in ring-0 as well at the moment.
1309 */
1310typedef struct PGMPAGER3MAPTLB
1311{
1312 /** The TLB entries. */
1313 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1314} PGMPAGER3MAPTLB;
1315/** Pointer to the ring-3 guest page mapping TLB. */
1316typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1317
1318/**
1319 * Calculates the index of the TLB entry for the specified guest page.
1320 * @returns Physical TLB index.
1321 * @param GCPhys The guest physical address.
1322 */
1323#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1324
1325
1326/**
1327 * Mapping cache usage set entry.
1328 *
1329 * @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1330 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1331 * cache. If it's extended to include ring-3, well, then something will
1332 * have be changed here...
1333 */
1334typedef struct PGMMAPSETENTRY
1335{
1336 /** The mapping cache index. */
1337 uint16_t iPage;
1338 /** The number of references.
1339 * The max is UINT16_MAX - 1. */
1340 uint16_t cRefs;
1341#if HC_ARCH_BITS == 64
1342 uint32_t alignment;
1343#endif
1344 /** Pointer to the page. */
1345 RTR0PTR pvPage;
1346 /** The physical address for this entry. */
1347 RTHCPHYS HCPhys;
1348} PGMMAPSETENTRY;
1349/** Pointer to a mapping cache usage set entry. */
1350typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1351
1352/**
1353 * Mapping cache usage set.
1354 *
1355 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1356 * done during exits / traps. The set is
1357 */
1358typedef struct PGMMAPSET
1359{
1360 /** The number of occupied entries.
1361 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1362 * dynamic mappings. */
1363 uint32_t cEntries;
1364 /** The start of the current subset.
1365 * This is UINT32_MAX if no subset is currently open. */
1366 uint32_t iSubset;
1367 /** The index of the current CPU, only valid if the set is open. */
1368 int32_t iCpu;
1369#if HC_ARCH_BITS == 64
1370 uint32_t alignment;
1371#endif
1372 /** The entries. */
1373 PGMMAPSETENTRY aEntries[64];
1374 /** HCPhys -> iEntry fast lookup table.
1375 * Use PGMMAPSET_HASH for hashing.
1376 * The entries may or may not be valid, check against cEntries. */
1377 uint8_t aiHashTable[128];
1378} PGMMAPSET;
1379/** Pointer to the mapping cache set. */
1380typedef PGMMAPSET *PPGMMAPSET;
1381
1382/** PGMMAPSET::cEntries value for a closed set. */
1383#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1384
1385/** Hash function for aiHashTable. */
1386#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1387
1388/** The max fill size (strict builds). */
1389#define PGMMAPSET_MAX_FILL (64U * 80U / 100U)
1390
1391
1392/** @name Context neutrual page mapper TLB.
1393 *
1394 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1395 * code is writting in a kind of context neutrual way. Time will show whether
1396 * this actually makes sense or not...
1397 *
1398 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1399 * context ends up using a global mapping cache on some platforms
1400 * (darwin).
1401 *
1402 * @{ */
1403/** @typedef PPGMPAGEMAPTLB
1404 * The page mapper TLB pointer type for the current context. */
1405/** @typedef PPGMPAGEMAPTLB
1406 * The page mapper TLB entry pointer type for the current context. */
1407/** @typedef PPGMPAGEMAPTLB
1408 * The page mapper TLB entry pointer pointer type for the current context. */
1409/** @def PGM_PAGEMAPTLB_ENTRIES
1410 * The number of TLB entries in the page mapper TLB for the current context. */
1411/** @def PGM_PAGEMAPTLB_IDX
1412 * Calculate the TLB index for a guest physical address.
1413 * @returns The TLB index.
1414 * @param GCPhys The guest physical address. */
1415/** @typedef PPGMPAGEMAP
1416 * Pointer to a page mapper unit for current context. */
1417/** @typedef PPPGMPAGEMAP
1418 * Pointer to a page mapper unit pointer for current context. */
1419#ifdef IN_RC
1420// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1421// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1422// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1423# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1424# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1425 typedef void * PPGMPAGEMAP;
1426 typedef void ** PPPGMPAGEMAP;
1427//#elif IN_RING0
1428// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1429// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1430// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1431//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1432//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1433// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1434// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1435#else
1436 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1437 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1438 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1439# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1440# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1441 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1442 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1443#endif
1444/** @} */
1445
1446
1447/** @name PGM Pool Indexes.
1448 * Aka. the unique shadow page identifier.
1449 * @{ */
1450/** NIL page pool IDX. */
1451#define NIL_PGMPOOL_IDX 0
1452/** The first normal index. */
1453#define PGMPOOL_IDX_FIRST_SPECIAL 1
1454/** Page directory (32-bit root). */
1455#define PGMPOOL_IDX_PD 1
1456/** Page Directory Pointer Table (PAE root). */
1457#define PGMPOOL_IDX_PDPT 2
1458/** AMD64 CR3 level index.*/
1459#define PGMPOOL_IDX_AMD64_CR3 3
1460/** Nested paging root.*/
1461#define PGMPOOL_IDX_NESTED_ROOT 4
1462/** The first normal index. */
1463#define PGMPOOL_IDX_FIRST 5
1464/** The last valid index. (inclusive, 14 bits) */
1465#define PGMPOOL_IDX_LAST 0x3fff
1466/** @} */
1467
1468/** The NIL index for the parent chain. */
1469#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1470
1471/**
1472 * Node in the chain linking a shadowed page to it's parent (user).
1473 */
1474#pragma pack(1)
1475typedef struct PGMPOOLUSER
1476{
1477 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1478 uint16_t iNext;
1479 /** The user page index. */
1480 uint16_t iUser;
1481 /** Index into the user table. */
1482 uint32_t iUserTable;
1483} PGMPOOLUSER, *PPGMPOOLUSER;
1484typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1485#pragma pack()
1486
1487
1488/** The NIL index for the phys ext chain. */
1489#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1490
1491/**
1492 * Node in the chain of physical cross reference extents.
1493 * @todo Calling this an 'extent' is not quite right, find a better name.
1494 */
1495#pragma pack(1)
1496typedef struct PGMPOOLPHYSEXT
1497{
1498 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1499 uint16_t iNext;
1500 /** The user page index. */
1501 uint16_t aidx[3];
1502} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1503typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1504#pragma pack()
1505
1506
1507/**
1508 * The kind of page that's being shadowed.
1509 */
1510typedef enum PGMPOOLKIND
1511{
1512 /** The virtual invalid 0 entry. */
1513 PGMPOOLKIND_INVALID = 0,
1514 /** The entry is free (=unused). */
1515 PGMPOOLKIND_FREE,
1516
1517 /** Shw: 32-bit page table; Gst: no paging */
1518 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1519 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1520 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1521 /** Shw: 32-bit page table; Gst: 4MB page. */
1522 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1523 /** Shw: PAE page table; Gst: no paging */
1524 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1525 /** Shw: PAE page table; Gst: 32-bit page table. */
1526 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1527 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1528 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1529 /** Shw: PAE page table; Gst: PAE page table. */
1530 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1531 /** Shw: PAE page table; Gst: 2MB page. */
1532 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1533
1534 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1535 PGMPOOLKIND_32BIT_PD,
1536 /** Shw: 32-bit page directory. Gst: no paging. */
1537 PGMPOOLKIND_32BIT_PD_PHYS,
1538 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1539 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1540 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1541 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1542 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1543 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1544 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1545 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1546 /** Shw: PAE page directory; Gst: PAE page directory. */
1547 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1548 /** Shw: PAE page directory; Gst: no paging. */
1549 PGMPOOLKIND_PAE_PD_PHYS,
1550
1551 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1552 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1553 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1554 PGMPOOLKIND_PAE_PDPT,
1555 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1556 PGMPOOLKIND_PAE_PDPT_PHYS,
1557
1558 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1559 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1560 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1561 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1562 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1563 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1564 /** Shw: 64-bit page directory table; Gst: no paging */
1565 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1566
1567 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1568 PGMPOOLKIND_64BIT_PML4,
1569
1570 /** Shw: EPT page directory pointer table; Gst: no paging */
1571 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1572 /** Shw: EPT page directory table; Gst: no paging */
1573 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1574 /** Shw: EPT page table; Gst: no paging */
1575 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1576
1577 /** Shw: Root Nested paging table. */
1578 PGMPOOLKIND_ROOT_NESTED,
1579
1580 /** The last valid entry. */
1581 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1582} PGMPOOLKIND;
1583
1584/**
1585 * The access attributes of the page; only applies to big pages.
1586 */
1587typedef enum
1588{
1589 PGMPOOLACCESS_DONTCARE = 0,
1590 PGMPOOLACCESS_USER_RW,
1591 PGMPOOLACCESS_USER_R,
1592 PGMPOOLACCESS_USER_RW_NX,
1593 PGMPOOLACCESS_USER_R_NX,
1594 PGMPOOLACCESS_SUPERVISOR_RW,
1595 PGMPOOLACCESS_SUPERVISOR_R,
1596 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1597 PGMPOOLACCESS_SUPERVISOR_R_NX
1598} PGMPOOLACCESS;
1599
1600/**
1601 * The tracking data for a page in the pool.
1602 */
1603typedef struct PGMPOOLPAGE
1604{
1605 /** AVL node code with the (R3) physical address of this page. */
1606 AVLOHCPHYSNODECORE Core;
1607 /** Pointer to the R3 mapping of the page. */
1608#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1609 R3PTRTYPE(void *) pvPageR3;
1610#else
1611 R3R0PTRTYPE(void *) pvPageR3;
1612#endif
1613 /** The guest physical address. */
1614#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1615 uint32_t Alignment0;
1616#endif
1617 RTGCPHYS GCPhys;
1618
1619 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
1620 RTGCPTR pvLastAccessHandlerRip;
1621 RTGCPTR pvLastAccessHandlerFault;
1622 uint64_t cLastAccessHandlerCount;
1623
1624 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1625 uint8_t enmKind;
1626 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1627 uint8_t enmAccess;
1628 /** The index of this page. */
1629 uint16_t idx;
1630 /** The next entry in the list this page currently resides in.
1631 * It's either in the free list or in the GCPhys hash. */
1632 uint16_t iNext;
1633#ifdef PGMPOOL_WITH_USER_TRACKING
1634 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1635 uint16_t iUserHead;
1636 /** The number of present entries. */
1637 uint16_t cPresent;
1638 /** The first entry in the table which is present. */
1639 uint16_t iFirstPresent;
1640#endif
1641#ifdef PGMPOOL_WITH_MONITORING
1642 /** The number of modifications to the monitored page. */
1643 uint16_t cModifications;
1644 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1645 uint16_t iModifiedNext;
1646 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1647 uint16_t iModifiedPrev;
1648 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1649 uint16_t iMonitoredNext;
1650 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1651 uint16_t iMonitoredPrev;
1652#endif
1653#ifdef PGMPOOL_WITH_CACHE
1654 /** The next page in the age list. */
1655 uint16_t iAgeNext;
1656 /** The previous page in the age list. */
1657 uint16_t iAgePrev;
1658#endif /* PGMPOOL_WITH_CACHE */
1659 /** Used to indicate that the page is zeroed. */
1660 bool fZeroed;
1661 /** Used to indicate that a PT has non-global entries. */
1662 bool fSeenNonGlobal;
1663 /** Used to indicate that we're monitoring writes to the guest page. */
1664 bool fMonitored;
1665 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1666 * (All pages are in the age list.) */
1667 bool fCached;
1668 /** This is used by the R3 access handlers when invoked by an async thread.
1669 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1670 bool volatile fReusedFlushPending;
1671#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1672 /** Used to mark the page as dirty (write monitoring if temporarily off. */
1673 bool fDirty;
1674#else
1675 bool bPadding1;
1676#endif
1677
1678 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
1679 uint32_t cLocked;
1680#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1681 uint32_t idxDirty;
1682 RTGCPTR pvDirtyFault;
1683#else
1684 uint32_t bPadding2;
1685#endif
1686} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1687/** Pointer to a const pool page. */
1688typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1689
1690
1691#ifdef PGMPOOL_WITH_CACHE
1692/** The hash table size. */
1693# define PGMPOOL_HASH_SIZE 0x40
1694/** The hash function. */
1695# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1696#endif
1697
1698
1699/**
1700 * The shadow page pool instance data.
1701 *
1702 * It's all one big allocation made at init time, except for the
1703 * pages that is. The user nodes follows immediatly after the
1704 * page structures.
1705 */
1706typedef struct PGMPOOL
1707{
1708 /** The VM handle - R3 Ptr. */
1709 PVMR3 pVMR3;
1710 /** The VM handle - R0 Ptr. */
1711 PVMR0 pVMR0;
1712 /** The VM handle - RC Ptr. */
1713 PVMRC pVMRC;
1714 /** The max pool size. This includes the special IDs. */
1715 uint16_t cMaxPages;
1716 /** The current pool size. */
1717 uint16_t cCurPages;
1718 /** The head of the free page list. */
1719 uint16_t iFreeHead;
1720 /* Padding. */
1721 uint16_t u16Padding;
1722#ifdef PGMPOOL_WITH_USER_TRACKING
1723 /** Head of the chain of free user nodes. */
1724 uint16_t iUserFreeHead;
1725 /** The number of user nodes we've allocated. */
1726 uint16_t cMaxUsers;
1727 /** The number of present page table entries in the entire pool. */
1728 uint32_t cPresent;
1729 /** Pointer to the array of user nodes - RC pointer. */
1730 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1731 /** Pointer to the array of user nodes - R3 pointer. */
1732 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1733 /** Pointer to the array of user nodes - R0 pointer. */
1734 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1735#endif /* PGMPOOL_WITH_USER_TRACKING */
1736#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1737 /** Head of the chain of free phys ext nodes. */
1738 uint16_t iPhysExtFreeHead;
1739 /** The number of user nodes we've allocated. */
1740 uint16_t cMaxPhysExts;
1741 /** Pointer to the array of physical xref extent - RC pointer. */
1742 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1743 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1744 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1745 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
1746 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1747#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1748#ifdef PGMPOOL_WITH_CACHE
1749 /** Hash table for GCPhys addresses. */
1750 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1751 /** The head of the age list. */
1752 uint16_t iAgeHead;
1753 /** The tail of the age list. */
1754 uint16_t iAgeTail;
1755 /** Set if the cache is enabled. */
1756 bool fCacheEnabled;
1757#endif /* PGMPOOL_WITH_CACHE */
1758#ifdef PGMPOOL_WITH_MONITORING
1759 /** Head of the list of modified pages. */
1760 uint16_t iModifiedHead;
1761 /** The current number of modified pages. */
1762 uint16_t cModifiedPages;
1763 /** Access handler, RC. */
1764 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1765 /** Access handler, R0. */
1766 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1767 /** Access handler, R3. */
1768 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1769 /** The access handler description (HC ptr). */
1770 R3PTRTYPE(const char *) pszAccessHandler;
1771# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1772 /* Next available slot. */
1773 uint32_t idxFreeDirtyPage;
1774 /* Number of active dirty pages. */
1775 uint32_t cDirtyPages;
1776 /* Array of current dirty pgm pool page indices. */
1777 uint16_t aIdxDirtyPages[8];
1778 uint64_t aDirtyPages[8][512];
1779# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1780#endif /* PGMPOOL_WITH_MONITORING */
1781 /** The number of pages currently in use. */
1782 uint16_t cUsedPages;
1783#ifdef VBOX_WITH_STATISTICS
1784 /** The high water mark for cUsedPages. */
1785 uint16_t cUsedPagesHigh;
1786 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1787 /** Profiling pgmPoolAlloc(). */
1788 STAMPROFILEADV StatAlloc;
1789 /** Profiling pgmPoolClearAll(). */
1790 STAMPROFILE StatClearAll;
1791 /** Profiling pgmPoolFlushAllInt(). */
1792 STAMPROFILE StatFlushAllInt;
1793 /** Profiling pgmPoolFlushPage(). */
1794 STAMPROFILE StatFlushPage;
1795 /** Profiling pgmPoolFree(). */
1796 STAMPROFILE StatFree;
1797 /** Profiling time spent zeroing pages. */
1798 STAMPROFILE StatZeroPage;
1799# ifdef PGMPOOL_WITH_USER_TRACKING
1800 /** Profiling of pgmPoolTrackDeref. */
1801 STAMPROFILE StatTrackDeref;
1802 /** Profiling pgmTrackFlushGCPhysPT. */
1803 STAMPROFILE StatTrackFlushGCPhysPT;
1804 /** Profiling pgmTrackFlushGCPhysPTs. */
1805 STAMPROFILE StatTrackFlushGCPhysPTs;
1806 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1807 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1808 /** Number of times we've been out of user records. */
1809 STAMCOUNTER StatTrackFreeUpOneUser;
1810# endif
1811# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1812 /** Profiling deref activity related tracking GC physical pages. */
1813 STAMPROFILE StatTrackDerefGCPhys;
1814 /** Number of linear searches for a HCPhys in the ram ranges. */
1815 STAMCOUNTER StatTrackLinearRamSearches;
1816 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1817 STAMCOUNTER StamTrackPhysExtAllocFailures;
1818# endif
1819# ifdef PGMPOOL_WITH_MONITORING
1820 /** Profiling the RC/R0 access handler. */
1821 STAMPROFILE StatMonitorRZ;
1822 /** Times we've failed interpreting the instruction. */
1823 STAMCOUNTER StatMonitorRZEmulateInstr;
1824 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1825 STAMPROFILE StatMonitorRZFlushPage;
1826 /* Times we've detected a page table reinit. */
1827 STAMCOUNTER StatMonitorRZFlushReinit;
1828 /** Times we've detected fork(). */
1829 STAMCOUNTER StatMonitorRZFork;
1830 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
1831 STAMPROFILE StatMonitorRZHandled;
1832 /** Times we've failed interpreting a patch code instruction. */
1833 STAMCOUNTER StatMonitorRZIntrFailPatch1;
1834 /** Times we've failed interpreting a patch code instruction during flushing. */
1835 STAMCOUNTER StatMonitorRZIntrFailPatch2;
1836 /** The number of times we've seen rep prefixes we can't handle. */
1837 STAMCOUNTER StatMonitorRZRepPrefix;
1838 /** Profiling the REP STOSD cases we've handled. */
1839 STAMPROFILE StatMonitorRZRepStosd;
1840
1841 /** Profiling the R3 access handler. */
1842 STAMPROFILE StatMonitorR3;
1843 /** Times we've failed interpreting the instruction. */
1844 STAMCOUNTER StatMonitorR3EmulateInstr;
1845 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1846 STAMPROFILE StatMonitorR3FlushPage;
1847 /* Times we've detected a page table reinit. */
1848 STAMCOUNTER StatMonitorR3FlushReinit;
1849 /** Times we've detected fork(). */
1850 STAMCOUNTER StatMonitorR3Fork;
1851 /** Profiling the R3 access we've handled (except REP STOSD). */
1852 STAMPROFILE StatMonitorR3Handled;
1853 /** The number of times we've seen rep prefixes we can't handle. */
1854 STAMCOUNTER StatMonitorR3RepPrefix;
1855 /** Profiling the REP STOSD cases we've handled. */
1856 STAMPROFILE StatMonitorR3RepStosd;
1857 /** The number of times we're called in an async thread an need to flush. */
1858 STAMCOUNTER StatMonitorR3Async;
1859 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
1860 STAMCOUNTER StatResetDirtyPages;
1861 /** Times we've called pgmPoolAddDirtyPage. */
1862 STAMCOUNTER StatDirtyPage;
1863 /** Times we've had to flush duplicates for dirty page management. */
1864 STAMCOUNTER StatDirtyPageDupFlush;
1865
1866 /** The high wather mark for cModifiedPages. */
1867 uint16_t cModifiedPagesHigh;
1868 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1869# endif
1870# ifdef PGMPOOL_WITH_CACHE
1871 /** The number of cache hits. */
1872 STAMCOUNTER StatCacheHits;
1873 /** The number of cache misses. */
1874 STAMCOUNTER StatCacheMisses;
1875 /** The number of times we've got a conflict of 'kind' in the cache. */
1876 STAMCOUNTER StatCacheKindMismatches;
1877 /** Number of times we've been out of pages. */
1878 STAMCOUNTER StatCacheFreeUpOne;
1879 /** The number of cacheable allocations. */
1880 STAMCOUNTER StatCacheCacheable;
1881 /** The number of uncacheable allocations. */
1882 STAMCOUNTER StatCacheUncacheable;
1883# endif
1884#elif HC_ARCH_BITS == 64
1885 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1886#endif
1887 /** The AVL tree for looking up a page by its HC physical address. */
1888 AVLOHCPHYSTREE HCPhysTree;
1889 uint32_t Alignment4; /**< Align the next member on a 64-bit boundrary. */
1890 /** Array of pages. (cMaxPages in length)
1891 * The Id is the index into thist array.
1892 */
1893 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1894} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1895
1896
1897/** @def PGMPOOL_PAGE_2_PTR
1898 * Maps a pool page pool into the current context.
1899 *
1900 * @returns VBox status code.
1901 * @param pVM The VM handle.
1902 * @param pPage The pool page.
1903 *
1904 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1905 * small page window employeed by that function. Be careful.
1906 * @remark There is no need to assert on the result.
1907 */
1908#if defined(IN_RC)
1909# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1910#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1911# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage))
1912#elif defined(VBOX_STRICT)
1913# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1914DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1915{
1916 Assert(pPage && pPage->pvPageR3);
1917 return pPage->pvPageR3;
1918}
1919#else
1920# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1921#endif
1922
1923/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1924 * Maps a pool page pool into the current context.
1925 *
1926 * @returns VBox status code.
1927 * @param pPGM Pointer to the PGM instance data.
1928 * @param pPage The pool page.
1929 *
1930 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1931 * small page window employeed by that function. Be careful.
1932 * @remark There is no need to assert on the result.
1933 */
1934#if defined(IN_RC)
1935# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1936#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1937# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined(pPGM, (pPage))
1938#else
1939# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1940#endif
1941
1942/** @def PGMPOOL_PAGE_2_PTR_BY_PGMCPU
1943 * Maps a pool page pool into the current context.
1944 *
1945 * @returns VBox status code.
1946 * @param pPGM Pointer to the PGMCPU instance data.
1947 * @param pPage The pool page.
1948 *
1949 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1950 * small page window employeed by that function. Be careful.
1951 * @remark There is no need to assert on the result.
1952 */
1953#if defined(IN_RC)
1954# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1955#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1956# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) pgmPoolMapPageInlined(PGMCPU2PGM(pPGM), (pPage))
1957#else
1958# define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)
1959#endif
1960
1961
1962/** @name Per guest page tracking data.
1963 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
1964 * is to use more bits for it and split it up later on. But for now we'll play
1965 * safe and change as little as possible.
1966 *
1967 * The 16-bit word has two parts:
1968 *
1969 * The first 14-bit forms the @a idx field. It is either the index of a page in
1970 * the shadow page pool, or and index into the extent list.
1971 *
1972 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
1973 * shadow page pool references to the page. If cRefs equals
1974 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
1975 * (misnomer) table and not the shadow page pool.
1976 *
1977 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
1978 * the 16-bit word.
1979 *
1980 * @{ */
1981/** The shift count for getting to the cRefs part. */
1982#define PGMPOOL_TD_CREFS_SHIFT 14
1983/** The mask applied after shifting the tracking data down by
1984 * PGMPOOL_TD_CREFS_SHIFT. */
1985#define PGMPOOL_TD_CREFS_MASK 0x3
1986/** The cRef value used to indiciate that the idx is the head of a
1987 * physical cross reference list. */
1988#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
1989/** The shift used to get idx. */
1990#define PGMPOOL_TD_IDX_SHIFT 0
1991/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
1992#define PGMPOOL_TD_IDX_MASK 0x3fff
1993/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
1994 * simply too many mappings of this page. */
1995#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
1996
1997/** @def PGMPOOL_TD_MAKE
1998 * Makes a 16-bit tracking data word.
1999 *
2000 * @returns tracking data.
2001 * @param cRefs The @a cRefs field. Must be within bounds!
2002 * @param idx The @a idx field. Must also be within bounds! */
2003#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2004
2005/** @def PGMPOOL_TD_GET_CREFS
2006 * Get the @a cRefs field from a tracking data word.
2007 *
2008 * @returns The @a cRefs field
2009 * @param u16 The tracking data word. */
2010#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2011
2012/** @def PGMPOOL_TD_GET_IDX
2013 * Get the @a idx field from a tracking data word.
2014 *
2015 * @returns The @a idx field
2016 * @param u16 The tracking data word. */
2017#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2018/** @} */
2019
2020
2021/**
2022 * Trees are using self relative offsets as pointers.
2023 * So, all its data, including the root pointer, must be in the heap for HC and GC
2024 * to have the same layout.
2025 */
2026typedef struct PGMTREES
2027{
2028 /** Physical access handlers (AVL range+offsetptr tree). */
2029 AVLROGCPHYSTREE PhysHandlers;
2030 /** Virtual access handlers (AVL range + GC ptr tree). */
2031 AVLROGCPTRTREE VirtHandlers;
2032 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2033 AVLROGCPHYSTREE PhysToVirtHandlers;
2034 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2035 AVLROGCPTRTREE HyperVirtHandlers;
2036} PGMTREES;
2037/** Pointer to PGM trees. */
2038typedef PGMTREES *PPGMTREES;
2039
2040
2041/** @name Paging mode macros
2042 * @{ */
2043#ifdef IN_RC
2044# define PGM_CTX(a,b) a##RC##b
2045# define PGM_CTX_STR(a,b) a "GC" b
2046# define PGM_CTX_DECL(type) VMMRCDECL(type)
2047#else
2048# ifdef IN_RING3
2049# define PGM_CTX(a,b) a##R3##b
2050# define PGM_CTX_STR(a,b) a "R3" b
2051# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2052# else
2053# define PGM_CTX(a,b) a##R0##b
2054# define PGM_CTX_STR(a,b) a "R0" b
2055# define PGM_CTX_DECL(type) VMMDECL(type)
2056# endif
2057#endif
2058
2059#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2060#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2061#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2062#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2063#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2064#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2065#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2066#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2067#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2068#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2069#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2070#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2071#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2072#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2073#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2074#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2075#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2076
2077#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2078#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2079#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2080#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2081#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2082#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2083#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2084#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2085#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2086#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2087#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2088#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2089#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2090#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2091#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2092#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2093#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2094
2095/* Shw_Gst */
2096#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2097#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2098#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2099#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2100#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2101#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2102#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2103#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2104#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2105#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2106#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2107#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2108#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2109#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2110#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2111#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2112#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2113#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2114#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2115
2116#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2117#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2118#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2119#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2120#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2121#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2122#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2123#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2124#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2125#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2126#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2127#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2128#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2129#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2130#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2131#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2132#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2133#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2134#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2135#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2136#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2137#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2138#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2139#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2140#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2141#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2142#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2143#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2144#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2145#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2146#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2147#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2148#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2149#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2150#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2151#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2152#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2153
2154#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2155#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2156/** @} */
2157
2158/**
2159 * Data for each paging mode.
2160 */
2161typedef struct PGMMODEDATA
2162{
2163 /** The guest mode type. */
2164 uint32_t uGstType;
2165 /** The shadow mode type. */
2166 uint32_t uShwType;
2167
2168 /** @name Function pointers for Shadow paging.
2169 * @{
2170 */
2171 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2172 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2173 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2174 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2175
2176 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2177 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2178
2179 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2180 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2181 /** @} */
2182
2183 /** @name Function pointers for Guest paging.
2184 * @{
2185 */
2186 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2187 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2188 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2189 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2190 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2191 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2192 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2193 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2194 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2195 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2196 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2197 /** @} */
2198
2199 /** @name Function pointers for Both Shadow and Guest paging.
2200 * @{
2201 */
2202 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2203 /* no pfnR3BthTrap0eHandler */
2204 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2205 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2206 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2207 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2208 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2209#ifdef VBOX_STRICT
2210 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2211#endif
2212 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2213 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2214
2215 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2216 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2217 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2218 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2219 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2220 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2221#ifdef VBOX_STRICT
2222 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2223#endif
2224 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2225 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2226
2227 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2228 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2229 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2230 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2231 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2232 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2233#ifdef VBOX_STRICT
2234 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2235#endif
2236 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2237 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2238 /** @} */
2239} PGMMODEDATA, *PPGMMODEDATA;
2240
2241
2242
2243/**
2244 * Converts a PGM pointer into a VM pointer.
2245 * @returns Pointer to the VM structure the PGM is part of.
2246 * @param pPGM Pointer to PGM instance data.
2247 */
2248#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2249
2250/**
2251 * PGM Data (part of VM)
2252 */
2253typedef struct PGM
2254{
2255 /** Offset to the VM structure. */
2256 RTINT offVM;
2257 /** Offset of the PGMCPU structure relative to VMCPU. */
2258 RTINT offVCpuPGM;
2259
2260 /** @cfgm{RamPreAlloc, boolean, false}
2261 * Indicates whether the base RAM should all be allocated before starting
2262 * the VM (default), or if it should be allocated when first written to.
2263 */
2264 bool fRamPreAlloc;
2265 /** Alignment padding. */
2266 bool afAlignment0[11];
2267
2268 /*
2269 * This will be redefined at least two more times before we're done, I'm sure.
2270 * The current code is only to get on with the coding.
2271 * - 2004-06-10: initial version, bird.
2272 * - 2004-07-02: 1st time, bird.
2273 * - 2004-10-18: 2nd time, bird.
2274 * - 2005-07-xx: 3rd time, bird.
2275 */
2276
2277 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2278 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2279 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2280 RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2281
2282 /** The host paging mode. (This is what SUPLib reports.) */
2283 SUPPAGINGMODE enmHostMode;
2284
2285 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2286 RTGCPHYS GCPhys4MBPSEMask;
2287
2288 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2289 * This is sorted by physical address and contains no overlapping ranges. */
2290 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2291 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2292 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2293 /** RC pointer corresponding to PGM::pRamRangesR3. */
2294 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2295 RTRCPTR alignment4; /**< structure alignment. */
2296
2297 /** Pointer to the list of ROM ranges - for R3.
2298 * This is sorted by physical address and contains no overlapping ranges. */
2299 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2300 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2301 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2302 /** RC pointer corresponding to PGM::pRomRangesR3. */
2303 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2304 /** Alignment padding. */
2305 RTRCPTR GCPtrPadding2;
2306
2307 /** Pointer to the list of MMIO2 ranges - for R3.
2308 * Registration order. */
2309 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2310
2311 /** PGM offset based trees - R3 Ptr. */
2312 R3PTRTYPE(PPGMTREES) pTreesR3;
2313 /** PGM offset based trees - R0 Ptr. */
2314 R0PTRTYPE(PPGMTREES) pTreesR0;
2315 /** PGM offset based trees - RC Ptr. */
2316 RCPTRTYPE(PPGMTREES) pTreesRC;
2317
2318 /** Linked list of GC mappings - for RC.
2319 * The list is sorted ascending on address.
2320 */
2321 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2322 /** Linked list of GC mappings - for HC.
2323 * The list is sorted ascending on address.
2324 */
2325 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2326 /** Linked list of GC mappings - for R0.
2327 * The list is sorted ascending on address.
2328 */
2329 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2330
2331 /** Pointer to the 5 page CR3 content mapping.
2332 * The first page is always the CR3 (in some form) while the 4 other pages
2333 * are used of the PDs in PAE mode. */
2334 RTGCPTR GCPtrCR3Mapping;
2335#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2336 uint32_t u32Alignment;
2337#endif
2338
2339 /** Indicates that PGMR3FinalizeMappings has been called and that further
2340 * PGMR3MapIntermediate calls will be rejected. */
2341 bool fFinalizedMappings;
2342 /** If set no conflict checks are required. (boolean) */
2343 bool fMappingsFixed;
2344 /** If set, then no mappings are put into the shadow page table. (boolean) */
2345 bool fDisableMappings;
2346 /** Size of fixed mapping */
2347 uint32_t cbMappingFixed;
2348 /** Base address (GC) of fixed mapping */
2349 RTGCPTR GCPtrMappingFixed;
2350 /** The address of the previous RAM range mapping. */
2351 RTGCPTR GCPtrPrevRamRangeMapping;
2352
2353 /** @name Intermediate Context
2354 * @{ */
2355 /** Pointer to the intermediate page directory - Normal. */
2356 R3PTRTYPE(PX86PD) pInterPD;
2357 /** Pointer to the intermedate page tables - Normal.
2358 * There are two page tables, one for the identity mapping and one for
2359 * the host context mapping (of the core code). */
2360 R3PTRTYPE(PX86PT) apInterPTs[2];
2361 /** Pointer to the intermedate page tables - PAE. */
2362 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2363 /** Pointer to the intermedate page directory - PAE. */
2364 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2365 /** Pointer to the intermedate page directory - PAE. */
2366 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2367 /** Pointer to the intermedate page-map level 4 - AMD64. */
2368 R3PTRTYPE(PX86PML4) pInterPaePML4;
2369 /** Pointer to the intermedate page directory - AMD64. */
2370 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2371 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2372 RTHCPHYS HCPhysInterPD;
2373 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2374 RTHCPHYS HCPhysInterPaePDPT;
2375 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2376 RTHCPHYS HCPhysInterPaePML4;
2377 /** @} */
2378
2379 /** Base address of the dynamic page mapping area.
2380 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2381 */
2382 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2383 /** The index of the last entry used in the dynamic page mapping area. */
2384 RTUINT iDynPageMapLast;
2385 /** Cache containing the last entries in the dynamic page mapping area.
2386 * The cache size is covering half of the mapping area. */
2387 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2388 /** Keep a lock counter for the full (!) mapping area. */
2389 uint32_t aLockedDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)];
2390
2391 /** The address of the ring-0 mapping cache if we're making use of it. */
2392 RTR0PTR pvR0DynMapUsed;
2393
2394 /** PGM critical section.
2395 * This protects the physical & virtual access handlers, ram ranges,
2396 * and the page flag updating (some of it anyway).
2397 */
2398 PDMCRITSECT CritSect;
2399
2400 /** Pointer to SHW+GST mode data (function pointers).
2401 * The index into this table is made up from */
2402 R3PTRTYPE(PPGMMODEDATA) paModeData;
2403
2404 /** Shadow Page Pool - R3 Ptr. */
2405 R3PTRTYPE(PPGMPOOL) pPoolR3;
2406 /** Shadow Page Pool - R0 Ptr. */
2407 R0PTRTYPE(PPGMPOOL) pPoolR0;
2408 /** Shadow Page Pool - RC Ptr. */
2409 RCPTRTYPE(PPGMPOOL) pPoolRC;
2410
2411 /** We're not in a state which permits writes to guest memory.
2412 * (Only used in strict builds.) */
2413 bool fNoMorePhysWrites;
2414
2415 /**
2416 * Data associated with managing the ring-3 mappings of the allocation chunks.
2417 */
2418 struct
2419 {
2420 /** The chunk tree, ordered by chunk id. */
2421#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2422 R3PTRTYPE(PAVLU32NODECORE) pTree;
2423#else
2424 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2425#endif
2426 /** The chunk mapping TLB. */
2427 PGMCHUNKR3MAPTLB Tlb;
2428 /** The number of mapped chunks. */
2429 uint32_t c;
2430 /** The maximum number of mapped chunks.
2431 * @cfgm PGM/MaxRing3Chunks */
2432 uint32_t cMax;
2433 /** The chunk age tree, ordered by ageing sequence number. */
2434 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2435 /** The current time. */
2436 uint32_t iNow;
2437 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2438 uint32_t AgeingCountdown;
2439 } ChunkR3Map;
2440
2441 /**
2442 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2443 */
2444 PGMPAGER3MAPTLB PhysTlbHC;
2445
2446 /** @name The zero page.
2447 * @{ */
2448 /** The host physical address of the zero page. */
2449 RTHCPHYS HCPhysZeroPg;
2450 /** The ring-3 mapping of the zero page. */
2451 RTR3PTR pvZeroPgR3;
2452 /** The ring-0 mapping of the zero page. */
2453 RTR0PTR pvZeroPgR0;
2454 /** The GC mapping of the zero page. */
2455 RTGCPTR pvZeroPgRC;
2456#if GC_ARCH_BITS != 32
2457 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2458#endif
2459 /** @}*/
2460
2461 /** The number of handy pages. */
2462 uint32_t cHandyPages;
2463 /**
2464 * Array of handy pages.
2465 *
2466 * This array is used in a two way communication between pgmPhysAllocPage
2467 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2468 * an intermediary.
2469 *
2470 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2471 * (The current size of 32 pages, means 128 KB of handy memory.)
2472 */
2473 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
2474
2475 /** @name Error injection.
2476 * @{ */
2477 /** Inject handy page allocation errors pretending we're completely out of
2478 * memory. */
2479 bool volatile fErrInjHandyPages;
2480 /** Padding. */
2481 bool afReserved[7];
2482 /** @} */
2483
2484 /** @name Release Statistics
2485 * @{ */
2486 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2487 uint32_t cPrivatePages; /**< The number of private pages. */
2488 uint32_t cSharedPages; /**< The number of shared pages. */
2489 uint32_t cZeroPages; /**< The number of zero backed pages. */
2490
2491 /** The number of times we were forced to change the hypervisor region location. */
2492 STAMCOUNTER cRelocations;
2493 /** @} */
2494
2495#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2496 /* R3 only: */
2497 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2498 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2499
2500 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2501 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2502 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2503 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2504 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2505 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2506 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2507 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2508 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2509 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2510 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2511 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2512 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2513 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2514 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2515 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2516 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2517 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2518/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2519 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2520 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2521/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2522
2523 /* RC only: */
2524 STAMCOUNTER StatRCDynMapCacheMisses; /**< RC: The number of dynamic page mapping cache misses */
2525 STAMCOUNTER StatRCDynMapCacheHits; /**< RC: The number of dynamic page mapping cache hits */
2526 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2527 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2528
2529 STAMCOUNTER StatRZPhysRead;
2530 STAMCOUNTER StatRZPhysReadBytes;
2531 STAMCOUNTER StatRZPhysWrite;
2532 STAMCOUNTER StatRZPhysWriteBytes;
2533 STAMCOUNTER StatR3PhysRead;
2534 STAMCOUNTER StatR3PhysReadBytes;
2535 STAMCOUNTER StatR3PhysWrite;
2536 STAMCOUNTER StatR3PhysWriteBytes;
2537 STAMCOUNTER StatRCPhysRead;
2538 STAMCOUNTER StatRCPhysReadBytes;
2539 STAMCOUNTER StatRCPhysWrite;
2540 STAMCOUNTER StatRCPhysWriteBytes;
2541
2542 STAMCOUNTER StatRZPhysSimpleRead;
2543 STAMCOUNTER StatRZPhysSimpleReadBytes;
2544 STAMCOUNTER StatRZPhysSimpleWrite;
2545 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2546 STAMCOUNTER StatR3PhysSimpleRead;
2547 STAMCOUNTER StatR3PhysSimpleReadBytes;
2548 STAMCOUNTER StatR3PhysSimpleWrite;
2549 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2550 STAMCOUNTER StatRCPhysSimpleRead;
2551 STAMCOUNTER StatRCPhysSimpleReadBytes;
2552 STAMCOUNTER StatRCPhysSimpleWrite;
2553 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2554
2555# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2556 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2557 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2558 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2559 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2560 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2561 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2562# endif
2563#endif
2564} PGM;
2565/** Pointer to the PGM instance data. */
2566typedef PGM *PPGM;
2567
2568
2569/**
2570 * Converts a PGMCPU pointer into a VM pointer.
2571 * @returns Pointer to the VM structure the PGM is part of.
2572 * @param pPGM Pointer to PGMCPU instance data.
2573 */
2574#define PGMCPU2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2575
2576/**
2577 * Converts a PGMCPU pointer into a PGM pointer.
2578 * @returns Pointer to the VM structure the PGM is part of.
2579 * @param pPGM Pointer to PGMCPU instance data.
2580 */
2581#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
2582
2583/**
2584 * PGMCPU Data (part of VMCPU).
2585 */
2586typedef struct PGMCPU
2587{
2588 /** Offset to the VM structure. */
2589 RTINT offVM;
2590 /** Offset to the VMCPU structure. */
2591 RTINT offVCpu;
2592 /** Offset of the PGM structure relative to VMCPU. */
2593 RTINT offPGM;
2594 RTINT uPadding0; /**< structure size alignment. */
2595
2596#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2597 /** Automatically tracked physical memory mapping set.
2598 * Ring-0 and strict raw-mode builds. */
2599 PGMMAPSET AutoSet;
2600#endif
2601
2602 /** A20 gate mask.
2603 * Our current approach to A20 emulation is to let REM do it and don't bother
2604 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2605 * But whould need arrise, we'll subject physical addresses to this mask. */
2606 RTGCPHYS GCPhysA20Mask;
2607 /** A20 gate state - boolean! */
2608 bool fA20Enabled;
2609
2610 /** What needs syncing (PGM_SYNC_*).
2611 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2612 * PGMFlushTLB, and PGMR3Load. */
2613 RTUINT fSyncFlags;
2614
2615 /** The shadow paging mode. */
2616 PGMMODE enmShadowMode;
2617 /** The guest paging mode. */
2618 PGMMODE enmGuestMode;
2619
2620 /** The current physical address representing in the guest CR3 register. */
2621 RTGCPHYS GCPhysCR3;
2622
2623 /** @name 32-bit Guest Paging.
2624 * @{ */
2625 /** The guest's page directory, R3 pointer. */
2626 R3PTRTYPE(PX86PD) pGst32BitPdR3;
2627#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2628 /** The guest's page directory, R0 pointer. */
2629 R0PTRTYPE(PX86PD) pGst32BitPdR0;
2630#endif
2631 /** The guest's page directory, static RC mapping. */
2632 RCPTRTYPE(PX86PD) pGst32BitPdRC;
2633 /** @} */
2634
2635 /** @name PAE Guest Paging.
2636 * @{ */
2637 /** The guest's page directory pointer table, static RC mapping. */
2638 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2639 /** The guest's page directory pointer table, R3 pointer. */
2640 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2641#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2642 /** The guest's page directory pointer table, R0 pointer. */
2643 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2644#endif
2645
2646 /** The guest's page directories, R3 pointers.
2647 * These are individual pointers and don't have to be adjecent.
2648 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2649 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2650 /** The guest's page directories, R0 pointers.
2651 * Same restrictions as apGstPaePDsR3. */
2652#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2653 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2654#endif
2655 /** The guest's page directories, static GC mapping.
2656 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2657 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2658 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2659 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2660 RTGCPHYS aGCPhysGstPaePDs[4];
2661 /** The physical addresses of the monitored guest page directories (PAE). */
2662 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2663 /** @} */
2664
2665 /** @name AMD64 Guest Paging.
2666 * @{ */
2667 /** The guest's page directory pointer table, R3 pointer. */
2668 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2669#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2670 /** The guest's page directory pointer table, R0 pointer. */
2671 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2672#endif
2673 /** @} */
2674
2675 /** Pointer to the page of the current active CR3 - R3 Ptr. */
2676 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2677 /** Pointer to the page of the current active CR3 - R0 Ptr. */
2678 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2679 /** Pointer to the page of the current active CR3 - RC Ptr. */
2680 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2681 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
2682 uint32_t iShwUser;
2683 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
2684 uint32_t iShwUserTable;
2685# if HC_ARCH_BITS == 64
2686 RTRCPTR alignment6; /**< structure size alignment. */
2687# endif
2688 /** @} */
2689
2690 /** @name Function pointers for Shadow paging.
2691 * @{
2692 */
2693 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2694 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2695 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2696 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2697
2698 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2699 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2700
2701 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2702 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2703
2704 /** @} */
2705
2706 /** @name Function pointers for Guest paging.
2707 * @{
2708 */
2709 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2710 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2711 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2712 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2713 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2714 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2715 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2716 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2717#if HC_ARCH_BITS == 64
2718 RTRCPTR alignment3; /**< structure size alignment. */
2719#endif
2720
2721 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2722 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2723 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2724 /** @} */
2725
2726 /** @name Function pointers for Both Shadow and Guest paging.
2727 * @{
2728 */
2729 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2730 /* no pfnR3BthTrap0eHandler */
2731 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2732 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2733 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2734 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2735 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2736 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2737 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2738 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2739
2740 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2741 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2742 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2743 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2744 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2745 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2746 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2747 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2748 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2749
2750 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2751 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2752 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2753 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2754 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2755 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2756 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2757 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2758 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2759#if HC_ARCH_BITS == 64
2760 RTRCPTR alignment2; /**< structure size alignment. */
2761#endif
2762 /** @} */
2763
2764 /** For saving stack space, the disassembler state is allocated here instead of
2765 * on the stack.
2766 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
2767 union
2768 {
2769 /** The disassembler scratch space. */
2770 DISCPUSTATE DisState;
2771 /** Padding. */
2772 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
2773 };
2774
2775 /* Count the number of pgm pool access handler calls. */
2776 uint64_t cPoolAccessHandler;
2777
2778 /** @name Release Statistics
2779 * @{ */
2780 /** The number of times the guest has switched mode since last reset or statistics reset. */
2781 STAMCOUNTER cGuestModeChanges;
2782 /** @} */
2783
2784#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2785 /** @name Statistics
2786 * @{ */
2787 /** RC: Which statistic this \#PF should be attributed to. */
2788 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2789 RTRCPTR padding0;
2790 /** R0: Which statistic this \#PF should be attributed to. */
2791 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2792 RTR0PTR padding1;
2793
2794 /* Common */
2795 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
2796 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
2797
2798 /* R0 only: */
2799 STAMCOUNTER StatR0DynMapMigrateInvlPg; /**< R0: invlpg in PGMDynMapMigrateAutoSet. */
2800 STAMPROFILE StatR0DynMapGCPageInl; /**< R0: Calls to pgmR0DynMapGCPageInlined. */
2801 STAMCOUNTER StatR0DynMapGCPageInlHits; /**< R0: Hash table lookup hits. */
2802 STAMCOUNTER StatR0DynMapGCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2803 STAMCOUNTER StatR0DynMapGCPageInlRamHits; /**< R0: 1st ram range hits. */
2804 STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /**< R0: 1st ram range misses, takes slow path. */
2805 STAMPROFILE StatR0DynMapHCPageInl; /**< R0: Calls to pgmR0DynMapHCPageInlined. */
2806 STAMCOUNTER StatR0DynMapHCPageInlHits; /**< R0: Hash table lookup hits. */
2807 STAMCOUNTER StatR0DynMapHCPageInlMisses; /**< R0: Misses that falls back to code common with PGMDynMapHCPage. */
2808 STAMPROFILE StatR0DynMapHCPage; /**< R0: Calls to PGMDynMapHCPage. */
2809 STAMCOUNTER StatR0DynMapSetOptimize; /**< R0: Calls to pgmDynMapOptimizeAutoSet. */
2810 STAMCOUNTER StatR0DynMapSetSearchFlushes; /**< R0: Set search restorting to subset flushes. */
2811 STAMCOUNTER StatR0DynMapSetSearchHits; /**< R0: Set search hits. */
2812 STAMCOUNTER StatR0DynMapSetSearchMisses; /**< R0: Set search misses. */
2813 STAMCOUNTER StatR0DynMapPage; /**< R0: Calls to pgmR0DynMapPage. */
2814 STAMCOUNTER StatR0DynMapPageHits0; /**< R0: Hits at iPage+0. */
2815 STAMCOUNTER StatR0DynMapPageHits1; /**< R0: Hits at iPage+1. */
2816 STAMCOUNTER StatR0DynMapPageHits2; /**< R0: Hits at iPage+2. */
2817 STAMCOUNTER StatR0DynMapPageInvlPg; /**< R0: invlpg. */
2818 STAMCOUNTER StatR0DynMapPageSlow; /**< R0: Calls to pgmR0DynMapPageSlow. */
2819 STAMCOUNTER StatR0DynMapPageSlowLoopHits; /**< R0: Hits in the pgmR0DynMapPageSlow search loop. */
2820 STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /**< R0: Misses in the pgmR0DynMapPageSlow search loop. */
2821 //STAMCOUNTER StatR0DynMapPageSlowLostHits; /**< R0: Lost hits. */
2822 STAMCOUNTER StatR0DynMapSubsets; /**< R0: Times PGMDynMapPushAutoSubset was called. */
2823 STAMCOUNTER StatR0DynMapPopFlushes; /**< R0: Times PGMDynMapPopAutoSubset flushes the subset. */
2824 STAMCOUNTER aStatR0DynMapSetSize[11]; /**< R0: Set size distribution. */
2825
2826 /* RZ only: */
2827 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
2828 STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2829 STAMPROFILE StatRZTrap0eTimeSyncPT;
2830 STAMPROFILE StatRZTrap0eTimeMapping;
2831 STAMPROFILE StatRZTrap0eTimeOutOfSync;
2832 STAMPROFILE StatRZTrap0eTimeHandlers;
2833 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
2834 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2835 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
2836 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
2837 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2838 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2839 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
2840 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2841 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2842 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2843 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2844 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2845 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
2846 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
2847 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
2848 STAMCOUNTER StatRZTrap0eHandlersPhysical; /**< RC/R0: Number of traps due to physical access handlers. */
2849 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
2850 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
2851 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2852 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
2853 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
2854 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: #PF err kind */
2855 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: #PF err kind */
2856 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: #PF err kind */
2857 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: #PF err kind */
2858 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: #PF err kind */
2859 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: #PF err kind */
2860 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: #PF err kind */
2861 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: #PF err kind */
2862 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: #PF err kind */
2863 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: #PF err kind */
2864 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: #PF err kind */
2865 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest #PFs. */
2866 STAMCOUNTER StatRZTrap0eGuestPFUnh; /**< RC/R0: Real guest #PF ending up at the end of the #PF code. */
2867 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest #PF to HMA or other mapping. */
2868 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
2869 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
2870 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the #PFs. */
2871 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
2872 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
2873 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
2874 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
2875 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
2876
2877 /* HC - R3 and (maybe) R0: */
2878
2879 /* RZ & R3: */
2880 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
2881 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
2882 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
2883 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
2884 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
2885 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
2886 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
2887 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
2888 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
2889 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
2890 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
2891 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
2892 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
2893 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
2894 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2895 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
2896 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
2897 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
2898 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2899 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
2900 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
2901 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
2902 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
2903 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
2904 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
2905 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
2906 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
2907 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
2908 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
2909 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
2910 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2911 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2912 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
2913 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2914 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2915 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2916 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2917 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
2918 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
2919 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2920 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2921 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2922 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2923 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
2924
2925 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
2926 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
2927 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
2928 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
2929 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
2930 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
2931 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
2932 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
2933 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
2934 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
2935 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
2936 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
2937 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
2938 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
2939 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2940 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
2941 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
2942 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
2943 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2944 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
2945 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
2946 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
2947 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
2948 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
2949 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
2950 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
2951 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
2952 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
2953 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
2954 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
2955 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
2956 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
2957 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
2958 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2959 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. */
2960 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. */
2961 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
2962 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
2963 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2964 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2965 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2966 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2967 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
2968 /** @} */
2969#endif /* VBOX_WITH_STATISTICS */
2970} PGMCPU;
2971/** Pointer to the per-cpu PGM data. */
2972typedef PGMCPU *PPGMCPU;
2973
2974
2975/** @name PGM::fSyncFlags Flags
2976 * @{
2977 */
2978/** Updates the virtual access handler state bit in PGMPAGE. */
2979#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2980/** Always sync CR3. */
2981#define PGM_SYNC_ALWAYS RT_BIT(1)
2982/** Check monitoring on next CR3 (re)load and invalidate page.
2983 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
2984#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2985/** Check guest mapping in SyncCR3. */
2986#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2987/** Clear the page pool (a light weight flush). */
2988#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
2989#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
2990/** @} */
2991
2992
2993RT_C_DECLS_BEGIN
2994
2995int pgmLock(PVM pVM);
2996void pgmUnlock(PVM pVM);
2997
2998int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2999int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3000PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3001void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
3002DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3003
3004void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3005bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3006void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage);
3007int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3008DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3009#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3010void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3011#else
3012# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3013#endif
3014DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3015
3016
3017int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3018int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3019int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3020int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3021int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3022int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
3023int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3024int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3025int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3026VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3027#ifdef IN_RING3
3028void pgmR3PhysRelinkRamRanges(PVM pVM);
3029int pgmR3PhysRamPreAllocate(PVM pVM);
3030int pgmR3PhysRamReset(PVM pVM);
3031int pgmR3PhysRomReset(PVM pVM);
3032int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3033
3034int pgmR3PoolInit(PVM pVM);
3035void pgmR3PoolRelocate(PVM pVM);
3036void pgmR3PoolReset(PVM pVM);
3037
3038#endif /* IN_RING3 */
3039#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3040int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
3041#endif
3042int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false);
3043
3044DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage = false)
3045{
3046 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, ppPage, fLockPage);
3047}
3048
3049void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3050void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3051int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3052void pgmPoolClearAll(PVM pVM);
3053PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3054int pgmPoolSyncCR3(PVMCPU pVCpu);
3055int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs);
3056uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
3057void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
3058void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
3059#ifdef PGMPOOL_WITH_MONITORING
3060void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu);
3061int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3062void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3063#endif
3064
3065void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3066void pgmPoolResetDirtyPages(PVM pVM, bool fForceRemoval = false);
3067
3068int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3069int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3070
3071void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3072void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3073int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3074int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3075
3076int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3077#ifndef IN_RC
3078int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
3079#endif
3080int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
3081
3082PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM);
3083PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
3084PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
3085PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM);
3086
3087RT_C_DECLS_END
3088
3089
3090/**
3091 * Gets the PGMRAMRANGE structure for a guest page.
3092 *
3093 * @returns Pointer to the RAM range on success.
3094 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3095 *
3096 * @param pPGM PGM handle.
3097 * @param GCPhys The GC physical address.
3098 */
3099DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
3100{
3101 /*
3102 * Optimize for the first range.
3103 */
3104 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3105 RTGCPHYS off = GCPhys - pRam->GCPhys;
3106 if (RT_UNLIKELY(off >= pRam->cb))
3107 {
3108 do
3109 {
3110 pRam = pRam->CTX_SUFF(pNext);
3111 if (RT_UNLIKELY(!pRam))
3112 break;
3113 off = GCPhys - pRam->GCPhys;
3114 } while (off >= pRam->cb);
3115 }
3116 return pRam;
3117}
3118
3119
3120/**
3121 * Gets the PGMPAGE structure for a guest page.
3122 *
3123 * @returns Pointer to the page on success.
3124 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3125 *
3126 * @param pPGM PGM handle.
3127 * @param GCPhys The GC physical address.
3128 */
3129DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3130{
3131 /*
3132 * Optimize for the first range.
3133 */
3134 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3135 RTGCPHYS off = GCPhys - pRam->GCPhys;
3136 if (RT_UNLIKELY(off >= pRam->cb))
3137 {
3138 do
3139 {
3140 pRam = pRam->CTX_SUFF(pNext);
3141 if (RT_UNLIKELY(!pRam))
3142 return NULL;
3143 off = GCPhys - pRam->GCPhys;
3144 } while (off >= pRam->cb);
3145 }
3146 return &pRam->aPages[off >> PAGE_SHIFT];
3147}
3148
3149
3150/**
3151 * Gets the PGMPAGE structure for a guest page.
3152 *
3153 * Old Phys code: Will make sure the page is present.
3154 *
3155 * @returns VBox status code.
3156 * @retval VINF_SUCCESS and a valid *ppPage on success.
3157 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3158 *
3159 * @param pPGM PGM handle.
3160 * @param GCPhys The GC physical address.
3161 * @param ppPage Where to store the page poitner on success.
3162 */
3163DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3164{
3165 /*
3166 * Optimize for the first range.
3167 */
3168 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3169 RTGCPHYS off = GCPhys - pRam->GCPhys;
3170 if (RT_UNLIKELY(off >= pRam->cb))
3171 {
3172 do
3173 {
3174 pRam = pRam->CTX_SUFF(pNext);
3175 if (RT_UNLIKELY(!pRam))
3176 {
3177 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
3178 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3179 }
3180 off = GCPhys - pRam->GCPhys;
3181 } while (off >= pRam->cb);
3182 }
3183 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3184 return VINF_SUCCESS;
3185}
3186
3187
3188
3189
3190/**
3191 * Gets the PGMPAGE structure for a guest page.
3192 *
3193 * Old Phys code: Will make sure the page is present.
3194 *
3195 * @returns VBox status code.
3196 * @retval VINF_SUCCESS and a valid *ppPage on success.
3197 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3198 *
3199 * @param pPGM PGM handle.
3200 * @param GCPhys The GC physical address.
3201 * @param ppPage Where to store the page poitner on success.
3202 * @param ppRamHint Where to read and store the ram list hint.
3203 * The caller initializes this to NULL before the call.
3204 */
3205DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3206{
3207 RTGCPHYS off;
3208 PPGMRAMRANGE pRam = *ppRamHint;
3209 if ( !pRam
3210 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3211 {
3212 pRam = pPGM->CTX_SUFF(pRamRanges);
3213 off = GCPhys - pRam->GCPhys;
3214 if (RT_UNLIKELY(off >= pRam->cb))
3215 {
3216 do
3217 {
3218 pRam = pRam->CTX_SUFF(pNext);
3219 if (RT_UNLIKELY(!pRam))
3220 {
3221 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
3222 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3223 }
3224 off = GCPhys - pRam->GCPhys;
3225 } while (off >= pRam->cb);
3226 }
3227 *ppRamHint = pRam;
3228 }
3229 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3230 return VINF_SUCCESS;
3231}
3232
3233
3234/**
3235 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3236 *
3237 * @returns Pointer to the page on success.
3238 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3239 *
3240 * @param pPGM PGM handle.
3241 * @param GCPhys The GC physical address.
3242 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
3243 */
3244DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3245{
3246 /*
3247 * Optimize for the first range.
3248 */
3249 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3250 RTGCPHYS off = GCPhys - pRam->GCPhys;
3251 if (RT_UNLIKELY(off >= pRam->cb))
3252 {
3253 do
3254 {
3255 pRam = pRam->CTX_SUFF(pNext);
3256 if (RT_UNLIKELY(!pRam))
3257 return NULL;
3258 off = GCPhys - pRam->GCPhys;
3259 } while (off >= pRam->cb);
3260 }
3261 *ppRam = pRam;
3262 return &pRam->aPages[off >> PAGE_SHIFT];
3263}
3264
3265
3266/**
3267 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3268 *
3269 * @returns Pointer to the page on success.
3270 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3271 *
3272 * @param pPGM PGM handle.
3273 * @param GCPhys The GC physical address.
3274 * @param ppPage Where to store the pointer to the PGMPAGE structure.
3275 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3276 */
3277DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3278{
3279 /*
3280 * Optimize for the first range.
3281 */
3282 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3283 RTGCPHYS off = GCPhys - pRam->GCPhys;
3284 if (RT_UNLIKELY(off >= pRam->cb))
3285 {
3286 do
3287 {
3288 pRam = pRam->CTX_SUFF(pNext);
3289 if (RT_UNLIKELY(!pRam))
3290 {
3291 *ppRam = NULL; /* Shut up silly GCC warnings. */
3292 *ppPage = NULL; /* ditto */
3293 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3294 }
3295 off = GCPhys - pRam->GCPhys;
3296 } while (off >= pRam->cb);
3297 }
3298 *ppRam = pRam;
3299 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3300 return VINF_SUCCESS;
3301}
3302
3303
3304/**
3305 * Convert GC Phys to HC Phys.
3306 *
3307 * @returns VBox status.
3308 * @param pPGM PGM handle.
3309 * @param GCPhys The GC physical address.
3310 * @param pHCPhys Where to store the corresponding HC physical address.
3311 *
3312 * @deprecated Doesn't deal with zero, shared or write monitored pages.
3313 * Avoid when writing new code!
3314 */
3315DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3316{
3317 PPGMPAGE pPage;
3318 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3319 if (RT_FAILURE(rc))
3320 return rc;
3321 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
3322 return VINF_SUCCESS;
3323}
3324
3325#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3326
3327/**
3328 * Inlined version of the ring-0 version of PGMDynMapHCPage that
3329 * optimizes access to pages already in the set.
3330 *
3331 * @returns VINF_SUCCESS. Will bail out to ring-3 on failure.
3332 * @param pPGM Pointer to the PVM instance data.
3333 * @param HCPhys The physical address of the page.
3334 * @param ppv Where to store the mapping address.
3335 */
3336DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3337{
3338 PVM pVM = PGM2VM(pPGM);
3339 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3340 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3341
3342 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapHCPageInl, a);
3343 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3344 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3345
3346 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3347 unsigned iEntry = pSet->aiHashTable[iHash];
3348 if ( iEntry < pSet->cEntries
3349 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3350 {
3351 *ppv = pSet->aEntries[iEntry].pvPage;
3352 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlHits);
3353 }
3354 else
3355 {
3356 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapHCPageInlMisses);
3357 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3358 }
3359
3360 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapHCPageInl, a);
3361 return VINF_SUCCESS;
3362}
3363
3364
3365/**
3366 * Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3367 * access to pages already in the set.
3368 *
3369 * @returns See PGMDynMapGCPage.
3370 * @param pPGM Pointer to the PVM instance data.
3371 * @param HCPhys The physical address of the page.
3372 * @param ppv Where to store the mapping address.
3373 */
3374DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3375{
3376 PVM pVM = PGM2VM(pPGM);
3377 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3378
3379 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3380 AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys));
3381
3382 /*
3383 * Get the ram range.
3384 */
3385 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3386 RTGCPHYS off = GCPhys - pRam->GCPhys;
3387 if (RT_UNLIKELY(off >= pRam->cb
3388 /** @todo || page state stuff */))
3389 {
3390 /* This case is not counted into StatR0DynMapGCPageInl. */
3391 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3392 return PGMDynMapGCPage(pVM, GCPhys, ppv);
3393 }
3394
3395 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3396 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3397
3398 /*
3399 * pgmR0DynMapHCPageInlined with out stats.
3400 */
3401 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3402 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3403 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3404
3405 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3406 unsigned iEntry = pSet->aiHashTable[iHash];
3407 if ( iEntry < pSet->cEntries
3408 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3409 {
3410 *ppv = pSet->aEntries[iEntry].pvPage;
3411 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3412 }
3413 else
3414 {
3415 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3416 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3417 }
3418
3419 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3420 return VINF_SUCCESS;
3421}
3422
3423
3424/**
3425 * Inlined version of the ring-0 version of PGMDynMapGCPageOff that optimizes
3426 * access to pages already in the set.
3427 *
3428 * @returns See PGMDynMapGCPage.
3429 * @param pPGM Pointer to the PVM instance data.
3430 * @param HCPhys The physical address of the page.
3431 * @param ppv Where to store the mapping address.
3432 */
3433DECLINLINE(int) pgmR0DynMapGCPageOffInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3434{
3435 PVM pVM = PGM2VM(pPGM);
3436 PPGMCPU pPGMCPU = (PPGMCPU)((uint8_t *)VMMGetCpu(pVM) + pPGM->offVCpuPGM); /* very pretty ;-) */
3437
3438 STAM_PROFILE_START(&pPGMCPU->StatR0DynMapGCPageInl, a);
3439
3440 /*
3441 * Get the ram range.
3442 */
3443 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3444 RTGCPHYS off = GCPhys - pRam->GCPhys;
3445 if (RT_UNLIKELY(off >= pRam->cb
3446 /** @todo || page state stuff */))
3447 {
3448 /* This case is not counted into StatR0DynMapGCPageInl. */
3449 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamMisses);
3450 return PGMDynMapGCPageOff(pVM, GCPhys, ppv);
3451 }
3452
3453 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3454 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlRamHits);
3455
3456 /*
3457 * pgmR0DynMapHCPageInlined with out stats.
3458 */
3459 PPGMMAPSET pSet = &pPGMCPU->AutoSet;
3460 Assert(!(HCPhys & PAGE_OFFSET_MASK));
3461 Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3462
3463 unsigned iHash = PGMMAPSET_HASH(HCPhys);
3464 unsigned iEntry = pSet->aiHashTable[iHash];
3465 if ( iEntry < pSet->cEntries
3466 && pSet->aEntries[iEntry].HCPhys == HCPhys)
3467 {
3468 *ppv = (void *)((uintptr_t)pSet->aEntries[iEntry].pvPage | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3469 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlHits);
3470 }
3471 else
3472 {
3473 STAM_COUNTER_INC(&pPGMCPU->StatR0DynMapGCPageInlMisses);
3474 pgmR0DynMapHCPageCommon(pVM, pSet, HCPhys, ppv);
3475 *ppv = (void *)((uintptr_t)*ppv | (PAGE_OFFSET_MASK & (uintptr_t)GCPhys));
3476 }
3477
3478 STAM_PROFILE_STOP(&pPGMCPU->StatR0DynMapGCPageInl, a);
3479 return VINF_SUCCESS;
3480}
3481
3482#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3483#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3484
3485/**
3486 * Maps the page into current context (RC and maybe R0).
3487 *
3488 * @returns pointer to the mapping.
3489 * @param pVM Pointer to the PGM instance data.
3490 * @param pPage The page.
3491 */
3492DECLINLINE(void *) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage)
3493{
3494 if (pPage->idx >= PGMPOOL_IDX_FIRST)
3495 {
3496 Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
3497 void *pv;
3498# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3499 pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
3500# else
3501 PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
3502# endif
3503 return pv;
3504 }
3505 AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
3506}
3507
3508/**
3509 * Temporarily maps one host page specified by HC physical address, returning
3510 * pointer within the page.
3511 *
3512 * Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
3513 * reused after 8 mappings (or perhaps a few more if you score with the cache).
3514 *
3515 * @returns The address corresponding to HCPhys.
3516 * @param pPGM Pointer to the PVM instance data.
3517 * @param HCPhys HC Physical address of the page.
3518 */
3519DECLINLINE(void *) pgmDynMapHCPageOff(PPGM pPGM, RTHCPHYS HCPhys)
3520{
3521 void *pv;
3522# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3523 pgmR0DynMapHCPageInlined(pPGM, HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3524# else
3525 PGMDynMapHCPage(PGM2VM(pPGM), HCPhys & ~(RTHCPHYS)PAGE_OFFSET_MASK, &pv);
3526# endif
3527 pv = (void *)((uintptr_t)pv | (HCPhys & PAGE_OFFSET_MASK));
3528 return pv;
3529}
3530
3531#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 || IN_RC */
3532#ifndef IN_RC
3533
3534/**
3535 * Queries the Physical TLB entry for a physical guest page,
3536 * attempting to load the TLB entry if necessary.
3537 *
3538 * @returns VBox status code.
3539 * @retval VINF_SUCCESS on success
3540 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3541 *
3542 * @param pPGM The PGM instance handle.
3543 * @param GCPhys The address of the guest page.
3544 * @param ppTlbe Where to store the pointer to the TLB entry.
3545 */
3546DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3547{
3548 int rc;
3549 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3550 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3551 {
3552 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3553 rc = VINF_SUCCESS;
3554 }
3555 else
3556 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3557 *ppTlbe = pTlbe;
3558 return rc;
3559}
3560
3561
3562/**
3563 * Queries the Physical TLB entry for a physical guest page,
3564 * attempting to load the TLB entry if necessary.
3565 *
3566 * @returns VBox status code.
3567 * @retval VINF_SUCCESS on success
3568 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3569 *
3570 * @param pPGM The PGM instance handle.
3571 * @param pPage Pointer to the PGMPAGE structure corresponding to
3572 * GCPhys.
3573 * @param GCPhys The address of the guest page.
3574 * @param ppTlbe Where to store the pointer to the TLB entry.
3575 */
3576DECLINLINE(int) pgmPhysPageQueryTlbeWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3577{
3578 int rc;
3579 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3580 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3581 {
3582 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3583 rc = VINF_SUCCESS;
3584 }
3585 else
3586 rc = pgmPhysPageLoadIntoTlbWithPage(pPGM, pPage, GCPhys);
3587 *ppTlbe = pTlbe;
3588 return rc;
3589}
3590
3591#endif /* !IN_RC */
3592
3593/**
3594 * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3595 * Takes PSE-36 into account.
3596 *
3597 * @returns guest physical address
3598 * @param pPGM Pointer to the PGM instance data.
3599 * @param Pde Guest Pde
3600 */
3601DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3602{
3603 RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3604 GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3605
3606 return GCPhys & pPGM->GCPhys4MBPSEMask;
3607}
3608
3609
3610/**
3611 * Gets the page directory entry for the specified address (32-bit paging).
3612 *
3613 * @returns The page directory entry in question.
3614 * @param pPGM Pointer to the PGM instance data.
3615 * @param GCPtr The address.
3616 */
3617DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3618{
3619#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3620 PCX86PD pGuestPD = NULL;
3621 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3622 if (RT_FAILURE(rc))
3623 {
3624 X86PDE ZeroPde = {0};
3625 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3626 }
3627#else
3628 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3629# ifdef IN_RING3
3630 if (!pGuestPD)
3631 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3632# endif
3633#endif
3634 return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3635}
3636
3637
3638/**
3639 * Gets the address of a specific page directory entry (32-bit paging).
3640 *
3641 * @returns Pointer the page directory entry in question.
3642 * @param pPGM Pointer to the PGM instance data.
3643 * @param GCPtr The address.
3644 */
3645DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3646{
3647#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3648 PX86PD pGuestPD = NULL;
3649 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3650 AssertRCReturn(rc, NULL);
3651#else
3652 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3653# ifdef IN_RING3
3654 if (!pGuestPD)
3655 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3656# endif
3657#endif
3658 return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3659}
3660
3661
3662/**
3663 * Gets the address the guest page directory (32-bit paging).
3664 *
3665 * @returns Pointer the page directory entry in question.
3666 * @param pPGM Pointer to the PGM instance data.
3667 */
3668DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGMCPU pPGM)
3669{
3670#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3671 PX86PD pGuestPD = NULL;
3672 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPD);
3673 AssertRCReturn(rc, NULL);
3674#else
3675 PX86PD pGuestPD = pPGM->CTX_SUFF(pGst32BitPd);
3676# ifdef IN_RING3
3677 if (!pGuestPD)
3678 pGuestPD = pgmGstLazyMap32BitPD(pPGM);
3679# endif
3680#endif
3681 return pGuestPD;
3682}
3683
3684
3685/**
3686 * Gets the guest page directory pointer table.
3687 *
3688 * @returns Pointer to the page directory in question.
3689 * @returns NULL if the page directory is not present or on an invalid page.
3690 * @param pPGM Pointer to the PGM instance data.
3691 */
3692DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGMCPU pPGM)
3693{
3694#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3695 PX86PDPT pGuestPDPT = NULL;
3696 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3697 AssertRCReturn(rc, NULL);
3698#else
3699 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3700# ifdef IN_RING3
3701 if (!pGuestPDPT)
3702 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3703# endif
3704#endif
3705 return pGuestPDPT;
3706}
3707
3708
3709/**
3710 * Gets the guest page directory pointer table entry for the specified address.
3711 *
3712 * @returns Pointer to the page directory in question.
3713 * @returns NULL if the page directory is not present or on an invalid page.
3714 * @param pPGM Pointer to the PGM instance data.
3715 * @param GCPtr The address.
3716 */
3717DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3718{
3719 AssertGCPtr32(GCPtr);
3720
3721#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3722 PX86PDPT pGuestPDPT = 0;
3723 int rc = pgmR0DynMapGCPageOffInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3724 AssertRCReturn(rc, 0);
3725#else
3726 PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3727# ifdef IN_RING3
3728 if (!pGuestPDPT)
3729 pGuestPDPT = pgmGstLazyMapPaePDPT(pPGM);
3730# endif
3731#endif
3732 return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3733}
3734
3735
3736/**
3737 * Gets the page directory for the specified address.
3738 *
3739 * @returns Pointer to the page directory in question.
3740 * @returns NULL if the page directory is not present or on an invalid page.
3741 * @param pPGM Pointer to the PGM instance data.
3742 * @param GCPtr The address.
3743 */
3744DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGMCPU pPGM, RTGCPTR GCPtr)
3745{
3746 AssertGCPtr32(GCPtr);
3747
3748 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3749 AssertReturn(pGuestPDPT, NULL);
3750 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3751 if (pGuestPDPT->a[iPdpt].n.u1Present)
3752 {
3753#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3754 PX86PDPAE pGuestPD = NULL;
3755 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3756 AssertRCReturn(rc, NULL);
3757#else
3758 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3759 if ( !pGuestPD
3760 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3761 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3762#endif
3763 return pGuestPD;
3764 /* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3765 }
3766 return NULL;
3767}
3768
3769
3770/**
3771 * Gets the page directory entry for the specified address.
3772 *
3773 * @returns Pointer to the page directory entry in question.
3774 * @returns NULL if the page directory is not present or on an invalid page.
3775 * @param pPGM Pointer to the PGM instance data.
3776 * @param GCPtr The address.
3777 */
3778DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
3779{
3780 AssertGCPtr32(GCPtr);
3781
3782 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3783 AssertReturn(pGuestPDPT, NULL);
3784 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3785 if (pGuestPDPT->a[iPdpt].n.u1Present)
3786 {
3787 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3788#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3789 PX86PDPAE pGuestPD = NULL;
3790 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3791 AssertRCReturn(rc, NULL);
3792#else
3793 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3794 if ( !pGuestPD
3795 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3796 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3797#endif
3798 return &pGuestPD->a[iPD];
3799 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3800 }
3801 return NULL;
3802}
3803
3804
3805/**
3806 * Gets the page directory entry for the specified address.
3807 *
3808 * @returns The page directory entry in question.
3809 * @returns A non-present entry if the page directory is not present or on an invalid page.
3810 * @param pPGM Pointer to the PGM instance data.
3811 * @param GCPtr The address.
3812 */
3813DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
3814{
3815 AssertGCPtr32(GCPtr);
3816 X86PDEPAE ZeroPde = {0};
3817 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3818 if (RT_LIKELY(pGuestPDPT))
3819 {
3820 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3821 if (pGuestPDPT->a[iPdpt].n.u1Present)
3822 {
3823 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3824#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3825 PX86PDPAE pGuestPD = NULL;
3826 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3827 AssertRCReturn(rc, ZeroPde);
3828#else
3829 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3830 if ( !pGuestPD
3831 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3832 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3833#endif
3834 return pGuestPD->a[iPD];
3835 }
3836 }
3837 return ZeroPde;
3838}
3839
3840
3841/**
3842 * Gets the page directory pointer table entry for the specified address
3843 * and returns the index into the page directory
3844 *
3845 * @returns Pointer to the page directory in question.
3846 * @returns NULL if the page directory is not present or on an invalid page.
3847 * @param pPGM Pointer to the PGM instance data.
3848 * @param GCPtr The address.
3849 * @param piPD Receives the index into the returned page directory
3850 * @param pPdpe Receives the page directory pointer entry. Optional.
3851 */
3852DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3853{
3854 AssertGCPtr32(GCPtr);
3855
3856 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3857 AssertReturn(pGuestPDPT, NULL);
3858 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3859 if (pPdpe)
3860 *pPdpe = pGuestPDPT->a[iPdpt];
3861 if (pGuestPDPT->a[iPdpt].n.u1Present)
3862 {
3863 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3864#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3865 PX86PDPAE pGuestPD = NULL;
3866 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK, (void **)&pGuestPD);
3867 AssertRCReturn(rc, NULL);
3868#else
3869 PX86PDPAE pGuestPD = pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
3870 if ( !pGuestPD
3871 || (pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK) != pPGM->aGCPhysGstPaePDs[iPdpt])
3872 pGuestPD = pgmGstLazyMapPaePD(pPGM, iPdpt);
3873#endif
3874 *piPD = iPD;
3875 return pGuestPD;
3876 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3877 }
3878 return NULL;
3879}
3880
3881#ifndef IN_RC
3882
3883/**
3884 * Gets the page map level-4 pointer for the guest.
3885 *
3886 * @returns Pointer to the PML4 page.
3887 * @param pPGM Pointer to the PGM instance data.
3888 */
3889DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGMCPU pPGM)
3890{
3891#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3892 PX86PML4 pGuestPml4;
3893 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3894 AssertRCReturn(rc, NULL);
3895#else
3896 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3897# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3898 if (!pGuestPml4)
3899 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3900# endif
3901 Assert(pGuestPml4);
3902#endif
3903 return pGuestPml4;
3904}
3905
3906
3907/**
3908 * Gets the pointer to a page map level-4 entry.
3909 *
3910 * @returns Pointer to the PML4 entry.
3911 * @param pPGM Pointer to the PGM instance data.
3912 * @param iPml4 The index.
3913 */
3914DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
3915{
3916#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3917 PX86PML4 pGuestPml4;
3918 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3919 AssertRCReturn(rc, NULL);
3920#else
3921 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3922# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3923 if (!pGuestPml4)
3924 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3925# endif
3926 Assert(pGuestPml4);
3927#endif
3928 return &pGuestPml4->a[iPml4];
3929}
3930
3931
3932/**
3933 * Gets a page map level-4 entry.
3934 *
3935 * @returns The PML4 entry.
3936 * @param pPGM Pointer to the PGM instance data.
3937 * @param iPml4 The index.
3938 */
3939DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGMCPU pPGM, unsigned int iPml4)
3940{
3941#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3942 PX86PML4 pGuestPml4;
3943 int rc = pgmR0DynMapGCPageInlined(PGMCPU2PGM(pPGM), pPGM->GCPhysCR3, (void **)&pGuestPml4);
3944 if (RT_FAILURE(rc))
3945 {
3946 X86PML4E ZeroPml4e = {0};
3947 AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3948 }
3949#else
3950 PX86PML4 pGuestPml4 = pPGM->CTX_SUFF(pGstAmd64Pml4);
3951# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
3952 if (!pGuestPml4)
3953 pGuestPml4 = pgmGstLazyMapPml4(pPGM);
3954# endif
3955 Assert(pGuestPml4);
3956#endif
3957 return pGuestPml4->a[iPml4];
3958}
3959
3960
3961/**
3962 * Gets the page directory pointer entry for the specified address.
3963 *
3964 * @returns Pointer to the page directory pointer entry in question.
3965 * @returns NULL if the page directory is not present or on an invalid page.
3966 * @param pPGM Pointer to the PGM instance data.
3967 * @param GCPtr The address.
3968 * @param ppPml4e Page Map Level-4 Entry (out)
3969 */
3970DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3971{
3972 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3973 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3974 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3975 if (pPml4e->n.u1Present)
3976 {
3977 PX86PDPT pPdpt;
3978 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3979 AssertRCReturn(rc, NULL);
3980
3981 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3982 return &pPdpt->a[iPdpt];
3983 }
3984 return NULL;
3985}
3986
3987
3988/**
3989 * Gets the page directory entry for the specified address.
3990 *
3991 * @returns The page directory entry in question.
3992 * @returns A non-present entry if the page directory is not present or on an invalid page.
3993 * @param pPGM Pointer to the PGM instance data.
3994 * @param GCPtr The address.
3995 * @param ppPml4e Page Map Level-4 Entry (out)
3996 * @param pPdpe Page directory pointer table entry (out)
3997 */
3998DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3999{
4000 X86PDEPAE ZeroPde = {0};
4001 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4002 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4003 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4004 if (pPml4e->n.u1Present)
4005 {
4006 PCX86PDPT pPdptTemp;
4007 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4008 AssertRCReturn(rc, ZeroPde);
4009
4010 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4011 *pPdpe = pPdptTemp->a[iPdpt];
4012 if (pPdptTemp->a[iPdpt].n.u1Present)
4013 {
4014 PCX86PDPAE pPD;
4015 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4016 AssertRCReturn(rc, ZeroPde);
4017
4018 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4019 return pPD->a[iPD];
4020 }
4021 }
4022
4023 return ZeroPde;
4024}
4025
4026
4027/**
4028 * Gets the page directory entry for the specified address.
4029 *
4030 * @returns The page directory entry in question.
4031 * @returns A non-present entry if the page directory is not present or on an invalid page.
4032 * @param pPGM Pointer to the PGM instance data.
4033 * @param GCPtr The address.
4034 */
4035DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4036{
4037 X86PDEPAE ZeroPde = {0};
4038 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4039 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4040 if (pGuestPml4->a[iPml4].n.u1Present)
4041 {
4042 PCX86PDPT pPdptTemp;
4043 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4044 AssertRCReturn(rc, ZeroPde);
4045
4046 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4047 if (pPdptTemp->a[iPdpt].n.u1Present)
4048 {
4049 PCX86PDPAE pPD;
4050 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4051 AssertRCReturn(rc, ZeroPde);
4052
4053 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4054 return pPD->a[iPD];
4055 }
4056 }
4057 return ZeroPde;
4058}
4059
4060
4061/**
4062 * Gets the page directory entry for the specified address.
4063 *
4064 * @returns Pointer to the page directory entry in question.
4065 * @returns NULL if the page directory is not present or on an invalid page.
4066 * @param pPGM Pointer to the PGM instance data.
4067 * @param GCPtr The address.
4068 */
4069DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr)
4070{
4071 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4072 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4073 if (pGuestPml4->a[iPml4].n.u1Present)
4074 {
4075 PCX86PDPT pPdptTemp;
4076 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4077 AssertRCReturn(rc, NULL);
4078
4079 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4080 if (pPdptTemp->a[iPdpt].n.u1Present)
4081 {
4082 PX86PDPAE pPD;
4083 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4084 AssertRCReturn(rc, NULL);
4085
4086 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4087 return &pPD->a[iPD];
4088 }
4089 }
4090 return NULL;
4091}
4092
4093
4094/**
4095 * Gets the GUEST page directory pointer for the specified address.
4096 *
4097 * @returns The page directory in question.
4098 * @returns NULL if the page directory is not present or on an invalid page.
4099 * @param pPGM Pointer to the PGM instance data.
4100 * @param GCPtr The address.
4101 * @param ppPml4e Page Map Level-4 Entry (out)
4102 * @param pPdpe Page directory pointer table entry (out)
4103 * @param piPD Receives the index into the returned page directory
4104 */
4105DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
4106{
4107 PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4108 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4109 PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4110 if (pPml4e->n.u1Present)
4111 {
4112 PCX86PDPT pPdptTemp;
4113 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4114 AssertRCReturn(rc, NULL);
4115
4116 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4117 *pPdpe = pPdptTemp->a[iPdpt];
4118 if (pPdptTemp->a[iPdpt].n.u1Present)
4119 {
4120 PX86PDPAE pPD;
4121 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4122 AssertRCReturn(rc, NULL);
4123
4124 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4125 return pPD;
4126 }
4127 }
4128 return 0;
4129}
4130
4131#endif /* !IN_RC */
4132
4133/**
4134 * Gets the shadow page directory, 32-bit.
4135 *
4136 * @returns Pointer to the shadow 32-bit PD.
4137 * @param pPGM Pointer to the PGM instance data.
4138 */
4139DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGMCPU pPGM)
4140{
4141 return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4142}
4143
4144
4145/**
4146 * Gets the shadow page directory entry for the specified address, 32-bit.
4147 *
4148 * @returns Shadow 32-bit PDE.
4149 * @param pPGM Pointer to the PGM instance data.
4150 * @param GCPtr The address.
4151 */
4152DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4153{
4154 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4155
4156 PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4157 if (!pShwPde)
4158 {
4159 X86PDE ZeroPde = {0};
4160 return ZeroPde;
4161 }
4162 return pShwPde->a[iPd];
4163}
4164
4165
4166/**
4167 * Gets the pointer to the shadow page directory entry for the specified
4168 * address, 32-bit.
4169 *
4170 * @returns Pointer to the shadow 32-bit PDE.
4171 * @param pPGM Pointer to the PGM instance data.
4172 * @param GCPtr The address.
4173 */
4174DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4175{
4176 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4177
4178 PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4179 AssertReturn(pPde, NULL);
4180 return &pPde->a[iPd];
4181}
4182
4183
4184/**
4185 * Gets the shadow page pointer table, PAE.
4186 *
4187 * @returns Pointer to the shadow PAE PDPT.
4188 * @param pPGM Pointer to the PGM instance data.
4189 */
4190DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGMCPU pPGM)
4191{
4192 return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4193}
4194
4195
4196/**
4197 * Gets the shadow page directory for the specified address, PAE.
4198 *
4199 * @returns Pointer to the shadow PD.
4200 * @param pPGM Pointer to the PGM instance data.
4201 * @param GCPtr The address.
4202 */
4203DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4204{
4205 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4206 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4207
4208 if (!pPdpt->a[iPdpt].n.u1Present)
4209 return NULL;
4210
4211 /* Fetch the pgm pool shadow descriptor. */
4212 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4213 AssertReturn(pShwPde, NULL);
4214
4215 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4216}
4217
4218
4219/**
4220 * Gets the shadow page directory for the specified address, PAE.
4221 *
4222 * @returns Pointer to the shadow PD.
4223 * @param pPGM Pointer to the PGM instance data.
4224 * @param GCPtr The address.
4225 */
4226DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGMCPU pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
4227{
4228 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4229
4230 if (!pPdpt->a[iPdpt].n.u1Present)
4231 return NULL;
4232
4233 /* Fetch the pgm pool shadow descriptor. */
4234 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4235 AssertReturn(pShwPde, NULL);
4236
4237 return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pShwPde);
4238}
4239
4240
4241/**
4242 * Gets the shadow page directory entry, PAE.
4243 *
4244 * @returns PDE.
4245 * @param pPGM Pointer to the PGM instance data.
4246 * @param GCPtr The address.
4247 */
4248DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGMCPU pPGM, RTGCPTR GCPtr)
4249{
4250 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4251
4252 PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4253 if (!pShwPde)
4254 {
4255 X86PDEPAE ZeroPde = {0};
4256 return ZeroPde;
4257 }
4258 return pShwPde->a[iPd];
4259}
4260
4261
4262/**
4263 * Gets the pointer to the shadow page directory entry for an address, PAE.
4264 *
4265 * @returns Pointer to the PDE.
4266 * @param pPGM Pointer to the PGM instance data.
4267 * @param GCPtr The address.
4268 */
4269DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGMCPU pPGM, RTGCPTR GCPtr)
4270{
4271 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4272
4273 PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4274 AssertReturn(pPde, NULL);
4275 return &pPde->a[iPd];
4276}
4277
4278#ifndef IN_RC
4279
4280/**
4281 * Gets the shadow page map level-4 pointer.
4282 *
4283 * @returns Pointer to the shadow PML4.
4284 * @param pPGM Pointer to the PGM instance data.
4285 */
4286DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGMCPU pPGM)
4287{
4288 return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4289}
4290
4291
4292/**
4293 * Gets the shadow page map level-4 entry for the specified address.
4294 *
4295 * @returns The entry.
4296 * @param pPGM Pointer to the PGM instance data.
4297 * @param GCPtr The address.
4298 */
4299DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGMCPU pPGM, RTGCPTR GCPtr)
4300{
4301 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4302 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4303
4304 if (!pShwPml4)
4305 {
4306 X86PML4E ZeroPml4e = {0};
4307 return ZeroPml4e;
4308 }
4309 return pShwPml4->a[iPml4];
4310}
4311
4312
4313/**
4314 * Gets the pointer to the specified shadow page map level-4 entry.
4315 *
4316 * @returns The entry.
4317 * @param pPGM Pointer to the PGM instance data.
4318 * @param iPml4 The PML4 index.
4319 */
4320DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGMCPU pPGM, unsigned int iPml4)
4321{
4322 PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4323 if (!pShwPml4)
4324 return NULL;
4325 return &pShwPml4->a[iPml4];
4326}
4327
4328
4329/**
4330 * Gets the GUEST page directory pointer for the specified address.
4331 *
4332 * @returns The page directory in question.
4333 * @returns NULL if the page directory is not present or on an invalid page.
4334 * @param pPGM Pointer to the PGM instance data.
4335 * @param GCPtr The address.
4336 * @param piPD Receives the index into the returned page directory
4337 */
4338DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGMCPU pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4339{
4340 PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4341 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4342 if (pGuestPml4->a[iPml4].n.u1Present)
4343 {
4344 PCX86PDPT pPdptTemp;
4345 int rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4346 AssertRCReturn(rc, NULL);
4347
4348 const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4349 if (pPdptTemp->a[iPdpt].n.u1Present)
4350 {
4351 PX86PDPAE pPD;
4352 rc = PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, pPdptTemp->a[iPdpt].u & X86_PDPE_PG_MASK, &pPD);
4353 AssertRCReturn(rc, NULL);
4354
4355 *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4356 return pPD;
4357 }
4358 }
4359 return NULL;
4360}
4361
4362#endif /* !IN_RC */
4363
4364/**
4365 * Gets the page state for a physical handler.
4366 *
4367 * @returns The physical handler page state.
4368 * @param pCur The physical handler in question.
4369 */
4370DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4371{
4372 switch (pCur->enmType)
4373 {
4374 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4375 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4376
4377 case PGMPHYSHANDLERTYPE_MMIO:
4378 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4379 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4380
4381 default:
4382 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4383 }
4384}
4385
4386
4387/**
4388 * Gets the page state for a virtual handler.
4389 *
4390 * @returns The virtual handler page state.
4391 * @param pCur The virtual handler in question.
4392 * @remarks This should never be used on a hypervisor access handler.
4393 */
4394DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4395{
4396 switch (pCur->enmType)
4397 {
4398 case PGMVIRTHANDLERTYPE_WRITE:
4399 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4400 case PGMVIRTHANDLERTYPE_ALL:
4401 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4402 default:
4403 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4404 }
4405}
4406
4407
4408/**
4409 * Clears one physical page of a virtual handler
4410 *
4411 * @param pPGM Pointer to the PGM instance.
4412 * @param pCur Virtual handler structure
4413 * @param iPage Physical page index
4414 *
4415 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4416 * need to care about other handlers in the same page.
4417 */
4418DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4419{
4420 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4421
4422 /*
4423 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
4424 */
4425#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4426 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4427 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4428 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4429#endif
4430 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4431 {
4432 /* We're the head of the alias chain. */
4433 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4434#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4435 AssertReleaseMsg(pRemove != NULL,
4436 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4437 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4438 AssertReleaseMsg(pRemove == pPhys2Virt,
4439 ("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4440 " got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4441 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4442 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4443#endif
4444 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4445 {
4446 /* Insert the next list in the alias chain into the tree. */
4447 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4448#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4449 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4450 ("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4451 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4452#endif
4453 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
4454 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4455 AssertRelease(fRc);
4456 }
4457 }
4458 else
4459 {
4460 /* Locate the previous node in the alias chain. */
4461 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4462#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4463 AssertReleaseMsg(pPrev != pPhys2Virt,
4464 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4465 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4466#endif
4467 for (;;)
4468 {
4469 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4470 if (pNext == pPhys2Virt)
4471 {
4472 /* unlink. */
4473 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4474 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4475 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4476 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4477 else
4478 {
4479 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4480 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4481 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4482 }
4483 break;
4484 }
4485
4486 /* next */
4487 if (pNext == pPrev)
4488 {
4489#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4490 AssertReleaseMsg(pNext != pPrev,
4491 ("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4492 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4493#endif
4494 break;
4495 }
4496 pPrev = pNext;
4497 }
4498 }
4499 Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4500 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4501 pPhys2Virt->offNextAlias = 0;
4502 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4503
4504 /*
4505 * Clear the ram flags for this page.
4506 */
4507 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4508 AssertReturnVoid(pPage);
4509 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4510}
4511
4512
4513/**
4514 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4515 *
4516 * @returns Pointer to the shadow page structure.
4517 * @param pPool The pool.
4518 * @param idx The pool page index.
4519 */
4520DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4521{
4522 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4523 return &pPool->aPages[idx];
4524}
4525
4526
4527#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4528/**
4529 * Clear references to guest physical memory.
4530 *
4531 * @param pPool The pool.
4532 * @param pPoolPage The pool page.
4533 * @param pPhysPage The physical guest page tracking structure.
4534 */
4535DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4536{
4537 /*
4538 * Just deal with the simple case here.
4539 */
4540# ifdef LOG_ENABLED
4541 const unsigned uOrg = PGM_PAGE_GET_TRACKING(pPhysPage);
4542# endif
4543 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4544 if (cRefs == 1)
4545 {
4546 Assert(pPoolPage->idx == PGM_PAGE_GET_TD_IDX(pPhysPage));
4547 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
4548 }
4549 else
4550 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4551 Log2(("pgmTrackDerefGCPhys: %x -> %x pPhysPage=%R[pgmpage]\n", uOrg, PGM_PAGE_GET_TRACKING(pPhysPage), pPhysPage ));
4552}
4553#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4554
4555
4556#ifdef PGMPOOL_WITH_CACHE
4557/**
4558 * Moves the page to the head of the age list.
4559 *
4560 * This is done when the cached page is used in one way or another.
4561 *
4562 * @param pPool The pool.
4563 * @param pPage The cached page.
4564 */
4565DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4566{
4567 PVM pVM = pPool->CTX_SUFF(pVM);
4568 pgmLock(pVM);
4569
4570 /*
4571 * Move to the head of the age list.
4572 */
4573 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4574 {
4575 /* unlink */
4576 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4577 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4578 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4579 else
4580 pPool->iAgeTail = pPage->iAgePrev;
4581
4582 /* insert at head */
4583 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4584 pPage->iAgeNext = pPool->iAgeHead;
4585 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4586 pPool->iAgeHead = pPage->idx;
4587 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4588 }
4589 pgmUnlock(pVM);
4590}
4591#endif /* PGMPOOL_WITH_CACHE */
4592
4593/**
4594 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
4595 *
4596 * @param pVM VM Handle.
4597 * @param pPage PGM pool page
4598 */
4599DECLINLINE(void) pgmPoolLockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4600{
4601 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4602 ASMAtomicIncU32(&pPage->cLocked);
4603}
4604
4605
4606/**
4607 * Unlocks a page to allow flushing again
4608 *
4609 * @param pVM VM Handle.
4610 * @param pPage PGM pool page
4611 */
4612DECLINLINE(void) pgmPoolUnlockPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4613{
4614 Assert(PGMIsLockOwner(pPool->CTX_SUFF(pVM)));
4615 Assert(pPage->cLocked);
4616 ASMAtomicDecU32(&pPage->cLocked);
4617}
4618
4619
4620/**
4621 * Checks if the page is locked (e.g. the active CR3 or one of the four PDs of a PAE PDPT)
4622 *
4623 * @returns VBox status code.
4624 * @param pPage PGM pool page
4625 */
4626DECLINLINE(bool) pgmPoolIsPageLocked(PPGM pPGM, PPGMPOOLPAGE pPage)
4627{
4628 if (pPage->cLocked)
4629 {
4630 LogFlow(("pgmPoolIsPageLocked found root page %d\n", pPage->enmKind));
4631 if (pPage->cModifications)
4632 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
4633 return true;
4634 }
4635 return false;
4636}
4637
4638/**
4639 * Tells if mappings are to be put into the shadow page table or not
4640 *
4641 * @returns boolean result
4642 * @param pVM VM handle.
4643 */
4644DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4645{
4646#ifdef IN_RING0
4647 /* There are no mappings in VT-x and AMD-V mode. */
4648 Assert(pPGM->fDisableMappings);
4649 return false;
4650#else
4651 return !pPGM->fDisableMappings;
4652#endif
4653}
4654
4655/** @} */
4656
4657#endif
4658
4659
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