PGMInternal.h@ 10196

Last change on this file since 10196 was 10063, checked in by vboxsync, 16 years ago
AMD64 updates for nested paging.
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1	/* $Id: PGMInternal.h 10063 2008-07-01 09:57:49Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/assert.h>
41	#include <iprt/critsect.h>
42
43	#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
44	# error "Not in PGM! This is an internal header!"
45	#endif
46
47
48	/** @defgroup grp_pgm_int Internals
49	* @ingroup grp_pgm
50	* @internal
51	* @{
52	*/
53
54
55	/** @name PGM Compile Time Config
56	* @{
57	*/
58
59	/**
60	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
61	* Comment it if it will break something.
62	*/
63	#define PGM_OUT_OF_SYNC_IN_GC
64
65	/**
66	* Check and skip global PDEs for non-global flushes
67	*/
68	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70	/**
71	* Sync N pages instead of a whole page table
72	*/
73	#define PGM_SYNC_N_PAGES
74
75	/**
76	* Number of pages to sync during a page fault
77	*
78	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
79	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
80	*/
81	#define PGM_SYNC_NR_PAGES 8
82
83	/**
84	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
85	*/
86	#define PGM_MAX_PHYSCACHE_ENTRIES 64
87	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
88
89	/**
90	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
91	*/
92	#define PGM_PHYSMEMACCESS_CACHING
93
94	/** @def PGMPOOL_WITH_CACHE
95	* Enable agressive caching using the page pool.
96	*
97	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
98	*/
99	#define PGMPOOL_WITH_CACHE
100
101	/** @def PGMPOOL_WITH_MIXED_PT_CR3
102	* When defined, we'll deal with 'uncachable' pages.
103	*/
104	#ifdef PGMPOOL_WITH_CACHE
105	# define PGMPOOL_WITH_MIXED_PT_CR3
106	#endif
107
108	/** @def PGMPOOL_WITH_MONITORING
109	* Monitor the guest pages which are shadowed.
110	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
111	* be enabled as well.
112	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
113	*/
114	#ifdef PGMPOOL_WITH_CACHE
115	# define PGMPOOL_WITH_MONITORING
116	#endif
117
118	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
119	* Tracking the of shadow pages mapping guest physical pages.
120	*
121	* This is very expensive, the current cache prototype is trying to figure out
122	* whether it will be acceptable with an agressive caching policy.
123	*/
124	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
125	# define PGMPOOL_WITH_GCPHYS_TRACKING
126	#endif
127
128	/** @def PGMPOOL_WITH_USER_TRACKNG
129	* Tracking users of shadow pages. This is required for the linking of shadow page
130	* tables and physical guest addresses.
131	*/
132	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
133	# define PGMPOOL_WITH_USER_TRACKING
134	#endif
135
136	/** @def PGMPOOL_CFG_MAX_GROW
137	* The maximum number of pages to add to the pool in one go.
138	*/
139	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
140
141	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
142	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
143	*/
144	#ifdef VBOX_STRICT
145	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
146	#endif
147	/** @} */
148
149
150	/** @name PDPT and PML4 flags.
151	* These are placed in the three bits available for system programs in
152	* the PDPT and PML4 entries.
153	* @{ */
154	/** The entry is a permanent one and it's must always be present.
155	* Never free such an entry. */
156	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
157	/** Mapping (hypervisor allocated pagetable). */
158	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
159	/** @} */
160
161	/** @name Page directory flags.
162	* These are placed in the three bits available for system programs in
163	* the page directory entries.
164	* @{ */
165	/** Mapping (hypervisor allocated pagetable). */
166	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
167	/** Made read-only to facilitate dirty bit tracking. */
168	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169	/** @} */
170
171	/** @name Page flags.
172	* These are placed in the three bits available for system programs in
173	* the page entries.
174	* @{ */
175	/** Made read-only to facilitate dirty bit tracking. */
176	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179	/** Scanned and approved by CSAM (tm).
180	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
181	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
182	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183	#endif
184	/** @} */
185
186	/** @name Defines used to indicate the shadow and guest paging in the templates.
187	* @{ */
188	#define PGM_TYPE_REAL 1
189	#define PGM_TYPE_PROT 2
190	#define PGM_TYPE_32BIT 3
191	#define PGM_TYPE_PAE 4
192	#define PGM_TYPE_AMD64 5
193	#define PGM_TYPE_NESTED 6
194	/** @} */
195
196	/** Macro for checking if the guest is using paging.
197	* @param uType PGM_TYPE_*
198	* @remark ASSUMES certain order of the PGM_TYPE_* values.
199	*/
200	#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT && (uType) != PGM_TYPE_NESTED)
201
202	/** Macro for checking if the guest supports the NX bit.
203	* @param uType PGM_TYPE_*
204	* @remark ASSUMES certain order of the PGM_TYPE_* values.
205	*/
206	#define PGM_WITH_NX(uType) ((uType) >= PGM_TYPE_PAE && (uType) != PGM_TYPE_NESTED)
207
208
209	/** @def PGM_HCPHYS_2_PTR
210	* Maps a HC physical page pool address to a virtual address.
211	*
212	* @returns VBox status code.
213	* @param pVM The VM handle.
214	* @param HCPhys The HC physical address to map to a virtual one.
215	* @param ppv Where to store the virtual address. No need to cast this.
216	*
217	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
218	* small page window employeed by that function. Be careful.
219	* @remark There is no need to assert on the result.
220	*/
221	#ifdef IN_GC
222	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
223	#else
224	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
225	#endif
226
227	/** @def PGM_GCPHYS_2_PTR
228	* Maps a GC physical page address to a virtual address.
229	*
230	* @returns VBox status code.
231	* @param pVM The VM handle.
232	* @param GCPhys The GC physical address to map to a virtual one.
233	* @param ppv Where to store the virtual address. No need to cast this.
234	*
235	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
236	* small page window employeed by that function. Be careful.
237	* @remark There is no need to assert on the result.
238	*/
239	#ifdef IN_GC
240	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
241	#else
242	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only /, (void )(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
243	#endif
244
245	/** @def PGM_GCPHYS_2_PTR_EX
246	* Maps a unaligned GC physical page address to a virtual address.
247	*
248	* @returns VBox status code.
249	* @param pVM The VM handle.
250	* @param GCPhys The GC physical address to map to a virtual one.
251	* @param ppv Where to store the virtual address. No need to cast this.
252	*
253	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
254	* small page window employeed by that function. Be careful.
255	* @remark There is no need to assert on the result.
256	*/
257	#ifdef IN_GC
258	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
259	#else
260	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only /, (void )(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
261	#endif
262
263	/** @def PGM_INVL_PG
264	* Invalidates a page when in GC does nothing in HC.
265	*
266	* @param GCVirt The virtual address of the page to invalidate.
267	*/
268	#ifdef IN_GC
269	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
270	#elif defined(IN_RING0)
271	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
272	#else
273	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
274	#endif
275
276	/** @def PGM_INVL_BIG_PG
277	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
278	*
279	* @param GCVirt The virtual address within the page directory to invalidate.
280	*/
281	#ifdef IN_GC
282	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
283	#elif defined(IN_RING0)
284	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
285	#else
286	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
287	#endif
288
289	/** @def PGM_INVL_GUEST_TLBS()
290	* Invalidates all guest TLBs.
291	*/
292	#ifdef IN_GC
293	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
294	#elif defined(IN_RING0)
295	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
296	#else
297	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
298	#endif
299
300
301	/**
302	* Structure for tracking GC Mappings.
303	*
304	* This structure is used by linked list in both GC and HC.
305	*/
306	typedef struct PGMMAPPING
307	{
308	/** Pointer to next entry. */
309	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
310	/** Pointer to next entry. */
311	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
312	/** Pointer to next entry. */
313	RCPTRTYPE(struct PGMMAPPING *) pNextGC;
314	#if GC_ARCH_BITS == 64
315	RTRCPTR padding0;
316	#endif
317	/** Start Virtual address. */
318	RTGCUINTPTR GCPtr;
319	/** Last Virtual address (inclusive). */
320	RTGCUINTPTR GCPtrLast;
321	/** Range size (bytes). */
322	RTGCUINTPTR cb;
323	/** Pointer to relocation callback function. */
324	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
325	/** User argument to the callback. */
326	R3PTRTYPE(void *) pvUser;
327	/** Mapping description / name. For easing debugging. */
328	R3PTRTYPE(const char *) pszDesc;
329	/** Number of page tables. */
330	RTUINT cPTs;
331	#if HC_ARCH_BITS != GC_ARCH_BITS \|\| GC_ARCH_BITS == 64
332	RTUINT uPadding1; /*< Alignment padding. /
333	#endif
334	/** Array of page table mapping data. Each entry
335	* describes one page table. The array can be longer
336	* than the declared length.
337	*/
338	struct
339	{
340	/** The HC physical address of the page table. */
341	RTHCPHYS HCPhysPT;
342	/** The HC physical address of the first PAE page table. */
343	RTHCPHYS HCPhysPaePT0;
344	/** The HC physical address of the second PAE page table. */
345	RTHCPHYS HCPhysPaePT1;
346	/** The HC virtual address of the 32-bit page table. */
347	R3PTRTYPE(PX86PT) pPTR3;
348	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
349	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
350	/** The GC virtual address of the 32-bit page table. */
351	RCPTRTYPE(PX86PT) pPTGC;
352	/** The GC virtual address of the two PAE page table. */
353	RCPTRTYPE(PX86PTPAE) paPaePTsGC;
354	/** The GC virtual address of the 32-bit page table. */
355	R0PTRTYPE(PX86PT) pPTR0;
356	/** The GC virtual address of the two PAE page table. */
357	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
358	} aPTs[1];
359	} PGMMAPPING;
360	/** Pointer to structure for tracking GC Mappings. */
361	typedef struct PGMMAPPING *PPGMMAPPING;
362
363
364	/**
365	* Physical page access handler structure.
366	*
367	* This is used to keep track of physical address ranges
368	* which are being monitored in some kind of way.
369	*/
370	typedef struct PGMPHYSHANDLER
371	{
372	AVLROGCPHYSNODECORE Core;
373	/** Access type. */
374	PGMPHYSHANDLERTYPE enmType;
375	/** Number of pages to update. */
376	uint32_t cPages;
377	/** Pointer to R3 callback function. */
378	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
379	/** User argument for R3 handlers. */
380	R3PTRTYPE(void *) pvUserR3;
381	/** Pointer to R0 callback function. */
382	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
383	/** User argument for R0 handlers. */
384	R0PTRTYPE(void *) pvUserR0;
385	/** Pointer to GC callback function. */
386	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
387	/** User argument for GC handlers. */
388	RCPTRTYPE(void *) pvUserGC;
389	/** Description / Name. For easing debugging. */
390	R3PTRTYPE(const char *) pszDesc;
391	#ifdef VBOX_WITH_STATISTICS
392	/** Profiling of this handler. */
393	STAMPROFILE Stat;
394	#endif
395	} PGMPHYSHANDLER;
396	/** Pointer to a physical page access handler structure. */
397	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
398
399
400	/**
401	* Cache node for the physical addresses covered by a virtual handler.
402	*/
403	typedef struct PGMPHYS2VIRTHANDLER
404	{
405	/** Core node for the tree based on physical ranges. */
406	AVLROGCPHYSNODECORE Core;
407	/** Offset from this struct to the PGMVIRTHANDLER structure. */
408	int32_t offVirtHandler;
409	/** Offset of the next alias relative to this one.
410	* Bit 0 is used for indicating whether we're in the tree.
411	* Bit 1 is used for indicating that we're the head node.
412	*/
413	int32_t offNextAlias;
414	} PGMPHYS2VIRTHANDLER;
415	/** Pointer to a phys to virtual handler structure. */
416	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
417
418	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
419	* node is in the tree. */
420	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
421	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
422	* node is in the head of an alias chain.
423	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
424	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
425	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
426	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
427
428
429	/**
430	* Virtual page access handler structure.
431	*
432	* This is used to keep track of virtual address ranges
433	* which are being monitored in some kind of way.
434	*/
435	typedef struct PGMVIRTHANDLER
436	{
437	/** Core node for the tree based on virtual ranges. */
438	AVLROGCPTRNODECORE Core;
439	/** Number of cache pages. */
440	uint32_t u32Padding;
441	/** Access type. */
442	PGMVIRTHANDLERTYPE enmType;
443	/** Number of cache pages. */
444	uint32_t cPages;
445	#if GC_ARCH_BITS == 64
446	uint32_t padding0;
447	#endif
448	/** @todo The next two members are redundant. It adds some readability though. */
449	/** Start of the range. */
450	RTGCPTR GCPtr;
451	/** End of the range (exclusive). */
452	RTGCPTR GCPtrLast;
453	/** Size of the range (in bytes). */
454	RTGCUINTPTR cb;
455	/** Pointer to the GC callback function. */
456	RCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
457	#if GC_ARCH_BITS == 64
458	RTRCPTR padding1;
459	#endif
460	/** Pointer to the HC callback function for invalidation. */
461	R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
462	/** Pointer to the HC callback function. */
463	R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
464	/** Description / Name. For easing debugging. */
465	R3PTRTYPE(const char *) pszDesc;
466	#ifdef VBOX_WITH_STATISTICS
467	/** Profiling of this handler. */
468	STAMPROFILE Stat;
469	#endif
470	/** Array of cached physical addresses for the monitored ranged. */
471	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
472	} PGMVIRTHANDLER;
473	/** Pointer to a virtual page access handler structure. */
474	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
475
476
477	/**
478	* Page type.
479	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
480	* @todo convert to \#defines.
481	*/
482	typedef enum PGMPAGETYPE
483	{
484	/** The usual invalid zero entry. */
485	PGMPAGETYPE_INVALID = 0,
486	/** RAM page. (RWX) */
487	PGMPAGETYPE_RAM,
488	/** MMIO2 page. (RWX) */
489	PGMPAGETYPE_MMIO2,
490	/** Shadowed ROM. (RWX) */
491	PGMPAGETYPE_ROM_SHADOW,
492	/** ROM page. (R-X) */
493	PGMPAGETYPE_ROM,
494	/** MMIO page. (---) */
495	PGMPAGETYPE_MMIO,
496	/** End of valid entries. */
497	PGMPAGETYPE_END
498	} PGMPAGETYPE;
499	AssertCompile(PGMPAGETYPE_END < 7);
500
501	/** @name Page type predicates.
502	* @{ */
503	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
504	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
505	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
506	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
507	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
508	/** @} */
509
510
511	/**
512	* A Physical Guest Page tracking structure.
513	*
514	* The format of this structure is complicated because we have to fit a lot
515	* of information into as few bits as possible. The format is also subject
516	* to change (there is one comming up soon). Which means that for we'll be
517	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
518	* accessess to the structure.
519	*/
520	typedef struct PGMPAGE
521	{
522	/** The physical address and a whole lot of other stuff. All bits are used! */
523	RTHCPHYS HCPhys;
524	/** The page state. */
525	uint32_t u2StateX : 2;
526	/** Flag indicating that a write monitored page was written to when set. */
527	uint32_t fWrittenToX : 1;
528	/** For later. */
529	uint32_t fSomethingElse : 1;
530	/** The Page ID.
531	* @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
532	* The HCPhys will be 100% static. */
533	uint32_t idPageX : 28;
534	/** The page type (PGMPAGETYPE). */
535	uint32_t u3Type : 3;
536	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
537	uint32_t u2HandlerPhysStateX : 2;
538	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
539	uint32_t u2HandlerVirtStateX : 2;
540	uint32_t u29B : 25;
541	} PGMPAGE;
542	AssertCompileSize(PGMPAGE, 16);
543	/** Pointer to a physical guest page. */
544	typedef PGMPAGE *PPGMPAGE;
545	/** Pointer to a const physical guest page. */
546	typedef const PGMPAGE *PCPGMPAGE;
547	/** Pointer to a physical guest page pointer. */
548	typedef PPGMPAGE *PPPGMPAGE;
549
550
551	/**
552	* Clears the page structure.
553	* @param pPage Pointer to the physical guest page tracking structure.
554	*/
555	#define PGM_PAGE_CLEAR(pPage) \
556	do { \
557	(pPage)->HCPhys = 0; \
558	(pPage)->u2StateX = 0; \
559	(pPage)->fWrittenToX = 0; \
560	(pPage)->fSomethingElse = 0; \
561	(pPage)->idPageX = 0; \
562	(pPage)->u3Type = 0; \
563	(pPage)->u29B = 0; \
564	} while (0)
565
566	/**
567	* Initializes the page structure.
568	* @param pPage Pointer to the physical guest page tracking structure.
569	*/
570	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
571	do { \
572	(pPage)->HCPhys = (_HCPhys); \
573	(pPage)->u2StateX = (_uState); \
574	(pPage)->fWrittenToX = 0; \
575	(pPage)->fSomethingElse = 0; \
576	(pPage)->idPageX = (_idPage); \
577	/(pPage)->u3Type = (_uType); - later / \
578	PGM_PAGE_SET_TYPE(pPage, _uType); \
579	(pPage)->u29B = 0; \
580	} while (0)
581
582	/**
583	* Initializes the page structure of a ZERO page.
584	* @param pPage Pointer to the physical guest page tracking structure.
585	*/
586	#ifdef VBOX_WITH_NEW_PHYS_CODE
587	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
588	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
589	#else
590	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
591	PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
592	#endif
593	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
594	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
595	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
596
597
598	/** @name The Page state, PGMPAGE::u2StateX.
599	* @{ */
600	/** The zero page.
601	* This is a per-VM page that's never ever mapped writable. */
602	#define PGM_PAGE_STATE_ZERO 0
603	/** A allocated page.
604	* This is a per-VM page allocated from the page pool (or wherever
605	* we get MMIO2 pages from if the type is MMIO2).
606	*/
607	#define PGM_PAGE_STATE_ALLOCATED 1
608	/** A allocated page that's being monitored for writes.
609	* The shadow page table mappings are read-only. When a write occurs, the
610	* fWrittenTo member is set, the page remapped as read-write and the state
611	* moved back to allocated. */
612	#define PGM_PAGE_STATE_WRITE_MONITORED 2
613	/** The page is shared, aka. copy-on-write.
614	* This is a page that's shared with other VMs. */
615	#define PGM_PAGE_STATE_SHARED 3
616	/** @} */
617
618
619	/**
620	* Gets the page state.
621	* @returns page state (PGM_PAGE_STATE_*).
622	* @param pPage Pointer to the physical guest page tracking structure.
623	*/
624	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
625
626	/**
627	* Sets the page state.
628	* @param pPage Pointer to the physical guest page tracking structure.
629	* @param _uState The new page state.
630	*/
631	#define PGM_PAGE_SET_STATE(pPage, _uState) \
632	do { (pPage)->u2StateX = (_uState); } while (0)
633
634
635	/**
636	* Gets the host physical address of the guest page.
637	* @returns host physical address (RTHCPHYS).
638	* @param pPage Pointer to the physical guest page tracking structure.
639	*/
640	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
641
642	/**
643	* Sets the host physical address of the guest page.
644	* @param pPage Pointer to the physical guest page tracking structure.
645	* @param _HCPhys The new host physical address.
646	*/
647	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
648	do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
649	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
650
651	/**
652	* Get the Page ID.
653	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
654	* @param pPage Pointer to the physical guest page tracking structure.
655	*/
656	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
657	/* later:
658	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
659	\| ((uint32_t)(pPage)->HCPhys & 0xfff) )
660	*/
661	/**
662	* Sets the Page ID.
663	* @param pPage Pointer to the physical guest page tracking structure.
664	*/
665	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
666	/* later:
667	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
668	\| ((_idPage) & 0xfff) \
669	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
670	*/
671
672	/**
673	* Get the Chunk ID.
674	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
675	* @param pPage Pointer to the physical guest page tracking structure.
676	*/
677	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
678	/* later:
679	#if GMM_CHUNKID_SHIFT == 12
680	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
681	#elif GMM_CHUNKID_SHIFT > 12
682	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
683	#elif GMM_CHUNKID_SHIFT < 12
684	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
685	\| ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
686	#else
687	# error "GMM_CHUNKID_SHIFT isn't defined or something."
688	#endif
689	*/
690
691	/**
692	* Get the index of the page within the allocaiton chunk.
693	* @returns The page index.
694	* @param pPage Pointer to the physical guest page tracking structure.
695	*/
696	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
697	/* later:
698	#if GMM_CHUNKID_SHIFT <= 12
699	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
700	#else
701	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
702	\| ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
703	#endif
704	*/
705
706
707	/**
708	* Gets the page type.
709	* @returns The page type.
710	* @param pPage Pointer to the physical guest page tracking structure.
711	*/
712	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
713
714	/**
715	* Sets the page type.
716	* @param pPage Pointer to the physical guest page tracking structure.
717	* @param _enmType The new page type (PGMPAGETYPE).
718	*/
719	#ifdef VBOX_WITH_NEW_PHYS_CODE
720	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
721	do { (pPage)->u3Type = (_enmType); } while (0)
722	#else
723	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
724	do { \
725	(pPage)->u3Type = (_enmType); \
726	if ((_enmType) == PGMPAGETYPE_ROM) \
727	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM; \
728	else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
729	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2; \
730	else if ((_enmType) == PGMPAGETYPE_MMIO2) \
731	(pPage)->HCPhys \|= MM_RAM_FLAGS_MMIO2; \
732	} while (0)
733	#endif
734
735
736	/**
737	* Checks if the page is 'reserved'.
738	* @returns true/false.
739	* @param pPage Pointer to the physical guest page tracking structure.
740	*/
741	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
742
743	/**
744	* Checks if the page is marked for MMIO.
745	* @returns true/false.
746	* @param pPage Pointer to the physical guest page tracking structure.
747	*/
748	#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
749
750	/**
751	* Checks if the page is backed by the ZERO page.
752	* @returns true/false.
753	* @param pPage Pointer to the physical guest page tracking structure.
754	*/
755	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
756
757	/**
758	* Checks if the page is backed by a SHARED page.
759	* @returns true/false.
760	* @param pPage Pointer to the physical guest page tracking structure.
761	*/
762	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
763
764
765	/**
766	* Marks the paget as written to (for GMM change monitoring).
767	* @param pPage Pointer to the physical guest page tracking structure.
768	*/
769	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
770
771	/**
772	* Clears the written-to indicator.
773	* @param pPage Pointer to the physical guest page tracking structure.
774	*/
775	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
776
777	/**
778	* Checks if the page was marked as written-to.
779	* @returns true/false.
780	* @param pPage Pointer to the physical guest page tracking structure.
781	*/
782	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
783
784
785	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
786	*
787	* @remarks The values are assigned in order of priority, so we can calculate
788	* the correct state for a page with different handlers installed.
789	* @{ */
790	/** No handler installed. */
791	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
792	/** Monitoring is temporarily disabled. */
793	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
794	/** Write access is monitored. */
795	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
796	/** All access is monitored. */
797	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
798	/** @} */
799
800	/**
801	* Gets the physical access handler state of a page.
802	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
803	* @param pPage Pointer to the physical guest page tracking structure.
804	*/
805	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
806
807	/**
808	* Sets the physical access handler state of a page.
809	* @param pPage Pointer to the physical guest page tracking structure.
810	* @param _uState The new state value.
811	*/
812	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
813	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
814
815	/**
816	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
817	* @returns true/false
818	* @param pPage Pointer to the physical guest page tracking structure.
819	*/
820	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
821
822	/**
823	* Checks if the page has any active physical access handlers.
824	* @returns true/false
825	* @param pPage Pointer to the physical guest page tracking structure.
826	*/
827	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
828
829
830	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
831	*
832	* @remarks The values are assigned in order of priority, so we can calculate
833	* the correct state for a page with different handlers installed.
834	* @{ */
835	/** No handler installed. */
836	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
837	/* 1 is reserved so the lineup is identical with the physical ones. */
838	/** Write access is monitored. */
839	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
840	/** All access is monitored. */
841	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
842	/** @} */
843
844	/**
845	* Gets the virtual access handler state of a page.
846	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
847	* @param pPage Pointer to the physical guest page tracking structure.
848	*/
849	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
850
851	/**
852	* Sets the virtual access handler state of a page.
853	* @param pPage Pointer to the physical guest page tracking structure.
854	* @param _uState The new state value.
855	*/
856	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
857	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
858
859	/**
860	* Checks if the page has any virtual access handlers.
861	* @returns true/false
862	* @param pPage Pointer to the physical guest page tracking structure.
863	*/
864	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
865
866	/**
867	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
868	* virtual handlers.
869	* @returns true/false
870	* @param pPage Pointer to the physical guest page tracking structure.
871	*/
872	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
873
874
875
876	/**
877	* Checks if the page has any access handlers, including temporarily disabled ones.
878	* @returns true/false
879	* @param pPage Pointer to the physical guest page tracking structure.
880	*/
881	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
882	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
883	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
884
885	/**
886	* Checks if the page has any active access handlers.
887	* @returns true/false
888	* @param pPage Pointer to the physical guest page tracking structure.
889	*/
890	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
891	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
892	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
893
894	/**
895	* Checks if the page has any active access handlers catching all accesses.
896	* @returns true/false
897	* @param pPage Pointer to the physical guest page tracking structure.
898	*/
899	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
900	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
901	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
902
903
904	/**
905	* Ram range for GC Phys to HC Phys conversion.
906	*
907	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
908	* conversions too, but we'll let MM handle that for now.
909	*
910	* This structure is used by linked lists in both GC and HC.
911	*/
912	typedef struct PGMRAMRANGE
913	{
914	/** Pointer to the next RAM range - for R3. */
915	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
916	/** Pointer to the next RAM range - for R0. */
917	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
918	/** Pointer to the next RAM range - for GC. */
919	RCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
920	/** Pointer alignment. */
921	RTRCPTR GCPtrAlignment;
922	/** Start of the range. Page aligned. */
923	RTGCPHYS GCPhys;
924	/** Last address in the range (inclusive). Page aligned (-1). */
925	RTGCPHYS GCPhysLast;
926	/** Size of the range. (Page aligned of course). */
927	RTGCPHYS cb;
928	/** MM_RAM_* flags */
929	uint32_t fFlags;
930	#ifdef VBOX_WITH_NEW_PHYS_CODE
931	uint32_t u32Alignment; /*< alignment. /
932	#else
933	/** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
934	RCPTRTYPE(PRTHCPTR) pavHCChunkGC;
935	/** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
936	R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
937	#endif
938	/** Start of the HC mapping of the range. This is only used for MMIO2. */
939	R3PTRTYPE(void *) pvHC;
940	/** The range description. */
941	R3PTRTYPE(const char *) pszDesc;
942
943	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
944	#ifdef VBOX_WITH_NEW_PHYS_CODE
945	uint32_t au32Reserved[2];
946	#elif HC_ARCH_BITS == 32
947	uint32_t au32Reserved[1];
948	#endif
949
950	/** Array of physical guest page tracking structures. */
951	PGMPAGE aPages[1];
952	} PGMRAMRANGE;
953	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
954	typedef PGMRAMRANGE *PPGMRAMRANGE;
955
956	/** Return hc ptr corresponding to the ram range and physical offset */
957	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
958	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
959	: (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
960
961	/**
962	* Per page tracking structure for ROM image.
963	*
964	* A ROM image may have a shadow page, in which case we may have
965	* two pages backing it. This structure contains the PGMPAGE for
966	* both while PGMRAMRANGE have a copy of the active one. It is
967	* important that these aren't out of sync in any regard other
968	* than page pool tracking data.
969	*/
970	typedef struct PGMROMPAGE
971	{
972	/** The page structure for the virgin ROM page. */
973	PGMPAGE Virgin;
974	/** The page structure for the shadow RAM page. */
975	PGMPAGE Shadow;
976	/** The current protection setting. */
977	PGMROMPROT enmProt;
978	/** Pad the structure size to a multiple of 8. */
979	uint32_t u32Padding;
980	} PGMROMPAGE;
981	/** Pointer to a ROM page tracking structure. */
982	typedef PGMROMPAGE *PPGMROMPAGE;
983
984
985	/**
986	* A registered ROM image.
987	*
988	* This is needed to keep track of ROM image since they generally
989	* intrude into a PGMRAMRANGE. It also keeps track of additional
990	* info like the two page sets (read-only virgin and read-write shadow),
991	* the current state of each page.
992	*
993	* Because access handlers cannot easily be executed in a different
994	* context, the ROM ranges needs to be accessible and in all contexts.
995	*/
996	typedef struct PGMROMRANGE
997	{
998	/** Pointer to the next range - R3. */
999	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1000	/** Pointer to the next range - R0. */
1001	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1002	/** Pointer to the next range - GC. */
1003	RCPTRTYPE(struct PGMROMRANGE *) pNextGC;
1004	/** Pointer alignment */
1005	RTRCPTR GCPtrAlignment;
1006	/** Address of the range. */
1007	RTGCPHYS GCPhys;
1008	/** Address of the last byte in the range. */
1009	RTGCPHYS GCPhysLast;
1010	/** Size of the range. */
1011	RTGCPHYS cb;
1012	/** The flags (PGMPHYS_ROM_FLAG_). /
1013	uint32_t fFlags;
1014	/*< Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. /
1015	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1016	/** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1017	* This is used for strictness checks. */
1018	R3PTRTYPE(const void *) pvOriginal;
1019	/** The ROM description. */
1020	R3PTRTYPE(const char *) pszDesc;
1021	/** The per page tracking structures. */
1022	PGMROMPAGE aPages[1];
1023	} PGMROMRANGE;
1024	/** Pointer to a ROM range. */
1025	typedef PGMROMRANGE *PPGMROMRANGE;
1026
1027
1028	/**
1029	* A registered MMIO2 (= Device RAM) range.
1030	*
1031	* There are a few reason why we need to keep track of these
1032	* registrations. One of them is the deregistration & cleanup
1033	* stuff, while another is that the PGMRAMRANGE associated with
1034	* such a region may have to be removed from the ram range list.
1035	*
1036	* Overlapping with a RAM range has to be 100% or none at all. The
1037	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1038	* meditation will be raised if a partial overlap or an overlap of
1039	* ROM pages is encountered. On an overlap we will free all the
1040	* existing RAM pages and put in the ram range pages instead.
1041	*/
1042	typedef struct PGMMMIO2RANGE
1043	{
1044	/** The owner of the range. (a device) */
1045	PPDMDEVINSR3 pDevInsR3;
1046	/** Pointer to the ring-3 mapping of the allocation. */
1047	RTR3PTR pvR3;
1048	/** Pointer to the next range - R3. */
1049	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1050	/** Whether it's mapped or not. */
1051	bool fMapped;
1052	/** Whether it's overlapping or not. */
1053	bool fOverlapping;
1054	/** The PCI region number.
1055	* @remarks This ASSUMES that nobody will ever really need to have multiple
1056	* PCI devices with matching MMIO region numbers on a single device. */
1057	uint8_t iRegion;
1058	/*< Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. /
1059	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1060	/** The associated RAM range. */
1061	PGMRAMRANGE RamRange;
1062	} PGMMMIO2RANGE;
1063	/** Pointer to a MMIO2 range. */
1064	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1065
1066
1067
1068
1069	/** @todo r=bird: fix typename. */
1070	/**
1071	* PGMPhysRead/Write cache entry
1072	*/
1073	typedef struct PGMPHYSCACHE_ENTRY
1074	{
1075	/** HC pointer to physical page */
1076	R3PTRTYPE(uint8_t *) pbHC;
1077	/** GC Physical address for cache entry */
1078	RTGCPHYS GCPhys;
1079	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1080	RTGCPHYS u32Padding0; /*< alignment padding. /
1081	#endif
1082	} PGMPHYSCACHE_ENTRY;
1083
1084	/**
1085	* PGMPhysRead/Write cache to reduce REM memory access overhead
1086	*/
1087	typedef struct PGMPHYSCACHE
1088	{
1089	/** Bitmap of valid cache entries */
1090	uint64_t aEntries;
1091	/** Cache entries */
1092	PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1093	} PGMPHYSCACHE;
1094
1095
1096	/** Pointer to an allocation chunk ring-3 mapping. */
1097	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1098	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1099	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1100
1101	/**
1102	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1103	*
1104	* The primary tree (Core) uses the chunk id as key.
1105	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1106	*/
1107	typedef struct PGMCHUNKR3MAP
1108	{
1109	/** The key is the chunk id. */
1110	AVLU32NODECORE Core;
1111	/** The key is the ageing sequence number. */
1112	AVLLU32NODECORE AgeCore;
1113	/** The current age thingy. */
1114	uint32_t iAge;
1115	/** The current reference count. */
1116	uint32_t volatile cRefs;
1117	/** The current permanent reference count. */
1118	uint32_t volatile cPermRefs;
1119	/** The mapping address. */
1120	void *pv;
1121	} PGMCHUNKR3MAP;
1122
1123	/**
1124	* Allocation chunk ring-3 mapping TLB entry.
1125	*/
1126	typedef struct PGMCHUNKR3MAPTLBE
1127	{
1128	/** The chunk id. */
1129	uint32_t volatile idChunk;
1130	#if HC_ARCH_BITS == 64
1131	uint32_t u32Padding; /*< alignment padding. /
1132	#endif
1133	/** The chunk map. */
1134	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1135	} PGMCHUNKR3MAPTLBE;
1136	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1137	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1138
1139	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1140	* @remark Must be a power of two value. */
1141	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1142
1143	/**
1144	* Allocation chunk ring-3 mapping TLB.
1145	*
1146	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1147	* At first glance this might look kinda odd since AVL trees are
1148	* supposed to give the most optimial lookup times of all trees
1149	* due to their balancing. However, take a tree with 1023 nodes
1150	* in it, that's 10 levels, meaning that most searches has to go
1151	* down 9 levels before they find what they want. This isn't fast
1152	* compared to a TLB hit. There is the factor of cache misses,
1153	* and of course the problem with trees and branch prediction.
1154	* This is why we use TLBs in front of most of the trees.
1155	*
1156	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1157	* difficult when we switch to inlined AVL trees (from kStuff).
1158	*/
1159	typedef struct PGMCHUNKR3MAPTLB
1160	{
1161	/** The TLB entries. */
1162	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1163	} PGMCHUNKR3MAPTLB;
1164
1165	/**
1166	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1167	* @returns Chunk TLB index.
1168	* @param idChunk The Chunk ID.
1169	*/
1170	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1171
1172
1173	/**
1174	* Ring-3 guest page mapping TLB entry.
1175	* @remarks used in ring-0 as well at the moment.
1176	*/
1177	typedef struct PGMPAGER3MAPTLBE
1178	{
1179	/** Address of the page. */
1180	RTGCPHYS volatile GCPhys;
1181	/** The guest page. */
1182	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1183	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1184	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1185	/** The address */
1186	R3R0PTRTYPE(void *) volatile pv;
1187	#if HC_ARCH_BITS == 32
1188	uint32_t u32Padding; /*< alignment padding. /
1189	#endif
1190	} PGMPAGER3MAPTLBE;
1191	/** Pointer to an entry in the HC physical TLB. */
1192	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1193
1194
1195	/** The number of entries in the ring-3 guest page mapping TLB.
1196	* @remarks The value must be a power of two. */
1197	#define PGM_PAGER3MAPTLB_ENTRIES 64
1198
1199	/**
1200	* Ring-3 guest page mapping TLB.
1201	* @remarks used in ring-0 as well at the moment.
1202	*/
1203	typedef struct PGMPAGER3MAPTLB
1204	{
1205	/** The TLB entries. */
1206	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1207	} PGMPAGER3MAPTLB;
1208	/** Pointer to the ring-3 guest page mapping TLB. */
1209	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1210
1211	/**
1212	* Calculates the index of the TLB entry for the specified guest page.
1213	* @returns Physical TLB index.
1214	* @param GCPhys The guest physical address.
1215	*/
1216	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1217
1218
1219	/** @name Context neutrual page mapper TLB.
1220	*
1221	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1222	* code is writting in a kind of context neutrual way. Time will show whether
1223	* this actually makes sense or not...
1224	*
1225	* @{ */
1226	/** @typedef PPGMPAGEMAPTLB
1227	* The page mapper TLB pointer type for the current context. */
1228	/** @typedef PPGMPAGEMAPTLB
1229	* The page mapper TLB entry pointer type for the current context. */
1230	/** @typedef PPGMPAGEMAPTLB
1231	* The page mapper TLB entry pointer pointer type for the current context. */
1232	/** @def PGMPAGEMAPTLB_ENTRIES
1233	* The number of TLB entries in the page mapper TLB for the current context. */
1234	/** @def PGM_PAGEMAPTLB_IDX
1235	* Calculate the TLB index for a guest physical address.
1236	* @returns The TLB index.
1237	* @param GCPhys The guest physical address. */
1238	/** @typedef PPGMPAGEMAP
1239	* Pointer to a page mapper unit for current context. */
1240	/** @typedef PPPGMPAGEMAP
1241	* Pointer to a page mapper unit pointer for current context. */
1242	#ifdef IN_GC
1243	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1244	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1245	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1246	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1247	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1248	typedef void * PPGMPAGEMAP;
1249	typedef void ** PPPGMPAGEMAP;
1250	//#elif IN_RING0
1251	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1252	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1253	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1254	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1255	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1256	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1257	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1258	#else
1259	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1260	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1261	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1262	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1263	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1264	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1265	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1266	#endif
1267	/** @} */
1268
1269
1270	/** @name PGM Pool Indexes.
1271	* Aka. the unique shadow page identifier.
1272	* @{ */
1273	/** NIL page pool IDX. */
1274	#define NIL_PGMPOOL_IDX 0
1275	/** The first normal index. */
1276	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1277	/** Page directory (32-bit root). */
1278	#define PGMPOOL_IDX_PD 1
1279	/** The extended PAE page directory (2048 entries, works as root currently). */
1280	#define PGMPOOL_IDX_PAE_PD 2
1281	/** PAE Page Directory Table 0. */
1282	#define PGMPOOL_IDX_PAE_PD_0 3
1283	/** PAE Page Directory Table 1. */
1284	#define PGMPOOL_IDX_PAE_PD_1 4
1285	/** PAE Page Directory Table 2. */
1286	#define PGMPOOL_IDX_PAE_PD_2 5
1287	/** PAE Page Directory Table 3. */
1288	#define PGMPOOL_IDX_PAE_PD_3 6
1289	/** Page Directory Pointer Table (PAE root, not currently used). */
1290	#define PGMPOOL_IDX_PDPT 7
1291	/** AMD64 CR3 level index.*/
1292	#define PGMPOOL_IDX_AMD64_CR3 8
1293	/** Nested paging root.*/
1294	#define PGMPOOL_IDX_NESTED_ROOT 9
1295	/** The first normal index. */
1296	#define PGMPOOL_IDX_FIRST 10
1297	/** The last valid index. (inclusive, 14 bits) */
1298	#define PGMPOOL_IDX_LAST 0x3fff
1299	/** @} */
1300
1301	/** The NIL index for the parent chain. */
1302	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1303
1304	/**
1305	* Node in the chain linking a shadowed page to it's parent (user).
1306	*/
1307	#pragma pack(1)
1308	typedef struct PGMPOOLUSER
1309	{
1310	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1311	uint16_t iNext;
1312	/** The user page index. */
1313	uint16_t iUser;
1314	/** Index into the user table. */
1315	uint32_t iUserTable;
1316	} PGMPOOLUSER, *PPGMPOOLUSER;
1317	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1318	#pragma pack()
1319
1320
1321	/** The NIL index for the phys ext chain. */
1322	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1323
1324	/**
1325	* Node in the chain of physical cross reference extents.
1326	*/
1327	#pragma pack(1)
1328	typedef struct PGMPOOLPHYSEXT
1329	{
1330	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1331	uint16_t iNext;
1332	/** The user page index. */
1333	uint16_t aidx[3];
1334	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1335	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1336	#pragma pack()
1337
1338
1339	/**
1340	* The kind of page that's being shadowed.
1341	*/
1342	typedef enum PGMPOOLKIND
1343	{
1344	/** The virtual invalid 0 entry. */
1345	PGMPOOLKIND_INVALID = 0,
1346	/** The entry is free (=unused). */
1347	PGMPOOLKIND_FREE,
1348
1349	/** Shw: 32-bit page table; Gst: no paging */
1350	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1351	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1352	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1353	/** Shw: 32-bit page table; Gst: 4MB page. */
1354	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1355	/** Shw: PAE page table; Gst: no paging */
1356	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1357	/** Shw: PAE page table; Gst: 32-bit page table. */
1358	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1359	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1360	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1361	/** Shw: PAE page table; Gst: PAE page table. */
1362	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1363	/** Shw: PAE page table; Gst: 2MB page. */
1364	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1365
1366	/** Shw: PAE page directory; Gst: 32-bit page directory. */
1367	PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1368	/** Shw: PAE page directory; Gst: PAE page directory. */
1369	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1370
1371	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1372	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1373	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1374	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1375	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1376	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1377	/** Shw: 64-bit page directory table; Gst: no paging */
1378	PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1379
1380	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1381	PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1382
1383	/** Shw: Root 32-bit page directory. */
1384	PGMPOOLKIND_ROOT_32BIT_PD,
1385	/** Shw: Root PAE page directory */
1386	PGMPOOLKIND_ROOT_PAE_PD,
1387	/** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1388	PGMPOOLKIND_ROOT_PDPT,
1389	/** Shw: Root Nested paging table. */
1390	PGMPOOLKIND_ROOT_NESTED,
1391
1392	/** The last valid entry. */
1393	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1394	} PGMPOOLKIND;
1395
1396
1397	/**
1398	* The tracking data for a page in the pool.
1399	*/
1400	typedef struct PGMPOOLPAGE
1401	{
1402	/** AVL node code with the (HC) physical address of this page. */
1403	AVLOHCPHYSNODECORE Core;
1404	/** Pointer to the HC mapping of the page. */
1405	R3R0PTRTYPE(void *) pvPageHC;
1406	/** The guest physical address. */
1407	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1408	uint32_t Alignment0;
1409	#endif
1410	RTGCPHYS GCPhys;
1411	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1412	uint8_t enmKind;
1413	uint8_t bPadding;
1414	/** The index of this page. */
1415	uint16_t idx;
1416	/** The next entry in the list this page currently resides in.
1417	* It's either in the free list or in the GCPhys hash. */
1418	uint16_t iNext;
1419	#ifdef PGMPOOL_WITH_USER_TRACKING
1420	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1421	uint16_t iUserHead;
1422	/** The number of present entries. */
1423	uint16_t cPresent;
1424	/** The first entry in the table which is present. */
1425	uint16_t iFirstPresent;
1426	#endif
1427	#ifdef PGMPOOL_WITH_MONITORING
1428	/** The number of modifications to the monitored page. */
1429	uint16_t cModifications;
1430	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1431	uint16_t iModifiedNext;
1432	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1433	uint16_t iModifiedPrev;
1434	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1435	uint16_t iMonitoredNext;
1436	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1437	uint16_t iMonitoredPrev;
1438	#endif
1439	#ifdef PGMPOOL_WITH_CACHE
1440	/** The next page in the age list. */
1441	uint16_t iAgeNext;
1442	/** The previous page in the age list. */
1443	uint16_t iAgePrev;
1444	#endif /* PGMPOOL_WITH_CACHE */
1445	/** Used to indicate that the page is zeroed. */
1446	bool fZeroed;
1447	/** Used to indicate that a PT has non-global entries. */
1448	bool fSeenNonGlobal;
1449	/** Used to indicate that we're monitoring writes to the guest page. */
1450	bool fMonitored;
1451	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1452	* (All pages are in the age list.) */
1453	bool fCached;
1454	/** This is used by the R3 access handlers when invoked by an async thread.
1455	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1456	bool volatile fReusedFlushPending;
1457	/** Used to indicate that the guest is mapping the page is also used as a CR3.
1458	* In these cases the access handler acts differently and will check
1459	* for mapping conflicts like the normal CR3 handler.
1460	* @todo When we change the CR3 shadowing to use pool pages, this flag can be
1461	* replaced by a list of pages which share access handler.
1462	*/
1463	bool fCR3Mix;
1464	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1465
1466
1467	#ifdef PGMPOOL_WITH_CACHE
1468	/** The hash table size. */
1469	# define PGMPOOL_HASH_SIZE 0x40
1470	/** The hash function. */
1471	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1472	#endif
1473
1474
1475	/**
1476	* The shadow page pool instance data.
1477	*
1478	* It's all one big allocation made at init time, except for the
1479	* pages that is. The user nodes follows immediatly after the
1480	* page structures.
1481	*/
1482	typedef struct PGMPOOL
1483	{
1484	/** The VM handle - HC Ptr. */
1485	R3R0PTRTYPE(PVM) pVMHC;
1486	/** The VM handle - GC Ptr. */
1487	RCPTRTYPE(PVM) pVMGC;
1488	/** The max pool size. This includes the special IDs. */
1489	uint16_t cMaxPages;
1490	/** The current pool size. */
1491	uint16_t cCurPages;
1492	/** The head of the free page list. */
1493	uint16_t iFreeHead;
1494	/* Padding. */
1495	uint16_t u16Padding;
1496	#ifdef PGMPOOL_WITH_USER_TRACKING
1497	/** Head of the chain of free user nodes. */
1498	uint16_t iUserFreeHead;
1499	/** The number of user nodes we've allocated. */
1500	uint16_t cMaxUsers;
1501	/** The number of present page table entries in the entire pool. */
1502	uint32_t cPresent;
1503	/** Pointer to the array of user nodes - GC pointer. */
1504	RCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1505	/** Pointer to the array of user nodes - HC pointer. */
1506	R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1507	#endif /* PGMPOOL_WITH_USER_TRACKING */
1508	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1509	/** Head of the chain of free phys ext nodes. */
1510	uint16_t iPhysExtFreeHead;
1511	/** The number of user nodes we've allocated. */
1512	uint16_t cMaxPhysExts;
1513	/** Pointer to the array of physical xref extent - GC pointer. */
1514	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1515	/** Pointer to the array of physical xref extent nodes - HC pointer. */
1516	R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1517	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1518	#ifdef PGMPOOL_WITH_CACHE
1519	/** Hash table for GCPhys addresses. */
1520	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1521	/** The head of the age list. */
1522	uint16_t iAgeHead;
1523	/** The tail of the age list. */
1524	uint16_t iAgeTail;
1525	/** Set if the cache is enabled. */
1526	bool fCacheEnabled;
1527	#endif /* PGMPOOL_WITH_CACHE */
1528	#ifdef PGMPOOL_WITH_MONITORING
1529	/** Head of the list of modified pages. */
1530	uint16_t iModifiedHead;
1531	/** The current number of modified pages. */
1532	uint16_t cModifiedPages;
1533	/** Access handler, GC. */
1534	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1535	/** Access handler, R0. */
1536	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1537	/** Access handler, R3. */
1538	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1539	/** The access handler description (HC ptr). */
1540	R3PTRTYPE(const char *) pszAccessHandler;
1541	#endif /* PGMPOOL_WITH_MONITORING */
1542	/** The number of pages currently in use. */
1543	uint16_t cUsedPages;
1544	#ifdef VBOX_WITH_STATISTICS
1545	/** The high wather mark for cUsedPages. */
1546	uint16_t cUsedPagesHigh;
1547	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1548	/** Profiling pgmPoolAlloc(). */
1549	STAMPROFILEADV StatAlloc;
1550	/** Profiling pgmPoolClearAll(). */
1551	STAMPROFILE StatClearAll;
1552	/** Profiling pgmPoolFlushAllInt(). */
1553	STAMPROFILE StatFlushAllInt;
1554	/** Profiling pgmPoolFlushPage(). */
1555	STAMPROFILE StatFlushPage;
1556	/** Profiling pgmPoolFree(). */
1557	STAMPROFILE StatFree;
1558	/** Profiling time spent zeroing pages. */
1559	STAMPROFILE StatZeroPage;
1560	# ifdef PGMPOOL_WITH_USER_TRACKING
1561	/** Profiling of pgmPoolTrackDeref. */
1562	STAMPROFILE StatTrackDeref;
1563	/** Profiling pgmTrackFlushGCPhysPT. */
1564	STAMPROFILE StatTrackFlushGCPhysPT;
1565	/** Profiling pgmTrackFlushGCPhysPTs. */
1566	STAMPROFILE StatTrackFlushGCPhysPTs;
1567	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1568	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1569	/** Number of times we've been out of user records. */
1570	STAMCOUNTER StatTrackFreeUpOneUser;
1571	# endif
1572	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1573	/** Profiling deref activity related tracking GC physical pages. */
1574	STAMPROFILE StatTrackDerefGCPhys;
1575	/** Number of linear searches for a HCPhys in the ram ranges. */
1576	STAMCOUNTER StatTrackLinearRamSearches;
1577	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1578	STAMCOUNTER StamTrackPhysExtAllocFailures;
1579	# endif
1580	# ifdef PGMPOOL_WITH_MONITORING
1581	/** Profiling the GC PT access handler. */
1582	STAMPROFILE StatMonitorGC;
1583	/** Times we've failed interpreting the instruction. */
1584	STAMCOUNTER StatMonitorGCEmulateInstr;
1585	/** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1586	STAMPROFILE StatMonitorGCFlushPage;
1587	/** Times we've detected fork(). */
1588	STAMCOUNTER StatMonitorGCFork;
1589	/** Profiling the GC access we've handled (except REP STOSD). */
1590	STAMPROFILE StatMonitorGCHandled;
1591	/** Times we've failed interpreting a patch code instruction. */
1592	STAMCOUNTER StatMonitorGCIntrFailPatch1;
1593	/** Times we've failed interpreting a patch code instruction during flushing. */
1594	STAMCOUNTER StatMonitorGCIntrFailPatch2;
1595	/** The number of times we've seen rep prefixes we can't handle. */
1596	STAMCOUNTER StatMonitorGCRepPrefix;
1597	/** Profiling the REP STOSD cases we've handled. */
1598	STAMPROFILE StatMonitorGCRepStosd;
1599
1600	/** Profiling the HC PT access handler. */
1601	STAMPROFILE StatMonitorHC;
1602	/** Times we've failed interpreting the instruction. */
1603	STAMCOUNTER StatMonitorHCEmulateInstr;
1604	/** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1605	STAMPROFILE StatMonitorHCFlushPage;
1606	/** Times we've detected fork(). */
1607	STAMCOUNTER StatMonitorHCFork;
1608	/** Profiling the HC access we've handled (except REP STOSD). */
1609	STAMPROFILE StatMonitorHCHandled;
1610	/** The number of times we've seen rep prefixes we can't handle. */
1611	STAMCOUNTER StatMonitorHCRepPrefix;
1612	/** Profiling the REP STOSD cases we've handled. */
1613	STAMPROFILE StatMonitorHCRepStosd;
1614	/** The number of times we're called in an async thread an need to flush. */
1615	STAMCOUNTER StatMonitorHCAsync;
1616	/** The high wather mark for cModifiedPages. */
1617	uint16_t cModifiedPagesHigh;
1618	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1619	# endif
1620	# ifdef PGMPOOL_WITH_CACHE
1621	/** The number of cache hits. */
1622	STAMCOUNTER StatCacheHits;
1623	/** The number of cache misses. */
1624	STAMCOUNTER StatCacheMisses;
1625	/** The number of times we've got a conflict of 'kind' in the cache. */
1626	STAMCOUNTER StatCacheKindMismatches;
1627	/** Number of times we've been out of pages. */
1628	STAMCOUNTER StatCacheFreeUpOne;
1629	/** The number of cacheable allocations. */
1630	STAMCOUNTER StatCacheCacheable;
1631	/** The number of uncacheable allocations. */
1632	STAMCOUNTER StatCacheUncacheable;
1633	# endif
1634	#elif HC_ARCH_BITS == 64
1635	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1636	#endif
1637	/** The AVL tree for looking up a page by its HC physical address. */
1638	AVLOHCPHYSTREE HCPhysTree;
1639	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1640	/** Array of pages. (cMaxPages in length)
1641	* The Id is the index into thist array.
1642	*/
1643	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1644	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1645
1646
1647	/** @def PGMPOOL_PAGE_2_PTR
1648	* Maps a pool page pool into the current context.
1649	*
1650	* @returns VBox status code.
1651	* @param pVM The VM handle.
1652	* @param pPage The pool page.
1653	*
1654	* @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1655	* small page window employeed by that function. Be careful.
1656	* @remark There is no need to assert on the result.
1657	*/
1658	#ifdef IN_GC
1659	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1660	#else
1661	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1662	#endif
1663
1664
1665	/**
1666	* Trees are using self relative offsets as pointers.
1667	* So, all its data, including the root pointer, must be in the heap for HC and GC
1668	* to have the same layout.
1669	*/
1670	typedef struct PGMTREES
1671	{
1672	/** Physical access handlers (AVL range+offsetptr tree). */
1673	AVLROGCPHYSTREE PhysHandlers;
1674	/** Virtual access handlers (AVL range + GC ptr tree). */
1675	AVLROGCPTRTREE VirtHandlers;
1676	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1677	AVLROGCPHYSTREE PhysToVirtHandlers;
1678	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1679	AVLROGCPTRTREE HyperVirtHandlers;
1680	} PGMTREES;
1681	/** Pointer to PGM trees. */
1682	typedef PGMTREES *PPGMTREES;
1683
1684
1685	/** @name Paging mode macros
1686	* @{ */
1687	#ifdef IN_GC
1688	# define PGM_CTX(a,b) a##GC##b
1689	# define PGM_CTX_STR(a,b) a "GC" b
1690	# define PGM_CTX_DECL(type) PGMGCDECL(type)
1691	#else
1692	# ifdef IN_RING3
1693	# define PGM_CTX(a,b) a##R3##b
1694	# define PGM_CTX_STR(a,b) a "R3" b
1695	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1696	# else
1697	# define PGM_CTX(a,b) a##R0##b
1698	# define PGM_CTX_STR(a,b) a "R0" b
1699	# define PGM_CTX_DECL(type) PGMDECL(type)
1700	# endif
1701	#endif
1702
1703	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1704	#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1705	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1706	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1707	#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1708	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1709	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1710	#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1711	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1712	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1713	#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1714	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1715	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1716	#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1717	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1718	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1719	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1720
1721	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1722	#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1723	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1724	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1725	#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1726	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1727	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1728	#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1729	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1730	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1731	#define PGM_SHW_NAME_GC_NESTED_STR(name) "pgmGCShwNested" #name
1732	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1733	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1734	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1735
1736	/* Shw_Gst */
1737	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1738	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1739	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1740	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1741	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1742	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1743	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1744	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1745	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1746	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1747	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1748	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1749	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1750	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1751
1752	#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1753	#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1754	#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1755	#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1756	#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1757	#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1758	#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1759	#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1760	#define PGM_BTH_NAME_GC_NESTED_REAL_STR(name) "pgmGCBthNestedReal" #name
1761	#define PGM_BTH_NAME_GC_NESTED_PROT_STR(name) "pgmGCBthNestedProt" #name
1762	#define PGM_BTH_NAME_GC_NESTED_32BIT_STR(name) "pgmGCBthNested32Bit" #name
1763	#define PGM_BTH_NAME_GC_NESTED_PAE_STR(name) "pgmGCBthNestedPAE" #name
1764	#define PGM_BTH_NAME_GC_NESTED_AMD64_STR(name) "pgmGCBthNestedAMD64" #name
1765	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1766	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1767	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1768	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1769	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1770	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1771	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1772	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1773	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1774	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1775	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1776	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1777	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1778	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
1779
1780	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1781	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1782	/** @} */
1783
1784	/**
1785	* Data for each paging mode.
1786	*/
1787	typedef struct PGMMODEDATA
1788	{
1789	/** The guest mode type. */
1790	uint32_t uGstType;
1791	/** The shadow mode type. */
1792	uint32_t uShwType;
1793
1794	/** @name Function pointers for Shadow paging.
1795	* @{
1796	*/
1797	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1798	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1799	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1800	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1801
1802	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1803	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1804
1805	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1806	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1807	/** @} */
1808
1809	/** @name Function pointers for Guest paging.
1810	* @{
1811	*/
1812	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1813	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1814	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1815	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1816	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1817	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1818	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1819	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1820	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1821	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1822	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1823	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1824	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1825
1826	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1827	DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1828	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1829	DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1830	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1831	DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1832	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1833	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1834	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1835
1836	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1837	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1838	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1839	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1840	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1841	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1842	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1843	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1844	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1845	/** @} */
1846
1847	/** @name Function pointers for Both Shadow and Guest paging.
1848	* @{
1849	*/
1850	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1851	DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1852	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1853	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1854	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1855	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1856	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1857	#ifdef VBOX_STRICT
1858	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1859	#endif
1860
1861	DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1862	DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1863	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1864	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1865	DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1866	DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1867	#ifdef VBOX_STRICT
1868	DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1869	#endif
1870
1871	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1872	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1873	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1874	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1875	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1876	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1877	#ifdef VBOX_STRICT
1878	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1879	#endif
1880	/** @} */
1881	} PGMMODEDATA, *PPGMMODEDATA;
1882
1883
1884
1885	/**
1886	* Converts a PGM pointer into a VM pointer.
1887	* @returns Pointer to the VM structure the PGM is part of.
1888	* @param pPGM Pointer to PGM instance data.
1889	*/
1890	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1891
1892	/**
1893	* PGM Data (part of VM)
1894	*/
1895	typedef struct PGM
1896	{
1897	/** Offset to the VM structure. */
1898	RTINT offVM;
1899
1900	/*
1901	* This will be redefined at least two more times before we're done, I'm sure.
1902	* The current code is only to get on with the coding.
1903	* - 2004-06-10: initial version, bird.
1904	* - 2004-07-02: 1st time, bird.
1905	* - 2004-10-18: 2nd time, bird.
1906	* - 2005-07-xx: 3rd time, bird.
1907	*/
1908
1909	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1910	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1911	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1912	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1913
1914	/** The host paging mode. (This is what SUPLib reports.) */
1915	SUPPAGINGMODE enmHostMode;
1916	/** The shadow paging mode. */
1917	PGMMODE enmShadowMode;
1918	/** The guest paging mode. */
1919	PGMMODE enmGuestMode;
1920
1921	/** The current physical address representing in the guest CR3 register. */
1922	RTGCPHYS GCPhysCR3;
1923	/** Pointer to the 5 page CR3 content mapping.
1924	* The first page is always the CR3 (in some form) while the 4 other pages
1925	* are used of the PDs in PAE mode. */
1926	RTGCPTR GCPtrCR3Mapping;
1927	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1928	uint32_t u32Alignment;
1929	#endif
1930	/** The physical address of the currently monitored guest CR3 page.
1931	* When this value is NIL_RTGCPHYS no page is being monitored. */
1932	RTGCPHYS GCPhysGstCR3Monitored;
1933
1934	/** @name 32-bit Guest Paging.
1935	* @{ */
1936	/** The guest's page directory, HC pointer. */
1937	R3R0PTRTYPE(PX86PD) pGuestPDHC;
1938	/** The guest's page directory, static GC mapping. */
1939	RCPTRTYPE(PX86PD) pGuestPDGC;
1940	/** @} */
1941
1942	/** @name PAE Guest Paging.
1943	* @{ */
1944	/** The guest's page directory pointer table, static GC mapping. */
1945	RCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1946	/** The guest's page directory pointer table, HC pointer. */
1947	R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1948	/** The guest's page directories, HC pointers.
1949	* These are individual pointers and don't have to be adjecent.
1950	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1951	R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1952	/** The guest's page directories, static GC mapping.
1953	* Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1954	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1955	RCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1956	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1957	RTGCPHYS aGCPhysGstPaePDs[4];
1958	/** The physical addresses of the monitored guest page directories (PAE). */
1959	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1960	/** @} */
1961
1962	/** @name AMD64 Guest Paging.
1963	* @{ */
1964	/** The guest's page directory pointer table, HC pointer. */
1965	R3R0PTRTYPE(PX86PML4) pGstPaePML4HC;
1966	/** @} */
1967
1968	/** @name 32-bit Shadow Paging
1969	* @{ */
1970	/** The 32-Bit PD - HC Ptr. */
1971	R3R0PTRTYPE(PX86PD) pHC32BitPD;
1972	/** The 32-Bit PD - GC Ptr. */
1973	RCPTRTYPE(PX86PD) pGC32BitPD;
1974	#if HC_ARCH_BITS == 64
1975	uint32_t u32Padding1; /*< alignment padding. /
1976	#endif
1977	/** The Physical Address (HC) of the 32-Bit PD. */
1978	RTHCPHYS HCPhys32BitPD;
1979	/** @} */
1980
1981	/** @name PAE Shadow Paging
1982	* @{ */
1983	/** The four PDs for the low 4GB - HC Ptr.
1984	* Even though these are 4 pointers, what they point at is a single table.
1985	* Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1986	R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1987	/** The four PDs for the low 4GB - GC Ptr.
1988	* Same kind of mapping as apHCPaePDs. */
1989	RCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1990	/** The Physical Address (HC) of the four PDs for the low 4GB.
1991	* These are NOT 4 contiguous pages. */
1992	RTHCPHYS aHCPhysPaePDs[4];
1993	/** The PAE PDP - HC Ptr. */
1994	R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
1995	/** The Physical Address (HC) of the PAE PDPT. */
1996	RTHCPHYS HCPhysPaePDPT;
1997	/** The PAE PDPT - GC Ptr. */
1998	RCPTRTYPE(PX86PDPT) pGCPaePDPT;
1999	/** @} */
2000
2001	/** @name AMD64 Shadow Paging
2002	* Extends PAE Paging.
2003	* @{ */
2004	#if HC_ARCH_BITS == 64
2005	RTRCPTR alignment5; /*< structure size alignment. /
2006	#endif
2007	/** The Page Map Level 4 table - HC Ptr. */
2008	R3R0PTRTYPE(PX86PML4) pHCPaePML4;
2009	/** The Physical Address (HC) of the Page Map Level 4 table. */
2010	RTHCPHYS HCPhysPaePML4;
2011	/** The pgm pool page descriptor for the current active CR3. */
2012	R3R0PTRTYPE(PPGMPOOLPAGE) pHCShwAmd64CR3;
2013
2014	/** @}*/
2015
2016	/** @name Nested Shadow Paging
2017	* @{ */
2018	/** Root table; format depends on the host paging mode (AMD-V) or EPT */
2019	R3R0PTRTYPE(void *) pHCNestedRoot;
2020	/** The Physical Address (HC) of the nested paging root. */
2021	RTHCPHYS HCPhysNestedRoot;
2022
2023	/** @name Function pointers for Shadow paging.
2024	* @{
2025	*/
2026	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2027	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2028	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2029	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2030
2031	DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2032	DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2033
2034	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2035	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2036
2037	/** @} */
2038
2039	/** @name Function pointers for Guest paging.
2040	* @{
2041	*/
2042	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2043	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2044	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2045	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2046	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2047	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2048	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2049	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2050	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2051	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2052	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2053	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2054	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2055
2056	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2057	DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2058	DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2059	DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2060	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
2061	DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2062	DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
2063	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
2064	RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
2065	#if HC_ARCH_BITS == 64
2066	RTRCPTR alignment3; /*< structure size alignment. /
2067	#endif
2068
2069	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2070	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2071	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2072	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2073	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2074	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2075	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2076	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2077	R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2078	/** @} */
2079
2080	/** @name Function pointers for Both Shadow and Guest paging.
2081	* @{
2082	*/
2083	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2084	DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2085	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2086	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2087	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2088	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2089	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2090	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2091
2092	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2093	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2094	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2095	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2096	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2097	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2098	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2099
2100	DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2101	DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2102	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2103	DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2104	DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2105	DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2106	DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2107	#if HC_ARCH_BITS == 64
2108	RTRCPTR alignment2; /*< structure size alignment. /
2109	#endif
2110	/** @} */
2111
2112	/** Pointer to SHW+GST mode data (function pointers).
2113	* The index into this table is made up from */
2114	R3PTRTYPE(PPGMMODEDATA) paModeData;
2115
2116	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2117	* This is sorted by physical address and contains no overlapping ranges. */
2118	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2119	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2120	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2121	/** GC pointer corresponding to PGM::pRamRangesR3. */
2122	RCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
2123	/** The configured RAM size. */
2124	RTUINT cbRamSize;
2125
2126	/** Pointer to the list of ROM ranges - for R3.
2127	* This is sorted by physical address and contains no overlapping ranges. */
2128	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2129	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2130	R0PTRTYPE(PPGMRAMRANGE) pRomRangesR0;
2131	/** GC pointer corresponding to PGM::pRomRangesR3. */
2132	RCPTRTYPE(PPGMRAMRANGE) pRomRangesGC;
2133	/** Alignment padding. */
2134	RTRCPTR GCPtrPadding2;
2135
2136	/** Pointer to the list of MMIO2 ranges - for R3.
2137	* Registration order. */
2138	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2139
2140	/** PGM offset based trees - HC Ptr. */
2141	R3R0PTRTYPE(PPGMTREES) pTreesHC;
2142	/** PGM offset based trees - GC Ptr. */
2143	RCPTRTYPE(PPGMTREES) pTreesGC;
2144
2145	/** Linked list of GC mappings - for GC.
2146	* The list is sorted ascending on address.
2147	*/
2148	RCPTRTYPE(PPGMMAPPING) pMappingsGC;
2149	/** Linked list of GC mappings - for HC.
2150	* The list is sorted ascending on address.
2151	*/
2152	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2153	/** Linked list of GC mappings - for R0.
2154	* The list is sorted ascending on address.
2155	*/
2156	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2157
2158	/** If set no conflict checks are required. (boolean) */
2159	bool fMappingsFixed;
2160	/** If set, then no mappings are put into the shadow page table. (boolean) */
2161	bool fDisableMappings;
2162	/** Size of fixed mapping */
2163	uint32_t cbMappingFixed;
2164	/** Base address (GC) of fixed mapping */
2165	RTGCPTR GCPtrMappingFixed;
2166	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2167	uint32_t u32Padding0; /*< alignment padding. /
2168	#endif
2169
2170
2171	/** @name Intermediate Context
2172	* @{ */
2173	/** Pointer to the intermediate page directory - Normal. */
2174	R3PTRTYPE(PX86PD) pInterPD;
2175	/** Pointer to the intermedate page tables - Normal.
2176	* There are two page tables, one for the identity mapping and one for
2177	* the host context mapping (of the core code). */
2178	R3PTRTYPE(PX86PT) apInterPTs[2];
2179	/** Pointer to the intermedate page tables - PAE. */
2180	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2181	/** Pointer to the intermedate page directory - PAE. */
2182	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2183	/** Pointer to the intermedate page directory - PAE. */
2184	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2185	/** Pointer to the intermedate page-map level 4 - AMD64. */
2186	R3PTRTYPE(PX86PML4) pInterPaePML4;
2187	/** Pointer to the intermedate page directory - AMD64. */
2188	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2189	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2190	RTHCPHYS HCPhysInterPD;
2191	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2192	RTHCPHYS HCPhysInterPaePDPT;
2193	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2194	RTHCPHYS HCPhysInterPaePML4;
2195	/** @} */
2196
2197	/** Base address of the dynamic page mapping area.
2198	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2199	*/
2200	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2201	/** The index of the last entry used in the dynamic page mapping area. */
2202	RTUINT iDynPageMapLast;
2203	/** Cache containing the last entries in the dynamic page mapping area.
2204	* The cache size is covering half of the mapping area. */
2205	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2206
2207	/** A20 gate mask.
2208	* Our current approach to A20 emulation is to let REM do it and don't bother
2209	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2210	* But whould need arrise, we'll subject physical addresses to this mask. */
2211	RTGCPHYS GCPhysA20Mask;
2212	/** A20 gate state - boolean! */
2213	RTUINT fA20Enabled;
2214
2215	/** What needs syncing (PGM_SYNC_*).
2216	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2217	* PGMFlushTLB, and PGMR3Load. */
2218	RTUINT fSyncFlags;
2219
2220	/** PGM critical section.
2221	* This protects the physical & virtual access handlers, ram ranges,
2222	* and the page flag updating (some of it anyway).
2223	*/
2224	PDMCRITSECT CritSect;
2225
2226	/** Shadow Page Pool - HC Ptr. */
2227	R3R0PTRTYPE(PPGMPOOL) pPoolHC;
2228	/** Shadow Page Pool - GC Ptr. */
2229	RCPTRTYPE(PPGMPOOL) pPoolGC;
2230
2231	/** We're not in a state which permits writes to guest memory.
2232	* (Only used in strict builds.) */
2233	bool fNoMorePhysWrites;
2234
2235	/** Flush the cache on the next access. */
2236	bool fPhysCacheFlushPending;
2237	/** @todo r=bird: Fix member names!*/
2238	/** PGMPhysRead cache */
2239	PGMPHYSCACHE pgmphysreadcache;
2240	/** PGMPhysWrite cache */
2241	PGMPHYSCACHE pgmphyswritecache;
2242
2243	/**
2244	* Data associated with managing the ring-3 mappings of the allocation chunks.
2245	*/
2246	struct
2247	{
2248	/** The chunk tree, ordered by chunk id. */
2249	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2250	/** The chunk mapping TLB. */
2251	PGMCHUNKR3MAPTLB Tlb;
2252	/** The number of mapped chunks. */
2253	uint32_t c;
2254	/** The maximum number of mapped chunks.
2255	* @cfgm PGM/MaxRing3Chunks */
2256	uint32_t cMax;
2257	/** The chunk age tree, ordered by ageing sequence number. */
2258	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2259	/** The current time. */
2260	uint32_t iNow;
2261	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2262	uint32_t AgeingCountdown;
2263	} ChunkR3Map;
2264
2265	/**
2266	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2267	*/
2268	PGMPAGER3MAPTLB PhysTlbHC;
2269
2270	/** @name The zero page.
2271	* @{ */
2272	/** The host physical address of the zero page. */
2273	RTHCPHYS HCPhysZeroPg;
2274	/** The ring-3 mapping of the zero page. */
2275	RTR3PTR pvZeroPgR3;
2276	/** The ring-0 mapping of the zero page. */
2277	RTR0PTR pvZeroPgR0;
2278	/** The GC mapping of the zero page. */
2279	RTGCPTR pvZeroPgGC;
2280	#if GC_ARCH_BITS != 32
2281	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2282	#endif
2283	/** @}*/
2284
2285	/** The number of handy pages. */
2286	uint32_t cHandyPages;
2287	/**
2288	* Array of handy pages.
2289	*
2290	* This array is used in a two way communication between pgmPhysAllocPage
2291	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2292	* an intermediary.
2293	*
2294	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2295	* (The current size of 32 pages, means 128 KB of handy memory.)
2296	*/
2297	GMMPAGEDESC aHandyPages[32];
2298
2299	/** @name Release Statistics
2300	* @{ */
2301	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2302	uint32_t cPrivatePages; /*< The number of private pages. /
2303	uint32_t cSharedPages; /*< The number of shared pages. /
2304	uint32_t cZeroPages; /*< The number of zero backed pages. /
2305	/** The number of times the guest has switched mode since last reset or statistics reset. */
2306	STAMCOUNTER cGuestModeChanges;
2307	/** @} */
2308
2309	#ifdef VBOX_WITH_STATISTICS
2310	/** GC: Which statistic this \#PF should be attributed to. */
2311	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
2312	RTRCPTR padding0;
2313	/** HC: Which statistic this \#PF should be attributed to. */
2314	R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
2315	RTHCPTR padding1;
2316	STAMPROFILE StatGCTrap0e; /*< GC: PGMGCTrap0eHandler() profiling. /
2317	STAMPROFILE StatTrap0eCSAM; /*< Profiling of the Trap0eHandler body when the cause is CSAM. /
2318	STAMPROFILE StatTrap0eDirtyAndAccessedBits; /*< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2319	STAMPROFILE StatTrap0eGuestTrap; /*< Profiling of the Trap0eHandler body when the cause is a guest trap. /
2320	STAMPROFILE StatTrap0eHndPhys; /*< Profiling of the Trap0eHandler body when the cause is a physical handler. /
2321	STAMPROFILE StatTrap0eHndVirt; /*< Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2322	STAMPROFILE StatTrap0eHndUnhandled; /*< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2323	STAMPROFILE StatTrap0eMisc; /*< Profiling of the Trap0eHandler body when the cause is not known. /
2324	STAMPROFILE StatTrap0eOutOfSync; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2325	STAMPROFILE StatTrap0eOutOfSyncHndPhys; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2326	STAMPROFILE StatTrap0eOutOfSyncHndVirt; /*< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2327	STAMPROFILE StatTrap0eOutOfSyncObsHnd; /*< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2328	STAMPROFILE StatTrap0eSyncPT; /*< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2329
2330	STAMCOUNTER StatTrap0eMapHandler; /*< Number of traps due to access handlers in mappings. /
2331	STAMCOUNTER StatGCTrap0eConflicts; /*< GC: The number of times \#PF was caused by an undetected conflict. /
2332
2333	STAMCOUNTER StatGCTrap0eUSNotPresentRead;
2334	STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
2335	STAMCOUNTER StatGCTrap0eUSWrite;
2336	STAMCOUNTER StatGCTrap0eUSReserved;
2337	STAMCOUNTER StatGCTrap0eUSNXE;
2338	STAMCOUNTER StatGCTrap0eUSRead;
2339
2340	STAMCOUNTER StatGCTrap0eSVNotPresentRead;
2341	STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
2342	STAMCOUNTER StatGCTrap0eSVWrite;
2343	STAMCOUNTER StatGCTrap0eSVReserved;
2344	STAMCOUNTER StatGCTrap0eSNXE;
2345
2346	STAMCOUNTER StatTrap0eWPEmulGC;
2347	STAMCOUNTER StatTrap0eWPEmulR3;
2348
2349	STAMCOUNTER StatGCTrap0eUnhandled;
2350	STAMCOUNTER StatGCTrap0eMap;
2351
2352	/** GC: PGMSyncPT() profiling. */
2353	STAMPROFILE StatGCSyncPT;
2354	/** GC: The number of times PGMSyncPT() needed to allocate page tables. */
2355	STAMCOUNTER StatGCSyncPTAlloc;
2356	/** GC: The number of times PGMSyncPT() detected conflicts. */
2357	STAMCOUNTER StatGCSyncPTConflict;
2358	/** GC: The number of times PGMSyncPT() failed. */
2359	STAMCOUNTER StatGCSyncPTFailed;
2360	/** GC: PGMGCInvalidatePage() profiling. */
2361	STAMPROFILE StatGCInvalidatePage;
2362	/** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
2363	STAMCOUNTER StatGCInvalidatePage4KBPages;
2364	/** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
2365	STAMCOUNTER StatGCInvalidatePage4MBPages;
2366	/** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
2367	STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
2368	/** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
2369	STAMCOUNTER StatGCInvalidatePagePDNAs;
2370	/** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
2371	STAMCOUNTER StatGCInvalidatePagePDNPs;
2372	/** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
2373	STAMCOUNTER StatGCInvalidatePagePDMappings;
2374	/** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2375	STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
2376	/** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2377	STAMCOUNTER StatGCInvalidatePageSkipped;
2378	/** GC: The number of times user page is out of sync was detected in GC. */
2379	STAMCOUNTER StatGCPageOutOfSyncUser;
2380	/** GC: The number of times supervisor page is out of sync was detected in GC. */
2381	STAMCOUNTER StatGCPageOutOfSyncSupervisor;
2382	/** GC: The number of dynamic page mapping cache hits */
2383	STAMCOUNTER StatDynMapCacheMisses;
2384	/** GC: The number of dynamic page mapping cache misses */
2385	STAMCOUNTER StatDynMapCacheHits;
2386	/** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
2387	STAMCOUNTER StatGCGuestCR3WriteHandled;
2388	/** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
2389	STAMCOUNTER StatGCGuestCR3WriteUnhandled;
2390	/** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
2391	STAMCOUNTER StatGCGuestCR3WriteConflict;
2392	/** GC: Number of out-of-sync handled pages. */
2393	STAMCOUNTER StatHandlersOutOfSync;
2394	/** GC: Number of traps due to physical access handlers. */
2395	STAMCOUNTER StatHandlersPhysical;
2396	/** GC: Number of traps due to virtual access handlers. */
2397	STAMCOUNTER StatHandlersVirtual;
2398	/** GC: Number of traps due to virtual access handlers found by physical address. */
2399	STAMCOUNTER StatHandlersVirtualByPhys;
2400	/** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2401	STAMCOUNTER StatHandlersVirtualUnmarked;
2402	/** GC: Number of traps due to access outside range of monitored page(s). */
2403	STAMCOUNTER StatHandlersUnhandled;
2404	/** GC: Number of traps due to access to invalid physical memory. */
2405	STAMCOUNTER StatHandlersInvalid;
2406
2407	/** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
2408	STAMCOUNTER StatGCGuestROMWriteHandled;
2409	/** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
2410	STAMCOUNTER StatGCGuestROMWriteUnhandled;
2411
2412	/** HC: PGMR3InvalidatePage() profiling. */
2413	STAMPROFILE StatHCInvalidatePage;
2414	/** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
2415	STAMCOUNTER StatHCInvalidatePage4KBPages;
2416	/** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2417	STAMCOUNTER StatHCInvalidatePage4MBPages;
2418	/** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2419	STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2420	/** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2421	STAMCOUNTER StatHCInvalidatePagePDNAs;
2422	/** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2423	STAMCOUNTER StatHCInvalidatePagePDNPs;
2424	/** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2425	STAMCOUNTER StatHCInvalidatePagePDMappings;
2426	/** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2427	STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2428	/** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2429	STAMCOUNTER StatHCInvalidatePageSkipped;
2430	/** HC: PGMR3SyncPT() profiling. */
2431	STAMPROFILE StatHCSyncPT;
2432	/** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2433	STAMPROFILE StatHCResolveConflict;
2434	/** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2435	STAMCOUNTER StatHCDetectedConflicts;
2436	/** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2437	STAMCOUNTER StatHCGuestPDWrite;
2438	/** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2439	STAMCOUNTER StatHCGuestPDWriteConflict;
2440
2441	/** HC: The number of pages marked not present for accessed bit emulation. */
2442	STAMCOUNTER StatHCAccessedPage;
2443	/** HC: The number of pages marked read-only for dirty bit tracking. */
2444	STAMCOUNTER StatHCDirtyPage;
2445	/** HC: The number of pages marked read-only for dirty bit tracking. */
2446	STAMCOUNTER StatHCDirtyPageBig;
2447	/** HC: The number of traps generated for dirty bit tracking. */
2448	STAMCOUNTER StatHCDirtyPageTrap;
2449	/** HC: The number of pages already dirty or readonly. */
2450	STAMCOUNTER StatHCDirtyPageSkipped;
2451
2452	/** GC: The number of pages marked not present for accessed bit emulation. */
2453	STAMCOUNTER StatGCAccessedPage;
2454	/** GC: The number of pages marked read-only for dirty bit tracking. */
2455	STAMCOUNTER StatGCDirtyPage;
2456	/** GC: The number of pages marked read-only for dirty bit tracking. */
2457	STAMCOUNTER StatGCDirtyPageBig;
2458	/** GC: The number of traps generated for dirty bit tracking. */
2459	STAMCOUNTER StatGCDirtyPageTrap;
2460	/** GC: The number of pages already dirty or readonly. */
2461	STAMCOUNTER StatGCDirtyPageSkipped;
2462	/** GC: The number of pages marked dirty because of write accesses. */
2463	STAMCOUNTER StatGCDirtiedPage;
2464	/** GC: The number of pages already marked dirty because of write accesses. */
2465	STAMCOUNTER StatGCPageAlreadyDirty;
2466	/** GC: The number of real pages faults during dirty bit tracking. */
2467	STAMCOUNTER StatGCDirtyTrackRealPF;
2468
2469	/** GC: Profiling of the PGMTrackDirtyBit() body */
2470	STAMPROFILE StatGCDirtyBitTracking;
2471	/** HC: Profiling of the PGMTrackDirtyBit() body */
2472	STAMPROFILE StatHCDirtyBitTracking;
2473
2474	/** GC: Profiling of the PGMGstModifyPage() body */
2475	STAMPROFILE StatGCGstModifyPage;
2476	/** HC: Profiling of the PGMGstModifyPage() body */
2477	STAMPROFILE StatHCGstModifyPage;
2478
2479	/** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2480	STAMCOUNTER StatGCSyncPagePDNAs;
2481	/** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2482	STAMCOUNTER StatGCSyncPagePDOutOfSync;
2483	/** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2484	STAMCOUNTER StatHCSyncPagePDNAs;
2485	/** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2486	STAMCOUNTER StatHCSyncPagePDOutOfSync;
2487
2488	STAMCOUNTER StatSynPT4kGC;
2489	STAMCOUNTER StatSynPT4kHC;
2490	STAMCOUNTER StatSynPT4MGC;
2491	STAMCOUNTER StatSynPT4MHC;
2492
2493	/** Profiling of the PGMFlushTLB() body. */
2494	STAMPROFILE StatFlushTLB;
2495	/** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2496	STAMCOUNTER StatFlushTLBNewCR3;
2497	/** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2498	STAMCOUNTER StatFlushTLBNewCR3Global;
2499	/** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2500	STAMCOUNTER StatFlushTLBSameCR3;
2501	/** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2502	STAMCOUNTER StatFlushTLBSameCR3Global;
2503
2504	STAMPROFILE StatGCSyncCR3; /*< GC: PGMSyncCR3() profiling. /
2505	STAMPROFILE StatGCSyncCR3Handlers; /*< GC: Profiling of the PGMSyncCR3() update handler section. /
2506	STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /*< GC: Profiling of the virtual handler resets. /
2507	STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /*< GC: Profiling of the virtual handler updates. /
2508	STAMCOUNTER StatGCSyncCR3Global; /*< GC: The number of global CR3 syncs. /
2509	STAMCOUNTER StatGCSyncCR3NotGlobal; /*< GC: The number of non-global CR3 syncs. /
2510	STAMCOUNTER StatGCSyncCR3DstFreed; /*< GC: The number of times we've had to free a shadow entry. /
2511	STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /*< GC: The number of times we've had to free a shadow entry for which the source entry was not present. /
2512	STAMCOUNTER StatGCSyncCR3DstNotPresent; /*< GC: The number of times we've encountered a not present shadow entry for a present guest entry. /
2513	STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /*< GC: The number of times a global page directory wasn't flushed. /
2514	STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /*< GC: The number of times a page table with only global entries wasn't flushed. /
2515	STAMCOUNTER StatGCSyncCR3DstCacheHit; /*< GC: The number of times we got some kind of cache hit on a page table. /
2516
2517	STAMPROFILE StatHCSyncCR3; /*< HC: PGMSyncCR3() profiling. /
2518	STAMPROFILE StatHCSyncCR3Handlers; /*< HC: Profiling of the PGMSyncCR3() update handler section. /
2519	STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /*< HC: Profiling of the virtual handler resets. /
2520	STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /*< HC: Profiling of the virtual handler updates. /
2521	STAMCOUNTER StatHCSyncCR3Global; /*< HC: The number of global CR3 syncs. /
2522	STAMCOUNTER StatHCSyncCR3NotGlobal; /*< HC: The number of non-global CR3 syncs. /
2523	STAMCOUNTER StatHCSyncCR3DstFreed; /*< HC: The number of times we've had to free a shadow entry. /
2524	STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /*< HC: The number of times we've had to free a shadow entry for which the source entry was not present. /
2525	STAMCOUNTER StatHCSyncCR3DstNotPresent; /*< HC: The number of times we've encountered a not present shadow entry for a present guest entry. /
2526	STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /*< HC: The number of times a global page directory wasn't flushed. /
2527	STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /*< HC: The number of times a page table with only global entries wasn't flushed. /
2528	STAMCOUNTER StatHCSyncCR3DstCacheHit; /*< HC: The number of times we got some kind of cache hit on a page table. /
2529
2530	/** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2531	STAMPROFILE StatVirtHandleSearchByPhysGC;
2532	/** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2533	STAMPROFILE StatVirtHandleSearchByPhysHC;
2534	/** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2535	STAMCOUNTER StatHandlePhysicalReset;
2536
2537	STAMPROFILE StatCheckPageFault;
2538	STAMPROFILE StatLazySyncPT;
2539	STAMPROFILE StatMapping;
2540	STAMPROFILE StatOutOfSync;
2541	STAMPROFILE StatHandlers;
2542	STAMPROFILE StatEIPHandlers;
2543	STAMPROFILE StatHCPrefetch;
2544
2545	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2546	/** The number of first time shadowings. */
2547	STAMCOUNTER StatTrackVirgin;
2548	/** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2549	STAMCOUNTER StatTrackAliased;
2550	/** The number of times we're tracking using cRef2. */
2551	STAMCOUNTER StatTrackAliasedMany;
2552	/** The number of times we're hitting pages which has overflowed cRef2. */
2553	STAMCOUNTER StatTrackAliasedLots;
2554	/** The number of times the extent list grows to long. */
2555	STAMCOUNTER StatTrackOverflows;
2556	/** Profiling of SyncPageWorkerTrackDeref (expensive). */
2557	STAMPROFILE StatTrackDeref;
2558	# endif
2559
2560	/** Ring-3/0 page mapper TLB hits. */
2561	STAMCOUNTER StatPageHCMapTlbHits;
2562	/** Ring-3/0 page mapper TLB misses. */
2563	STAMCOUNTER StatPageHCMapTlbMisses;
2564	/** Ring-3/0 chunk mapper TLB hits. */
2565	STAMCOUNTER StatChunkR3MapTlbHits;
2566	/** Ring-3/0 chunk mapper TLB misses. */
2567	STAMCOUNTER StatChunkR3MapTlbMisses;
2568	/** Times a shared page has been replaced by a private one. */
2569	STAMCOUNTER StatPageReplaceShared;
2570	/** Times the zero page has been replaced by a private one. */
2571	STAMCOUNTER StatPageReplaceZero;
2572	/** The number of times we've executed GMMR3AllocateHandyPages. */
2573	STAMCOUNTER StatPageHandyAllocs;
2574
2575	/** Allocated mbs of guest ram */
2576	STAMCOUNTER StatDynRamTotal;
2577	/** Nr of pgmr3PhysGrowRange calls. */
2578	STAMCOUNTER StatDynRamGrow;
2579
2580	STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2581	STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2582	STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2583	#endif
2584	} PGM, *PPGM;
2585
2586
2587	/** @name PGM::fSyncFlags Flags
2588	* @{
2589	*/
2590	/** Updates the virtual access handler state bit in PGMPAGE. */
2591	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2592	/** Always sync CR3. */
2593	#define PGM_SYNC_ALWAYS RT_BIT(1)
2594	/** Check monitoring on next CR3 (re)load and invalidate page. */
2595	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2596	/** Clear the page pool (a light weight flush). */
2597	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2598	/** @} */
2599
2600
2601	__BEGIN_DECLS
2602
2603	int pgmLock(PVM pVM);
2604	void pgmUnlock(PVM pVM);
2605
2606	PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2607	PGMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2608
2609	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2610	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2611	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2612	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2613	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2614
2615	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2616	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2617	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2618	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2619	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2620	#else
2621	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2622	#endif
2623	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2624
2625
2626	void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2627	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2628	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2629	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2630	#ifdef IN_RING3
2631	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2632	int pgmR3PhysRamReset(PVM pVM);
2633	int pgmR3PhysRomReset(PVM pVM);
2634	#ifndef VBOX_WITH_NEW_PHYS_CODE
2635	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2636	#endif
2637
2638	int pgmR3PoolInit(PVM pVM);
2639	void pgmR3PoolRelocate(PVM pVM);
2640	void pgmR3PoolReset(PVM pVM);
2641
2642	#endif /* IN_RING3 */
2643	#ifdef IN_GC
2644	void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2645	#endif
2646	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2647	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2648	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2649	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2650	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2651	void pgmPoolFlushAll(PVM pVM);
2652	void pgmPoolClearAll(PVM pVM);
2653	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2654	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2655	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2656	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2657	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2658	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2659	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2660	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2661	#ifdef PGMPOOL_WITH_MONITORING
2662	# ifdef IN_RING3
2663	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2664	# else
2665	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2666	# endif
2667	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2668	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2669	void pgmPoolMonitorModifiedClearAll(PVM pVM);
2670	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2671	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2672	#endif
2673
2674	__END_DECLS
2675
2676
2677	/**
2678	* Gets the PGMRAMRANGE structure for a guest page.
2679	*
2680	* @returns Pointer to the RAM range on success.
2681	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2682	*
2683	* @param pPGM PGM handle.
2684	* @param GCPhys The GC physical address.
2685	*/
2686	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2687	{
2688	/*
2689	* Optimize for the first range.
2690	*/
2691	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2692	RTGCPHYS off = GCPhys - pRam->GCPhys;
2693	if (RT_UNLIKELY(off >= pRam->cb))
2694	{
2695	do
2696	{
2697	pRam = CTXALLSUFF(pRam->pNext);
2698	if (RT_UNLIKELY(!pRam))
2699	break;
2700	off = GCPhys - pRam->GCPhys;
2701	} while (off >= pRam->cb);
2702	}
2703	return pRam;
2704	}
2705
2706
2707	/**
2708	* Gets the PGMPAGE structure for a guest page.
2709	*
2710	* @returns Pointer to the page on success.
2711	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2712	*
2713	* @param pPGM PGM handle.
2714	* @param GCPhys The GC physical address.
2715	*/
2716	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2717	{
2718	/*
2719	* Optimize for the first range.
2720	*/
2721	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2722	RTGCPHYS off = GCPhys - pRam->GCPhys;
2723	if (RT_UNLIKELY(off >= pRam->cb))
2724	{
2725	do
2726	{
2727	pRam = CTXALLSUFF(pRam->pNext);
2728	if (RT_UNLIKELY(!pRam))
2729	return NULL;
2730	off = GCPhys - pRam->GCPhys;
2731	} while (off >= pRam->cb);
2732	}
2733	return &pRam->aPages[off >> PAGE_SHIFT];
2734	}
2735
2736
2737	/**
2738	* Gets the PGMPAGE structure for a guest page.
2739	*
2740	* Old Phys code: Will make sure the page is present.
2741	*
2742	* @returns VBox status code.
2743	* @retval VINF_SUCCESS and a valid *ppPage on success.
2744	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2745	*
2746	* @param pPGM PGM handle.
2747	* @param GCPhys The GC physical address.
2748	* @param ppPage Where to store the page poitner on success.
2749	*/
2750	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2751	{
2752	/*
2753	* Optimize for the first range.
2754	*/
2755	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2756	RTGCPHYS off = GCPhys - pRam->GCPhys;
2757	if (RT_UNLIKELY(off >= pRam->cb))
2758	{
2759	do
2760	{
2761	pRam = CTXALLSUFF(pRam->pNext);
2762	if (RT_UNLIKELY(!pRam))
2763	{
2764	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
2765	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2766	}
2767	off = GCPhys - pRam->GCPhys;
2768	} while (off >= pRam->cb);
2769	}
2770	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2771	#ifndef VBOX_WITH_NEW_PHYS_CODE
2772
2773	/*
2774	* Make sure it's present.
2775	*/
2776	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2777	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2778	{
2779	#ifdef IN_RING3
2780	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2781	#else
2782	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2783	#endif
2784	if (VBOX_FAILURE(rc))
2785	{
2786	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
2787	return rc;
2788	}
2789	Assert(rc == VINF_SUCCESS);
2790	}
2791	#endif
2792	return VINF_SUCCESS;
2793	}
2794
2795
2796
2797
2798	/**
2799	* Gets the PGMPAGE structure for a guest page.
2800	*
2801	* Old Phys code: Will make sure the page is present.
2802	*
2803	* @returns VBox status code.
2804	* @retval VINF_SUCCESS and a valid *ppPage on success.
2805	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2806	*
2807	* @param pPGM PGM handle.
2808	* @param GCPhys The GC physical address.
2809	* @param ppPage Where to store the page poitner on success.
2810	* @param ppRamHint Where to read and store the ram list hint.
2811	* The caller initializes this to NULL before the call.
2812	*/
2813	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2814	{
2815	RTGCPHYS off;
2816	PPGMRAMRANGE pRam = *ppRamHint;
2817	if ( !pRam
2818	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2819	{
2820	pRam = CTXALLSUFF(pPGM->pRamRanges);
2821	off = GCPhys - pRam->GCPhys;
2822	if (RT_UNLIKELY(off >= pRam->cb))
2823	{
2824	do
2825	{
2826	pRam = CTXALLSUFF(pRam->pNext);
2827	if (RT_UNLIKELY(!pRam))
2828	{
2829	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
2830	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2831	}
2832	off = GCPhys - pRam->GCPhys;
2833	} while (off >= pRam->cb);
2834	}
2835	*ppRamHint = pRam;
2836	}
2837	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2838	#ifndef VBOX_WITH_NEW_PHYS_CODE
2839
2840	/*
2841	* Make sure it's present.
2842	*/
2843	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2844	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2845	{
2846	#ifdef IN_RING3
2847	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2848	#else
2849	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2850	#endif
2851	if (VBOX_FAILURE(rc))
2852	{
2853	ppPage = NULL; / Shut up annoying smart ass. */
2854	return rc;
2855	}
2856	Assert(rc == VINF_SUCCESS);
2857	}
2858	#endif
2859	return VINF_SUCCESS;
2860	}
2861
2862
2863	/**
2864	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2865	*
2866	* @returns Pointer to the page on success.
2867	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2868	*
2869	* @param pPGM PGM handle.
2870	* @param GCPhys The GC physical address.
2871	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
2872	*/
2873	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2874	{
2875	/*
2876	* Optimize for the first range.
2877	*/
2878	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2879	RTGCPHYS off = GCPhys - pRam->GCPhys;
2880	if (RT_UNLIKELY(off >= pRam->cb))
2881	{
2882	do
2883	{
2884	pRam = CTXALLSUFF(pRam->pNext);
2885	if (RT_UNLIKELY(!pRam))
2886	return NULL;
2887	off = GCPhys - pRam->GCPhys;
2888	} while (off >= pRam->cb);
2889	}
2890	*ppRam = pRam;
2891	return &pRam->aPages[off >> PAGE_SHIFT];
2892	}
2893
2894
2895
2896
2897	/**
2898	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2899	*
2900	* @returns Pointer to the page on success.
2901	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2902	*
2903	* @param pPGM PGM handle.
2904	* @param GCPhys The GC physical address.
2905	* @param ppPage Where to store the pointer to the PGMPAGE structure.
2906	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2907	*/
2908	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2909	{
2910	/*
2911	* Optimize for the first range.
2912	*/
2913	PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2914	RTGCPHYS off = GCPhys - pRam->GCPhys;
2915	if (RT_UNLIKELY(off >= pRam->cb))
2916	{
2917	do
2918	{
2919	pRam = CTXALLSUFF(pRam->pNext);
2920	if (RT_UNLIKELY(!pRam))
2921	{
2922	ppRam = NULL; / Shut up silly GCC warnings. */
2923	ppPage = NULL; / ditto */
2924	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2925	}
2926	off = GCPhys - pRam->GCPhys;
2927	} while (off >= pRam->cb);
2928	}
2929	*ppRam = pRam;
2930	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2931	#ifndef VBOX_WITH_NEW_PHYS_CODE
2932
2933	/*
2934	* Make sure it's present.
2935	*/
2936	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2937	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2938	{
2939	#ifdef IN_RING3
2940	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2941	#else
2942	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2943	#endif
2944	if (VBOX_FAILURE(rc))
2945	{
2946	ppPage = NULL; / Shut up silly GCC warnings. */
2947	ppPage = NULL; / ditto */
2948	return rc;
2949	}
2950	Assert(rc == VINF_SUCCESS);
2951
2952	}
2953	#endif
2954	return VINF_SUCCESS;
2955	}
2956
2957
2958	/**
2959	* Convert GC Phys to HC Phys.
2960	*
2961	* @returns VBox status.
2962	* @param pPGM PGM handle.
2963	* @param GCPhys The GC physical address.
2964	* @param pHCPhys Where to store the corresponding HC physical address.
2965	*
2966	* @deprecated Doesn't deal with zero, shared or write monitored pages.
2967	* Avoid when writing new code!
2968	*/
2969	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2970	{
2971	PPGMPAGE pPage;
2972	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2973	if (VBOX_FAILURE(rc))
2974	return rc;
2975	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
2976	return VINF_SUCCESS;
2977	}
2978
2979
2980	#ifndef IN_GC
2981	/**
2982	* Queries the Physical TLB entry for a physical guest page,
2983	* attemting to load the TLB entry if necessary.
2984	*
2985	* @returns VBox status code.
2986	* @retval VINF_SUCCESS on success
2987	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2988	* @param pPGM The PGM instance handle.
2989	* @param GCPhys The address of the guest page.
2990	* @param ppTlbe Where to store the pointer to the TLB entry.
2991	*/
2992
2993	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2994	{
2995	int rc;
2996	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2997	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2998	{
2999	STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
3000	rc = VINF_SUCCESS;
3001	}
3002	else
3003	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3004	*ppTlbe = pTlbe;
3005	return rc;
3006	}
3007	#endif /* !IN_GC */
3008
3009
3010	#ifndef VBOX_WITH_NEW_PHYS_CODE
3011	/**
3012	* Convert GC Phys to HC Virt.
3013	*
3014	* @returns VBox status.
3015	* @param pPGM PGM handle.
3016	* @param GCPhys The GC physical address.
3017	* @param pHCPtr Where to store the corresponding HC virtual address.
3018	*
3019	* @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
3020	*/
3021	DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3022	{
3023	PPGMRAMRANGE pRam;
3024	PPGMPAGE pPage;
3025	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3026	if (VBOX_FAILURE(rc))
3027	{
3028	pHCPtr = 0; / Shut up silly GCC warnings. */
3029	return rc;
3030	}
3031	RTGCPHYS off = GCPhys - pRam->GCPhys;
3032
3033	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3034	{
3035	unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3036	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3037	return VINF_SUCCESS;
3038	}
3039	if (pRam->pvHC)
3040	{
3041	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3042	return VINF_SUCCESS;
3043	}
3044	pHCPtr = 0; / Shut up silly GCC warnings. */
3045	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3046	}
3047	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3048
3049
3050	/**
3051	* Convert GC Phys to HC Virt.
3052	*
3053	* @returns VBox status.
3054	* @param PVM VM handle.
3055	* @param pRam Ram range
3056	* @param GCPhys The GC physical address.
3057	* @param pHCPtr Where to store the corresponding HC virtual address.
3058	*
3059	* @deprecated This will be eliminated. Don't use it.
3060	*/
3061	DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3062	{
3063	RTGCPHYS off = GCPhys - pRam->GCPhys;
3064	Assert(off < pRam->cb);
3065
3066	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3067	{
3068	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3069	/* Physical chunk in dynamically allocated range not present? */
3070	if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
3071	{
3072	#ifdef IN_RING3
3073	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3074	#else
3075	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3076	#endif
3077	if (rc != VINF_SUCCESS)
3078	{
3079	pHCPtr = 0; / GCC crap */
3080	return rc;
3081	}
3082	}
3083	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3084	return VINF_SUCCESS;
3085	}
3086	if (pRam->pvHC)
3087	{
3088	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3089	return VINF_SUCCESS;
3090	}
3091	pHCPtr = 0; / GCC crap */
3092	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3093	}
3094
3095
3096	/**
3097	* Convert GC Phys to HC Virt and HC Phys.
3098	*
3099	* @returns VBox status.
3100	* @param pPGM PGM handle.
3101	* @param GCPhys The GC physical address.
3102	* @param pHCPtr Where to store the corresponding HC virtual address.
3103	* @param pHCPhys Where to store the HC Physical address and its flags.
3104	*
3105	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3106	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3107	*/
3108	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3109	{
3110	PPGMRAMRANGE pRam;
3111	PPGMPAGE pPage;
3112	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3113	if (VBOX_FAILURE(rc))
3114	{
3115	pHCPtr = 0; / Shut up crappy GCC warnings */
3116	pHCPhys = 0; / ditto */
3117	return rc;
3118	}
3119	RTGCPHYS off = GCPhys - pRam->GCPhys;
3120
3121	pHCPhys = pPage->HCPhys; /* @todo PAGE FLAGS */
3122	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3123	{
3124	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3125	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3126	return VINF_SUCCESS;
3127	}
3128	if (pRam->pvHC)
3129	{
3130	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3131	return VINF_SUCCESS;
3132	}
3133	*pHCPtr = 0;
3134	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3135	}
3136
3137
3138	/**
3139	* Clears flags associated with a RAM address.
3140	*
3141	* @returns VBox status code.
3142	* @param pPGM PGM handle.
3143	* @param GCPhys Guest context physical address.
3144	* @param fFlags fFlags to clear. (Bits 0-11.)
3145	*/
3146	DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3147	{
3148	PPGMPAGE pPage;
3149	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3150	if (VBOX_FAILURE(rc))
3151	return rc;
3152
3153	fFlags &= ~X86_PTE_PAE_PG_MASK;
3154	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3155	return VINF_SUCCESS;
3156	}
3157
3158
3159	/**
3160	* Clears flags associated with a RAM address.
3161	*
3162	* @returns VBox status code.
3163	* @param pPGM PGM handle.
3164	* @param GCPhys Guest context physical address.
3165	* @param fFlags fFlags to clear. (Bits 0-11.)
3166	* @param ppRamHint Where to read and store the ram list hint.
3167	* The caller initializes this to NULL before the call.
3168	*/
3169	DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3170	{
3171	PPGMPAGE pPage;
3172	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3173	if (VBOX_FAILURE(rc))
3174	return rc;
3175
3176	fFlags &= ~X86_PTE_PAE_PG_MASK;
3177	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3178	return VINF_SUCCESS;
3179	}
3180
3181	/**
3182	* Sets (bitwise OR) flags associated with a RAM address.
3183	*
3184	* @returns VBox status code.
3185	* @param pPGM PGM handle.
3186	* @param GCPhys Guest context physical address.
3187	* @param fFlags fFlags to set clear. (Bits 0-11.)
3188	*/
3189	DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3190	{
3191	PPGMPAGE pPage;
3192	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3193	if (VBOX_FAILURE(rc))
3194	return rc;
3195
3196	fFlags &= ~X86_PTE_PAE_PG_MASK;
3197	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3198	return VINF_SUCCESS;
3199	}
3200
3201
3202	/**
3203	* Sets (bitwise OR) flags associated with a RAM address.
3204	*
3205	* @returns VBox status code.
3206	* @param pPGM PGM handle.
3207	* @param GCPhys Guest context physical address.
3208	* @param fFlags fFlags to set clear. (Bits 0-11.)
3209	* @param ppRamHint Where to read and store the ram list hint.
3210	* The caller initializes this to NULL before the call.
3211	*/
3212	DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3213	{
3214	PPGMPAGE pPage;
3215	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3216	if (VBOX_FAILURE(rc))
3217	return rc;
3218
3219	fFlags &= ~X86_PTE_PAE_PG_MASK;
3220	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3221	return VINF_SUCCESS;
3222	}
3223
3224
3225	/**
3226	* Gets the page directory for the specified address.
3227	*
3228	* @returns Pointer to the page directory in question.
3229	* @returns NULL if the page directory is not present or on an invalid page.
3230	* @param pPGM Pointer to the PGM instance data.
3231	* @param GCPtr The address.
3232	*/
3233	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3234	{
3235	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3236	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3237	{
3238	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3239	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3240
3241	/* cache is out-of-sync. */
3242	PX86PDPAE pPD;
3243	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3244	if (VBOX_SUCCESS(rc))
3245	return pPD;
3246	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3247	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3248	}
3249	return NULL;
3250	}
3251
3252
3253	/**
3254	* Gets the page directory entry for the specified address.
3255	*
3256	* @returns Pointer to the page directory entry in question.
3257	* @returns NULL if the page directory is not present or on an invalid page.
3258	* @param pPGM Pointer to the PGM instance data.
3259	* @param GCPtr The address.
3260	*/
3261	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3262	{
3263	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3264	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3265	{
3266	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3267	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3268	return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3269
3270	/* The cache is out-of-sync. */
3271	PX86PDPAE pPD;
3272	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3273	if (VBOX_SUCCESS(rc))
3274	return &pPD->a[iPD];
3275	AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3276	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3277	}
3278	return NULL;
3279	}
3280
3281
3282	/**
3283	* Gets the page directory entry for the specified address.
3284	*
3285	* @returns The page directory entry in question.
3286	* @returns A non-present entry if the page directory is not present or on an invalid page.
3287	* @param pPGM Pointer to the PGM instance data.
3288	* @param GCPtr The address.
3289	*/
3290	DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3291	{
3292	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3293	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3294	{
3295	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3296	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3297	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3298
3299	/* cache is out-of-sync. */
3300	PX86PDPAE pPD;
3301	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3302	if (VBOX_SUCCESS(rc))
3303	return pPD->a[iPD].u;
3304	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3305	}
3306	return 0ULL;
3307	}
3308
3309
3310	/**
3311	* Gets the page directory pointer table entry for the specified address
3312	* and returns the index into the page directory
3313	*
3314	* @returns Pointer to the page directory in question.
3315	* @returns NULL if the page directory is not present or on an invalid page.
3316	* @param pPGM Pointer to the PGM instance data.
3317	* @param GCPtr The address.
3318	* @param piPD Receives the index into the returned page directory
3319	*/
3320	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3321	{
3322	const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3323	if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3324	{
3325	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3326	if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3327	{
3328	*piPD = iPD;
3329	return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3330	}
3331
3332	/* cache is out-of-sync. */
3333	PX86PDPAE pPD;
3334	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3335	if (VBOX_SUCCESS(rc))
3336	{
3337	*piPD = iPD;
3338	return pPD;
3339	}
3340	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3341	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3342	}
3343	return NULL;
3344	}
3345
3346	#ifndef IN_GC
3347	/**
3348	* Gets the page directory pointer entry for the specified address.
3349	*
3350	* @returns Pointer to the page directory pointer entry in question.
3351	* @returns NULL if the page directory is not present or on an invalid page.
3352	* @param pPGM Pointer to the PGM instance data.
3353	* @param GCPtr The address.
3354	* @param ppPml4e Page Map Level-4 Entry (out)
3355	*/
3356	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
3357	{
3358	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3359
3360	Assert(pPGM->pGstPaePML4HC);
3361	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3362	if ((*ppPml4e)->n.u1Present)
3363	{
3364	PX86PDPT pPdpt;
3365	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
3366	if (VBOX_FAILURE(rc))
3367	{
3368	AssertFailed();
3369	return NULL;
3370	}
3371	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3372	return &pPdpt->a[iPdPt];
3373	}
3374	return NULL;
3375	}
3376
3377	/**
3378	* Gets the page directory entry for the specified address.
3379	*
3380	* @returns The page directory entry in question.
3381	* @returns A non-present entry if the page directory is not present or on an invalid page.
3382	* @param pPGM Pointer to the PGM instance data.
3383	* @param GCPtr The address.
3384	* @param ppPml4e Page Map Level-4 Entry (out)
3385	* @param pPdpe Page directory pointer table entry (out)
3386	*/
3387	DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3388	{
3389	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3390
3391	Assert(pPGM->pGstPaePML4HC);
3392	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3393	if ((*ppPml4e)->n.u1Present)
3394	{
3395	PX86PDPT pPdptTemp;
3396	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3397	if (VBOX_FAILURE(rc))
3398	{
3399	AssertFailed();
3400	return 0ULL;
3401	}
3402
3403	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3404	*pPdpe = pPdptTemp->a[iPdPt];
3405	if (pPdpe->n.u1Present)
3406	{
3407	PX86PDPAE pPD;
3408
3409	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3410	if (VBOX_FAILURE(rc))
3411	{
3412	AssertFailed();
3413	return 0ULL;
3414	}
3415	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3416	return pPD->a[iPD].u;
3417	}
3418	}
3419	return 0ULL;
3420	}
3421
3422	/**
3423	* Gets the page directory entry for the specified address.
3424	*
3425	* @returns The page directory entry in question.
3426	* @returns A non-present entry if the page directory is not present or on an invalid page.
3427	* @param pPGM Pointer to the PGM instance data.
3428	* @param GCPtr The address.
3429	*/
3430	DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3431	{
3432	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3433
3434	Assert(pPGM->pGstPaePML4HC);
3435	if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3436	{
3437	PX86PDPT pPdptTemp;
3438	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3439	if (VBOX_FAILURE(rc))
3440	{
3441	AssertFailed();
3442	return 0ULL;
3443	}
3444
3445	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3446	if (pPdptTemp->a[iPdPt].n.u1Present)
3447	{
3448	PX86PDPAE pPD;
3449
3450	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3451	if (VBOX_FAILURE(rc))
3452	{
3453	AssertFailed();
3454	return 0ULL;
3455	}
3456	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3457	return pPD->a[iPD].u;
3458	}
3459	}
3460	return 0ULL;
3461	}
3462
3463	/**
3464	* Gets the page directory entry for the specified address.
3465	*
3466	* @returns Pointer to the page directory entry in question.
3467	* @returns NULL if the page directory is not present or on an invalid page.
3468	* @param pPGM Pointer to the PGM instance data.
3469	* @param GCPtr The address.
3470	*/
3471	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3472	{
3473	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3474
3475	Assert(pPGM->pGstPaePML4HC);
3476	if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
3477	{
3478	PX86PDPT pPdptTemp;
3479	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3480	if (VBOX_FAILURE(rc))
3481	{
3482	AssertFailed();
3483	return NULL;
3484	}
3485
3486	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3487	if (pPdptTemp->a[iPdPt].n.u1Present)
3488	{
3489	PX86PDPAE pPD;
3490
3491	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3492	if (VBOX_FAILURE(rc))
3493	{
3494	AssertFailed();
3495	return NULL;
3496	}
3497	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3498	return &pPD->a[iPD];
3499	}
3500	}
3501	return NULL;
3502	}
3503
3504
3505	/**
3506	* Gets the GUEST page directory pointer for the specified address.
3507	*
3508	* @returns The page directory in question.
3509	* @returns NULL if the page directory is not present or on an invalid page.
3510	* @param pPGM Pointer to the PGM instance data.
3511	* @param GCPtr The address.
3512	* @param ppPml4e Page Map Level-4 Entry (out)
3513	* @param pPdpe Page directory pointer table entry (out)
3514	* @param piPD Receives the index into the returned page directory
3515	*/
3516	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
3517	{
3518	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3519
3520	Assert(pPGM->pGstPaePML4HC);
3521	*ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3522	if ((*ppPml4e)->n.u1Present)
3523	{
3524	PX86PDPT pPdptTemp;
3525	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3526	if (VBOX_FAILURE(rc))
3527	{
3528	AssertFailed();
3529	return 0ULL;
3530	}
3531
3532	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3533	*pPdpe = pPdptTemp->a[iPdPt];
3534	if (pPdpe->n.u1Present)
3535	{
3536	PX86PDPAE pPD;
3537
3538	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3539	if (VBOX_FAILURE(rc))
3540	{
3541	AssertFailed();
3542	return 0ULL;
3543	}
3544	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3545	return pPD;
3546	}
3547	}
3548	return 0ULL;
3549	}
3550
3551	/**
3552	* Gets the GUEST page directory pointer for the specified address.
3553	*
3554	* @returns The page directory in question.
3555	* @returns NULL if the page directory is not present or on an invalid page.
3556	* @param pPGM Pointer to the PGM instance data.
3557	* @param GCPtr The address.
3558	* @param piPD Receives the index into the returned page directory
3559	*/
3560	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, unsigned *piPD)
3561	{
3562	PX86PML4E pPml4e;
3563	PX86PDPE pPdpe;
3564	const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3565
3566	Assert(pPGM->pGstPaePML4HC);
3567	pPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
3568	if (pPml4e->n.u1Present)
3569	{
3570	PX86PDPT pPdptTemp;
3571	int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3572	if (VBOX_FAILURE(rc))
3573	{
3574	AssertFailed();
3575	return 0ULL;
3576	}
3577
3578	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3579	pPdpe = &pPdptTemp->a[iPdPt];
3580	if (pPdpe->n.u1Present)
3581	{
3582	PX86PDPAE pPD;
3583
3584	rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3585	if (VBOX_FAILURE(rc))
3586	{
3587	AssertFailed();
3588	return 0ULL;
3589	}
3590	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3591	return pPD;
3592	}
3593	}
3594	return 0ULL;
3595	}
3596
3597	#endif /* !IN_GC */
3598
3599	/**
3600	* Checks if any of the specified page flags are set for the given page.
3601	*
3602	* @returns true if any of the flags are set.
3603	* @returns false if all the flags are clear.
3604	* @param pPGM PGM handle.
3605	* @param GCPhys The GC physical address.
3606	* @param fFlags The flags to check for.
3607	*/
3608	DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3609	{
3610	PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3611	return pPage
3612	&& (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3613	}
3614
3615
3616	/**
3617	* Gets the page state for a physical handler.
3618	*
3619	* @returns The physical handler page state.
3620	* @param pCur The physical handler in question.
3621	*/
3622	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3623	{
3624	switch (pCur->enmType)
3625	{
3626	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3627	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3628
3629	case PGMPHYSHANDLERTYPE_MMIO:
3630	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3631	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3632
3633	default:
3634	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3635	}
3636	}
3637
3638
3639	/**
3640	* Gets the page state for a virtual handler.
3641	*
3642	* @returns The virtual handler page state.
3643	* @param pCur The virtual handler in question.
3644	* @remarks This should never be used on a hypervisor access handler.
3645	*/
3646	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3647	{
3648	switch (pCur->enmType)
3649	{
3650	case PGMVIRTHANDLERTYPE_WRITE:
3651	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3652	case PGMVIRTHANDLERTYPE_ALL:
3653	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3654	default:
3655	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3656	}
3657	}
3658
3659
3660	/**
3661	* Clears one physical page of a virtual handler
3662	*
3663	* @param pPGM Pointer to the PGM instance.
3664	* @param pCur Virtual handler structure
3665	* @param iPage Physical page index
3666	*
3667	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3668	* need to care about other handlers in the same page.
3669	*/
3670	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3671	{
3672	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3673
3674	/*
3675	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
3676	*/
3677	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3678	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3679	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3680	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3681	#endif
3682	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3683	{
3684	/* We're the head of the alias chain. */
3685	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3686	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3687	AssertReleaseMsg(pRemove != NULL,
3688	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3689	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3690	AssertReleaseMsg(pRemove == pPhys2Virt,
3691	("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3692	" got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3693	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3694	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3695	#endif
3696	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3697	{
3698	/* Insert the next list in the alias chain into the tree. */
3699	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3700	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3701	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3702	("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3703	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3704	#endif
3705	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
3706	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3707	AssertRelease(fRc);
3708	}
3709	}
3710	else
3711	{
3712	/* Locate the previous node in the alias chain. */
3713	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3714	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3715	AssertReleaseMsg(pPrev != pPhys2Virt,
3716	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3717	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3718	#endif
3719	for (;;)
3720	{
3721	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3722	if (pNext == pPhys2Virt)
3723	{
3724	/* unlink. */
3725	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3726	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3727	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3728	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3729	else
3730	{
3731	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3732	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3733	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3734	}
3735	break;
3736	}
3737
3738	/* next */
3739	if (pNext == pPrev)
3740	{
3741	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3742	AssertReleaseMsg(pNext != pPrev,
3743	("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3744	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3745	#endif
3746	break;
3747	}
3748	pPrev = pNext;
3749	}
3750	}
3751	Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3752	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3753	pPhys2Virt->offNextAlias = 0;
3754	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3755
3756	/*
3757	* Clear the ram flags for this page.
3758	*/
3759	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3760	AssertReturnVoid(pPage);
3761	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3762	}
3763
3764
3765	/**
3766	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
3767	*
3768	* @returns Pointer to the shadow page structure.
3769	* @param pPool The pool.
3770	* @param HCPhys The HC physical address of the shadow page.
3771	*/
3772	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3773	{
3774	/*
3775	* Look up the page.
3776	*/
3777	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3778	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3779	return pPage;
3780	}
3781
3782
3783	/**
3784	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
3785	*
3786	* @returns Pointer to the shadow page structure.
3787	* @param pPool The pool.
3788	* @param idx The pool page index.
3789	*/
3790	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3791	{
3792	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3793	return &pPool->aPages[idx];
3794	}
3795
3796
3797	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3798	/**
3799	* Clear references to guest physical memory.
3800	*
3801	* @param pPool The pool.
3802	* @param pPoolPage The pool page.
3803	* @param pPhysPage The physical guest page tracking structure.
3804	*/
3805	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3806	{
3807	/*
3808	* Just deal with the simple case here.
3809	*/
3810	#ifdef LOG_ENABLED
3811	const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3812	#endif
3813	const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3814	if (cRefs == 1)
3815	{
3816	Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3817	pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3818	}
3819	else
3820	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3821	LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3822	}
3823	#endif
3824
3825
3826	#ifdef PGMPOOL_WITH_CACHE
3827	/**
3828	* Moves the page to the head of the age list.
3829	*
3830	* This is done when the cached page is used in one way or another.
3831	*
3832	* @param pPool The pool.
3833	* @param pPage The cached page.
3834	* @todo inline in PGMInternal.h!
3835	*/
3836	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3837	{
3838	/*
3839	* Move to the head of the age list.
3840	*/
3841	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3842	{
3843	/* unlink */
3844	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3845	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3846	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3847	else
3848	pPool->iAgeTail = pPage->iAgePrev;
3849
3850	/* insert at head */
3851	pPage->iAgePrev = NIL_PGMPOOL_IDX;
3852	pPage->iAgeNext = pPool->iAgeHead;
3853	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3854	pPool->iAgeHead = pPage->idx;
3855	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3856	}
3857	}
3858	#endif /* PGMPOOL_WITH_CACHE */
3859
3860	/**
3861	* Tells if mappings are to be put into the shadow page table or not
3862	*
3863	* @returns boolean result
3864	* @param pVM VM handle.
3865	*/
3866
3867	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3868	{
3869	#ifdef IN_RING0
3870	/* There are no mappings in VT-x and AMD-V mode. */
3871	Assert(pPGM->fDisableMappings);
3872	return false;
3873	#else
3874	return !pPGM->fDisableMappings;
3875	#endif
3876	}
3877
3878	/** @} */
3879
3880	#endif

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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 10196

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