PGM.cpp@ 4403

Last change on this file since 4403 was 4388, checked in by vboxsync, 17 years ago
Shadow ROM emulation. Clear the RESERVED flag for ROM.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 158.4 KB

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1	/* $Id: PGM.cpp 4388 2007-08-27 14:26:05Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	*
22	*
23	* @section sec_pg_modes Paging Modes
24	*
25	* There are three memory contexts: Host Context (HC), Guest Context (GC)
26	* and intermediate context. When talking about paging HC can also be refered to
27	* as "host paging", and GC refered to as "shadow paging".
28	*
29	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
30	* is defined by the host operating system. The mode used in the shadow paging mode
31	* depends on the host paging mode and what the mode the guest is currently in. The
32	* following relation between the two is defined:
33	*
34	* @verbatim
35	Host > 32-bit \| PAE \| AMD64 \|
36	Guest \| \| \| \|
37	==v================================
38	32-bit 32-bit PAE PAE
39	-------\|--------\|--------\|--------\|
40	PAE PAE PAE PAE
41	-------\|--------\|--------\|--------\|
42	AMD64 AMD64 AMD64 AMD64
43	-------\|--------\|--------\|--------\| @endverbatim
44	*
45	* All configuration except those in the diagonal (upper left) are expected to
46	* require special effort from the switcher (i.e. a bit slower).
47	*
48	*
49	*
50	*
51	* @section sec_pg_shw The Shadow Memory Context
52	*
53	*
54	* [..]
55	*
56	* Because of guest context mappings requires PDPTR and PML4 entries to allow
57	* writing on AMD64, the two upper levels will have fixed flags whatever the
58	* guest is thinking of using there. So, when shadowing the PD level we will
59	* calculate the effective flags of PD and all the higher levels. In legacy
60	* PAE mode this only applies to the PWT and PCD bits (the rest are
61	* ignored/reserved/MBZ). We will ignore those bits for the present.
62	*
63	*
64	*
65	* @section sec_pg_int The Intermediate Memory Context
66	*
67	* The world switch goes thru an intermediate memory context which purpose it is
68	* to provide different mappings of the switcher code. All guest mappings are also
69	* present in this context.
70	*
71	* The switcher code is mapped at the same location as on the host, at an
72	* identity mapped location (physical equals virtual address), and at the
73	* hypervisor location.
74	*
75	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
76	* simplifies switching guest CPU mode and consistency at the cost of more
77	* code to do the work. All memory use for those page tables is located below
78	* 4GB (this includes page tables for guest context mappings).
79	*
80	*
81	* @subsection subsec_pg_int_gc Guest Context Mappings
82	*
83	* During assignment and relocation of a guest context mapping the intermediate
84	* memory context is used to verify the new location.
85	*
86	* Guest context mappings are currently restricted to below 4GB, for reasons
87	* of simplicity. This may change when we implement AMD64 support.
88	*
89	*
90	*
91	*
92	* @section sec_pg_misc Misc
93	*
94	* @subsection subsec_pg_misc_diff Differences Between Legacy PAE and Long Mode PAE
95	*
96	* The differences between legacy PAE and long mode PAE are:
97	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
98	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
99	* usual meanings while 6 is ignored (AMD). This means that upon switching to
100	* legacy PAE mode we'll have to clear these bits and when going to long mode
101	* they must be set. This applies to both intermediate and shadow contexts,
102	* however we don't need to do it for the intermediate one since we're
103	* executing with CR0.WP at that time.
104	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
105	* a page aligned one is required.
106	*/
107
108
109
110	/** Saved state data unit version. */
111	#define PGM_SAVED_STATE_VERSION 5
112
113	/*******************************************************************************
114	* Header Files *
115	*******************************************************************************/
116	#define LOG_GROUP LOG_GROUP_PGM
117	#include <VBox/dbgf.h>
118	#include <VBox/pgm.h>
119	#include <VBox/cpum.h>
120	#include <VBox/iom.h>
121	#include <VBox/sup.h>
122	#include <VBox/mm.h>
123	#include <VBox/em.h>
124	#include <VBox/stam.h>
125	#include <VBox/rem.h>
126	#include <VBox/dbgf.h>
127	#include <VBox/rem.h>
128	#include <VBox/selm.h>
129	#include <VBox/ssm.h>
130	#include "PGMInternal.h"
131	#include <VBox/vm.h>
132	#include <VBox/dbg.h>
133	#include <VBox/hwaccm.h>
134
135	#include <iprt/assert.h>
136	#include <iprt/alloc.h>
137	#include <iprt/asm.h>
138	#include <iprt/thread.h>
139	#include <iprt/string.h>
140	#include <VBox/param.h>
141	#include <VBox/err.h>
142
143
144
145	/*******************************************************************************
146	* Internal Functions *
147	*******************************************************************************/
148	static int pgmR3InitPaging(PVM pVM);
149	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
150	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
151	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
152	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
153	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
154	#ifdef VBOX_STRICT
155	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
156	#endif
157	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
158	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
159	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
160	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
161	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
162
163	#ifdef VBOX_WITH_STATISTICS
164	static void pgmR3InitStats(PVM pVM);
165	#endif
166
167	#ifdef VBOX_WITH_DEBUGGER
168	/** @todo all but the two last commands must be converted to 'info'. */
169	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
170	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
171	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
172	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
173	#endif
174
175
176	/*******************************************************************************
177	* Global Variables *
178	*******************************************************************************/
179	#ifdef VBOX_WITH_DEBUGGER
180	/** Command descriptors. */
181	static const DBGCCMD g_aCmds[] =
182	{
183	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
184	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
185	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
186	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
187	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
188	};
189	#endif
190
191
192
193
194	#if 1/// @todo ndef RT_ARCH_AMD64
195	/*
196	* Shadow - 32-bit mode
197	*/
198	#define PGM_SHW_TYPE PGM_TYPE_32BIT
199	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
200	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
201	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
202	#include "PGMShw.h"
203
204	/* Guest - real mode */
205	#define PGM_GST_TYPE PGM_TYPE_REAL
206	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
207	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
208	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
209	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
210	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
211	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
212	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
213	#include "PGMGst.h"
214	#include "PGMBth.h"
215	#undef BTH_PGMPOOLKIND_PT_FOR_PT
216	#undef PGM_BTH_NAME
217	#undef PGM_BTH_NAME_GC_STR
218	#undef PGM_BTH_NAME_R0_STR
219	#undef PGM_GST_TYPE
220	#undef PGM_GST_NAME
221	#undef PGM_GST_NAME_GC_STR
222	#undef PGM_GST_NAME_R0_STR
223
224	/* Guest - protected mode */
225	#define PGM_GST_TYPE PGM_TYPE_PROT
226	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
227	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
228	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
229	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
230	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
231	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
232	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
233	#include "PGMGst.h"
234	#include "PGMBth.h"
235	#undef BTH_PGMPOOLKIND_PT_FOR_PT
236	#undef PGM_BTH_NAME
237	#undef PGM_BTH_NAME_GC_STR
238	#undef PGM_BTH_NAME_R0_STR
239	#undef PGM_GST_TYPE
240	#undef PGM_GST_NAME
241	#undef PGM_GST_NAME_GC_STR
242	#undef PGM_GST_NAME_R0_STR
243
244	/* Guest - 32-bit mode */
245	#define PGM_GST_TYPE PGM_TYPE_32BIT
246	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
247	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
248	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
249	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
250	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
251	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
252	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
253	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
254	#include "PGMGst.h"
255	#include "PGMBth.h"
256	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
257	#undef BTH_PGMPOOLKIND_PT_FOR_PT
258	#undef PGM_BTH_NAME
259	#undef PGM_BTH_NAME_GC_STR
260	#undef PGM_BTH_NAME_R0_STR
261	#undef PGM_GST_TYPE
262	#undef PGM_GST_NAME
263	#undef PGM_GST_NAME_GC_STR
264	#undef PGM_GST_NAME_R0_STR
265
266	#undef PGM_SHW_TYPE
267	#undef PGM_SHW_NAME
268	#undef PGM_SHW_NAME_GC_STR
269	#undef PGM_SHW_NAME_R0_STR
270	#endif /* !RT_ARCH_AMD64 */
271
272
273	/*
274	* Shadow - PAE mode
275	*/
276	#define PGM_SHW_TYPE PGM_TYPE_PAE
277	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
278	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
279	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
280	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
281	#include "PGMShw.h"
282
283	/* Guest - real mode */
284	#define PGM_GST_TYPE PGM_TYPE_REAL
285	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
286	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
287	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
288	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
289	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
290	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
291	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
292	#include "PGMBth.h"
293	#undef BTH_PGMPOOLKIND_PT_FOR_PT
294	#undef PGM_BTH_NAME
295	#undef PGM_BTH_NAME_GC_STR
296	#undef PGM_BTH_NAME_R0_STR
297	#undef PGM_GST_TYPE
298	#undef PGM_GST_NAME
299	#undef PGM_GST_NAME_GC_STR
300	#undef PGM_GST_NAME_R0_STR
301
302	/* Guest - protected mode */
303	#define PGM_GST_TYPE PGM_TYPE_PROT
304	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
305	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
306	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
307	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
308	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
309	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
310	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
311	#include "PGMBth.h"
312	#undef BTH_PGMPOOLKIND_PT_FOR_PT
313	#undef PGM_BTH_NAME
314	#undef PGM_BTH_NAME_GC_STR
315	#undef PGM_BTH_NAME_R0_STR
316	#undef PGM_GST_TYPE
317	#undef PGM_GST_NAME
318	#undef PGM_GST_NAME_GC_STR
319	#undef PGM_GST_NAME_R0_STR
320
321	/* Guest - 32-bit mode */
322	#define PGM_GST_TYPE PGM_TYPE_32BIT
323	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
324	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
325	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
326	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
327	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
328	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
329	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
330	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
331	#include "PGMBth.h"
332	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
333	#undef BTH_PGMPOOLKIND_PT_FOR_PT
334	#undef PGM_BTH_NAME
335	#undef PGM_BTH_NAME_GC_STR
336	#undef PGM_BTH_NAME_R0_STR
337	#undef PGM_GST_TYPE
338	#undef PGM_GST_NAME
339	#undef PGM_GST_NAME_GC_STR
340	#undef PGM_GST_NAME_R0_STR
341
342	/* Guest - PAE mode */
343	#define PGM_GST_TYPE PGM_TYPE_PAE
344	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
345	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
346	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
347	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
348	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
349	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
350	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
351	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
352	#include "PGMGst.h"
353	#include "PGMBth.h"
354	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
355	#undef BTH_PGMPOOLKIND_PT_FOR_PT
356	#undef PGM_BTH_NAME
357	#undef PGM_BTH_NAME_GC_STR
358	#undef PGM_BTH_NAME_R0_STR
359	#undef PGM_GST_TYPE
360	#undef PGM_GST_NAME
361	#undef PGM_GST_NAME_GC_STR
362	#undef PGM_GST_NAME_R0_STR
363
364	#undef PGM_SHW_TYPE
365	#undef PGM_SHW_NAME
366	#undef PGM_SHW_NAME_GC_STR
367	#undef PGM_SHW_NAME_R0_STR
368
369
370	/*
371	* Shadow - AMD64 mode
372	*/
373	#define PGM_SHW_TYPE PGM_TYPE_AMD64
374	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
375	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
376	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
377	#include "PGMShw.h"
378
379	/* Guest - real mode */
380	#define PGM_GST_TYPE PGM_TYPE_REAL
381	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
382	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
383	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
384	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
385	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_REAL_STR(name)
386	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_REAL_STR(name)
387	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
388	#include "PGMBth.h"
389	#undef BTH_PGMPOOLKIND_PT_FOR_PT
390	#undef PGM_BTH_NAME
391	#undef PGM_BTH_NAME_GC_STR
392	#undef PGM_BTH_NAME_R0_STR
393	#undef PGM_GST_TYPE
394	#undef PGM_GST_NAME
395	#undef PGM_GST_NAME_GC_STR
396	#undef PGM_GST_NAME_R0_STR
397
398	/* Guest - protected mode */
399	#define PGM_GST_TYPE PGM_TYPE_PROT
400	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
401	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
402	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
403	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
404	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_PROT_STR(name)
405	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_PROT_STR(name)
406	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
407	#include "PGMBth.h"
408	#undef BTH_PGMPOOLKIND_PT_FOR_PT
409	#undef PGM_BTH_NAME
410	#undef PGM_BTH_NAME_GC_STR
411	#undef PGM_BTH_NAME_R0_STR
412	#undef PGM_GST_TYPE
413	#undef PGM_GST_NAME
414	#undef PGM_GST_NAME_GC_STR
415	#undef PGM_GST_NAME_R0_STR
416
417	/* Guest - AMD64 mode */
418	#define PGM_GST_TYPE PGM_TYPE_AMD64
419	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
420	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
421	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
422	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
423	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
424	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
425	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
426	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
427	#include "PGMGst.h"
428	#include "PGMBth.h"
429	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
430	#undef BTH_PGMPOOLKIND_PT_FOR_PT
431	#undef PGM_BTH_NAME
432	#undef PGM_BTH_NAME_GC_STR
433	#undef PGM_BTH_NAME_R0_STR
434	#undef PGM_GST_TYPE
435	#undef PGM_GST_NAME
436	#undef PGM_GST_NAME_GC_STR
437	#undef PGM_GST_NAME_R0_STR
438
439	#undef PGM_SHW_TYPE
440	#undef PGM_SHW_NAME
441	#undef PGM_SHW_NAME_GC_STR
442	#undef PGM_SHW_NAME_R0_STR
443
444
445	/**
446	* Initiates the paging of VM.
447	*
448	* @returns VBox status code.
449	* @param pVM Pointer to VM structure.
450	*/
451	PGMR3DECL(int) PGMR3Init(PVM pVM)
452	{
453	LogFlow(("PGMR3Init:\n"));
454
455	/*
456	* Assert alignment and sizes.
457	*/
458	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
459
460	/*
461	* Init the structure.
462	*/
463	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
464	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
465	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
466	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
467	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
468	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
469	pVM->pgm.s.fA20Enabled = true;
470	pVM->pgm.s.pGstPaePDPTRHC = NULL;
471	pVM->pgm.s.pGstPaePDPTRGC = 0;
472	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
473	{
474	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
475	pVM->pgm.s.apGstPaePDsGC[i] = 0;
476	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
477	}
478
479	#ifdef VBOX_STRICT
480	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
481	#endif
482
483	/*
484	* Get the configured RAM size - to estimate saved state size.
485	*/
486	uint64_t cbRam;
487	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
488	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
489	cbRam = pVM->pgm.s.cbRamSize = 0;
490	else if (VBOX_SUCCESS(rc))
491	{
492	if (cbRam < PAGE_SIZE)
493	cbRam = 0;
494	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
495	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
496	}
497	else
498	{
499	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
500	return rc;
501	}
502
503	/*
504	* Register saved state data unit.
505	*/
506	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
507	NULL, pgmR3Save, NULL,
508	NULL, pgmR3Load, NULL);
509	if (VBOX_FAILURE(rc))
510	return rc;
511
512	/* Initialise PGM critical section. */
513	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
514	AssertRCReturn(rc, rc);
515
516	/*
517	* Trees
518	*/
519	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
520	if (VBOX_SUCCESS(rc))
521	{
522	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
523
524	/*
525	* Init the paging.
526	*/
527	rc = pgmR3InitPaging(pVM);
528	}
529	if (VBOX_SUCCESS(rc))
530	{
531	/*
532	* Init the page pool.
533	*/
534	rc = pgmR3PoolInit(pVM);
535	}
536	if (VBOX_SUCCESS(rc))
537	{
538	/*
539	* Info & statistics
540	*/
541	DBGFR3InfoRegisterInternal(pVM, "mode",
542	"Shows the current paging mode. "
543	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
544	pgmR3InfoMode);
545	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
546	"Dumps all the entries in the top level paging table. No arguments.",
547	pgmR3InfoCr3);
548	DBGFR3InfoRegisterInternal(pVM, "phys",
549	"Dumps all the physical address ranges. No arguments.",
550	pgmR3PhysInfo);
551	DBGFR3InfoRegisterInternal(pVM, "handlers",
552	"Dumps physical and virtual handlers. "
553	"Pass 'phys' or 'virt' as argument if only one kind is wanted.",
554	pgmR3InfoHandlers);
555
556	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
557	#ifdef VBOX_WITH_STATISTICS
558	pgmR3InitStats(pVM);
559	#endif
560	#ifdef VBOX_WITH_DEBUGGER
561	/*
562	* Debugger commands.
563	*/
564	static bool fRegisteredCmds = false;
565	if (!fRegisteredCmds)
566	{
567	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
568	if (VBOX_SUCCESS(rc))
569	fRegisteredCmds = true;
570	}
571	#endif
572	return VINF_SUCCESS;
573	}
574	/* No cleanup necessary, MM frees all memory. */
575
576	return rc;
577	}
578
579
580	/**
581	* Init paging.
582	*
583	* Since we need to check what mode the host is operating in before we can choose
584	* the right paging functions for the host we have to delay this until R0 has
585	* been initialized.
586	*
587	* @returns VBox status code.
588	* @param pVM VM handle.
589	*/
590	static int pgmR3InitPaging(PVM pVM)
591	{
592	/*
593	* Force a recalculation of modes and switcher so everyone gets notified.
594	*/
595	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
596	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
597	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
598
599	/*
600	* Allocate static mapping space for whatever the cr3 register
601	* points to and in the case of PAE mode to the 4 PDs.
602	*/
603	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
604	if (VBOX_FAILURE(rc))
605	{
606	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
607	return rc;
608	}
609	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
610
611	/*
612	* Allocate pages for the three possible intermediate contexts
613	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
614	* for the sake of simplicity. The AMD64 uses the PAE for the
615	* lower levels, making the total number of pages 11 (3 + 7 + 1).
616	*
617	* We assume that two page tables will be enought for the core code
618	* mappings (HC virtual and identity).
619	*/
620	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
621	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
622	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
623	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
624	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
625	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
626	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
627	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
628	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
629	pVM->pgm.s.pInterPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
630	pVM->pgm.s.pInterPaePDPTR64 = (PX86PDPTR)MMR3PageAllocLow(pVM);
631	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
632	if ( !pVM->pgm.s.pInterPD
633	\|\| !pVM->pgm.s.apInterPTs[0]
634	\|\| !pVM->pgm.s.apInterPTs[1]
635	\|\| !pVM->pgm.s.apInterPaePTs[0]
636	\|\| !pVM->pgm.s.apInterPaePTs[1]
637	\|\| !pVM->pgm.s.apInterPaePDs[0]
638	\|\| !pVM->pgm.s.apInterPaePDs[1]
639	\|\| !pVM->pgm.s.apInterPaePDs[2]
640	\|\| !pVM->pgm.s.apInterPaePDs[3]
641	\|\| !pVM->pgm.s.pInterPaePDPTR
642	\|\| !pVM->pgm.s.pInterPaePDPTR64
643	\|\| !pVM->pgm.s.pInterPaePML4)
644	{
645	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
646	return VERR_NO_PAGE_MEMORY;
647	}
648
649	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
650	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
651	pVM->pgm.s.HCPhysInterPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR);
652	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPTR != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPTR & PAGE_OFFSET_MASK));
653	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
654	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
655
656	/*
657	* Initialize the pages, setting up the PML4 and PDPTR for repetitive 4GB action.
658	*/
659	ASMMemZeroPage(pVM->pgm.s.pInterPD);
660	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
661	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
662
663	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
664	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
665
666	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPTR);
667	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
668	{
669	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
670	pVM->pgm.s.pInterPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
671	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
672	}
673
674	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPTR64->a); i++)
675	{
676	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
677	pVM->pgm.s.pInterPaePDPTR64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
678	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
679	}
680
681	RTHCPHYS HCPhysInterPaePDPTR64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64);
682	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
683	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
684	\| HCPhysInterPaePDPTR64;
685
686	/*
687	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
688	* We allocate pages for all three posibilities to in order to simplify mappings and
689	* avoid resource failure during mode switches. So, we need to cover all levels of the
690	* of the first 4GB down to PD level.
691	* As with the intermediate context, AMD64 uses the PAE PDPTR and PDs.
692	*/
693	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
694	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
695	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
696	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
697	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
698	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
699	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
700	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
701	pVM->pgm.s.pHCPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
702	pVM->pgm.s.pHCPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
703	if ( !pVM->pgm.s.pHC32BitPD
704	\|\| !pVM->pgm.s.apHCPaePDs[0]
705	\|\| !pVM->pgm.s.apHCPaePDs[1]
706	\|\| !pVM->pgm.s.apHCPaePDs[2]
707	\|\| !pVM->pgm.s.apHCPaePDs[3]
708	\|\| !pVM->pgm.s.pHCPaePDPTR
709	\|\| !pVM->pgm.s.pHCPaePML4)
710	{
711	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
712	return VERR_NO_PAGE_MEMORY;
713	}
714
715	/* get physical addresses. */
716	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
717	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
718	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
719	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
720	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
721	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
722	pVM->pgm.s.HCPhysPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPTR);
723	pVM->pgm.s.HCPhysPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePML4);
724
725	/*
726	* Initialize the pages, setting up the PML4 and PDPTR for action below 4GB.
727	*/
728	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
729
730	ASMMemZero32(pVM->pgm.s.pHCPaePDPTR, PAGE_SIZE);
731	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
732	{
733	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
734	pVM->pgm.s.pHCPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
735	/* The flags will be corrected when entering and leaving long mode. */
736	}
737
738	ASMMemZero32(pVM->pgm.s.pHCPaePML4, PAGE_SIZE);
739	pVM->pgm.s.pHCPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_A
740	\| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.HCPhysPaePDPTR;
741
742	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
743
744	/*
745	* Initialize paging workers and mode from current host mode
746	* and the guest running in real mode.
747	*/
748	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
749	switch (pVM->pgm.s.enmHostMode)
750	{
751	case SUPPAGINGMODE_32_BIT:
752	case SUPPAGINGMODE_32_BIT_GLOBAL:
753	case SUPPAGINGMODE_PAE:
754	case SUPPAGINGMODE_PAE_GLOBAL:
755	case SUPPAGINGMODE_PAE_NX:
756	case SUPPAGINGMODE_PAE_GLOBAL_NX:
757	break;
758
759	case SUPPAGINGMODE_AMD64:
760	case SUPPAGINGMODE_AMD64_GLOBAL:
761	case SUPPAGINGMODE_AMD64_NX:
762	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
763	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
764	if (ARCH_BITS != 64)
765	{
766	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
767	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
768	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
769	}
770	#endif
771	break;
772	default:
773	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
774	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
775	}
776	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
777	if (VBOX_SUCCESS(rc))
778	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
779	if (VBOX_SUCCESS(rc))
780	{
781	LogFlow(("pgmR3InitPaging: returns successfully\n"));
782	#if HC_ARCH_BITS == 64
783	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPTR=%VHp HCPhysPaePML4=%VHp\n",
784	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
785	pVM->pgm.s.HCPhysPaePDPTR, pVM->pgm.s.HCPhysPaePML4));
786	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPTR=%VHp HCPhysInterPaePML4=%VHp\n",
787	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPTR, pVM->pgm.s.HCPhysInterPaePML4));
788	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPTR64=%VHp\n",
789	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
790	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
791	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
792	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64)));
793	#endif
794
795	return VINF_SUCCESS;
796	}
797
798	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
799	return rc;
800	}
801
802
803	#ifdef VBOX_WITH_STATISTICS
804	/**
805	* Init statistics
806	*/
807	static void pgmR3InitStats(PVM pVM)
808	{
809	PPGM pPGM = &pVM->pgm.s;
810	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
811	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
812	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
813	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
814	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
815	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
816	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
817	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
818	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
819	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
820	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
821	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
822	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
823	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
824	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
825	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
826	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
827	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
828	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
829	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
830	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
831	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
832
833	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
834	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
835	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
836	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
837	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
838	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
839	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
840	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
841	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
842	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
843	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
844	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
845	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
846	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
847	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
848	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
849	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
850	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
851	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
852
853	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
854	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
855	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
856	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
857	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
858	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
859	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
860
861	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
862	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
863	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
864	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
865	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
866	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
867
868	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
869	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
870	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
871	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
872	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
873	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
874
875
876	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
877	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
878	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
879
880	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
881	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
882
883	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
884	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
885
886	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
887	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
888
889	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
890	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
891	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
892
893	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
894	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
895	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
896	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
897	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
898	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
899	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
900	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
901	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
902	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
903	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
904
905	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
906	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
907	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
908	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
909	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
910	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
911	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
912
913	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
914	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
915	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
916	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
917
918	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
919	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
920	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
921	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
922	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
923
924	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
925	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
926	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
927	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
928	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
929	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
930	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
931	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
932	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
933	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
934	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
935	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
936
937	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
938	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
939	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
940	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
941	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
942	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
943	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
944	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
945	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
946	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
947	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
948	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
949
950	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
951	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
952	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
953
954	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
955	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
956
957	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
958	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
959	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
960	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
961
962	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
963	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
964
965	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
966	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
967	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
968	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
969	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
970	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
971	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
972	#endif
973
974	for (unsigned i = 0; i < PAGE_ENTRIES; i++)
975	{
976	/** @todo r=bird: We need a STAMR3RegisterF()! */
977	char szName[32];
978
979	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
980	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
981	AssertRC(rc);
982
983	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
984	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
985	AssertRC(rc);
986
987	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
988	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
989	AssertRC(rc);
990	}
991	}
992	#endif /* VBOX_WITH_STATISTICS */
993
994	/**
995	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
996	*
997	* The dynamic mapping area will also be allocated and initialized at this
998	* time. We could allocate it during PGMR3Init of course, but the mapping
999	* wouldn't be allocated at that time preventing us from setting up the
1000	* page table entries with the dummy page.
1001	*
1002	* @returns VBox status code.
1003	* @param pVM VM handle.
1004	*/
1005	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1006	{
1007	/*
1008	* Reserve space for mapping the paging pages into guest context.
1009	*/
1010	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &pVM->pgm.s.pGC32BitPD);
1011	AssertRCReturn(rc, rc);
1012	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1013
1014	/*
1015	* Reserve space for the dynamic mappings.
1016	*/
1017	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1018	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &pVM->pgm.s.pbDynPageMapBaseGC);
1019	if ( VBOX_SUCCESS(rc)
1020	&& (pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT))
1021	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &pVM->pgm.s.pbDynPageMapBaseGC);
1022	if (VBOX_SUCCESS(rc))
1023	{
1024	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT));
1025	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1026	}
1027	return rc;
1028	}
1029
1030
1031	/**
1032	* Ring-3 init finalizing.
1033	*
1034	* @returns VBox status code.
1035	* @param pVM The VM handle.
1036	*/
1037	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1038	{
1039	/*
1040	* Map the paging pages into the guest context.
1041	*/
1042	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1043	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1044
1045	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1046	AssertRCReturn(rc, rc);
1047	pVM->pgm.s.pGC32BitPD = GCPtr;
1048	GCPtr += PAGE_SIZE;
1049	GCPtr += PAGE_SIZE; /* reserved page */
1050
1051	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1052	{
1053	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1054	AssertRCReturn(rc, rc);
1055	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1056	GCPtr += PAGE_SIZE;
1057	}
1058	/* A bit of paranoia is justified. */
1059	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1060	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1061	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1062	GCPtr += PAGE_SIZE; /* reserved page */
1063
1064	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPTR, PAGE_SIZE, 0);
1065	AssertRCReturn(rc, rc);
1066	pVM->pgm.s.pGCPaePDPTR = GCPtr;
1067	GCPtr += PAGE_SIZE;
1068	GCPtr += PAGE_SIZE; /* reserved page */
1069
1070	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePML4, PAGE_SIZE, 0);
1071	AssertRCReturn(rc, rc);
1072	pVM->pgm.s.pGCPaePML4 = GCPtr;
1073	GCPtr += PAGE_SIZE;
1074	GCPtr += PAGE_SIZE; /* reserved page */
1075
1076
1077	/*
1078	* Reserve space for the dynamic mappings.
1079	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1080	*/
1081	/* get the pointer to the page table entries. */
1082	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1083	AssertRelease(pMapping);
1084	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1085	const unsigned iPT = off >> X86_PD_SHIFT;
1086	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1087	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1088	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1089
1090	/* init cache */
1091	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1092	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1093	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1094
1095	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1096	{
1097	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1098	AssertRCReturn(rc, rc);
1099	}
1100
1101	return rc;
1102	}
1103
1104
1105	/**
1106	* Applies relocations to data and code managed by this
1107	* component. This function will be called at init and
1108	* whenever the VMM need to relocate it self inside the GC.
1109	*
1110	* @param pVM The VM.
1111	* @param offDelta Relocation delta relative to old location.
1112	*/
1113	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1114	{
1115	LogFlow(("PGMR3Relocate\n"));
1116
1117	/*
1118	* Paging stuff.
1119	*/
1120	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1121	/** @todo move this into shadow and guest specific relocation functions. */
1122	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1123	pVM->pgm.s.pGC32BitPD += offDelta;
1124	pVM->pgm.s.pGuestPDGC += offDelta;
1125	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1126	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1127	pVM->pgm.s.pGCPaePDPTR += offDelta;
1128	pVM->pgm.s.pGCPaePML4 += offDelta;
1129
1130	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1131	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1132
1133	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1134	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1135	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1136
1137	/*
1138	* Trees.
1139	*/
1140	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1141
1142	/*
1143	* Ram ranges.
1144	*/
1145	if (pVM->pgm.s.pRamRangesHC)
1146	{
1147	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesHC);
1148	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur->pNextHC; pCur = pCur->pNextHC)
1149	{
1150	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1151	if (pCur->pavHCChunkGC)
1152	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1153	}
1154	}
1155
1156	/*
1157	* Update the two page directories with all page table mappings.
1158	* (One or more of them have changed, that's why we're here.)
1159	*/
1160	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1161	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1162	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1163
1164	/* Relocate GC addresses of Page Tables. */
1165	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1166	{
1167	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1168	{
1169	pCur->aPTs[i].pPTGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].pPTR3);
1170	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].paPaePTsR3);
1171	}
1172	}
1173
1174	/*
1175	* Dynamic page mapping area.
1176	*/
1177	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1178	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1179	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1180
1181	/*
1182	* Physical and virtual handlers.
1183	*/
1184	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1185	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1186
1187	/*
1188	* The page pool.
1189	*/
1190	pgmR3PoolRelocate(pVM);
1191	}
1192
1193
1194	/**
1195	* Callback function for relocating a physical access handler.
1196	*
1197	* @returns 0 (continue enum)
1198	* @param pNode Pointer to a PGMPHYSHANDLER node.
1199	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1200	* not certain the delta will fit in a void pointer for all possible configs.
1201	*/
1202	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1203	{
1204	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1205	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1206	if (pHandler->pfnHandlerGC)
1207	pHandler->pfnHandlerGC += offDelta;
1208	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1209	pHandler->pvUserGC += offDelta;
1210	return 0;
1211	}
1212
1213
1214	/**
1215	* Callback function for relocating a virtual access handler.
1216	*
1217	* @returns 0 (continue enum)
1218	* @param pNode Pointer to a PGMVIRTHANDLER node.
1219	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1220	* not certain the delta will fit in a void pointer for all possible configs.
1221	*/
1222	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1223	{
1224	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1225	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1226	Assert(pHandler->pfnHandlerGC);
1227	pHandler->pfnHandlerGC += offDelta;
1228	return 0;
1229	}
1230
1231
1232	/**
1233	* The VM is being reset.
1234	*
1235	* For the PGM component this means that any PD write monitors
1236	* needs to be removed.
1237	*
1238	* @param pVM VM handle.
1239	*/
1240	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1241	{
1242	LogFlow(("PGMR3Reset:\n"));
1243	VM_ASSERT_EMT(pVM);
1244
1245	/*
1246	* Unfix any fixed mappings and disable CR3 monitoring.
1247	*/
1248	pVM->pgm.s.fMappingsFixed = false;
1249	pVM->pgm.s.GCPtrMappingFixed = 0;
1250	pVM->pgm.s.cbMappingFixed = 0;
1251
1252	int rc = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
1253	AssertRC(rc);
1254	#ifdef DEBUG
1255	PGMR3DumpMappings(pVM);
1256	#endif
1257
1258	/*
1259	* Reset the shadow page pool.
1260	*/
1261	pgmR3PoolReset(pVM);
1262
1263	/*
1264	* Re-init other members.
1265	*/
1266	pVM->pgm.s.fA20Enabled = true;
1267
1268	/*
1269	* Clear the FFs PGM owns.
1270	*/
1271	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1272	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1273
1274	/*
1275	* Zero memory.
1276	*/
1277	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
1278	{
1279	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1280	while (iPage-- > 0)
1281	{
1282	if (pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2))
1283	{
1284	/* shadow ram is reloaded elsewhere. */
1285	Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO)));
1286	continue;
1287	}
1288	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1289	{
1290	unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1291	if (pRam->pavHCChunkHC[iChunk])
1292	ASMMemZero32((char *)pRam->pavHCChunkHC[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
1293	}
1294	else
1295	ASMMemZero32((char *)pRam->pvHC + (iPage << PAGE_SHIFT), PAGE_SIZE);
1296	}
1297	}
1298
1299	/*
1300	* Switch mode back to real mode.
1301	*/
1302	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1303	AssertReleaseRC(rc);
1304	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1305	}
1306
1307
1308	/**
1309	* Terminates the PGM.
1310	*
1311	* @returns VBox status code.
1312	* @param pVM Pointer to VM structure.
1313	*/
1314	PGMR3DECL(int) PGMR3Term(PVM pVM)
1315	{
1316	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1317	}
1318
1319
1320	#ifdef VBOX_STRICT
1321	/**
1322	* VM state change callback for clearing fNoMorePhysWrites after
1323	* a snapshot has been created.
1324	*/
1325	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
1326	{
1327	if (enmState == VMSTATE_RUNNING)
1328	pVM->pgm.s.fNoMorePhysWrites = false;
1329	}
1330	#endif
1331
1332
1333	/**
1334	* Execute state save operation.
1335	*
1336	* @returns VBox status code.
1337	* @param pVM VM Handle.
1338	* @param pSSM SSM operation handle.
1339	*/
1340	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1341	{
1342	PPGM pPGM = &pVM->pgm.s;
1343
1344	/* No more writes to physical memory after this point! */
1345	pVM->pgm.s.fNoMorePhysWrites = true;
1346
1347	/*
1348	* Save basic data (required / unaffected by relocation).
1349	*/
1350	#if 1
1351	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1352	#else
1353	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1354	#endif
1355	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1356	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1357	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1358	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1359	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1360	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1361	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1362	SSMR3PutU32(pSSM, ~0); /* Separator. */
1363
1364	/*
1365	* The guest mappings.
1366	*/
1367	uint32_t i = 0;
1368	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1369	{
1370	SSMR3PutU32(pSSM, i);
1371	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1372	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1373	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1374	/* flags are done by the mapping owners! */
1375	}
1376	SSMR3PutU32(pSSM, ~0); /* terminator. */
1377
1378	/*
1379	* Ram range flags and bits.
1380	*/
1381	i = 0;
1382	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1383	{
1384	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1385
1386	SSMR3PutU32(pSSM, i);
1387	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1388	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1389	SSMR3PutGCPhys(pSSM, pRam->cb);
1390	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
1391
1392	/* Flags. */
1393	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1394	for (unsigned iPage = 0; iPage < cPages; iPage++)
1395	SSMR3PutU16(pSSM, (uint16_t)(pRam->aHCPhys[iPage] & ~X86_PTE_PAE_PG_MASK));
1396
1397	/* any memory associated with the range. */
1398	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1399	{
1400	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1401	{
1402	if (pRam->pavHCChunkHC[iChunk])
1403	{
1404	SSMR3PutU8(pSSM, 1); /* chunk present */
1405	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1406	}
1407	else
1408	SSMR3PutU8(pSSM, 0); /* no chunk present */
1409	}
1410	}
1411	else if (pRam->pvHC)
1412	{
1413	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
1414	if (VBOX_FAILURE(rc))
1415	{
1416	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1417	return rc;
1418	}
1419	}
1420	}
1421	return SSMR3PutU32(pSSM, ~0); /* terminator. */
1422	}
1423
1424
1425	/**
1426	* Execute state load operation.
1427	*
1428	* @returns VBox status code.
1429	* @param pVM VM Handle.
1430	* @param pSSM SSM operation handle.
1431	* @param u32Version Data layout version.
1432	*/
1433	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1434	{
1435	/*
1436	* Validate version.
1437	*/
1438	if (u32Version != PGM_SAVED_STATE_VERSION)
1439	{
1440	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
1441	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1442	}
1443
1444	/*
1445	* Call the reset function to make sure all the memory is cleared.
1446	*/
1447	PGMR3Reset(pVM);
1448
1449	/*
1450	* Load basic data (required / unaffected by relocation).
1451	*/
1452	PPGM pPGM = &pVM->pgm.s;
1453	#if 1
1454	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
1455	#else
1456	uint32_t u;
1457	SSMR3GetU32(pSSM, &u);
1458	pPGM->fMappingsFixed = u;
1459	#endif
1460	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
1461	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
1462
1463	RTUINT cbRamSize;
1464	int rc = SSMR3GetU32(pSSM, &cbRamSize);
1465	if (VBOX_FAILURE(rc))
1466	return rc;
1467	if (cbRamSize != pPGM->cbRamSize)
1468	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
1469	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
1470	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
1471	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
1472	RTUINT uGuestMode;
1473	SSMR3GetUInt(pSSM, &uGuestMode);
1474	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
1475
1476	/* check separator. */
1477	uint32_t u32Sep;
1478	SSMR3GetU32(pSSM, &u32Sep);
1479	if (VBOX_FAILURE(rc))
1480	return rc;
1481	if (u32Sep != (uint32_t)~0)
1482	{
1483	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1484	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1485	}
1486
1487	/*
1488	* The guest mappings.
1489	*/
1490	uint32_t i = 0;
1491	for (;; i++)
1492	{
1493	/* Check the seqence number / separator. */
1494	rc = SSMR3GetU32(pSSM, &u32Sep);
1495	if (VBOX_FAILURE(rc))
1496	return rc;
1497	if (u32Sep == ~0U)
1498	break;
1499	if (u32Sep != i)
1500	{
1501	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1502	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1503	}
1504
1505	/* get the mapping details. */
1506	char szDesc[256];
1507	szDesc[0] = '\0';
1508	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
1509	if (VBOX_FAILURE(rc))
1510	return rc;
1511	RTGCPTR GCPtr;
1512	SSMR3GetGCPtr(pSSM, &GCPtr);
1513	RTGCUINTPTR cPTs;
1514	rc = SSMR3GetU32(pSSM, &cPTs);
1515	if (VBOX_FAILURE(rc))
1516	return rc;
1517
1518	/* find matching range. */
1519	PPGMMAPPING pMapping;
1520	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
1521	if ( pMapping->cPTs == cPTs
1522	&& !strcmp(pMapping->pszDesc, szDesc))
1523	break;
1524	if (!pMapping)
1525	{
1526	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
1527	cPTs, szDesc, GCPtr));
1528	AssertFailed();
1529	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1530	}
1531
1532	/* relocate it. */
1533	if (pMapping->GCPtr != GCPtr)
1534	{
1535	AssertMsg((GCPtr >> PGDIR_SHIFT << PGDIR_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
1536	#if HC_ARCH_BITS == 64
1537	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
1538	#endif
1539	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr >> PGDIR_SHIFT, GCPtr >> PGDIR_SHIFT);
1540	}
1541	else
1542	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
1543	}
1544
1545	/*
1546	* Ram range flags and bits.
1547	*/
1548	i = 0;
1549	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1550	{
1551	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1552	/* Check the seqence number / separator. */
1553	rc = SSMR3GetU32(pSSM, &u32Sep);
1554	if (VBOX_FAILURE(rc))
1555	return rc;
1556	if (u32Sep == ~0U)
1557	break;
1558	if (u32Sep != i)
1559	{
1560	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1561	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1562	}
1563
1564	/* Get the range details. */
1565	RTGCPHYS GCPhys;
1566	SSMR3GetGCPhys(pSSM, &GCPhys);
1567	RTGCPHYS GCPhysLast;
1568	SSMR3GetGCPhys(pSSM, &GCPhysLast);
1569	RTGCPHYS cb;
1570	SSMR3GetGCPhys(pSSM, &cb);
1571	uint8_t fHaveBits;
1572	rc = SSMR3GetU8(pSSM, &fHaveBits);
1573	if (VBOX_FAILURE(rc))
1574	return rc;
1575	if (fHaveBits & ~1)
1576	{
1577	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1578	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1579	}
1580
1581	/* Match it up with the current range. */
1582	if ( GCPhys != pRam->GCPhys
1583	\|\| GCPhysLast != pRam->GCPhysLast
1584	\|\| cb != pRam->cb
1585	\|\| fHaveBits != !!pRam->pvHC)
1586	{
1587	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
1588	"State : %VGp-%VGp %VGp bytes %s\n",
1589	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
1590	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
1591	/*
1592	* If we're loading a state for debugging purpose, don't make a fuss if
1593	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
1594	*/
1595	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
1596	\|\| GCPhys < 8 * _1M)
1597	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1598
1599	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
1600	while (cPages-- > 0)
1601	{
1602	uint16_t u16Ignore;
1603	SSMR3GetU16(pSSM, &u16Ignore);
1604	}
1605	continue;
1606	}
1607
1608	/* Flags. */
1609	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1610	for (unsigned iPage = 0; iPage < cPages; iPage++)
1611	{
1612	uint16_t u16 = 0;
1613	SSMR3GetU16(pSSM, &u16);
1614	u16 &= PAGE_OFFSET_MASK & ~( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
1615	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL
1616	\| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF );
1617	pRam->aHCPhys[iPage] = (pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK) \| (RTHCPHYS)u16;
1618	}
1619
1620	/* any memory associated with the range. */
1621	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1622	{
1623	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1624	{
1625	uint8_t fValidChunk;
1626
1627	rc = SSMR3GetU8(pSSM, &fValidChunk);
1628	if (VBOX_FAILURE(rc))
1629	return rc;
1630	if (fValidChunk > 1)
1631	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1632
1633	if (fValidChunk)
1634	{
1635	if (!pRam->pavHCChunkHC[iChunk])
1636	{
1637	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
1638	if (VBOX_FAILURE(rc))
1639	return rc;
1640	}
1641	Assert(pRam->pavHCChunkHC[iChunk]);
1642
1643	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1644	}
1645	/* else nothing to do */
1646	}
1647	}
1648	else if (pRam->pvHC)
1649	{
1650	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
1651	if (VBOX_FAILURE(rc))
1652	{
1653	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1654	return rc;
1655	}
1656	}
1657	}
1658
1659	/*
1660	* We require a full resync now.
1661	*/
1662	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1663	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1664	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
1665	pPGM->fPhysCacheFlushPending = true;
1666	pgmR3HandlerPhysicalUpdateAll(pVM);
1667
1668	/*
1669	* Change the paging mode.
1670	*/
1671	return pgmR3ChangeMode(pVM, pPGM->enmGuestMode);
1672	}
1673
1674
1675	/**
1676	* Show paging mode.
1677	*
1678	* @param pVM VM Handle.
1679	* @param pHlp The info helpers.
1680	* @param pszArgs "all" (default), "guest", "shadow" or "host".
1681	*/
1682	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1683	{
1684	/* digest argument. */
1685	bool fGuest, fShadow, fHost;
1686	if (pszArgs)
1687	pszArgs = RTStrStripL(pszArgs);
1688	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
1689	fShadow = fHost = fGuest = true;
1690	else
1691	{
1692	fShadow = fHost = fGuest = false;
1693	if (strstr(pszArgs, "guest"))
1694	fGuest = true;
1695	if (strstr(pszArgs, "shadow"))
1696	fShadow = true;
1697	if (strstr(pszArgs, "host"))
1698	fHost = true;
1699	}
1700
1701	/* print info. */
1702	if (fGuest)
1703	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
1704	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
1705	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
1706	if (fShadow)
1707	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
1708	if (fHost)
1709	{
1710	const char *psz;
1711	switch (pVM->pgm.s.enmHostMode)
1712	{
1713	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
1714	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
1715	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
1716	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
1717	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
1718	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
1719	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
1720	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
1721	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
1722	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
1723	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
1724	default: psz = "unknown"; break;
1725	}
1726	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
1727	}
1728	}
1729
1730
1731	/**
1732	* Dump registered MMIO ranges to the log.
1733	*
1734	* @param pVM VM Handle.
1735	* @param pHlp The info helpers.
1736	* @param pszArgs Arguments, ignored.
1737	*/
1738	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1739	{
1740	NOREF(pszArgs);
1741	pHlp->pfnPrintf(pHlp,
1742	"RAM ranges (pVM=%p)\n"
1743	"%.s %.s\n",
1744	pVM,
1745	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
1746	sizeof(RTHCPTR) * 2, "pvHC ");
1747
1748	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur; pCur = pCur->pNextHC)
1749	pHlp->pfnPrintf(pHlp,
1750	"%VGp-%VGp %VHv\n",
1751	pCur->GCPhys,
1752	pCur->GCPhysLast,
1753	pCur->pvHC);
1754	}
1755
1756	/**
1757	* Dump the page directory to the log.
1758	*
1759	* @param pVM VM Handle.
1760	* @param pHlp The info helpers.
1761	* @param pszArgs Arguments, ignored.
1762	*/
1763	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1764	{
1765	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
1766	/* Big pages supported? */
1767	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1768	/* Global pages supported? */
1769	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
1770
1771	NOREF(pszArgs);
1772
1773	/*
1774	* Get page directory addresses.
1775	*/
1776	PVBOXPD pPDSrc = pVM->pgm.s.pGuestPDHC;
1777	Assert(pPDSrc);
1778	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
1779
1780	/*
1781	* Iterate the page directory.
1782	*/
1783	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
1784	{
1785	VBOXPDE PdeSrc = pPDSrc->a[iPD];
1786	if (PdeSrc.n.u1Present)
1787	{
1788	if (PdeSrc.b.u1Size && fPSE)
1789	{
1790	pHlp->pfnPrintf(pHlp,
1791	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
1792	iPD,
1793	PdeSrc.u & X86_PDE_PG_MASK,
1794	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
1795	}
1796	else
1797	{
1798	pHlp->pfnPrintf(pHlp,
1799	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
1800	iPD,
1801	PdeSrc.u & X86_PDE4M_PG_MASK,
1802	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
1803	}
1804	}
1805	}
1806	}
1807
1808
1809	/**
1810	* Serivce a VMMCALLHOST_PGM_LOCK call.
1811	*
1812	* @returns VBox status code.
1813	* @param pVM The VM handle.
1814	*/
1815	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
1816	{
1817	return pgmLock(pVM);
1818	}
1819
1820
1821	/**
1822	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
1823	*
1824	* @returns PGM_TYPE_*.
1825	* @param pgmMode The mode value to convert.
1826	*/
1827	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
1828	{
1829	switch (pgmMode)
1830	{
1831	case PGMMODE_REAL: return PGM_TYPE_REAL;
1832	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
1833	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
1834	case PGMMODE_PAE:
1835	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
1836	case PGMMODE_AMD64:
1837	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
1838	default:
1839	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
1840	}
1841	}
1842
1843
1844	/**
1845	* Gets the index into the paging mode data array of a SHW+GST mode.
1846	*
1847	* @returns PGM::paPagingData index.
1848	* @param uShwType The shadow paging mode type.
1849	* @param uGstType The guest paging mode type.
1850	*/
1851	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
1852	{
1853	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_AMD64);
1854	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
1855	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_32BIT + 1)
1856	+ (uGstType - PGM_TYPE_REAL);
1857	}
1858
1859
1860	/**
1861	* Gets the index into the paging mode data array of a SHW+GST mode.
1862	*
1863	* @returns PGM::paPagingData index.
1864	* @param enmShw The shadow paging mode.
1865	* @param enmGst The guest paging mode.
1866	*/
1867	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
1868	{
1869	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
1870	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
1871	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
1872	}
1873
1874
1875	/**
1876	* Calculates the max data index.
1877	* @returns The number of entries in the pagaing data array.
1878	*/
1879	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
1880	{
1881	return pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64) + 1;
1882	}
1883
1884
1885	/**
1886	* Initializes the paging mode data kept in PGM::paModeData.
1887	*
1888	* @param pVM The VM handle.
1889	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
1890	* This is used early in the init process to avoid trouble with PDM
1891	* not being initialized yet.
1892	*/
1893	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
1894	{
1895	PPGMMODEDATA pModeData;
1896	int rc;
1897
1898	/*
1899	* Allocate the array on the first call.
1900	*/
1901	if (!pVM->pgm.s.paModeData)
1902	{
1903	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
1904	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
1905	}
1906
1907	/*
1908	* Initialize the array entries.
1909	*/
1910	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
1911	pModeData->uShwType = PGM_TYPE_32BIT;
1912	pModeData->uGstType = PGM_TYPE_REAL;
1913	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1914	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1915	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1916
1917	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
1918	pModeData->uShwType = PGM_TYPE_32BIT;
1919	pModeData->uGstType = PGM_TYPE_PROT;
1920	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1921	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1922	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1923
1924	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
1925	pModeData->uShwType = PGM_TYPE_32BIT;
1926	pModeData->uGstType = PGM_TYPE_32BIT;
1927	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1928	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1929	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1930
1931	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
1932	pModeData->uShwType = PGM_TYPE_PAE;
1933	pModeData->uGstType = PGM_TYPE_REAL;
1934	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1935	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1936	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1937
1938	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
1939	pModeData->uShwType = PGM_TYPE_PAE;
1940	pModeData->uGstType = PGM_TYPE_PROT;
1941	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1942	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1943	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1944
1945	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
1946	pModeData->uShwType = PGM_TYPE_PAE;
1947	pModeData->uGstType = PGM_TYPE_32BIT;
1948	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1949	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1950	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1951
1952	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
1953	pModeData->uShwType = PGM_TYPE_PAE;
1954	pModeData->uGstType = PGM_TYPE_PAE;
1955	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1956	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1957	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1958
1959	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_REAL)];
1960	pModeData->uShwType = PGM_TYPE_AMD64;
1961	pModeData->uGstType = PGM_TYPE_REAL;
1962	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1963	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1964	rc = PGM_BTH_NAME_AMD64_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1965
1966	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_PROT)];
1967	pModeData->uShwType = PGM_TYPE_AMD64;
1968	pModeData->uGstType = PGM_TYPE_PROT;
1969	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1970	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1971	rc = PGM_BTH_NAME_AMD64_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1972
1973	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
1974	pModeData->uShwType = PGM_TYPE_AMD64;
1975	pModeData->uGstType = PGM_TYPE_AMD64;
1976	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1977	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1978	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1979
1980	return VINF_SUCCESS;
1981	}
1982
1983
1984	/**
1985	* Swtich to different (or relocated in the relocate case) mode data.
1986	*
1987	* @param pVM The VM handle.
1988	* @param enmShw The the shadow paging mode.
1989	* @param enmGst The the guest paging mode.
1990	*/
1991	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
1992	{
1993	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(enmShw, enmGst)];
1994
1995	Assert(pModeData->uGstType == pgmModeToType(enmGst));
1996	Assert(pModeData->uShwType == pgmModeToType(enmShw));
1997
1998	/* shadow */
1999	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2000	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2001	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2002	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2003	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2004	pVM->pgm.s.pfnR3ShwGetPDEByIndex = pModeData->pfnR3ShwGetPDEByIndex;
2005	pVM->pgm.s.pfnR3ShwSetPDEByIndex = pModeData->pfnR3ShwSetPDEByIndex;
2006	pVM->pgm.s.pfnR3ShwModifyPDEByIndex = pModeData->pfnR3ShwModifyPDEByIndex;
2007
2008	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2009	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2010	pVM->pgm.s.pfnGCShwGetPDEByIndex = pModeData->pfnGCShwGetPDEByIndex;
2011	pVM->pgm.s.pfnGCShwSetPDEByIndex = pModeData->pfnGCShwSetPDEByIndex;
2012	pVM->pgm.s.pfnGCShwModifyPDEByIndex = pModeData->pfnGCShwModifyPDEByIndex;
2013
2014	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2015	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2016	pVM->pgm.s.pfnR0ShwGetPDEByIndex = pModeData->pfnR0ShwGetPDEByIndex;
2017	pVM->pgm.s.pfnR0ShwSetPDEByIndex = pModeData->pfnR0ShwSetPDEByIndex;
2018	pVM->pgm.s.pfnR0ShwModifyPDEByIndex = pModeData->pfnR0ShwModifyPDEByIndex;
2019
2020
2021	/* guest */
2022	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2023	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2024	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2025	Assert(pVM->pgm.s.pfnR3GstGetPage);
2026	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2027	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2028	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2029	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2030	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2031	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2032	pVM->pgm.s.pfnHCGstWriteHandlerCR3 = pModeData->pfnHCGstWriteHandlerCR3;
2033	pVM->pgm.s.pszHCGstWriteHandlerCR3 = pModeData->pszHCGstWriteHandlerCR3;
2034
2035	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2036	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2037	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2038	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2039	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2040	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2041	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2042	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2043
2044	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2045	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2046	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2047	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2048	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2049	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2050	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2051	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2052
2053
2054	/* both */
2055	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2056	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2057	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2058	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2059	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2060	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2061	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2062	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2063	#ifdef VBOX_STRICT
2064	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2065	#endif
2066
2067	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2068	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2069	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2070	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2071	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2072	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2073	#ifdef VBOX_STRICT
2074	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2075	#endif
2076
2077	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2078	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2079	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2080	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2081	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2082	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2083	#ifdef VBOX_STRICT
2084	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2085	#endif
2086	}
2087
2088
2089	#ifdef DEBUG_bird
2090	#include <stdlib.h> /* getenv() remove me! */
2091	#endif
2092
2093	/**
2094	* Calculates the shadow paging mode.
2095	*
2096	* @returns The shadow paging mode.
2097	* @param enmGuestMode The guest mode.
2098	* @param enmHostMode The host mode.
2099	* @param enmShadowMode The current shadow mode.
2100	* @param penmSwitcher Where to store the switcher to use.
2101	* VMMSWITCHER_INVALID means no change.
2102	*/
2103	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2104	{
2105	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2106	switch (enmGuestMode)
2107	{
2108	/*
2109	* When switching to real or protected mode we don't change
2110	* anything since it's likely that we'll switch back pretty soon.
2111	*
2112	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2113	* and is supposed to determin which shadow paging and switcher to
2114	* use during init.
2115	*/
2116	case PGMMODE_REAL:
2117	case PGMMODE_PROTECTED:
2118	if (enmShadowMode != PGMMODE_INVALID)
2119	break; /* (no change) */
2120	switch (enmHostMode)
2121	{
2122	case SUPPAGINGMODE_32_BIT:
2123	case SUPPAGINGMODE_32_BIT_GLOBAL:
2124	enmShadowMode = PGMMODE_32_BIT;
2125	enmSwitcher = VMMSWITCHER_32_TO_32;
2126	break;
2127
2128	case SUPPAGINGMODE_PAE:
2129	case SUPPAGINGMODE_PAE_NX:
2130	case SUPPAGINGMODE_PAE_GLOBAL:
2131	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2132	enmShadowMode = PGMMODE_PAE;
2133	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2134	#ifdef DEBUG_bird
2135	if (getenv("VBOX_32BIT"))
2136	{
2137	enmShadowMode = PGMMODE_32_BIT;
2138	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2139	}
2140	#endif
2141	break;
2142
2143	case SUPPAGINGMODE_AMD64:
2144	case SUPPAGINGMODE_AMD64_GLOBAL:
2145	case SUPPAGINGMODE_AMD64_NX:
2146	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2147	enmShadowMode = PGMMODE_PAE;
2148	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2149	break;
2150
2151	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2152	}
2153	break;
2154
2155	case PGMMODE_32_BIT:
2156	switch (enmHostMode)
2157	{
2158	case SUPPAGINGMODE_32_BIT:
2159	case SUPPAGINGMODE_32_BIT_GLOBAL:
2160	enmShadowMode = PGMMODE_32_BIT;
2161	enmSwitcher = VMMSWITCHER_32_TO_32;
2162	break;
2163
2164	case SUPPAGINGMODE_PAE:
2165	case SUPPAGINGMODE_PAE_NX:
2166	case SUPPAGINGMODE_PAE_GLOBAL:
2167	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2168	enmShadowMode = PGMMODE_PAE;
2169	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2170	#ifdef DEBUG_bird
2171	if (getenv("VBOX_32BIT"))
2172	{
2173	enmShadowMode = PGMMODE_32_BIT;
2174	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2175	}
2176	#endif
2177	break;
2178
2179	case SUPPAGINGMODE_AMD64:
2180	case SUPPAGINGMODE_AMD64_GLOBAL:
2181	case SUPPAGINGMODE_AMD64_NX:
2182	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2183	enmShadowMode = PGMMODE_PAE;
2184	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2185	break;
2186
2187	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2188	}
2189	break;
2190
2191	case PGMMODE_PAE:
2192	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2193	switch (enmHostMode)
2194	{
2195	case SUPPAGINGMODE_32_BIT:
2196	case SUPPAGINGMODE_32_BIT_GLOBAL:
2197	enmShadowMode = PGMMODE_PAE;
2198	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2199	break;
2200
2201	case SUPPAGINGMODE_PAE:
2202	case SUPPAGINGMODE_PAE_NX:
2203	case SUPPAGINGMODE_PAE_GLOBAL:
2204	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2205	enmShadowMode = PGMMODE_PAE;
2206	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2207	break;
2208
2209	case SUPPAGINGMODE_AMD64:
2210	case SUPPAGINGMODE_AMD64_GLOBAL:
2211	case SUPPAGINGMODE_AMD64_NX:
2212	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2213	enmShadowMode = PGMMODE_PAE;
2214	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2215	break;
2216
2217	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2218	}
2219	break;
2220
2221	case PGMMODE_AMD64:
2222	case PGMMODE_AMD64_NX:
2223	switch (enmHostMode)
2224	{
2225	case SUPPAGINGMODE_32_BIT:
2226	case SUPPAGINGMODE_32_BIT_GLOBAL:
2227	enmShadowMode = PGMMODE_PAE;
2228	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2229	break;
2230
2231	case SUPPAGINGMODE_PAE:
2232	case SUPPAGINGMODE_PAE_NX:
2233	case SUPPAGINGMODE_PAE_GLOBAL:
2234	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2235	enmShadowMode = PGMMODE_PAE;
2236	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2237	break;
2238
2239	case SUPPAGINGMODE_AMD64:
2240	case SUPPAGINGMODE_AMD64_GLOBAL:
2241	case SUPPAGINGMODE_AMD64_NX:
2242	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2243	enmShadowMode = PGMMODE_PAE;
2244	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2245	break;
2246
2247	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2248	}
2249	break;
2250
2251
2252	default:
2253	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2254	return PGMMODE_INVALID;
2255	}
2256
2257	*penmSwitcher = enmSwitcher;
2258	return enmShadowMode;
2259	}
2260
2261
2262	/**
2263	* Performs the actual mode change.
2264	* This is called by PGMChangeMode and pgmR3InitPaging().
2265	*
2266	* @returns VBox status code.
2267	* @param pVM VM handle.
2268	* @param enmGuestMode The new guest mode. This is assumed to be different from
2269	* the current mode.
2270	*/
2271	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
2272	{
2273	LogFlow(("pgmR3ChangeMode: Guest mode: %d -> %d\n", pVM->pgm.s.enmGuestMode, enmGuestMode));
2274	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
2275
2276	/*
2277	* Calc the shadow mode and switcher.
2278	*/
2279	VMMSWITCHER enmSwitcher;
2280	PGMMODE enmShadowMode = pgmR3CalcShadowMode(enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
2281	if (enmSwitcher != VMMSWITCHER_INVALID)
2282	{
2283	/*
2284	* Select new switcher.
2285	*/
2286	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
2287	if (VBOX_FAILURE(rc))
2288	{
2289	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
2290	return rc;
2291	}
2292	}
2293
2294	/*
2295	* Exit old mode(s).
2296	*/
2297	/* shadow */
2298	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2299	{
2300	LogFlow(("pgmR3ChangeMode: Shadow mode: %d -> %d\n", pVM->pgm.s.enmShadowMode, enmShadowMode));
2301	if (PGM_SHW_PFN(Exit, pVM))
2302	{
2303	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
2304	if (VBOX_FAILURE(rc))
2305	{
2306	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
2307	return rc;
2308	}
2309	}
2310
2311	}
2312
2313	/* guest */
2314	if (PGM_GST_PFN(Exit, pVM))
2315	{
2316	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2317	if (VBOX_FAILURE(rc))
2318	{
2319	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
2320	return rc;
2321	}
2322	}
2323
2324	/*
2325	* Load new paging mode data.
2326	*/
2327	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
2328
2329	/*
2330	* Enter new shadow mode (if changed).
2331	*/
2332	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2333	{
2334	int rc;
2335	pVM->pgm.s.enmShadowMode = enmShadowMode;
2336	switch (enmShadowMode)
2337	{
2338	case PGMMODE_32_BIT:
2339	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
2340	break;
2341	case PGMMODE_PAE:
2342	case PGMMODE_PAE_NX:
2343	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
2344	break;
2345	case PGMMODE_AMD64:
2346	case PGMMODE_AMD64_NX:
2347	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
2348	break;
2349	case PGMMODE_REAL:
2350	case PGMMODE_PROTECTED:
2351	default:
2352	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
2353	return VERR_INTERNAL_ERROR;
2354	}
2355	if (VBOX_FAILURE(rc))
2356	{
2357	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
2358	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
2359	return rc;
2360	}
2361	}
2362
2363	/*
2364	* Enter the new guest and shadow+guest modes.
2365	*/
2366	int rc = -1;
2367	int rc2 = -1;
2368	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
2369	pVM->pgm.s.enmGuestMode = enmGuestMode;
2370	switch (enmGuestMode)
2371	{
2372	case PGMMODE_REAL:
2373	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
2374	switch (pVM->pgm.s.enmShadowMode)
2375	{
2376	case PGMMODE_32_BIT:
2377	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
2378	break;
2379	case PGMMODE_PAE:
2380	case PGMMODE_PAE_NX:
2381	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
2382	break;
2383	case PGMMODE_AMD64:
2384	case PGMMODE_AMD64_NX:
2385	rc2 = PGM_BTH_NAME_AMD64_REAL(Enter)(pVM, NIL_RTGCPHYS);
2386	break;
2387	default: AssertFailed(); break;
2388	}
2389	break;
2390
2391	case PGMMODE_PROTECTED:
2392	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
2393	switch (pVM->pgm.s.enmShadowMode)
2394	{
2395	case PGMMODE_32_BIT:
2396	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
2397	break;
2398	case PGMMODE_PAE:
2399	case PGMMODE_PAE_NX:
2400	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
2401	break;
2402	case PGMMODE_AMD64:
2403	case PGMMODE_AMD64_NX:
2404	rc2 = PGM_BTH_NAME_AMD64_PROT(Enter)(pVM, NIL_RTGCPHYS);
2405	break;
2406	default: AssertFailed(); break;
2407	}
2408	break;
2409
2410	case PGMMODE_32_BIT:
2411	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
2412	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
2413	switch (pVM->pgm.s.enmShadowMode)
2414	{
2415	case PGMMODE_32_BIT:
2416	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
2417	break;
2418	case PGMMODE_PAE:
2419	case PGMMODE_PAE_NX:
2420	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
2421	break;
2422	case PGMMODE_AMD64:
2423	case PGMMODE_AMD64_NX:
2424	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2425	default: AssertFailed(); break;
2426	}
2427	break;
2428
2429	//case PGMMODE_PAE_NX:
2430	case PGMMODE_PAE:
2431	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
2432	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
2433	switch (pVM->pgm.s.enmShadowMode)
2434	{
2435	case PGMMODE_PAE:
2436	case PGMMODE_PAE_NX:
2437	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
2438	break;
2439	case PGMMODE_32_BIT:
2440	case PGMMODE_AMD64:
2441	case PGMMODE_AMD64_NX:
2442	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2443	default: AssertFailed(); break;
2444	}
2445	break;
2446
2447	//case PGMMODE_AMD64_NX:
2448	case PGMMODE_AMD64:
2449	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask and make CR3 64-bit in this case! */
2450	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
2451	switch (pVM->pgm.s.enmShadowMode)
2452	{
2453	case PGMMODE_AMD64:
2454	case PGMMODE_AMD64_NX:
2455	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
2456	break;
2457	case PGMMODE_32_BIT:
2458	case PGMMODE_PAE:
2459	case PGMMODE_PAE_NX:
2460	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
2461	default: AssertFailed(); break;
2462	}
2463	break;
2464
2465	default:
2466	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2467	rc = VERR_NOT_IMPLEMENTED;
2468	break;
2469	}
2470
2471	/* status codes. */
2472	AssertRC(rc);
2473	AssertRC(rc2);
2474	if (VBOX_SUCCESS(rc))
2475	{
2476	rc = rc2;
2477	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
2478	rc = VINF_SUCCESS;
2479	}
2480
2481	/*
2482	* Notify SELM so it can update the TSSes with correct CR3s.
2483	*/
2484	SELMR3PagingModeChanged(pVM);
2485
2486	/* Notify HWACCM as well. */
2487	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
2488	return rc;
2489	}
2490
2491
2492	/**
2493	* Dumps a PAE shadow page table.
2494	*
2495	* @returns VBox status code (VINF_SUCCESS).
2496	* @param pVM The VM handle.
2497	* @param pPT Pointer to the page table.
2498	* @param u64Address The virtual address of the page table starts.
2499	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2500	* @param cMaxDepth The maxium depth.
2501	* @param pHlp Pointer to the output functions.
2502	*/
2503	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2504	{
2505	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2506	{
2507	X86PTEPAE Pte = pPT->a[i];
2508	if (Pte.n.u1Present)
2509	{
2510	pHlp->pfnPrintf(pHlp,
2511	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2512	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
2513	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
2514	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
2515	Pte.n.u1Write ? 'W' : 'R',
2516	Pte.n.u1User ? 'U' : 'S',
2517	Pte.n.u1Accessed ? 'A' : '-',
2518	Pte.n.u1Dirty ? 'D' : '-',
2519	Pte.n.u1Global ? 'G' : '-',
2520	Pte.n.u1WriteThru ? "WT" : "--",
2521	Pte.n.u1CacheDisable? "CD" : "--",
2522	Pte.n.u1PAT ? "AT" : "--",
2523	Pte.n.u1NoExecute ? "NX" : "--",
2524	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2525	Pte.u & BIT(10) ? '1' : '0',
2526	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
2527	Pte.u & X86_PTE_PAE_PG_MASK);
2528	}
2529	}
2530	return VINF_SUCCESS;
2531	}
2532
2533
2534	/**
2535	* Dumps a PAE shadow page directory table.
2536	*
2537	* @returns VBox status code (VINF_SUCCESS).
2538	* @param pVM The VM handle.
2539	* @param HCPhys The physical address of the page directory table.
2540	* @param u64Address The virtual address of the page table starts.
2541	* @param cr4 The CR4, PSE is currently used.
2542	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2543	* @param cMaxDepth The maxium depth.
2544	* @param pHlp Pointer to the output functions.
2545	*/
2546	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2547	{
2548	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
2549	if (!pPD)
2550	{
2551	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
2552	fLongMode ? 16 : 8, u64Address, HCPhys);
2553	return VERR_INVALID_PARAMETER;
2554	}
2555	int rc = VINF_SUCCESS;
2556	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2557	{
2558	X86PDEPAE Pde = pPD->a[i];
2559	if (Pde.n.u1Present)
2560	{
2561	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2562	pHlp->pfnPrintf(pHlp,
2563	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2564	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
2565	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
2566	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2567	Pde.b.u1Write ? 'W' : 'R',
2568	Pde.b.u1User ? 'U' : 'S',
2569	Pde.b.u1Accessed ? 'A' : '-',
2570	Pde.b.u1Dirty ? 'D' : '-',
2571	Pde.b.u1Global ? 'G' : '-',
2572	Pde.b.u1WriteThru ? "WT" : "--",
2573	Pde.b.u1CacheDisable? "CD" : "--",
2574	Pde.b.u1PAT ? "AT" : "--",
2575	Pde.b.u1NoExecute ? "NX" : "--",
2576	Pde.u & BIT64(9) ? '1' : '0',
2577	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2578	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2579	Pde.u & X86_PDE_PAE_PG_MASK);
2580	else
2581	{
2582	pHlp->pfnPrintf(pHlp,
2583	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2584	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
2585	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
2586	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2587	Pde.n.u1Write ? 'W' : 'R',
2588	Pde.n.u1User ? 'U' : 'S',
2589	Pde.n.u1Accessed ? 'A' : '-',
2590	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2591	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2592	Pde.n.u1WriteThru ? "WT" : "--",
2593	Pde.n.u1CacheDisable? "CD" : "--",
2594	Pde.n.u1NoExecute ? "NX" : "--",
2595	Pde.u & BIT64(9) ? '1' : '0',
2596	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2597	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2598	Pde.u & X86_PDE_PAE_PG_MASK);
2599	if (cMaxDepth >= 1)
2600	{
2601	/** @todo what about using the page pool for mapping PTs? */
2602	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
2603	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
2604	PX86PTPAE pPT = NULL;
2605	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2606	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
2607	else
2608	{
2609	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
2610	{
2611	uint64_t off = u64AddressPT - pMap->GCPtr;
2612	if (off < pMap->cb)
2613	{
2614	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
2615	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
2616	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
2617	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2618	fLongMode ? 16 : 8, u64AddressPT, iPDE,
2619	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
2620	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
2621	}
2622	}
2623	}
2624	int rc2 = VERR_INVALID_PARAMETER;
2625	if (pPT)
2626	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
2627	else
2628	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
2629	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
2630	if (rc2 < rc && VBOX_SUCCESS(rc))
2631	rc = rc2;
2632	}
2633	}
2634	}
2635	}
2636	return rc;
2637	}
2638
2639
2640	/**
2641	* Dumps a PAE shadow page directory pointer table.
2642	*
2643	* @returns VBox status code (VINF_SUCCESS).
2644	* @param pVM The VM handle.
2645	* @param HCPhys The physical address of the page directory pointer table.
2646	* @param u64Address The virtual address of the page table starts.
2647	* @param cr4 The CR4, PSE is currently used.
2648	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2649	* @param cMaxDepth The maxium depth.
2650	* @param pHlp Pointer to the output functions.
2651	*/
2652	static int pgmR3DumpHierarchyHCPaePDPTR(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2653	{
2654	PX86PDPTR pPDPTR = (PX86PDPTR)MMPagePhys2Page(pVM, HCPhys);
2655	if (!pPDPTR)
2656	{
2657	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
2658	fLongMode ? 16 : 8, u64Address, HCPhys);
2659	return VERR_INVALID_PARAMETER;
2660	}
2661
2662	int rc = VINF_SUCCESS;
2663	const unsigned c = fLongMode ? ELEMENTS(pPDPTR->a) : 4;
2664	for (unsigned i = 0; i < c; i++)
2665	{
2666	X86PDPE Pdpe = pPDPTR->a[i];
2667	if (Pdpe.n.u1Present)
2668	{
2669	if (fLongMode)
2670	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2671	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2672	u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2673	Pdpe.n.u1Write ? 'W' : 'R',
2674	Pdpe.n.u1User ? 'U' : 'S',
2675	Pdpe.n.u1Accessed ? 'A' : '-',
2676	Pdpe.n.u3Reserved & 1? '?' : '.', /* ignored */
2677	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2678	Pdpe.n.u1WriteThru ? "WT" : "--",
2679	Pdpe.n.u1CacheDisable? "CD" : "--",
2680	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2681	Pdpe.n.u1NoExecute ? "NX" : "--",
2682	Pdpe.u & BIT(9) ? '1' : '0',
2683	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2684	Pdpe.u & BIT(11) ? '1' : '0',
2685	Pdpe.u & X86_PDPE_PG_MASK);
2686	else
2687	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2688	"%08x 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2689	i << X86_PDPTR_SHIFT,
2690	Pdpe.n.u1Write ? '!' : '.', /* mbz */
2691	Pdpe.n.u1User ? '!' : '.', /* mbz */
2692	Pdpe.n.u1Accessed ? '!' : '.', /* mbz */
2693	Pdpe.n.u3Reserved & 1? '!' : '.', /* mbz */
2694	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2695	Pdpe.n.u1WriteThru ? "WT" : "--",
2696	Pdpe.n.u1CacheDisable? "CD" : "--",
2697	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2698	Pdpe.n.u1NoExecute ? "NX" : "--",
2699	Pdpe.u & BIT(9) ? '1' : '0',
2700	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2701	Pdpe.u & BIT(11) ? '1' : '0',
2702	Pdpe.u & X86_PDPE_PG_MASK);
2703	if (cMaxDepth >= 1)
2704	{
2705	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2706	cr4, fLongMode, cMaxDepth - 1, pHlp);
2707	if (rc2 < rc && VBOX_SUCCESS(rc))
2708	rc = rc2;
2709	}
2710	}
2711	}
2712	return rc;
2713	}
2714
2715
2716	/**
2717	* Dumps a 32-bit shadow page table.
2718	*
2719	* @returns VBox status code (VINF_SUCCESS).
2720	* @param pVM The VM handle.
2721	* @param HCPhys The physical address of the table.
2722	* @param cr4 The CR4, PSE is currently used.
2723	* @param cMaxDepth The maxium depth.
2724	* @param pHlp Pointer to the output functions.
2725	*/
2726	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2727	{
2728	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
2729	if (!pPML4)
2730	{
2731	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
2732	return VERR_INVALID_PARAMETER;
2733	}
2734
2735	int rc = VINF_SUCCESS;
2736	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
2737	{
2738	X86PML4E Pml4e = pPML4->a[i];
2739	if (Pml4e.n.u1Present)
2740	{
2741	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPTR_SHIFT - 1)) * 0xffff000000000000ULL);
2742	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2743	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2744	u64Address,
2745	Pml4e.n.u1Write ? 'W' : 'R',
2746	Pml4e.n.u1User ? 'U' : 'S',
2747	Pml4e.n.u1Accessed ? 'A' : '-',
2748	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
2749	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
2750	Pml4e.n.u1WriteThru ? "WT" : "--",
2751	Pml4e.n.u1CacheDisable? "CD" : "--",
2752	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
2753	Pml4e.n.u1NoExecute ? "NX" : "--",
2754	Pml4e.u & BIT(9) ? '1' : '0',
2755	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2756	Pml4e.u & BIT(11) ? '1' : '0',
2757	Pml4e.u & X86_PML4E_PG_MASK);
2758
2759	if (cMaxDepth >= 1)
2760	{
2761	int rc2 = pgmR3DumpHierarchyHCPaePDPTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
2762	if (rc2 < rc && VBOX_SUCCESS(rc))
2763	rc = rc2;
2764	}
2765	}
2766	}
2767	return rc;
2768	}
2769
2770
2771	/**
2772	* Dumps a 32-bit shadow page table.
2773	*
2774	* @returns VBox status code (VINF_SUCCESS).
2775	* @param pVM The VM handle.
2776	* @param pPT Pointer to the page table.
2777	* @param u32Address The virtual address this table starts at.
2778	* @param pHlp Pointer to the output functions.
2779	*/
2780	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
2781	{
2782	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2783	{
2784	X86PTE Pte = pPT->a[i];
2785	if (Pte.n.u1Present)
2786	{
2787	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2788	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2789	u32Address + (i << X86_PT_SHIFT),
2790	Pte.n.u1Write ? 'W' : 'R',
2791	Pte.n.u1User ? 'U' : 'S',
2792	Pte.n.u1Accessed ? 'A' : '-',
2793	Pte.n.u1Dirty ? 'D' : '-',
2794	Pte.n.u1Global ? 'G' : '-',
2795	Pte.n.u1WriteThru ? "WT" : "--",
2796	Pte.n.u1CacheDisable? "CD" : "--",
2797	Pte.n.u1PAT ? "AT" : "--",
2798	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2799	Pte.u & BIT(10) ? '1' : '0',
2800	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2801	Pte.u & X86_PDE_PG_MASK);
2802	}
2803	}
2804	return VINF_SUCCESS;
2805	}
2806
2807
2808	/**
2809	* Dumps a 32-bit shadow page directory and page tables.
2810	*
2811	* @returns VBox status code (VINF_SUCCESS).
2812	* @param pVM The VM handle.
2813	* @param cr3 The root of the hierarchy.
2814	* @param cr4 The CR4, PSE is currently used.
2815	* @param cMaxDepth How deep into the hierarchy the dumper should go.
2816	* @param pHlp Pointer to the output functions.
2817	*/
2818	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2819	{
2820	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
2821	if (!pPD)
2822	{
2823	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
2824	return VERR_INVALID_PARAMETER;
2825	}
2826
2827	int rc = VINF_SUCCESS;
2828	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2829	{
2830	X86PDE Pde = pPD->a[i];
2831	if (Pde.n.u1Present)
2832	{
2833	const uint32_t u32Address = i << X86_PD_SHIFT;
2834	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2835	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2836	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2837	u32Address,
2838	Pde.b.u1Write ? 'W' : 'R',
2839	Pde.b.u1User ? 'U' : 'S',
2840	Pde.b.u1Accessed ? 'A' : '-',
2841	Pde.b.u1Dirty ? 'D' : '-',
2842	Pde.b.u1Global ? 'G' : '-',
2843	Pde.b.u1WriteThru ? "WT" : "--",
2844	Pde.b.u1CacheDisable? "CD" : "--",
2845	Pde.b.u1PAT ? "AT" : "--",
2846	Pde.u & BIT64(9) ? '1' : '0',
2847	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2848	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2849	Pde.u & X86_PDE4M_PG_MASK);
2850	else
2851	{
2852	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2853	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
2854	u32Address,
2855	Pde.n.u1Write ? 'W' : 'R',
2856	Pde.n.u1User ? 'U' : 'S',
2857	Pde.n.u1Accessed ? 'A' : '-',
2858	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2859	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2860	Pde.n.u1WriteThru ? "WT" : "--",
2861	Pde.n.u1CacheDisable? "CD" : "--",
2862	Pde.u & BIT64(9) ? '1' : '0',
2863	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2864	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2865	Pde.u & X86_PDE_PG_MASK);
2866	if (cMaxDepth >= 1)
2867	{
2868	/** @todo what about using the page pool for mapping PTs? */
2869	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
2870	PX86PT pPT = NULL;
2871	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2872	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
2873	else
2874	{
2875	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
2876	if (u32Address - pMap->GCPtr < pMap->cb)
2877	{
2878	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
2879	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
2880	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2881	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
2882	pPT = pMap->aPTs[iPDE].pPTR3;
2883	}
2884	}
2885	int rc2 = VERR_INVALID_PARAMETER;
2886	if (pPT)
2887	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
2888	else
2889	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
2890	if (rc2 < rc && VBOX_SUCCESS(rc))
2891	rc = rc2;
2892	}
2893	}
2894	}
2895	}
2896
2897	return rc;
2898	}
2899
2900
2901	/**
2902	* Dumps a 32-bit shadow page table.
2903	*
2904	* @returns VBox status code (VINF_SUCCESS).
2905	* @param pVM The VM handle.
2906	* @param pPT Pointer to the page table.
2907	* @param u32Address The virtual address this table starts at.
2908	* @param PhysSearch Address to search for.
2909	*/
2910	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
2911	{
2912	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2913	{
2914	X86PTE Pte = pPT->a[i];
2915	if (Pte.n.u1Present)
2916	{
2917	Log(( /P R S A D G WT CD AT NX 4M a m d /
2918	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2919	u32Address + (i << X86_PT_SHIFT),
2920	Pte.n.u1Write ? 'W' : 'R',
2921	Pte.n.u1User ? 'U' : 'S',
2922	Pte.n.u1Accessed ? 'A' : '-',
2923	Pte.n.u1Dirty ? 'D' : '-',
2924	Pte.n.u1Global ? 'G' : '-',
2925	Pte.n.u1WriteThru ? "WT" : "--",
2926	Pte.n.u1CacheDisable? "CD" : "--",
2927	Pte.n.u1PAT ? "AT" : "--",
2928	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2929	Pte.u & BIT(10) ? '1' : '0',
2930	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2931	Pte.u & X86_PDE_PG_MASK));
2932
2933	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
2934	{
2935	uint64_t fPageShw = 0;
2936	RTHCPHYS pPhysHC = 0;
2937
2938	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
2939	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
2940	}
2941	}
2942	}
2943	return VINF_SUCCESS;
2944	}
2945
2946
2947	/**
2948	* Dumps a 32-bit guest page directory and page tables.
2949	*
2950	* @returns VBox status code (VINF_SUCCESS).
2951	* @param pVM The VM handle.
2952	* @param cr3 The root of the hierarchy.
2953	* @param cr4 The CR4, PSE is currently used.
2954	* @param PhysSearch Address to search for.
2955	*/
2956	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCPHYS PhysSearch)
2957	{
2958	bool fLongMode = false;
2959	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
2960	PX86PD pPD = 0;
2961
2962	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
2963	if (VBOX_FAILURE(rc) \|\| !pPD)
2964	{
2965	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
2966	return VERR_INVALID_PARAMETER;
2967	}
2968
2969	Log(("cr3=%08x cr4=%08x%s\n"
2970	"%-*s P - Present\n"
2971	"%-*s \| R/W - Read (0) / Write (1)\n"
2972	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
2973	"%-*s \| \| \| A - Accessed\n"
2974	"%-*s \| \| \| \| D - Dirty\n"
2975	"%-*s \| \| \| \| \| G - Global\n"
2976	"%-*s \| \| \| \| \| \| WT - Write thru\n"
2977	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
2978	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
2979	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
2980	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
2981	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
2982	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
2983	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
2984	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
2985	- W U - - - -- -- -- -- -- 010 */
2986	, cr3, cr4, fLongMode ? " Long Mode" : "",
2987	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
2988	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
2989
2990	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2991	{
2992	X86PDE Pde = pPD->a[i];
2993	if (Pde.n.u1Present)
2994	{
2995	const uint32_t u32Address = i << X86_PD_SHIFT;
2996
2997	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2998	Log(( /P R S A D G WT CD AT NX 4M a m d /
2999	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3000	u32Address,
3001	Pde.b.u1Write ? 'W' : 'R',
3002	Pde.b.u1User ? 'U' : 'S',
3003	Pde.b.u1Accessed ? 'A' : '-',
3004	Pde.b.u1Dirty ? 'D' : '-',
3005	Pde.b.u1Global ? 'G' : '-',
3006	Pde.b.u1WriteThru ? "WT" : "--",
3007	Pde.b.u1CacheDisable? "CD" : "--",
3008	Pde.b.u1PAT ? "AT" : "--",
3009	Pde.u & BIT(9) ? '1' : '0',
3010	Pde.u & BIT(10) ? '1' : '0',
3011	Pde.u & BIT(11) ? '1' : '0',
3012	Pde.u & X86_PDE4M_PG_MASK));
3013	/** @todo PhysSearch */
3014	else
3015	{
3016	Log(( /P R S A D G WT CD AT NX 4M a m d /
3017	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3018	u32Address,
3019	Pde.n.u1Write ? 'W' : 'R',
3020	Pde.n.u1User ? 'U' : 'S',
3021	Pde.n.u1Accessed ? 'A' : '-',
3022	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3023	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3024	Pde.n.u1WriteThru ? "WT" : "--",
3025	Pde.n.u1CacheDisable? "CD" : "--",
3026	Pde.u & BIT(9) ? '1' : '0',
3027	Pde.u & BIT(10) ? '1' : '0',
3028	Pde.u & BIT(11) ? '1' : '0',
3029	Pde.u & X86_PDE_PG_MASK));
3030	////if (cMaxDepth >= 1)
3031	{
3032	/** @todo what about using the page pool for mapping PTs? */
3033	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3034	PX86PT pPT = NULL;
3035
3036	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3037
3038	int rc2 = VERR_INVALID_PARAMETER;
3039	if (pPT)
3040	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3041	else
3042	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3043	if (rc2 < rc && VBOX_SUCCESS(rc))
3044	rc = rc2;
3045	}
3046	}
3047	}
3048	}
3049
3050	return rc;
3051	}
3052
3053
3054	/**
3055	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3056	*
3057	* @returns VBox status code (VINF_SUCCESS).
3058	* @param pVM The VM handle.
3059	* @param cr3 The root of the hierarchy.
3060	* @param cr4 The cr4, only PAE and PSE is currently used.
3061	* @param fLongMode Set if long mode, false if not long mode.
3062	* @param cMaxDepth Number of levels to dump.
3063	* @param pHlp Pointer to the output functions.
3064	*/
3065	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3066	{
3067	if (!pHlp)
3068	pHlp = DBGFR3InfoLogHlp();
3069	if (!cMaxDepth)
3070	return VINF_SUCCESS;
3071	const unsigned cch = fLongMode ? 16 : 8;
3072	pHlp->pfnPrintf(pHlp,
3073	"cr3=%08x cr4=%08x%s\n"
3074	"%-*s P - Present\n"
3075	"%-*s \| R/W - Read (0) / Write (1)\n"
3076	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3077	"%-*s \| \| \| A - Accessed\n"
3078	"%-*s \| \| \| \| D - Dirty\n"
3079	"%-*s \| \| \| \| \| G - Global\n"
3080	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3081	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3082	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3083	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3084	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3085	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3086	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3087	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3088	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3089	- W U - - - -- -- -- -- -- 010 */
3090	, cr3, cr4, fLongMode ? " Long Mode" : "",
3091	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3092	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3093	if (cr4 & X86_CR4_PAE)
3094	{
3095	if (fLongMode)
3096	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3097	return pgmR3DumpHierarchyHCPaePDPTR(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3098	}
3099	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3100	}
3101
3102
3103
3104	#ifdef VBOX_WITH_DEBUGGER
3105	/**
3106	* The '.pgmram' command.
3107	*
3108	* @returns VBox status.
3109	* @param pCmd Pointer to the command descriptor (as registered).
3110	* @param pCmdHlp Pointer to command helper functions.
3111	* @param pVM Pointer to the current VM (if any).
3112	* @param paArgs Pointer to (readonly) array of arguments.
3113	* @param cArgs Number of arguments in the array.
3114	*/
3115	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3116	{
3117	/*
3118	* Validate input.
3119	*/
3120	if (!pVM)
3121	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3122	if (!pVM->pgm.s.pRamRangesGC)
3123	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3124
3125	/*
3126	* Dump the ranges.
3127	*/
3128	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3129	PPGMRAMRANGE pRam;
3130	for (pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
3131	{
3132	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3133	"%VGp - %VGp %p\n",
3134	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3135	if (VBOX_FAILURE(rc))
3136	return rc;
3137	}
3138
3139	return VINF_SUCCESS;
3140	}
3141
3142
3143	/**
3144	* The '.pgmmap' command.
3145	*
3146	* @returns VBox status.
3147	* @param pCmd Pointer to the command descriptor (as registered).
3148	* @param pCmdHlp Pointer to command helper functions.
3149	* @param pVM Pointer to the current VM (if any).
3150	* @param paArgs Pointer to (readonly) array of arguments.
3151	* @param cArgs Number of arguments in the array.
3152	*/
3153	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3154	{
3155	/*
3156	* Validate input.
3157	*/
3158	if (!pVM)
3159	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3160	if (!pVM->pgm.s.pMappingsR3)
3161	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3162
3163	/*
3164	* Print message about the fixedness of the mappings.
3165	*/
3166	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3167	if (VBOX_FAILURE(rc))
3168	return rc;
3169
3170	/*
3171	* Dump the ranges.
3172	*/
3173	PPGMMAPPING pCur;
3174	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
3175	{
3176	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3177	"%08x - %08x %s\n",
3178	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3179	if (VBOX_FAILURE(rc))
3180	return rc;
3181	}
3182
3183	return VINF_SUCCESS;
3184	}
3185
3186
3187	/**
3188	* The '.pgmsync' command.
3189	*
3190	* @returns VBox status.
3191	* @param pCmd Pointer to the command descriptor (as registered).
3192	* @param pCmdHlp Pointer to command helper functions.
3193	* @param pVM Pointer to the current VM (if any).
3194	* @param paArgs Pointer to (readonly) array of arguments.
3195	* @param cArgs Number of arguments in the array.
3196	*/
3197	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3198	{
3199	/*
3200	* Validate input.
3201	*/
3202	if (!pVM)
3203	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3204
3205	/*
3206	* Force page directory sync.
3207	*/
3208	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3209
3210	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3211	if (VBOX_FAILURE(rc))
3212	return rc;
3213
3214	return VINF_SUCCESS;
3215	}
3216
3217
3218	/**
3219	* The '.pgmsyncalways' command.
3220	*
3221	* @returns VBox status.
3222	* @param pCmd Pointer to the command descriptor (as registered).
3223	* @param pCmdHlp Pointer to command helper functions.
3224	* @param pVM Pointer to the current VM (if any).
3225	* @param paArgs Pointer to (readonly) array of arguments.
3226	* @param cArgs Number of arguments in the array.
3227	*/
3228	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3229	{
3230	/*
3231	* Validate input.
3232	*/
3233	if (!pVM)
3234	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3235
3236	/*
3237	* Force page directory sync.
3238	*/
3239	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3240	{
3241	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3242	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3243	}
3244	else
3245	{
3246	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3247	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3248	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3249	}
3250	}
3251
3252	#endif
3253
3254	/**
3255	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3256	*/
3257	typedef struct PGMCHECKINTARGS
3258	{
3259	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3260	PPGMPHYSHANDLER pPrevPhys;
3261	PPGMVIRTHANDLER pPrevVirt;
3262	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3263	PVM pVM;
3264	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3265
3266	/**
3267	* Validate a node in the physical handler tree.
3268	*
3269	* @returns 0 on if ok, other wise 1.
3270	* @param pNode The handler node.
3271	* @param pvUser pVM.
3272	*/
3273	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3274	{
3275	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3276	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3277	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3278	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3279	AssertReleaseMsg( !pArgs->pPrevPhys
3280	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3281	("pPrevPhys=%p %VGp-%VGp %s\n"
3282	" pCur=%p %VGp-%VGp %s\n",
3283	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3284	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3285	pArgs->pPrevPhys = pCur;
3286	return 0;
3287	}
3288
3289
3290	/**
3291	* Validate a node in the virtual handler tree.
3292	*
3293	* @returns 0 on if ok, other wise 1.
3294	* @param pNode The handler node.
3295	* @param pvUser pVM.
3296	*/
3297	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
3298	{
3299	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3300	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
3301	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3302	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3303	AssertReleaseMsg( !pArgs->pPrevVirt
3304	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
3305	("pPrevVirt=%p %VGv-%VGv %s\n"
3306	" pCur=%p %VGv-%VGv %s\n",
3307	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
3308	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3309	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
3310	{
3311	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
3312	("pCur=%p %VGv-%VGv %s\n"
3313	"iPage=%d offVirtHandle=%#x expected %#x\n",
3314	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
3315	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
3316	}
3317	pArgs->pPrevVirt = pCur;
3318	return 0;
3319	}
3320
3321
3322	/**
3323	* Validate a node in the virtual handler tree.
3324	*
3325	* @returns 0 on if ok, other wise 1.
3326	* @param pNode The handler node.
3327	* @param pvUser pVM.
3328	*/
3329	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3330	{
3331	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3332	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
3333	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
3334	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
3335	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
3336	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3337	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3338	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3339	" pCur=%p %VGp-%VGp\n",
3340	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3341	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3342	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3343	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3344	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3345	" pCur=%p %VGp-%VGp\n",
3346	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3347	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3348	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
3349	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3350	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3351	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3352	{
3353	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
3354	for (;;)
3355	{
3356	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3357	AssertReleaseMsg(pCur2 != pCur,
3358	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3359	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3360	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
3361	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3362	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3363	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3364	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3365	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
3366	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3367	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3368	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3369	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3370	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
3371	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3372	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3373	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3374	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3375	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3376	break;
3377	}
3378	}
3379
3380	pArgs->pPrevPhys2Virt = pCur;
3381	return 0;
3382	}
3383
3384
3385	/**
3386	* Perform an integrity check on the PGM component.
3387	*
3388	* @returns VINF_SUCCESS if everything is fine.
3389	* @returns VBox error status after asserting on integrity breach.
3390	* @param pVM The VM handle.
3391	*/
3392	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
3393	{
3394	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
3395
3396	/*
3397	* Check the trees.
3398	*/
3399	int cErrors = 0;
3400	PGMCHECKINTARGS Args = { true, NULL, NULL, NULL, pVM };
3401	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3402	Args.fLeftToRight = false;
3403	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3404	Args.fLeftToRight = true;
3405	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3406	Args.fLeftToRight = false;
3407	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3408	Args.fLeftToRight = true;
3409	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3410	Args.fLeftToRight = false;
3411	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3412
3413	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
3414	}
3415
3416
3417	/**
3418	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
3419	*
3420	* @returns VBox status code.
3421	* @param pVM VM handle.
3422	* @param fEnable Enable or disable shadow mappings
3423	*/
3424	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
3425	{
3426	pVM->pgm.s.fDisableMappings = !fEnable;
3427
3428	size_t cb;
3429	int rc = PGMR3MappingsSize(pVM, &cb);
3430	AssertRCReturn(rc, rc);
3431
3432	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
3433	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
3434	AssertRCReturn(rc, rc);
3435
3436	return VINF_SUCCESS;
3437	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 4403

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