PGM.cpp@ 40

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1	/* $Id: PGM.cpp 40 2007-01-15 17:44:46Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pg_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pg_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPTR and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pg_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pg_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pg_misc Misc
97	*
98	* @subsection subsec_pg_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*/
111
112
113
114	/** Saved state data unit version. */
115	#define PGM_SAVED_STATE_VERSION 5
116
117	/*******************************************************************************
118	* Header Files *
119	*******************************************************************************/
120	#define LOG_GROUP LOG_GROUP_PGM
121	#include <VBox/dbgf.h>
122	#include <VBox/pgm.h>
123	#include <VBox/cpum.h>
124	#include <VBox/iom.h>
125	#include <VBox/sup.h>
126	#include <VBox/mm.h>
127	#include <VBox/pdm.h>
128	#include <VBox/em.h>
129	#include <VBox/stam.h>
130	#include <VBox/rem.h>
131	#include <VBox/dbgf.h>
132	#include <VBox/rem.h>
133	#include <VBox/selm.h>
134	#include <VBox/ssm.h>
135	#include "PGMInternal.h"
136	#include <VBox/vm.h>
137	#include <VBox/dbg.h>
138	#include <VBox/hwaccm.h>
139
140	#include <VBox/log.h>
141	#include <iprt/assert.h>
142	#include <iprt/alloc.h>
143	#include <iprt/asm.h>
144	#include <iprt/thread.h>
145	#include <iprt/string.h>
146	#include <VBox/param.h>
147	#include <VBox/err.h>
148
149
150
151	/*******************************************************************************
152	* Internal Functions *
153	*******************************************************************************/
154	static int pgmR3InitPaging(PVM pVM);
155	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
156	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
157	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
158	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
159	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
160	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
161	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
162	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
163	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
164	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
165
166	#ifdef VBOX_WITH_STATISTICS
167	static void pgmR3InitStats(PVM pVM);
168	#endif
169
170	#ifdef VBOX_WITH_DEBUGGER
171	/** @todo all but the two last commands must be converted to 'info'. */
172	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
173	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
174	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
175	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
176	#endif
177
178
179	/*******************************************************************************
180	* Global Variables *
181	*******************************************************************************/
182	#ifdef VBOX_WITH_DEBUGGER
183	/** Command descriptors. */
184	static const DBGCCMD g_aCmds[] =
185	{
186	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
187	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
188	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
189	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
190	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
191	};
192	#endif
193
194
195
196
197	#ifndef __AMD64__
198	/*
199	* Shadow - 32-bit mode
200	*/
201	#define PGM_SHW_TYPE PGM_TYPE_32BIT
202	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
203	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
204	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
205	#include "PGMShw.h"
206
207	/* Guest - real mode */
208	#define PGM_GST_TYPE PGM_TYPE_REAL
209	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
210	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
211	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
212	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
213	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
214	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
215	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
216	#include "PGMGst.h"
217	#include "PGMBth.h"
218	#undef BTH_PGMPOOLKIND_PT_FOR_PT
219	#undef PGM_BTH_NAME
220	#undef PGM_BTH_NAME_GC_STR
221	#undef PGM_BTH_NAME_R0_STR
222	#undef PGM_GST_TYPE
223	#undef PGM_GST_NAME
224	#undef PGM_GST_NAME_GC_STR
225	#undef PGM_GST_NAME_R0_STR
226
227	/* Guest - protected mode */
228	#define PGM_GST_TYPE PGM_TYPE_PROT
229	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
230	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
231	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
232	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
233	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
234	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
235	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
236	#include "PGMGst.h"
237	#include "PGMBth.h"
238	#undef BTH_PGMPOOLKIND_PT_FOR_PT
239	#undef PGM_BTH_NAME
240	#undef PGM_BTH_NAME_GC_STR
241	#undef PGM_BTH_NAME_R0_STR
242	#undef PGM_GST_TYPE
243	#undef PGM_GST_NAME
244	#undef PGM_GST_NAME_GC_STR
245	#undef PGM_GST_NAME_R0_STR
246
247	/* Guest - 32-bit mode */
248	#define PGM_GST_TYPE PGM_TYPE_32BIT
249	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
250	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
251	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
252	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
253	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
254	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
255	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
256	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
257	#include "PGMGst.h"
258	#include "PGMBth.h"
259	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
260	#undef BTH_PGMPOOLKIND_PT_FOR_PT
261	#undef PGM_BTH_NAME
262	#undef PGM_BTH_NAME_GC_STR
263	#undef PGM_BTH_NAME_R0_STR
264	#undef PGM_GST_TYPE
265	#undef PGM_GST_NAME
266	#undef PGM_GST_NAME_GC_STR
267	#undef PGM_GST_NAME_R0_STR
268
269	#undef PGM_SHW_TYPE
270	#undef PGM_SHW_NAME
271	#undef PGM_SHW_NAME_GC_STR
272	#undef PGM_SHW_NAME_R0_STR
273	#endif /* !__AMD64__ */
274
275
276	/*
277	* Shadow - PAE mode
278	*/
279	#define PGM_SHW_TYPE PGM_TYPE_PAE
280	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
281	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
282	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
283	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
284	#include "PGMShw.h"
285
286	/* Guest - real mode */
287	#define PGM_GST_TYPE PGM_TYPE_REAL
288	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
289	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
290	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
291	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
292	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
293	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
294	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
295	#include "PGMBth.h"
296	#undef BTH_PGMPOOLKIND_PT_FOR_PT
297	#undef PGM_BTH_NAME
298	#undef PGM_BTH_NAME_GC_STR
299	#undef PGM_BTH_NAME_R0_STR
300	#undef PGM_GST_TYPE
301	#undef PGM_GST_NAME
302	#undef PGM_GST_NAME_GC_STR
303	#undef PGM_GST_NAME_R0_STR
304
305	/* Guest - protected mode */
306	#define PGM_GST_TYPE PGM_TYPE_PROT
307	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
308	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
309	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
310	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
311	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
312	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
313	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
314	#include "PGMBth.h"
315	#undef BTH_PGMPOOLKIND_PT_FOR_PT
316	#undef PGM_BTH_NAME
317	#undef PGM_BTH_NAME_GC_STR
318	#undef PGM_BTH_NAME_R0_STR
319	#undef PGM_GST_TYPE
320	#undef PGM_GST_NAME
321	#undef PGM_GST_NAME_GC_STR
322	#undef PGM_GST_NAME_R0_STR
323
324	/* Guest - 32-bit mode */
325	#define PGM_GST_TYPE PGM_TYPE_32BIT
326	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
327	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
328	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
329	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
330	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
331	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
332	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
333	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
334	#include "PGMBth.h"
335	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
336	#undef BTH_PGMPOOLKIND_PT_FOR_PT
337	#undef PGM_BTH_NAME
338	#undef PGM_BTH_NAME_GC_STR
339	#undef PGM_BTH_NAME_R0_STR
340	#undef PGM_GST_TYPE
341	#undef PGM_GST_NAME
342	#undef PGM_GST_NAME_GC_STR
343	#undef PGM_GST_NAME_R0_STR
344
345	/* Guest - PAE mode */
346	#define PGM_GST_TYPE PGM_TYPE_PAE
347	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
348	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
349	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
350	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
351	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
352	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
353	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
354	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
355	#include "PGMGst.h"
356	#include "PGMBth.h"
357	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
358	#undef BTH_PGMPOOLKIND_PT_FOR_PT
359	#undef PGM_BTH_NAME
360	#undef PGM_BTH_NAME_GC_STR
361	#undef PGM_BTH_NAME_R0_STR
362	#undef PGM_GST_TYPE
363	#undef PGM_GST_NAME
364	#undef PGM_GST_NAME_GC_STR
365	#undef PGM_GST_NAME_R0_STR
366
367	#undef PGM_SHW_TYPE
368	#undef PGM_SHW_NAME
369	#undef PGM_SHW_NAME_GC_STR
370	#undef PGM_SHW_NAME_R0_STR
371
372
373	/*
374	* Shadow - AMD64 mode
375	*/
376	#define PGM_SHW_TYPE PGM_TYPE_AMD64
377	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
378	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
379	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
380	#include "PGMShw.h"
381
382	/* Guest - real mode */
383	#define PGM_GST_TYPE PGM_TYPE_REAL
384	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
385	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
386	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
387	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
388	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_REAL_STR(name)
389	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_REAL_STR(name)
390	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
391	#include "PGMBth.h"
392	#undef BTH_PGMPOOLKIND_PT_FOR_PT
393	#undef PGM_BTH_NAME
394	#undef PGM_BTH_NAME_GC_STR
395	#undef PGM_BTH_NAME_R0_STR
396	#undef PGM_GST_TYPE
397	#undef PGM_GST_NAME
398	#undef PGM_GST_NAME_GC_STR
399	#undef PGM_GST_NAME_R0_STR
400
401	/* Guest - protected mode */
402	#define PGM_GST_TYPE PGM_TYPE_PROT
403	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
404	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
405	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
406	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
407	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_PROT_STR(name)
408	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_PROT_STR(name)
409	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
410	#include "PGMBth.h"
411	#undef BTH_PGMPOOLKIND_PT_FOR_PT
412	#undef PGM_BTH_NAME
413	#undef PGM_BTH_NAME_GC_STR
414	#undef PGM_BTH_NAME_R0_STR
415	#undef PGM_GST_TYPE
416	#undef PGM_GST_NAME
417	#undef PGM_GST_NAME_GC_STR
418	#undef PGM_GST_NAME_R0_STR
419
420	/* Guest - AMD64 mode */
421	#define PGM_GST_TYPE PGM_TYPE_AMD64
422	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
423	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
424	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
425	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
426	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
427	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
428	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
429	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
430	#include "PGMGst.h"
431	#include "PGMBth.h"
432	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
433	#undef BTH_PGMPOOLKIND_PT_FOR_PT
434	#undef PGM_BTH_NAME
435	#undef PGM_BTH_NAME_GC_STR
436	#undef PGM_BTH_NAME_R0_STR
437	#undef PGM_GST_TYPE
438	#undef PGM_GST_NAME
439	#undef PGM_GST_NAME_GC_STR
440	#undef PGM_GST_NAME_R0_STR
441
442	#undef PGM_SHW_TYPE
443	#undef PGM_SHW_NAME
444	#undef PGM_SHW_NAME_GC_STR
445	#undef PGM_SHW_NAME_R0_STR
446
447
448
449
450	/**
451	* Initiates the paging of VM.
452	*
453	* @returns VBox status code.
454	* @param pVM Pointer to VM structure.
455	*/
456	PGMR3DECL(int) PGMR3Init(PVM pVM)
457	{
458	LogFlow(("PGMR3Init:\n"));
459
460	/*
461	* Assert alignment and sizes.
462	*/
463	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
464
465	/*
466	* Init the structure.
467	*/
468	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
469	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
470	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
471	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
472	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
473	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
474	pVM->pgm.s.fA20Enabled = true;
475	pVM->pgm.s.pGstPaePDPTRHC = NULL;
476	pVM->pgm.s.pGstPaePDPTRGC = 0;
477	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
478	{
479	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
480	pVM->pgm.s.apGstPaePDsGC[i] = 0;
481	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
482	}
483
484	/*
485	* Get the configured RAM size - to estimate saved state size.
486	*/
487	uint64_t cbRam;
488	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
489	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
490	cbRam = pVM->pgm.s.cbRamSize = 0;
491	else if (VBOX_SUCCESS(rc))
492	{
493	if (cbRam < PAGE_SIZE)
494	cbRam = 0;
495	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
496	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
497	}
498	else
499	{
500	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
501	return rc;
502	}
503
504	/*
505	* Register saved state data unit.
506	*/
507	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
508	NULL, pgmR3Save, NULL,
509	NULL, pgmR3Load, NULL);
510	if (VBOX_FAILURE(rc))
511	return rc;
512
513	/* Initialise PGM critical section. */
514	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
515	AssertRCReturn(rc, rc);
516
517	/*
518	* Trees
519	*/
520	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
521	if (VBOX_SUCCESS(rc))
522	{
523	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
524
525	/*
526	* Init the paging.
527	*/
528	rc = pgmR3InitPaging(pVM);
529	}
530	if (VBOX_SUCCESS(rc))
531	{
532	/*
533	* Init the page pool.
534	*/
535	rc = pgmR3PoolInit(pVM);
536	}
537	if (VBOX_SUCCESS(rc))
538	{
539	/*
540	* Info & statistics
541	*/
542	DBGFR3InfoRegisterInternal(pVM, "mode",
543	"Shows the current paging mode. "
544	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
545	pgmR3InfoMode);
546	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
547	"Dumps all the entries in the top level paging table. No arguments.",
548	pgmR3InfoCr3);
549	DBGFR3InfoRegisterInternal(pVM, "phys",
550	"Dumps all the physical address ranges. No arguments.",
551	pgmR3PhysInfo);
552	DBGFR3InfoRegisterInternal(pVM, "handlers",
553	"Dumps physical and virtual handlers. "
554	"Pass 'phys' or 'virt' as argument if only one kind is wanted.",
555	pgmR3InfoHandlers);
556
557	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
558	#ifdef VBOX_WITH_STATISTICS
559	pgmR3InitStats(pVM);
560	#endif
561	#ifdef VBOX_WITH_DEBUGGER
562	/*
563	* Debugger commands.
564	*/
565	static bool fRegisteredCmds = false;
566	if (!fRegisteredCmds)
567	{
568	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
569	if (VBOX_SUCCESS(rc))
570	fRegisteredCmds = true;
571	}
572	#endif
573	return VINF_SUCCESS;
574	}
575	/* No cleanup necessary, MM frees all memory. */
576
577	return rc;
578	}
579
580
581	/**
582	* Init paging.
583	*
584	* Since we need to check what mode the host is operating in before we can choose
585	* the right paging functions for the host we have to delay this until R0 has
586	* been initialized.
587	*
588	* @returns VBox status code.
589	* @param pVM VM handle.
590	*/
591	static int pgmR3InitPaging(PVM pVM)
592	{
593	/*
594	* Force a recalculation of modes and switcher so everyone gets notified.
595	*/
596	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
597	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
598	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
599
600	/*
601	* Allocate static mapping space for whatever the cr3 register
602	* points to and in the case of PAE mode to the 4 PDs.
603	*/
604	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
605	if (VBOX_FAILURE(rc))
606	{
607	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
608	return rc;
609	}
610	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
611
612	/*
613	* Allocate pages for the three possible intermediate contexts
614	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
615	* for the sake of simplicity. The AMD64 uses the PAE for the
616	* lower levels, making the total number of pages 11 (3 + 7 + 1).
617	*
618	* We assume that two page tables will be enought for the core code
619	* mappings (HC virtual and identity).
620	*/
621	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
622	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
623	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
624	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
625	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
626	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
627	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
628	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
629	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
630	pVM->pgm.s.pInterPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
631	#if 1
632	pVM->pgm.s.pInterPaePDPTR64 = (PX86PDPTR)MMR3PageAllocLow(pVM);
633	#endif
634	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
635	if ( !pVM->pgm.s.pInterPD
636	\|\| !pVM->pgm.s.apInterPTs[0]
637	\|\| !pVM->pgm.s.apInterPTs[1]
638	\|\| !pVM->pgm.s.apInterPaePTs[0]
639	\|\| !pVM->pgm.s.apInterPaePTs[1]
640	\|\| !pVM->pgm.s.apInterPaePDs[0]
641	\|\| !pVM->pgm.s.apInterPaePDs[1]
642	\|\| !pVM->pgm.s.apInterPaePDs[2]
643	\|\| !pVM->pgm.s.apInterPaePDs[3]
644	\|\| !pVM->pgm.s.pInterPaePDPTR
645	#if 1
646	\|\| !pVM->pgm.s.pInterPaePDPTR64
647	#endif
648	\|\| !pVM->pgm.s.pInterPaePML4)
649	{
650	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
651	return VERR_NO_PAGE_MEMORY;
652	}
653
654	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
655	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
656	pVM->pgm.s.HCPhysInterPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR);
657	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPTR != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPTR & PAGE_OFFSET_MASK));
658	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
659	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
660
661	#if 1 /* let's see if this is the cause of the problems... */
662	/*
663	* Initialize the pages, setting up the PML4 and PDPTR for repetitive 4GB action.
664	*/
665	ASMMemZeroPage(pVM->pgm.s.pInterPD);
666	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
667	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
668
669	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
670	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
671
672	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPTR);
673	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
674	{
675	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
676	pVM->pgm.s.pInterPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
677	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
678	}
679
680	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPTR64->a); i++)
681	{
682	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
683	pVM->pgm.s.pInterPaePDPTR64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
684	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
685	}
686
687	RTHCPHYS HCPhysInterPaePDPTR64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64);
688	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
689	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
690	\| HCPhysInterPaePDPTR64;
691	#else
692	/*
693	* Initialize the pages, setting up the PML4 and PDPTR for action below 4GB.
694	*/
695	ASMMemZero32(pVM->pgm.s.pInterPD, PAGE_SIZE);
696	ASMMemZero32(pVM->pgm.s.apInterPTs[0], PAGE_SIZE);
697	ASMMemZero32(pVM->pgm.s.apInterPTs[1], PAGE_SIZE);
698
699	ASMMemZero32(pVM->pgm.s.apInterPaePTs[0], PAGE_SIZE);
700	ASMMemZero32(pVM->pgm.s.apInterPaePTs[1], PAGE_SIZE);
701
702	ASMMemZero32(pVM->pgm.s.pInterPaePDPTR, PAGE_SIZE);
703	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
704	{
705	ASMMemZero32(pVM->pgm.s.apInterPaePDs[i], PAGE_SIZE);
706	pVM->pgm.s.pInterPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
707	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
708	}
709
710	ASMMemZero32(pVM->pgm.s.pInterPaePML4, PAGE_SIZE);
711	pVM->pgm.s.pInterPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A
712	\| pVM->pgm.s.HCPhysInterPaePDPTR;
713	#endif
714
715
716	/*
717	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
718	* We allocate pages for all three posibilities to in order to simplify mappings and
719	* avoid resource failure during mode switches. So, we need to cover all levels of the
720	* of the first 4GB down to PD level.
721	* As with the intermediate context, AMD64 uses the PAE PDPTR and PDs.
722	*/
723	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
724	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
725	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
726	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
727	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
728	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
729	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
730	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
731	pVM->pgm.s.pHCPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
732	pVM->pgm.s.pHCPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
733	if ( !pVM->pgm.s.pHC32BitPD
734	\|\| !pVM->pgm.s.apHCPaePDs[0]
735	\|\| !pVM->pgm.s.apHCPaePDs[1]
736	\|\| !pVM->pgm.s.apHCPaePDs[2]
737	\|\| !pVM->pgm.s.apHCPaePDs[3]
738	\|\| !pVM->pgm.s.pHCPaePDPTR
739	\|\| !pVM->pgm.s.pHCPaePML4)
740	{
741	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
742	return VERR_NO_PAGE_MEMORY;
743	}
744
745	/* get physical addresses. */
746	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
747	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
748	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
749	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
750	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
751	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
752	pVM->pgm.s.HCPhysPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPTR);
753	pVM->pgm.s.HCPhysPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePML4);
754
755	/*
756	* Initialize the pages, setting up the PML4 and PDPTR for action below 4GB.
757	*/
758	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
759
760	ASMMemZero32(pVM->pgm.s.pHCPaePDPTR, PAGE_SIZE);
761	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
762	{
763	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
764	pVM->pgm.s.pHCPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
765	/* The flags will be corrected when entering and leaving long mode. */
766	}
767
768	ASMMemZero32(pVM->pgm.s.pHCPaePML4, PAGE_SIZE);
769	pVM->pgm.s.pHCPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_A
770	\| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.HCPhysPaePDPTR;
771
772	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
773
774	/*
775	* Initialize paging workers and mode from current host mode
776	* and the guest running in real mode.
777	*/
778	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
779	switch (pVM->pgm.s.enmHostMode)
780	{
781	case SUPPAGINGMODE_32_BIT:
782	case SUPPAGINGMODE_32_BIT_GLOBAL:
783	case SUPPAGINGMODE_PAE:
784	case SUPPAGINGMODE_PAE_GLOBAL:
785	case SUPPAGINGMODE_PAE_NX:
786	case SUPPAGINGMODE_PAE_GLOBAL_NX:
787	break;
788
789	case SUPPAGINGMODE_AMD64:
790	case SUPPAGINGMODE_AMD64_GLOBAL:
791	case SUPPAGINGMODE_AMD64_NX:
792	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
793	if (ARCH_BITS != 64)
794	{
795	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
796	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
797	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
798	}
799	break;
800	default:
801	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
802	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
803	}
804	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
805	if (VBOX_SUCCESS(rc))
806	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
807	if (VBOX_SUCCESS(rc))
808	{
809	LogFlow(("pgmR3InitPaging: returns successfully\n"));
810	return VINF_SUCCESS;
811	}
812
813	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
814	return rc;
815	}
816
817
818	#ifdef VBOX_WITH_STATISTICS
819	/**
820	* Init statistics
821	*/
822	static void pgmR3InitStats(PVM pVM)
823	{
824	PPGM pPGM = &pVM->pgm.s;
825	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
826	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
827	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
828	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
829	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
830	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
831	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
832	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
833	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
834	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
835	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
836	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
837	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
838	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
839	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
840	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
841	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
842	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
843	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
844	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
845	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
846	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
847
848	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
849	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
850	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
851	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
852	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
853	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
854	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
855	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
856	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
857	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
858	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
859	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
860	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
861	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
862	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
863	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
864	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
865	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
866	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
867
868	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
869	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
870	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
871	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
872	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
873	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
874	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
875
876	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
877	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
878	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
879	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
880	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
881	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
882
883	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
884	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
885	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
886	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
887	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
888	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
889
890
891	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
892	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
893	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
894
895	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
896	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
897
898	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
899	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
900
901	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
902	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
903
904	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
905	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
906	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
907
908	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
909	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
910	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
911	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
912	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
913	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
914	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
915	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
916	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
917	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
918	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
919
920	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
921	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
922	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
923	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
924	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
925	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
926	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
927
928	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
929	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
930	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
931	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
932
933	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
934	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
935	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
936	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
937	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
938
939	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
940	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
941	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
942	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
943	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
944	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
945	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
946	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
947	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
948	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
949	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
950	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
951
952	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
953	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
954	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
955	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
956	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
957	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
958	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
959	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
960	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
961	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
962	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
963	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
964
965	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
966	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
967	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
968
969	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
970	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
971
972	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
973	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
974	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
975	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
976
977	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
978	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
979
980	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
981	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
982	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
983	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
984	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
985	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
986	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
987	#endif
988
989	for (unsigned i = 0; i < PAGE_ENTRIES; i++)
990	{
991	/** @todo r=bird: We need a STAMR3RegisterF()! */
992	char szName[32];
993
994	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
995	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
996	AssertRC(rc);
997
998	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
999	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1000	AssertRC(rc);
1001
1002	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1003	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1004	AssertRC(rc);
1005	}
1006	}
1007	#endif /* VBOX_WITH_STATISTICS */
1008
1009	/**
1010	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1011	*
1012	* The dynamic mapping area will also be allocated and initialized at this
1013	* time. We could allocate it during PGMR3Init of course, but the mapping
1014	* wouldn't be allocated at that time preventing us from setting up the
1015	* page table entries with the dummy page.
1016	*
1017	* @returns VBox status code.
1018	* @param pVM VM handle.
1019	*/
1020	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1021	{
1022	/*
1023	* Reserve space for mapping the paging pages into guest context.
1024	*/
1025	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &pVM->pgm.s.pGC32BitPD);
1026	AssertRCReturn(rc, rc);
1027	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1028
1029	/*
1030	* Reserve space for the dynamic mappings.
1031	*/
1032	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1033	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &pVM->pgm.s.pbDynPageMapBaseGC);
1034	if ( VBOX_SUCCESS(rc)
1035	&& (pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT))
1036	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &pVM->pgm.s.pbDynPageMapBaseGC);
1037	if (VBOX_SUCCESS(rc))
1038	{
1039	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT));
1040	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1041	}
1042	return rc;
1043	}
1044
1045
1046	/**
1047	* Ring-3 init finalizing.
1048	*
1049	* @returns VBox status code.
1050	* @param pVM The VM handle.
1051	*/
1052	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1053	{
1054	/*
1055	* Map the paging pages into the guest context.
1056	*/
1057	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1058	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1059
1060	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1061	AssertRCReturn(rc, rc);
1062	pVM->pgm.s.pGC32BitPD = GCPtr;
1063	GCPtr += PAGE_SIZE;
1064	GCPtr += PAGE_SIZE; /* reserved page */
1065
1066	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1067	{
1068	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1069	AssertRCReturn(rc, rc);
1070	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1071	GCPtr += PAGE_SIZE;
1072	}
1073	/* A bit of paranoia is justified. */
1074	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1075	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1076	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1077	GCPtr += PAGE_SIZE; /* reserved page */
1078
1079	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPTR, PAGE_SIZE, 0);
1080	AssertRCReturn(rc, rc);
1081	pVM->pgm.s.pGCPaePDPTR = GCPtr;
1082	GCPtr += PAGE_SIZE;
1083	GCPtr += PAGE_SIZE; /* reserved page */
1084
1085	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePML4, PAGE_SIZE, 0);
1086	AssertRCReturn(rc, rc);
1087	pVM->pgm.s.pGCPaePML4 = GCPtr;
1088	GCPtr += PAGE_SIZE;
1089	GCPtr += PAGE_SIZE; /* reserved page */
1090
1091
1092	/*
1093	* Reserve space for the dynamic mappings.
1094	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1095	*/
1096	/* get the pointer to the page table entries. */
1097	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1098	AssertRelease(pMapping);
1099	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1100	const unsigned iPT = off >> X86_PD_SHIFT;
1101	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1102	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTHC->a[0]);
1103	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsHC->a[0]);
1104
1105	/* init cache */
1106	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1107	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1108	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1109
1110	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1111	{
1112	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1113	AssertRCReturn(rc, rc);
1114	}
1115
1116	return rc;
1117	}
1118
1119
1120	/**
1121	* Applies relocations to data and code managed by this
1122	* component. This function will be called at init and
1123	* whenever the VMM need to relocate it self inside the GC.
1124	*
1125	* @param pVM The VM.
1126	* @param offDelta Relocation delta relative to old location.
1127	*/
1128	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1129	{
1130	LogFlow(("PGMR3Relocate\n"));
1131
1132	/*
1133	* Paging stuff.
1134	*/
1135	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1136	/** @todo move this into shadow and guest specific relocation functions. */
1137	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1138	pVM->pgm.s.pGC32BitPD += offDelta;
1139	pVM->pgm.s.pGuestPDGC += offDelta;
1140	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1141	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1142	pVM->pgm.s.pGCPaePDPTR += offDelta;
1143	pVM->pgm.s.pGCPaePML4 += offDelta;
1144
1145	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1146	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1147
1148	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1149	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1150	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1151
1152	/*
1153	* Trees.
1154	*/
1155	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1156
1157	/*
1158	* Ram ranges.
1159	*/
1160	if (pVM->pgm.s.pRamRangesHC)
1161	{
1162	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesHC);
1163	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur->pNextHC; pCur = pCur->pNextHC)
1164	{
1165	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1166	if (pCur->pavHCChunkGC)
1167	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1168	}
1169	}
1170
1171	/*
1172	* Update the two page directories with all page table mappings.
1173	* (One or more of them have changed, that's why we're here.)
1174	*/
1175	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsHC);
1176	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsHC; pCur->pNextHC; pCur = pCur->pNextHC)
1177	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1178
1179	/* Relocate GC addresses of Page Tables. */
1180	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsHC; pCur; pCur = pCur->pNextHC)
1181	{
1182	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1183	{
1184	pCur->aPTs[i].pPTGC = MMHyperHC2GC(pVM, pCur->aPTs[i].pPTHC);
1185	pCur->aPTs[i].paPaePTsGC = MMHyperHC2GC(pVM, pCur->aPTs[i].paPaePTsHC);
1186	}
1187	}
1188
1189	/*
1190	* Dynamic page mapping area.
1191	*/
1192	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1193	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1194	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1195
1196	/*
1197	* Physical and virtual handlers.
1198	*/
1199	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1200	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1201
1202	/*
1203	* The page pool.
1204	*/
1205	pgmR3PoolRelocate(pVM);
1206	}
1207
1208
1209	/**
1210	* Callback function for relocating a physical access handler.
1211	*
1212	* @returns 0 (continue enum)
1213	* @param pNode Pointer to a PGMPHYSHANDLER node.
1214	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1215	* not certain the delta will fit in a void pointer for all possible configs.
1216	*/
1217	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1218	{
1219	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1220	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1221	Assert(pHandler->pfnHandlerGC);
1222	pHandler->pfnHandlerGC += offDelta;
1223	if (pHandler->pvUserGC)
1224	pHandler->pvUserGC += offDelta;
1225	return 0;
1226	}
1227
1228	/**
1229	* Callback function for relocating a virtual access handler.
1230	*
1231	* @returns 0 (continue enum)
1232	* @param pNode Pointer to a PGMVIRTHANDLER node.
1233	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1234	* not certain the delta will fit in a void pointer for all possible configs.
1235	*/
1236	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1237	{
1238	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1239	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1240	Assert(pHandler->pfnHandlerGC);
1241	pHandler->pfnHandlerGC += offDelta;
1242	return 0;
1243	}
1244
1245
1246	/**
1247	* The VM is being reset.
1248	*
1249	* For the PGM component this means that any PD write monitors
1250	* needs to be removed.
1251	*
1252	* @param pVM VM handle.
1253	*/
1254	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1255	{
1256	LogFlow(("PGMR3Reset:\n"));
1257	VM_ASSERT_EMT(pVM);
1258
1259	/*
1260	* Unfix any fixed mappings and disable CR3 monitoring.
1261	*/
1262	pVM->pgm.s.fMappingsFixed = false;
1263	pVM->pgm.s.GCPtrMappingFixed = 0;
1264	pVM->pgm.s.cbMappingFixed = 0;
1265
1266	int rc = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
1267	AssertRC(rc);
1268	#ifdef DEBUG
1269	PGMR3DumpMappings(pVM);
1270	#endif
1271
1272	/*
1273	* Reset the shadow page pool.
1274	*/
1275	pgmR3PoolReset(pVM);
1276
1277	/*
1278	* Re-init other members.
1279	*/
1280	pVM->pgm.s.fA20Enabled = true;
1281
1282	/*
1283	* Clear the FFs PGM owns.
1284	*/
1285	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1286	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1287
1288	/*
1289	* Zero memory.
1290	*/
1291	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
1292	{
1293	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1294	while (iPage-- > 0)
1295	{
1296	if (pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2))
1297	{
1298	Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO)));
1299	continue;
1300	}
1301	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1302	{
1303	unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1304	if (pRam->pavHCChunkHC[iChunk])
1305	ASMMemZero32((char *)pRam->pavHCChunkHC[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
1306	}
1307	else
1308	ASMMemZero32((char *)pRam->pvHC + (iPage << PAGE_SHIFT), PAGE_SIZE);
1309	}
1310	}
1311
1312	/*
1313	* Switch mode back to real mode.
1314	*/
1315	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1316	AssertReleaseRC(rc);
1317	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1318	}
1319
1320
1321	/**
1322	* Terminates the PGM.
1323	*
1324	* @returns VBox status code.
1325	* @param pVM Pointer to VM structure.
1326	*/
1327	PGMR3DECL(int) PGMR3Term(PVM pVM)
1328	{
1329	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1330	}
1331
1332
1333	/**
1334	* Execute state save operation.
1335	*
1336	* @returns VBox status code.
1337	* @param pVM VM Handle.
1338	* @param pSSM SSM operation handle.
1339	*/
1340	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1341	{
1342	PPGM pPGM = &pVM->pgm.s;
1343
1344	/*
1345	* Save basic data (required / unaffected by relocation).
1346	*/
1347	#if 1
1348	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1349	#else
1350	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1351	#endif
1352	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1353	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1354	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1355	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1356	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1357	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1358	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1359	SSMR3PutU32(pSSM, ~0); /* Separator. */
1360
1361	/*
1362	* The guest mappings.
1363	*/
1364	uint32_t i = 0;
1365	for (PPGMMAPPING pMapping = pPGM->pMappingsHC; pMapping; pMapping = pMapping->pNextHC, i++)
1366	{
1367	SSMR3PutU32(pSSM, i);
1368	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1369	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1370	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1371	/* flags are done by the mapping owners! */
1372	}
1373	SSMR3PutU32(pSSM, ~0); /* terminator. */
1374
1375	/*
1376	* Ram range flags and bits.
1377	*/
1378	i = 0;
1379	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1380	{
1381	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1382
1383	SSMR3PutU32(pSSM, i);
1384	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1385	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1386	SSMR3PutGCPhys(pSSM, pRam->cb);
1387	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
1388
1389	/* Flags. */
1390	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1391	for (unsigned iPage = 0; iPage < cPages; iPage++)
1392	SSMR3PutU16(pSSM, (uint16_t)(pRam->aHCPhys[iPage] & ~X86_PTE_PAE_PG_MASK));
1393
1394	/* any memory associated with the range. */
1395	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1396	{
1397	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1398	{
1399	if (pRam->pavHCChunkHC[iChunk])
1400	{
1401	SSMR3PutU8(pSSM, 1); /* chunk present */
1402	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1403	}
1404	else
1405	SSMR3PutU8(pSSM, 0); /* no chunk present */
1406	}
1407	}
1408	else if (pRam->pvHC)
1409	{
1410	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
1411	if (VBOX_FAILURE(rc))
1412	{
1413	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1414	return rc;
1415	}
1416	}
1417	}
1418	return SSMR3PutU32(pSSM, ~0); /* terminator. */
1419	}
1420
1421
1422	/**
1423	* Execute state load operation.
1424	*
1425	* @returns VBox status code.
1426	* @param pVM VM Handle.
1427	* @param pSSM SSM operation handle.
1428	* @param u32Version Data layout version.
1429	*/
1430	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1431	{
1432	/*
1433	* Validate version.
1434	*/
1435	if (u32Version != PGM_SAVED_STATE_VERSION)
1436	{
1437	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
1438	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1439	}
1440
1441	/*
1442	* Call the reset function to be on the safe side...
1443	*/
1444	PGMR3Reset(pVM);
1445
1446	/*
1447	* Load basic data (required / unaffected by relocation).
1448	*/
1449	PPGM pPGM = &pVM->pgm.s;
1450	#if 1
1451	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
1452	#else
1453	uint32_t u;
1454	SSMR3GetU32(pSSM, &u);
1455	pPGM->fMappingsFixed = u;
1456	#endif
1457	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
1458	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
1459
1460	RTUINT cbRamSize;
1461	int rc = SSMR3GetU32(pSSM, &cbRamSize);
1462	if (VBOX_FAILURE(rc))
1463	return rc;
1464	if (cbRamSize != pPGM->cbRamSize)
1465	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
1466	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
1467	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
1468	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
1469	RTUINT uGuestMode;
1470	SSMR3GetUInt(pSSM, &uGuestMode);
1471	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
1472
1473	/* check separator. */
1474	uint32_t u32Sep;
1475	SSMR3GetU32(pSSM, &u32Sep);
1476	if (VBOX_FAILURE(rc))
1477	return rc;
1478	if (u32Sep != (uint32_t)~0)
1479	{
1480	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1481	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1482	}
1483
1484	/*
1485	* The guest mappings.
1486	*/
1487	uint32_t i = 0;
1488	for (;; i++)
1489	{
1490	/* Check the seqence number / separator. */
1491	rc = SSMR3GetU32(pSSM, &u32Sep);
1492	if (VBOX_FAILURE(rc))
1493	return rc;
1494	if (u32Sep == ~0U)
1495	break;
1496	if (u32Sep != i)
1497	{
1498	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1499	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1500	}
1501
1502	/* get the mapping details. */
1503	char szDesc[256];
1504	szDesc[0] = '\0';
1505	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
1506	if (VBOX_FAILURE(rc))
1507	return rc;
1508	RTGCPTR GCPtr;
1509	SSMR3GetGCPtr(pSSM, &GCPtr);
1510	RTGCUINTPTR cPTs;
1511	rc = SSMR3GetU32(pSSM, &cPTs);
1512	if (VBOX_FAILURE(rc))
1513	return rc;
1514
1515	/* find matching range. */
1516	PPGMMAPPING pMapping;
1517	for (pMapping = pPGM->pMappingsHC; pMapping; pMapping = pMapping->pNextHC)
1518	if ( pMapping->cPTs == cPTs
1519	&& !strcmp(pMapping->pszDesc, szDesc))
1520	break;
1521	if (!pMapping)
1522	{
1523	AssertMsgFailed(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
1524	cPTs, szDesc, GCPtr));
1525	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1526	}
1527
1528	/* relocate it. */
1529	if (pMapping->GCPtr != GCPtr)
1530	{
1531	AssertMsg((GCPtr >> PGDIR_SHIFT << PGDIR_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
1532	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr >> PGDIR_SHIFT, GCPtr >> PGDIR_SHIFT);
1533	}
1534	else
1535	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
1536	}
1537
1538	/*
1539	* Ram range flags and bits.
1540	*/
1541	i = 0;
1542	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1543	{
1544	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1545	/* Check the seqence number / separator. */
1546	rc = SSMR3GetU32(pSSM, &u32Sep);
1547	if (VBOX_FAILURE(rc))
1548	return rc;
1549	if (u32Sep == ~0U)
1550	break;
1551	if (u32Sep != i)
1552	{
1553	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1554	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1555	}
1556
1557	/* Get the range details. */
1558	RTGCPHYS GCPhys;
1559	SSMR3GetGCPhys(pSSM, &GCPhys);
1560	RTGCPHYS GCPhysLast;
1561	SSMR3GetGCPhys(pSSM, &GCPhysLast);
1562	RTGCPHYS cb;
1563	SSMR3GetGCPhys(pSSM, &cb);
1564	uint8_t fHaveBits;
1565	rc = SSMR3GetU8(pSSM, &fHaveBits);
1566	if (VBOX_FAILURE(rc))
1567	return rc;
1568	if (fHaveBits & ~1)
1569	{
1570	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1571	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1572	}
1573
1574	/* Match it up with the current range. */
1575	if ( GCPhys != pRam->GCPhys
1576	\|\| GCPhysLast != pRam->GCPhysLast
1577	\|\| cb != pRam->cb
1578	\|\| fHaveBits != !!pRam->pvHC)
1579	{
1580	AssertMsgFailed(("Ram range: %VGp-%VGp %VGp bytes %s\n"
1581	"State : %VGp-%VGp %VGp bytes %s\n",
1582	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
1583	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
1584	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1585	}
1586
1587	/* Flags. */
1588	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1589	for (unsigned iPage = 0; iPage < cPages; iPage++)
1590	{
1591	uint16_t u16 = 0;
1592	SSMR3GetU16(pSSM, &u16);
1593	u16 &= PAGE_OFFSET_MASK & ~( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
1594	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL
1595	\| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF );
1596	pRam->aHCPhys[iPage] = (pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK) \| (RTHCPHYS)u16;
1597	}
1598
1599	/* any memory associated with the range. */
1600	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1601	{
1602	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1603	{
1604	uint8_t fValidChunk;
1605
1606	rc = SSMR3GetU8(pSSM, &fValidChunk);
1607	if (VBOX_FAILURE(rc))
1608	return rc;
1609	if (fValidChunk > 1)
1610	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1611
1612	if (fValidChunk)
1613	{
1614	if (!pRam->pavHCChunkHC[iChunk])
1615	{
1616	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
1617	if (VBOX_FAILURE(rc))
1618	return rc;
1619	}
1620
1621	Assert(pRam->pavHCChunkHC[iChunk]);
1622
1623	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1624	}
1625	/* else nothing to do */
1626	}
1627	}
1628	else if (pRam->pvHC)
1629	{
1630	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
1631	if (VBOX_FAILURE(rc))
1632	{
1633	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1634	return rc;
1635	}
1636	}
1637	}
1638
1639	/*
1640	* We require a full resync now.
1641	*/
1642	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1643	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1644	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
1645	pPGM->fPhysCacheFlushPending = true;
1646	pgmR3HandlerPhysicalUpdateAll(pVM);
1647
1648	/*
1649	* Change the paging mode.
1650	*/
1651	return pgmR3ChangeMode(pVM, pPGM->enmGuestMode);
1652	}
1653
1654
1655	/**
1656	* Show paging mode.
1657	*
1658	* @param pVM VM Handle.
1659	* @param pHlp The info helpers.
1660	* @param pszArgs "all" (default), "guest", "shadow" or "host".
1661	*/
1662	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1663	{
1664	/* digest argument. */
1665	bool fGuest, fShadow, fHost;
1666	if (pszArgs)
1667	pszArgs = RTStrStripL(pszArgs);
1668	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
1669	fShadow = fHost = fGuest = true;
1670	else
1671	{
1672	fShadow = fHost = fGuest = false;
1673	if (strstr(pszArgs, "guest"))
1674	fGuest = true;
1675	if (strstr(pszArgs, "shadow"))
1676	fShadow = true;
1677	if (strstr(pszArgs, "host"))
1678	fHost = true;
1679	}
1680
1681	/* print info. */
1682	if (fGuest)
1683	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
1684	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
1685	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
1686	if (fShadow)
1687	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
1688	if (fHost)
1689	{
1690	const char *psz;
1691	switch (pVM->pgm.s.enmHostMode)
1692	{
1693	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
1694	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
1695	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
1696	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
1697	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
1698	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
1699	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
1700	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
1701	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
1702	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
1703	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
1704	default: psz = "unknown"; break;
1705	}
1706	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
1707	}
1708	}
1709
1710
1711	/**
1712	* Dump registered MMIO ranges to the log.
1713	*
1714	* @param pVM VM Handle.
1715	* @param pHlp The info helpers.
1716	* @param pszArgs Arguments, ignored.
1717	*/
1718	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1719	{
1720	NOREF(pszArgs);
1721	pHlp->pfnPrintf(pHlp,
1722	"RAM ranges (pVM=%p)\n"
1723	"%.s %.s\n",
1724	pVM,
1725	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
1726	sizeof(RTHCPTR) * 2, "pvHC ");
1727
1728	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur; pCur = pCur->pNextHC)
1729	pHlp->pfnPrintf(pHlp,
1730	"%VGp-%VGp %VHv\n",
1731	pCur->GCPhys,
1732	pCur->GCPhysLast,
1733	pCur->pvHC);
1734	}
1735
1736	/**
1737	* Dump the page directory to the log.
1738	*
1739	* @param pVM VM Handle.
1740	* @param pHlp The info helpers.
1741	* @param pszArgs Arguments, ignored.
1742	*/
1743	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1744	{
1745	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
1746	/* Big pages supported? */
1747	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1748	/* Global pages supported? */
1749	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
1750
1751	NOREF(pszArgs);
1752
1753	/*
1754	* Get page directory addresses.
1755	*/
1756	PVBOXPD pPDSrc = pVM->pgm.s.pGuestPDHC;
1757	Assert(pPDSrc);
1758	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK)) == pPDSrc);
1759
1760	/*
1761	* Iterate the page directory.
1762	*/
1763	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
1764	{
1765	VBOXPDE PdeSrc = pPDSrc->a[iPD];
1766	if (PdeSrc.n.u1Present)
1767	{
1768	if (PdeSrc.b.u1Size && fPSE)
1769	{
1770	pHlp->pfnPrintf(pHlp,
1771	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
1772	iPD,
1773	PdeSrc.u & X86_PDE_PG_MASK,
1774	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
1775	}
1776	else
1777	{
1778	pHlp->pfnPrintf(pHlp,
1779	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
1780	iPD,
1781	PdeSrc.u & X86_PDE4M_PG_MASK,
1782	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
1783	}
1784	}
1785	}
1786	}
1787
1788
1789	/**
1790	* Serivce a VMMCALLHOST_PGM_LOCK call.
1791	*
1792	* @returns VBox status code.
1793	* @param pVM The VM handle.
1794	*/
1795	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
1796	{
1797	return pgmLock(pVM);
1798	}
1799
1800
1801	/**
1802	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
1803	*
1804	* @returns PGM_TYPE_*.
1805	* @param pgmMode The mode value to convert.
1806	*/
1807	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
1808	{
1809	switch (pgmMode)
1810	{
1811	case PGMMODE_REAL: return PGM_TYPE_REAL;
1812	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
1813	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
1814	case PGMMODE_PAE:
1815	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
1816	case PGMMODE_AMD64:
1817	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
1818	default:
1819	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
1820	}
1821	}
1822
1823
1824	/**
1825	* Gets the index into the paging mode data array of a SHW+GST mode.
1826	*
1827	* @returns PGM::paPagingData index.
1828	* @param uShwType The shadow paging mode type.
1829	* @param uGstType The guest paging mode type.
1830	*/
1831	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
1832	{
1833	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_AMD64);
1834	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
1835	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_32BIT + 1)
1836	+ (uGstType - PGM_TYPE_REAL);
1837	}
1838
1839
1840	/**
1841	* Gets the index into the paging mode data array of a SHW+GST mode.
1842	*
1843	* @returns PGM::paPagingData index.
1844	* @param enmShw The shadow paging mode.
1845	* @param enmGst The guest paging mode.
1846	*/
1847	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
1848	{
1849	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
1850	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
1851	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
1852	}
1853
1854
1855	/**
1856	* Calculates the max data index.
1857	* @returns The number of entries in the pagaing data array.
1858	*/
1859	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
1860	{
1861	return pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64) + 1;
1862	}
1863
1864
1865	/**
1866	* Initializes the paging mode data kept in PGM::paModeData.
1867	*
1868	* @param pVM The VM handle.
1869	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
1870	* This is used early in the init process to avoid trouble with PDM
1871	* not being initialized yet.
1872	*/
1873	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
1874	{
1875	PPGMMODEDATA pModeData;
1876	int rc;
1877
1878	/*
1879	* Allocate the array on the first call.
1880	*/
1881	if (!pVM->pgm.s.paModeData)
1882	{
1883	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
1884	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
1885	}
1886
1887	/*
1888	* Initialize the array entries.
1889	*/
1890	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
1891	pModeData->uShwType = PGM_TYPE_32BIT;
1892	pModeData->uGstType = PGM_TYPE_REAL;
1893	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1894	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1895	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1896
1897	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
1898	pModeData->uShwType = PGM_TYPE_32BIT;
1899	pModeData->uGstType = PGM_TYPE_PROT;
1900	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1901	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1902	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1903
1904	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
1905	pModeData->uShwType = PGM_TYPE_32BIT;
1906	pModeData->uGstType = PGM_TYPE_32BIT;
1907	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1908	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1909	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1910
1911	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
1912	pModeData->uShwType = PGM_TYPE_PAE;
1913	pModeData->uGstType = PGM_TYPE_REAL;
1914	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1915	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1916	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1917
1918	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
1919	pModeData->uShwType = PGM_TYPE_PAE;
1920	pModeData->uGstType = PGM_TYPE_PROT;
1921	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1922	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1923	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1924
1925	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
1926	pModeData->uShwType = PGM_TYPE_PAE;
1927	pModeData->uGstType = PGM_TYPE_32BIT;
1928	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1929	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1930	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1931
1932	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
1933	pModeData->uShwType = PGM_TYPE_PAE;
1934	pModeData->uGstType = PGM_TYPE_PAE;
1935	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1936	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1937	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1938
1939	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_REAL)];
1940	pModeData->uShwType = PGM_TYPE_AMD64;
1941	pModeData->uGstType = PGM_TYPE_REAL;
1942	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1943	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1944	rc = PGM_BTH_NAME_AMD64_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1945
1946	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_PROT)];
1947	pModeData->uShwType = PGM_TYPE_AMD64;
1948	pModeData->uGstType = PGM_TYPE_PROT;
1949	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1950	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1951	rc = PGM_BTH_NAME_AMD64_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1952
1953	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
1954	pModeData->uShwType = PGM_TYPE_AMD64;
1955	pModeData->uGstType = PGM_TYPE_AMD64;
1956	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1957	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1958	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1959
1960	return VINF_SUCCESS;
1961	}
1962
1963
1964	/**
1965	* Swtich to different (or relocated in the relocate case) mode data.
1966	*
1967	* @param pVM The VM handle.
1968	* @param enmShw The the shadow paging mode.
1969	* @param enmGst The the guest paging mode.
1970	*/
1971	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
1972	{
1973	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(enmShw, enmGst)];
1974
1975	Assert(pModeData->uGstType == pgmModeToType(enmGst));
1976	Assert(pModeData->uShwType == pgmModeToType(enmShw));
1977
1978	/* shadow */
1979	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
1980	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
1981	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
1982	Assert(pVM->pgm.s.pfnR3ShwGetPage);
1983	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
1984	pVM->pgm.s.pfnR3ShwGetPDEByIndex = pModeData->pfnR3ShwGetPDEByIndex;
1985	pVM->pgm.s.pfnR3ShwSetPDEByIndex = pModeData->pfnR3ShwSetPDEByIndex;
1986	pVM->pgm.s.pfnR3ShwModifyPDEByIndex = pModeData->pfnR3ShwModifyPDEByIndex;
1987
1988	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
1989	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
1990	pVM->pgm.s.pfnGCShwGetPDEByIndex = pModeData->pfnGCShwGetPDEByIndex;
1991	pVM->pgm.s.pfnGCShwSetPDEByIndex = pModeData->pfnGCShwSetPDEByIndex;
1992	pVM->pgm.s.pfnGCShwModifyPDEByIndex = pModeData->pfnGCShwModifyPDEByIndex;
1993
1994	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
1995	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
1996	pVM->pgm.s.pfnR0ShwGetPDEByIndex = pModeData->pfnR0ShwGetPDEByIndex;
1997	pVM->pgm.s.pfnR0ShwSetPDEByIndex = pModeData->pfnR0ShwSetPDEByIndex;
1998	pVM->pgm.s.pfnR0ShwModifyPDEByIndex = pModeData->pfnR0ShwModifyPDEByIndex;
1999
2000
2001	/* guest */
2002	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2003	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2004	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2005	Assert(pVM->pgm.s.pfnR3GstGetPage);
2006	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2007	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2008	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2009	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2010	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2011	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2012	pVM->pgm.s.pfnHCGstWriteHandlerCR3 = pModeData->pfnHCGstWriteHandlerCR3;
2013	pVM->pgm.s.pszHCGstWriteHandlerCR3 = pModeData->pszHCGstWriteHandlerCR3;
2014
2015	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2016	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2017	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2018	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2019	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2020	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2021	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2022	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2023
2024	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2025	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2026	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2027	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2028	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2029	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2030	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2031	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2032
2033
2034	/* both */
2035	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2036	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2037	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2038	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2039	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2040	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2041	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2042	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2043	#ifdef VBOX_STRICT
2044	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2045	#endif
2046
2047	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2048	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2049	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2050	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2051	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2052	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2053	#ifdef VBOX_STRICT
2054	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2055	#endif
2056
2057	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2058	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2059	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2060	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2061	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2062	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2063	#ifdef VBOX_STRICT
2064	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2065	#endif
2066	}
2067
2068
2069	#ifdef DEBUG_bird
2070	#include <stdlib.h> /* getenv() remove me! */
2071	#endif
2072
2073	/**
2074	* Calculates the shadow paging mode.
2075	*
2076	* @returns The shadow paging mode.
2077	* @param enmGuestMode The guest mode.
2078	* @param enmHostMode The host mode.
2079	* @param enmShadowMode The current shadow mode.
2080	* @param penmSwitcher Where to store the switcher to use.
2081	* VMMSWITCHER_INVALID means no change.
2082	*/
2083	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2084	{
2085	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2086	switch (enmGuestMode)
2087	{
2088	/*
2089	* When switching to real or protected mode we don't change
2090	* anything since it's likely that we'll switch back pretty soon.
2091	*
2092	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2093	* and is supposed to determin which shadow paging and switcher to
2094	* use during init.
2095	*/
2096	case PGMMODE_REAL:
2097	case PGMMODE_PROTECTED:
2098	if (enmShadowMode != PGMMODE_INVALID)
2099	break; /* (no change) */
2100	switch (enmHostMode)
2101	{
2102	case SUPPAGINGMODE_32_BIT:
2103	case SUPPAGINGMODE_32_BIT_GLOBAL:
2104	enmShadowMode = PGMMODE_32_BIT;
2105	enmSwitcher = VMMSWITCHER_32_TO_32;
2106	break;
2107
2108	case SUPPAGINGMODE_PAE:
2109	case SUPPAGINGMODE_PAE_NX:
2110	case SUPPAGINGMODE_PAE_GLOBAL:
2111	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2112	enmShadowMode = PGMMODE_PAE;
2113	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2114	#ifdef DEBUG_bird
2115	if (getenv("VBOX_32BIT"))
2116	{
2117	enmShadowMode = PGMMODE_32_BIT;
2118	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2119	}
2120	#endif
2121	break;
2122
2123	case SUPPAGINGMODE_AMD64:
2124	case SUPPAGINGMODE_AMD64_GLOBAL:
2125	case SUPPAGINGMODE_AMD64_NX:
2126	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2127	enmShadowMode = PGMMODE_PAE;
2128	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2129	break;
2130
2131	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2132	}
2133	break;
2134
2135	case PGMMODE_32_BIT:
2136	switch (enmHostMode)
2137	{
2138	case SUPPAGINGMODE_32_BIT:
2139	case SUPPAGINGMODE_32_BIT_GLOBAL:
2140	enmShadowMode = PGMMODE_32_BIT;
2141	enmSwitcher = VMMSWITCHER_32_TO_32;
2142	break;
2143
2144	case SUPPAGINGMODE_PAE:
2145	case SUPPAGINGMODE_PAE_NX:
2146	case SUPPAGINGMODE_PAE_GLOBAL:
2147	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2148	enmShadowMode = PGMMODE_PAE;
2149	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2150	#ifdef DEBUG_bird
2151	if (getenv("VBOX_32BIT"))
2152	{
2153	enmShadowMode = PGMMODE_32_BIT;
2154	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2155	}
2156	#endif
2157	break;
2158
2159	case SUPPAGINGMODE_AMD64:
2160	case SUPPAGINGMODE_AMD64_GLOBAL:
2161	case SUPPAGINGMODE_AMD64_NX:
2162	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2163	enmShadowMode = PGMMODE_PAE;
2164	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2165	break;
2166
2167	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2168	}
2169	break;
2170
2171	case PGMMODE_PAE:
2172	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2173	switch (enmHostMode)
2174	{
2175	case SUPPAGINGMODE_32_BIT:
2176	case SUPPAGINGMODE_32_BIT_GLOBAL:
2177	enmShadowMode = PGMMODE_PAE;
2178	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2179	break;
2180
2181	case SUPPAGINGMODE_PAE:
2182	case SUPPAGINGMODE_PAE_NX:
2183	case SUPPAGINGMODE_PAE_GLOBAL:
2184	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2185	enmShadowMode = PGMMODE_PAE;
2186	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2187	break;
2188
2189	case SUPPAGINGMODE_AMD64:
2190	case SUPPAGINGMODE_AMD64_GLOBAL:
2191	case SUPPAGINGMODE_AMD64_NX:
2192	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2193	enmShadowMode = PGMMODE_PAE;
2194	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2195	break;
2196
2197	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2198	}
2199	break;
2200
2201	case PGMMODE_AMD64:
2202	case PGMMODE_AMD64_NX:
2203	switch (enmHostMode)
2204	{
2205	case SUPPAGINGMODE_32_BIT:
2206	case SUPPAGINGMODE_32_BIT_GLOBAL:
2207	enmShadowMode = PGMMODE_PAE;
2208	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2209	break;
2210
2211	case SUPPAGINGMODE_PAE:
2212	case SUPPAGINGMODE_PAE_NX:
2213	case SUPPAGINGMODE_PAE_GLOBAL:
2214	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2215	enmShadowMode = PGMMODE_PAE;
2216	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2217	break;
2218
2219	case SUPPAGINGMODE_AMD64:
2220	case SUPPAGINGMODE_AMD64_GLOBAL:
2221	case SUPPAGINGMODE_AMD64_NX:
2222	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2223	enmShadowMode = PGMMODE_PAE;
2224	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2225	break;
2226
2227	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2228	}
2229	break;
2230
2231
2232	default:
2233	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2234	return PGMMODE_INVALID;
2235	}
2236
2237	*penmSwitcher = enmSwitcher;
2238	return enmShadowMode;
2239	}
2240
2241
2242	/**
2243	* Performs the actual mode change.
2244	* This is called by PGMChangeMode and pgmR3InitPaging().
2245	*
2246	* @returns VBox status code.
2247	* @param pVM VM handle.
2248	* @param enmGuestMode The new guest mode. This is assumed to be different from
2249	* the current mode.
2250	*/
2251	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
2252	{
2253	LogFlow(("pgmR3ChangeMode: Guest mode: %d -> %d\n", pVM->pgm.s.enmGuestMode, enmGuestMode));
2254	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
2255
2256	/*
2257	* Calc the shadow mode and switcher.
2258	*/
2259	VMMSWITCHER enmSwitcher;
2260	PGMMODE enmShadowMode = pgmR3CalcShadowMode(enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
2261	if (enmSwitcher != VMMSWITCHER_INVALID)
2262	{
2263	/*
2264	* Select new switcher.
2265	*/
2266	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
2267	if (VBOX_FAILURE(rc))
2268	{
2269	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
2270	return rc;
2271	}
2272	}
2273
2274	/*
2275	* Exit old mode(s).
2276	*/
2277	/* shadow */
2278	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2279	{
2280	LogFlow(("pgmR3ChangeMode: Shadow mode: %d -> %d\n", pVM->pgm.s.enmShadowMode, enmShadowMode));
2281	if (PGM_SHW_PFN(Exit, pVM))
2282	{
2283	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
2284	if (VBOX_FAILURE(rc))
2285	{
2286	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
2287	return rc;
2288	}
2289	}
2290
2291	}
2292
2293	/* guest */
2294	if (PGM_GST_PFN(Exit, pVM))
2295	{
2296	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2297	if (VBOX_FAILURE(rc))
2298	{
2299	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
2300	return rc;
2301	}
2302	}
2303
2304	/*
2305	* Load new paging mode data.
2306	*/
2307	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
2308
2309	/*
2310	* Enter new shadow mode (if changed).
2311	*/
2312	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2313	{
2314	int rc;
2315	pVM->pgm.s.enmShadowMode = enmShadowMode;
2316	switch (enmShadowMode)
2317	{
2318	case PGMMODE_32_BIT:
2319	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
2320	break;
2321	case PGMMODE_PAE:
2322	case PGMMODE_PAE_NX:
2323	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
2324	break;
2325	case PGMMODE_AMD64:
2326	case PGMMODE_AMD64_NX:
2327	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
2328	break;
2329	case PGMMODE_REAL:
2330	case PGMMODE_PROTECTED:
2331	default:
2332	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
2333	return VERR_INTERNAL_ERROR;
2334	}
2335	if (VBOX_FAILURE(rc))
2336	{
2337	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
2338	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
2339	return rc;
2340	}
2341	}
2342
2343	/*
2344	* Enter the new guest and shadow+guest modes.
2345	*/
2346	int rc = -1;
2347	int rc2 = -1;
2348	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
2349	pVM->pgm.s.enmGuestMode = enmGuestMode;
2350	switch (enmGuestMode)
2351	{
2352	case PGMMODE_REAL:
2353	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
2354	switch (pVM->pgm.s.enmShadowMode)
2355	{
2356	case PGMMODE_32_BIT:
2357	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
2358	break;
2359	case PGMMODE_PAE:
2360	case PGMMODE_PAE_NX:
2361	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
2362	break;
2363	case PGMMODE_AMD64:
2364	case PGMMODE_AMD64_NX:
2365	rc2 = PGM_BTH_NAME_AMD64_REAL(Enter)(pVM, NIL_RTGCPHYS);
2366	break;
2367	default: AssertFailed(); break;
2368	}
2369	break;
2370
2371	case PGMMODE_PROTECTED:
2372	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
2373	switch (pVM->pgm.s.enmShadowMode)
2374	{
2375	case PGMMODE_32_BIT:
2376	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
2377	break;
2378	case PGMMODE_PAE:
2379	case PGMMODE_PAE_NX:
2380	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
2381	break;
2382	case PGMMODE_AMD64:
2383	case PGMMODE_AMD64_NX:
2384	rc2 = PGM_BTH_NAME_AMD64_PROT(Enter)(pVM, NIL_RTGCPHYS);
2385	break;
2386	default: AssertFailed(); break;
2387	}
2388	break;
2389
2390	case PGMMODE_32_BIT:
2391	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
2392	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
2393	switch (pVM->pgm.s.enmShadowMode)
2394	{
2395	case PGMMODE_32_BIT:
2396	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
2397	break;
2398	case PGMMODE_PAE:
2399	case PGMMODE_PAE_NX:
2400	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
2401	break;
2402	case PGMMODE_AMD64:
2403	case PGMMODE_AMD64_NX:
2404	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2405	default: AssertFailed(); break;
2406	}
2407	break;
2408
2409	//case PGMMODE_PAE_NX:
2410	case PGMMODE_PAE:
2411	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
2412	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
2413	switch (pVM->pgm.s.enmShadowMode)
2414	{
2415	case PGMMODE_PAE:
2416	case PGMMODE_PAE_NX:
2417	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
2418	break;
2419	case PGMMODE_32_BIT:
2420	case PGMMODE_AMD64:
2421	case PGMMODE_AMD64_NX:
2422	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2423	default: AssertFailed(); break;
2424	}
2425	break;
2426
2427	//case PGMMODE_AMD64_NX:
2428	case PGMMODE_AMD64:
2429	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask and make CR3 64-bit in this case! */
2430	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
2431	switch (pVM->pgm.s.enmShadowMode)
2432	{
2433	case PGMMODE_AMD64:
2434	case PGMMODE_AMD64_NX:
2435	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
2436	break;
2437	case PGMMODE_32_BIT:
2438	case PGMMODE_PAE:
2439	case PGMMODE_PAE_NX:
2440	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
2441	default: AssertFailed(); break;
2442	}
2443	break;
2444
2445	default:
2446	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2447	rc = VERR_NOT_IMPLEMENTED;
2448	break;
2449	}
2450
2451	/* status codes. */
2452	AssertRC(rc);
2453	AssertRC(rc2);
2454	if (VBOX_SUCCESS(rc))
2455	{
2456	rc = rc2;
2457	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
2458	rc = VINF_SUCCESS;
2459	}
2460
2461	/*
2462	* Notify SELM so it can update the TSSes with correct CR3s.
2463	*/
2464	SELMR3PagingModeChanged(pVM);
2465
2466	/* Notify HWACCM as well. */
2467	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
2468	return rc;
2469	}
2470
2471
2472	/**
2473	* Dumps a PAE shadow page table.
2474	*
2475	* @returns VBox status code (VINF_SUCCESS).
2476	* @param pVM The VM handle.
2477	* @param pPT Pointer to the page table.
2478	* @param u64Address The virtual address of the page table starts.
2479	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2480	* @param cMaxDepth The maxium depth.
2481	* @param pHlp Pointer to the output functions.
2482	*/
2483	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2484	{
2485	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2486	{
2487	X86PTEPAE Pte = pPT->a[i];
2488	if (Pte.n.u1Present)
2489	{
2490	pHlp->pfnPrintf(pHlp,
2491	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2492	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
2493	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
2494	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
2495	Pte.n.u1Write ? 'W' : 'R',
2496	Pte.n.u1User ? 'U' : 'S',
2497	Pte.n.u1Accessed ? 'A' : '-',
2498	Pte.n.u1Dirty ? 'D' : '-',
2499	Pte.n.u1Global ? 'G' : '-',
2500	Pte.n.u1WriteThru ? "WT" : "--",
2501	Pte.n.u1CacheDisable? "CD" : "--",
2502	Pte.n.u1PAT ? "AT" : "--",
2503	Pte.n.u1NoExecute ? "NX" : "--",
2504	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2505	Pte.u & BIT(10) ? '1' : '0',
2506	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
2507	Pte.u & X86_PTE_PAE_PG_MASK);
2508	}
2509	}
2510	return VINF_SUCCESS;
2511	}
2512
2513
2514	/**
2515	* Dumps a PAE shadow page directory table.
2516	*
2517	* @returns VBox status code (VINF_SUCCESS).
2518	* @param pVM The VM handle.
2519	* @param HCPhys The physical address of the page directory table.
2520	* @param u64Address The virtual address of the page table starts.
2521	* @param cr4 The CR4, PSE is currently used.
2522	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2523	* @param cMaxDepth The maxium depth.
2524	* @param pHlp Pointer to the output functions.
2525	*/
2526	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2527	{
2528	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
2529	if (!pPD)
2530	{
2531	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
2532	fLongMode ? 16 : 8, u64Address, HCPhys);
2533	return VERR_INVALID_PARAMETER;
2534	}
2535	int rc = VINF_SUCCESS;
2536	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2537	{
2538	X86PDEPAE Pde = pPD->a[i];
2539	if (Pde.n.u1Present)
2540	{
2541	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2542	pHlp->pfnPrintf(pHlp,
2543	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2544	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
2545	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
2546	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2547	Pde.b.u1Write ? 'W' : 'R',
2548	Pde.b.u1User ? 'U' : 'S',
2549	Pde.b.u1Accessed ? 'A' : '-',
2550	Pde.b.u1Dirty ? 'D' : '-',
2551	Pde.b.u1Global ? 'G' : '-',
2552	Pde.b.u1WriteThru ? "WT" : "--",
2553	Pde.b.u1CacheDisable? "CD" : "--",
2554	Pde.b.u1PAT ? "AT" : "--",
2555	Pde.b.u1NoExecute ? "NX" : "--",
2556	Pde.u & BIT64(9) ? '1' : '0',
2557	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2558	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2559	Pde.u & X86_PDE_PAE_PG_MASK);
2560	else
2561	{
2562	pHlp->pfnPrintf(pHlp,
2563	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2564	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
2565	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
2566	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2567	Pde.n.u1Write ? 'W' : 'R',
2568	Pde.n.u1User ? 'U' : 'S',
2569	Pde.n.u1Accessed ? 'A' : '-',
2570	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2571	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2572	Pde.n.u1WriteThru ? "WT" : "--",
2573	Pde.n.u1CacheDisable? "CD" : "--",
2574	Pde.n.u1NoExecute ? "NX" : "--",
2575	Pde.u & BIT64(9) ? '1' : '0',
2576	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2577	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2578	Pde.u & X86_PDE_PAE_PG_MASK);
2579	if (cMaxDepth >= 1)
2580	{
2581	/** @todo what about using the page pool for mapping PTs? */
2582	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
2583	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
2584	PX86PTPAE pPT = NULL;
2585	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2586	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
2587	else
2588	{
2589	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsHC; pMap; pMap = pMap->pNextHC)
2590	{
2591	uint64_t off = u64AddressPT - pMap->GCPtr;
2592	if (off < pMap->cb)
2593	{
2594	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
2595	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
2596	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
2597	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2598	fLongMode ? 16 : 8, u64AddressPT, iPDE,
2599	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
2600	pPT = &pMap->aPTs[iPDE].paPaePTsHC[iSub];
2601	}
2602	}
2603	}
2604	int rc2 = VERR_INVALID_PARAMETER;
2605	if (pPT)
2606	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
2607	else
2608	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
2609	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
2610	if (rc2 < rc && VBOX_SUCCESS(rc))
2611	rc = rc2;
2612	}
2613	}
2614	}
2615	}
2616	return rc;
2617	}
2618
2619
2620	/**
2621	* Dumps a PAE shadow page directory pointer table.
2622	*
2623	* @returns VBox status code (VINF_SUCCESS).
2624	* @param pVM The VM handle.
2625	* @param HCPhys The physical address of the page directory pointer table.
2626	* @param u64Address The virtual address of the page table starts.
2627	* @param cr4 The CR4, PSE is currently used.
2628	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2629	* @param cMaxDepth The maxium depth.
2630	* @param pHlp Pointer to the output functions.
2631	*/
2632	static int pgmR3DumpHierarchyHCPaePDPTR(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2633	{
2634	PX86PDPTR pPDPTR = (PX86PDPTR)MMPagePhys2Page(pVM, HCPhys);
2635	if (!pPDPTR)
2636	{
2637	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
2638	fLongMode ? 16 : 8, u64Address, HCPhys);
2639	return VERR_INVALID_PARAMETER;
2640	}
2641
2642	int rc = VINF_SUCCESS;
2643	const unsigned c = fLongMode ? ELEMENTS(pPDPTR->a) : 4;
2644	for (unsigned i = 0; i < c; i++)
2645	{
2646	X86PDPE Pdpe = pPDPTR->a[i];
2647	if (Pdpe.n.u1Present)
2648	{
2649	if (fLongMode)
2650	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2651	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2652	u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2653	Pdpe.n.u1Write ? 'W' : 'R',
2654	Pdpe.n.u1User ? 'U' : 'S',
2655	Pdpe.n.u1Accessed ? 'A' : '-',
2656	Pdpe.n.u3Reserved & 1? '?' : '.', /* ignored */
2657	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2658	Pdpe.n.u1WriteThru ? "WT" : "--",
2659	Pdpe.n.u1CacheDisable? "CD" : "--",
2660	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2661	Pdpe.n.u1NoExecute ? "NX" : "--",
2662	Pdpe.u & BIT(9) ? '1' : '0',
2663	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2664	Pdpe.u & BIT(11) ? '1' : '0',
2665	Pdpe.u & X86_PDPE_PG_MASK);
2666	else
2667	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2668	"%08x 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2669	i << X86_PDPTR_SHIFT,
2670	Pdpe.n.u1Write ? '!' : '.', /* mbz */
2671	Pdpe.n.u1User ? '!' : '.', /* mbz */
2672	Pdpe.n.u1Accessed ? '!' : '.', /* mbz */
2673	Pdpe.n.u3Reserved & 1? '!' : '.', /* mbz */
2674	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2675	Pdpe.n.u1WriteThru ? "WT" : "--",
2676	Pdpe.n.u1CacheDisable? "CD" : "--",
2677	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2678	Pdpe.n.u1NoExecute ? "NX" : "--",
2679	Pdpe.u & BIT(9) ? '1' : '0',
2680	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2681	Pdpe.u & BIT(11) ? '1' : '0',
2682	Pdpe.u & X86_PDPE_PG_MASK);
2683	if (cMaxDepth >= 1)
2684	{
2685	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2686	cr4, fLongMode, cMaxDepth - 1, pHlp);
2687	if (rc2 < rc && VBOX_SUCCESS(rc))
2688	rc = rc2;
2689	}
2690	}
2691	}
2692	return rc;
2693	}
2694
2695
2696	/**
2697	* Dumps a 32-bit shadow page table.
2698	*
2699	* @returns VBox status code (VINF_SUCCESS).
2700	* @param pVM The VM handle.
2701	* @param HCPhys The physical address of the table.
2702	* @param cr4 The CR4, PSE is currently used.
2703	* @param cMaxDepth The maxium depth.
2704	* @param pHlp Pointer to the output functions.
2705	*/
2706	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2707	{
2708	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
2709	if (!pPML4)
2710	{
2711	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
2712	return VERR_INVALID_PARAMETER;
2713	}
2714
2715	int rc = VINF_SUCCESS;
2716	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
2717	{
2718	X86PML4E Pml4e = pPML4->a[i];
2719	if (Pml4e.n.u1Present)
2720	{
2721	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPTR_SHIFT - 1)) * 0xffff000000000000ULL);
2722	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2723	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2724	u64Address,
2725	Pml4e.n.u1Write ? 'W' : 'R',
2726	Pml4e.n.u1User ? 'U' : 'S',
2727	Pml4e.n.u1Accessed ? 'A' : '-',
2728	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
2729	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
2730	Pml4e.n.u1WriteThru ? "WT" : "--",
2731	Pml4e.n.u1CacheDisable? "CD" : "--",
2732	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
2733	Pml4e.n.u1NoExecute ? "NX" : "--",
2734	Pml4e.u & BIT(9) ? '1' : '0',
2735	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2736	Pml4e.u & BIT(11) ? '1' : '0',
2737	Pml4e.u & X86_PML4E_PG_MASK);
2738
2739	if (cMaxDepth >= 1)
2740	{
2741	int rc2 = pgmR3DumpHierarchyHCPaePDPTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
2742	if (rc2 < rc && VBOX_SUCCESS(rc))
2743	rc = rc2;
2744	}
2745	}
2746	}
2747	return rc;
2748	}
2749
2750
2751	/**
2752	* Dumps a 32-bit shadow page table.
2753	*
2754	* @returns VBox status code (VINF_SUCCESS).
2755	* @param pVM The VM handle.
2756	* @param pPT Pointer to the page table.
2757	* @param u32Address The virtual address this table starts at.
2758	* @param pHlp Pointer to the output functions.
2759	*/
2760	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
2761	{
2762	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2763	{
2764	X86PTE Pte = pPT->a[i];
2765	if (Pte.n.u1Present)
2766	{
2767	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2768	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2769	u32Address + (i << X86_PT_SHIFT),
2770	Pte.n.u1Write ? 'W' : 'R',
2771	Pte.n.u1User ? 'U' : 'S',
2772	Pte.n.u1Accessed ? 'A' : '-',
2773	Pte.n.u1Dirty ? 'D' : '-',
2774	Pte.n.u1Global ? 'G' : '-',
2775	Pte.n.u1WriteThru ? "WT" : "--",
2776	Pte.n.u1CacheDisable? "CD" : "--",
2777	Pte.n.u1PAT ? "AT" : "--",
2778	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2779	Pte.u & BIT(10) ? '1' : '0',
2780	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2781	Pte.u & X86_PDE_PG_MASK);
2782	}
2783	}
2784	return VINF_SUCCESS;
2785	}
2786
2787
2788	/**
2789	* Dumps a 32-bit shadow page directory and page tables.
2790	*
2791	* @returns VBox status code (VINF_SUCCESS).
2792	* @param pVM The VM handle.
2793	* @param cr3 The root of the hierarchy.
2794	* @param cr4 The CR4, PSE is currently used.
2795	* @param cMaxDepth How deep into the hierarchy the dumper should go.
2796	* @param pHlp Pointer to the output functions.
2797	*/
2798	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2799	{
2800	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
2801	if (!pPD)
2802	{
2803	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
2804	return VERR_INVALID_PARAMETER;
2805	}
2806
2807	int rc = VINF_SUCCESS;
2808	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2809	{
2810	X86PDE Pde = pPD->a[i];
2811	if (Pde.n.u1Present)
2812	{
2813	const uint32_t u32Address = i << X86_PD_SHIFT;
2814	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2815	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2816	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2817	u32Address,
2818	Pde.b.u1Write ? 'W' : 'R',
2819	Pde.b.u1User ? 'U' : 'S',
2820	Pde.b.u1Accessed ? 'A' : '-',
2821	Pde.b.u1Dirty ? 'D' : '-',
2822	Pde.b.u1Global ? 'G' : '-',
2823	Pde.b.u1WriteThru ? "WT" : "--",
2824	Pde.b.u1CacheDisable? "CD" : "--",
2825	Pde.b.u1PAT ? "AT" : "--",
2826	Pde.u & BIT64(9) ? '1' : '0',
2827	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2828	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2829	Pde.u & X86_PDE4M_PG_MASK);
2830	else
2831	{
2832	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2833	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
2834	u32Address,
2835	Pde.n.u1Write ? 'W' : 'R',
2836	Pde.n.u1User ? 'U' : 'S',
2837	Pde.n.u1Accessed ? 'A' : '-',
2838	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2839	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2840	Pde.n.u1WriteThru ? "WT" : "--",
2841	Pde.n.u1CacheDisable? "CD" : "--",
2842	Pde.u & BIT64(9) ? '1' : '0',
2843	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2844	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2845	Pde.u & X86_PDE_PG_MASK);
2846	if (cMaxDepth >= 1)
2847	{
2848	/** @todo what about using the page pool for mapping PTs? */
2849	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
2850	PX86PT pPT = NULL;
2851	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2852	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
2853	else
2854	{
2855	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsHC; pMap; pMap = pMap->pNextHC)
2856	if (u32Address - pMap->GCPtr < pMap->cb)
2857	{
2858	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
2859	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
2860	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2861	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
2862	pPT = pMap->aPTs[iPDE].pPTHC;
2863	}
2864	}
2865	int rc2 = VERR_INVALID_PARAMETER;
2866	if (pPT)
2867	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
2868	else
2869	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
2870	if (rc2 < rc && VBOX_SUCCESS(rc))
2871	rc = rc2;
2872	}
2873	}
2874	}
2875	}
2876
2877	return rc;
2878	}
2879
2880
2881	/**
2882	* Dumps a 32-bit shadow page table.
2883	*
2884	* @returns VBox status code (VINF_SUCCESS).
2885	* @param pVM The VM handle.
2886	* @param pPT Pointer to the page table.
2887	* @param u32Address The virtual address this table starts at.
2888	* @param PhysSearch Address to search for.
2889	*/
2890	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
2891	{
2892	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2893	{
2894	X86PTE Pte = pPT->a[i];
2895	if (Pte.n.u1Present)
2896	{
2897	Log(( /P R S A D G WT CD AT NX 4M a m d /
2898	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2899	u32Address + (i << X86_PT_SHIFT),
2900	Pte.n.u1Write ? 'W' : 'R',
2901	Pte.n.u1User ? 'U' : 'S',
2902	Pte.n.u1Accessed ? 'A' : '-',
2903	Pte.n.u1Dirty ? 'D' : '-',
2904	Pte.n.u1Global ? 'G' : '-',
2905	Pte.n.u1WriteThru ? "WT" : "--",
2906	Pte.n.u1CacheDisable? "CD" : "--",
2907	Pte.n.u1PAT ? "AT" : "--",
2908	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2909	Pte.u & BIT(10) ? '1' : '0',
2910	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2911	Pte.u & X86_PDE_PG_MASK));
2912
2913	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
2914	{
2915	uint64_t fPageShw = 0;
2916	RTHCPHYS pPhysHC = 0;
2917
2918	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
2919	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
2920	}
2921	}
2922	}
2923	return VINF_SUCCESS;
2924	}
2925
2926
2927	/**
2928	* Dumps a 32-bit guest page directory and page tables.
2929	*
2930	* @returns VBox status code (VINF_SUCCESS).
2931	* @param pVM The VM handle.
2932	* @param cr3 The root of the hierarchy.
2933	* @param cr4 The CR4, PSE is currently used.
2934	* @param PhysSearch Address to search for.
2935	*/
2936	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCPHYS PhysSearch)
2937	{
2938	bool fLongMode = false;
2939	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
2940	PX86PD pPD = 0;
2941
2942	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
2943	if (VBOX_FAILURE(rc) \|\| !pPD)
2944	{
2945	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
2946	return VERR_INVALID_PARAMETER;
2947	}
2948
2949	Log(("cr3=%08x cr4=%08x%s\n"
2950	"%-*s P - Present\n"
2951	"%-*s \| R/W - Read (0) / Write (1)\n"
2952	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
2953	"%-*s \| \| \| A - Accessed\n"
2954	"%-*s \| \| \| \| D - Dirty\n"
2955	"%-*s \| \| \| \| \| G - Global\n"
2956	"%-*s \| \| \| \| \| \| WT - Write thru\n"
2957	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
2958	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
2959	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
2960	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
2961	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
2962	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
2963	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
2964	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
2965	- W U - - - -- -- -- -- -- 010 */
2966	, cr3, cr4, fLongMode ? " Long Mode" : "",
2967	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
2968	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
2969
2970	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2971	{
2972	X86PDE Pde = pPD->a[i];
2973	if (Pde.n.u1Present)
2974	{
2975	const uint32_t u32Address = i << X86_PD_SHIFT;
2976
2977	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2978	Log(( /P R S A D G WT CD AT NX 4M a m d /
2979	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2980	u32Address,
2981	Pde.b.u1Write ? 'W' : 'R',
2982	Pde.b.u1User ? 'U' : 'S',
2983	Pde.b.u1Accessed ? 'A' : '-',
2984	Pde.b.u1Dirty ? 'D' : '-',
2985	Pde.b.u1Global ? 'G' : '-',
2986	Pde.b.u1WriteThru ? "WT" : "--",
2987	Pde.b.u1CacheDisable? "CD" : "--",
2988	Pde.b.u1PAT ? "AT" : "--",
2989	Pde.u & BIT(9) ? '1' : '0',
2990	Pde.u & BIT(10) ? '1' : '0',
2991	Pde.u & BIT(11) ? '1' : '0',
2992	Pde.u & X86_PDE4M_PG_MASK));
2993	/** @todo PhysSearch */
2994	else
2995	{
2996	Log(( /P R S A D G WT CD AT NX 4M a m d /
2997	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
2998	u32Address,
2999	Pde.n.u1Write ? 'W' : 'R',
3000	Pde.n.u1User ? 'U' : 'S',
3001	Pde.n.u1Accessed ? 'A' : '-',
3002	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3003	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3004	Pde.n.u1WriteThru ? "WT" : "--",
3005	Pde.n.u1CacheDisable? "CD" : "--",
3006	Pde.u & BIT(9) ? '1' : '0',
3007	Pde.u & BIT(10) ? '1' : '0',
3008	Pde.u & BIT(11) ? '1' : '0',
3009	Pde.u & X86_PDE_PG_MASK));
3010	////if (cMaxDepth >= 1)
3011	{
3012	/** @todo what about using the page pool for mapping PTs? */
3013	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3014	PX86PT pPT = NULL;
3015
3016	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3017
3018	int rc2 = VERR_INVALID_PARAMETER;
3019	if (pPT)
3020	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3021	else
3022	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3023	if (rc2 < rc && VBOX_SUCCESS(rc))
3024	rc = rc2;
3025	}
3026	}
3027	}
3028	}
3029
3030	return rc;
3031	}
3032
3033
3034	/**
3035	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3036	*
3037	* @returns VBox status code (VINF_SUCCESS).
3038	* @param pVM The VM handle.
3039	* @param cr3 The root of the hierarchy.
3040	* @param cr4 The cr4, only PAE and PSE is currently used.
3041	* @param fLongMode Set if long mode, false if not long mode.
3042	* @param cMaxDepth Number of levels to dump.
3043	* @param pHlp Pointer to the output functions.
3044	*/
3045	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3046	{
3047	if (!pHlp)
3048	pHlp = DBGFR3InfoLogHlp();
3049	if (!cMaxDepth)
3050	return VINF_SUCCESS;
3051	const unsigned cch = fLongMode ? 16 : 8;
3052	pHlp->pfnPrintf(pHlp,
3053	"cr3=%08x cr4=%08x%s\n"
3054	"%-*s P - Present\n"
3055	"%-*s \| R/W - Read (0) / Write (1)\n"
3056	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3057	"%-*s \| \| \| A - Accessed\n"
3058	"%-*s \| \| \| \| D - Dirty\n"
3059	"%-*s \| \| \| \| \| G - Global\n"
3060	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3061	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3062	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3063	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3064	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3065	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3066	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3067	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3068	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3069	- W U - - - -- -- -- -- -- 010 */
3070	, cr3, cr4, fLongMode ? " Long Mode" : "",
3071	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3072	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3073	if (cr4 & X86_CR4_PAE)
3074	{
3075	if (fLongMode)
3076	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3077	return pgmR3DumpHierarchyHCPaePDPTR(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3078	}
3079	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3080	}
3081
3082
3083
3084	#ifdef VBOX_WITH_DEBUGGER
3085	/**
3086	* The '.pgmram' command.
3087	*
3088	* @returns VBox status.
3089	* @param pCmd Pointer to the command descriptor (as registered).
3090	* @param pCmdHlp Pointer to command helper functions.
3091	* @param pVM Pointer to the current VM (if any).
3092	* @param paArgs Pointer to (readonly) array of arguments.
3093	* @param cArgs Number of arguments in the array.
3094	*/
3095	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3096	{
3097	/*
3098	* Validate input.
3099	*/
3100	if (!pVM)
3101	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3102	if (!pVM->pgm.s.pRamRangesGC)
3103	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3104
3105	/*
3106	* Dump the ranges.
3107	*/
3108	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3109	PPGMRAMRANGE pRam;
3110	for (pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
3111	{
3112	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3113	"%VGp - %VGp %p\n",
3114	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3115	if (VBOX_FAILURE(rc))
3116	return rc;
3117	}
3118
3119	return VINF_SUCCESS;
3120	}
3121
3122
3123	/**
3124	* The '.pgmmap' command.
3125	*
3126	* @returns VBox status.
3127	* @param pCmd Pointer to the command descriptor (as registered).
3128	* @param pCmdHlp Pointer to command helper functions.
3129	* @param pVM Pointer to the current VM (if any).
3130	* @param paArgs Pointer to (readonly) array of arguments.
3131	* @param cArgs Number of arguments in the array.
3132	*/
3133	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3134	{
3135	/*
3136	* Validate input.
3137	*/
3138	if (!pVM)
3139	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3140	if (!pVM->pgm.s.pMappingsHC)
3141	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3142
3143	/*
3144	* Print message about the fixedness of the mappings.
3145	*/
3146	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3147	if (VBOX_FAILURE(rc))
3148	return rc;
3149
3150	/*
3151	* Dump the ranges.
3152	*/
3153	PPGMMAPPING pCur;
3154	for (pCur = pVM->pgm.s.pMappingsHC; pCur; pCur = pCur->pNextHC)
3155	{
3156	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3157	"%08x - %08x %s\n",
3158	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3159	if (VBOX_FAILURE(rc))
3160	return rc;
3161	}
3162
3163	return VINF_SUCCESS;
3164	}
3165
3166
3167	/**
3168	* The '.pgmsync' command.
3169	*
3170	* @returns VBox status.
3171	* @param pCmd Pointer to the command descriptor (as registered).
3172	* @param pCmdHlp Pointer to command helper functions.
3173	* @param pVM Pointer to the current VM (if any).
3174	* @param paArgs Pointer to (readonly) array of arguments.
3175	* @param cArgs Number of arguments in the array.
3176	*/
3177	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3178	{
3179	/*
3180	* Validate input.
3181	*/
3182	if (!pVM)
3183	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3184
3185	/*
3186	* Force page directory sync.
3187	*/
3188	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3189
3190	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3191	if (VBOX_FAILURE(rc))
3192	return rc;
3193
3194	return VINF_SUCCESS;
3195	}
3196
3197
3198	/**
3199	* The '.pgmsyncalways' command.
3200	*
3201	* @returns VBox status.
3202	* @param pCmd Pointer to the command descriptor (as registered).
3203	* @param pCmdHlp Pointer to command helper functions.
3204	* @param pVM Pointer to the current VM (if any).
3205	* @param paArgs Pointer to (readonly) array of arguments.
3206	* @param cArgs Number of arguments in the array.
3207	*/
3208	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3209	{
3210	/*
3211	* Validate input.
3212	*/
3213	if (!pVM)
3214	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3215
3216	/*
3217	* Force page directory sync.
3218	*/
3219	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3220	{
3221	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3222	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3223	}
3224	else
3225	{
3226	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3227	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3228	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3229	}
3230	}
3231
3232	#endif
3233
3234	/**
3235	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3236	*/
3237	typedef struct PGMCHECKINTARGS
3238	{
3239	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3240	PPGMPHYSHANDLER pPrevPhys;
3241	PPGMVIRTHANDLER pPrevVirt;
3242	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3243	PVM pVM;
3244	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3245
3246	/**
3247	* Validate a node in the physical handler tree.
3248	*
3249	* @returns 0 on if ok, other wise 1.
3250	* @param pNode The handler node.
3251	* @param pvUser pVM.
3252	*/
3253	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3254	{
3255	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3256	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3257	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3258	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3259	AssertReleaseMsg( !pArgs->pPrevPhys
3260	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3261	("pPrevPhys=%p %VGp-%VGp %s\n"
3262	" pCur=%p %VGp-%VGp %s\n",
3263	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3264	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3265	pArgs->pPrevPhys = pCur;
3266	return 0;
3267	}
3268
3269
3270	/**
3271	* Validate a node in the virtual handler tree.
3272	*
3273	* @returns 0 on if ok, other wise 1.
3274	* @param pNode The handler node.
3275	* @param pvUser pVM.
3276	*/
3277	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
3278	{
3279	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3280	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
3281	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3282	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3283	AssertReleaseMsg( !pArgs->pPrevVirt
3284	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
3285	("pPrevVirt=%p %VGv-%VGv %s\n"
3286	" pCur=%p %VGv-%VGv %s\n",
3287	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
3288	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3289	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
3290	{
3291	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
3292	("pCur=%p %VGv-%VGv %s\n"
3293	"iPage=%d offVirtHandle=%#x expected %#x\n",
3294	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
3295	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
3296	}
3297	pArgs->pPrevVirt = pCur;
3298	return 0;
3299	}
3300
3301
3302	/**
3303	* Validate a node in the virtual handler tree.
3304	*
3305	* @returns 0 on if ok, other wise 1.
3306	* @param pNode The handler node.
3307	* @param pvUser pVM.
3308	*/
3309	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3310	{
3311	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3312	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
3313	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
3314	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
3315	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
3316	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3317	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3318	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3319	" pCur=%p %VGp-%VGp\n",
3320	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3321	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3322	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3323	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3324	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3325	" pCur=%p %VGp-%VGp\n",
3326	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3327	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3328	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
3329	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3330	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3331	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3332	{
3333	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
3334	for (;;)
3335	{
3336	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3337	AssertReleaseMsg(pCur2 != pCur,
3338	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3339	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3340	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
3341	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3342	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3343	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3344	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3345	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
3346	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3347	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3348	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3349	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3350	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
3351	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3352	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3353	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3354	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3355	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3356	break;
3357	}
3358	}
3359
3360	pArgs->pPrevPhys2Virt = pCur;
3361	return 0;
3362	}
3363
3364
3365	/**
3366	* Perform an integrity check on the PGM component.
3367	*
3368	* @returns VINF_SUCCESS if everything is fine.
3369	* @returns VBox error status after asserting on integrity breach.
3370	* @param pVM The VM handle.
3371	*/
3372	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
3373	{
3374	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
3375
3376	/*
3377	* Check the trees.
3378	*/
3379	int cErrors = 0;
3380	PGMCHECKINTARGS Args = { true, NULL, NULL, NULL, pVM };
3381	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3382	Args.fLeftToRight = false;
3383	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3384	Args.fLeftToRight = true;
3385	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3386	Args.fLeftToRight = false;
3387	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3388	Args.fLeftToRight = true;
3389	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3390	Args.fLeftToRight = false;
3391	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3392
3393	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
3394	}
3395
3396
3397	/**
3398	* Inform PGM we don't wish any mapping to be put into the shadow page table. (necessary for e.g. VMX)
3399	*
3400	* @returns VBox status code.
3401	* @param pVM VM handle.
3402	*/
3403	PGMR3DECL(int) PGMR3RemoveMappingsFromShwPD(PVM pVM)
3404	{
3405
3406	pVM->pgm.s.fDisableMappings = true;
3407
3408	size_t cb;
3409	int rc = PGMR3MappingsSize(pVM, &cb);
3410	AssertRCReturn(rc, rc);
3411
3412	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
3413	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
3414	AssertRCReturn(rc, rc);
3415
3416	VMMR3DisableSwitcher(pVM);
3417	return VINF_SUCCESS;
3418	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 40

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