PGM.cpp@ 3723

Last change on this file since 3723 was 3696, checked in by vboxsync, 17 years ago
double underscore cleanup.
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1	/* $Id: PGM.cpp 3696 2007-07-18 17:00:33Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pg_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pg_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPTR and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pg_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pg_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pg_misc Misc
97	*
98	* @subsection subsec_pg_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*/
111
112
113
114	/** Saved state data unit version. */
115	#define PGM_SAVED_STATE_VERSION 5
116
117	/*******************************************************************************
118	* Header Files *
119	*******************************************************************************/
120	#define LOG_GROUP LOG_GROUP_PGM
121	#include <VBox/dbgf.h>
122	#include <VBox/pgm.h>
123	#include <VBox/cpum.h>
124	#include <VBox/iom.h>
125	#include <VBox/sup.h>
126	#include <VBox/mm.h>
127	#include <VBox/pdm.h>
128	#include <VBox/em.h>
129	#include <VBox/stam.h>
130	#include <VBox/rem.h>
131	#include <VBox/dbgf.h>
132	#include <VBox/rem.h>
133	#include <VBox/selm.h>
134	#include <VBox/ssm.h>
135	#include "PGMInternal.h"
136	#include <VBox/vm.h>
137	#include <VBox/dbg.h>
138	#include <VBox/hwaccm.h>
139
140	#include <VBox/log.h>
141	#include <iprt/assert.h>
142	#include <iprt/alloc.h>
143	#include <iprt/asm.h>
144	#include <iprt/thread.h>
145	#include <iprt/string.h>
146	#include <VBox/param.h>
147	#include <VBox/err.h>
148
149
150
151	/*******************************************************************************
152	* Internal Functions *
153	*******************************************************************************/
154	static int pgmR3InitPaging(PVM pVM);
155	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
156	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
157	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
158	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
159	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
160	#ifdef VBOX_STRICT
161	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
162	#endif
163	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
164	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
165	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
166	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
167	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
168
169	#ifdef VBOX_WITH_STATISTICS
170	static void pgmR3InitStats(PVM pVM);
171	#endif
172
173	#ifdef VBOX_WITH_DEBUGGER
174	/** @todo all but the two last commands must be converted to 'info'. */
175	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
176	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
177	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
178	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
179	#endif
180
181
182	/*******************************************************************************
183	* Global Variables *
184	*******************************************************************************/
185	#ifdef VBOX_WITH_DEBUGGER
186	/** Command descriptors. */
187	static const DBGCCMD g_aCmds[] =
188	{
189	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
190	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
191	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
192	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
193	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
194	};
195	#endif
196
197
198
199
200	#if 1/// @todo ndef RT_ARCH_AMD64
201	/*
202	* Shadow - 32-bit mode
203	*/
204	#define PGM_SHW_TYPE PGM_TYPE_32BIT
205	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
206	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
207	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
208	#include "PGMShw.h"
209
210	/* Guest - real mode */
211	#define PGM_GST_TYPE PGM_TYPE_REAL
212	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
213	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
214	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
215	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
216	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
217	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
218	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
219	#include "PGMGst.h"
220	#include "PGMBth.h"
221	#undef BTH_PGMPOOLKIND_PT_FOR_PT
222	#undef PGM_BTH_NAME
223	#undef PGM_BTH_NAME_GC_STR
224	#undef PGM_BTH_NAME_R0_STR
225	#undef PGM_GST_TYPE
226	#undef PGM_GST_NAME
227	#undef PGM_GST_NAME_GC_STR
228	#undef PGM_GST_NAME_R0_STR
229
230	/* Guest - protected mode */
231	#define PGM_GST_TYPE PGM_TYPE_PROT
232	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
233	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
234	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
235	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
236	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
237	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
238	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
239	#include "PGMGst.h"
240	#include "PGMBth.h"
241	#undef BTH_PGMPOOLKIND_PT_FOR_PT
242	#undef PGM_BTH_NAME
243	#undef PGM_BTH_NAME_GC_STR
244	#undef PGM_BTH_NAME_R0_STR
245	#undef PGM_GST_TYPE
246	#undef PGM_GST_NAME
247	#undef PGM_GST_NAME_GC_STR
248	#undef PGM_GST_NAME_R0_STR
249
250	/* Guest - 32-bit mode */
251	#define PGM_GST_TYPE PGM_TYPE_32BIT
252	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
253	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
254	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
255	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
256	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
257	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
258	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
259	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
260	#include "PGMGst.h"
261	#include "PGMBth.h"
262	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
263	#undef BTH_PGMPOOLKIND_PT_FOR_PT
264	#undef PGM_BTH_NAME
265	#undef PGM_BTH_NAME_GC_STR
266	#undef PGM_BTH_NAME_R0_STR
267	#undef PGM_GST_TYPE
268	#undef PGM_GST_NAME
269	#undef PGM_GST_NAME_GC_STR
270	#undef PGM_GST_NAME_R0_STR
271
272	#undef PGM_SHW_TYPE
273	#undef PGM_SHW_NAME
274	#undef PGM_SHW_NAME_GC_STR
275	#undef PGM_SHW_NAME_R0_STR
276	#endif /* !RT_ARCH_AMD64 */
277
278
279	/*
280	* Shadow - PAE mode
281	*/
282	#define PGM_SHW_TYPE PGM_TYPE_PAE
283	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
284	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
285	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
286	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
287	#include "PGMShw.h"
288
289	/* Guest - real mode */
290	#define PGM_GST_TYPE PGM_TYPE_REAL
291	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
292	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
293	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
294	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
295	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
296	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
297	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
298	#include "PGMBth.h"
299	#undef BTH_PGMPOOLKIND_PT_FOR_PT
300	#undef PGM_BTH_NAME
301	#undef PGM_BTH_NAME_GC_STR
302	#undef PGM_BTH_NAME_R0_STR
303	#undef PGM_GST_TYPE
304	#undef PGM_GST_NAME
305	#undef PGM_GST_NAME_GC_STR
306	#undef PGM_GST_NAME_R0_STR
307
308	/* Guest - protected mode */
309	#define PGM_GST_TYPE PGM_TYPE_PROT
310	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
311	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
312	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
313	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
314	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
315	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
316	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
317	#include "PGMBth.h"
318	#undef BTH_PGMPOOLKIND_PT_FOR_PT
319	#undef PGM_BTH_NAME
320	#undef PGM_BTH_NAME_GC_STR
321	#undef PGM_BTH_NAME_R0_STR
322	#undef PGM_GST_TYPE
323	#undef PGM_GST_NAME
324	#undef PGM_GST_NAME_GC_STR
325	#undef PGM_GST_NAME_R0_STR
326
327	/* Guest - 32-bit mode */
328	#define PGM_GST_TYPE PGM_TYPE_32BIT
329	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
330	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
331	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
332	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
333	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
334	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
335	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
336	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
337	#include "PGMBth.h"
338	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
339	#undef BTH_PGMPOOLKIND_PT_FOR_PT
340	#undef PGM_BTH_NAME
341	#undef PGM_BTH_NAME_GC_STR
342	#undef PGM_BTH_NAME_R0_STR
343	#undef PGM_GST_TYPE
344	#undef PGM_GST_NAME
345	#undef PGM_GST_NAME_GC_STR
346	#undef PGM_GST_NAME_R0_STR
347
348	/* Guest - PAE mode */
349	#define PGM_GST_TYPE PGM_TYPE_PAE
350	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
351	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
352	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
353	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
354	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
355	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
356	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
357	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
358	#include "PGMGst.h"
359	#include "PGMBth.h"
360	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
361	#undef BTH_PGMPOOLKIND_PT_FOR_PT
362	#undef PGM_BTH_NAME
363	#undef PGM_BTH_NAME_GC_STR
364	#undef PGM_BTH_NAME_R0_STR
365	#undef PGM_GST_TYPE
366	#undef PGM_GST_NAME
367	#undef PGM_GST_NAME_GC_STR
368	#undef PGM_GST_NAME_R0_STR
369
370	#undef PGM_SHW_TYPE
371	#undef PGM_SHW_NAME
372	#undef PGM_SHW_NAME_GC_STR
373	#undef PGM_SHW_NAME_R0_STR
374
375
376	/*
377	* Shadow - AMD64 mode
378	*/
379	#define PGM_SHW_TYPE PGM_TYPE_AMD64
380	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
381	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
382	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
383	#include "PGMShw.h"
384
385	/* Guest - real mode */
386	#define PGM_GST_TYPE PGM_TYPE_REAL
387	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
388	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
389	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
390	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
391	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_REAL_STR(name)
392	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_REAL_STR(name)
393	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
394	#include "PGMBth.h"
395	#undef BTH_PGMPOOLKIND_PT_FOR_PT
396	#undef PGM_BTH_NAME
397	#undef PGM_BTH_NAME_GC_STR
398	#undef PGM_BTH_NAME_R0_STR
399	#undef PGM_GST_TYPE
400	#undef PGM_GST_NAME
401	#undef PGM_GST_NAME_GC_STR
402	#undef PGM_GST_NAME_R0_STR
403
404	/* Guest - protected mode */
405	#define PGM_GST_TYPE PGM_TYPE_PROT
406	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
407	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
408	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
409	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
410	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_PROT_STR(name)
411	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_PROT_STR(name)
412	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
413	#include "PGMBth.h"
414	#undef BTH_PGMPOOLKIND_PT_FOR_PT
415	#undef PGM_BTH_NAME
416	#undef PGM_BTH_NAME_GC_STR
417	#undef PGM_BTH_NAME_R0_STR
418	#undef PGM_GST_TYPE
419	#undef PGM_GST_NAME
420	#undef PGM_GST_NAME_GC_STR
421	#undef PGM_GST_NAME_R0_STR
422
423	/* Guest - AMD64 mode */
424	#define PGM_GST_TYPE PGM_TYPE_AMD64
425	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
426	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
427	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
428	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
429	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
430	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
431	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
432	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
433	#include "PGMGst.h"
434	#include "PGMBth.h"
435	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
436	#undef BTH_PGMPOOLKIND_PT_FOR_PT
437	#undef PGM_BTH_NAME
438	#undef PGM_BTH_NAME_GC_STR
439	#undef PGM_BTH_NAME_R0_STR
440	#undef PGM_GST_TYPE
441	#undef PGM_GST_NAME
442	#undef PGM_GST_NAME_GC_STR
443	#undef PGM_GST_NAME_R0_STR
444
445	#undef PGM_SHW_TYPE
446	#undef PGM_SHW_NAME
447	#undef PGM_SHW_NAME_GC_STR
448	#undef PGM_SHW_NAME_R0_STR
449
450
451	/**
452	* Initiates the paging of VM.
453	*
454	* @returns VBox status code.
455	* @param pVM Pointer to VM structure.
456	*/
457	PGMR3DECL(int) PGMR3Init(PVM pVM)
458	{
459	LogFlow(("PGMR3Init:\n"));
460
461	/*
462	* Assert alignment and sizes.
463	*/
464	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
465
466	/*
467	* Init the structure.
468	*/
469	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
470	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
471	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
472	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
473	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
474	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
475	pVM->pgm.s.fA20Enabled = true;
476	pVM->pgm.s.pGstPaePDPTRHC = NULL;
477	pVM->pgm.s.pGstPaePDPTRGC = 0;
478	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
479	{
480	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
481	pVM->pgm.s.apGstPaePDsGC[i] = 0;
482	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
483	}
484
485	#ifdef VBOX_STRICT
486	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
487	#endif
488
489	/*
490	* Get the configured RAM size - to estimate saved state size.
491	*/
492	uint64_t cbRam;
493	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
494	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
495	cbRam = pVM->pgm.s.cbRamSize = 0;
496	else if (VBOX_SUCCESS(rc))
497	{
498	if (cbRam < PAGE_SIZE)
499	cbRam = 0;
500	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
501	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
502	}
503	else
504	{
505	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
506	return rc;
507	}
508
509	/*
510	* Register saved state data unit.
511	*/
512	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
513	NULL, pgmR3Save, NULL,
514	NULL, pgmR3Load, NULL);
515	if (VBOX_FAILURE(rc))
516	return rc;
517
518	/* Initialise PGM critical section. */
519	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
520	AssertRCReturn(rc, rc);
521
522	/*
523	* Trees
524	*/
525	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
526	if (VBOX_SUCCESS(rc))
527	{
528	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
529
530	/*
531	* Init the paging.
532	*/
533	rc = pgmR3InitPaging(pVM);
534	}
535	if (VBOX_SUCCESS(rc))
536	{
537	/*
538	* Init the page pool.
539	*/
540	rc = pgmR3PoolInit(pVM);
541	}
542	if (VBOX_SUCCESS(rc))
543	{
544	/*
545	* Info & statistics
546	*/
547	DBGFR3InfoRegisterInternal(pVM, "mode",
548	"Shows the current paging mode. "
549	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
550	pgmR3InfoMode);
551	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
552	"Dumps all the entries in the top level paging table. No arguments.",
553	pgmR3InfoCr3);
554	DBGFR3InfoRegisterInternal(pVM, "phys",
555	"Dumps all the physical address ranges. No arguments.",
556	pgmR3PhysInfo);
557	DBGFR3InfoRegisterInternal(pVM, "handlers",
558	"Dumps physical and virtual handlers. "
559	"Pass 'phys' or 'virt' as argument if only one kind is wanted.",
560	pgmR3InfoHandlers);
561
562	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
563	#ifdef VBOX_WITH_STATISTICS
564	pgmR3InitStats(pVM);
565	#endif
566	#ifdef VBOX_WITH_DEBUGGER
567	/*
568	* Debugger commands.
569	*/
570	static bool fRegisteredCmds = false;
571	if (!fRegisteredCmds)
572	{
573	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
574	if (VBOX_SUCCESS(rc))
575	fRegisteredCmds = true;
576	}
577	#endif
578	return VINF_SUCCESS;
579	}
580	/* No cleanup necessary, MM frees all memory. */
581
582	return rc;
583	}
584
585
586	/**
587	* Init paging.
588	*
589	* Since we need to check what mode the host is operating in before we can choose
590	* the right paging functions for the host we have to delay this until R0 has
591	* been initialized.
592	*
593	* @returns VBox status code.
594	* @param pVM VM handle.
595	*/
596	static int pgmR3InitPaging(PVM pVM)
597	{
598	/*
599	* Force a recalculation of modes and switcher so everyone gets notified.
600	*/
601	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
602	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
603	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
604
605	/*
606	* Allocate static mapping space for whatever the cr3 register
607	* points to and in the case of PAE mode to the 4 PDs.
608	*/
609	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
610	if (VBOX_FAILURE(rc))
611	{
612	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
613	return rc;
614	}
615	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
616
617	/*
618	* Allocate pages for the three possible intermediate contexts
619	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
620	* for the sake of simplicity. The AMD64 uses the PAE for the
621	* lower levels, making the total number of pages 11 (3 + 7 + 1).
622	*
623	* We assume that two page tables will be enought for the core code
624	* mappings (HC virtual and identity).
625	*/
626	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
627	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
628	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
629	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
630	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
631	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
632	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
633	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
634	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
635	pVM->pgm.s.pInterPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
636	pVM->pgm.s.pInterPaePDPTR64 = (PX86PDPTR)MMR3PageAllocLow(pVM);
637	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
638	if ( !pVM->pgm.s.pInterPD
639	\|\| !pVM->pgm.s.apInterPTs[0]
640	\|\| !pVM->pgm.s.apInterPTs[1]
641	\|\| !pVM->pgm.s.apInterPaePTs[0]
642	\|\| !pVM->pgm.s.apInterPaePTs[1]
643	\|\| !pVM->pgm.s.apInterPaePDs[0]
644	\|\| !pVM->pgm.s.apInterPaePDs[1]
645	\|\| !pVM->pgm.s.apInterPaePDs[2]
646	\|\| !pVM->pgm.s.apInterPaePDs[3]
647	\|\| !pVM->pgm.s.pInterPaePDPTR
648	\|\| !pVM->pgm.s.pInterPaePDPTR64
649	\|\| !pVM->pgm.s.pInterPaePML4)
650	{
651	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
652	return VERR_NO_PAGE_MEMORY;
653	}
654
655	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
656	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
657	pVM->pgm.s.HCPhysInterPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR);
658	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPTR != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPTR & PAGE_OFFSET_MASK));
659	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
660	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
661
662	/*
663	* Initialize the pages, setting up the PML4 and PDPTR for repetitive 4GB action.
664	*/
665	ASMMemZeroPage(pVM->pgm.s.pInterPD);
666	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
667	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
668
669	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
670	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
671
672	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPTR);
673	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
674	{
675	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
676	pVM->pgm.s.pInterPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
677	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
678	}
679
680	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPTR64->a); i++)
681	{
682	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
683	pVM->pgm.s.pInterPaePDPTR64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
684	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
685	}
686
687	RTHCPHYS HCPhysInterPaePDPTR64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64);
688	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
689	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
690	\| HCPhysInterPaePDPTR64;
691
692	/*
693	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
694	* We allocate pages for all three posibilities to in order to simplify mappings and
695	* avoid resource failure during mode switches. So, we need to cover all levels of the
696	* of the first 4GB down to PD level.
697	* As with the intermediate context, AMD64 uses the PAE PDPTR and PDs.
698	*/
699	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
700	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
701	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
702	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
703	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
704	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
705	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
706	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
707	pVM->pgm.s.pHCPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
708	pVM->pgm.s.pHCPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
709	if ( !pVM->pgm.s.pHC32BitPD
710	\|\| !pVM->pgm.s.apHCPaePDs[0]
711	\|\| !pVM->pgm.s.apHCPaePDs[1]
712	\|\| !pVM->pgm.s.apHCPaePDs[2]
713	\|\| !pVM->pgm.s.apHCPaePDs[3]
714	\|\| !pVM->pgm.s.pHCPaePDPTR
715	\|\| !pVM->pgm.s.pHCPaePML4)
716	{
717	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
718	return VERR_NO_PAGE_MEMORY;
719	}
720
721	/* get physical addresses. */
722	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
723	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
724	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
725	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
726	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
727	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
728	pVM->pgm.s.HCPhysPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPTR);
729	pVM->pgm.s.HCPhysPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePML4);
730
731	/*
732	* Initialize the pages, setting up the PML4 and PDPTR for action below 4GB.
733	*/
734	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
735
736	ASMMemZero32(pVM->pgm.s.pHCPaePDPTR, PAGE_SIZE);
737	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
738	{
739	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
740	pVM->pgm.s.pHCPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
741	/* The flags will be corrected when entering and leaving long mode. */
742	}
743
744	ASMMemZero32(pVM->pgm.s.pHCPaePML4, PAGE_SIZE);
745	pVM->pgm.s.pHCPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_A
746	\| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.HCPhysPaePDPTR;
747
748	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
749
750	/*
751	* Initialize paging workers and mode from current host mode
752	* and the guest running in real mode.
753	*/
754	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
755	switch (pVM->pgm.s.enmHostMode)
756	{
757	case SUPPAGINGMODE_32_BIT:
758	case SUPPAGINGMODE_32_BIT_GLOBAL:
759	case SUPPAGINGMODE_PAE:
760	case SUPPAGINGMODE_PAE_GLOBAL:
761	case SUPPAGINGMODE_PAE_NX:
762	case SUPPAGINGMODE_PAE_GLOBAL_NX:
763	break;
764
765	case SUPPAGINGMODE_AMD64:
766	case SUPPAGINGMODE_AMD64_GLOBAL:
767	case SUPPAGINGMODE_AMD64_NX:
768	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
769	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
770	if (ARCH_BITS != 64)
771	{
772	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
773	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
774	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
775	}
776	#endif
777	break;
778	default:
779	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
780	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
781	}
782	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
783	if (VBOX_SUCCESS(rc))
784	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
785	if (VBOX_SUCCESS(rc))
786	{
787	LogFlow(("pgmR3InitPaging: returns successfully\n"));
788	#if HC_ARCH_BITS == 64
789	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPTR=%VHp HCPhysPaePML4=%VHp\n",
790	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
791	pVM->pgm.s.HCPhysPaePDPTR, pVM->pgm.s.HCPhysPaePML4));
792	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPTR=%VHp HCPhysInterPaePML4=%VHp\n",
793	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPTR, pVM->pgm.s.HCPhysInterPaePML4));
794	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPTR64=%VHp\n",
795	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
796	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
797	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
798	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64)));
799	#endif
800
801	return VINF_SUCCESS;
802	}
803
804	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
805	return rc;
806	}
807
808
809	#ifdef VBOX_WITH_STATISTICS
810	/**
811	* Init statistics
812	*/
813	static void pgmR3InitStats(PVM pVM)
814	{
815	PPGM pPGM = &pVM->pgm.s;
816	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
817	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
818	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
819	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
820	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
821	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
822	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
823	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
824	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
825	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
826	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
827	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
828	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
829	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
830	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
831	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
832	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
833	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
834	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
835	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
836	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
837	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
838
839	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
840	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
841	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
842	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
843	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
844	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
845	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
846	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
847	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
848	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
849	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
850	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
851	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
852	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
853	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
854	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
855	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
856	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
857	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
858
859	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
860	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
861	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
862	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
863	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
864	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
865	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
866
867	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
868	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
869	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
870	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
871	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
872	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
873
874	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
875	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
876	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
877	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
878	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
879	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
880
881
882	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
883	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
884	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
885
886	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
887	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
888
889	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
890	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
891
892	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
893	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
894
895	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
896	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
897	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
898
899	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
900	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
901	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
902	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
903	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
904	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
905	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
906	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
907	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
908	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
909	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
910
911	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
912	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
913	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
914	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
915	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
916	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
917	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
918
919	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
920	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
921	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
922	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
923
924	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
925	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
926	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
927	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
928	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
929
930	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
931	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
932	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
933	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
934	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
935	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
936	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
937	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
938	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
939	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
940	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
941	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
942
943	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
944	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
945	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
946	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
947	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
948	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
949	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
950	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
951	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
952	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
953	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
954	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
955
956	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
957	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
958	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
959
960	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
961	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
962
963	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
964	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
965	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
966	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
967
968	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
969	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
970
971	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
972	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
973	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
974	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
975	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
976	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
977	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
978	#endif
979
980	for (unsigned i = 0; i < PAGE_ENTRIES; i++)
981	{
982	/** @todo r=bird: We need a STAMR3RegisterF()! */
983	char szName[32];
984
985	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
986	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
987	AssertRC(rc);
988
989	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
990	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
991	AssertRC(rc);
992
993	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
994	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
995	AssertRC(rc);
996	}
997	}
998	#endif /* VBOX_WITH_STATISTICS */
999
1000	/**
1001	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1002	*
1003	* The dynamic mapping area will also be allocated and initialized at this
1004	* time. We could allocate it during PGMR3Init of course, but the mapping
1005	* wouldn't be allocated at that time preventing us from setting up the
1006	* page table entries with the dummy page.
1007	*
1008	* @returns VBox status code.
1009	* @param pVM VM handle.
1010	*/
1011	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1012	{
1013	/*
1014	* Reserve space for mapping the paging pages into guest context.
1015	*/
1016	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &pVM->pgm.s.pGC32BitPD);
1017	AssertRCReturn(rc, rc);
1018	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1019
1020	/*
1021	* Reserve space for the dynamic mappings.
1022	*/
1023	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1024	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &pVM->pgm.s.pbDynPageMapBaseGC);
1025	if ( VBOX_SUCCESS(rc)
1026	&& (pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT))
1027	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &pVM->pgm.s.pbDynPageMapBaseGC);
1028	if (VBOX_SUCCESS(rc))
1029	{
1030	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT));
1031	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1032	}
1033	return rc;
1034	}
1035
1036
1037	/**
1038	* Ring-3 init finalizing.
1039	*
1040	* @returns VBox status code.
1041	* @param pVM The VM handle.
1042	*/
1043	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1044	{
1045	/*
1046	* Map the paging pages into the guest context.
1047	*/
1048	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1049	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1050
1051	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1052	AssertRCReturn(rc, rc);
1053	pVM->pgm.s.pGC32BitPD = GCPtr;
1054	GCPtr += PAGE_SIZE;
1055	GCPtr += PAGE_SIZE; /* reserved page */
1056
1057	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1058	{
1059	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1060	AssertRCReturn(rc, rc);
1061	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1062	GCPtr += PAGE_SIZE;
1063	}
1064	/* A bit of paranoia is justified. */
1065	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1066	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1067	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1068	GCPtr += PAGE_SIZE; /* reserved page */
1069
1070	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPTR, PAGE_SIZE, 0);
1071	AssertRCReturn(rc, rc);
1072	pVM->pgm.s.pGCPaePDPTR = GCPtr;
1073	GCPtr += PAGE_SIZE;
1074	GCPtr += PAGE_SIZE; /* reserved page */
1075
1076	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePML4, PAGE_SIZE, 0);
1077	AssertRCReturn(rc, rc);
1078	pVM->pgm.s.pGCPaePML4 = GCPtr;
1079	GCPtr += PAGE_SIZE;
1080	GCPtr += PAGE_SIZE; /* reserved page */
1081
1082
1083	/*
1084	* Reserve space for the dynamic mappings.
1085	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1086	*/
1087	/* get the pointer to the page table entries. */
1088	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1089	AssertRelease(pMapping);
1090	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1091	const unsigned iPT = off >> X86_PD_SHIFT;
1092	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1093	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1094	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1095
1096	/* init cache */
1097	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1098	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1099	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1100
1101	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1102	{
1103	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1104	AssertRCReturn(rc, rc);
1105	}
1106
1107	return rc;
1108	}
1109
1110
1111	/**
1112	* Applies relocations to data and code managed by this
1113	* component. This function will be called at init and
1114	* whenever the VMM need to relocate it self inside the GC.
1115	*
1116	* @param pVM The VM.
1117	* @param offDelta Relocation delta relative to old location.
1118	*/
1119	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1120	{
1121	LogFlow(("PGMR3Relocate\n"));
1122
1123	/*
1124	* Paging stuff.
1125	*/
1126	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1127	/** @todo move this into shadow and guest specific relocation functions. */
1128	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1129	pVM->pgm.s.pGC32BitPD += offDelta;
1130	pVM->pgm.s.pGuestPDGC += offDelta;
1131	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1132	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1133	pVM->pgm.s.pGCPaePDPTR += offDelta;
1134	pVM->pgm.s.pGCPaePML4 += offDelta;
1135
1136	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1137	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1138
1139	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1140	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1141	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1142
1143	/*
1144	* Trees.
1145	*/
1146	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1147
1148	/*
1149	* Ram ranges.
1150	*/
1151	if (pVM->pgm.s.pRamRangesHC)
1152	{
1153	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesHC);
1154	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur->pNextHC; pCur = pCur->pNextHC)
1155	{
1156	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1157	if (pCur->pavHCChunkGC)
1158	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1159	}
1160	}
1161
1162	/*
1163	* Update the two page directories with all page table mappings.
1164	* (One or more of them have changed, that's why we're here.)
1165	*/
1166	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1167	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1168	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1169
1170	/* Relocate GC addresses of Page Tables. */
1171	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1172	{
1173	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1174	{
1175	pCur->aPTs[i].pPTGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].pPTR3);
1176	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].paPaePTsR3);
1177	}
1178	}
1179
1180	/*
1181	* Dynamic page mapping area.
1182	*/
1183	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1184	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1185	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1186
1187	/*
1188	* Physical and virtual handlers.
1189	*/
1190	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1191	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1192
1193	/*
1194	* The page pool.
1195	*/
1196	pgmR3PoolRelocate(pVM);
1197	}
1198
1199
1200	/**
1201	* Callback function for relocating a physical access handler.
1202	*
1203	* @returns 0 (continue enum)
1204	* @param pNode Pointer to a PGMPHYSHANDLER node.
1205	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1206	* not certain the delta will fit in a void pointer for all possible configs.
1207	*/
1208	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1209	{
1210	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1211	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1212	if (pHandler->pfnHandlerGC)
1213	pHandler->pfnHandlerGC += offDelta;
1214	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1215	pHandler->pvUserGC += offDelta;
1216	return 0;
1217	}
1218
1219
1220	/**
1221	* Callback function for relocating a virtual access handler.
1222	*
1223	* @returns 0 (continue enum)
1224	* @param pNode Pointer to a PGMVIRTHANDLER node.
1225	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1226	* not certain the delta will fit in a void pointer for all possible configs.
1227	*/
1228	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1229	{
1230	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1231	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1232	Assert(pHandler->pfnHandlerGC);
1233	pHandler->pfnHandlerGC += offDelta;
1234	return 0;
1235	}
1236
1237
1238	/**
1239	* The VM is being reset.
1240	*
1241	* For the PGM component this means that any PD write monitors
1242	* needs to be removed.
1243	*
1244	* @param pVM VM handle.
1245	*/
1246	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1247	{
1248	LogFlow(("PGMR3Reset:\n"));
1249	VM_ASSERT_EMT(pVM);
1250
1251	/*
1252	* Unfix any fixed mappings and disable CR3 monitoring.
1253	*/
1254	pVM->pgm.s.fMappingsFixed = false;
1255	pVM->pgm.s.GCPtrMappingFixed = 0;
1256	pVM->pgm.s.cbMappingFixed = 0;
1257
1258	int rc = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
1259	AssertRC(rc);
1260	#ifdef DEBUG
1261	PGMR3DumpMappings(pVM);
1262	#endif
1263
1264	/*
1265	* Reset the shadow page pool.
1266	*/
1267	pgmR3PoolReset(pVM);
1268
1269	/*
1270	* Re-init other members.
1271	*/
1272	pVM->pgm.s.fA20Enabled = true;
1273
1274	/*
1275	* Clear the FFs PGM owns.
1276	*/
1277	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1278	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1279
1280	/*
1281	* Zero memory.
1282	*/
1283	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
1284	{
1285	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1286	while (iPage-- > 0)
1287	{
1288	if (pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2))
1289	{
1290	Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO)));
1291	continue;
1292	}
1293	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1294	{
1295	unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1296	if (pRam->pavHCChunkHC[iChunk])
1297	ASMMemZero32((char *)pRam->pavHCChunkHC[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
1298	}
1299	else
1300	ASMMemZero32((char *)pRam->pvHC + (iPage << PAGE_SHIFT), PAGE_SIZE);
1301	}
1302	}
1303
1304	/*
1305	* Switch mode back to real mode.
1306	*/
1307	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1308	AssertReleaseRC(rc);
1309	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1310	}
1311
1312
1313	/**
1314	* Terminates the PGM.
1315	*
1316	* @returns VBox status code.
1317	* @param pVM Pointer to VM structure.
1318	*/
1319	PGMR3DECL(int) PGMR3Term(PVM pVM)
1320	{
1321	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1322	}
1323
1324
1325	#ifdef VBOX_STRICT
1326	/**
1327	* VM state change callback for clearing fNoMorePhysWrites after
1328	* a snapshot has been created.
1329	*/
1330	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
1331	{
1332	if (enmState == VMSTATE_RUNNING)
1333	pVM->pgm.s.fNoMorePhysWrites = false;
1334	}
1335	#endif
1336
1337
1338	/**
1339	* Execute state save operation.
1340	*
1341	* @returns VBox status code.
1342	* @param pVM VM Handle.
1343	* @param pSSM SSM operation handle.
1344	*/
1345	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1346	{
1347	PPGM pPGM = &pVM->pgm.s;
1348
1349	/* No more writes to physical memory after this point! */
1350	pVM->pgm.s.fNoMorePhysWrites = true;
1351
1352	/*
1353	* Save basic data (required / unaffected by relocation).
1354	*/
1355	#if 1
1356	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1357	#else
1358	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1359	#endif
1360	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1361	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1362	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1363	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1364	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1365	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1366	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1367	SSMR3PutU32(pSSM, ~0); /* Separator. */
1368
1369	/*
1370	* The guest mappings.
1371	*/
1372	uint32_t i = 0;
1373	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1374	{
1375	SSMR3PutU32(pSSM, i);
1376	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1377	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1378	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1379	/* flags are done by the mapping owners! */
1380	}
1381	SSMR3PutU32(pSSM, ~0); /* terminator. */
1382
1383	/*
1384	* Ram range flags and bits.
1385	*/
1386	i = 0;
1387	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1388	{
1389	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1390
1391	SSMR3PutU32(pSSM, i);
1392	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1393	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1394	SSMR3PutGCPhys(pSSM, pRam->cb);
1395	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
1396
1397	/* Flags. */
1398	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1399	for (unsigned iPage = 0; iPage < cPages; iPage++)
1400	SSMR3PutU16(pSSM, (uint16_t)(pRam->aHCPhys[iPage] & ~X86_PTE_PAE_PG_MASK));
1401
1402	/* any memory associated with the range. */
1403	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1404	{
1405	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1406	{
1407	if (pRam->pavHCChunkHC[iChunk])
1408	{
1409	SSMR3PutU8(pSSM, 1); /* chunk present */
1410	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1411	}
1412	else
1413	SSMR3PutU8(pSSM, 0); /* no chunk present */
1414	}
1415	}
1416	else if (pRam->pvHC)
1417	{
1418	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
1419	if (VBOX_FAILURE(rc))
1420	{
1421	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1422	return rc;
1423	}
1424	}
1425	}
1426	return SSMR3PutU32(pSSM, ~0); /* terminator. */
1427	}
1428
1429
1430	/**
1431	* Execute state load operation.
1432	*
1433	* @returns VBox status code.
1434	* @param pVM VM Handle.
1435	* @param pSSM SSM operation handle.
1436	* @param u32Version Data layout version.
1437	*/
1438	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1439	{
1440	/*
1441	* Validate version.
1442	*/
1443	if (u32Version != PGM_SAVED_STATE_VERSION)
1444	{
1445	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
1446	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1447	}
1448
1449	/*
1450	* Call the reset function to make sure all the memory is cleared.
1451	*/
1452	PGMR3Reset(pVM);
1453
1454	/*
1455	* Load basic data (required / unaffected by relocation).
1456	*/
1457	PPGM pPGM = &pVM->pgm.s;
1458	#if 1
1459	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
1460	#else
1461	uint32_t u;
1462	SSMR3GetU32(pSSM, &u);
1463	pPGM->fMappingsFixed = u;
1464	#endif
1465	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
1466	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
1467
1468	RTUINT cbRamSize;
1469	int rc = SSMR3GetU32(pSSM, &cbRamSize);
1470	if (VBOX_FAILURE(rc))
1471	return rc;
1472	if (cbRamSize != pPGM->cbRamSize)
1473	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
1474	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
1475	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
1476	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
1477	RTUINT uGuestMode;
1478	SSMR3GetUInt(pSSM, &uGuestMode);
1479	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
1480
1481	/* check separator. */
1482	uint32_t u32Sep;
1483	SSMR3GetU32(pSSM, &u32Sep);
1484	if (VBOX_FAILURE(rc))
1485	return rc;
1486	if (u32Sep != (uint32_t)~0)
1487	{
1488	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1489	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1490	}
1491
1492	/*
1493	* The guest mappings.
1494	*/
1495	uint32_t i = 0;
1496	for (;; i++)
1497	{
1498	/* Check the seqence number / separator. */
1499	rc = SSMR3GetU32(pSSM, &u32Sep);
1500	if (VBOX_FAILURE(rc))
1501	return rc;
1502	if (u32Sep == ~0U)
1503	break;
1504	if (u32Sep != i)
1505	{
1506	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1507	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1508	}
1509
1510	/* get the mapping details. */
1511	char szDesc[256];
1512	szDesc[0] = '\0';
1513	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
1514	if (VBOX_FAILURE(rc))
1515	return rc;
1516	RTGCPTR GCPtr;
1517	SSMR3GetGCPtr(pSSM, &GCPtr);
1518	RTGCUINTPTR cPTs;
1519	rc = SSMR3GetU32(pSSM, &cPTs);
1520	if (VBOX_FAILURE(rc))
1521	return rc;
1522
1523	/* find matching range. */
1524	PPGMMAPPING pMapping;
1525	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
1526	if ( pMapping->cPTs == cPTs
1527	&& !strcmp(pMapping->pszDesc, szDesc))
1528	break;
1529	if (!pMapping)
1530	{
1531	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
1532	cPTs, szDesc, GCPtr));
1533	AssertFailed();
1534	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1535	}
1536
1537	/* relocate it. */
1538	if (pMapping->GCPtr != GCPtr)
1539	{
1540	AssertMsg((GCPtr >> PGDIR_SHIFT << PGDIR_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
1541	#if HC_ARCH_BITS == 64
1542	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
1543	#endif
1544	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr >> PGDIR_SHIFT, GCPtr >> PGDIR_SHIFT);
1545	}
1546	else
1547	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
1548	}
1549
1550	/*
1551	* Ram range flags and bits.
1552	*/
1553	i = 0;
1554	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1555	{
1556	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1557	/* Check the seqence number / separator. */
1558	rc = SSMR3GetU32(pSSM, &u32Sep);
1559	if (VBOX_FAILURE(rc))
1560	return rc;
1561	if (u32Sep == ~0U)
1562	break;
1563	if (u32Sep != i)
1564	{
1565	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1566	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1567	}
1568
1569	/* Get the range details. */
1570	RTGCPHYS GCPhys;
1571	SSMR3GetGCPhys(pSSM, &GCPhys);
1572	RTGCPHYS GCPhysLast;
1573	SSMR3GetGCPhys(pSSM, &GCPhysLast);
1574	RTGCPHYS cb;
1575	SSMR3GetGCPhys(pSSM, &cb);
1576	uint8_t fHaveBits;
1577	rc = SSMR3GetU8(pSSM, &fHaveBits);
1578	if (VBOX_FAILURE(rc))
1579	return rc;
1580	if (fHaveBits & ~1)
1581	{
1582	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1583	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1584	}
1585
1586	/* Match it up with the current range. */
1587	if ( GCPhys != pRam->GCPhys
1588	\|\| GCPhysLast != pRam->GCPhysLast
1589	\|\| cb != pRam->cb
1590	\|\| fHaveBits != !!pRam->pvHC)
1591	{
1592	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
1593	"State : %VGp-%VGp %VGp bytes %s\n",
1594	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
1595	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
1596	AssertFailed();
1597	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1598	}
1599
1600	/* Flags. */
1601	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1602	for (unsigned iPage = 0; iPage < cPages; iPage++)
1603	{
1604	uint16_t u16 = 0;
1605	SSMR3GetU16(pSSM, &u16);
1606	u16 &= PAGE_OFFSET_MASK & ~( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
1607	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL
1608	\| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF );
1609	pRam->aHCPhys[iPage] = (pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK) \| (RTHCPHYS)u16;
1610	}
1611
1612	/* any memory associated with the range. */
1613	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1614	{
1615	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1616	{
1617	uint8_t fValidChunk;
1618
1619	rc = SSMR3GetU8(pSSM, &fValidChunk);
1620	if (VBOX_FAILURE(rc))
1621	return rc;
1622	if (fValidChunk > 1)
1623	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1624
1625	if (fValidChunk)
1626	{
1627	if (!pRam->pavHCChunkHC[iChunk])
1628	{
1629	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
1630	if (VBOX_FAILURE(rc))
1631	return rc;
1632	}
1633	Assert(pRam->pavHCChunkHC[iChunk]);
1634
1635	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1636	}
1637	/* else nothing to do */
1638	}
1639	}
1640	else if (pRam->pvHC)
1641	{
1642	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
1643	if (VBOX_FAILURE(rc))
1644	{
1645	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1646	return rc;
1647	}
1648	}
1649	}
1650
1651	/*
1652	* We require a full resync now.
1653	*/
1654	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1655	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1656	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
1657	pPGM->fPhysCacheFlushPending = true;
1658	pgmR3HandlerPhysicalUpdateAll(pVM);
1659
1660	/*
1661	* Change the paging mode.
1662	*/
1663	return pgmR3ChangeMode(pVM, pPGM->enmGuestMode);
1664	}
1665
1666
1667	/**
1668	* Show paging mode.
1669	*
1670	* @param pVM VM Handle.
1671	* @param pHlp The info helpers.
1672	* @param pszArgs "all" (default), "guest", "shadow" or "host".
1673	*/
1674	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1675	{
1676	/* digest argument. */
1677	bool fGuest, fShadow, fHost;
1678	if (pszArgs)
1679	pszArgs = RTStrStripL(pszArgs);
1680	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
1681	fShadow = fHost = fGuest = true;
1682	else
1683	{
1684	fShadow = fHost = fGuest = false;
1685	if (strstr(pszArgs, "guest"))
1686	fGuest = true;
1687	if (strstr(pszArgs, "shadow"))
1688	fShadow = true;
1689	if (strstr(pszArgs, "host"))
1690	fHost = true;
1691	}
1692
1693	/* print info. */
1694	if (fGuest)
1695	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
1696	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
1697	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
1698	if (fShadow)
1699	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
1700	if (fHost)
1701	{
1702	const char *psz;
1703	switch (pVM->pgm.s.enmHostMode)
1704	{
1705	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
1706	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
1707	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
1708	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
1709	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
1710	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
1711	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
1712	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
1713	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
1714	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
1715	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
1716	default: psz = "unknown"; break;
1717	}
1718	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
1719	}
1720	}
1721
1722
1723	/**
1724	* Dump registered MMIO ranges to the log.
1725	*
1726	* @param pVM VM Handle.
1727	* @param pHlp The info helpers.
1728	* @param pszArgs Arguments, ignored.
1729	*/
1730	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1731	{
1732	NOREF(pszArgs);
1733	pHlp->pfnPrintf(pHlp,
1734	"RAM ranges (pVM=%p)\n"
1735	"%.s %.s\n",
1736	pVM,
1737	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
1738	sizeof(RTHCPTR) * 2, "pvHC ");
1739
1740	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur; pCur = pCur->pNextHC)
1741	pHlp->pfnPrintf(pHlp,
1742	"%VGp-%VGp %VHv\n",
1743	pCur->GCPhys,
1744	pCur->GCPhysLast,
1745	pCur->pvHC);
1746	}
1747
1748	/**
1749	* Dump the page directory to the log.
1750	*
1751	* @param pVM VM Handle.
1752	* @param pHlp The info helpers.
1753	* @param pszArgs Arguments, ignored.
1754	*/
1755	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1756	{
1757	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
1758	/* Big pages supported? */
1759	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1760	/* Global pages supported? */
1761	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
1762
1763	NOREF(pszArgs);
1764
1765	/*
1766	* Get page directory addresses.
1767	*/
1768	PVBOXPD pPDSrc = pVM->pgm.s.pGuestPDHC;
1769	Assert(pPDSrc);
1770	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
1771
1772	/*
1773	* Iterate the page directory.
1774	*/
1775	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
1776	{
1777	VBOXPDE PdeSrc = pPDSrc->a[iPD];
1778	if (PdeSrc.n.u1Present)
1779	{
1780	if (PdeSrc.b.u1Size && fPSE)
1781	{
1782	pHlp->pfnPrintf(pHlp,
1783	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
1784	iPD,
1785	PdeSrc.u & X86_PDE_PG_MASK,
1786	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
1787	}
1788	else
1789	{
1790	pHlp->pfnPrintf(pHlp,
1791	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
1792	iPD,
1793	PdeSrc.u & X86_PDE4M_PG_MASK,
1794	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
1795	}
1796	}
1797	}
1798	}
1799
1800
1801	/**
1802	* Serivce a VMMCALLHOST_PGM_LOCK call.
1803	*
1804	* @returns VBox status code.
1805	* @param pVM The VM handle.
1806	*/
1807	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
1808	{
1809	return pgmLock(pVM);
1810	}
1811
1812
1813	/**
1814	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
1815	*
1816	* @returns PGM_TYPE_*.
1817	* @param pgmMode The mode value to convert.
1818	*/
1819	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
1820	{
1821	switch (pgmMode)
1822	{
1823	case PGMMODE_REAL: return PGM_TYPE_REAL;
1824	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
1825	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
1826	case PGMMODE_PAE:
1827	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
1828	case PGMMODE_AMD64:
1829	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
1830	default:
1831	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
1832	}
1833	}
1834
1835
1836	/**
1837	* Gets the index into the paging mode data array of a SHW+GST mode.
1838	*
1839	* @returns PGM::paPagingData index.
1840	* @param uShwType The shadow paging mode type.
1841	* @param uGstType The guest paging mode type.
1842	*/
1843	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
1844	{
1845	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_AMD64);
1846	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
1847	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_32BIT + 1)
1848	+ (uGstType - PGM_TYPE_REAL);
1849	}
1850
1851
1852	/**
1853	* Gets the index into the paging mode data array of a SHW+GST mode.
1854	*
1855	* @returns PGM::paPagingData index.
1856	* @param enmShw The shadow paging mode.
1857	* @param enmGst The guest paging mode.
1858	*/
1859	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
1860	{
1861	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
1862	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
1863	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
1864	}
1865
1866
1867	/**
1868	* Calculates the max data index.
1869	* @returns The number of entries in the pagaing data array.
1870	*/
1871	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
1872	{
1873	return pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64) + 1;
1874	}
1875
1876
1877	/**
1878	* Initializes the paging mode data kept in PGM::paModeData.
1879	*
1880	* @param pVM The VM handle.
1881	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
1882	* This is used early in the init process to avoid trouble with PDM
1883	* not being initialized yet.
1884	*/
1885	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
1886	{
1887	PPGMMODEDATA pModeData;
1888	int rc;
1889
1890	/*
1891	* Allocate the array on the first call.
1892	*/
1893	if (!pVM->pgm.s.paModeData)
1894	{
1895	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
1896	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
1897	}
1898
1899	/*
1900	* Initialize the array entries.
1901	*/
1902	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
1903	pModeData->uShwType = PGM_TYPE_32BIT;
1904	pModeData->uGstType = PGM_TYPE_REAL;
1905	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1906	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1907	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1908
1909	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
1910	pModeData->uShwType = PGM_TYPE_32BIT;
1911	pModeData->uGstType = PGM_TYPE_PROT;
1912	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1913	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1914	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1915
1916	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
1917	pModeData->uShwType = PGM_TYPE_32BIT;
1918	pModeData->uGstType = PGM_TYPE_32BIT;
1919	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1920	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1921	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1922
1923	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
1924	pModeData->uShwType = PGM_TYPE_PAE;
1925	pModeData->uGstType = PGM_TYPE_REAL;
1926	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1927	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1928	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1929
1930	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
1931	pModeData->uShwType = PGM_TYPE_PAE;
1932	pModeData->uGstType = PGM_TYPE_PROT;
1933	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1934	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1935	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1936
1937	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
1938	pModeData->uShwType = PGM_TYPE_PAE;
1939	pModeData->uGstType = PGM_TYPE_32BIT;
1940	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1941	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1942	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1943
1944	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
1945	pModeData->uShwType = PGM_TYPE_PAE;
1946	pModeData->uGstType = PGM_TYPE_PAE;
1947	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1948	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1949	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1950
1951	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_REAL)];
1952	pModeData->uShwType = PGM_TYPE_AMD64;
1953	pModeData->uGstType = PGM_TYPE_REAL;
1954	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1955	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1956	rc = PGM_BTH_NAME_AMD64_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1957
1958	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_PROT)];
1959	pModeData->uShwType = PGM_TYPE_AMD64;
1960	pModeData->uGstType = PGM_TYPE_PROT;
1961	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1962	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1963	rc = PGM_BTH_NAME_AMD64_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1964
1965	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
1966	pModeData->uShwType = PGM_TYPE_AMD64;
1967	pModeData->uGstType = PGM_TYPE_AMD64;
1968	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1969	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1970	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1971
1972	return VINF_SUCCESS;
1973	}
1974
1975
1976	/**
1977	* Swtich to different (or relocated in the relocate case) mode data.
1978	*
1979	* @param pVM The VM handle.
1980	* @param enmShw The the shadow paging mode.
1981	* @param enmGst The the guest paging mode.
1982	*/
1983	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
1984	{
1985	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(enmShw, enmGst)];
1986
1987	Assert(pModeData->uGstType == pgmModeToType(enmGst));
1988	Assert(pModeData->uShwType == pgmModeToType(enmShw));
1989
1990	/* shadow */
1991	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
1992	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
1993	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
1994	Assert(pVM->pgm.s.pfnR3ShwGetPage);
1995	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
1996	pVM->pgm.s.pfnR3ShwGetPDEByIndex = pModeData->pfnR3ShwGetPDEByIndex;
1997	pVM->pgm.s.pfnR3ShwSetPDEByIndex = pModeData->pfnR3ShwSetPDEByIndex;
1998	pVM->pgm.s.pfnR3ShwModifyPDEByIndex = pModeData->pfnR3ShwModifyPDEByIndex;
1999
2000	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2001	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2002	pVM->pgm.s.pfnGCShwGetPDEByIndex = pModeData->pfnGCShwGetPDEByIndex;
2003	pVM->pgm.s.pfnGCShwSetPDEByIndex = pModeData->pfnGCShwSetPDEByIndex;
2004	pVM->pgm.s.pfnGCShwModifyPDEByIndex = pModeData->pfnGCShwModifyPDEByIndex;
2005
2006	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2007	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2008	pVM->pgm.s.pfnR0ShwGetPDEByIndex = pModeData->pfnR0ShwGetPDEByIndex;
2009	pVM->pgm.s.pfnR0ShwSetPDEByIndex = pModeData->pfnR0ShwSetPDEByIndex;
2010	pVM->pgm.s.pfnR0ShwModifyPDEByIndex = pModeData->pfnR0ShwModifyPDEByIndex;
2011
2012
2013	/* guest */
2014	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2015	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2016	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2017	Assert(pVM->pgm.s.pfnR3GstGetPage);
2018	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2019	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2020	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2021	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2022	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2023	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2024	pVM->pgm.s.pfnHCGstWriteHandlerCR3 = pModeData->pfnHCGstWriteHandlerCR3;
2025	pVM->pgm.s.pszHCGstWriteHandlerCR3 = pModeData->pszHCGstWriteHandlerCR3;
2026
2027	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2028	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2029	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2030	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2031	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2032	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2033	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2034	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2035
2036	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2037	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2038	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2039	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2040	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2041	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2042	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2043	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2044
2045
2046	/* both */
2047	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2048	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2049	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2050	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2051	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2052	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2053	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2054	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2055	#ifdef VBOX_STRICT
2056	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2057	#endif
2058
2059	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2060	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2061	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2062	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2063	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2064	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2065	#ifdef VBOX_STRICT
2066	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2067	#endif
2068
2069	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2070	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2071	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2072	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2073	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2074	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2075	#ifdef VBOX_STRICT
2076	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2077	#endif
2078	}
2079
2080
2081	#ifdef DEBUG_bird
2082	#include <stdlib.h> /* getenv() remove me! */
2083	#endif
2084
2085	/**
2086	* Calculates the shadow paging mode.
2087	*
2088	* @returns The shadow paging mode.
2089	* @param enmGuestMode The guest mode.
2090	* @param enmHostMode The host mode.
2091	* @param enmShadowMode The current shadow mode.
2092	* @param penmSwitcher Where to store the switcher to use.
2093	* VMMSWITCHER_INVALID means no change.
2094	*/
2095	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2096	{
2097	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2098	switch (enmGuestMode)
2099	{
2100	/*
2101	* When switching to real or protected mode we don't change
2102	* anything since it's likely that we'll switch back pretty soon.
2103	*
2104	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2105	* and is supposed to determin which shadow paging and switcher to
2106	* use during init.
2107	*/
2108	case PGMMODE_REAL:
2109	case PGMMODE_PROTECTED:
2110	if (enmShadowMode != PGMMODE_INVALID)
2111	break; /* (no change) */
2112	switch (enmHostMode)
2113	{
2114	case SUPPAGINGMODE_32_BIT:
2115	case SUPPAGINGMODE_32_BIT_GLOBAL:
2116	enmShadowMode = PGMMODE_32_BIT;
2117	enmSwitcher = VMMSWITCHER_32_TO_32;
2118	break;
2119
2120	case SUPPAGINGMODE_PAE:
2121	case SUPPAGINGMODE_PAE_NX:
2122	case SUPPAGINGMODE_PAE_GLOBAL:
2123	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2124	enmShadowMode = PGMMODE_PAE;
2125	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2126	#ifdef DEBUG_bird
2127	if (getenv("VBOX_32BIT"))
2128	{
2129	enmShadowMode = PGMMODE_32_BIT;
2130	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2131	}
2132	#endif
2133	break;
2134
2135	case SUPPAGINGMODE_AMD64:
2136	case SUPPAGINGMODE_AMD64_GLOBAL:
2137	case SUPPAGINGMODE_AMD64_NX:
2138	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2139	enmShadowMode = PGMMODE_PAE;
2140	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2141	break;
2142
2143	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2144	}
2145	break;
2146
2147	case PGMMODE_32_BIT:
2148	switch (enmHostMode)
2149	{
2150	case SUPPAGINGMODE_32_BIT:
2151	case SUPPAGINGMODE_32_BIT_GLOBAL:
2152	enmShadowMode = PGMMODE_32_BIT;
2153	enmSwitcher = VMMSWITCHER_32_TO_32;
2154	break;
2155
2156	case SUPPAGINGMODE_PAE:
2157	case SUPPAGINGMODE_PAE_NX:
2158	case SUPPAGINGMODE_PAE_GLOBAL:
2159	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2160	enmShadowMode = PGMMODE_PAE;
2161	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2162	#ifdef DEBUG_bird
2163	if (getenv("VBOX_32BIT"))
2164	{
2165	enmShadowMode = PGMMODE_32_BIT;
2166	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2167	}
2168	#endif
2169	break;
2170
2171	case SUPPAGINGMODE_AMD64:
2172	case SUPPAGINGMODE_AMD64_GLOBAL:
2173	case SUPPAGINGMODE_AMD64_NX:
2174	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2175	enmShadowMode = PGMMODE_PAE;
2176	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2177	break;
2178
2179	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2180	}
2181	break;
2182
2183	case PGMMODE_PAE:
2184	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2185	switch (enmHostMode)
2186	{
2187	case SUPPAGINGMODE_32_BIT:
2188	case SUPPAGINGMODE_32_BIT_GLOBAL:
2189	enmShadowMode = PGMMODE_PAE;
2190	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2191	break;
2192
2193	case SUPPAGINGMODE_PAE:
2194	case SUPPAGINGMODE_PAE_NX:
2195	case SUPPAGINGMODE_PAE_GLOBAL:
2196	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2197	enmShadowMode = PGMMODE_PAE;
2198	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2199	break;
2200
2201	case SUPPAGINGMODE_AMD64:
2202	case SUPPAGINGMODE_AMD64_GLOBAL:
2203	case SUPPAGINGMODE_AMD64_NX:
2204	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2205	enmShadowMode = PGMMODE_PAE;
2206	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2207	break;
2208
2209	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2210	}
2211	break;
2212
2213	case PGMMODE_AMD64:
2214	case PGMMODE_AMD64_NX:
2215	switch (enmHostMode)
2216	{
2217	case SUPPAGINGMODE_32_BIT:
2218	case SUPPAGINGMODE_32_BIT_GLOBAL:
2219	enmShadowMode = PGMMODE_PAE;
2220	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2221	break;
2222
2223	case SUPPAGINGMODE_PAE:
2224	case SUPPAGINGMODE_PAE_NX:
2225	case SUPPAGINGMODE_PAE_GLOBAL:
2226	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2227	enmShadowMode = PGMMODE_PAE;
2228	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2229	break;
2230
2231	case SUPPAGINGMODE_AMD64:
2232	case SUPPAGINGMODE_AMD64_GLOBAL:
2233	case SUPPAGINGMODE_AMD64_NX:
2234	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2235	enmShadowMode = PGMMODE_PAE;
2236	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2237	break;
2238
2239	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2240	}
2241	break;
2242
2243
2244	default:
2245	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2246	return PGMMODE_INVALID;
2247	}
2248
2249	*penmSwitcher = enmSwitcher;
2250	return enmShadowMode;
2251	}
2252
2253
2254	/**
2255	* Performs the actual mode change.
2256	* This is called by PGMChangeMode and pgmR3InitPaging().
2257	*
2258	* @returns VBox status code.
2259	* @param pVM VM handle.
2260	* @param enmGuestMode The new guest mode. This is assumed to be different from
2261	* the current mode.
2262	*/
2263	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
2264	{
2265	LogFlow(("pgmR3ChangeMode: Guest mode: %d -> %d\n", pVM->pgm.s.enmGuestMode, enmGuestMode));
2266	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
2267
2268	/*
2269	* Calc the shadow mode and switcher.
2270	*/
2271	VMMSWITCHER enmSwitcher;
2272	PGMMODE enmShadowMode = pgmR3CalcShadowMode(enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
2273	if (enmSwitcher != VMMSWITCHER_INVALID)
2274	{
2275	/*
2276	* Select new switcher.
2277	*/
2278	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
2279	if (VBOX_FAILURE(rc))
2280	{
2281	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
2282	return rc;
2283	}
2284	}
2285
2286	/*
2287	* Exit old mode(s).
2288	*/
2289	/* shadow */
2290	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2291	{
2292	LogFlow(("pgmR3ChangeMode: Shadow mode: %d -> %d\n", pVM->pgm.s.enmShadowMode, enmShadowMode));
2293	if (PGM_SHW_PFN(Exit, pVM))
2294	{
2295	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
2296	if (VBOX_FAILURE(rc))
2297	{
2298	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
2299	return rc;
2300	}
2301	}
2302
2303	}
2304
2305	/* guest */
2306	if (PGM_GST_PFN(Exit, pVM))
2307	{
2308	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2309	if (VBOX_FAILURE(rc))
2310	{
2311	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
2312	return rc;
2313	}
2314	}
2315
2316	/*
2317	* Load new paging mode data.
2318	*/
2319	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
2320
2321	/*
2322	* Enter new shadow mode (if changed).
2323	*/
2324	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2325	{
2326	int rc;
2327	pVM->pgm.s.enmShadowMode = enmShadowMode;
2328	switch (enmShadowMode)
2329	{
2330	case PGMMODE_32_BIT:
2331	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
2332	break;
2333	case PGMMODE_PAE:
2334	case PGMMODE_PAE_NX:
2335	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
2336	break;
2337	case PGMMODE_AMD64:
2338	case PGMMODE_AMD64_NX:
2339	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
2340	break;
2341	case PGMMODE_REAL:
2342	case PGMMODE_PROTECTED:
2343	default:
2344	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
2345	return VERR_INTERNAL_ERROR;
2346	}
2347	if (VBOX_FAILURE(rc))
2348	{
2349	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
2350	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
2351	return rc;
2352	}
2353	}
2354
2355	/*
2356	* Enter the new guest and shadow+guest modes.
2357	*/
2358	int rc = -1;
2359	int rc2 = -1;
2360	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
2361	pVM->pgm.s.enmGuestMode = enmGuestMode;
2362	switch (enmGuestMode)
2363	{
2364	case PGMMODE_REAL:
2365	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
2366	switch (pVM->pgm.s.enmShadowMode)
2367	{
2368	case PGMMODE_32_BIT:
2369	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
2370	break;
2371	case PGMMODE_PAE:
2372	case PGMMODE_PAE_NX:
2373	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
2374	break;
2375	case PGMMODE_AMD64:
2376	case PGMMODE_AMD64_NX:
2377	rc2 = PGM_BTH_NAME_AMD64_REAL(Enter)(pVM, NIL_RTGCPHYS);
2378	break;
2379	default: AssertFailed(); break;
2380	}
2381	break;
2382
2383	case PGMMODE_PROTECTED:
2384	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
2385	switch (pVM->pgm.s.enmShadowMode)
2386	{
2387	case PGMMODE_32_BIT:
2388	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
2389	break;
2390	case PGMMODE_PAE:
2391	case PGMMODE_PAE_NX:
2392	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
2393	break;
2394	case PGMMODE_AMD64:
2395	case PGMMODE_AMD64_NX:
2396	rc2 = PGM_BTH_NAME_AMD64_PROT(Enter)(pVM, NIL_RTGCPHYS);
2397	break;
2398	default: AssertFailed(); break;
2399	}
2400	break;
2401
2402	case PGMMODE_32_BIT:
2403	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
2404	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
2405	switch (pVM->pgm.s.enmShadowMode)
2406	{
2407	case PGMMODE_32_BIT:
2408	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
2409	break;
2410	case PGMMODE_PAE:
2411	case PGMMODE_PAE_NX:
2412	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
2413	break;
2414	case PGMMODE_AMD64:
2415	case PGMMODE_AMD64_NX:
2416	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2417	default: AssertFailed(); break;
2418	}
2419	break;
2420
2421	//case PGMMODE_PAE_NX:
2422	case PGMMODE_PAE:
2423	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
2424	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
2425	switch (pVM->pgm.s.enmShadowMode)
2426	{
2427	case PGMMODE_PAE:
2428	case PGMMODE_PAE_NX:
2429	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
2430	break;
2431	case PGMMODE_32_BIT:
2432	case PGMMODE_AMD64:
2433	case PGMMODE_AMD64_NX:
2434	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2435	default: AssertFailed(); break;
2436	}
2437	break;
2438
2439	//case PGMMODE_AMD64_NX:
2440	case PGMMODE_AMD64:
2441	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask and make CR3 64-bit in this case! */
2442	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
2443	switch (pVM->pgm.s.enmShadowMode)
2444	{
2445	case PGMMODE_AMD64:
2446	case PGMMODE_AMD64_NX:
2447	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
2448	break;
2449	case PGMMODE_32_BIT:
2450	case PGMMODE_PAE:
2451	case PGMMODE_PAE_NX:
2452	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
2453	default: AssertFailed(); break;
2454	}
2455	break;
2456
2457	default:
2458	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2459	rc = VERR_NOT_IMPLEMENTED;
2460	break;
2461	}
2462
2463	/* status codes. */
2464	AssertRC(rc);
2465	AssertRC(rc2);
2466	if (VBOX_SUCCESS(rc))
2467	{
2468	rc = rc2;
2469	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
2470	rc = VINF_SUCCESS;
2471	}
2472
2473	/*
2474	* Notify SELM so it can update the TSSes with correct CR3s.
2475	*/
2476	SELMR3PagingModeChanged(pVM);
2477
2478	/* Notify HWACCM as well. */
2479	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
2480	return rc;
2481	}
2482
2483
2484	/**
2485	* Dumps a PAE shadow page table.
2486	*
2487	* @returns VBox status code (VINF_SUCCESS).
2488	* @param pVM The VM handle.
2489	* @param pPT Pointer to the page table.
2490	* @param u64Address The virtual address of the page table starts.
2491	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2492	* @param cMaxDepth The maxium depth.
2493	* @param pHlp Pointer to the output functions.
2494	*/
2495	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2496	{
2497	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2498	{
2499	X86PTEPAE Pte = pPT->a[i];
2500	if (Pte.n.u1Present)
2501	{
2502	pHlp->pfnPrintf(pHlp,
2503	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2504	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
2505	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
2506	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
2507	Pte.n.u1Write ? 'W' : 'R',
2508	Pte.n.u1User ? 'U' : 'S',
2509	Pte.n.u1Accessed ? 'A' : '-',
2510	Pte.n.u1Dirty ? 'D' : '-',
2511	Pte.n.u1Global ? 'G' : '-',
2512	Pte.n.u1WriteThru ? "WT" : "--",
2513	Pte.n.u1CacheDisable? "CD" : "--",
2514	Pte.n.u1PAT ? "AT" : "--",
2515	Pte.n.u1NoExecute ? "NX" : "--",
2516	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2517	Pte.u & BIT(10) ? '1' : '0',
2518	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
2519	Pte.u & X86_PTE_PAE_PG_MASK);
2520	}
2521	}
2522	return VINF_SUCCESS;
2523	}
2524
2525
2526	/**
2527	* Dumps a PAE shadow page directory table.
2528	*
2529	* @returns VBox status code (VINF_SUCCESS).
2530	* @param pVM The VM handle.
2531	* @param HCPhys The physical address of the page directory table.
2532	* @param u64Address The virtual address of the page table starts.
2533	* @param cr4 The CR4, PSE is currently used.
2534	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2535	* @param cMaxDepth The maxium depth.
2536	* @param pHlp Pointer to the output functions.
2537	*/
2538	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2539	{
2540	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
2541	if (!pPD)
2542	{
2543	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
2544	fLongMode ? 16 : 8, u64Address, HCPhys);
2545	return VERR_INVALID_PARAMETER;
2546	}
2547	int rc = VINF_SUCCESS;
2548	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2549	{
2550	X86PDEPAE Pde = pPD->a[i];
2551	if (Pde.n.u1Present)
2552	{
2553	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2554	pHlp->pfnPrintf(pHlp,
2555	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2556	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
2557	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
2558	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2559	Pde.b.u1Write ? 'W' : 'R',
2560	Pde.b.u1User ? 'U' : 'S',
2561	Pde.b.u1Accessed ? 'A' : '-',
2562	Pde.b.u1Dirty ? 'D' : '-',
2563	Pde.b.u1Global ? 'G' : '-',
2564	Pde.b.u1WriteThru ? "WT" : "--",
2565	Pde.b.u1CacheDisable? "CD" : "--",
2566	Pde.b.u1PAT ? "AT" : "--",
2567	Pde.b.u1NoExecute ? "NX" : "--",
2568	Pde.u & BIT64(9) ? '1' : '0',
2569	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2570	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2571	Pde.u & X86_PDE_PAE_PG_MASK);
2572	else
2573	{
2574	pHlp->pfnPrintf(pHlp,
2575	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2576	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
2577	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
2578	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2579	Pde.n.u1Write ? 'W' : 'R',
2580	Pde.n.u1User ? 'U' : 'S',
2581	Pde.n.u1Accessed ? 'A' : '-',
2582	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2583	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2584	Pde.n.u1WriteThru ? "WT" : "--",
2585	Pde.n.u1CacheDisable? "CD" : "--",
2586	Pde.n.u1NoExecute ? "NX" : "--",
2587	Pde.u & BIT64(9) ? '1' : '0',
2588	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2589	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2590	Pde.u & X86_PDE_PAE_PG_MASK);
2591	if (cMaxDepth >= 1)
2592	{
2593	/** @todo what about using the page pool for mapping PTs? */
2594	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
2595	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
2596	PX86PTPAE pPT = NULL;
2597	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2598	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
2599	else
2600	{
2601	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
2602	{
2603	uint64_t off = u64AddressPT - pMap->GCPtr;
2604	if (off < pMap->cb)
2605	{
2606	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
2607	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
2608	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
2609	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2610	fLongMode ? 16 : 8, u64AddressPT, iPDE,
2611	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
2612	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
2613	}
2614	}
2615	}
2616	int rc2 = VERR_INVALID_PARAMETER;
2617	if (pPT)
2618	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
2619	else
2620	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
2621	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
2622	if (rc2 < rc && VBOX_SUCCESS(rc))
2623	rc = rc2;
2624	}
2625	}
2626	}
2627	}
2628	return rc;
2629	}
2630
2631
2632	/**
2633	* Dumps a PAE shadow page directory pointer table.
2634	*
2635	* @returns VBox status code (VINF_SUCCESS).
2636	* @param pVM The VM handle.
2637	* @param HCPhys The physical address of the page directory pointer table.
2638	* @param u64Address The virtual address of the page table starts.
2639	* @param cr4 The CR4, PSE is currently used.
2640	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2641	* @param cMaxDepth The maxium depth.
2642	* @param pHlp Pointer to the output functions.
2643	*/
2644	static int pgmR3DumpHierarchyHCPaePDPTR(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2645	{
2646	PX86PDPTR pPDPTR = (PX86PDPTR)MMPagePhys2Page(pVM, HCPhys);
2647	if (!pPDPTR)
2648	{
2649	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
2650	fLongMode ? 16 : 8, u64Address, HCPhys);
2651	return VERR_INVALID_PARAMETER;
2652	}
2653
2654	int rc = VINF_SUCCESS;
2655	const unsigned c = fLongMode ? ELEMENTS(pPDPTR->a) : 4;
2656	for (unsigned i = 0; i < c; i++)
2657	{
2658	X86PDPE Pdpe = pPDPTR->a[i];
2659	if (Pdpe.n.u1Present)
2660	{
2661	if (fLongMode)
2662	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2663	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2664	u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2665	Pdpe.n.u1Write ? 'W' : 'R',
2666	Pdpe.n.u1User ? 'U' : 'S',
2667	Pdpe.n.u1Accessed ? 'A' : '-',
2668	Pdpe.n.u3Reserved & 1? '?' : '.', /* ignored */
2669	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2670	Pdpe.n.u1WriteThru ? "WT" : "--",
2671	Pdpe.n.u1CacheDisable? "CD" : "--",
2672	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2673	Pdpe.n.u1NoExecute ? "NX" : "--",
2674	Pdpe.u & BIT(9) ? '1' : '0',
2675	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2676	Pdpe.u & BIT(11) ? '1' : '0',
2677	Pdpe.u & X86_PDPE_PG_MASK);
2678	else
2679	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2680	"%08x 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2681	i << X86_PDPTR_SHIFT,
2682	Pdpe.n.u1Write ? '!' : '.', /* mbz */
2683	Pdpe.n.u1User ? '!' : '.', /* mbz */
2684	Pdpe.n.u1Accessed ? '!' : '.', /* mbz */
2685	Pdpe.n.u3Reserved & 1? '!' : '.', /* mbz */
2686	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2687	Pdpe.n.u1WriteThru ? "WT" : "--",
2688	Pdpe.n.u1CacheDisable? "CD" : "--",
2689	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2690	Pdpe.n.u1NoExecute ? "NX" : "--",
2691	Pdpe.u & BIT(9) ? '1' : '0',
2692	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2693	Pdpe.u & BIT(11) ? '1' : '0',
2694	Pdpe.u & X86_PDPE_PG_MASK);
2695	if (cMaxDepth >= 1)
2696	{
2697	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2698	cr4, fLongMode, cMaxDepth - 1, pHlp);
2699	if (rc2 < rc && VBOX_SUCCESS(rc))
2700	rc = rc2;
2701	}
2702	}
2703	}
2704	return rc;
2705	}
2706
2707
2708	/**
2709	* Dumps a 32-bit shadow page table.
2710	*
2711	* @returns VBox status code (VINF_SUCCESS).
2712	* @param pVM The VM handle.
2713	* @param HCPhys The physical address of the table.
2714	* @param cr4 The CR4, PSE is currently used.
2715	* @param cMaxDepth The maxium depth.
2716	* @param pHlp Pointer to the output functions.
2717	*/
2718	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2719	{
2720	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
2721	if (!pPML4)
2722	{
2723	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
2724	return VERR_INVALID_PARAMETER;
2725	}
2726
2727	int rc = VINF_SUCCESS;
2728	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
2729	{
2730	X86PML4E Pml4e = pPML4->a[i];
2731	if (Pml4e.n.u1Present)
2732	{
2733	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPTR_SHIFT - 1)) * 0xffff000000000000ULL);
2734	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2735	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2736	u64Address,
2737	Pml4e.n.u1Write ? 'W' : 'R',
2738	Pml4e.n.u1User ? 'U' : 'S',
2739	Pml4e.n.u1Accessed ? 'A' : '-',
2740	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
2741	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
2742	Pml4e.n.u1WriteThru ? "WT" : "--",
2743	Pml4e.n.u1CacheDisable? "CD" : "--",
2744	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
2745	Pml4e.n.u1NoExecute ? "NX" : "--",
2746	Pml4e.u & BIT(9) ? '1' : '0',
2747	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2748	Pml4e.u & BIT(11) ? '1' : '0',
2749	Pml4e.u & X86_PML4E_PG_MASK);
2750
2751	if (cMaxDepth >= 1)
2752	{
2753	int rc2 = pgmR3DumpHierarchyHCPaePDPTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
2754	if (rc2 < rc && VBOX_SUCCESS(rc))
2755	rc = rc2;
2756	}
2757	}
2758	}
2759	return rc;
2760	}
2761
2762
2763	/**
2764	* Dumps a 32-bit shadow page table.
2765	*
2766	* @returns VBox status code (VINF_SUCCESS).
2767	* @param pVM The VM handle.
2768	* @param pPT Pointer to the page table.
2769	* @param u32Address The virtual address this table starts at.
2770	* @param pHlp Pointer to the output functions.
2771	*/
2772	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
2773	{
2774	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2775	{
2776	X86PTE Pte = pPT->a[i];
2777	if (Pte.n.u1Present)
2778	{
2779	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2780	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2781	u32Address + (i << X86_PT_SHIFT),
2782	Pte.n.u1Write ? 'W' : 'R',
2783	Pte.n.u1User ? 'U' : 'S',
2784	Pte.n.u1Accessed ? 'A' : '-',
2785	Pte.n.u1Dirty ? 'D' : '-',
2786	Pte.n.u1Global ? 'G' : '-',
2787	Pte.n.u1WriteThru ? "WT" : "--",
2788	Pte.n.u1CacheDisable? "CD" : "--",
2789	Pte.n.u1PAT ? "AT" : "--",
2790	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2791	Pte.u & BIT(10) ? '1' : '0',
2792	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2793	Pte.u & X86_PDE_PG_MASK);
2794	}
2795	}
2796	return VINF_SUCCESS;
2797	}
2798
2799
2800	/**
2801	* Dumps a 32-bit shadow page directory and page tables.
2802	*
2803	* @returns VBox status code (VINF_SUCCESS).
2804	* @param pVM The VM handle.
2805	* @param cr3 The root of the hierarchy.
2806	* @param cr4 The CR4, PSE is currently used.
2807	* @param cMaxDepth How deep into the hierarchy the dumper should go.
2808	* @param pHlp Pointer to the output functions.
2809	*/
2810	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2811	{
2812	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
2813	if (!pPD)
2814	{
2815	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
2816	return VERR_INVALID_PARAMETER;
2817	}
2818
2819	int rc = VINF_SUCCESS;
2820	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2821	{
2822	X86PDE Pde = pPD->a[i];
2823	if (Pde.n.u1Present)
2824	{
2825	const uint32_t u32Address = i << X86_PD_SHIFT;
2826	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2827	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2828	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2829	u32Address,
2830	Pde.b.u1Write ? 'W' : 'R',
2831	Pde.b.u1User ? 'U' : 'S',
2832	Pde.b.u1Accessed ? 'A' : '-',
2833	Pde.b.u1Dirty ? 'D' : '-',
2834	Pde.b.u1Global ? 'G' : '-',
2835	Pde.b.u1WriteThru ? "WT" : "--",
2836	Pde.b.u1CacheDisable? "CD" : "--",
2837	Pde.b.u1PAT ? "AT" : "--",
2838	Pde.u & BIT64(9) ? '1' : '0',
2839	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2840	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2841	Pde.u & X86_PDE4M_PG_MASK);
2842	else
2843	{
2844	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2845	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
2846	u32Address,
2847	Pde.n.u1Write ? 'W' : 'R',
2848	Pde.n.u1User ? 'U' : 'S',
2849	Pde.n.u1Accessed ? 'A' : '-',
2850	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2851	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2852	Pde.n.u1WriteThru ? "WT" : "--",
2853	Pde.n.u1CacheDisable? "CD" : "--",
2854	Pde.u & BIT64(9) ? '1' : '0',
2855	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2856	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2857	Pde.u & X86_PDE_PG_MASK);
2858	if (cMaxDepth >= 1)
2859	{
2860	/** @todo what about using the page pool for mapping PTs? */
2861	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
2862	PX86PT pPT = NULL;
2863	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2864	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
2865	else
2866	{
2867	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
2868	if (u32Address - pMap->GCPtr < pMap->cb)
2869	{
2870	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
2871	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
2872	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2873	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
2874	pPT = pMap->aPTs[iPDE].pPTR3;
2875	}
2876	}
2877	int rc2 = VERR_INVALID_PARAMETER;
2878	if (pPT)
2879	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
2880	else
2881	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
2882	if (rc2 < rc && VBOX_SUCCESS(rc))
2883	rc = rc2;
2884	}
2885	}
2886	}
2887	}
2888
2889	return rc;
2890	}
2891
2892
2893	/**
2894	* Dumps a 32-bit shadow page table.
2895	*
2896	* @returns VBox status code (VINF_SUCCESS).
2897	* @param pVM The VM handle.
2898	* @param pPT Pointer to the page table.
2899	* @param u32Address The virtual address this table starts at.
2900	* @param PhysSearch Address to search for.
2901	*/
2902	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
2903	{
2904	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2905	{
2906	X86PTE Pte = pPT->a[i];
2907	if (Pte.n.u1Present)
2908	{
2909	Log(( /P R S A D G WT CD AT NX 4M a m d /
2910	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2911	u32Address + (i << X86_PT_SHIFT),
2912	Pte.n.u1Write ? 'W' : 'R',
2913	Pte.n.u1User ? 'U' : 'S',
2914	Pte.n.u1Accessed ? 'A' : '-',
2915	Pte.n.u1Dirty ? 'D' : '-',
2916	Pte.n.u1Global ? 'G' : '-',
2917	Pte.n.u1WriteThru ? "WT" : "--",
2918	Pte.n.u1CacheDisable? "CD" : "--",
2919	Pte.n.u1PAT ? "AT" : "--",
2920	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2921	Pte.u & BIT(10) ? '1' : '0',
2922	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2923	Pte.u & X86_PDE_PG_MASK));
2924
2925	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
2926	{
2927	uint64_t fPageShw = 0;
2928	RTHCPHYS pPhysHC = 0;
2929
2930	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
2931	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
2932	}
2933	}
2934	}
2935	return VINF_SUCCESS;
2936	}
2937
2938
2939	/**
2940	* Dumps a 32-bit guest page directory and page tables.
2941	*
2942	* @returns VBox status code (VINF_SUCCESS).
2943	* @param pVM The VM handle.
2944	* @param cr3 The root of the hierarchy.
2945	* @param cr4 The CR4, PSE is currently used.
2946	* @param PhysSearch Address to search for.
2947	*/
2948	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCPHYS PhysSearch)
2949	{
2950	bool fLongMode = false;
2951	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
2952	PX86PD pPD = 0;
2953
2954	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
2955	if (VBOX_FAILURE(rc) \|\| !pPD)
2956	{
2957	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
2958	return VERR_INVALID_PARAMETER;
2959	}
2960
2961	Log(("cr3=%08x cr4=%08x%s\n"
2962	"%-*s P - Present\n"
2963	"%-*s \| R/W - Read (0) / Write (1)\n"
2964	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
2965	"%-*s \| \| \| A - Accessed\n"
2966	"%-*s \| \| \| \| D - Dirty\n"
2967	"%-*s \| \| \| \| \| G - Global\n"
2968	"%-*s \| \| \| \| \| \| WT - Write thru\n"
2969	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
2970	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
2971	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
2972	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
2973	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
2974	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
2975	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
2976	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
2977	- W U - - - -- -- -- -- -- 010 */
2978	, cr3, cr4, fLongMode ? " Long Mode" : "",
2979	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
2980	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
2981
2982	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2983	{
2984	X86PDE Pde = pPD->a[i];
2985	if (Pde.n.u1Present)
2986	{
2987	const uint32_t u32Address = i << X86_PD_SHIFT;
2988
2989	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2990	Log(( /P R S A D G WT CD AT NX 4M a m d /
2991	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2992	u32Address,
2993	Pde.b.u1Write ? 'W' : 'R',
2994	Pde.b.u1User ? 'U' : 'S',
2995	Pde.b.u1Accessed ? 'A' : '-',
2996	Pde.b.u1Dirty ? 'D' : '-',
2997	Pde.b.u1Global ? 'G' : '-',
2998	Pde.b.u1WriteThru ? "WT" : "--",
2999	Pde.b.u1CacheDisable? "CD" : "--",
3000	Pde.b.u1PAT ? "AT" : "--",
3001	Pde.u & BIT(9) ? '1' : '0',
3002	Pde.u & BIT(10) ? '1' : '0',
3003	Pde.u & BIT(11) ? '1' : '0',
3004	Pde.u & X86_PDE4M_PG_MASK));
3005	/** @todo PhysSearch */
3006	else
3007	{
3008	Log(( /P R S A D G WT CD AT NX 4M a m d /
3009	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3010	u32Address,
3011	Pde.n.u1Write ? 'W' : 'R',
3012	Pde.n.u1User ? 'U' : 'S',
3013	Pde.n.u1Accessed ? 'A' : '-',
3014	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3015	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3016	Pde.n.u1WriteThru ? "WT" : "--",
3017	Pde.n.u1CacheDisable? "CD" : "--",
3018	Pde.u & BIT(9) ? '1' : '0',
3019	Pde.u & BIT(10) ? '1' : '0',
3020	Pde.u & BIT(11) ? '1' : '0',
3021	Pde.u & X86_PDE_PG_MASK));
3022	////if (cMaxDepth >= 1)
3023	{
3024	/** @todo what about using the page pool for mapping PTs? */
3025	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3026	PX86PT pPT = NULL;
3027
3028	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3029
3030	int rc2 = VERR_INVALID_PARAMETER;
3031	if (pPT)
3032	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3033	else
3034	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3035	if (rc2 < rc && VBOX_SUCCESS(rc))
3036	rc = rc2;
3037	}
3038	}
3039	}
3040	}
3041
3042	return rc;
3043	}
3044
3045
3046	/**
3047	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3048	*
3049	* @returns VBox status code (VINF_SUCCESS).
3050	* @param pVM The VM handle.
3051	* @param cr3 The root of the hierarchy.
3052	* @param cr4 The cr4, only PAE and PSE is currently used.
3053	* @param fLongMode Set if long mode, false if not long mode.
3054	* @param cMaxDepth Number of levels to dump.
3055	* @param pHlp Pointer to the output functions.
3056	*/
3057	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3058	{
3059	if (!pHlp)
3060	pHlp = DBGFR3InfoLogHlp();
3061	if (!cMaxDepth)
3062	return VINF_SUCCESS;
3063	const unsigned cch = fLongMode ? 16 : 8;
3064	pHlp->pfnPrintf(pHlp,
3065	"cr3=%08x cr4=%08x%s\n"
3066	"%-*s P - Present\n"
3067	"%-*s \| R/W - Read (0) / Write (1)\n"
3068	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3069	"%-*s \| \| \| A - Accessed\n"
3070	"%-*s \| \| \| \| D - Dirty\n"
3071	"%-*s \| \| \| \| \| G - Global\n"
3072	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3073	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3074	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3075	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3076	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3077	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3078	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3079	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3080	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3081	- W U - - - -- -- -- -- -- 010 */
3082	, cr3, cr4, fLongMode ? " Long Mode" : "",
3083	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3084	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3085	if (cr4 & X86_CR4_PAE)
3086	{
3087	if (fLongMode)
3088	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3089	return pgmR3DumpHierarchyHCPaePDPTR(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3090	}
3091	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3092	}
3093
3094
3095
3096	#ifdef VBOX_WITH_DEBUGGER
3097	/**
3098	* The '.pgmram' command.
3099	*
3100	* @returns VBox status.
3101	* @param pCmd Pointer to the command descriptor (as registered).
3102	* @param pCmdHlp Pointer to command helper functions.
3103	* @param pVM Pointer to the current VM (if any).
3104	* @param paArgs Pointer to (readonly) array of arguments.
3105	* @param cArgs Number of arguments in the array.
3106	*/
3107	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3108	{
3109	/*
3110	* Validate input.
3111	*/
3112	if (!pVM)
3113	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3114	if (!pVM->pgm.s.pRamRangesGC)
3115	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3116
3117	/*
3118	* Dump the ranges.
3119	*/
3120	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3121	PPGMRAMRANGE pRam;
3122	for (pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
3123	{
3124	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3125	"%VGp - %VGp %p\n",
3126	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3127	if (VBOX_FAILURE(rc))
3128	return rc;
3129	}
3130
3131	return VINF_SUCCESS;
3132	}
3133
3134
3135	/**
3136	* The '.pgmmap' command.
3137	*
3138	* @returns VBox status.
3139	* @param pCmd Pointer to the command descriptor (as registered).
3140	* @param pCmdHlp Pointer to command helper functions.
3141	* @param pVM Pointer to the current VM (if any).
3142	* @param paArgs Pointer to (readonly) array of arguments.
3143	* @param cArgs Number of arguments in the array.
3144	*/
3145	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3146	{
3147	/*
3148	* Validate input.
3149	*/
3150	if (!pVM)
3151	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3152	if (!pVM->pgm.s.pMappingsR3)
3153	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3154
3155	/*
3156	* Print message about the fixedness of the mappings.
3157	*/
3158	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3159	if (VBOX_FAILURE(rc))
3160	return rc;
3161
3162	/*
3163	* Dump the ranges.
3164	*/
3165	PPGMMAPPING pCur;
3166	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
3167	{
3168	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3169	"%08x - %08x %s\n",
3170	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3171	if (VBOX_FAILURE(rc))
3172	return rc;
3173	}
3174
3175	return VINF_SUCCESS;
3176	}
3177
3178
3179	/**
3180	* The '.pgmsync' command.
3181	*
3182	* @returns VBox status.
3183	* @param pCmd Pointer to the command descriptor (as registered).
3184	* @param pCmdHlp Pointer to command helper functions.
3185	* @param pVM Pointer to the current VM (if any).
3186	* @param paArgs Pointer to (readonly) array of arguments.
3187	* @param cArgs Number of arguments in the array.
3188	*/
3189	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3190	{
3191	/*
3192	* Validate input.
3193	*/
3194	if (!pVM)
3195	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3196
3197	/*
3198	* Force page directory sync.
3199	*/
3200	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3201
3202	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3203	if (VBOX_FAILURE(rc))
3204	return rc;
3205
3206	return VINF_SUCCESS;
3207	}
3208
3209
3210	/**
3211	* The '.pgmsyncalways' command.
3212	*
3213	* @returns VBox status.
3214	* @param pCmd Pointer to the command descriptor (as registered).
3215	* @param pCmdHlp Pointer to command helper functions.
3216	* @param pVM Pointer to the current VM (if any).
3217	* @param paArgs Pointer to (readonly) array of arguments.
3218	* @param cArgs Number of arguments in the array.
3219	*/
3220	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3221	{
3222	/*
3223	* Validate input.
3224	*/
3225	if (!pVM)
3226	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3227
3228	/*
3229	* Force page directory sync.
3230	*/
3231	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3232	{
3233	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3234	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3235	}
3236	else
3237	{
3238	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3239	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3240	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3241	}
3242	}
3243
3244	#endif
3245
3246	/**
3247	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3248	*/
3249	typedef struct PGMCHECKINTARGS
3250	{
3251	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3252	PPGMPHYSHANDLER pPrevPhys;
3253	PPGMVIRTHANDLER pPrevVirt;
3254	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3255	PVM pVM;
3256	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3257
3258	/**
3259	* Validate a node in the physical handler tree.
3260	*
3261	* @returns 0 on if ok, other wise 1.
3262	* @param pNode The handler node.
3263	* @param pvUser pVM.
3264	*/
3265	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3266	{
3267	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3268	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3269	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3270	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3271	AssertReleaseMsg( !pArgs->pPrevPhys
3272	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3273	("pPrevPhys=%p %VGp-%VGp %s\n"
3274	" pCur=%p %VGp-%VGp %s\n",
3275	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3276	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3277	pArgs->pPrevPhys = pCur;
3278	return 0;
3279	}
3280
3281
3282	/**
3283	* Validate a node in the virtual handler tree.
3284	*
3285	* @returns 0 on if ok, other wise 1.
3286	* @param pNode The handler node.
3287	* @param pvUser pVM.
3288	*/
3289	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
3290	{
3291	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3292	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
3293	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3294	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3295	AssertReleaseMsg( !pArgs->pPrevVirt
3296	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
3297	("pPrevVirt=%p %VGv-%VGv %s\n"
3298	" pCur=%p %VGv-%VGv %s\n",
3299	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
3300	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3301	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
3302	{
3303	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
3304	("pCur=%p %VGv-%VGv %s\n"
3305	"iPage=%d offVirtHandle=%#x expected %#x\n",
3306	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
3307	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
3308	}
3309	pArgs->pPrevVirt = pCur;
3310	return 0;
3311	}
3312
3313
3314	/**
3315	* Validate a node in the virtual handler tree.
3316	*
3317	* @returns 0 on if ok, other wise 1.
3318	* @param pNode The handler node.
3319	* @param pvUser pVM.
3320	*/
3321	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3322	{
3323	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3324	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
3325	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
3326	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
3327	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
3328	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3329	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3330	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3331	" pCur=%p %VGp-%VGp\n",
3332	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3333	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3334	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3335	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3336	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3337	" pCur=%p %VGp-%VGp\n",
3338	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3339	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3340	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
3341	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3342	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3343	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3344	{
3345	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
3346	for (;;)
3347	{
3348	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3349	AssertReleaseMsg(pCur2 != pCur,
3350	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3351	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3352	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
3353	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3354	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3355	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3356	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3357	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
3358	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3359	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3360	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3361	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3362	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
3363	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3364	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3365	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3366	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3367	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3368	break;
3369	}
3370	}
3371
3372	pArgs->pPrevPhys2Virt = pCur;
3373	return 0;
3374	}
3375
3376
3377	/**
3378	* Perform an integrity check on the PGM component.
3379	*
3380	* @returns VINF_SUCCESS if everything is fine.
3381	* @returns VBox error status after asserting on integrity breach.
3382	* @param pVM The VM handle.
3383	*/
3384	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
3385	{
3386	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
3387
3388	/*
3389	* Check the trees.
3390	*/
3391	int cErrors = 0;
3392	PGMCHECKINTARGS Args = { true, NULL, NULL, NULL, pVM };
3393	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3394	Args.fLeftToRight = false;
3395	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3396	Args.fLeftToRight = true;
3397	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3398	Args.fLeftToRight = false;
3399	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3400	Args.fLeftToRight = true;
3401	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3402	Args.fLeftToRight = false;
3403	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3404
3405	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
3406	}
3407
3408
3409	/**
3410	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
3411	*
3412	* @returns VBox status code.
3413	* @param pVM VM handle.
3414	* @param fEnable Enable or disable shadow mappings
3415	*/
3416	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
3417	{
3418	pVM->pgm.s.fDisableMappings = !fEnable;
3419
3420	size_t cb;
3421	int rc = PGMR3MappingsSize(pVM, &cb);
3422	AssertRCReturn(rc, rc);
3423
3424	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
3425	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
3426	AssertRCReturn(rc, rc);
3427
3428	return VINF_SUCCESS;
3429	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 3723

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