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1	/* $Id: PGM.cpp 31684 2010-08-16 09:56:13Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be refered to
30	* as "host paging", and GC refered to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgm_phys PGM Physical Guest Memory Management
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
484	* however on 32-bit darwin the ring-0 code is running in a different memory
485	* context and therefore needs a separate cache. In raw-mode context we also
486	* need a separate cache. The 32-bit darwin mapping cache and the one for
487	* raw-mode context share a lot of code, see PGMRZDYNMAP.
488	*
489	*
490	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
491	*
492	* We've considered implementing the ring-3 mapping cache page based but found
493	* that this was bother some when one had to take into account TLBs+SMP and
494	* portability (missing the necessary APIs on several platforms). There were
495	* also some performance concerns with this approach which hadn't quite been
496	* worked out.
497	*
498	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
499	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
500	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
501	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
502	* costly than a single page, although how much more costly is uncertain. We'll
503	* try address this by using a very big cache, preferably bigger than the actual
504	* VM RAM size if possible. The current VM RAM sizes should give some idea for
505	* 32-bit boxes, while on 64-bit we can probably get away with employing an
506	* unlimited cache.
507	*
508	* The cache have to parts, as already indicated, the ring-3 side and the
509	* ring-0 side.
510	*
511	* The ring-0 will be tied to the page allocator since it will operate on the
512	* memory objects it contains. It will therefore require the first ring-0 mutex
513	* discussed in @ref subsec_pgmPhys_Serializing. We
514	* some double house keeping wrt to who has mapped what I think, since both
515	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
516	*
517	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
518	* require anyone that desires to do changes to the mapping cache to do that
519	* from within this critsect. Alternatively, we could employ a separate critsect
520	* for serializing changes to the mapping cache as this would reduce potential
521	* contention with other threads accessing mappings unrelated to the changes
522	* that are in process. We can see about this later, contention will show
523	* up in the statistics anyway, so it'll be simple to tell.
524	*
525	* The organization of the ring-3 part will be very much like how the allocation
526	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
527	* having to walk the tree all the time, we'll have a couple of lookaside entries
528	* like in we do for I/O ports and MMIO in IOM.
529	*
530	* The simplified flow of a PGMPhysRead/Write function:
531	* -# Enter the PGM critsect.
532	* -# Lookup GCPhys in the ram ranges and get the Page ID.
533	* -# Calc the Allocation Chunk ID from the Page ID.
534	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
535	* If not found in cache:
536	* -# Call ring-0 and request it to be mapped and supply
537	* a chunk to be unmapped if the cache is maxed out already.
538	* -# Insert the new mapping into the AVL tree (id + R3 address).
539	* -# Update the relevant lookaside entry and return the mapping address.
540	* -# Do the read/write according to monitoring flags and everything.
541	* -# Leave the critsect.
542	*
543	*
544	* @section sec_pgmPhys_Fallback Fallback
545	*
546	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
547	* API and thus require a fallback.
548	*
549	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
550	* will return to the ring-3 caller (and later ring-0) and asking it to seed
551	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
552	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
553	* "SeededAllocPages" call to ring-0.
554	*
555	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
556	* all page sharing (zero page detection will continue). It will also force
557	* all allocations to come from the VM which seeded the page. Both these
558	* measures are taken to make sure that there will never be any need for
559	* mapping anything into ring-3 - everything will be mapped already.
560	*
561	* Whether we'll continue to use the current MM locked memory management
562	* for this I don't quite know (I'd prefer not to and just ditch that all
563	* togther), we'll see what's simplest to do.
564	*
565	*
566	*
567	* @section sec_pgmPhys_Changes Changes
568	*
569	* Breakdown of the changes involved?
570	*/
571
572	/*******************************************************************************
573	* Header Files *
574	*******************************************************************************/
575	#define LOG_GROUP LOG_GROUP_PGM
576	#include <VBox/dbgf.h>
577	#include <VBox/pgm.h>
578	#include <VBox/cpum.h>
579	#include <VBox/iom.h>
580	#include <VBox/sup.h>
581	#include <VBox/mm.h>
582	#include <VBox/em.h>
583	#include <VBox/stam.h>
584	#include <VBox/rem.h>
585	#include <VBox/selm.h>
586	#include <VBox/ssm.h>
587	#include <VBox/hwaccm.h>
588	#include "PGMInternal.h"
589	#include <VBox/vm.h>
590	#include "PGMInline.h"
591
592	#include <VBox/dbg.h>
593	#include <VBox/param.h>
594	#include <VBox/err.h>
595
596	#include <iprt/asm.h>
597	#include <iprt/asm-amd64-x86.h>
598	#include <iprt/assert.h>
599	#include <iprt/env.h>
600	#include <iprt/mem.h>
601	#include <iprt/file.h>
602	#include <iprt/string.h>
603	#include <iprt/thread.h>
604
605
606	/*******************************************************************************
607	* Internal Functions *
608	*******************************************************************************/
609	static int pgmR3InitPaging(PVM pVM);
610	static int pgmR3InitStats(PVM pVM);
611	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
612	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
613	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
614	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
615	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
616	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
617	#ifdef VBOX_STRICT
618	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
619	#endif
620	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
621	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
622	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
623
624	#ifdef VBOX_WITH_DEBUGGER
625	/** @todo Convert the first two commands to 'info' items. */
626	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
627	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
628	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
629	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
630	# ifdef VBOX_STRICT
631	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
632	# endif
633	# ifdef DEBUG_sandervl
634	static DECLCALLBACK(int) pgmR3CmdCountPhysWrites(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	static DECLCALLBACK(void) pgmR3PhysWriteCountTMCallback(PVM pVM, PTMTIMER pTimer, void *pvUser);
636	# endif
637	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	#endif
639
640
641	/*******************************************************************************
642	* Global Variables *
643	*******************************************************************************/
644	#ifdef VBOX_WITH_DEBUGGER
645	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
646	static const DBGCVARDESC g_aPgmErrorArgs[] =
647	{
648	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
649	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
650	};
651
652	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
653	{
654	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
655	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
656	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
657	};
658
659	# ifdef DEBUG_sandervl
660	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
661	{
662	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
663	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
664	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
665	};
666	# endif
667
668	/** Command descriptors. */
669	static const DBGCCMD g_aCmds[] =
670	{
671	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
672	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
673	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
674	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
675	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
676	# ifdef VBOX_STRICT
677	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
678	# if HC_ARCH_BITS == 64
679	{ "pgmcheckduppages", 0, 0, NULL, 0, NULL, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
680	{ "pgmsharedmodules", 0, 0, NULL, 0, NULL, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
681	# endif
682	# endif
683	# ifdef DEBUG_sandervl
684	{ "pgmcountphyswrites", 2, 2, &g_aPgmCountPhysWritesArgs[0], 2, NULL, 0, pgmR3CmdCountPhysWrites, "", "Count physical page writes."},
685	# endif
686	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
687	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
688	};
689	#endif
690
691
692
693
694	/*
695	* Shadow - 32-bit mode
696	*/
697	#define PGM_SHW_TYPE PGM_TYPE_32BIT
698	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
699	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
700	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
701	#include "PGMShw.h"
702
703	/* Guest - real mode */
704	#define PGM_GST_TYPE PGM_TYPE_REAL
705	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
706	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
707	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
708	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
709	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
710	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
711	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
712	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
713	#include "PGMBth.h"
714	#include "PGMGstDefs.h"
715	#include "PGMGst.h"
716	#undef BTH_PGMPOOLKIND_PT_FOR_PT
717	#undef BTH_PGMPOOLKIND_ROOT
718	#undef PGM_BTH_NAME
719	#undef PGM_BTH_NAME_RC_STR
720	#undef PGM_BTH_NAME_R0_STR
721	#undef PGM_GST_TYPE
722	#undef PGM_GST_NAME
723	#undef PGM_GST_NAME_RC_STR
724	#undef PGM_GST_NAME_R0_STR
725
726	/* Guest - protected mode */
727	#define PGM_GST_TYPE PGM_TYPE_PROT
728	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
729	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
730	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
731	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
732	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
733	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
734	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
735	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
736	#include "PGMBth.h"
737	#include "PGMGstDefs.h"
738	#include "PGMGst.h"
739	#undef BTH_PGMPOOLKIND_PT_FOR_PT
740	#undef BTH_PGMPOOLKIND_ROOT
741	#undef PGM_BTH_NAME
742	#undef PGM_BTH_NAME_RC_STR
743	#undef PGM_BTH_NAME_R0_STR
744	#undef PGM_GST_TYPE
745	#undef PGM_GST_NAME
746	#undef PGM_GST_NAME_RC_STR
747	#undef PGM_GST_NAME_R0_STR
748
749	/* Guest - 32-bit mode */
750	#define PGM_GST_TYPE PGM_TYPE_32BIT
751	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
752	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
753	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
754	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
755	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
756	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
757	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
758	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
759	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
760	#include "PGMBth.h"
761	#include "PGMGstDefs.h"
762	#include "PGMGst.h"
763	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
764	#undef BTH_PGMPOOLKIND_PT_FOR_PT
765	#undef BTH_PGMPOOLKIND_ROOT
766	#undef PGM_BTH_NAME
767	#undef PGM_BTH_NAME_RC_STR
768	#undef PGM_BTH_NAME_R0_STR
769	#undef PGM_GST_TYPE
770	#undef PGM_GST_NAME
771	#undef PGM_GST_NAME_RC_STR
772	#undef PGM_GST_NAME_R0_STR
773
774	#undef PGM_SHW_TYPE
775	#undef PGM_SHW_NAME
776	#undef PGM_SHW_NAME_RC_STR
777	#undef PGM_SHW_NAME_R0_STR
778
779
780	/*
781	* Shadow - PAE mode
782	*/
783	#define PGM_SHW_TYPE PGM_TYPE_PAE
784	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
785	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
786	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
787	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
788	#include "PGMShw.h"
789
790	/* Guest - real mode */
791	#define PGM_GST_TYPE PGM_TYPE_REAL
792	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
793	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
794	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
795	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
796	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
797	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
798	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
799	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
800	#include "PGMGstDefs.h"
801	#include "PGMBth.h"
802	#undef BTH_PGMPOOLKIND_PT_FOR_PT
803	#undef BTH_PGMPOOLKIND_ROOT
804	#undef PGM_BTH_NAME
805	#undef PGM_BTH_NAME_RC_STR
806	#undef PGM_BTH_NAME_R0_STR
807	#undef PGM_GST_TYPE
808	#undef PGM_GST_NAME
809	#undef PGM_GST_NAME_RC_STR
810	#undef PGM_GST_NAME_R0_STR
811
812	/* Guest - protected mode */
813	#define PGM_GST_TYPE PGM_TYPE_PROT
814	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
815	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
816	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
817	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
818	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
819	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
820	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
821	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
822	#include "PGMGstDefs.h"
823	#include "PGMBth.h"
824	#undef BTH_PGMPOOLKIND_PT_FOR_PT
825	#undef BTH_PGMPOOLKIND_ROOT
826	#undef PGM_BTH_NAME
827	#undef PGM_BTH_NAME_RC_STR
828	#undef PGM_BTH_NAME_R0_STR
829	#undef PGM_GST_TYPE
830	#undef PGM_GST_NAME
831	#undef PGM_GST_NAME_RC_STR
832	#undef PGM_GST_NAME_R0_STR
833
834	/* Guest - 32-bit mode */
835	#define PGM_GST_TYPE PGM_TYPE_32BIT
836	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
837	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
838	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
839	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
840	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
841	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
842	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
843	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
844	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
845	#include "PGMGstDefs.h"
846	#include "PGMBth.h"
847	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
848	#undef BTH_PGMPOOLKIND_PT_FOR_PT
849	#undef BTH_PGMPOOLKIND_ROOT
850	#undef PGM_BTH_NAME
851	#undef PGM_BTH_NAME_RC_STR
852	#undef PGM_BTH_NAME_R0_STR
853	#undef PGM_GST_TYPE
854	#undef PGM_GST_NAME
855	#undef PGM_GST_NAME_RC_STR
856	#undef PGM_GST_NAME_R0_STR
857
858	/* Guest - PAE mode */
859	#define PGM_GST_TYPE PGM_TYPE_PAE
860	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
861	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
862	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
863	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
864	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
865	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
866	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
867	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
868	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
869	#include "PGMBth.h"
870	#include "PGMGstDefs.h"
871	#include "PGMGst.h"
872	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
873	#undef BTH_PGMPOOLKIND_PT_FOR_PT
874	#undef BTH_PGMPOOLKIND_ROOT
875	#undef PGM_BTH_NAME
876	#undef PGM_BTH_NAME_RC_STR
877	#undef PGM_BTH_NAME_R0_STR
878	#undef PGM_GST_TYPE
879	#undef PGM_GST_NAME
880	#undef PGM_GST_NAME_RC_STR
881	#undef PGM_GST_NAME_R0_STR
882
883	#undef PGM_SHW_TYPE
884	#undef PGM_SHW_NAME
885	#undef PGM_SHW_NAME_RC_STR
886	#undef PGM_SHW_NAME_R0_STR
887
888
889	/*
890	* Shadow - AMD64 mode
891	*/
892	#define PGM_SHW_TYPE PGM_TYPE_AMD64
893	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
894	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
895	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
896	#include "PGMShw.h"
897
898	#ifdef VBOX_WITH_64_BITS_GUESTS
899	/* Guest - AMD64 mode */
900	# define PGM_GST_TYPE PGM_TYPE_AMD64
901	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
902	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
903	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
904	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
905	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
906	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
907	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
908	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
909	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
910	# include "PGMBth.h"
911	# include "PGMGstDefs.h"
912	# include "PGMGst.h"
913	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
914	# undef BTH_PGMPOOLKIND_PT_FOR_PT
915	# undef BTH_PGMPOOLKIND_ROOT
916	# undef PGM_BTH_NAME
917	# undef PGM_BTH_NAME_RC_STR
918	# undef PGM_BTH_NAME_R0_STR
919	# undef PGM_GST_TYPE
920	# undef PGM_GST_NAME
921	# undef PGM_GST_NAME_RC_STR
922	# undef PGM_GST_NAME_R0_STR
923	#endif /* VBOX_WITH_64_BITS_GUESTS */
924
925	#undef PGM_SHW_TYPE
926	#undef PGM_SHW_NAME
927	#undef PGM_SHW_NAME_RC_STR
928	#undef PGM_SHW_NAME_R0_STR
929
930
931	/*
932	* Shadow - Nested paging mode
933	*/
934	#define PGM_SHW_TYPE PGM_TYPE_NESTED
935	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
936	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
937	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
938	#include "PGMShw.h"
939
940	/* Guest - real mode */
941	#define PGM_GST_TYPE PGM_TYPE_REAL
942	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
943	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
944	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
945	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
946	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
947	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
948	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
949	#include "PGMGstDefs.h"
950	#include "PGMBth.h"
951	#undef BTH_PGMPOOLKIND_PT_FOR_PT
952	#undef PGM_BTH_NAME
953	#undef PGM_BTH_NAME_RC_STR
954	#undef PGM_BTH_NAME_R0_STR
955	#undef PGM_GST_TYPE
956	#undef PGM_GST_NAME
957	#undef PGM_GST_NAME_RC_STR
958	#undef PGM_GST_NAME_R0_STR
959
960	/* Guest - protected mode */
961	#define PGM_GST_TYPE PGM_TYPE_PROT
962	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
963	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
964	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
965	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
966	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
967	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
968	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
969	#include "PGMGstDefs.h"
970	#include "PGMBth.h"
971	#undef BTH_PGMPOOLKIND_PT_FOR_PT
972	#undef PGM_BTH_NAME
973	#undef PGM_BTH_NAME_RC_STR
974	#undef PGM_BTH_NAME_R0_STR
975	#undef PGM_GST_TYPE
976	#undef PGM_GST_NAME
977	#undef PGM_GST_NAME_RC_STR
978	#undef PGM_GST_NAME_R0_STR
979
980	/* Guest - 32-bit mode */
981	#define PGM_GST_TYPE PGM_TYPE_32BIT
982	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
983	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
984	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
985	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
986	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
987	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
988	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
989	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
990	#include "PGMGstDefs.h"
991	#include "PGMBth.h"
992	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
993	#undef BTH_PGMPOOLKIND_PT_FOR_PT
994	#undef PGM_BTH_NAME
995	#undef PGM_BTH_NAME_RC_STR
996	#undef PGM_BTH_NAME_R0_STR
997	#undef PGM_GST_TYPE
998	#undef PGM_GST_NAME
999	#undef PGM_GST_NAME_RC_STR
1000	#undef PGM_GST_NAME_R0_STR
1001
1002	/* Guest - PAE mode */
1003	#define PGM_GST_TYPE PGM_TYPE_PAE
1004	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1005	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1006	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1007	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1008	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1009	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1010	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1011	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1012	#include "PGMGstDefs.h"
1013	#include "PGMBth.h"
1014	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1015	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1016	#undef PGM_BTH_NAME
1017	#undef PGM_BTH_NAME_RC_STR
1018	#undef PGM_BTH_NAME_R0_STR
1019	#undef PGM_GST_TYPE
1020	#undef PGM_GST_NAME
1021	#undef PGM_GST_NAME_RC_STR
1022	#undef PGM_GST_NAME_R0_STR
1023
1024	#ifdef VBOX_WITH_64_BITS_GUESTS
1025	/* Guest - AMD64 mode */
1026	# define PGM_GST_TYPE PGM_TYPE_AMD64
1027	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1028	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1029	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1030	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1031	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1032	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1033	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1034	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1035	# include "PGMGstDefs.h"
1036	# include "PGMBth.h"
1037	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1038	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1039	# undef PGM_BTH_NAME
1040	# undef PGM_BTH_NAME_RC_STR
1041	# undef PGM_BTH_NAME_R0_STR
1042	# undef PGM_GST_TYPE
1043	# undef PGM_GST_NAME
1044	# undef PGM_GST_NAME_RC_STR
1045	# undef PGM_GST_NAME_R0_STR
1046	#endif /* VBOX_WITH_64_BITS_GUESTS */
1047
1048	#undef PGM_SHW_TYPE
1049	#undef PGM_SHW_NAME
1050	#undef PGM_SHW_NAME_RC_STR
1051	#undef PGM_SHW_NAME_R0_STR
1052
1053
1054	/*
1055	* Shadow - EPT
1056	*/
1057	#define PGM_SHW_TYPE PGM_TYPE_EPT
1058	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1059	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1060	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1061	#include "PGMShw.h"
1062
1063	/* Guest - real mode */
1064	#define PGM_GST_TYPE PGM_TYPE_REAL
1065	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1066	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1067	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1068	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1069	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1070	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1071	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1072	#include "PGMGstDefs.h"
1073	#include "PGMBth.h"
1074	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1075	#undef PGM_BTH_NAME
1076	#undef PGM_BTH_NAME_RC_STR
1077	#undef PGM_BTH_NAME_R0_STR
1078	#undef PGM_GST_TYPE
1079	#undef PGM_GST_NAME
1080	#undef PGM_GST_NAME_RC_STR
1081	#undef PGM_GST_NAME_R0_STR
1082
1083	/* Guest - protected mode */
1084	#define PGM_GST_TYPE PGM_TYPE_PROT
1085	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1086	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1087	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1088	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1089	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1090	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1091	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1092	#include "PGMGstDefs.h"
1093	#include "PGMBth.h"
1094	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1095	#undef PGM_BTH_NAME
1096	#undef PGM_BTH_NAME_RC_STR
1097	#undef PGM_BTH_NAME_R0_STR
1098	#undef PGM_GST_TYPE
1099	#undef PGM_GST_NAME
1100	#undef PGM_GST_NAME_RC_STR
1101	#undef PGM_GST_NAME_R0_STR
1102
1103	/* Guest - 32-bit mode */
1104	#define PGM_GST_TYPE PGM_TYPE_32BIT
1105	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1106	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1107	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1108	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1109	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1110	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1111	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1112	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1113	#include "PGMGstDefs.h"
1114	#include "PGMBth.h"
1115	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1116	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1117	#undef PGM_BTH_NAME
1118	#undef PGM_BTH_NAME_RC_STR
1119	#undef PGM_BTH_NAME_R0_STR
1120	#undef PGM_GST_TYPE
1121	#undef PGM_GST_NAME
1122	#undef PGM_GST_NAME_RC_STR
1123	#undef PGM_GST_NAME_R0_STR
1124
1125	/* Guest - PAE mode */
1126	#define PGM_GST_TYPE PGM_TYPE_PAE
1127	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1128	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1129	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1130	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1131	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1132	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1133	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1134	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1135	#include "PGMGstDefs.h"
1136	#include "PGMBth.h"
1137	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1138	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1139	#undef PGM_BTH_NAME
1140	#undef PGM_BTH_NAME_RC_STR
1141	#undef PGM_BTH_NAME_R0_STR
1142	#undef PGM_GST_TYPE
1143	#undef PGM_GST_NAME
1144	#undef PGM_GST_NAME_RC_STR
1145	#undef PGM_GST_NAME_R0_STR
1146
1147	#ifdef VBOX_WITH_64_BITS_GUESTS
1148	/* Guest - AMD64 mode */
1149	# define PGM_GST_TYPE PGM_TYPE_AMD64
1150	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1151	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1152	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1153	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1154	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1155	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1156	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1157	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1158	# include "PGMGstDefs.h"
1159	# include "PGMBth.h"
1160	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1161	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1162	# undef PGM_BTH_NAME
1163	# undef PGM_BTH_NAME_RC_STR
1164	# undef PGM_BTH_NAME_R0_STR
1165	# undef PGM_GST_TYPE
1166	# undef PGM_GST_NAME
1167	# undef PGM_GST_NAME_RC_STR
1168	# undef PGM_GST_NAME_R0_STR
1169	#endif /* VBOX_WITH_64_BITS_GUESTS */
1170
1171	#undef PGM_SHW_TYPE
1172	#undef PGM_SHW_NAME
1173	#undef PGM_SHW_NAME_RC_STR
1174	#undef PGM_SHW_NAME_R0_STR
1175
1176
1177
1178	/**
1179	* Initiates the paging of VM.
1180	*
1181	* @returns VBox status code.
1182	* @param pVM Pointer to VM structure.
1183	*/
1184	VMMR3DECL(int) PGMR3Init(PVM pVM)
1185	{
1186	LogFlow(("PGMR3Init:\n"));
1187	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1188	int rc;
1189
1190	/*
1191	* Assert alignment and sizes.
1192	*/
1193	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1194	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1195	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1196
1197	/*
1198	* Init the structure.
1199	*/
1200	#ifdef PGM_WITHOUT_MAPPINGS
1201	pVM->pgm.s.fMappingsDisabled = true;
1202	#endif
1203	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1204	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1205
1206	/* Init the per-CPU part. */
1207	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1208	{
1209	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1210	PPGMCPU pPGM = &pVCpu->pgm.s;
1211
1212	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1213	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1214	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1215
1216	pPGM->enmShadowMode = PGMMODE_INVALID;
1217	pPGM->enmGuestMode = PGMMODE_INVALID;
1218
1219	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1220
1221	pPGM->pGst32BitPdR3 = NULL;
1222	pPGM->pGstPaePdptR3 = NULL;
1223	pPGM->pGstAmd64Pml4R3 = NULL;
1224	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1225	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1226	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1227	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1228	#endif
1229	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1230	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1231	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1232	{
1233	pPGM->apGstPaePDsR3[i] = NULL;
1234	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1235	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1236	#endif
1237	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1238	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1239	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1240	}
1241
1242	pPGM->fA20Enabled = true;
1243	}
1244
1245	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1246	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1247	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1248
1249	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1250	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1251	true
1252	#else
1253	false
1254	#endif
1255	);
1256	AssertLogRelRCReturn(rc, rc);
1257
1258	#ifdef PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
1259	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1260	#else
1261	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1262	#endif
1263	AssertLogRelRCReturn(rc, rc);
1264	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1265	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1266
1267	/*
1268	* Get the configured RAM size - to estimate saved state size.
1269	*/
1270	uint64_t cbRam;
1271	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1272	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1273	cbRam = 0;
1274	else if (RT_SUCCESS(rc))
1275	{
1276	if (cbRam < PAGE_SIZE)
1277	cbRam = 0;
1278	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1279	}
1280	else
1281	{
1282	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1283	return rc;
1284	}
1285
1286	#ifdef VBOX_WITH_STATISTICS
1287	/*
1288	* Allocate memory for the statistics before someone tries to use them.
1289	*/
1290	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1291	void *pv;
1292	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1293	AssertRCReturn(rc, rc);
1294
1295	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1296	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1297	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1298	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1299
1300	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1301	{
1302	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1303	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1304	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1305
1306	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1307	}
1308	#endif /* VBOX_WITH_STATISTICS */
1309
1310	/*
1311	* Register callbacks, string formatters and the saved state data unit.
1312	*/
1313	#ifdef VBOX_STRICT
1314	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1315	#endif
1316	PGMRegisterStringFormatTypes();
1317
1318	rc = pgmR3InitSavedState(pVM, cbRam);
1319	if (RT_FAILURE(rc))
1320	return rc;
1321
1322	/*
1323	* Initialize the PGM critical section and flush the phys TLBs
1324	*/
1325	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, RT_SRC_POS, "PGM");
1326	AssertRCReturn(rc, rc);
1327
1328	PGMR3PhysChunkInvalidateTLB(pVM);
1329	PGMPhysInvalidatePageMapTLB(pVM);
1330
1331	/*
1332	* For the time being we sport a full set of handy pages in addition to the base
1333	* memory to simplify things.
1334	*/
1335	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1336	AssertRCReturn(rc, rc);
1337
1338	/*
1339	* Trees
1340	*/
1341	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1342	if (RT_SUCCESS(rc))
1343	{
1344	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1345	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1346
1347	/*
1348	* Allocate the zero page.
1349	*/
1350	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1351	}
1352	if (RT_SUCCESS(rc))
1353	{
1354	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1355	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1356	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1357	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1358
1359	/*
1360	* Allocate the invalid MMIO page.
1361	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1362	*/
1363	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1364	}
1365	if (RT_SUCCESS(rc))
1366	{
1367	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1368	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1369	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1370	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1371
1372	/*
1373	* Init the paging.
1374	*/
1375	rc = pgmR3InitPaging(pVM);
1376	}
1377	if (RT_SUCCESS(rc))
1378	{
1379	/*
1380	* Init the page pool.
1381	*/
1382	rc = pgmR3PoolInit(pVM);
1383	}
1384	if (RT_SUCCESS(rc))
1385	{
1386	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1387	{
1388	PVMCPU pVCpu = &pVM->aCpus[i];
1389	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1390	if (RT_FAILURE(rc))
1391	break;
1392	}
1393	}
1394
1395	if (RT_SUCCESS(rc))
1396	{
1397	/*
1398	* Info & statistics
1399	*/
1400	DBGFR3InfoRegisterInternal(pVM, "mode",
1401	"Shows the current paging mode. "
1402	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1403	pgmR3InfoMode);
1404	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1405	"Dumps all the entries in the top level paging table. No arguments.",
1406	pgmR3InfoCr3);
1407	DBGFR3InfoRegisterInternal(pVM, "phys",
1408	"Dumps all the physical address ranges. No arguments.",
1409	pgmR3PhysInfo);
1410	DBGFR3InfoRegisterInternal(pVM, "handlers",
1411	"Dumps physical, virtual and hyper virtual handlers. "
1412	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1413	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1414	pgmR3InfoHandlers);
1415	DBGFR3InfoRegisterInternal(pVM, "mappings",
1416	"Dumps guest mappings.",
1417	pgmR3MapInfo);
1418
1419	pgmR3InitStats(pVM);
1420
1421	#ifdef VBOX_WITH_DEBUGGER
1422	/*
1423	* Debugger commands.
1424	*/
1425	static bool s_fRegisteredCmds = false;
1426	if (!s_fRegisteredCmds)
1427	{
1428	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1429	if (RT_SUCCESS(rc2))
1430	s_fRegisteredCmds = true;
1431	}
1432	#endif
1433	return VINF_SUCCESS;
1434	}
1435
1436	/* Almost no cleanup necessary, MM frees all memory. */
1437	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1438
1439	return rc;
1440	}
1441
1442
1443	/**
1444	* Initializes the per-VCPU PGM.
1445	*
1446	* @returns VBox status code.
1447	* @param pVM The VM to operate on.
1448	*/
1449	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1450	{
1451	LogFlow(("PGMR3InitCPU\n"));
1452	return VINF_SUCCESS;
1453	}
1454
1455
1456	/**
1457	* Init paging.
1458	*
1459	* Since we need to check what mode the host is operating in before we can choose
1460	* the right paging functions for the host we have to delay this until R0 has
1461	* been initialized.
1462	*
1463	* @returns VBox status code.
1464	* @param pVM VM handle.
1465	*/
1466	static int pgmR3InitPaging(PVM pVM)
1467	{
1468	/*
1469	* Force a recalculation of modes and switcher so everyone gets notified.
1470	*/
1471	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1472	{
1473	PVMCPU pVCpu = &pVM->aCpus[i];
1474
1475	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1476	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1477	}
1478
1479	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1480
1481	/*
1482	* Allocate static mapping space for whatever the cr3 register
1483	* points to and in the case of PAE mode to the 4 PDs.
1484	*/
1485	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1486	if (RT_FAILURE(rc))
1487	{
1488	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1489	return rc;
1490	}
1491	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1492
1493	/*
1494	* Allocate pages for the three possible intermediate contexts
1495	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1496	* for the sake of simplicity. The AMD64 uses the PAE for the
1497	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1498	*
1499	* We assume that two page tables will be enought for the core code
1500	* mappings (HC virtual and identity).
1501	*/
1502	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1503	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1504	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1505	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1506	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1507	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1508	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1509	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1510	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1511	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1512	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1513	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1514
1515	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1516	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1517	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1518	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1519	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1520	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1521
1522	/*
1523	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1524	*/
1525	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1526	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1527	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1528
1529	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1530	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1531
1532	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1533	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1534	{
1535	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1536	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1537	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1538	}
1539
1540	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1541	{
1542	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1543	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1544	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1545	}
1546
1547	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1548	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1549	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1550	\| HCPhysInterPaePDPT64;
1551
1552	/*
1553	* Initialize paging workers and mode from current host mode
1554	* and the guest running in real mode.
1555	*/
1556	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1557	switch (pVM->pgm.s.enmHostMode)
1558	{
1559	case SUPPAGINGMODE_32_BIT:
1560	case SUPPAGINGMODE_32_BIT_GLOBAL:
1561	case SUPPAGINGMODE_PAE:
1562	case SUPPAGINGMODE_PAE_GLOBAL:
1563	case SUPPAGINGMODE_PAE_NX:
1564	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1565	break;
1566
1567	case SUPPAGINGMODE_AMD64:
1568	case SUPPAGINGMODE_AMD64_GLOBAL:
1569	case SUPPAGINGMODE_AMD64_NX:
1570	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1571	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1572	if (ARCH_BITS != 64)
1573	{
1574	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1575	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1576	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1577	}
1578	#endif
1579	break;
1580	default:
1581	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1582	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1583	}
1584	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1585	if (RT_SUCCESS(rc))
1586	{
1587	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1588	#if HC_ARCH_BITS == 64
1589	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1590	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1591	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1592	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1593	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1594	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1595	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1596	#endif
1597	return VINF_SUCCESS;
1598	}
1599
1600	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1601	return rc;
1602	}
1603
1604
1605	/**
1606	* Init statistics
1607	* @returns VBox status code.
1608	*/
1609	static int pgmR3InitStats(PVM pVM)
1610	{
1611	PPGM pPGM = &pVM->pgm.s;
1612	int rc;
1613
1614	/*
1615	* Release statistics.
1616	*/
1617	/* Common - misc variables */
1618	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1619	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1620	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1621	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1622	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1623	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1624	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1625	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1626	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1627	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1628	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1629	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1630	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1631	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1632	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1633	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1634	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1635
1636	STAM_REL_REG(pVM, &pPGM->StatLargePageAlloc, STAMTYPE_COUNTER, "/PGM/LargePage/Alloc", STAMUNIT_OCCURENCES, "The number of large pages we've used.");
1637	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1638	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1639	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1640
1641	/* Live save */
1642	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1643	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1644	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1645	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1646	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1647	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1648	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1649	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1650	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1651	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1652	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1653	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1654	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1655	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1656	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1657	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1658	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1659	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1660
1661	#ifdef VBOX_WITH_STATISTICS
1662
1663	# define PGM_REG_COUNTER(a, b, c) \
1664	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1665	AssertRC(rc);
1666
1667	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1668	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1669	AssertRC(rc);
1670
1671	# define PGM_REG_PROFILE(a, b, c) \
1672	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1673	AssertRC(rc);
1674
1675	# ifdef DEBUG_sandervl
1676	PGM_REG_COUNTER(&pPGM->StatRZFTPhysPageWrite, "/PGM/FT/RZ/PageWrite", "The number of times a physical page was written to (FT stats).");
1677	PGM_REG_COUNTER(&pPGM->StatR3FTPhysPageWrite, "/PGM/FT/R3/PageWrite", "The number of times a physical page was written to (FT stats).");
1678	# endif
1679
1680	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1681
1682	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1683	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1684	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1685	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1686
1687	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1688	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1689	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1690	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1691	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1692	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1693	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1694	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1695	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1696	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1697
1698	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1699	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1700	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1701	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1702	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1703	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1704
1705	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1706	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1707	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1708	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1709	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1710	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1711	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1712	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1713
1714	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1715	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1716	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1717	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1718
1719	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1720	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1721	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1722	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1723	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1724	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1725	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1726	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1727
1728	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1729	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1730	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1731	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1732	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1733	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1734
1735	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1736	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1737	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1738	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1739	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1740	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1741	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1742	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1743
1744	/* GC only: */
1745	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1746	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1747
1748	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1749	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1750	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1751	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1752	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1753	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1754	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1755	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1756
1757	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1758	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1759	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1760	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1761	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1762	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1763	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1764
1765	# undef PGM_REG_COUNTER
1766	# undef PGM_REG_PROFILE
1767	#endif
1768
1769	/*
1770	* Note! The layout below matches the member layout exactly!
1771	*/
1772
1773	/*
1774	* Common - stats
1775	*/
1776	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1777	{
1778	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1779
1780	#define PGM_REG_COUNTER(a, b, c) \
1781	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1782	AssertRC(rc);
1783	#define PGM_REG_PROFILE(a, b, c) \
1784	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1785	AssertRC(rc);
1786
1787	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1788
1789	#ifdef VBOX_WITH_STATISTICS
1790	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1791
1792	# if 0 /* rarely useful; leave for debugging. */
1793	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1794	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1795	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1796	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1797	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1798	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1799	# endif
1800	/* R0 only: */
1801	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1802	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1803
1804	/* RZ only: */
1805	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1806	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1807	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1808	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1809	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1810	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1811	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1812	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1813	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1814	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1815	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is releated to the guest mappings.");
1816	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1817	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1818	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1819	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1820	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1821	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1822	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1823	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1824	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1825	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1826	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysical, "/PGM/CPU%u/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1827	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysicalOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysicalOpt", "Number of the physical access handler traps using the optimization.");
1828	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1829	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1830	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1831	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1832	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1833	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1834	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1835	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1836	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1837	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1838	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1839	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1840	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1841	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1842	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1843	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1844	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1845	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1846	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1847	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1848	#if 0 /* rarely useful; leave for debugging. */
1849	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1850	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1851	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1852	#endif
1853	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1854	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1855	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1856	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1857	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1858
1859	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1860	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1861	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1862	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1863	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1864	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1865	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1866	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1867	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1868	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1869	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1870	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restorting to subset flushes.");
1871	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1872	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1873	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1874	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1875	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1876	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1877	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1878	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1879	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1880	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1881	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1882	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1883	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1884	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1885	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1886	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1887	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1888	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1889	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1890	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1891	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1892	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1893	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1894	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1895
1896	/* HC only: */
1897
1898	/* RZ & R3: */
1899	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1900	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1901	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1902	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1903	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1904	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1905	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1906	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1907	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1908	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1909	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1910	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1911	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1912	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1913	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1914	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1915	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1916	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1917	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1918	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1919	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1920	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1921	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1922	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1923	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1924	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1925	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1926	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1927	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1928	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1929	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1930	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1931	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1932	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1933	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1934	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1935	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1936	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1937	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1938	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1939	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1940	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1941	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1942	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1943	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1944	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1945	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1946
1947	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1948	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1949	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1950	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1951	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1952	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1953	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1954	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1955	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1956	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1957	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1958	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1959	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1960	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1961	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1962	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1963	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1964	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1965	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1966	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1967	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1968	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1969	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1970	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1971	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1972	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1973	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1974	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1975	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1976	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1977	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1978	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1979	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1980	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1981	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1982	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1983	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1984	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1985	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1986	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1987	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1988	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1989	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1990	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1991	#endif /* VBOX_WITH_STATISTICS */
1992
1993	#undef PGM_REG_PROFILE
1994	#undef PGM_REG_COUNTER
1995
1996	}
1997
1998	return VINF_SUCCESS;
1999	}
2000
2001
2002	/**
2003	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
2004	*
2005	* The dynamic mapping area will also be allocated and initialized at this
2006	* time. We could allocate it during PGMR3Init of course, but the mapping
2007	* wouldn't be allocated at that time preventing us from setting up the
2008	* page table entries with the dummy page.
2009	*
2010	* @returns VBox status code.
2011	* @param pVM VM handle.
2012	*/
2013	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2014	{
2015	RTGCPTR GCPtr;
2016	int rc;
2017
2018	/*
2019	* Reserve space for the dynamic mappings.
2020	*/
2021	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2022	if (RT_SUCCESS(rc))
2023	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2024
2025	if ( RT_SUCCESS(rc)
2026	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2027	{
2028	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2029	if (RT_SUCCESS(rc))
2030	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2031	}
2032	if (RT_SUCCESS(rc))
2033	{
2034	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2035	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2036	}
2037	return rc;
2038	}
2039
2040
2041	/**
2042	* Ring-3 init finalizing.
2043	*
2044	* @returns VBox status code.
2045	* @param pVM The VM handle.
2046	*/
2047	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2048	{
2049	int rc;
2050
2051	/*
2052	* Reserve space for the dynamic mappings.
2053	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2054	*/
2055	/* get the pointer to the page table entries. */
2056	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2057	AssertRelease(pMapping);
2058	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2059	const unsigned iPT = off >> X86_PD_SHIFT;
2060	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2061	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2062	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2063
2064	/* init cache area */
2065	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2066	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2067	{
2068	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2069	AssertRCReturn(rc, rc);
2070	}
2071
2072	/*
2073	* Determin the max physical address width (MAXPHYADDR) and apply it to
2074	* all the mask members and stuff.
2075	*/
2076	uint32_t cMaxPhysAddrWidth;
2077	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2078	if ( uMaxExtLeaf >= 0x80000008
2079	&& uMaxExtLeaf <= 0x80000fff)
2080	{
2081	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2082	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2083	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2084	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2085	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2086	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2087	}
2088	else
2089	{
2090	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2091	cMaxPhysAddrWidth = 48;
2092	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2093	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2094	}
2095
2096	pVM->pgm.s.GCPhysInvAddrMask = 0;
2097	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2098	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2099
2100	/*
2101	* Initialize the invalid paging entry masks, assuming NX is disabled.
2102	*/
2103	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2104	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2105	{
2106	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2107
2108	/** @todo The manuals are not entirely clear whether the physical
2109	* address width is relevant. See table 5-9 in the intel
2110	* manual vs the PDE4M descriptions. Write testcase (NP). */
2111	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2112	\| X86_PDE4M_MBZ_MASK;
2113
2114	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2115	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2116	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2117	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2118
2119	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2120	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2121	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2122	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2123	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2124	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2125	}
2126
2127	/*
2128	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2129	* Intel only goes up to 36 bits, so we stick to 36 as well.
2130	* Update: More recent intel manuals specifies 40 bits just like AMD.
2131	*/
2132	uint32_t u32Dummy, u32Features;
2133	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2134	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2135	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2136	else
2137	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2138
2139	/*
2140	* Allocate memory if we're supposed to do that.
2141	*/
2142	if (pVM->pgm.s.fRamPreAlloc)
2143	rc = pgmR3PhysRamPreAllocate(pVM);
2144
2145	#ifdef DEBUG_sandervl
2146	rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, pgmR3PhysWriteCountTMCallback, NULL, "Physical page write counting timer", &pVM->pgm.s.pPhysWritesCountTimer);
2147	AssertRC(rc);
2148	#endif
2149
2150	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2151	return rc;
2152	}
2153
2154
2155	/**
2156	* Applies relocations to data and code managed by this component.
2157	*
2158	* This function will be called at init and whenever the VMM need to relocate it
2159	* self inside the GC.
2160	*
2161	* @param pVM The VM.
2162	* @param offDelta Relocation delta relative to old location.
2163	*/
2164	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2165	{
2166	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2167
2168	/*
2169	* Paging stuff.
2170	*/
2171	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2172
2173	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2174
2175	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2176	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2177	{
2178	PVMCPU pVCpu = &pVM->aCpus[i];
2179
2180	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2181
2182	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2183	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2184	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2185	}
2186
2187	/*
2188	* Trees.
2189	*/
2190	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2191
2192	/*
2193	* Ram ranges.
2194	*/
2195	if (pVM->pgm.s.pRamRangesR3)
2196	{
2197	/* Update the pSelfRC pointers and relink them. */
2198	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2199	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2200	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2201	pgmR3PhysRelinkRamRanges(pVM);
2202	}
2203
2204	/*
2205	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2206	* be mapped and thus not included in the above exercise.
2207	*/
2208	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2209	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2210	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2211
2212	/*
2213	* Update the two page directories with all page table mappings.
2214	* (One or more of them have changed, that's why we're here.)
2215	*/
2216	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2217	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2218	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2219
2220	/* Relocate GC addresses of Page Tables. */
2221	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2222	{
2223	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2224	{
2225	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2226	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2227	}
2228	}
2229
2230	/*
2231	* Dynamic page mapping area.
2232	*/
2233	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2234	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2235	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2236
2237	if (pVM->pgm.s.pRCDynMap)
2238	{
2239	pVM->pgm.s.pRCDynMap += offDelta;
2240	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2241
2242	pDynMap->paPages += offDelta;
2243	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2244
2245	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2246	{
2247	paPages[iPage].pvPage += offDelta;
2248	paPages[iPage].uPte.pv += offDelta;
2249	}
2250	}
2251
2252	/*
2253	* The Zero page.
2254	*/
2255	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2256	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2257	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2258	#else
2259	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2260	#endif
2261
2262	/*
2263	* Physical and virtual handlers.
2264	*/
2265	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2266	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2267	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2268	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2269
2270	/*
2271	* The page pool.
2272	*/
2273	pgmR3PoolRelocate(pVM);
2274
2275	#ifdef VBOX_WITH_STATISTICS
2276	/*
2277	* Statistics.
2278	*/
2279	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2280	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2281	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2282	#endif
2283	}
2284
2285
2286	/**
2287	* Callback function for relocating a physical access handler.
2288	*
2289	* @returns 0 (continue enum)
2290	* @param pNode Pointer to a PGMPHYSHANDLER node.
2291	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2292	* not certain the delta will fit in a void pointer for all possible configs.
2293	*/
2294	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2295	{
2296	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2297	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2298	if (pHandler->pfnHandlerRC)
2299	pHandler->pfnHandlerRC += offDelta;
2300	if (pHandler->pvUserRC >= 0x10000)
2301	pHandler->pvUserRC += offDelta;
2302	return 0;
2303	}
2304
2305
2306	/**
2307	* Callback function for relocating a virtual access handler.
2308	*
2309	* @returns 0 (continue enum)
2310	* @param pNode Pointer to a PGMVIRTHANDLER node.
2311	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2312	* not certain the delta will fit in a void pointer for all possible configs.
2313	*/
2314	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2315	{
2316	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2317	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2318	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2319	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2320	Assert(pHandler->pfnHandlerRC);
2321	pHandler->pfnHandlerRC += offDelta;
2322	return 0;
2323	}
2324
2325
2326	/**
2327	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2328	*
2329	* @returns 0 (continue enum)
2330	* @param pNode Pointer to a PGMVIRTHANDLER node.
2331	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2332	* not certain the delta will fit in a void pointer for all possible configs.
2333	*/
2334	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2335	{
2336	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2337	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2338	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2339	Assert(pHandler->pfnHandlerRC);
2340	pHandler->pfnHandlerRC += offDelta;
2341	return 0;
2342	}
2343
2344
2345	/**
2346	* Resets a virtual CPU when unplugged.
2347	*
2348	* @param pVM The VM handle.
2349	* @param pVCpu The virtual CPU handle.
2350	*/
2351	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2352	{
2353	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2354	AssertRC(rc);
2355
2356	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2357	AssertRC(rc);
2358
2359	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2360
2361	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2362
2363	/*
2364	* Re-init other members.
2365	*/
2366	pVCpu->pgm.s.fA20Enabled = true;
2367
2368	/*
2369	* Clear the FFs PGM owns.
2370	*/
2371	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2372	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2373	}
2374
2375
2376	/**
2377	* The VM is being reset.
2378	*
2379	* For the PGM component this means that any PD write monitors
2380	* needs to be removed.
2381	*
2382	* @param pVM VM handle.
2383	*/
2384	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2385	{
2386	int rc;
2387
2388	LogFlow(("PGMR3Reset:\n"));
2389	VM_ASSERT_EMT(pVM);
2390
2391	pgmLock(pVM);
2392
2393	/*
2394	* Unfix any fixed mappings and disable CR3 monitoring.
2395	*/
2396	pVM->pgm.s.fMappingsFixed = false;
2397	pVM->pgm.s.fMappingsFixedRestored = false;
2398	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2399	pVM->pgm.s.cbMappingFixed = 0;
2400
2401	/*
2402	* Exit the guest paging mode before the pgm pool gets reset.
2403	* Important to clean up the amd64 case.
2404	*/
2405	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2406	{
2407	PVMCPU pVCpu = &pVM->aCpus[i];
2408	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2409	AssertRC(rc);
2410	}
2411
2412	#ifdef DEBUG
2413	DBGFR3InfoLog(pVM, "mappings", NULL);
2414	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2415	#endif
2416
2417	/*
2418	* Switch mode back to real mode. (before resetting the pgm pool!)
2419	*/
2420	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2421	{
2422	PVMCPU pVCpu = &pVM->aCpus[i];
2423
2424	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2425	AssertRC(rc);
2426
2427	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2428	}
2429
2430	/*
2431	* Reset the shadow page pool.
2432	*/
2433	pgmR3PoolReset(pVM);
2434
2435	/*
2436	* Re-init various other members and clear the FFs that PGM owns.
2437	*/
2438	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2439	{
2440	PVMCPU pVCpu = &pVM->aCpus[i];
2441
2442	pVCpu->pgm.s.fA20Enabled = true;
2443	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2444	PGMNotifyNxeChanged(pVCpu, false);
2445
2446	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2447	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2448	}
2449
2450	/*
2451	* Reset (zero) RAM and shadow ROM pages.
2452	*/
2453	rc = pgmR3PhysRamReset(pVM);
2454	if (RT_SUCCESS(rc))
2455	rc = pgmR3PhysRomReset(pVM);
2456
2457
2458	pgmUnlock(pVM);
2459	AssertReleaseRC(rc);
2460	}
2461
2462
2463	#ifdef VBOX_STRICT
2464	/**
2465	* VM state change callback for clearing fNoMorePhysWrites after
2466	* a snapshot has been created.
2467	*/
2468	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2469	{
2470	if ( enmState == VMSTATE_RUNNING
2471	\|\| enmState == VMSTATE_RESUMING)
2472	pVM->pgm.s.fNoMorePhysWrites = false;
2473	}
2474	#endif
2475
2476
2477	/**
2478	* Terminates the PGM.
2479	*
2480	* @returns VBox status code.
2481	* @param pVM Pointer to VM structure.
2482	*/
2483	VMMR3DECL(int) PGMR3Term(PVM pVM)
2484	{
2485	/* Must free shared pages here. */
2486	pgmLock(pVM);
2487	pgmR3PhysRamTerm(pVM);
2488	pgmR3PhysRomTerm(pVM);
2489	pgmUnlock(pVM);
2490
2491	PGMDeregisterStringFormatTypes();
2492	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2493	}
2494
2495
2496	/**
2497	* Terminates the per-VCPU PGM.
2498	*
2499	* Termination means cleaning up and freeing all resources,
2500	* the VM it self is at this point powered off or suspended.
2501	*
2502	* @returns VBox status code.
2503	* @param pVM The VM to operate on.
2504	*/
2505	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2506	{
2507	return 0;
2508	}
2509
2510
2511	/**
2512	* Show paging mode.
2513	*
2514	* @param pVM VM Handle.
2515	* @param pHlp The info helpers.
2516	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2517	*/
2518	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2519	{
2520	/* digest argument. */
2521	bool fGuest, fShadow, fHost;
2522	if (pszArgs)
2523	pszArgs = RTStrStripL(pszArgs);
2524	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2525	fShadow = fHost = fGuest = true;
2526	else
2527	{
2528	fShadow = fHost = fGuest = false;
2529	if (strstr(pszArgs, "guest"))
2530	fGuest = true;
2531	if (strstr(pszArgs, "shadow"))
2532	fShadow = true;
2533	if (strstr(pszArgs, "host"))
2534	fHost = true;
2535	}
2536
2537	/** @todo SMP support! */
2538	/* print info. */
2539	if (fGuest)
2540	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2541	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2542	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2543	if (fShadow)
2544	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2545	if (fHost)
2546	{
2547	const char *psz;
2548	switch (pVM->pgm.s.enmHostMode)
2549	{
2550	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2551	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2552	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2553	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2554	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2555	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2556	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2557	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2558	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2559	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2560	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2561	default: psz = "unknown"; break;
2562	}
2563	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2564	}
2565	}
2566
2567
2568	/**
2569	* Dump registered MMIO ranges to the log.
2570	*
2571	* @param pVM VM Handle.
2572	* @param pHlp The info helpers.
2573	* @param pszArgs Arguments, ignored.
2574	*/
2575	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2576	{
2577	NOREF(pszArgs);
2578	pHlp->pfnPrintf(pHlp,
2579	"RAM ranges (pVM=%p)\n"
2580	"%.s %.s\n",
2581	pVM,
2582	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2583	sizeof(RTHCPTR) * 2, "pvHC ");
2584
2585	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2586	pHlp->pfnPrintf(pHlp,
2587	"%RGp-%RGp %RHv %s\n",
2588	pCur->GCPhys,
2589	pCur->GCPhysLast,
2590	pCur->pvR3,
2591	pCur->pszDesc);
2592	}
2593
2594	/**
2595	* Dump the page directory to the log.
2596	*
2597	* @param pVM VM Handle.
2598	* @param pHlp The info helpers.
2599	* @param pszArgs Arguments, ignored.
2600	*/
2601	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2602	{
2603	/** @todo SMP support!! */
2604	PVMCPU pVCpu = &pVM->aCpus[0];
2605
2606	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2607	/* Big pages supported? */
2608	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2609
2610	/* Global pages supported? */
2611	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2612
2613	NOREF(pszArgs);
2614
2615	/*
2616	* Get page directory addresses.
2617	*/
2618	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2619	Assert(pPDSrc);
2620	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2621
2622	/*
2623	* Iterate the page directory.
2624	*/
2625	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2626	{
2627	X86PDE PdeSrc = pPDSrc->a[iPD];
2628	if (PdeSrc.n.u1Present)
2629	{
2630	if (PdeSrc.b.u1Size && fPSE)
2631	pHlp->pfnPrintf(pHlp,
2632	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2633	iPD,
2634	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2635	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2636	else
2637	pHlp->pfnPrintf(pHlp,
2638	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2639	iPD,
2640	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2641	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2642	}
2643	}
2644	}
2645
2646
2647	/**
2648	* Service a VMMCALLRING3_PGM_LOCK call.
2649	*
2650	* @returns VBox status code.
2651	* @param pVM The VM handle.
2652	*/
2653	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2654	{
2655	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2656	AssertRC(rc);
2657	return rc;
2658	}
2659
2660
2661	/**
2662	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2663	*
2664	* @returns PGM_TYPE_*.
2665	* @param pgmMode The mode value to convert.
2666	*/
2667	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2668	{
2669	switch (pgmMode)
2670	{
2671	case PGMMODE_REAL: return PGM_TYPE_REAL;
2672	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2673	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2674	case PGMMODE_PAE:
2675	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2676	case PGMMODE_AMD64:
2677	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2678	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2679	case PGMMODE_EPT: return PGM_TYPE_EPT;
2680	default:
2681	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2682	}
2683	}
2684
2685
2686	/**
2687	* Gets the index into the paging mode data array of a SHW+GST mode.
2688	*
2689	* @returns PGM::paPagingData index.
2690	* @param uShwType The shadow paging mode type.
2691	* @param uGstType The guest paging mode type.
2692	*/
2693	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2694	{
2695	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2696	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2697	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2698	+ (uGstType - PGM_TYPE_REAL);
2699	}
2700
2701
2702	/**
2703	* Gets the index into the paging mode data array of a SHW+GST mode.
2704	*
2705	* @returns PGM::paPagingData index.
2706	* @param enmShw The shadow paging mode.
2707	* @param enmGst The guest paging mode.
2708	*/
2709	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2710	{
2711	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2712	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2713	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2714	}
2715
2716
2717	/**
2718	* Calculates the max data index.
2719	* @returns The number of entries in the paging data array.
2720	*/
2721	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2722	{
2723	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2724	}
2725
2726
2727	/**
2728	* Initializes the paging mode data kept in PGM::paModeData.
2729	*
2730	* @param pVM The VM handle.
2731	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2732	* This is used early in the init process to avoid trouble with PDM
2733	* not being initialized yet.
2734	*/
2735	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2736	{
2737	PPGMMODEDATA pModeData;
2738	int rc;
2739
2740	/*
2741	* Allocate the array on the first call.
2742	*/
2743	if (!pVM->pgm.s.paModeData)
2744	{
2745	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2746	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2747	}
2748
2749	/*
2750	* Initialize the array entries.
2751	*/
2752	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2753	pModeData->uShwType = PGM_TYPE_32BIT;
2754	pModeData->uGstType = PGM_TYPE_REAL;
2755	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2756	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2757	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2758
2759	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2760	pModeData->uShwType = PGM_TYPE_32BIT;
2761	pModeData->uGstType = PGM_TYPE_PROT;
2762	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2763	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2764	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2765
2766	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2767	pModeData->uShwType = PGM_TYPE_32BIT;
2768	pModeData->uGstType = PGM_TYPE_32BIT;
2769	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2770	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2771	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2772
2773	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2774	pModeData->uShwType = PGM_TYPE_PAE;
2775	pModeData->uGstType = PGM_TYPE_REAL;
2776	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2777	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2778	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2779
2780	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2781	pModeData->uShwType = PGM_TYPE_PAE;
2782	pModeData->uGstType = PGM_TYPE_PROT;
2783	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2784	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2785	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2786
2787	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2788	pModeData->uShwType = PGM_TYPE_PAE;
2789	pModeData->uGstType = PGM_TYPE_32BIT;
2790	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2791	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2792	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2793
2794	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2795	pModeData->uShwType = PGM_TYPE_PAE;
2796	pModeData->uGstType = PGM_TYPE_PAE;
2797	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2798	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2799	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2800
2801	#ifdef VBOX_WITH_64_BITS_GUESTS
2802	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2803	pModeData->uShwType = PGM_TYPE_AMD64;
2804	pModeData->uGstType = PGM_TYPE_AMD64;
2805	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2806	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2807	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2808	#endif
2809
2810	/* The nested paging mode. */
2811	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2812	pModeData->uShwType = PGM_TYPE_NESTED;
2813	pModeData->uGstType = PGM_TYPE_REAL;
2814	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2815	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2816
2817	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2818	pModeData->uShwType = PGM_TYPE_NESTED;
2819	pModeData->uGstType = PGM_TYPE_PROT;
2820	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2821	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2822
2823	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2824	pModeData->uShwType = PGM_TYPE_NESTED;
2825	pModeData->uGstType = PGM_TYPE_32BIT;
2826	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2827	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2828
2829	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2830	pModeData->uShwType = PGM_TYPE_NESTED;
2831	pModeData->uGstType = PGM_TYPE_PAE;
2832	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2833	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2834
2835	#ifdef VBOX_WITH_64_BITS_GUESTS
2836	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2837	pModeData->uShwType = PGM_TYPE_NESTED;
2838	pModeData->uGstType = PGM_TYPE_AMD64;
2839	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2840	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2841	#endif
2842
2843	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2844	switch (pVM->pgm.s.enmHostMode)
2845	{
2846	#if HC_ARCH_BITS == 32
2847	case SUPPAGINGMODE_32_BIT:
2848	case SUPPAGINGMODE_32_BIT_GLOBAL:
2849	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2850	{
2851	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2852	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2853	}
2854	# ifdef VBOX_WITH_64_BITS_GUESTS
2855	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2856	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2857	# endif
2858	break;
2859
2860	case SUPPAGINGMODE_PAE:
2861	case SUPPAGINGMODE_PAE_NX:
2862	case SUPPAGINGMODE_PAE_GLOBAL:
2863	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2864	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2865	{
2866	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2867	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2868	}
2869	# ifdef VBOX_WITH_64_BITS_GUESTS
2870	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2871	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2872	# endif
2873	break;
2874	#endif /* HC_ARCH_BITS == 32 */
2875
2876	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2877	case SUPPAGINGMODE_AMD64:
2878	case SUPPAGINGMODE_AMD64_GLOBAL:
2879	case SUPPAGINGMODE_AMD64_NX:
2880	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2881	# ifdef VBOX_WITH_64_BITS_GUESTS
2882	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2883	# else
2884	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2885	# endif
2886	{
2887	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2888	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2889	}
2890	break;
2891	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2892
2893	default:
2894	AssertFailed();
2895	break;
2896	}
2897
2898	/* Extended paging (EPT) / Intel VT-x */
2899	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2900	pModeData->uShwType = PGM_TYPE_EPT;
2901	pModeData->uGstType = PGM_TYPE_REAL;
2902	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2903	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2904	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2905
2906	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2907	pModeData->uShwType = PGM_TYPE_EPT;
2908	pModeData->uGstType = PGM_TYPE_PROT;
2909	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2910	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2911	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2912
2913	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2914	pModeData->uShwType = PGM_TYPE_EPT;
2915	pModeData->uGstType = PGM_TYPE_32BIT;
2916	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2917	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2918	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2919
2920	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2921	pModeData->uShwType = PGM_TYPE_EPT;
2922	pModeData->uGstType = PGM_TYPE_PAE;
2923	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2924	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2925	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2926
2927	#ifdef VBOX_WITH_64_BITS_GUESTS
2928	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2929	pModeData->uShwType = PGM_TYPE_EPT;
2930	pModeData->uGstType = PGM_TYPE_AMD64;
2931	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2932	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2933	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2934	#endif
2935	return VINF_SUCCESS;
2936	}
2937
2938
2939	/**
2940	* Switch to different (or relocated in the relocate case) mode data.
2941	*
2942	* @param pVM The VM handle.
2943	* @param pVCpu The VMCPU to operate on.
2944	* @param enmShw The the shadow paging mode.
2945	* @param enmGst The the guest paging mode.
2946	*/
2947	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2948	{
2949	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2950
2951	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2952	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2953
2954	/* shadow */
2955	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2956	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2957	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2958	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2959	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2960
2961	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2962	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2963
2964	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2965	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2966
2967
2968	/* guest */
2969	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2970	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2971	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2972	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2973	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2974	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2975	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2976	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2977	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2978	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2979	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2980	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2981
2982	/* both */
2983	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2984	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2985	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2986	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2987	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2988	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2989	#ifdef VBOX_STRICT
2990	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2991	#endif
2992	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2993	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2994
2995	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2996	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2997	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2998	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2999	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3000	#ifdef VBOX_STRICT
3001	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3002	#endif
3003	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3004	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3005
3006	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3007	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3008	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3009	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3010	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3011	#ifdef VBOX_STRICT
3012	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3013	#endif
3014	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3015	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3016	}
3017
3018
3019	/**
3020	* Calculates the shadow paging mode.
3021	*
3022	* @returns The shadow paging mode.
3023	* @param pVM VM handle.
3024	* @param enmGuestMode The guest mode.
3025	* @param enmHostMode The host mode.
3026	* @param enmShadowMode The current shadow mode.
3027	* @param penmSwitcher Where to store the switcher to use.
3028	* VMMSWITCHER_INVALID means no change.
3029	*/
3030	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3031	{
3032	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3033	switch (enmGuestMode)
3034	{
3035	/*
3036	* When switching to real or protected mode we don't change
3037	* anything since it's likely that we'll switch back pretty soon.
3038	*
3039	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3040	* and is supposed to determine which shadow paging and switcher to
3041	* use during init.
3042	*/
3043	case PGMMODE_REAL:
3044	case PGMMODE_PROTECTED:
3045	if ( enmShadowMode != PGMMODE_INVALID
3046	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3047	break; /* (no change) */
3048
3049	switch (enmHostMode)
3050	{
3051	case SUPPAGINGMODE_32_BIT:
3052	case SUPPAGINGMODE_32_BIT_GLOBAL:
3053	enmShadowMode = PGMMODE_32_BIT;
3054	enmSwitcher = VMMSWITCHER_32_TO_32;
3055	break;
3056
3057	case SUPPAGINGMODE_PAE:
3058	case SUPPAGINGMODE_PAE_NX:
3059	case SUPPAGINGMODE_PAE_GLOBAL:
3060	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3061	enmShadowMode = PGMMODE_PAE;
3062	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3063	#ifdef DEBUG_bird
3064	if (RTEnvExist("VBOX_32BIT"))
3065	{
3066	enmShadowMode = PGMMODE_32_BIT;
3067	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3068	}
3069	#endif
3070	break;
3071
3072	case SUPPAGINGMODE_AMD64:
3073	case SUPPAGINGMODE_AMD64_GLOBAL:
3074	case SUPPAGINGMODE_AMD64_NX:
3075	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3076	enmShadowMode = PGMMODE_PAE;
3077	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3078	#ifdef DEBUG_bird
3079	if (RTEnvExist("VBOX_32BIT"))
3080	{
3081	enmShadowMode = PGMMODE_32_BIT;
3082	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3083	}
3084	#endif
3085	break;
3086
3087	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3088	}
3089	break;
3090
3091	case PGMMODE_32_BIT:
3092	switch (enmHostMode)
3093	{
3094	case SUPPAGINGMODE_32_BIT:
3095	case SUPPAGINGMODE_32_BIT_GLOBAL:
3096	enmShadowMode = PGMMODE_32_BIT;
3097	enmSwitcher = VMMSWITCHER_32_TO_32;
3098	break;
3099
3100	case SUPPAGINGMODE_PAE:
3101	case SUPPAGINGMODE_PAE_NX:
3102	case SUPPAGINGMODE_PAE_GLOBAL:
3103	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3104	enmShadowMode = PGMMODE_PAE;
3105	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3106	#ifdef DEBUG_bird
3107	if (RTEnvExist("VBOX_32BIT"))
3108	{
3109	enmShadowMode = PGMMODE_32_BIT;
3110	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3111	}
3112	#endif
3113	break;
3114
3115	case SUPPAGINGMODE_AMD64:
3116	case SUPPAGINGMODE_AMD64_GLOBAL:
3117	case SUPPAGINGMODE_AMD64_NX:
3118	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3119	enmShadowMode = PGMMODE_PAE;
3120	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3121	#ifdef DEBUG_bird
3122	if (RTEnvExist("VBOX_32BIT"))
3123	{
3124	enmShadowMode = PGMMODE_32_BIT;
3125	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3126	}
3127	#endif
3128	break;
3129
3130	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3131	}
3132	break;
3133
3134	case PGMMODE_PAE:
3135	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3136	switch (enmHostMode)
3137	{
3138	case SUPPAGINGMODE_32_BIT:
3139	case SUPPAGINGMODE_32_BIT_GLOBAL:
3140	enmShadowMode = PGMMODE_PAE;
3141	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3142	break;
3143
3144	case SUPPAGINGMODE_PAE:
3145	case SUPPAGINGMODE_PAE_NX:
3146	case SUPPAGINGMODE_PAE_GLOBAL:
3147	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3148	enmShadowMode = PGMMODE_PAE;
3149	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3150	break;
3151
3152	case SUPPAGINGMODE_AMD64:
3153	case SUPPAGINGMODE_AMD64_GLOBAL:
3154	case SUPPAGINGMODE_AMD64_NX:
3155	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3156	enmShadowMode = PGMMODE_PAE;
3157	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3158	break;
3159
3160	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3161	}
3162	break;
3163
3164	case PGMMODE_AMD64:
3165	case PGMMODE_AMD64_NX:
3166	switch (enmHostMode)
3167	{
3168	case SUPPAGINGMODE_32_BIT:
3169	case SUPPAGINGMODE_32_BIT_GLOBAL:
3170	enmShadowMode = PGMMODE_AMD64;
3171	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3172	break;
3173
3174	case SUPPAGINGMODE_PAE:
3175	case SUPPAGINGMODE_PAE_NX:
3176	case SUPPAGINGMODE_PAE_GLOBAL:
3177	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3178	enmShadowMode = PGMMODE_AMD64;
3179	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3180	break;
3181
3182	case SUPPAGINGMODE_AMD64:
3183	case SUPPAGINGMODE_AMD64_GLOBAL:
3184	case SUPPAGINGMODE_AMD64_NX:
3185	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3186	enmShadowMode = PGMMODE_AMD64;
3187	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3188	break;
3189
3190	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3191	}
3192	break;
3193
3194
3195	default:
3196	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3197	*penmSwitcher = VMMSWITCHER_INVALID;
3198	return PGMMODE_INVALID;
3199	}
3200	/* Override the shadow mode is nested paging is active. */
3201	pVM->pgm.s.fNestedPaging = HWACCMIsNestedPagingActive(pVM);
3202	if (pVM->pgm.s.fNestedPaging)
3203	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3204
3205	*penmSwitcher = enmSwitcher;
3206	return enmShadowMode;
3207	}
3208
3209
3210	/**
3211	* Performs the actual mode change.
3212	* This is called by PGMChangeMode and pgmR3InitPaging().
3213	*
3214	* @returns VBox status code. May suspend or power off the VM on error, but this
3215	* will trigger using FFs and not status codes.
3216	*
3217	* @param pVM VM handle.
3218	* @param pVCpu The VMCPU to operate on.
3219	* @param enmGuestMode The new guest mode. This is assumed to be different from
3220	* the current mode.
3221	*/
3222	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3223	{
3224	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3225	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3226
3227	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3228	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3229
3230	/*
3231	* Calc the shadow mode and switcher.
3232	*/
3233	VMMSWITCHER enmSwitcher;
3234	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3235
3236	#ifdef VBOX_WITH_RAW_MODE
3237	if (enmSwitcher != VMMSWITCHER_INVALID)
3238	{
3239	/*
3240	* Select new switcher.
3241	*/
3242	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3243	if (RT_FAILURE(rc))
3244	{
3245	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3246	return rc;
3247	}
3248	}
3249	#endif
3250
3251	/*
3252	* Exit old mode(s).
3253	*/
3254	#if HC_ARCH_BITS == 32
3255	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3256	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3257	&& enmShadowMode == PGMMODE_NESTED);
3258	#else
3259	const bool fForceShwEnterExit = false;
3260	#endif
3261	/* shadow */
3262	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3263	\|\| fForceShwEnterExit)
3264	{
3265	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3266	if (PGM_SHW_PFN(Exit, pVCpu))
3267	{
3268	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3269	if (RT_FAILURE(rc))
3270	{
3271	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3272	return rc;
3273	}
3274	}
3275
3276	}
3277	else
3278	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3279
3280	/* guest */
3281	if (PGM_GST_PFN(Exit, pVCpu))
3282	{
3283	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3284	if (RT_FAILURE(rc))
3285	{
3286	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3287	return rc;
3288	}
3289	}
3290
3291	/*
3292	* Load new paging mode data.
3293	*/
3294	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3295
3296	/*
3297	* Enter new shadow mode (if changed).
3298	*/
3299	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3300	\|\| fForceShwEnterExit)
3301	{
3302	int rc;
3303	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3304	switch (enmShadowMode)
3305	{
3306	case PGMMODE_32_BIT:
3307	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3308	break;
3309	case PGMMODE_PAE:
3310	case PGMMODE_PAE_NX:
3311	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3312	break;
3313	case PGMMODE_AMD64:
3314	case PGMMODE_AMD64_NX:
3315	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3316	break;
3317	case PGMMODE_NESTED:
3318	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3319	break;
3320	case PGMMODE_EPT:
3321	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3322	break;
3323	case PGMMODE_REAL:
3324	case PGMMODE_PROTECTED:
3325	default:
3326	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3327	return VERR_INTERNAL_ERROR;
3328	}
3329	if (RT_FAILURE(rc))
3330	{
3331	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3332	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3333	return rc;
3334	}
3335	}
3336
3337	/*
3338	* Always flag the necessary updates
3339	*/
3340	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3341
3342	/*
3343	* Enter the new guest and shadow+guest modes.
3344	*/
3345	int rc = -1;
3346	int rc2 = -1;
3347	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3348	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3349	switch (enmGuestMode)
3350	{
3351	case PGMMODE_REAL:
3352	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3353	switch (pVCpu->pgm.s.enmShadowMode)
3354	{
3355	case PGMMODE_32_BIT:
3356	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3357	break;
3358	case PGMMODE_PAE:
3359	case PGMMODE_PAE_NX:
3360	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3361	break;
3362	case PGMMODE_NESTED:
3363	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3364	break;
3365	case PGMMODE_EPT:
3366	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3367	break;
3368	case PGMMODE_AMD64:
3369	case PGMMODE_AMD64_NX:
3370	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3371	default: AssertFailed(); break;
3372	}
3373	break;
3374
3375	case PGMMODE_PROTECTED:
3376	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3377	switch (pVCpu->pgm.s.enmShadowMode)
3378	{
3379	case PGMMODE_32_BIT:
3380	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3381	break;
3382	case PGMMODE_PAE:
3383	case PGMMODE_PAE_NX:
3384	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3385	break;
3386	case PGMMODE_NESTED:
3387	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3388	break;
3389	case PGMMODE_EPT:
3390	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3391	break;
3392	case PGMMODE_AMD64:
3393	case PGMMODE_AMD64_NX:
3394	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3395	default: AssertFailed(); break;
3396	}
3397	break;
3398
3399	case PGMMODE_32_BIT:
3400	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3401	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3402	switch (pVCpu->pgm.s.enmShadowMode)
3403	{
3404	case PGMMODE_32_BIT:
3405	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3406	break;
3407	case PGMMODE_PAE:
3408	case PGMMODE_PAE_NX:
3409	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3410	break;
3411	case PGMMODE_NESTED:
3412	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3413	break;
3414	case PGMMODE_EPT:
3415	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3416	break;
3417	case PGMMODE_AMD64:
3418	case PGMMODE_AMD64_NX:
3419	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3420	default: AssertFailed(); break;
3421	}
3422	break;
3423
3424	case PGMMODE_PAE_NX:
3425	case PGMMODE_PAE:
3426	{
3427	uint32_t u32Dummy, u32Features;
3428
3429	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3430	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3431	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3432	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3433
3434	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3435	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3436	switch (pVCpu->pgm.s.enmShadowMode)
3437	{
3438	case PGMMODE_PAE:
3439	case PGMMODE_PAE_NX:
3440	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3441	break;
3442	case PGMMODE_NESTED:
3443	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3444	break;
3445	case PGMMODE_EPT:
3446	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3447	break;
3448	case PGMMODE_32_BIT:
3449	case PGMMODE_AMD64:
3450	case PGMMODE_AMD64_NX:
3451	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3452	default: AssertFailed(); break;
3453	}
3454	break;
3455	}
3456
3457	#ifdef VBOX_WITH_64_BITS_GUESTS
3458	case PGMMODE_AMD64_NX:
3459	case PGMMODE_AMD64:
3460	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3461	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3462	switch (pVCpu->pgm.s.enmShadowMode)
3463	{
3464	case PGMMODE_AMD64:
3465	case PGMMODE_AMD64_NX:
3466	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3467	break;
3468	case PGMMODE_NESTED:
3469	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3470	break;
3471	case PGMMODE_EPT:
3472	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3473	break;
3474	case PGMMODE_32_BIT:
3475	case PGMMODE_PAE:
3476	case PGMMODE_PAE_NX:
3477	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3478	default: AssertFailed(); break;
3479	}
3480	break;
3481	#endif
3482
3483	default:
3484	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3485	rc = VERR_NOT_IMPLEMENTED;
3486	break;
3487	}
3488
3489	/* status codes. */
3490	AssertRC(rc);
3491	AssertRC(rc2);
3492	if (RT_SUCCESS(rc))
3493	{
3494	rc = rc2;
3495	if (RT_SUCCESS(rc)) /* no informational status codes. */
3496	rc = VINF_SUCCESS;
3497	}
3498
3499	/* Notify HWACCM as well. */
3500	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3501	return rc;
3502	}
3503
3504
3505	/**
3506	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3507	*
3508	* @returns VBox status code, fully asserted.
3509	* @param pVM The VM handle.
3510	* @param pVCpu The VMCPU to operate on.
3511	*/
3512	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3513	{
3514	/* Unmap the old CR3 value before flushing everything. */
3515	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3516	AssertRC(rc);
3517
3518	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3519	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3520	AssertRC(rc);
3521	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3522	return rc;
3523	}
3524
3525
3526	/**
3527	* Called by pgmPoolFlushAllInt after flushing the pool.
3528	*
3529	* @returns VBox status code, fully asserted.
3530	* @param pVM The VM handle.
3531	* @param pVCpu The VMCPU to operate on.
3532	*/
3533	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3534	{
3535	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3536	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3537	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3538	AssertRCReturn(rc, rc);
3539	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3540
3541	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3542	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3543	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3544	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3545	return rc;
3546	}
3547
3548
3549	/**
3550	* Dumps a PAE shadow page table.
3551	*
3552	* @returns VBox status code (VINF_SUCCESS).
3553	* @param pVM The VM handle.
3554	* @param pPT Pointer to the page table.
3555	* @param u64Address The virtual address of the page table starts.
3556	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3557	* @param cMaxDepth The maxium depth.
3558	* @param pHlp Pointer to the output functions.
3559	*/
3560	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3561	{
3562	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3563	{
3564	X86PTEPAE Pte = pPT->a[i];
3565	if (Pte.n.u1Present)
3566	{
3567	pHlp->pfnPrintf(pHlp,
3568	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3569	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3570	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3571	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3572	Pte.n.u1Write ? 'W' : 'R',
3573	Pte.n.u1User ? 'U' : 'S',
3574	Pte.n.u1Accessed ? 'A' : '-',
3575	Pte.n.u1Dirty ? 'D' : '-',
3576	Pte.n.u1Global ? 'G' : '-',
3577	Pte.n.u1WriteThru ? "WT" : "--",
3578	Pte.n.u1CacheDisable? "CD" : "--",
3579	Pte.n.u1PAT ? "AT" : "--",
3580	Pte.n.u1NoExecute ? "NX" : "--",
3581	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3582	Pte.u & RT_BIT(10) ? '1' : '0',
3583	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3584	Pte.u & X86_PTE_PAE_PG_MASK);
3585	}
3586	}
3587	return VINF_SUCCESS;
3588	}
3589
3590
3591	/**
3592	* Dumps a PAE shadow page directory table.
3593	*
3594	* @returns VBox status code (VINF_SUCCESS).
3595	* @param pVM The VM handle.
3596	* @param HCPhys The physical address of the page directory table.
3597	* @param u64Address The virtual address of the page table starts.
3598	* @param cr4 The CR4, PSE is currently used.
3599	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3600	* @param cMaxDepth The maxium depth.
3601	* @param pHlp Pointer to the output functions.
3602	*/
3603	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3604	{
3605	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3606	if (!pPD)
3607	{
3608	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3609	fLongMode ? 16 : 8, u64Address, HCPhys);
3610	return VERR_INVALID_PARAMETER;
3611	}
3612	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3613
3614	int rc = VINF_SUCCESS;
3615	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3616	{
3617	X86PDEPAE Pde = pPD->a[i];
3618	if (Pde.n.u1Present)
3619	{
3620	if (fBigPagesSupported && Pde.b.u1Size)
3621	pHlp->pfnPrintf(pHlp,
3622	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3623	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3624	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3625	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3626	Pde.b.u1Write ? 'W' : 'R',
3627	Pde.b.u1User ? 'U' : 'S',
3628	Pde.b.u1Accessed ? 'A' : '-',
3629	Pde.b.u1Dirty ? 'D' : '-',
3630	Pde.b.u1Global ? 'G' : '-',
3631	Pde.b.u1WriteThru ? "WT" : "--",
3632	Pde.b.u1CacheDisable? "CD" : "--",
3633	Pde.b.u1PAT ? "AT" : "--",
3634	Pde.b.u1NoExecute ? "NX" : "--",
3635	Pde.u & RT_BIT_64(9) ? '1' : '0',
3636	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3637	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3638	Pde.u & X86_PDE_PAE_PG_MASK);
3639	else
3640	{
3641	pHlp->pfnPrintf(pHlp,
3642	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3643	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3644	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3645	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3646	Pde.n.u1Write ? 'W' : 'R',
3647	Pde.n.u1User ? 'U' : 'S',
3648	Pde.n.u1Accessed ? 'A' : '-',
3649	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3650	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3651	Pde.n.u1WriteThru ? "WT" : "--",
3652	Pde.n.u1CacheDisable? "CD" : "--",
3653	Pde.n.u1NoExecute ? "NX" : "--",
3654	Pde.u & RT_BIT_64(9) ? '1' : '0',
3655	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3656	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3657	Pde.u & X86_PDE_PAE_PG_MASK);
3658	if (cMaxDepth >= 1)
3659	{
3660	/** @todo what about using the page pool for mapping PTs? */
3661	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3662	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3663	PX86PTPAE pPT = NULL;
3664	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3665	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3666	else
3667	{
3668	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3669	{
3670	uint64_t off = u64AddressPT - pMap->GCPtr;
3671	if (off < pMap->cb)
3672	{
3673	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3674	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3675	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3676	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3677	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3678	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3679	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3680	}
3681	}
3682	}
3683	int rc2 = VERR_INVALID_PARAMETER;
3684	if (pPT)
3685	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3686	else
3687	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3688	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3689	if (rc2 < rc && RT_SUCCESS(rc))
3690	rc = rc2;
3691	}
3692	}
3693	}
3694	}
3695	return rc;
3696	}
3697
3698
3699	/**
3700	* Dumps a PAE shadow page directory pointer table.
3701	*
3702	* @returns VBox status code (VINF_SUCCESS).
3703	* @param pVM The VM handle.
3704	* @param HCPhys The physical address of the page directory pointer table.
3705	* @param u64Address The virtual address of the page table starts.
3706	* @param cr4 The CR4, PSE is currently used.
3707	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3708	* @param cMaxDepth The maxium depth.
3709	* @param pHlp Pointer to the output functions.
3710	*/
3711	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3712	{
3713	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3714	if (!pPDPT)
3715	{
3716	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3717	fLongMode ? 16 : 8, u64Address, HCPhys);
3718	return VERR_INVALID_PARAMETER;
3719	}
3720
3721	int rc = VINF_SUCCESS;
3722	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3723	for (unsigned i = 0; i < c; i++)
3724	{
3725	X86PDPE Pdpe = pPDPT->a[i];
3726	if (Pdpe.n.u1Present)
3727	{
3728	if (fLongMode)
3729	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3730	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3731	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3732	Pdpe.lm.u1Write ? 'W' : 'R',
3733	Pdpe.lm.u1User ? 'U' : 'S',
3734	Pdpe.lm.u1Accessed ? 'A' : '-',
3735	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3736	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3737	Pdpe.lm.u1WriteThru ? "WT" : "--",
3738	Pdpe.lm.u1CacheDisable? "CD" : "--",
3739	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3740	Pdpe.lm.u1NoExecute ? "NX" : "--",
3741	Pdpe.u & RT_BIT(9) ? '1' : '0',
3742	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3743	Pdpe.u & RT_BIT(11) ? '1' : '0',
3744	Pdpe.u & X86_PDPE_PG_MASK);
3745	else
3746	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3747	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3748	i << X86_PDPT_SHIFT,
3749	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3750	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3751	Pdpe.n.u1WriteThru ? "WT" : "--",
3752	Pdpe.n.u1CacheDisable? "CD" : "--",
3753	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3754	Pdpe.u & RT_BIT(9) ? '1' : '0',
3755	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3756	Pdpe.u & RT_BIT(11) ? '1' : '0',
3757	Pdpe.u & X86_PDPE_PG_MASK);
3758	if (cMaxDepth >= 1)
3759	{
3760	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3761	cr4, fLongMode, cMaxDepth - 1, pHlp);
3762	if (rc2 < rc && RT_SUCCESS(rc))
3763	rc = rc2;
3764	}
3765	}
3766	}
3767	return rc;
3768	}
3769
3770
3771	/**
3772	* Dumps a 32-bit shadow page table.
3773	*
3774	* @returns VBox status code (VINF_SUCCESS).
3775	* @param pVM The VM handle.
3776	* @param HCPhys The physical address of the table.
3777	* @param cr4 The CR4, PSE is currently used.
3778	* @param cMaxDepth The maxium depth.
3779	* @param pHlp Pointer to the output functions.
3780	*/
3781	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3782	{
3783	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3784	if (!pPML4)
3785	{
3786	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3787	return VERR_INVALID_PARAMETER;
3788	}
3789
3790	int rc = VINF_SUCCESS;
3791	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3792	{
3793	X86PML4E Pml4e = pPML4->a[i];
3794	if (Pml4e.n.u1Present)
3795	{
3796	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3797	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3798	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3799	u64Address,
3800	Pml4e.n.u1Write ? 'W' : 'R',
3801	Pml4e.n.u1User ? 'U' : 'S',
3802	Pml4e.n.u1Accessed ? 'A' : '-',
3803	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3804	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3805	Pml4e.n.u1WriteThru ? "WT" : "--",
3806	Pml4e.n.u1CacheDisable? "CD" : "--",
3807	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3808	Pml4e.n.u1NoExecute ? "NX" : "--",
3809	Pml4e.u & RT_BIT(9) ? '1' : '0',
3810	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3811	Pml4e.u & RT_BIT(11) ? '1' : '0',
3812	Pml4e.u & X86_PML4E_PG_MASK);
3813
3814	if (cMaxDepth >= 1)
3815	{
3816	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3817	if (rc2 < rc && RT_SUCCESS(rc))
3818	rc = rc2;
3819	}
3820	}
3821	}
3822	return rc;
3823	}
3824
3825
3826	/**
3827	* Dumps a 32-bit shadow page table.
3828	*
3829	* @returns VBox status code (VINF_SUCCESS).
3830	* @param pVM The VM handle.
3831	* @param pPT Pointer to the page table.
3832	* @param u32Address The virtual address this table starts at.
3833	* @param pHlp Pointer to the output functions.
3834	*/
3835	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3836	{
3837	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3838	{
3839	X86PTE Pte = pPT->a[i];
3840	if (Pte.n.u1Present)
3841	{
3842	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3843	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3844	u32Address + (i << X86_PT_SHIFT),
3845	Pte.n.u1Write ? 'W' : 'R',
3846	Pte.n.u1User ? 'U' : 'S',
3847	Pte.n.u1Accessed ? 'A' : '-',
3848	Pte.n.u1Dirty ? 'D' : '-',
3849	Pte.n.u1Global ? 'G' : '-',
3850	Pte.n.u1WriteThru ? "WT" : "--",
3851	Pte.n.u1CacheDisable? "CD" : "--",
3852	Pte.n.u1PAT ? "AT" : "--",
3853	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3854	Pte.u & RT_BIT(10) ? '1' : '0',
3855	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3856	Pte.u & X86_PDE_PG_MASK);
3857	}
3858	}
3859	return VINF_SUCCESS;
3860	}
3861
3862
3863	/**
3864	* Dumps a 32-bit shadow page directory and page tables.
3865	*
3866	* @returns VBox status code (VINF_SUCCESS).
3867	* @param pVM The VM handle.
3868	* @param cr3 The root of the hierarchy.
3869	* @param cr4 The CR4, PSE is currently used.
3870	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3871	* @param pHlp Pointer to the output functions.
3872	*/
3873	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3874	{
3875	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3876	if (!pPD)
3877	{
3878	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3879	return VERR_INVALID_PARAMETER;
3880	}
3881
3882	int rc = VINF_SUCCESS;
3883	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3884	{
3885	X86PDE Pde = pPD->a[i];
3886	if (Pde.n.u1Present)
3887	{
3888	const uint32_t u32Address = i << X86_PD_SHIFT;
3889	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3890	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3891	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3892	u32Address,
3893	Pde.b.u1Write ? 'W' : 'R',
3894	Pde.b.u1User ? 'U' : 'S',
3895	Pde.b.u1Accessed ? 'A' : '-',
3896	Pde.b.u1Dirty ? 'D' : '-',
3897	Pde.b.u1Global ? 'G' : '-',
3898	Pde.b.u1WriteThru ? "WT" : "--",
3899	Pde.b.u1CacheDisable? "CD" : "--",
3900	Pde.b.u1PAT ? "AT" : "--",
3901	Pde.u & RT_BIT_64(9) ? '1' : '0',
3902	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3903	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3904	Pde.u & X86_PDE4M_PG_MASK);
3905	else
3906	{
3907	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3908	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3909	u32Address,
3910	Pde.n.u1Write ? 'W' : 'R',
3911	Pde.n.u1User ? 'U' : 'S',
3912	Pde.n.u1Accessed ? 'A' : '-',
3913	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3914	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3915	Pde.n.u1WriteThru ? "WT" : "--",
3916	Pde.n.u1CacheDisable? "CD" : "--",
3917	Pde.u & RT_BIT_64(9) ? '1' : '0',
3918	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3919	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3920	Pde.u & X86_PDE_PG_MASK);
3921	if (cMaxDepth >= 1)
3922	{
3923	/** @todo what about using the page pool for mapping PTs? */
3924	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3925	PX86PT pPT = NULL;
3926	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3927	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3928	else
3929	{
3930	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3931	if (u32Address - pMap->GCPtr < pMap->cb)
3932	{
3933	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3934	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3935	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3936	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3937	pPT = pMap->aPTs[iPDE].pPTR3;
3938	}
3939	}
3940	int rc2 = VERR_INVALID_PARAMETER;
3941	if (pPT)
3942	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3943	else
3944	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3945	if (rc2 < rc && RT_SUCCESS(rc))
3946	rc = rc2;
3947	}
3948	}
3949	}
3950	}
3951
3952	return rc;
3953	}
3954
3955
3956	/**
3957	* Dumps a 32-bit shadow page table.
3958	*
3959	* @returns VBox status code (VINF_SUCCESS).
3960	* @param pVM The VM handle.
3961	* @param pPT Pointer to the page table.
3962	* @param u32Address The virtual address this table starts at.
3963	* @param PhysSearch Address to search for.
3964	*/
3965	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3966	{
3967	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3968	{
3969	X86PTE Pte = pPT->a[i];
3970	if (Pte.n.u1Present)
3971	{
3972	Log(( /P R S A D G WT CD AT NX 4M a m d /
3973	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3974	u32Address + (i << X86_PT_SHIFT),
3975	Pte.n.u1Write ? 'W' : 'R',
3976	Pte.n.u1User ? 'U' : 'S',
3977	Pte.n.u1Accessed ? 'A' : '-',
3978	Pte.n.u1Dirty ? 'D' : '-',
3979	Pte.n.u1Global ? 'G' : '-',
3980	Pte.n.u1WriteThru ? "WT" : "--",
3981	Pte.n.u1CacheDisable? "CD" : "--",
3982	Pte.n.u1PAT ? "AT" : "--",
3983	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3984	Pte.u & RT_BIT(10) ? '1' : '0',
3985	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3986	Pte.u & X86_PDE_PG_MASK));
3987
3988	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3989	{
3990	uint64_t fPageShw = 0;
3991	RTHCPHYS pPhysHC = 0;
3992
3993	/** @todo SMP support!! */
3994	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3995	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3996	}
3997	}
3998	}
3999	return VINF_SUCCESS;
4000	}
4001
4002
4003	/**
4004	* Dumps a 32-bit guest page directory and page tables.
4005	*
4006	* @returns VBox status code (VINF_SUCCESS).
4007	* @param pVM The VM handle.
4008	* @param cr3 The root of the hierarchy.
4009	* @param cr4 The CR4, PSE is currently used.
4010	* @param PhysSearch Address to search for.
4011	*/
4012	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4013	{
4014	bool fLongMode = false;
4015	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4016	PX86PD pPD = 0;
4017	PGMPAGEMAPLOCK LockCr3;
4018
4019	int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, cr3 & X86_CR3_PAGE_MASK, (const void **)&pPD, &LockCr3);
4020	if ( RT_FAILURE(rc)
4021	\|\| !pPD)
4022	{
4023	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4024	return VERR_INVALID_PARAMETER;
4025	}
4026
4027	Log(("cr3=%08x cr4=%08x%s\n"
4028	"%-*s P - Present\n"
4029	"%-*s \| R/W - Read (0) / Write (1)\n"
4030	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4031	"%-*s \| \| \| A - Accessed\n"
4032	"%-*s \| \| \| \| D - Dirty\n"
4033	"%-*s \| \| \| \| \| G - Global\n"
4034	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4035	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4036	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4037	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4038	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4039	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4040	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4041	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4042	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4043	- W U - - - -- -- -- -- -- 010 */
4044	, cr3, cr4, fLongMode ? " Long Mode" : "",
4045	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4046	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4047
4048	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4049	{
4050	X86PDE Pde = pPD->a[i];
4051	if (Pde.n.u1Present)
4052	{
4053	const uint32_t u32Address = i << X86_PD_SHIFT;
4054
4055	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4056	Log(( /P R S A D G WT CD AT NX 4M a m d /
4057	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4058	u32Address,
4059	Pde.b.u1Write ? 'W' : 'R',
4060	Pde.b.u1User ? 'U' : 'S',
4061	Pde.b.u1Accessed ? 'A' : '-',
4062	Pde.b.u1Dirty ? 'D' : '-',
4063	Pde.b.u1Global ? 'G' : '-',
4064	Pde.b.u1WriteThru ? "WT" : "--",
4065	Pde.b.u1CacheDisable? "CD" : "--",
4066	Pde.b.u1PAT ? "AT" : "--",
4067	Pde.u & RT_BIT(9) ? '1' : '0',
4068	Pde.u & RT_BIT(10) ? '1' : '0',
4069	Pde.u & RT_BIT(11) ? '1' : '0',
4070	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4071	/** @todo PhysSearch */
4072	else
4073	{
4074	Log(( /P R S A D G WT CD AT NX 4M a m d /
4075	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4076	u32Address,
4077	Pde.n.u1Write ? 'W' : 'R',
4078	Pde.n.u1User ? 'U' : 'S',
4079	Pde.n.u1Accessed ? 'A' : '-',
4080	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4081	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4082	Pde.n.u1WriteThru ? "WT" : "--",
4083	Pde.n.u1CacheDisable? "CD" : "--",
4084	Pde.u & RT_BIT(9) ? '1' : '0',
4085	Pde.u & RT_BIT(10) ? '1' : '0',
4086	Pde.u & RT_BIT(11) ? '1' : '0',
4087	Pde.u & X86_PDE_PG_MASK));
4088	////if (cMaxDepth >= 1)
4089	{
4090	/** @todo what about using the page pool for mapping PTs? */
4091	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4092	PX86PT pPT = NULL;
4093	PGMPAGEMAPLOCK LockPT;
4094
4095	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, (const void **)&pPT, &LockPT);
4096
4097	int rc2 = VERR_INVALID_PARAMETER;
4098	if (pPT)
4099	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4100	else
4101	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4102
4103	if (rc == VINF_SUCCESS)
4104	PGMPhysReleasePageMappingLock(pVM, &LockPT);
4105
4106	if (rc2 < rc && RT_SUCCESS(rc))
4107	rc = rc2;
4108	}
4109	}
4110	}
4111	}
4112	PGMPhysReleasePageMappingLock(pVM, &LockCr3);
4113	return rc;
4114	}
4115
4116
4117	/**
4118	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4119	*
4120	* @returns VBox status code (VINF_SUCCESS).
4121	* @param pVM The VM handle.
4122	* @param cr3 The root of the hierarchy.
4123	* @param cr4 The cr4, only PAE and PSE is currently used.
4124	* @param fLongMode Set if long mode, false if not long mode.
4125	* @param cMaxDepth Number of levels to dump.
4126	* @param pHlp Pointer to the output functions.
4127	*/
4128	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4129	{
4130	if (!pHlp)
4131	pHlp = DBGFR3InfoLogHlp();
4132	if (!cMaxDepth)
4133	return VINF_SUCCESS;
4134	const unsigned cch = fLongMode ? 16 : 8;
4135	pHlp->pfnPrintf(pHlp,
4136	"cr3=%08x cr4=%08x%s\n"
4137	"%-*s P - Present\n"
4138	"%-*s \| R/W - Read (0) / Write (1)\n"
4139	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4140	"%-*s \| \| \| A - Accessed\n"
4141	"%-*s \| \| \| \| D - Dirty\n"
4142	"%-*s \| \| \| \| \| G - Global\n"
4143	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4144	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4145	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4146	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4147	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4148	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4149	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4150	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4151	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4152	- W U - - - -- -- -- -- -- 010 */
4153	, cr3, cr4, fLongMode ? " Long Mode" : "",
4154	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4155	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4156	if (cr4 & X86_CR4_PAE)
4157	{
4158	if (fLongMode)
4159	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4160	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4161	}
4162	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4163	}
4164
4165	#ifdef VBOX_WITH_DEBUGGER
4166
4167	/**
4168	* The '.pgmram' command.
4169	*
4170	* @returns VBox status.
4171	* @param pCmd Pointer to the command descriptor (as registered).
4172	* @param pCmdHlp Pointer to command helper functions.
4173	* @param pVM Pointer to the current VM (if any).
4174	* @param paArgs Pointer to (readonly) array of arguments.
4175	* @param cArgs Number of arguments in the array.
4176	*/
4177	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4178	{
4179	/*
4180	* Validate input.
4181	*/
4182	if (!pVM)
4183	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4184	if (!pVM->pgm.s.pRamRangesRC)
4185	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4186
4187	/*
4188	* Dump the ranges.
4189	*/
4190	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4191	PPGMRAMRANGE pRam;
4192	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4193	{
4194	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4195	"%RGp - %RGp %p\n",
4196	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4197	if (RT_FAILURE(rc))
4198	return rc;
4199	}
4200
4201	return VINF_SUCCESS;
4202	}
4203
4204
4205	/**
4206	* The '.pgmerror' and '.pgmerroroff' commands.
4207	*
4208	* @returns VBox status.
4209	* @param pCmd Pointer to the command descriptor (as registered).
4210	* @param pCmdHlp Pointer to command helper functions.
4211	* @param pVM Pointer to the current VM (if any).
4212	* @param paArgs Pointer to (readonly) array of arguments.
4213	* @param cArgs Number of arguments in the array.
4214	*/
4215	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4216	{
4217	/*
4218	* Validate input.
4219	*/
4220	if (!pVM)
4221	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4222	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4223	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4224
4225	if (!cArgs)
4226	{
4227	/*
4228	* Print the list of error injection locations with status.
4229	*/
4230	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4231	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4232	}
4233	else
4234	{
4235
4236	/*
4237	* String switch on where to inject the error.
4238	*/
4239	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4240	const char *pszWhere = paArgs[0].u.pszString;
4241	if (!strcmp(pszWhere, "handy"))
4242	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4243	else
4244	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4245	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4246	}
4247	return VINF_SUCCESS;
4248	}
4249
4250
4251	/**
4252	* The '.pgmsync' command.
4253	*
4254	* @returns VBox status.
4255	* @param pCmd Pointer to the command descriptor (as registered).
4256	* @param pCmdHlp Pointer to command helper functions.
4257	* @param pVM Pointer to the current VM (if any).
4258	* @param paArgs Pointer to (readonly) array of arguments.
4259	* @param cArgs Number of arguments in the array.
4260	*/
4261	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4262	{
4263	/** @todo SMP support */
4264	PVMCPU pVCpu = &pVM->aCpus[0];
4265
4266	/*
4267	* Validate input.
4268	*/
4269	if (!pVM)
4270	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4271
4272	/*
4273	* Force page directory sync.
4274	*/
4275	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4276
4277	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4278	if (RT_FAILURE(rc))
4279	return rc;
4280
4281	return VINF_SUCCESS;
4282	}
4283
4284
4285	#ifdef VBOX_STRICT
4286	/**
4287	* The '.pgmassertcr3' command.
4288	*
4289	* @returns VBox status.
4290	* @param pCmd Pointer to the command descriptor (as registered).
4291	* @param pCmdHlp Pointer to command helper functions.
4292	* @param pVM Pointer to the current VM (if any).
4293	* @param paArgs Pointer to (readonly) array of arguments.
4294	* @param cArgs Number of arguments in the array.
4295	*/
4296	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4297	{
4298	/** @todo SMP support!! */
4299	PVMCPU pVCpu = &pVM->aCpus[0];
4300
4301	/*
4302	* Validate input.
4303	*/
4304	if (!pVM)
4305	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4306
4307	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4308	if (RT_FAILURE(rc))
4309	return rc;
4310
4311	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4312
4313	return VINF_SUCCESS;
4314	}
4315
4316	# ifdef DEBUG_sandervl
4317	/**
4318	* Internal timer callback function.
4319	*
4320	* @param pVM The VM.
4321	* @param pTimer The timer handle.
4322	* @param pvUser User argument specified upon timer creation.
4323	*/
4324	static DECLCALLBACK(void) pgmR3PhysWriteCountTMCallback(PVM pVM, PTMTIMER pTimer, void *pvUser)
4325	{
4326	if (pVM->pgm.s.fCountingPhysWrites)
4327	{
4328	pgmR3PoolClearAll(pVM, true/* fFlushRemTlb */);
4329
4330	/* Program next invocation. */
4331	int rc = TMTimerSetMillies(pVM->pgm.s.pPhysWritesCountTimer, pVM->pgm.s.u32PhysWriteCountTimerInterval);
4332	AssertRC(rc);
4333	}
4334	}
4335
4336	/**
4337	* The '.pgmcountphyswrites' command.
4338	*
4339	* @returns VBox status.
4340	* @param pCmd Pointer to the command descriptor (as registered).
4341	* @param pCmdHlp Pointer to command helper functions.
4342	* @param pVM Pointer to the current VM (if any).
4343	* @param paArgs Pointer to (readonly) array of arguments.
4344	* @param cArgs Number of arguments in the array.
4345	*/
4346	static DECLCALLBACK(int) pgmR3CmdCountPhysWrites(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4347	{
4348	/*
4349	* Validate input.
4350	*/
4351	if (!pVM)
4352	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4353	if ( cArgs != 2
4354	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4355	\|\| paArgs[1].enmType != DBGCVAR_TYPE_NUMBER)
4356	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4357
4358	if (!strcmp(paArgs[0].u.pszString, "off"))
4359	{
4360	if (!pVM->pgm.s.fCountingPhysWrites)
4361	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: not enabled!\n");
4362
4363	TMTimerStop(pVM->pgm.s.pPhysWritesCountTimer);
4364	pVM->pgm.s.fCountingPhysWrites = false;
4365	return VINF_SUCCESS;
4366	}
4367	else
4368	if (strcmp(paArgs[0].u.pszString, "on"))
4369	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 1st argument '%s', must be 'on' or 'off'.\n", paArgs[0].u.pszString);
4370
4371	if ( paArgs[1].u.u64Number < 10
4372	\|\| paArgs[1].u.u64Number > 1000)
4373	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%d', must be between 10 and 1000 ms.\n", paArgs[1].u.u64Number);
4374
4375	pVM->pgm.s.u32PhysWriteCountTimerInterval = paArgs[1].u.u64Number;
4376	pVM->pgm.s.fCountingPhysWrites = true;
4377	int rc = TMTimerSetMillies(pVM->pgm.s.pPhysWritesCountTimer, paArgs[1].u.u64Number);
4378	AssertRC(rc);
4379	return VINF_SUCCESS;
4380	}
4381	# endif /* DEBUG_sandervl */
4382
4383	#endif /* VBOX_STRICT */
4384
4385
4386	/**
4387	* The '.pgmsyncalways' command.
4388	*
4389	* @returns VBox status.
4390	* @param pCmd Pointer to the command descriptor (as registered).
4391	* @param pCmdHlp Pointer to command helper functions.
4392	* @param pVM Pointer to the current VM (if any).
4393	* @param paArgs Pointer to (readonly) array of arguments.
4394	* @param cArgs Number of arguments in the array.
4395	*/
4396	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4397	{
4398	/** @todo SMP support!! */
4399	PVMCPU pVCpu = &pVM->aCpus[0];
4400
4401	/*
4402	* Validate input.
4403	*/
4404	if (!pVM)
4405	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4406
4407	/*
4408	* Force page directory sync.
4409	*/
4410	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4411	{
4412	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4413	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4414	}
4415	else
4416	{
4417	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4418	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4419	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4420	}
4421	}
4422
4423
4424	/**
4425	* The '.pgmphystofile' command.
4426	*
4427	* @returns VBox status.
4428	* @param pCmd Pointer to the command descriptor (as registered).
4429	* @param pCmdHlp Pointer to command helper functions.
4430	* @param pVM Pointer to the current VM (if any).
4431	* @param paArgs Pointer to (readonly) array of arguments.
4432	* @param cArgs Number of arguments in the array.
4433	*/
4434	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4435	{
4436	/*
4437	* Validate input.
4438	*/
4439	if (!pVM)
4440	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4441	if ( cArgs < 1
4442	\|\| cArgs > 2
4443	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4444	\|\| ( cArgs > 1
4445	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4446	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4447	if ( cArgs >= 2
4448	&& strcmp(paArgs[1].u.pszString, "nozero"))
4449	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4450	bool fIncZeroPgs = cArgs < 2;
4451
4452	/*
4453	* Open the output file and get the ram parameters.
4454	*/
4455	RTFILE hFile;
4456	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
4457	if (RT_FAILURE(rc))
4458	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4459
4460	uint32_t cbRamHole = 0;
4461	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4462	uint64_t cbRam = 0;
4463	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4464	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4465
4466	/*
4467	* Dump the physical memory, page by page.
4468	*/
4469	RTGCPHYS GCPhys = 0;
4470	char abZeroPg[PAGE_SIZE];
4471	RT_ZERO(abZeroPg);
4472
4473	pgmLock(pVM);
4474	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4475	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4476	pRam = pRam->pNextR3)
4477	{
4478	/* fill the gap */
4479	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4480	{
4481	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4482	{
4483	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4484	GCPhys += PAGE_SIZE;
4485	}
4486	}
4487
4488	PCPGMPAGE pPage = &pRam->aPages[0];
4489	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4490	{
4491	if ( PGM_PAGE_IS_ZERO(pPage)
4492	\|\| PGM_PAGE_IS_BALLOONED(pPage))
4493	{
4494	if (fIncZeroPgs)
4495	{
4496	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4497	if (RT_FAILURE(rc))
4498	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4499	}
4500	}
4501	else
4502	{
4503	switch (PGM_PAGE_GET_TYPE(pPage))
4504	{
4505	case PGMPAGETYPE_RAM:
4506	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4507	case PGMPAGETYPE_ROM:
4508	case PGMPAGETYPE_MMIO2:
4509	{
4510	void const *pvPage;
4511	PGMPAGEMAPLOCK Lock;
4512	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4513	if (RT_SUCCESS(rc))
4514	{
4515	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4516	PGMPhysReleasePageMappingLock(pVM, &Lock);
4517	if (RT_FAILURE(rc))
4518	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4519	}
4520	else
4521	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4522	break;
4523	}
4524
4525	default:
4526	AssertFailed();
4527	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4528	case PGMPAGETYPE_MMIO:
4529	if (fIncZeroPgs)
4530	{
4531	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4532	if (RT_FAILURE(rc))
4533	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4534	}
4535	break;
4536	}
4537	}
4538
4539
4540	/* advance */
4541	GCPhys += PAGE_SIZE;
4542	pPage++;
4543	}
4544	}
4545	pgmUnlock(pVM);
4546
4547	RTFileClose(hFile);
4548	if (RT_SUCCESS(rc))
4549	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4550	return VINF_SUCCESS;
4551	}
4552
4553	#endif /* VBOX_WITH_DEBUGGER */
4554
4555	/**
4556	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4557	*/
4558	typedef struct PGMCHECKINTARGS
4559	{
4560	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4561	PPGMPHYSHANDLER pPrevPhys;
4562	PPGMVIRTHANDLER pPrevVirt;
4563	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4564	PVM pVM;
4565	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4566
4567	/**
4568	* Validate a node in the physical handler tree.
4569	*
4570	* @returns 0 on if ok, other wise 1.
4571	* @param pNode The handler node.
4572	* @param pvUser pVM.
4573	*/
4574	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4575	{
4576	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4577	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4578	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4579	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4580	AssertReleaseMsg( !pArgs->pPrevPhys
4581	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4582	("pPrevPhys=%p %RGp-%RGp %s\n"
4583	" pCur=%p %RGp-%RGp %s\n",
4584	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4585	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4586	pArgs->pPrevPhys = pCur;
4587	return 0;
4588	}
4589
4590
4591	/**
4592	* Validate a node in the virtual handler tree.
4593	*
4594	* @returns 0 on if ok, other wise 1.
4595	* @param pNode The handler node.
4596	* @param pvUser pVM.
4597	*/
4598	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4599	{
4600	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4601	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4602	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4603	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4604	AssertReleaseMsg( !pArgs->pPrevVirt
4605	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4606	("pPrevVirt=%p %RGv-%RGv %s\n"
4607	" pCur=%p %RGv-%RGv %s\n",
4608	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4609	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4610	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4611	{
4612	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4613	("pCur=%p %RGv-%RGv %s\n"
4614	"iPage=%d offVirtHandle=%#x expected %#x\n",
4615	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4616	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4617	}
4618	pArgs->pPrevVirt = pCur;
4619	return 0;
4620	}
4621
4622
4623	/**
4624	* Validate a node in the virtual handler tree.
4625	*
4626	* @returns 0 on if ok, other wise 1.
4627	* @param pNode The handler node.
4628	* @param pvUser pVM.
4629	*/
4630	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4631	{
4632	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4633	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4634	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4635	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4636	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4637	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4638	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4639	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4640	" pCur=%p %RGp-%RGp\n",
4641	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4642	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4643	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4644	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4645	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4646	" pCur=%p %RGp-%RGp\n",
4647	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4648	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4649	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4650	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4651	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4652	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4653	{
4654	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4655	for (;;)
4656	{
4657	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4658	AssertReleaseMsg(pCur2 != pCur,
4659	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4660	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4661	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4662	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4663	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4664	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4665	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4666	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4667	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4668	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4669	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4670	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4671	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4672	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4673	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4674	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4675	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4676	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4677	break;
4678	}
4679	}
4680
4681	pArgs->pPrevPhys2Virt = pCur;
4682	return 0;
4683	}
4684
4685
4686	/**
4687	* Perform an integrity check on the PGM component.
4688	*
4689	* @returns VINF_SUCCESS if everything is fine.
4690	* @returns VBox error status after asserting on integrity breach.
4691	* @param pVM The VM handle.
4692	*/
4693	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4694	{
4695	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4696
4697	/*
4698	* Check the trees.
4699	*/
4700	int cErrors = 0;
4701	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4702	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4703	PGMCHECKINTARGS Args = s_LeftToRight;
4704	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4705	Args = s_RightToLeft;
4706	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4707	Args = s_LeftToRight;
4708	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4709	Args = s_RightToLeft;
4710	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4711	Args = s_LeftToRight;
4712	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4713	Args = s_RightToLeft;
4714	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4715	Args = s_LeftToRight;
4716	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4717	Args = s_RightToLeft;
4718	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4719
4720	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4721	}
4722

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 31684

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