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1	/* $Id: PGM.cpp 30845 2010-07-14 14:33:10Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be refered to
30	* as "host paging", and GC refered to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgm_phys PGM Physical Guest Memory Management
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485	* memory context for the HWACCM execution.
486	*
487	*
488	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489	*
490	* We've considered implementing the ring-3 mapping cache page based but found
491	* that this was bother some when one had to take into account TLBs+SMP and
492	* portability (missing the necessary APIs on several platforms). There were
493	* also some performance concerns with this approach which hadn't quite been
494	* worked out.
495	*
496	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500	* costly than a single page, although how much more costly is uncertain. We'll
501	* try address this by using a very big cache, preferably bigger than the actual
502	* VM RAM size if possible. The current VM RAM sizes should give some idea for
503	* 32-bit boxes, while on 64-bit we can probably get away with employing an
504	* unlimited cache.
505	*
506	* The cache have to parts, as already indicated, the ring-3 side and the
507	* ring-0 side.
508	*
509	* The ring-0 will be tied to the page allocator since it will operate on the
510	* memory objects it contains. It will therefore require the first ring-0 mutex
511	* discussed in @ref subsec_pgmPhys_Serializing. We
512	* some double house keeping wrt to who has mapped what I think, since both
513	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514	*
515	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516	* require anyone that desires to do changes to the mapping cache to do that
517	* from within this critsect. Alternatively, we could employ a separate critsect
518	* for serializing changes to the mapping cache as this would reduce potential
519	* contention with other threads accessing mappings unrelated to the changes
520	* that are in process. We can see about this later, contention will show
521	* up in the statistics anyway, so it'll be simple to tell.
522	*
523	* The organization of the ring-3 part will be very much like how the allocation
524	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525	* having to walk the tree all the time, we'll have a couple of lookaside entries
526	* like in we do for I/O ports and MMIO in IOM.
527	*
528	* The simplified flow of a PGMPhysRead/Write function:
529	* -# Enter the PGM critsect.
530	* -# Lookup GCPhys in the ram ranges and get the Page ID.
531	* -# Calc the Allocation Chunk ID from the Page ID.
532	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533	* If not found in cache:
534	* -# Call ring-0 and request it to be mapped and supply
535	* a chunk to be unmapped if the cache is maxed out already.
536	* -# Insert the new mapping into the AVL tree (id + R3 address).
537	* -# Update the relevant lookaside entry and return the mapping address.
538	* -# Do the read/write according to monitoring flags and everything.
539	* -# Leave the critsect.
540	*
541	*
542	* @section sec_pgmPhys_Fallback Fallback
543	*
544	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545	* API and thus require a fallback.
546	*
547	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548	* will return to the ring-3 caller (and later ring-0) and asking it to seed
549	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551	* "SeededAllocPages" call to ring-0.
552	*
553	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554	* all page sharing (zero page detection will continue). It will also force
555	* all allocations to come from the VM which seeded the page. Both these
556	* measures are taken to make sure that there will never be any need for
557	* mapping anything into ring-3 - everything will be mapped already.
558	*
559	* Whether we'll continue to use the current MM locked memory management
560	* for this I don't quite know (I'd prefer not to and just ditch that all
561	* togther), we'll see what's simplest to do.
562	*
563	*
564	*
565	* @section sec_pgmPhys_Changes Changes
566	*
567	* Breakdown of the changes involved?
568	*/
569
570	/*******************************************************************************
571	* Header Files *
572	*******************************************************************************/
573	#define LOG_GROUP LOG_GROUP_PGM
574	#include <VBox/dbgf.h>
575	#include <VBox/pgm.h>
576	#include <VBox/cpum.h>
577	#include <VBox/iom.h>
578	#include <VBox/sup.h>
579	#include <VBox/mm.h>
580	#include <VBox/em.h>
581	#include <VBox/stam.h>
582	#include <VBox/rem.h>
583	#include <VBox/selm.h>
584	#include <VBox/ssm.h>
585	#include <VBox/hwaccm.h>
586	#include "PGMInternal.h"
587	#include <VBox/vm.h>
588	#include "PGMInline.h"
589
590	#include <VBox/dbg.h>
591	#include <VBox/param.h>
592	#include <VBox/err.h>
593
594	#include <iprt/asm.h>
595	#include <iprt/assert.h>
596	#include <iprt/env.h>
597	#include <iprt/mem.h>
598	#include <iprt/file.h>
599	#include <iprt/string.h>
600	#include <iprt/thread.h>
601
602
603	/*******************************************************************************
604	* Defined Constants And Macros *
605	*******************************************************************************/
606	/** Saved state data unit version for 2.5.x and later. */
607	#define PGM_SAVED_STATE_VERSION 9
608	/** Saved state data unit version for 2.2.2 and later. */
609	#define PGM_SAVED_STATE_VERSION_2_2_2 8
610	/** Saved state data unit version for 2.2.0. */
611	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
612	/** Saved state data unit version. */
613	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
614
615
616	/*******************************************************************************
617	* Internal Functions *
618	*******************************************************************************/
619	static int pgmR3InitPaging(PVM pVM);
620	static void pgmR3InitStats(PVM pVM);
621	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
622	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
623	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
624	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
625	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
626	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
627	#ifdef VBOX_STRICT
628	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
629	#endif
630	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
631	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
632	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
633
634	#ifdef VBOX_WITH_DEBUGGER
635	/** @todo Convert the first two commands to 'info' items. */
636	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	# ifdef VBOX_STRICT
641	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# endif
643	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	#endif
645
646
647	/*******************************************************************************
648	* Global Variables *
649	*******************************************************************************/
650	#ifdef VBOX_WITH_DEBUGGER
651	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
652	static const DBGCVARDESC g_aPgmErrorArgs[] =
653	{
654	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
655	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
656	};
657
658	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
659	{
660	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
661	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
662	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
663	};
664
665	/** Command descriptors. */
666	static const DBGCCMD g_aCmds[] =
667	{
668	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
669	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
670	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
671	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
672	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
673	#ifdef VBOX_STRICT
674	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
675	#endif
676	#if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
677	{ "pgmcheckduppages", 0, 0, NULL, 0, NULL, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
678	{ "pgmsharedmodules", 0, 0, NULL, 0, NULL, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
679	#endif
680	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
681	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
682	};
683	#endif
684
685
686
687
688	/*
689	* Shadow - 32-bit mode
690	*/
691	#define PGM_SHW_TYPE PGM_TYPE_32BIT
692	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
693	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
694	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
695	#include "PGMShw.h"
696
697	/* Guest - real mode */
698	#define PGM_GST_TYPE PGM_TYPE_REAL
699	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
700	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
701	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
702	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
703	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
704	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
705	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
706	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
707	#include "PGMBth.h"
708	#include "PGMGstDefs.h"
709	#include "PGMGst.h"
710	#undef BTH_PGMPOOLKIND_PT_FOR_PT
711	#undef BTH_PGMPOOLKIND_ROOT
712	#undef PGM_BTH_NAME
713	#undef PGM_BTH_NAME_RC_STR
714	#undef PGM_BTH_NAME_R0_STR
715	#undef PGM_GST_TYPE
716	#undef PGM_GST_NAME
717	#undef PGM_GST_NAME_RC_STR
718	#undef PGM_GST_NAME_R0_STR
719
720	/* Guest - protected mode */
721	#define PGM_GST_TYPE PGM_TYPE_PROT
722	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
723	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
724	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
725	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
726	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
727	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
728	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
729	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
730	#include "PGMBth.h"
731	#include "PGMGstDefs.h"
732	#include "PGMGst.h"
733	#undef BTH_PGMPOOLKIND_PT_FOR_PT
734	#undef BTH_PGMPOOLKIND_ROOT
735	#undef PGM_BTH_NAME
736	#undef PGM_BTH_NAME_RC_STR
737	#undef PGM_BTH_NAME_R0_STR
738	#undef PGM_GST_TYPE
739	#undef PGM_GST_NAME
740	#undef PGM_GST_NAME_RC_STR
741	#undef PGM_GST_NAME_R0_STR
742
743	/* Guest - 32-bit mode */
744	#define PGM_GST_TYPE PGM_TYPE_32BIT
745	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
746	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
747	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
748	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
749	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
750	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
751	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
752	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
753	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
754	#include "PGMBth.h"
755	#include "PGMGstDefs.h"
756	#include "PGMGst.h"
757	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
758	#undef BTH_PGMPOOLKIND_PT_FOR_PT
759	#undef BTH_PGMPOOLKIND_ROOT
760	#undef PGM_BTH_NAME
761	#undef PGM_BTH_NAME_RC_STR
762	#undef PGM_BTH_NAME_R0_STR
763	#undef PGM_GST_TYPE
764	#undef PGM_GST_NAME
765	#undef PGM_GST_NAME_RC_STR
766	#undef PGM_GST_NAME_R0_STR
767
768	#undef PGM_SHW_TYPE
769	#undef PGM_SHW_NAME
770	#undef PGM_SHW_NAME_RC_STR
771	#undef PGM_SHW_NAME_R0_STR
772
773
774	/*
775	* Shadow - PAE mode
776	*/
777	#define PGM_SHW_TYPE PGM_TYPE_PAE
778	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
779	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
780	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
781	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
782	#include "PGMShw.h"
783
784	/* Guest - real mode */
785	#define PGM_GST_TYPE PGM_TYPE_REAL
786	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
787	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
788	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
789	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
790	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
791	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
792	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
793	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
794	#include "PGMGstDefs.h"
795	#include "PGMBth.h"
796	#undef BTH_PGMPOOLKIND_PT_FOR_PT
797	#undef BTH_PGMPOOLKIND_ROOT
798	#undef PGM_BTH_NAME
799	#undef PGM_BTH_NAME_RC_STR
800	#undef PGM_BTH_NAME_R0_STR
801	#undef PGM_GST_TYPE
802	#undef PGM_GST_NAME
803	#undef PGM_GST_NAME_RC_STR
804	#undef PGM_GST_NAME_R0_STR
805
806	/* Guest - protected mode */
807	#define PGM_GST_TYPE PGM_TYPE_PROT
808	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
809	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
810	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
811	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
812	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
813	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
814	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
815	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
816	#include "PGMGstDefs.h"
817	#include "PGMBth.h"
818	#undef BTH_PGMPOOLKIND_PT_FOR_PT
819	#undef BTH_PGMPOOLKIND_ROOT
820	#undef PGM_BTH_NAME
821	#undef PGM_BTH_NAME_RC_STR
822	#undef PGM_BTH_NAME_R0_STR
823	#undef PGM_GST_TYPE
824	#undef PGM_GST_NAME
825	#undef PGM_GST_NAME_RC_STR
826	#undef PGM_GST_NAME_R0_STR
827
828	/* Guest - 32-bit mode */
829	#define PGM_GST_TYPE PGM_TYPE_32BIT
830	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
831	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
832	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
833	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
834	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
835	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
836	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
837	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
838	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
839	#include "PGMGstDefs.h"
840	#include "PGMBth.h"
841	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
842	#undef BTH_PGMPOOLKIND_PT_FOR_PT
843	#undef BTH_PGMPOOLKIND_ROOT
844	#undef PGM_BTH_NAME
845	#undef PGM_BTH_NAME_RC_STR
846	#undef PGM_BTH_NAME_R0_STR
847	#undef PGM_GST_TYPE
848	#undef PGM_GST_NAME
849	#undef PGM_GST_NAME_RC_STR
850	#undef PGM_GST_NAME_R0_STR
851
852	/* Guest - PAE mode */
853	#define PGM_GST_TYPE PGM_TYPE_PAE
854	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
855	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
856	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
857	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
858	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
859	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
860	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
861	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
862	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
863	#include "PGMBth.h"
864	#include "PGMGstDefs.h"
865	#include "PGMGst.h"
866	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
867	#undef BTH_PGMPOOLKIND_PT_FOR_PT
868	#undef BTH_PGMPOOLKIND_ROOT
869	#undef PGM_BTH_NAME
870	#undef PGM_BTH_NAME_RC_STR
871	#undef PGM_BTH_NAME_R0_STR
872	#undef PGM_GST_TYPE
873	#undef PGM_GST_NAME
874	#undef PGM_GST_NAME_RC_STR
875	#undef PGM_GST_NAME_R0_STR
876
877	#undef PGM_SHW_TYPE
878	#undef PGM_SHW_NAME
879	#undef PGM_SHW_NAME_RC_STR
880	#undef PGM_SHW_NAME_R0_STR
881
882
883	/*
884	* Shadow - AMD64 mode
885	*/
886	#define PGM_SHW_TYPE PGM_TYPE_AMD64
887	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
888	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
889	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
890	#include "PGMShw.h"
891
892	#ifdef VBOX_WITH_64_BITS_GUESTS
893	/* Guest - AMD64 mode */
894	# define PGM_GST_TYPE PGM_TYPE_AMD64
895	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
896	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
897	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
898	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
899	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
900	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
901	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
902	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
903	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
904	# include "PGMBth.h"
905	# include "PGMGstDefs.h"
906	# include "PGMGst.h"
907	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
908	# undef BTH_PGMPOOLKIND_PT_FOR_PT
909	# undef BTH_PGMPOOLKIND_ROOT
910	# undef PGM_BTH_NAME
911	# undef PGM_BTH_NAME_RC_STR
912	# undef PGM_BTH_NAME_R0_STR
913	# undef PGM_GST_TYPE
914	# undef PGM_GST_NAME
915	# undef PGM_GST_NAME_RC_STR
916	# undef PGM_GST_NAME_R0_STR
917	#endif /* VBOX_WITH_64_BITS_GUESTS */
918
919	#undef PGM_SHW_TYPE
920	#undef PGM_SHW_NAME
921	#undef PGM_SHW_NAME_RC_STR
922	#undef PGM_SHW_NAME_R0_STR
923
924
925	/*
926	* Shadow - Nested paging mode
927	*/
928	#define PGM_SHW_TYPE PGM_TYPE_NESTED
929	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
930	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
931	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
932	#include "PGMShw.h"
933
934	/* Guest - real mode */
935	#define PGM_GST_TYPE PGM_TYPE_REAL
936	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
937	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
938	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
939	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
940	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
941	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
942	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
943	#include "PGMGstDefs.h"
944	#include "PGMBth.h"
945	#undef BTH_PGMPOOLKIND_PT_FOR_PT
946	#undef PGM_BTH_NAME
947	#undef PGM_BTH_NAME_RC_STR
948	#undef PGM_BTH_NAME_R0_STR
949	#undef PGM_GST_TYPE
950	#undef PGM_GST_NAME
951	#undef PGM_GST_NAME_RC_STR
952	#undef PGM_GST_NAME_R0_STR
953
954	/* Guest - protected mode */
955	#define PGM_GST_TYPE PGM_TYPE_PROT
956	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
957	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
958	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
959	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
960	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
961	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
962	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
963	#include "PGMGstDefs.h"
964	#include "PGMBth.h"
965	#undef BTH_PGMPOOLKIND_PT_FOR_PT
966	#undef PGM_BTH_NAME
967	#undef PGM_BTH_NAME_RC_STR
968	#undef PGM_BTH_NAME_R0_STR
969	#undef PGM_GST_TYPE
970	#undef PGM_GST_NAME
971	#undef PGM_GST_NAME_RC_STR
972	#undef PGM_GST_NAME_R0_STR
973
974	/* Guest - 32-bit mode */
975	#define PGM_GST_TYPE PGM_TYPE_32BIT
976	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
977	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
978	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
979	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
980	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
981	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
982	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
983	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
984	#include "PGMGstDefs.h"
985	#include "PGMBth.h"
986	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
987	#undef BTH_PGMPOOLKIND_PT_FOR_PT
988	#undef PGM_BTH_NAME
989	#undef PGM_BTH_NAME_RC_STR
990	#undef PGM_BTH_NAME_R0_STR
991	#undef PGM_GST_TYPE
992	#undef PGM_GST_NAME
993	#undef PGM_GST_NAME_RC_STR
994	#undef PGM_GST_NAME_R0_STR
995
996	/* Guest - PAE mode */
997	#define PGM_GST_TYPE PGM_TYPE_PAE
998	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
999	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1000	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1001	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1002	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1003	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1004	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1005	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1006	#include "PGMGstDefs.h"
1007	#include "PGMBth.h"
1008	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1009	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1010	#undef PGM_BTH_NAME
1011	#undef PGM_BTH_NAME_RC_STR
1012	#undef PGM_BTH_NAME_R0_STR
1013	#undef PGM_GST_TYPE
1014	#undef PGM_GST_NAME
1015	#undef PGM_GST_NAME_RC_STR
1016	#undef PGM_GST_NAME_R0_STR
1017
1018	#ifdef VBOX_WITH_64_BITS_GUESTS
1019	/* Guest - AMD64 mode */
1020	# define PGM_GST_TYPE PGM_TYPE_AMD64
1021	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1022	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1023	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1024	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1025	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1026	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1027	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1028	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1029	# include "PGMGstDefs.h"
1030	# include "PGMBth.h"
1031	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1032	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1033	# undef PGM_BTH_NAME
1034	# undef PGM_BTH_NAME_RC_STR
1035	# undef PGM_BTH_NAME_R0_STR
1036	# undef PGM_GST_TYPE
1037	# undef PGM_GST_NAME
1038	# undef PGM_GST_NAME_RC_STR
1039	# undef PGM_GST_NAME_R0_STR
1040	#endif /* VBOX_WITH_64_BITS_GUESTS */
1041
1042	#undef PGM_SHW_TYPE
1043	#undef PGM_SHW_NAME
1044	#undef PGM_SHW_NAME_RC_STR
1045	#undef PGM_SHW_NAME_R0_STR
1046
1047
1048	/*
1049	* Shadow - EPT
1050	*/
1051	#define PGM_SHW_TYPE PGM_TYPE_EPT
1052	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1053	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1054	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1055	#include "PGMShw.h"
1056
1057	/* Guest - real mode */
1058	#define PGM_GST_TYPE PGM_TYPE_REAL
1059	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1060	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1061	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1062	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1063	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1064	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1065	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1066	#include "PGMGstDefs.h"
1067	#include "PGMBth.h"
1068	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1069	#undef PGM_BTH_NAME
1070	#undef PGM_BTH_NAME_RC_STR
1071	#undef PGM_BTH_NAME_R0_STR
1072	#undef PGM_GST_TYPE
1073	#undef PGM_GST_NAME
1074	#undef PGM_GST_NAME_RC_STR
1075	#undef PGM_GST_NAME_R0_STR
1076
1077	/* Guest - protected mode */
1078	#define PGM_GST_TYPE PGM_TYPE_PROT
1079	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1080	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1081	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1082	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1083	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1084	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1085	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1086	#include "PGMGstDefs.h"
1087	#include "PGMBth.h"
1088	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1089	#undef PGM_BTH_NAME
1090	#undef PGM_BTH_NAME_RC_STR
1091	#undef PGM_BTH_NAME_R0_STR
1092	#undef PGM_GST_TYPE
1093	#undef PGM_GST_NAME
1094	#undef PGM_GST_NAME_RC_STR
1095	#undef PGM_GST_NAME_R0_STR
1096
1097	/* Guest - 32-bit mode */
1098	#define PGM_GST_TYPE PGM_TYPE_32BIT
1099	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1100	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1101	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1102	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1103	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1104	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1105	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1106	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1107	#include "PGMGstDefs.h"
1108	#include "PGMBth.h"
1109	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1110	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1111	#undef PGM_BTH_NAME
1112	#undef PGM_BTH_NAME_RC_STR
1113	#undef PGM_BTH_NAME_R0_STR
1114	#undef PGM_GST_TYPE
1115	#undef PGM_GST_NAME
1116	#undef PGM_GST_NAME_RC_STR
1117	#undef PGM_GST_NAME_R0_STR
1118
1119	/* Guest - PAE mode */
1120	#define PGM_GST_TYPE PGM_TYPE_PAE
1121	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1122	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1123	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1124	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1125	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1126	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1127	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1128	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1129	#include "PGMGstDefs.h"
1130	#include "PGMBth.h"
1131	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1132	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1133	#undef PGM_BTH_NAME
1134	#undef PGM_BTH_NAME_RC_STR
1135	#undef PGM_BTH_NAME_R0_STR
1136	#undef PGM_GST_TYPE
1137	#undef PGM_GST_NAME
1138	#undef PGM_GST_NAME_RC_STR
1139	#undef PGM_GST_NAME_R0_STR
1140
1141	#ifdef VBOX_WITH_64_BITS_GUESTS
1142	/* Guest - AMD64 mode */
1143	# define PGM_GST_TYPE PGM_TYPE_AMD64
1144	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1145	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1146	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1147	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1148	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1149	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1150	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1151	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1152	# include "PGMGstDefs.h"
1153	# include "PGMBth.h"
1154	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1155	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1156	# undef PGM_BTH_NAME
1157	# undef PGM_BTH_NAME_RC_STR
1158	# undef PGM_BTH_NAME_R0_STR
1159	# undef PGM_GST_TYPE
1160	# undef PGM_GST_NAME
1161	# undef PGM_GST_NAME_RC_STR
1162	# undef PGM_GST_NAME_R0_STR
1163	#endif /* VBOX_WITH_64_BITS_GUESTS */
1164
1165	#undef PGM_SHW_TYPE
1166	#undef PGM_SHW_NAME
1167	#undef PGM_SHW_NAME_RC_STR
1168	#undef PGM_SHW_NAME_R0_STR
1169
1170
1171
1172	/**
1173	* Initiates the paging of VM.
1174	*
1175	* @returns VBox status code.
1176	* @param pVM Pointer to VM structure.
1177	*/
1178	VMMR3DECL(int) PGMR3Init(PVM pVM)
1179	{
1180	LogFlow(("PGMR3Init:\n"));
1181	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1182	int rc;
1183
1184	/*
1185	* Assert alignment and sizes.
1186	*/
1187	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1188	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1189	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1190
1191	/*
1192	* Init the structure.
1193	*/
1194	#ifdef PGM_WITHOUT_MAPPINGS
1195	pVM->pgm.s.fMappingsDisabled = true;
1196	#endif
1197	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1198	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1199
1200	/* Init the per-CPU part. */
1201	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1202	{
1203	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1204	PPGMCPU pPGM = &pVCpu->pgm.s;
1205
1206	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1207	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1208	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1209
1210	pPGM->enmShadowMode = PGMMODE_INVALID;
1211	pPGM->enmGuestMode = PGMMODE_INVALID;
1212
1213	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1214
1215	pPGM->pGst32BitPdR3 = NULL;
1216	pPGM->pGstPaePdptR3 = NULL;
1217	pPGM->pGstAmd64Pml4R3 = NULL;
1218	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1219	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1220	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1221	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1222	#endif
1223	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1224	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1225	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1226	{
1227	pPGM->apGstPaePDsR3[i] = NULL;
1228	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1229	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1230	#endif
1231	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1232	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1233	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1234	}
1235
1236	pPGM->fA20Enabled = true;
1237	}
1238
1239	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1240	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1241	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1242
1243	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1244	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1245	true
1246	#else
1247	false
1248	#endif
1249	);
1250	AssertLogRelRCReturn(rc, rc);
1251
1252	#ifdef PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
1253	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1254	#else
1255	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1256	#endif
1257	AssertLogRelRCReturn(rc, rc);
1258	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1259	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1260
1261	/*
1262	* Get the configured RAM size - to estimate saved state size.
1263	*/
1264	uint64_t cbRam;
1265	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1266	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1267	cbRam = 0;
1268	else if (RT_SUCCESS(rc))
1269	{
1270	if (cbRam < PAGE_SIZE)
1271	cbRam = 0;
1272	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1273	}
1274	else
1275	{
1276	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1277	return rc;
1278	}
1279
1280	/*
1281	* Register callbacks, string formatters and the saved state data unit.
1282	*/
1283	#ifdef VBOX_STRICT
1284	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1285	#endif
1286	PGMRegisterStringFormatTypes();
1287
1288	rc = pgmR3InitSavedState(pVM, cbRam);
1289	if (RT_FAILURE(rc))
1290	return rc;
1291
1292	/*
1293	* Initialize the PGM critical section and flush the phys TLBs
1294	*/
1295	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, RT_SRC_POS, "PGM");
1296	AssertRCReturn(rc, rc);
1297
1298	PGMR3PhysChunkInvalidateTLB(pVM);
1299	PGMPhysInvalidatePageMapTLB(pVM);
1300
1301	/*
1302	* For the time being we sport a full set of handy pages in addition to the base
1303	* memory to simplify things.
1304	*/
1305	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1306	AssertRCReturn(rc, rc);
1307
1308	/*
1309	* Trees
1310	*/
1311	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1312	if (RT_SUCCESS(rc))
1313	{
1314	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1315	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1316
1317	/*
1318	* Alocate the zero page.
1319	*/
1320	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1321	}
1322	if (RT_SUCCESS(rc))
1323	{
1324	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1325	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1326	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1327	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1328
1329	/*
1330	* Init the paging.
1331	*/
1332	rc = pgmR3InitPaging(pVM);
1333	}
1334	if (RT_SUCCESS(rc))
1335	{
1336	/*
1337	* Init the page pool.
1338	*/
1339	rc = pgmR3PoolInit(pVM);
1340	}
1341	if (RT_SUCCESS(rc))
1342	{
1343	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1344	{
1345	PVMCPU pVCpu = &pVM->aCpus[i];
1346	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1347	if (RT_FAILURE(rc))
1348	break;
1349	}
1350	}
1351
1352	if (RT_SUCCESS(rc))
1353	{
1354	/*
1355	* Info & statistics
1356	*/
1357	DBGFR3InfoRegisterInternal(pVM, "mode",
1358	"Shows the current paging mode. "
1359	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1360	pgmR3InfoMode);
1361	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1362	"Dumps all the entries in the top level paging table. No arguments.",
1363	pgmR3InfoCr3);
1364	DBGFR3InfoRegisterInternal(pVM, "phys",
1365	"Dumps all the physical address ranges. No arguments.",
1366	pgmR3PhysInfo);
1367	DBGFR3InfoRegisterInternal(pVM, "handlers",
1368	"Dumps physical, virtual and hyper virtual handlers. "
1369	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1370	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1371	pgmR3InfoHandlers);
1372	DBGFR3InfoRegisterInternal(pVM, "mappings",
1373	"Dumps guest mappings.",
1374	pgmR3MapInfo);
1375
1376	pgmR3InitStats(pVM);
1377
1378	#ifdef VBOX_WITH_DEBUGGER
1379	/*
1380	* Debugger commands.
1381	*/
1382	static bool s_fRegisteredCmds = false;
1383	if (!s_fRegisteredCmds)
1384	{
1385	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1386	if (RT_SUCCESS(rc2))
1387	s_fRegisteredCmds = true;
1388	}
1389	#endif
1390	return VINF_SUCCESS;
1391	}
1392
1393	/* Almost no cleanup necessary, MM frees all memory. */
1394	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1395
1396	return rc;
1397	}
1398
1399
1400	/**
1401	* Initializes the per-VCPU PGM.
1402	*
1403	* @returns VBox status code.
1404	* @param pVM The VM to operate on.
1405	*/
1406	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1407	{
1408	LogFlow(("PGMR3InitCPU\n"));
1409	return VINF_SUCCESS;
1410	}
1411
1412
1413	/**
1414	* Init paging.
1415	*
1416	* Since we need to check what mode the host is operating in before we can choose
1417	* the right paging functions for the host we have to delay this until R0 has
1418	* been initialized.
1419	*
1420	* @returns VBox status code.
1421	* @param pVM VM handle.
1422	*/
1423	static int pgmR3InitPaging(PVM pVM)
1424	{
1425	/*
1426	* Force a recalculation of modes and switcher so everyone gets notified.
1427	*/
1428	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1429	{
1430	PVMCPU pVCpu = &pVM->aCpus[i];
1431
1432	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1433	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1434	}
1435
1436	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1437
1438	/*
1439	* Allocate static mapping space for whatever the cr3 register
1440	* points to and in the case of PAE mode to the 4 PDs.
1441	*/
1442	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1443	if (RT_FAILURE(rc))
1444	{
1445	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1446	return rc;
1447	}
1448	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1449
1450	/*
1451	* Allocate pages for the three possible intermediate contexts
1452	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1453	* for the sake of simplicity. The AMD64 uses the PAE for the
1454	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1455	*
1456	* We assume that two page tables will be enought for the core code
1457	* mappings (HC virtual and identity).
1458	*/
1459	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1460	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1463	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1464	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1465	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1466	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1467	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1468	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1469	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1470	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1471
1472	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1473	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1474	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1475	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1476	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1477	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1478
1479	/*
1480	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1481	*/
1482	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1483	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1484	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1485
1486	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1487	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1488
1489	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1490	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1491	{
1492	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1493	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1494	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1495	}
1496
1497	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1498	{
1499	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1500	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1501	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1502	}
1503
1504	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1505	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1506	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1507	\| HCPhysInterPaePDPT64;
1508
1509	/*
1510	* Initialize paging workers and mode from current host mode
1511	* and the guest running in real mode.
1512	*/
1513	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1514	switch (pVM->pgm.s.enmHostMode)
1515	{
1516	case SUPPAGINGMODE_32_BIT:
1517	case SUPPAGINGMODE_32_BIT_GLOBAL:
1518	case SUPPAGINGMODE_PAE:
1519	case SUPPAGINGMODE_PAE_GLOBAL:
1520	case SUPPAGINGMODE_PAE_NX:
1521	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1522	break;
1523
1524	case SUPPAGINGMODE_AMD64:
1525	case SUPPAGINGMODE_AMD64_GLOBAL:
1526	case SUPPAGINGMODE_AMD64_NX:
1527	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1528	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1529	if (ARCH_BITS != 64)
1530	{
1531	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1532	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1533	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1534	}
1535	#endif
1536	break;
1537	default:
1538	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1539	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1540	}
1541	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1542	if (RT_SUCCESS(rc))
1543	{
1544	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1545	#if HC_ARCH_BITS == 64
1546	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1547	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1548	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1549	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1550	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1551	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1552	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1553	#endif
1554
1555	return VINF_SUCCESS;
1556	}
1557
1558	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1559	return rc;
1560	}
1561
1562
1563	/**
1564	* Init statistics
1565	*/
1566	static void pgmR3InitStats(PVM pVM)
1567	{
1568	PPGM pPGM = &pVM->pgm.s;
1569	int rc;
1570
1571	/* Common - misc variables */
1572	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1573	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1574	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1575	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1576	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1577	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1578	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1579	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1580	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1581	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1582	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1583	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1584	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1585	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1586	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1587	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1588	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1589
1590	STAM_REL_REG(pVM, &pPGM->StatLargePageAlloc, STAMTYPE_COUNTER, "/PGM/LargePage/Alloc", STAMUNIT_OCCURENCES, "The number of large pages we've used.");
1591	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1592	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1593	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1594
1595	/* Live save */
1596	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1597	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1598	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1599	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1600	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1601	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1602	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1603	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1604	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1605	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1606	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1607	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1608	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1609	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1610	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1611	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1612	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1613	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1614
1615	#ifdef VBOX_WITH_STATISTICS
1616
1617	# define PGM_REG_COUNTER(a, b, c) \
1618	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1619	AssertRC(rc);
1620
1621	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1622	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1623	AssertRC(rc);
1624
1625	# define PGM_REG_PROFILE(a, b, c) \
1626	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1627	AssertRC(rc);
1628
1629	PGM_REG_PROFILE(&pPGM->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1630	PGM_REG_PROFILE(&pPGM->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1631	PGM_REG_PROFILE(&pPGM->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1632	PGM_REG_PROFILE(&pPGM->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1633
1634	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1635	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1636	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1637	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1638	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1639	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1640	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1641	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1642	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1643	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1644
1645	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1646	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1647	PGM_REG_PROFILE(&pPGM->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1648	PGM_REG_PROFILE(&pPGM->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1649	PGM_REG_PROFILE(&pPGM->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1650	PGM_REG_PROFILE(&pPGM->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1651
1652	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1653	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1654	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1655	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1656	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1657	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1658	PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1659	PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1660
1661	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1662	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1663	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1664	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1665
1666	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1667	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1668	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1669	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1670
1671	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1672	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1673	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1674	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1675	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1676	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1677
1678	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1679	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1680	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1681	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1682	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1683	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1684	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1685	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1686
1687	/* GC only: */
1688	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1689	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1690	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1691	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1692
1693	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1694	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1695	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1696	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1697	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1698	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1699	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1700	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1701
1702	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1703	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1704	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1705	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1706	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1707	PGM_REG_COUNTER(&pPGM->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1708	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1709
1710	# undef PGM_REG_COUNTER
1711	# undef PGM_REG_PROFILE
1712	#endif
1713
1714	/*
1715	* Note! The layout below matches the member layout exactly!
1716	*/
1717
1718	/*
1719	* Common - stats
1720	*/
1721	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1722	{
1723	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1724
1725	#define PGM_REG_COUNTER(a, b, c) \
1726	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1727	AssertRC(rc);
1728	#define PGM_REG_PROFILE(a, b, c) \
1729	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1730	AssertRC(rc);
1731
1732	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1733
1734	#ifdef VBOX_WITH_STATISTICS
1735
1736	# if 0 /* rarely useful; leave for debugging. */
1737	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1738	STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1739	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1740	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPagePD); j++)
1741	STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1742	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1743	# endif
1744	/* R0 only: */
1745	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapMigrateInvlPg, "/PGM/CPU%u/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1746	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapGCPageInl, "/PGM/CPU%u/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1747	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1748	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1749	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1750	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1751	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPageInl, "/PGM/CPU%u/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1752	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlHits, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1753	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1754	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPage, "/PGM/CPU%u/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1755	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetOptimize, "/PGM/CPU%u/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1756	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchFlushes, "/PGM/CPU%u/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1757	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchHits, "/PGM/CPU%u/R0/DynMapPage/SetSearchHits", "Set search hits.");
1758	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchMisses, "/PGM/CPU%u/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1759	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPage, "/PGM/CPU%u/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1760	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits0, "/PGM/CPU%u/R0/DynMapPage/Hits0", "Hits at iPage+0");
1761	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits1, "/PGM/CPU%u/R0/DynMapPage/Hits1", "Hits at iPage+1");
1762	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits2, "/PGM/CPU%u/R0/DynMapPage/Hits2", "Hits at iPage+2");
1763	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageInvlPg, "/PGM/CPU%u/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1764	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlow, "/PGM/CPU%u/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1765	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%u/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1766	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%u/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1767	//PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMapPage/SlowLostHits", "Lost hits.");
1768	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSubsets, "/PGM/CPU%u/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1769	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPopFlushes, "/PGM/CPU%u/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1770	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[0], "/PGM/CPU%u/R0/SetSize000..09", "00-09% filled");
1771	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[1], "/PGM/CPU%u/R0/SetSize010..19", "10-19% filled");
1772	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[2], "/PGM/CPU%u/R0/SetSize020..29", "20-29% filled");
1773	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[3], "/PGM/CPU%u/R0/SetSize030..39", "30-39% filled");
1774	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[4], "/PGM/CPU%u/R0/SetSize040..49", "40-49% filled");
1775	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[5], "/PGM/CPU%u/R0/SetSize050..59", "50-59% filled");
1776	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[6], "/PGM/CPU%u/R0/SetSize060..69", "60-69% filled");
1777	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[7], "/PGM/CPU%u/R0/SetSize070..79", "70-79% filled");
1778	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[8], "/PGM/CPU%u/R0/SetSize080..89", "80-89% filled");
1779	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[9], "/PGM/CPU%u/R0/SetSize090..99", "90-99% filled");
1780	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[10], "/PGM/CPU%u/R0/SetSize100", "100% filled");
1781
1782	/* RZ only: */
1783	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1784	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%u/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1785	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeSyncPT, "/PGM/CPU%u/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1786	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeMapping, "/PGM/CPU%u/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1787	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1788	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeHandlers, "/PGM/CPU%u/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1789	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1790	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1791	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1792	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1793	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1794	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1795	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1796	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1797	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1798	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1799	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1800	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1801	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1802	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1803	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1804	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersPhysical, "/PGM/CPU%u/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1805	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1806	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1807	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1808	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1809	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1810	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1811	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1812	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1813	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1814	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1815	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1816	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1817	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1818	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1819	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1820	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1821	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1822	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFUnh, "/PGM/CPU%u/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1823	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1824	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1825	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1826	#if 0 /* rarely useful; leave for debugging. */
1827	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatRZTrap0ePD); j++)
1828	STAMR3RegisterF(pVM, &pPgmCpu->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1829	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1830	#endif
1831	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1832	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1833	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1834	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1835	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1836
1837	/* HC only: */
1838
1839	/* RZ & R3: */
1840	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1841	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1842	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1843	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1844	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1845	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1846	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1847	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1848	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1849	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1850	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1851	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1852	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1853	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1854	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1855	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1856	PGM_REG_COUNTER(&pPgmCpu->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1857	PGM_REG_PROFILE(&pPgmCpu->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1858	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1859	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1860	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1861	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1862	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1863	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1864	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1865	PGM_REG_COUNTER(&pPgmCpu->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1866	PGM_REG_PROFILE(&pPgmCpu->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1867	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1868	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1869	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1870	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1871	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1872	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1873	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1874	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1875	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1876	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1877	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1878	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1879	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1880	PGM_REG_PROFILE(&pPgmCpu->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1881	PGM_REG_PROFILE(&pPgmCpu->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1882	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1883	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1884	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1885	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1886	PGM_REG_PROFILE(&pPgmCpu->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1887
1888	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1889	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1890	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1891	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1892	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1893	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1894	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1895	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1896	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1897	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1898	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1899	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1900	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1901	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1902	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1903	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1904	PGM_REG_COUNTER(&pPgmCpu->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1905	PGM_REG_PROFILE(&pPgmCpu->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1906	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1907	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1908	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1909	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1910	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1911	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1912	PGM_REG_COUNTER(&pPgmCpu->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1913	PGM_REG_PROFILE(&pPgmCpu->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1914	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1915	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1916	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1917	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1918	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1919	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1920	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1921	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1922	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1923	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1924	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1925	PGM_REG_PROFILE(&pPgmCpu->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1926	PGM_REG_PROFILE(&pPgmCpu->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1927	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1928	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1929	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1930	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1931	PGM_REG_PROFILE(&pPgmCpu->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1932	#endif /* VBOX_WITH_STATISTICS */
1933
1934	#undef PGM_REG_PROFILE
1935	#undef PGM_REG_COUNTER
1936
1937	}
1938	}
1939
1940
1941	/**
1942	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1943	*
1944	* The dynamic mapping area will also be allocated and initialized at this
1945	* time. We could allocate it during PGMR3Init of course, but the mapping
1946	* wouldn't be allocated at that time preventing us from setting up the
1947	* page table entries with the dummy page.
1948	*
1949	* @returns VBox status code.
1950	* @param pVM VM handle.
1951	*/
1952	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1953	{
1954	RTGCPTR GCPtr;
1955	int rc;
1956
1957	/*
1958	* Reserve space for the dynamic mappings.
1959	*/
1960	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1961	if (RT_SUCCESS(rc))
1962	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1963
1964	if ( RT_SUCCESS(rc)
1965	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1966	{
1967	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1968	if (RT_SUCCESS(rc))
1969	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1970	}
1971	if (RT_SUCCESS(rc))
1972	{
1973	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1974	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1975	}
1976	return rc;
1977	}
1978
1979
1980	/**
1981	* Ring-3 init finalizing.
1982	*
1983	* @returns VBox status code.
1984	* @param pVM The VM handle.
1985	*/
1986	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1987	{
1988	int rc;
1989
1990	/*
1991	* Reserve space for the dynamic mappings.
1992	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1993	*/
1994	/* get the pointer to the page table entries. */
1995	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1996	AssertRelease(pMapping);
1997	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1998	const unsigned iPT = off >> X86_PD_SHIFT;
1999	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2000	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2001	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2002
2003	/* init cache */
2004	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2005	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
2006	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
2007
2008	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
2009	{
2010	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
2011	AssertRCReturn(rc, rc);
2012	}
2013
2014	/*
2015	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2016	* Intel only goes up to 36 bits, so we stick to 36 as well.
2017	*/
2018	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
2019	uint32_t u32Dummy, u32Features;
2020	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2021
2022	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2023	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
2024	else
2025	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2026
2027	/*
2028	* Allocate memory if we're supposed to do that.
2029	*/
2030	if (pVM->pgm.s.fRamPreAlloc)
2031	rc = pgmR3PhysRamPreAllocate(pVM);
2032
2033	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2034	return rc;
2035	}
2036
2037
2038	/**
2039	* Applies relocations to data and code managed by this component.
2040	*
2041	* This function will be called at init and whenever the VMM need to relocate it
2042	* self inside the GC.
2043	*
2044	* @param pVM The VM.
2045	* @param offDelta Relocation delta relative to old location.
2046	*/
2047	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2048	{
2049	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2050
2051	/*
2052	* Paging stuff.
2053	*/
2054	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2055
2056	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2057
2058	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2059	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2060	{
2061	PVMCPU pVCpu = &pVM->aCpus[i];
2062
2063	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2064
2065	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2066	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2067	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2068	}
2069
2070	/*
2071	* Trees.
2072	*/
2073	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2074
2075	/*
2076	* Ram ranges.
2077	*/
2078	if (pVM->pgm.s.pRamRangesR3)
2079	{
2080	/* Update the pSelfRC pointers and relink them. */
2081	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2082	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2083	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2084	pgmR3PhysRelinkRamRanges(pVM);
2085	}
2086
2087	/*
2088	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2089	* be mapped and thus not included in the above exercise.
2090	*/
2091	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2092	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2093	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2094
2095	/*
2096	* Update the two page directories with all page table mappings.
2097	* (One or more of them have changed, that's why we're here.)
2098	*/
2099	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2100	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2101	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2102
2103	/* Relocate GC addresses of Page Tables. */
2104	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2105	{
2106	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2107	{
2108	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2109	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2110	}
2111	}
2112
2113	/*
2114	* Dynamic page mapping area.
2115	*/
2116	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2117	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2118	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2119
2120	/*
2121	* The Zero page.
2122	*/
2123	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2124	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2125	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2126	#else
2127	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2128	#endif
2129
2130	/*
2131	* Physical and virtual handlers.
2132	*/
2133	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2134	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2135	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2136
2137	/*
2138	* The page pool.
2139	*/
2140	pgmR3PoolRelocate(pVM);
2141	}
2142
2143
2144	/**
2145	* Callback function for relocating a physical access handler.
2146	*
2147	* @returns 0 (continue enum)
2148	* @param pNode Pointer to a PGMPHYSHANDLER node.
2149	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2150	* not certain the delta will fit in a void pointer for all possible configs.
2151	*/
2152	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2153	{
2154	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2155	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2156	if (pHandler->pfnHandlerRC)
2157	pHandler->pfnHandlerRC += offDelta;
2158	if (pHandler->pvUserRC >= 0x10000)
2159	pHandler->pvUserRC += offDelta;
2160	return 0;
2161	}
2162
2163
2164	/**
2165	* Callback function for relocating a virtual access handler.
2166	*
2167	* @returns 0 (continue enum)
2168	* @param pNode Pointer to a PGMVIRTHANDLER node.
2169	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2170	* not certain the delta will fit in a void pointer for all possible configs.
2171	*/
2172	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2173	{
2174	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2175	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2176	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2177	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2178	Assert(pHandler->pfnHandlerRC);
2179	pHandler->pfnHandlerRC += offDelta;
2180	return 0;
2181	}
2182
2183
2184	/**
2185	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2186	*
2187	* @returns 0 (continue enum)
2188	* @param pNode Pointer to a PGMVIRTHANDLER node.
2189	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2190	* not certain the delta will fit in a void pointer for all possible configs.
2191	*/
2192	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2193	{
2194	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2195	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2196	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2197	Assert(pHandler->pfnHandlerRC);
2198	pHandler->pfnHandlerRC += offDelta;
2199	return 0;
2200	}
2201
2202
2203	/**
2204	* Resets a virtual CPU when unplugged.
2205	*
2206	* @param pVM The VM handle.
2207	* @param pVCpu The virtual CPU handle.
2208	*/
2209	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2210	{
2211	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2212	AssertRC(rc);
2213
2214	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2215	AssertRC(rc);
2216
2217	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2218
2219	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2220
2221	/*
2222	* Re-init other members.
2223	*/
2224	pVCpu->pgm.s.fA20Enabled = true;
2225
2226	/*
2227	* Clear the FFs PGM owns.
2228	*/
2229	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2230	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2231	}
2232
2233
2234	/**
2235	* The VM is being reset.
2236	*
2237	* For the PGM component this means that any PD write monitors
2238	* needs to be removed.
2239	*
2240	* @param pVM VM handle.
2241	*/
2242	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2243	{
2244	int rc;
2245
2246	LogFlow(("PGMR3Reset:\n"));
2247	VM_ASSERT_EMT(pVM);
2248
2249	pgmLock(pVM);
2250
2251	/*
2252	* Unfix any fixed mappings and disable CR3 monitoring.
2253	*/
2254	pVM->pgm.s.fMappingsFixed = false;
2255	pVM->pgm.s.fMappingsFixedRestored = false;
2256	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2257	pVM->pgm.s.cbMappingFixed = 0;
2258
2259	/*
2260	* Exit the guest paging mode before the pgm pool gets reset.
2261	* Important to clean up the amd64 case.
2262	*/
2263	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2264	{
2265	PVMCPU pVCpu = &pVM->aCpus[i];
2266	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2267	AssertRC(rc);
2268	}
2269
2270	#ifdef DEBUG
2271	DBGFR3InfoLog(pVM, "mappings", NULL);
2272	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2273	#endif
2274
2275	/*
2276	* Switch mode back to real mode. (before resetting the pgm pool!)
2277	*/
2278	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2279	{
2280	PVMCPU pVCpu = &pVM->aCpus[i];
2281
2282	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2283	AssertRC(rc);
2284
2285	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2286	}
2287
2288	/*
2289	* Reset the shadow page pool.
2290	*/
2291	pgmR3PoolReset(pVM);
2292
2293	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2294	{
2295	PVMCPU pVCpu = &pVM->aCpus[i];
2296
2297	/*
2298	* Re-init other members.
2299	*/
2300	pVCpu->pgm.s.fA20Enabled = true;
2301
2302	/*
2303	* Clear the FFs PGM owns.
2304	*/
2305	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2306	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2307	}
2308
2309	/*
2310	* Reset (zero) RAM pages.
2311	*/
2312	rc = pgmR3PhysRamReset(pVM);
2313	if (RT_SUCCESS(rc))
2314	{
2315	/*
2316	* Reset (zero) shadow ROM pages.
2317	*/
2318	rc = pgmR3PhysRomReset(pVM);
2319	}
2320
2321	pgmUnlock(pVM);
2322	AssertReleaseRC(rc);
2323	}
2324
2325
2326	#ifdef VBOX_STRICT
2327	/**
2328	* VM state change callback for clearing fNoMorePhysWrites after
2329	* a snapshot has been created.
2330	*/
2331	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2332	{
2333	if ( enmState == VMSTATE_RUNNING
2334	\|\| enmState == VMSTATE_RESUMING)
2335	pVM->pgm.s.fNoMorePhysWrites = false;
2336	}
2337	#endif
2338
2339
2340	/**
2341	* Terminates the PGM.
2342	*
2343	* @returns VBox status code.
2344	* @param pVM Pointer to VM structure.
2345	*/
2346	VMMR3DECL(int) PGMR3Term(PVM pVM)
2347	{
2348	/* Must free shared pages here. */
2349	pgmLock(pVM);
2350	pgmR3PhysRamTerm(pVM);
2351	pgmUnlock(pVM);
2352
2353	PGMDeregisterStringFormatTypes();
2354	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2355	}
2356
2357
2358	/**
2359	* Terminates the per-VCPU PGM.
2360	*
2361	* Termination means cleaning up and freeing all resources,
2362	* the VM it self is at this point powered off or suspended.
2363	*
2364	* @returns VBox status code.
2365	* @param pVM The VM to operate on.
2366	*/
2367	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2368	{
2369	return 0;
2370	}
2371
2372
2373	/**
2374	* Show paging mode.
2375	*
2376	* @param pVM VM Handle.
2377	* @param pHlp The info helpers.
2378	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2379	*/
2380	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2381	{
2382	/* digest argument. */
2383	bool fGuest, fShadow, fHost;
2384	if (pszArgs)
2385	pszArgs = RTStrStripL(pszArgs);
2386	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2387	fShadow = fHost = fGuest = true;
2388	else
2389	{
2390	fShadow = fHost = fGuest = false;
2391	if (strstr(pszArgs, "guest"))
2392	fGuest = true;
2393	if (strstr(pszArgs, "shadow"))
2394	fShadow = true;
2395	if (strstr(pszArgs, "host"))
2396	fHost = true;
2397	}
2398
2399	/** @todo SMP support! */
2400	/* print info. */
2401	if (fGuest)
2402	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2403	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2404	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2405	if (fShadow)
2406	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2407	if (fHost)
2408	{
2409	const char *psz;
2410	switch (pVM->pgm.s.enmHostMode)
2411	{
2412	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2413	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2414	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2415	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2416	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2417	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2418	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2419	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2420	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2421	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2422	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2423	default: psz = "unknown"; break;
2424	}
2425	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2426	}
2427	}
2428
2429
2430	/**
2431	* Dump registered MMIO ranges to the log.
2432	*
2433	* @param pVM VM Handle.
2434	* @param pHlp The info helpers.
2435	* @param pszArgs Arguments, ignored.
2436	*/
2437	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2438	{
2439	NOREF(pszArgs);
2440	pHlp->pfnPrintf(pHlp,
2441	"RAM ranges (pVM=%p)\n"
2442	"%.s %.s\n",
2443	pVM,
2444	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2445	sizeof(RTHCPTR) * 2, "pvHC ");
2446
2447	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2448	pHlp->pfnPrintf(pHlp,
2449	"%RGp-%RGp %RHv %s\n",
2450	pCur->GCPhys,
2451	pCur->GCPhysLast,
2452	pCur->pvR3,
2453	pCur->pszDesc);
2454	}
2455
2456	/**
2457	* Dump the page directory to the log.
2458	*
2459	* @param pVM VM Handle.
2460	* @param pHlp The info helpers.
2461	* @param pszArgs Arguments, ignored.
2462	*/
2463	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2464	{
2465	/** @todo SMP support!! */
2466	PVMCPU pVCpu = &pVM->aCpus[0];
2467
2468	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2469	/* Big pages supported? */
2470	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2471
2472	/* Global pages supported? */
2473	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2474
2475	NOREF(pszArgs);
2476
2477	/*
2478	* Get page directory addresses.
2479	*/
2480	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2481	Assert(pPDSrc);
2482	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2483
2484	/*
2485	* Iterate the page directory.
2486	*/
2487	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2488	{
2489	X86PDE PdeSrc = pPDSrc->a[iPD];
2490	if (PdeSrc.n.u1Present)
2491	{
2492	if (PdeSrc.b.u1Size && fPSE)
2493	pHlp->pfnPrintf(pHlp,
2494	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2495	iPD,
2496	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2497	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2498	else
2499	pHlp->pfnPrintf(pHlp,
2500	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2501	iPD,
2502	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2503	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2504	}
2505	}
2506	}
2507
2508
2509	/**
2510	* Service a VMMCALLRING3_PGM_LOCK call.
2511	*
2512	* @returns VBox status code.
2513	* @param pVM The VM handle.
2514	*/
2515	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2516	{
2517	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2518	AssertRC(rc);
2519	return rc;
2520	}
2521
2522
2523	/**
2524	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2525	*
2526	* @returns PGM_TYPE_*.
2527	* @param pgmMode The mode value to convert.
2528	*/
2529	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2530	{
2531	switch (pgmMode)
2532	{
2533	case PGMMODE_REAL: return PGM_TYPE_REAL;
2534	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2535	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2536	case PGMMODE_PAE:
2537	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2538	case PGMMODE_AMD64:
2539	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2540	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2541	case PGMMODE_EPT: return PGM_TYPE_EPT;
2542	default:
2543	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2544	}
2545	}
2546
2547
2548	/**
2549	* Gets the index into the paging mode data array of a SHW+GST mode.
2550	*
2551	* @returns PGM::paPagingData index.
2552	* @param uShwType The shadow paging mode type.
2553	* @param uGstType The guest paging mode type.
2554	*/
2555	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2556	{
2557	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2558	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2559	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2560	+ (uGstType - PGM_TYPE_REAL);
2561	}
2562
2563
2564	/**
2565	* Gets the index into the paging mode data array of a SHW+GST mode.
2566	*
2567	* @returns PGM::paPagingData index.
2568	* @param enmShw The shadow paging mode.
2569	* @param enmGst The guest paging mode.
2570	*/
2571	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2572	{
2573	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2574	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2575	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2576	}
2577
2578
2579	/**
2580	* Calculates the max data index.
2581	* @returns The number of entries in the paging data array.
2582	*/
2583	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2584	{
2585	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2586	}
2587
2588
2589	/**
2590	* Initializes the paging mode data kept in PGM::paModeData.
2591	*
2592	* @param pVM The VM handle.
2593	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2594	* This is used early in the init process to avoid trouble with PDM
2595	* not being initialized yet.
2596	*/
2597	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2598	{
2599	PPGMMODEDATA pModeData;
2600	int rc;
2601
2602	/*
2603	* Allocate the array on the first call.
2604	*/
2605	if (!pVM->pgm.s.paModeData)
2606	{
2607	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2608	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2609	}
2610
2611	/*
2612	* Initialize the array entries.
2613	*/
2614	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2615	pModeData->uShwType = PGM_TYPE_32BIT;
2616	pModeData->uGstType = PGM_TYPE_REAL;
2617	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2618	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2619	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2620
2621	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2622	pModeData->uShwType = PGM_TYPE_32BIT;
2623	pModeData->uGstType = PGM_TYPE_PROT;
2624	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2625	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2626	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2627
2628	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2629	pModeData->uShwType = PGM_TYPE_32BIT;
2630	pModeData->uGstType = PGM_TYPE_32BIT;
2631	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2632	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2633	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2634
2635	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2636	pModeData->uShwType = PGM_TYPE_PAE;
2637	pModeData->uGstType = PGM_TYPE_REAL;
2638	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2639	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2640	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2641
2642	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2643	pModeData->uShwType = PGM_TYPE_PAE;
2644	pModeData->uGstType = PGM_TYPE_PROT;
2645	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2646	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2647	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2648
2649	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2650	pModeData->uShwType = PGM_TYPE_PAE;
2651	pModeData->uGstType = PGM_TYPE_32BIT;
2652	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2653	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2654	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2655
2656	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2657	pModeData->uShwType = PGM_TYPE_PAE;
2658	pModeData->uGstType = PGM_TYPE_PAE;
2659	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2660	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2661	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2662
2663	#ifdef VBOX_WITH_64_BITS_GUESTS
2664	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2665	pModeData->uShwType = PGM_TYPE_AMD64;
2666	pModeData->uGstType = PGM_TYPE_AMD64;
2667	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2668	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2669	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2670	#endif
2671
2672	/* The nested paging mode. */
2673	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2674	pModeData->uShwType = PGM_TYPE_NESTED;
2675	pModeData->uGstType = PGM_TYPE_REAL;
2676	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2677	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2678
2679	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2680	pModeData->uShwType = PGM_TYPE_NESTED;
2681	pModeData->uGstType = PGM_TYPE_PROT;
2682	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2683	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2684
2685	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2686	pModeData->uShwType = PGM_TYPE_NESTED;
2687	pModeData->uGstType = PGM_TYPE_32BIT;
2688	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2689	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2690
2691	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2692	pModeData->uShwType = PGM_TYPE_NESTED;
2693	pModeData->uGstType = PGM_TYPE_PAE;
2694	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2695	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2696
2697	#ifdef VBOX_WITH_64_BITS_GUESTS
2698	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2699	pModeData->uShwType = PGM_TYPE_NESTED;
2700	pModeData->uGstType = PGM_TYPE_AMD64;
2701	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2702	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2703	#endif
2704
2705	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2706	switch (pVM->pgm.s.enmHostMode)
2707	{
2708	#if HC_ARCH_BITS == 32
2709	case SUPPAGINGMODE_32_BIT:
2710	case SUPPAGINGMODE_32_BIT_GLOBAL:
2711	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2712	{
2713	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2714	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2715	}
2716	# ifdef VBOX_WITH_64_BITS_GUESTS
2717	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2718	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2719	# endif
2720	break;
2721
2722	case SUPPAGINGMODE_PAE:
2723	case SUPPAGINGMODE_PAE_NX:
2724	case SUPPAGINGMODE_PAE_GLOBAL:
2725	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2726	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2727	{
2728	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2729	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2730	}
2731	# ifdef VBOX_WITH_64_BITS_GUESTS
2732	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2733	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2734	# endif
2735	break;
2736	#endif /* HC_ARCH_BITS == 32 */
2737
2738	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2739	case SUPPAGINGMODE_AMD64:
2740	case SUPPAGINGMODE_AMD64_GLOBAL:
2741	case SUPPAGINGMODE_AMD64_NX:
2742	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2743	# ifdef VBOX_WITH_64_BITS_GUESTS
2744	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2745	# else
2746	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2747	# endif
2748	{
2749	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2750	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2751	}
2752	break;
2753	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2754
2755	default:
2756	AssertFailed();
2757	break;
2758	}
2759
2760	/* Extended paging (EPT) / Intel VT-x */
2761	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2762	pModeData->uShwType = PGM_TYPE_EPT;
2763	pModeData->uGstType = PGM_TYPE_REAL;
2764	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2765	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2766	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2767
2768	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2769	pModeData->uShwType = PGM_TYPE_EPT;
2770	pModeData->uGstType = PGM_TYPE_PROT;
2771	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2772	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2773	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2774
2775	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2776	pModeData->uShwType = PGM_TYPE_EPT;
2777	pModeData->uGstType = PGM_TYPE_32BIT;
2778	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2779	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2780	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2781
2782	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2783	pModeData->uShwType = PGM_TYPE_EPT;
2784	pModeData->uGstType = PGM_TYPE_PAE;
2785	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2786	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2787	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2788
2789	#ifdef VBOX_WITH_64_BITS_GUESTS
2790	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2791	pModeData->uShwType = PGM_TYPE_EPT;
2792	pModeData->uGstType = PGM_TYPE_AMD64;
2793	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2794	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2795	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2796	#endif
2797	return VINF_SUCCESS;
2798	}
2799
2800
2801	/**
2802	* Switch to different (or relocated in the relocate case) mode data.
2803	*
2804	* @param pVM The VM handle.
2805	* @param pVCpu The VMCPU to operate on.
2806	* @param enmShw The the shadow paging mode.
2807	* @param enmGst The the guest paging mode.
2808	*/
2809	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2810	{
2811	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2812
2813	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2814	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2815
2816	/* shadow */
2817	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2818	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2819	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2820	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2821	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2822
2823	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2824	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2825
2826	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2827	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2828
2829
2830	/* guest */
2831	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2832	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2833	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2834	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2835	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2836	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2837	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2838	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2839	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2840	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2841	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2842	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2843
2844	/* both */
2845	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2846	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2847	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2848	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2849	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2850	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2851	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2852	#ifdef VBOX_STRICT
2853	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2854	#endif
2855	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2856	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2857
2858	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2859	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2860	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2861	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2862	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2863	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2864	#ifdef VBOX_STRICT
2865	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2866	#endif
2867	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2868	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2869
2870	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2871	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2872	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2873	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2874	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2875	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2876	#ifdef VBOX_STRICT
2877	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2878	#endif
2879	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2880	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
2881	}
2882
2883
2884	/**
2885	* Calculates the shadow paging mode.
2886	*
2887	* @returns The shadow paging mode.
2888	* @param pVM VM handle.
2889	* @param enmGuestMode The guest mode.
2890	* @param enmHostMode The host mode.
2891	* @param enmShadowMode The current shadow mode.
2892	* @param penmSwitcher Where to store the switcher to use.
2893	* VMMSWITCHER_INVALID means no change.
2894	*/
2895	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2896	{
2897	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2898	switch (enmGuestMode)
2899	{
2900	/*
2901	* When switching to real or protected mode we don't change
2902	* anything since it's likely that we'll switch back pretty soon.
2903	*
2904	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2905	* and is supposed to determine which shadow paging and switcher to
2906	* use during init.
2907	*/
2908	case PGMMODE_REAL:
2909	case PGMMODE_PROTECTED:
2910	if ( enmShadowMode != PGMMODE_INVALID
2911	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2912	break; /* (no change) */
2913
2914	switch (enmHostMode)
2915	{
2916	case SUPPAGINGMODE_32_BIT:
2917	case SUPPAGINGMODE_32_BIT_GLOBAL:
2918	enmShadowMode = PGMMODE_32_BIT;
2919	enmSwitcher = VMMSWITCHER_32_TO_32;
2920	break;
2921
2922	case SUPPAGINGMODE_PAE:
2923	case SUPPAGINGMODE_PAE_NX:
2924	case SUPPAGINGMODE_PAE_GLOBAL:
2925	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2926	enmShadowMode = PGMMODE_PAE;
2927	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2928	#ifdef DEBUG_bird
2929	if (RTEnvExist("VBOX_32BIT"))
2930	{
2931	enmShadowMode = PGMMODE_32_BIT;
2932	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2933	}
2934	#endif
2935	break;
2936
2937	case SUPPAGINGMODE_AMD64:
2938	case SUPPAGINGMODE_AMD64_GLOBAL:
2939	case SUPPAGINGMODE_AMD64_NX:
2940	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2941	enmShadowMode = PGMMODE_PAE;
2942	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2943	#ifdef DEBUG_bird
2944	if (RTEnvExist("VBOX_32BIT"))
2945	{
2946	enmShadowMode = PGMMODE_32_BIT;
2947	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2948	}
2949	#endif
2950	break;
2951
2952	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2953	}
2954	break;
2955
2956	case PGMMODE_32_BIT:
2957	switch (enmHostMode)
2958	{
2959	case SUPPAGINGMODE_32_BIT:
2960	case SUPPAGINGMODE_32_BIT_GLOBAL:
2961	enmShadowMode = PGMMODE_32_BIT;
2962	enmSwitcher = VMMSWITCHER_32_TO_32;
2963	break;
2964
2965	case SUPPAGINGMODE_PAE:
2966	case SUPPAGINGMODE_PAE_NX:
2967	case SUPPAGINGMODE_PAE_GLOBAL:
2968	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2969	enmShadowMode = PGMMODE_PAE;
2970	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2971	#ifdef DEBUG_bird
2972	if (RTEnvExist("VBOX_32BIT"))
2973	{
2974	enmShadowMode = PGMMODE_32_BIT;
2975	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2976	}
2977	#endif
2978	break;
2979
2980	case SUPPAGINGMODE_AMD64:
2981	case SUPPAGINGMODE_AMD64_GLOBAL:
2982	case SUPPAGINGMODE_AMD64_NX:
2983	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2984	enmShadowMode = PGMMODE_PAE;
2985	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2986	#ifdef DEBUG_bird
2987	if (RTEnvExist("VBOX_32BIT"))
2988	{
2989	enmShadowMode = PGMMODE_32_BIT;
2990	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2991	}
2992	#endif
2993	break;
2994
2995	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2996	}
2997	break;
2998
2999	case PGMMODE_PAE:
3000	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3001	switch (enmHostMode)
3002	{
3003	case SUPPAGINGMODE_32_BIT:
3004	case SUPPAGINGMODE_32_BIT_GLOBAL:
3005	enmShadowMode = PGMMODE_PAE;
3006	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3007	break;
3008
3009	case SUPPAGINGMODE_PAE:
3010	case SUPPAGINGMODE_PAE_NX:
3011	case SUPPAGINGMODE_PAE_GLOBAL:
3012	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3013	enmShadowMode = PGMMODE_PAE;
3014	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3015	break;
3016
3017	case SUPPAGINGMODE_AMD64:
3018	case SUPPAGINGMODE_AMD64_GLOBAL:
3019	case SUPPAGINGMODE_AMD64_NX:
3020	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3021	enmShadowMode = PGMMODE_PAE;
3022	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3023	break;
3024
3025	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3026	}
3027	break;
3028
3029	case PGMMODE_AMD64:
3030	case PGMMODE_AMD64_NX:
3031	switch (enmHostMode)
3032	{
3033	case SUPPAGINGMODE_32_BIT:
3034	case SUPPAGINGMODE_32_BIT_GLOBAL:
3035	enmShadowMode = PGMMODE_AMD64;
3036	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3037	break;
3038
3039	case SUPPAGINGMODE_PAE:
3040	case SUPPAGINGMODE_PAE_NX:
3041	case SUPPAGINGMODE_PAE_GLOBAL:
3042	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3043	enmShadowMode = PGMMODE_AMD64;
3044	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3045	break;
3046
3047	case SUPPAGINGMODE_AMD64:
3048	case SUPPAGINGMODE_AMD64_GLOBAL:
3049	case SUPPAGINGMODE_AMD64_NX:
3050	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3051	enmShadowMode = PGMMODE_AMD64;
3052	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3053	break;
3054
3055	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3056	}
3057	break;
3058
3059
3060	default:
3061	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3062	*penmSwitcher = VMMSWITCHER_INVALID;
3063	return PGMMODE_INVALID;
3064	}
3065	/* Override the shadow mode is nested paging is active. */
3066	if (HWACCMIsNestedPagingActive(pVM))
3067	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3068
3069	*penmSwitcher = enmSwitcher;
3070	return enmShadowMode;
3071	}
3072
3073
3074	/**
3075	* Performs the actual mode change.
3076	* This is called by PGMChangeMode and pgmR3InitPaging().
3077	*
3078	* @returns VBox status code. May suspend or power off the VM on error, but this
3079	* will trigger using FFs and not status codes.
3080	*
3081	* @param pVM VM handle.
3082	* @param pVCpu The VMCPU to operate on.
3083	* @param enmGuestMode The new guest mode. This is assumed to be different from
3084	* the current mode.
3085	*/
3086	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3087	{
3088	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3089	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3090
3091	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3092	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3093
3094	/*
3095	* Calc the shadow mode and switcher.
3096	*/
3097	VMMSWITCHER enmSwitcher;
3098	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3099
3100	#ifdef VBOX_WITH_RAW_MODE
3101	if (enmSwitcher != VMMSWITCHER_INVALID)
3102	{
3103	/*
3104	* Select new switcher.
3105	*/
3106	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3107	if (RT_FAILURE(rc))
3108	{
3109	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3110	return rc;
3111	}
3112	}
3113	#endif
3114
3115	/*
3116	* Exit old mode(s).
3117	*/
3118	#if HC_ARCH_BITS == 32
3119	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3120	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3121	&& enmShadowMode == PGMMODE_NESTED);
3122	#else
3123	const bool fForceShwEnterExit = false;
3124	#endif
3125	/* shadow */
3126	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3127	\|\| fForceShwEnterExit)
3128	{
3129	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3130	if (PGM_SHW_PFN(Exit, pVCpu))
3131	{
3132	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3133	if (RT_FAILURE(rc))
3134	{
3135	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3136	return rc;
3137	}
3138	}
3139
3140	}
3141	else
3142	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3143
3144	/* guest */
3145	if (PGM_GST_PFN(Exit, pVCpu))
3146	{
3147	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3148	if (RT_FAILURE(rc))
3149	{
3150	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3151	return rc;
3152	}
3153	}
3154
3155	/*
3156	* Load new paging mode data.
3157	*/
3158	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3159
3160	/*
3161	* Enter new shadow mode (if changed).
3162	*/
3163	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3164	\|\| fForceShwEnterExit)
3165	{
3166	int rc;
3167	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3168	switch (enmShadowMode)
3169	{
3170	case PGMMODE_32_BIT:
3171	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3172	break;
3173	case PGMMODE_PAE:
3174	case PGMMODE_PAE_NX:
3175	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3176	break;
3177	case PGMMODE_AMD64:
3178	case PGMMODE_AMD64_NX:
3179	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3180	break;
3181	case PGMMODE_NESTED:
3182	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3183	break;
3184	case PGMMODE_EPT:
3185	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3186	break;
3187	case PGMMODE_REAL:
3188	case PGMMODE_PROTECTED:
3189	default:
3190	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3191	return VERR_INTERNAL_ERROR;
3192	}
3193	if (RT_FAILURE(rc))
3194	{
3195	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3196	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3197	return rc;
3198	}
3199	}
3200
3201	/*
3202	* Always flag the necessary updates
3203	*/
3204	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3205
3206	/*
3207	* Enter the new guest and shadow+guest modes.
3208	*/
3209	int rc = -1;
3210	int rc2 = -1;
3211	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3212	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3213	switch (enmGuestMode)
3214	{
3215	case PGMMODE_REAL:
3216	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3217	switch (pVCpu->pgm.s.enmShadowMode)
3218	{
3219	case PGMMODE_32_BIT:
3220	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3221	break;
3222	case PGMMODE_PAE:
3223	case PGMMODE_PAE_NX:
3224	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3225	break;
3226	case PGMMODE_NESTED:
3227	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3228	break;
3229	case PGMMODE_EPT:
3230	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3231	break;
3232	case PGMMODE_AMD64:
3233	case PGMMODE_AMD64_NX:
3234	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3235	default: AssertFailed(); break;
3236	}
3237	break;
3238
3239	case PGMMODE_PROTECTED:
3240	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3241	switch (pVCpu->pgm.s.enmShadowMode)
3242	{
3243	case PGMMODE_32_BIT:
3244	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3245	break;
3246	case PGMMODE_PAE:
3247	case PGMMODE_PAE_NX:
3248	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3249	break;
3250	case PGMMODE_NESTED:
3251	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3252	break;
3253	case PGMMODE_EPT:
3254	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3255	break;
3256	case PGMMODE_AMD64:
3257	case PGMMODE_AMD64_NX:
3258	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3259	default: AssertFailed(); break;
3260	}
3261	break;
3262
3263	case PGMMODE_32_BIT:
3264	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3265	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3266	switch (pVCpu->pgm.s.enmShadowMode)
3267	{
3268	case PGMMODE_32_BIT:
3269	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3270	break;
3271	case PGMMODE_PAE:
3272	case PGMMODE_PAE_NX:
3273	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3274	break;
3275	case PGMMODE_NESTED:
3276	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3277	break;
3278	case PGMMODE_EPT:
3279	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3280	break;
3281	case PGMMODE_AMD64:
3282	case PGMMODE_AMD64_NX:
3283	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3284	default: AssertFailed(); break;
3285	}
3286	break;
3287
3288	case PGMMODE_PAE_NX:
3289	case PGMMODE_PAE:
3290	{
3291	uint32_t u32Dummy, u32Features;
3292
3293	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3294	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3295	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3296	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3297
3298	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3299	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3300	switch (pVCpu->pgm.s.enmShadowMode)
3301	{
3302	case PGMMODE_PAE:
3303	case PGMMODE_PAE_NX:
3304	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3305	break;
3306	case PGMMODE_NESTED:
3307	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3308	break;
3309	case PGMMODE_EPT:
3310	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3311	break;
3312	case PGMMODE_32_BIT:
3313	case PGMMODE_AMD64:
3314	case PGMMODE_AMD64_NX:
3315	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3316	default: AssertFailed(); break;
3317	}
3318	break;
3319	}
3320
3321	#ifdef VBOX_WITH_64_BITS_GUESTS
3322	case PGMMODE_AMD64_NX:
3323	case PGMMODE_AMD64:
3324	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3325	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3326	switch (pVCpu->pgm.s.enmShadowMode)
3327	{
3328	case PGMMODE_AMD64:
3329	case PGMMODE_AMD64_NX:
3330	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3331	break;
3332	case PGMMODE_NESTED:
3333	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3334	break;
3335	case PGMMODE_EPT:
3336	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3337	break;
3338	case PGMMODE_32_BIT:
3339	case PGMMODE_PAE:
3340	case PGMMODE_PAE_NX:
3341	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3342	default: AssertFailed(); break;
3343	}
3344	break;
3345	#endif
3346
3347	default:
3348	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3349	rc = VERR_NOT_IMPLEMENTED;
3350	break;
3351	}
3352
3353	/* status codes. */
3354	AssertRC(rc);
3355	AssertRC(rc2);
3356	if (RT_SUCCESS(rc))
3357	{
3358	rc = rc2;
3359	if (RT_SUCCESS(rc)) /* no informational status codes. */
3360	rc = VINF_SUCCESS;
3361	}
3362
3363	/* Notify HWACCM as well. */
3364	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3365	return rc;
3366	}
3367
3368
3369	/**
3370	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3371	*
3372	* @returns VBox status code, fully asserted.
3373	* @param pVM The VM handle.
3374	* @param pVCpu The VMCPU to operate on.
3375	*/
3376	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3377	{
3378	/* Unmap the old CR3 value before flushing everything. */
3379	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3380	AssertRC(rc);
3381
3382	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3383	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3384	AssertRC(rc);
3385	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3386	return rc;
3387	}
3388
3389
3390	/**
3391	* Called by pgmPoolFlushAllInt after flushing the pool.
3392	*
3393	* @returns VBox status code, fully asserted.
3394	* @param pVM The VM handle.
3395	* @param pVCpu The VMCPU to operate on.
3396	*/
3397	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3398	{
3399	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3400	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3401	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3402	AssertRCReturn(rc, rc);
3403	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3404
3405	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3406	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3407	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3408	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3409	return rc;
3410	}
3411
3412
3413	/**
3414	* Dumps a PAE shadow page table.
3415	*
3416	* @returns VBox status code (VINF_SUCCESS).
3417	* @param pVM The VM handle.
3418	* @param pPT Pointer to the page table.
3419	* @param u64Address The virtual address of the page table starts.
3420	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3421	* @param cMaxDepth The maxium depth.
3422	* @param pHlp Pointer to the output functions.
3423	*/
3424	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3425	{
3426	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3427	{
3428	X86PTEPAE Pte = pPT->a[i];
3429	if (Pte.n.u1Present)
3430	{
3431	pHlp->pfnPrintf(pHlp,
3432	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3433	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3434	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3435	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3436	Pte.n.u1Write ? 'W' : 'R',
3437	Pte.n.u1User ? 'U' : 'S',
3438	Pte.n.u1Accessed ? 'A' : '-',
3439	Pte.n.u1Dirty ? 'D' : '-',
3440	Pte.n.u1Global ? 'G' : '-',
3441	Pte.n.u1WriteThru ? "WT" : "--",
3442	Pte.n.u1CacheDisable? "CD" : "--",
3443	Pte.n.u1PAT ? "AT" : "--",
3444	Pte.n.u1NoExecute ? "NX" : "--",
3445	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3446	Pte.u & RT_BIT(10) ? '1' : '0',
3447	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3448	Pte.u & X86_PTE_PAE_PG_MASK);
3449	}
3450	}
3451	return VINF_SUCCESS;
3452	}
3453
3454
3455	/**
3456	* Dumps a PAE shadow page directory table.
3457	*
3458	* @returns VBox status code (VINF_SUCCESS).
3459	* @param pVM The VM handle.
3460	* @param HCPhys The physical address of the page directory table.
3461	* @param u64Address The virtual address of the page table starts.
3462	* @param cr4 The CR4, PSE is currently used.
3463	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3464	* @param cMaxDepth The maxium depth.
3465	* @param pHlp Pointer to the output functions.
3466	*/
3467	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3468	{
3469	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3470	if (!pPD)
3471	{
3472	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3473	fLongMode ? 16 : 8, u64Address, HCPhys);
3474	return VERR_INVALID_PARAMETER;
3475	}
3476	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3477
3478	int rc = VINF_SUCCESS;
3479	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3480	{
3481	X86PDEPAE Pde = pPD->a[i];
3482	if (Pde.n.u1Present)
3483	{
3484	if (fBigPagesSupported && Pde.b.u1Size)
3485	pHlp->pfnPrintf(pHlp,
3486	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3487	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3488	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3489	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3490	Pde.b.u1Write ? 'W' : 'R',
3491	Pde.b.u1User ? 'U' : 'S',
3492	Pde.b.u1Accessed ? 'A' : '-',
3493	Pde.b.u1Dirty ? 'D' : '-',
3494	Pde.b.u1Global ? 'G' : '-',
3495	Pde.b.u1WriteThru ? "WT" : "--",
3496	Pde.b.u1CacheDisable? "CD" : "--",
3497	Pde.b.u1PAT ? "AT" : "--",
3498	Pde.b.u1NoExecute ? "NX" : "--",
3499	Pde.u & RT_BIT_64(9) ? '1' : '0',
3500	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3501	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3502	Pde.u & X86_PDE_PAE_PG_MASK);
3503	else
3504	{
3505	pHlp->pfnPrintf(pHlp,
3506	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3507	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3508	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3509	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3510	Pde.n.u1Write ? 'W' : 'R',
3511	Pde.n.u1User ? 'U' : 'S',
3512	Pde.n.u1Accessed ? 'A' : '-',
3513	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3514	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3515	Pde.n.u1WriteThru ? "WT" : "--",
3516	Pde.n.u1CacheDisable? "CD" : "--",
3517	Pde.n.u1NoExecute ? "NX" : "--",
3518	Pde.u & RT_BIT_64(9) ? '1' : '0',
3519	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3520	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3521	Pde.u & X86_PDE_PAE_PG_MASK);
3522	if (cMaxDepth >= 1)
3523	{
3524	/** @todo what about using the page pool for mapping PTs? */
3525	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3526	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3527	PX86PTPAE pPT = NULL;
3528	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3529	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3530	else
3531	{
3532	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3533	{
3534	uint64_t off = u64AddressPT - pMap->GCPtr;
3535	if (off < pMap->cb)
3536	{
3537	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3538	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3539	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3540	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3541	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3542	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3543	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3544	}
3545	}
3546	}
3547	int rc2 = VERR_INVALID_PARAMETER;
3548	if (pPT)
3549	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3550	else
3551	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3552	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3553	if (rc2 < rc && RT_SUCCESS(rc))
3554	rc = rc2;
3555	}
3556	}
3557	}
3558	}
3559	return rc;
3560	}
3561
3562
3563	/**
3564	* Dumps a PAE shadow page directory pointer table.
3565	*
3566	* @returns VBox status code (VINF_SUCCESS).
3567	* @param pVM The VM handle.
3568	* @param HCPhys The physical address of the page directory pointer table.
3569	* @param u64Address The virtual address of the page table starts.
3570	* @param cr4 The CR4, PSE is currently used.
3571	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3572	* @param cMaxDepth The maxium depth.
3573	* @param pHlp Pointer to the output functions.
3574	*/
3575	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3576	{
3577	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3578	if (!pPDPT)
3579	{
3580	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3581	fLongMode ? 16 : 8, u64Address, HCPhys);
3582	return VERR_INVALID_PARAMETER;
3583	}
3584
3585	int rc = VINF_SUCCESS;
3586	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3587	for (unsigned i = 0; i < c; i++)
3588	{
3589	X86PDPE Pdpe = pPDPT->a[i];
3590	if (Pdpe.n.u1Present)
3591	{
3592	if (fLongMode)
3593	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3594	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3595	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3596	Pdpe.lm.u1Write ? 'W' : 'R',
3597	Pdpe.lm.u1User ? 'U' : 'S',
3598	Pdpe.lm.u1Accessed ? 'A' : '-',
3599	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3600	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3601	Pdpe.lm.u1WriteThru ? "WT" : "--",
3602	Pdpe.lm.u1CacheDisable? "CD" : "--",
3603	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3604	Pdpe.lm.u1NoExecute ? "NX" : "--",
3605	Pdpe.u & RT_BIT(9) ? '1' : '0',
3606	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3607	Pdpe.u & RT_BIT(11) ? '1' : '0',
3608	Pdpe.u & X86_PDPE_PG_MASK);
3609	else
3610	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3611	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3612	i << X86_PDPT_SHIFT,
3613	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3614	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3615	Pdpe.n.u1WriteThru ? "WT" : "--",
3616	Pdpe.n.u1CacheDisable? "CD" : "--",
3617	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3618	Pdpe.u & RT_BIT(9) ? '1' : '0',
3619	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3620	Pdpe.u & RT_BIT(11) ? '1' : '0',
3621	Pdpe.u & X86_PDPE_PG_MASK);
3622	if (cMaxDepth >= 1)
3623	{
3624	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3625	cr4, fLongMode, cMaxDepth - 1, pHlp);
3626	if (rc2 < rc && RT_SUCCESS(rc))
3627	rc = rc2;
3628	}
3629	}
3630	}
3631	return rc;
3632	}
3633
3634
3635	/**
3636	* Dumps a 32-bit shadow page table.
3637	*
3638	* @returns VBox status code (VINF_SUCCESS).
3639	* @param pVM The VM handle.
3640	* @param HCPhys The physical address of the table.
3641	* @param cr4 The CR4, PSE is currently used.
3642	* @param cMaxDepth The maxium depth.
3643	* @param pHlp Pointer to the output functions.
3644	*/
3645	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3646	{
3647	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3648	if (!pPML4)
3649	{
3650	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3651	return VERR_INVALID_PARAMETER;
3652	}
3653
3654	int rc = VINF_SUCCESS;
3655	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3656	{
3657	X86PML4E Pml4e = pPML4->a[i];
3658	if (Pml4e.n.u1Present)
3659	{
3660	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3661	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3662	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3663	u64Address,
3664	Pml4e.n.u1Write ? 'W' : 'R',
3665	Pml4e.n.u1User ? 'U' : 'S',
3666	Pml4e.n.u1Accessed ? 'A' : '-',
3667	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3668	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3669	Pml4e.n.u1WriteThru ? "WT" : "--",
3670	Pml4e.n.u1CacheDisable? "CD" : "--",
3671	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3672	Pml4e.n.u1NoExecute ? "NX" : "--",
3673	Pml4e.u & RT_BIT(9) ? '1' : '0',
3674	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3675	Pml4e.u & RT_BIT(11) ? '1' : '0',
3676	Pml4e.u & X86_PML4E_PG_MASK);
3677
3678	if (cMaxDepth >= 1)
3679	{
3680	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3681	if (rc2 < rc && RT_SUCCESS(rc))
3682	rc = rc2;
3683	}
3684	}
3685	}
3686	return rc;
3687	}
3688
3689
3690	/**
3691	* Dumps a 32-bit shadow page table.
3692	*
3693	* @returns VBox status code (VINF_SUCCESS).
3694	* @param pVM The VM handle.
3695	* @param pPT Pointer to the page table.
3696	* @param u32Address The virtual address this table starts at.
3697	* @param pHlp Pointer to the output functions.
3698	*/
3699	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3700	{
3701	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3702	{
3703	X86PTE Pte = pPT->a[i];
3704	if (Pte.n.u1Present)
3705	{
3706	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3707	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3708	u32Address + (i << X86_PT_SHIFT),
3709	Pte.n.u1Write ? 'W' : 'R',
3710	Pte.n.u1User ? 'U' : 'S',
3711	Pte.n.u1Accessed ? 'A' : '-',
3712	Pte.n.u1Dirty ? 'D' : '-',
3713	Pte.n.u1Global ? 'G' : '-',
3714	Pte.n.u1WriteThru ? "WT" : "--",
3715	Pte.n.u1CacheDisable? "CD" : "--",
3716	Pte.n.u1PAT ? "AT" : "--",
3717	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3718	Pte.u & RT_BIT(10) ? '1' : '0',
3719	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3720	Pte.u & X86_PDE_PG_MASK);
3721	}
3722	}
3723	return VINF_SUCCESS;
3724	}
3725
3726
3727	/**
3728	* Dumps a 32-bit shadow page directory and page tables.
3729	*
3730	* @returns VBox status code (VINF_SUCCESS).
3731	* @param pVM The VM handle.
3732	* @param cr3 The root of the hierarchy.
3733	* @param cr4 The CR4, PSE is currently used.
3734	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3735	* @param pHlp Pointer to the output functions.
3736	*/
3737	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3738	{
3739	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3740	if (!pPD)
3741	{
3742	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3743	return VERR_INVALID_PARAMETER;
3744	}
3745
3746	int rc = VINF_SUCCESS;
3747	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3748	{
3749	X86PDE Pde = pPD->a[i];
3750	if (Pde.n.u1Present)
3751	{
3752	const uint32_t u32Address = i << X86_PD_SHIFT;
3753	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3754	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3755	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3756	u32Address,
3757	Pde.b.u1Write ? 'W' : 'R',
3758	Pde.b.u1User ? 'U' : 'S',
3759	Pde.b.u1Accessed ? 'A' : '-',
3760	Pde.b.u1Dirty ? 'D' : '-',
3761	Pde.b.u1Global ? 'G' : '-',
3762	Pde.b.u1WriteThru ? "WT" : "--",
3763	Pde.b.u1CacheDisable? "CD" : "--",
3764	Pde.b.u1PAT ? "AT" : "--",
3765	Pde.u & RT_BIT_64(9) ? '1' : '0',
3766	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3767	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3768	Pde.u & X86_PDE4M_PG_MASK);
3769	else
3770	{
3771	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3772	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3773	u32Address,
3774	Pde.n.u1Write ? 'W' : 'R',
3775	Pde.n.u1User ? 'U' : 'S',
3776	Pde.n.u1Accessed ? 'A' : '-',
3777	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3778	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3779	Pde.n.u1WriteThru ? "WT" : "--",
3780	Pde.n.u1CacheDisable? "CD" : "--",
3781	Pde.u & RT_BIT_64(9) ? '1' : '0',
3782	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3783	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3784	Pde.u & X86_PDE_PG_MASK);
3785	if (cMaxDepth >= 1)
3786	{
3787	/** @todo what about using the page pool for mapping PTs? */
3788	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3789	PX86PT pPT = NULL;
3790	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3791	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3792	else
3793	{
3794	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3795	if (u32Address - pMap->GCPtr < pMap->cb)
3796	{
3797	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3798	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3799	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3800	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3801	pPT = pMap->aPTs[iPDE].pPTR3;
3802	}
3803	}
3804	int rc2 = VERR_INVALID_PARAMETER;
3805	if (pPT)
3806	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3807	else
3808	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3809	if (rc2 < rc && RT_SUCCESS(rc))
3810	rc = rc2;
3811	}
3812	}
3813	}
3814	}
3815
3816	return rc;
3817	}
3818
3819
3820	/**
3821	* Dumps a 32-bit shadow page table.
3822	*
3823	* @returns VBox status code (VINF_SUCCESS).
3824	* @param pVM The VM handle.
3825	* @param pPT Pointer to the page table.
3826	* @param u32Address The virtual address this table starts at.
3827	* @param PhysSearch Address to search for.
3828	*/
3829	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3830	{
3831	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3832	{
3833	X86PTE Pte = pPT->a[i];
3834	if (Pte.n.u1Present)
3835	{
3836	Log(( /P R S A D G WT CD AT NX 4M a m d /
3837	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3838	u32Address + (i << X86_PT_SHIFT),
3839	Pte.n.u1Write ? 'W' : 'R',
3840	Pte.n.u1User ? 'U' : 'S',
3841	Pte.n.u1Accessed ? 'A' : '-',
3842	Pte.n.u1Dirty ? 'D' : '-',
3843	Pte.n.u1Global ? 'G' : '-',
3844	Pte.n.u1WriteThru ? "WT" : "--",
3845	Pte.n.u1CacheDisable? "CD" : "--",
3846	Pte.n.u1PAT ? "AT" : "--",
3847	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3848	Pte.u & RT_BIT(10) ? '1' : '0',
3849	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3850	Pte.u & X86_PDE_PG_MASK));
3851
3852	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3853	{
3854	uint64_t fPageShw = 0;
3855	RTHCPHYS pPhysHC = 0;
3856
3857	/** @todo SMP support!! */
3858	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3859	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3860	}
3861	}
3862	}
3863	return VINF_SUCCESS;
3864	}
3865
3866
3867	/**
3868	* Dumps a 32-bit guest page directory and page tables.
3869	*
3870	* @returns VBox status code (VINF_SUCCESS).
3871	* @param pVM The VM handle.
3872	* @param cr3 The root of the hierarchy.
3873	* @param cr4 The CR4, PSE is currently used.
3874	* @param PhysSearch Address to search for.
3875	*/
3876	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3877	{
3878	bool fLongMode = false;
3879	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3880	PX86PD pPD = 0;
3881	PGMPAGEMAPLOCK LockCr3;
3882
3883	int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, cr3 & X86_CR3_PAGE_MASK, (const void **)&pPD, &LockCr3);
3884	if ( RT_FAILURE(rc)
3885	\|\| !pPD)
3886	{
3887	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3888	return VERR_INVALID_PARAMETER;
3889	}
3890
3891	Log(("cr3=%08x cr4=%08x%s\n"
3892	"%-*s P - Present\n"
3893	"%-*s \| R/W - Read (0) / Write (1)\n"
3894	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3895	"%-*s \| \| \| A - Accessed\n"
3896	"%-*s \| \| \| \| D - Dirty\n"
3897	"%-*s \| \| \| \| \| G - Global\n"
3898	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3899	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3900	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3901	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3902	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3903	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3904	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3905	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3906	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3907	- W U - - - -- -- -- -- -- 010 */
3908	, cr3, cr4, fLongMode ? " Long Mode" : "",
3909	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3910	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3911
3912	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3913	{
3914	X86PDE Pde = pPD->a[i];
3915	if (Pde.n.u1Present)
3916	{
3917	const uint32_t u32Address = i << X86_PD_SHIFT;
3918
3919	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3920	Log(( /P R S A D G WT CD AT NX 4M a m d /
3921	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3922	u32Address,
3923	Pde.b.u1Write ? 'W' : 'R',
3924	Pde.b.u1User ? 'U' : 'S',
3925	Pde.b.u1Accessed ? 'A' : '-',
3926	Pde.b.u1Dirty ? 'D' : '-',
3927	Pde.b.u1Global ? 'G' : '-',
3928	Pde.b.u1WriteThru ? "WT" : "--",
3929	Pde.b.u1CacheDisable? "CD" : "--",
3930	Pde.b.u1PAT ? "AT" : "--",
3931	Pde.u & RT_BIT(9) ? '1' : '0',
3932	Pde.u & RT_BIT(10) ? '1' : '0',
3933	Pde.u & RT_BIT(11) ? '1' : '0',
3934	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3935	/** @todo PhysSearch */
3936	else
3937	{
3938	Log(( /P R S A D G WT CD AT NX 4M a m d /
3939	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3940	u32Address,
3941	Pde.n.u1Write ? 'W' : 'R',
3942	Pde.n.u1User ? 'U' : 'S',
3943	Pde.n.u1Accessed ? 'A' : '-',
3944	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3945	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3946	Pde.n.u1WriteThru ? "WT" : "--",
3947	Pde.n.u1CacheDisable? "CD" : "--",
3948	Pde.u & RT_BIT(9) ? '1' : '0',
3949	Pde.u & RT_BIT(10) ? '1' : '0',
3950	Pde.u & RT_BIT(11) ? '1' : '0',
3951	Pde.u & X86_PDE_PG_MASK));
3952	////if (cMaxDepth >= 1)
3953	{
3954	/** @todo what about using the page pool for mapping PTs? */
3955	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3956	PX86PT pPT = NULL;
3957	PGMPAGEMAPLOCK LockPT;
3958
3959	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, (const void **)&pPT, &LockPT);
3960
3961	int rc2 = VERR_INVALID_PARAMETER;
3962	if (pPT)
3963	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3964	else
3965	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3966
3967	if (rc == VINF_SUCCESS)
3968	PGMPhysReleasePageMappingLock(pVM, &LockPT);
3969
3970	if (rc2 < rc && RT_SUCCESS(rc))
3971	rc = rc2;
3972	}
3973	}
3974	}
3975	}
3976	PGMPhysReleasePageMappingLock(pVM, &LockCr3);
3977	return rc;
3978	}
3979
3980
3981	/**
3982	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3983	*
3984	* @returns VBox status code (VINF_SUCCESS).
3985	* @param pVM The VM handle.
3986	* @param cr3 The root of the hierarchy.
3987	* @param cr4 The cr4, only PAE and PSE is currently used.
3988	* @param fLongMode Set if long mode, false if not long mode.
3989	* @param cMaxDepth Number of levels to dump.
3990	* @param pHlp Pointer to the output functions.
3991	*/
3992	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3993	{
3994	if (!pHlp)
3995	pHlp = DBGFR3InfoLogHlp();
3996	if (!cMaxDepth)
3997	return VINF_SUCCESS;
3998	const unsigned cch = fLongMode ? 16 : 8;
3999	pHlp->pfnPrintf(pHlp,
4000	"cr3=%08x cr4=%08x%s\n"
4001	"%-*s P - Present\n"
4002	"%-*s \| R/W - Read (0) / Write (1)\n"
4003	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4004	"%-*s \| \| \| A - Accessed\n"
4005	"%-*s \| \| \| \| D - Dirty\n"
4006	"%-*s \| \| \| \| \| G - Global\n"
4007	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4008	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4009	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4010	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4011	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4012	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4013	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4014	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4015	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4016	- W U - - - -- -- -- -- -- 010 */
4017	, cr3, cr4, fLongMode ? " Long Mode" : "",
4018	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4019	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4020	if (cr4 & X86_CR4_PAE)
4021	{
4022	if (fLongMode)
4023	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4024	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4025	}
4026	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4027	}
4028
4029	#ifdef VBOX_WITH_DEBUGGER
4030
4031	/**
4032	* The '.pgmram' command.
4033	*
4034	* @returns VBox status.
4035	* @param pCmd Pointer to the command descriptor (as registered).
4036	* @param pCmdHlp Pointer to command helper functions.
4037	* @param pVM Pointer to the current VM (if any).
4038	* @param paArgs Pointer to (readonly) array of arguments.
4039	* @param cArgs Number of arguments in the array.
4040	*/
4041	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4042	{
4043	/*
4044	* Validate input.
4045	*/
4046	if (!pVM)
4047	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4048	if (!pVM->pgm.s.pRamRangesRC)
4049	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4050
4051	/*
4052	* Dump the ranges.
4053	*/
4054	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4055	PPGMRAMRANGE pRam;
4056	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4057	{
4058	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4059	"%RGp - %RGp %p\n",
4060	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4061	if (RT_FAILURE(rc))
4062	return rc;
4063	}
4064
4065	return VINF_SUCCESS;
4066	}
4067
4068
4069	/**
4070	* The '.pgmerror' and '.pgmerroroff' commands.
4071	*
4072	* @returns VBox status.
4073	* @param pCmd Pointer to the command descriptor (as registered).
4074	* @param pCmdHlp Pointer to command helper functions.
4075	* @param pVM Pointer to the current VM (if any).
4076	* @param paArgs Pointer to (readonly) array of arguments.
4077	* @param cArgs Number of arguments in the array.
4078	*/
4079	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4080	{
4081	/*
4082	* Validate input.
4083	*/
4084	if (!pVM)
4085	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4086	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4087	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4088
4089	if (!cArgs)
4090	{
4091	/*
4092	* Print the list of error injection locations with status.
4093	*/
4094	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4095	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4096	}
4097	else
4098	{
4099
4100	/*
4101	* String switch on where to inject the error.
4102	*/
4103	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4104	const char *pszWhere = paArgs[0].u.pszString;
4105	if (!strcmp(pszWhere, "handy"))
4106	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4107	else
4108	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4109	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4110	}
4111	return VINF_SUCCESS;
4112	}
4113
4114
4115	/**
4116	* The '.pgmsync' command.
4117	*
4118	* @returns VBox status.
4119	* @param pCmd Pointer to the command descriptor (as registered).
4120	* @param pCmdHlp Pointer to command helper functions.
4121	* @param pVM Pointer to the current VM (if any).
4122	* @param paArgs Pointer to (readonly) array of arguments.
4123	* @param cArgs Number of arguments in the array.
4124	*/
4125	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4126	{
4127	/** @todo SMP support */
4128	PVMCPU pVCpu = &pVM->aCpus[0];
4129
4130	/*
4131	* Validate input.
4132	*/
4133	if (!pVM)
4134	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4135
4136	/*
4137	* Force page directory sync.
4138	*/
4139	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4140
4141	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4142	if (RT_FAILURE(rc))
4143	return rc;
4144
4145	return VINF_SUCCESS;
4146	}
4147
4148
4149	#ifdef VBOX_STRICT
4150	/**
4151	* The '.pgmassertcr3' command.
4152	*
4153	* @returns VBox status.
4154	* @param pCmd Pointer to the command descriptor (as registered).
4155	* @param pCmdHlp Pointer to command helper functions.
4156	* @param pVM Pointer to the current VM (if any).
4157	* @param paArgs Pointer to (readonly) array of arguments.
4158	* @param cArgs Number of arguments in the array.
4159	*/
4160	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4161	{
4162	/** @todo SMP support!! */
4163	PVMCPU pVCpu = &pVM->aCpus[0];
4164
4165	/*
4166	* Validate input.
4167	*/
4168	if (!pVM)
4169	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4170
4171	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4172	if (RT_FAILURE(rc))
4173	return rc;
4174
4175	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4176
4177	return VINF_SUCCESS;
4178	}
4179	#endif /* VBOX_STRICT */
4180
4181
4182	/**
4183	* The '.pgmsyncalways' command.
4184	*
4185	* @returns VBox status.
4186	* @param pCmd Pointer to the command descriptor (as registered).
4187	* @param pCmdHlp Pointer to command helper functions.
4188	* @param pVM Pointer to the current VM (if any).
4189	* @param paArgs Pointer to (readonly) array of arguments.
4190	* @param cArgs Number of arguments in the array.
4191	*/
4192	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4193	{
4194	/** @todo SMP support!! */
4195	PVMCPU pVCpu = &pVM->aCpus[0];
4196
4197	/*
4198	* Validate input.
4199	*/
4200	if (!pVM)
4201	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4202
4203	/*
4204	* Force page directory sync.
4205	*/
4206	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4207	{
4208	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4209	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4210	}
4211	else
4212	{
4213	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4214	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4215	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4216	}
4217	}
4218
4219
4220	/**
4221	* The '.pgmsyncalways' command.
4222	*
4223	* @returns VBox status.
4224	* @param pCmd Pointer to the command descriptor (as registered).
4225	* @param pCmdHlp Pointer to command helper functions.
4226	* @param pVM Pointer to the current VM (if any).
4227	* @param paArgs Pointer to (readonly) array of arguments.
4228	* @param cArgs Number of arguments in the array.
4229	*/
4230	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4231	{
4232	/*
4233	* Validate input.
4234	*/
4235	if (!pVM)
4236	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4237	if ( cArgs < 1
4238	\|\| cArgs > 2
4239	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4240	\|\| ( cArgs > 1
4241	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4242	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4243	if ( cArgs >= 2
4244	&& strcmp(paArgs[1].u.pszString, "nozero"))
4245	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4246	bool fIncZeroPgs = cArgs < 2;
4247
4248	/*
4249	* Open the output file and get the ram parameters.
4250	*/
4251	RTFILE hFile;
4252	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
4253	if (RT_FAILURE(rc))
4254	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4255
4256	uint32_t cbRamHole = 0;
4257	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4258	uint64_t cbRam = 0;
4259	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4260	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4261
4262	/*
4263	* Dump the physical memory, page by page.
4264	*/
4265	RTGCPHYS GCPhys = 0;
4266	char abZeroPg[PAGE_SIZE];
4267	RT_ZERO(abZeroPg);
4268
4269	pgmLock(pVM);
4270	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4271	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4272	pRam = pRam->pNextR3)
4273	{
4274	/* fill the gap */
4275	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4276	{
4277	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4278	{
4279	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4280	GCPhys += PAGE_SIZE;
4281	}
4282	}
4283
4284	PCPGMPAGE pPage = &pRam->aPages[0];
4285	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4286	{
4287	if ( PGM_PAGE_IS_ZERO(pPage)
4288	\|\| PGM_PAGE_IS_BALLOONED(pPage))
4289	{
4290	if (fIncZeroPgs)
4291	{
4292	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4293	if (RT_FAILURE(rc))
4294	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4295	}
4296	}
4297	else
4298	{
4299	switch (PGM_PAGE_GET_TYPE(pPage))
4300	{
4301	case PGMPAGETYPE_RAM:
4302	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4303	case PGMPAGETYPE_ROM:
4304	case PGMPAGETYPE_MMIO2:
4305	{
4306	void const *pvPage;
4307	PGMPAGEMAPLOCK Lock;
4308	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4309	if (RT_SUCCESS(rc))
4310	{
4311	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4312	PGMPhysReleasePageMappingLock(pVM, &Lock);
4313	if (RT_FAILURE(rc))
4314	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4315	}
4316	else
4317	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4318	break;
4319	}
4320
4321	default:
4322	AssertFailed();
4323	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4324	case PGMPAGETYPE_MMIO:
4325	if (fIncZeroPgs)
4326	{
4327	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4328	if (RT_FAILURE(rc))
4329	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4330	}
4331	break;
4332	}
4333	}
4334
4335
4336	/* advance */
4337	GCPhys += PAGE_SIZE;
4338	pPage++;
4339	}
4340	}
4341	pgmUnlock(pVM);
4342
4343	RTFileClose(hFile);
4344	if (RT_SUCCESS(rc))
4345	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4346	return VINF_SUCCESS;
4347	}
4348
4349	#endif /* VBOX_WITH_DEBUGGER */
4350
4351	/**
4352	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4353	*/
4354	typedef struct PGMCHECKINTARGS
4355	{
4356	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4357	PPGMPHYSHANDLER pPrevPhys;
4358	PPGMVIRTHANDLER pPrevVirt;
4359	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4360	PVM pVM;
4361	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4362
4363	/**
4364	* Validate a node in the physical handler tree.
4365	*
4366	* @returns 0 on if ok, other wise 1.
4367	* @param pNode The handler node.
4368	* @param pvUser pVM.
4369	*/
4370	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4371	{
4372	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4373	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4374	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4375	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4376	AssertReleaseMsg( !pArgs->pPrevPhys
4377	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4378	("pPrevPhys=%p %RGp-%RGp %s\n"
4379	" pCur=%p %RGp-%RGp %s\n",
4380	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4381	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4382	pArgs->pPrevPhys = pCur;
4383	return 0;
4384	}
4385
4386
4387	/**
4388	* Validate a node in the virtual handler tree.
4389	*
4390	* @returns 0 on if ok, other wise 1.
4391	* @param pNode The handler node.
4392	* @param pvUser pVM.
4393	*/
4394	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4395	{
4396	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4397	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4398	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4399	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4400	AssertReleaseMsg( !pArgs->pPrevVirt
4401	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4402	("pPrevVirt=%p %RGv-%RGv %s\n"
4403	" pCur=%p %RGv-%RGv %s\n",
4404	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4405	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4406	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4407	{
4408	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4409	("pCur=%p %RGv-%RGv %s\n"
4410	"iPage=%d offVirtHandle=%#x expected %#x\n",
4411	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4412	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4413	}
4414	pArgs->pPrevVirt = pCur;
4415	return 0;
4416	}
4417
4418
4419	/**
4420	* Validate a node in the virtual handler tree.
4421	*
4422	* @returns 0 on if ok, other wise 1.
4423	* @param pNode The handler node.
4424	* @param pvUser pVM.
4425	*/
4426	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4427	{
4428	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4429	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4430	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4431	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4432	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4433	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4434	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4435	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4436	" pCur=%p %RGp-%RGp\n",
4437	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4438	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4439	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4440	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4441	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4442	" pCur=%p %RGp-%RGp\n",
4443	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4444	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4445	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4446	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4447	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4448	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4449	{
4450	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4451	for (;;)
4452	{
4453	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4454	AssertReleaseMsg(pCur2 != pCur,
4455	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4456	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4457	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4458	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4459	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4460	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4461	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4462	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4463	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4464	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4465	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4466	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4467	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4468	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4469	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4470	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4471	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4472	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4473	break;
4474	}
4475	}
4476
4477	pArgs->pPrevPhys2Virt = pCur;
4478	return 0;
4479	}
4480
4481
4482	/**
4483	* Perform an integrity check on the PGM component.
4484	*
4485	* @returns VINF_SUCCESS if everything is fine.
4486	* @returns VBox error status after asserting on integrity breach.
4487	* @param pVM The VM handle.
4488	*/
4489	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4490	{
4491	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4492
4493	/*
4494	* Check the trees.
4495	*/
4496	int cErrors = 0;
4497	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4498	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4499	PGMCHECKINTARGS Args = s_LeftToRight;
4500	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4501	Args = s_RightToLeft;
4502	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4503	Args = s_LeftToRight;
4504	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4505	Args = s_RightToLeft;
4506	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4507	Args = s_LeftToRight;
4508	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4509	Args = s_RightToLeft;
4510	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4511	Args = s_LeftToRight;
4512	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4513	Args = s_RightToLeft;
4514	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4515
4516	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4517	}
4518

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 30863

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