PGM.cpp@ 26234

Last change on this file since 26234 was 26150, checked in by vboxsync, 15 years ago
PGM: Split out the inlined code from PGMInternal.h and into PGMInline.h so we can drop all the &pVM->pgm.s and &pVCpu->pgm.s stuff.
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1	/* $Id: PGM.cpp 26150 2010-02-02 15:52:54Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/selm.h>
588	#include <VBox/ssm.h>
589	#include <VBox/hwaccm.h>
590	#include "PGMInternal.h"
591	#include <VBox/vm.h>
592	#include "PGMInline.h"
593
594	#include <VBox/dbg.h>
595	#include <VBox/param.h>
596	#include <VBox/err.h>
597
598	#include <iprt/asm.h>
599	#include <iprt/assert.h>
600	#include <iprt/env.h>
601	#include <iprt/mem.h>
602	#include <iprt/file.h>
603	#include <iprt/string.h>
604	#include <iprt/thread.h>
605
606
607	/*******************************************************************************
608	* Defined Constants And Macros *
609	*******************************************************************************/
610	/** Saved state data unit version for 2.5.x and later. */
611	#define PGM_SAVED_STATE_VERSION 9
612	/** Saved state data unit version for 2.2.2 and later. */
613	#define PGM_SAVED_STATE_VERSION_2_2_2 8
614	/** Saved state data unit version for 2.2.0. */
615	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
616	/** Saved state data unit version. */
617	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
618
619
620	/*******************************************************************************
621	* Internal Functions *
622	*******************************************************************************/
623	static int pgmR3InitPaging(PVM pVM);
624	static void pgmR3InitStats(PVM pVM);
625	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
626	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
628	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
629	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
630	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
631	#ifdef VBOX_STRICT
632	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
633	#endif
634	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
635	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
636	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
637
638	#ifdef VBOX_WITH_DEBUGGER
639	/** @todo Convert the first two commands to 'info' items. */
640	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# ifdef VBOX_STRICT
645	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	# endif
647	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	#endif
649
650
651	/*******************************************************************************
652	* Global Variables *
653	*******************************************************************************/
654	#ifdef VBOX_WITH_DEBUGGER
655	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
656	static const DBGCVARDESC g_aPgmErrorArgs[] =
657	{
658	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
659	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
660	};
661
662	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
663	{
664	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
665	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
666	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
667	};
668
669	/** Command descriptors. */
670	static const DBGCCMD g_aCmds[] =
671	{
672	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
673	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
674	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
675	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
676	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
677	#ifdef VBOX_STRICT
678	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
679	#endif
680	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
681	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
682	};
683	#endif
684
685
686
687
688	/*
689	* Shadow - 32-bit mode
690	*/
691	#define PGM_SHW_TYPE PGM_TYPE_32BIT
692	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
693	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
694	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
695	#include "PGMShw.h"
696
697	/* Guest - real mode */
698	#define PGM_GST_TYPE PGM_TYPE_REAL
699	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
700	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
701	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
702	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
703	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
704	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
705	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
706	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
707	#include "PGMBth.h"
708	#include "PGMGstDefs.h"
709	#include "PGMGst.h"
710	#undef BTH_PGMPOOLKIND_PT_FOR_PT
711	#undef BTH_PGMPOOLKIND_ROOT
712	#undef PGM_BTH_NAME
713	#undef PGM_BTH_NAME_RC_STR
714	#undef PGM_BTH_NAME_R0_STR
715	#undef PGM_GST_TYPE
716	#undef PGM_GST_NAME
717	#undef PGM_GST_NAME_RC_STR
718	#undef PGM_GST_NAME_R0_STR
719
720	/* Guest - protected mode */
721	#define PGM_GST_TYPE PGM_TYPE_PROT
722	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
723	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
724	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
725	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
726	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
727	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
728	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
729	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
730	#include "PGMBth.h"
731	#include "PGMGstDefs.h"
732	#include "PGMGst.h"
733	#undef BTH_PGMPOOLKIND_PT_FOR_PT
734	#undef BTH_PGMPOOLKIND_ROOT
735	#undef PGM_BTH_NAME
736	#undef PGM_BTH_NAME_RC_STR
737	#undef PGM_BTH_NAME_R0_STR
738	#undef PGM_GST_TYPE
739	#undef PGM_GST_NAME
740	#undef PGM_GST_NAME_RC_STR
741	#undef PGM_GST_NAME_R0_STR
742
743	/* Guest - 32-bit mode */
744	#define PGM_GST_TYPE PGM_TYPE_32BIT
745	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
746	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
747	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
748	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
749	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
750	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
751	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
752	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
753	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
754	#include "PGMBth.h"
755	#include "PGMGstDefs.h"
756	#include "PGMGst.h"
757	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
758	#undef BTH_PGMPOOLKIND_PT_FOR_PT
759	#undef BTH_PGMPOOLKIND_ROOT
760	#undef PGM_BTH_NAME
761	#undef PGM_BTH_NAME_RC_STR
762	#undef PGM_BTH_NAME_R0_STR
763	#undef PGM_GST_TYPE
764	#undef PGM_GST_NAME
765	#undef PGM_GST_NAME_RC_STR
766	#undef PGM_GST_NAME_R0_STR
767
768	#undef PGM_SHW_TYPE
769	#undef PGM_SHW_NAME
770	#undef PGM_SHW_NAME_RC_STR
771	#undef PGM_SHW_NAME_R0_STR
772
773
774	/*
775	* Shadow - PAE mode
776	*/
777	#define PGM_SHW_TYPE PGM_TYPE_PAE
778	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
779	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
780	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
781	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
782	#include "PGMShw.h"
783
784	/* Guest - real mode */
785	#define PGM_GST_TYPE PGM_TYPE_REAL
786	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
787	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
788	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
789	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
790	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
791	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
792	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
793	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
794	#include "PGMGstDefs.h"
795	#include "PGMBth.h"
796	#undef BTH_PGMPOOLKIND_PT_FOR_PT
797	#undef BTH_PGMPOOLKIND_ROOT
798	#undef PGM_BTH_NAME
799	#undef PGM_BTH_NAME_RC_STR
800	#undef PGM_BTH_NAME_R0_STR
801	#undef PGM_GST_TYPE
802	#undef PGM_GST_NAME
803	#undef PGM_GST_NAME_RC_STR
804	#undef PGM_GST_NAME_R0_STR
805
806	/* Guest - protected mode */
807	#define PGM_GST_TYPE PGM_TYPE_PROT
808	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
809	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
810	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
811	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
812	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
813	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
814	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
815	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
816	#include "PGMGstDefs.h"
817	#include "PGMBth.h"
818	#undef BTH_PGMPOOLKIND_PT_FOR_PT
819	#undef BTH_PGMPOOLKIND_ROOT
820	#undef PGM_BTH_NAME
821	#undef PGM_BTH_NAME_RC_STR
822	#undef PGM_BTH_NAME_R0_STR
823	#undef PGM_GST_TYPE
824	#undef PGM_GST_NAME
825	#undef PGM_GST_NAME_RC_STR
826	#undef PGM_GST_NAME_R0_STR
827
828	/* Guest - 32-bit mode */
829	#define PGM_GST_TYPE PGM_TYPE_32BIT
830	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
831	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
832	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
833	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
834	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
835	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
836	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
837	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
838	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
839	#include "PGMGstDefs.h"
840	#include "PGMBth.h"
841	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
842	#undef BTH_PGMPOOLKIND_PT_FOR_PT
843	#undef BTH_PGMPOOLKIND_ROOT
844	#undef PGM_BTH_NAME
845	#undef PGM_BTH_NAME_RC_STR
846	#undef PGM_BTH_NAME_R0_STR
847	#undef PGM_GST_TYPE
848	#undef PGM_GST_NAME
849	#undef PGM_GST_NAME_RC_STR
850	#undef PGM_GST_NAME_R0_STR
851
852	/* Guest - PAE mode */
853	#define PGM_GST_TYPE PGM_TYPE_PAE
854	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
855	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
856	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
857	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
858	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
859	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
860	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
861	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
862	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
863	#include "PGMBth.h"
864	#include "PGMGstDefs.h"
865	#include "PGMGst.h"
866	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
867	#undef BTH_PGMPOOLKIND_PT_FOR_PT
868	#undef BTH_PGMPOOLKIND_ROOT
869	#undef PGM_BTH_NAME
870	#undef PGM_BTH_NAME_RC_STR
871	#undef PGM_BTH_NAME_R0_STR
872	#undef PGM_GST_TYPE
873	#undef PGM_GST_NAME
874	#undef PGM_GST_NAME_RC_STR
875	#undef PGM_GST_NAME_R0_STR
876
877	#undef PGM_SHW_TYPE
878	#undef PGM_SHW_NAME
879	#undef PGM_SHW_NAME_RC_STR
880	#undef PGM_SHW_NAME_R0_STR
881
882
883	/*
884	* Shadow - AMD64 mode
885	*/
886	#define PGM_SHW_TYPE PGM_TYPE_AMD64
887	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
888	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
889	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
890	#include "PGMShw.h"
891
892	#ifdef VBOX_WITH_64_BITS_GUESTS
893	/* Guest - AMD64 mode */
894	# define PGM_GST_TYPE PGM_TYPE_AMD64
895	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
896	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
897	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
898	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
899	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
900	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
901	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
902	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
903	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
904	# include "PGMBth.h"
905	# include "PGMGstDefs.h"
906	# include "PGMGst.h"
907	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
908	# undef BTH_PGMPOOLKIND_PT_FOR_PT
909	# undef BTH_PGMPOOLKIND_ROOT
910	# undef PGM_BTH_NAME
911	# undef PGM_BTH_NAME_RC_STR
912	# undef PGM_BTH_NAME_R0_STR
913	# undef PGM_GST_TYPE
914	# undef PGM_GST_NAME
915	# undef PGM_GST_NAME_RC_STR
916	# undef PGM_GST_NAME_R0_STR
917	#endif /* VBOX_WITH_64_BITS_GUESTS */
918
919	#undef PGM_SHW_TYPE
920	#undef PGM_SHW_NAME
921	#undef PGM_SHW_NAME_RC_STR
922	#undef PGM_SHW_NAME_R0_STR
923
924
925	/*
926	* Shadow - Nested paging mode
927	*/
928	#define PGM_SHW_TYPE PGM_TYPE_NESTED
929	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
930	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
931	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
932	#include "PGMShw.h"
933
934	/* Guest - real mode */
935	#define PGM_GST_TYPE PGM_TYPE_REAL
936	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
937	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
938	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
939	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
940	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
941	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
942	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
943	#include "PGMGstDefs.h"
944	#include "PGMBth.h"
945	#undef BTH_PGMPOOLKIND_PT_FOR_PT
946	#undef PGM_BTH_NAME
947	#undef PGM_BTH_NAME_RC_STR
948	#undef PGM_BTH_NAME_R0_STR
949	#undef PGM_GST_TYPE
950	#undef PGM_GST_NAME
951	#undef PGM_GST_NAME_RC_STR
952	#undef PGM_GST_NAME_R0_STR
953
954	/* Guest - protected mode */
955	#define PGM_GST_TYPE PGM_TYPE_PROT
956	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
957	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
958	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
959	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
960	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
961	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
962	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
963	#include "PGMGstDefs.h"
964	#include "PGMBth.h"
965	#undef BTH_PGMPOOLKIND_PT_FOR_PT
966	#undef PGM_BTH_NAME
967	#undef PGM_BTH_NAME_RC_STR
968	#undef PGM_BTH_NAME_R0_STR
969	#undef PGM_GST_TYPE
970	#undef PGM_GST_NAME
971	#undef PGM_GST_NAME_RC_STR
972	#undef PGM_GST_NAME_R0_STR
973
974	/* Guest - 32-bit mode */
975	#define PGM_GST_TYPE PGM_TYPE_32BIT
976	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
977	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
978	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
979	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
980	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
981	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
982	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
983	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
984	#include "PGMGstDefs.h"
985	#include "PGMBth.h"
986	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
987	#undef BTH_PGMPOOLKIND_PT_FOR_PT
988	#undef PGM_BTH_NAME
989	#undef PGM_BTH_NAME_RC_STR
990	#undef PGM_BTH_NAME_R0_STR
991	#undef PGM_GST_TYPE
992	#undef PGM_GST_NAME
993	#undef PGM_GST_NAME_RC_STR
994	#undef PGM_GST_NAME_R0_STR
995
996	/* Guest - PAE mode */
997	#define PGM_GST_TYPE PGM_TYPE_PAE
998	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
999	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1000	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1001	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1002	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1003	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1004	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1005	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1006	#include "PGMGstDefs.h"
1007	#include "PGMBth.h"
1008	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1009	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1010	#undef PGM_BTH_NAME
1011	#undef PGM_BTH_NAME_RC_STR
1012	#undef PGM_BTH_NAME_R0_STR
1013	#undef PGM_GST_TYPE
1014	#undef PGM_GST_NAME
1015	#undef PGM_GST_NAME_RC_STR
1016	#undef PGM_GST_NAME_R0_STR
1017
1018	#ifdef VBOX_WITH_64_BITS_GUESTS
1019	/* Guest - AMD64 mode */
1020	# define PGM_GST_TYPE PGM_TYPE_AMD64
1021	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1022	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1023	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1024	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1025	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1026	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1027	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1028	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1029	# include "PGMGstDefs.h"
1030	# include "PGMBth.h"
1031	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1032	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1033	# undef PGM_BTH_NAME
1034	# undef PGM_BTH_NAME_RC_STR
1035	# undef PGM_BTH_NAME_R0_STR
1036	# undef PGM_GST_TYPE
1037	# undef PGM_GST_NAME
1038	# undef PGM_GST_NAME_RC_STR
1039	# undef PGM_GST_NAME_R0_STR
1040	#endif /* VBOX_WITH_64_BITS_GUESTS */
1041
1042	#undef PGM_SHW_TYPE
1043	#undef PGM_SHW_NAME
1044	#undef PGM_SHW_NAME_RC_STR
1045	#undef PGM_SHW_NAME_R0_STR
1046
1047
1048	/*
1049	* Shadow - EPT
1050	*/
1051	#define PGM_SHW_TYPE PGM_TYPE_EPT
1052	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1053	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1054	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1055	#include "PGMShw.h"
1056
1057	/* Guest - real mode */
1058	#define PGM_GST_TYPE PGM_TYPE_REAL
1059	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1060	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1061	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1062	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1063	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1064	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1065	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1066	#include "PGMGstDefs.h"
1067	#include "PGMBth.h"
1068	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1069	#undef PGM_BTH_NAME
1070	#undef PGM_BTH_NAME_RC_STR
1071	#undef PGM_BTH_NAME_R0_STR
1072	#undef PGM_GST_TYPE
1073	#undef PGM_GST_NAME
1074	#undef PGM_GST_NAME_RC_STR
1075	#undef PGM_GST_NAME_R0_STR
1076
1077	/* Guest - protected mode */
1078	#define PGM_GST_TYPE PGM_TYPE_PROT
1079	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1080	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1081	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1082	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1083	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1084	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1085	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1086	#include "PGMGstDefs.h"
1087	#include "PGMBth.h"
1088	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1089	#undef PGM_BTH_NAME
1090	#undef PGM_BTH_NAME_RC_STR
1091	#undef PGM_BTH_NAME_R0_STR
1092	#undef PGM_GST_TYPE
1093	#undef PGM_GST_NAME
1094	#undef PGM_GST_NAME_RC_STR
1095	#undef PGM_GST_NAME_R0_STR
1096
1097	/* Guest - 32-bit mode */
1098	#define PGM_GST_TYPE PGM_TYPE_32BIT
1099	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1100	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1101	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1102	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1103	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1104	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1105	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1106	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1107	#include "PGMGstDefs.h"
1108	#include "PGMBth.h"
1109	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1110	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1111	#undef PGM_BTH_NAME
1112	#undef PGM_BTH_NAME_RC_STR
1113	#undef PGM_BTH_NAME_R0_STR
1114	#undef PGM_GST_TYPE
1115	#undef PGM_GST_NAME
1116	#undef PGM_GST_NAME_RC_STR
1117	#undef PGM_GST_NAME_R0_STR
1118
1119	/* Guest - PAE mode */
1120	#define PGM_GST_TYPE PGM_TYPE_PAE
1121	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1122	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1123	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1124	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1125	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1126	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1127	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1128	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1129	#include "PGMGstDefs.h"
1130	#include "PGMBth.h"
1131	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1132	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1133	#undef PGM_BTH_NAME
1134	#undef PGM_BTH_NAME_RC_STR
1135	#undef PGM_BTH_NAME_R0_STR
1136	#undef PGM_GST_TYPE
1137	#undef PGM_GST_NAME
1138	#undef PGM_GST_NAME_RC_STR
1139	#undef PGM_GST_NAME_R0_STR
1140
1141	#ifdef VBOX_WITH_64_BITS_GUESTS
1142	/* Guest - AMD64 mode */
1143	# define PGM_GST_TYPE PGM_TYPE_AMD64
1144	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1145	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1146	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1147	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1148	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1149	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1150	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1151	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1152	# include "PGMGstDefs.h"
1153	# include "PGMBth.h"
1154	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1155	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1156	# undef PGM_BTH_NAME
1157	# undef PGM_BTH_NAME_RC_STR
1158	# undef PGM_BTH_NAME_R0_STR
1159	# undef PGM_GST_TYPE
1160	# undef PGM_GST_NAME
1161	# undef PGM_GST_NAME_RC_STR
1162	# undef PGM_GST_NAME_R0_STR
1163	#endif /* VBOX_WITH_64_BITS_GUESTS */
1164
1165	#undef PGM_SHW_TYPE
1166	#undef PGM_SHW_NAME
1167	#undef PGM_SHW_NAME_RC_STR
1168	#undef PGM_SHW_NAME_R0_STR
1169
1170
1171
1172	/**
1173	* Initiates the paging of VM.
1174	*
1175	* @returns VBox status code.
1176	* @param pVM Pointer to VM structure.
1177	*/
1178	VMMR3DECL(int) PGMR3Init(PVM pVM)
1179	{
1180	LogFlow(("PGMR3Init:\n"));
1181	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1182	int rc;
1183
1184	/*
1185	* Assert alignment and sizes.
1186	*/
1187	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1188	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1189	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1190
1191	/*
1192	* Init the structure.
1193	*/
1194	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1195	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1196
1197	/* Init the per-CPU part. */
1198	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1199	{
1200	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1201	PPGMCPU pPGM = &pVCpu->pgm.s;
1202
1203	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1204	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1205	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1206
1207	pPGM->enmShadowMode = PGMMODE_INVALID;
1208	pPGM->enmGuestMode = PGMMODE_INVALID;
1209
1210	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1211
1212	pPGM->pGstPaePdptR3 = NULL;
1213	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1214	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1215	#endif
1216	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1217	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1218	{
1219	pPGM->apGstPaePDsR3[i] = NULL;
1220	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1221	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1222	#endif
1223	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1224	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1225	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1226	}
1227
1228	pPGM->fA20Enabled = true;
1229	}
1230
1231	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1232	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1233	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1234
1235	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1236	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1237	true
1238	#else
1239	false
1240	#endif
1241	);
1242	AssertLogRelRCReturn(rc, rc);
1243
1244	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1245	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1246	#else
1247	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1248	#endif
1249	AssertLogRelRCReturn(rc, rc);
1250	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1251	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1252
1253	/*
1254	* Get the configured RAM size - to estimate saved state size.
1255	*/
1256	uint64_t cbRam;
1257	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1258	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1259	cbRam = 0;
1260	else if (RT_SUCCESS(rc))
1261	{
1262	if (cbRam < PAGE_SIZE)
1263	cbRam = 0;
1264	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1265	}
1266	else
1267	{
1268	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1269	return rc;
1270	}
1271
1272	/*
1273	* Register callbacks, string formatters and the saved state data unit.
1274	*/
1275	#ifdef VBOX_STRICT
1276	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1277	#endif
1278	PGMRegisterStringFormatTypes();
1279
1280	rc = pgmR3InitSavedState(pVM, cbRam);
1281	if (RT_FAILURE(rc))
1282	return rc;
1283
1284	/*
1285	* Initialize the PGM critical section and flush the phys TLBs
1286	*/
1287	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, RT_SRC_POS, "PGM");
1288	AssertRCReturn(rc, rc);
1289
1290	PGMR3PhysChunkInvalidateTLB(pVM);
1291	PGMPhysInvalidatePageMapTLB(pVM);
1292
1293	/*
1294	* For the time being we sport a full set of handy pages in addition to the base
1295	* memory to simplify things.
1296	*/
1297	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1298	AssertRCReturn(rc, rc);
1299
1300	/*
1301	* Trees
1302	*/
1303	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1304	if (RT_SUCCESS(rc))
1305	{
1306	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1307	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1308
1309	/*
1310	* Alocate the zero page.
1311	*/
1312	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1313	}
1314	if (RT_SUCCESS(rc))
1315	{
1316	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1317	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1318	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1319	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1320
1321	/*
1322	* Init the paging.
1323	*/
1324	rc = pgmR3InitPaging(pVM);
1325	}
1326	if (RT_SUCCESS(rc))
1327	{
1328	/*
1329	* Init the page pool.
1330	*/
1331	rc = pgmR3PoolInit(pVM);
1332	}
1333	if (RT_SUCCESS(rc))
1334	{
1335	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1336	{
1337	PVMCPU pVCpu = &pVM->aCpus[i];
1338	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1339	if (RT_FAILURE(rc))
1340	break;
1341	}
1342	}
1343
1344	if (RT_SUCCESS(rc))
1345	{
1346	/*
1347	* Info & statistics
1348	*/
1349	DBGFR3InfoRegisterInternal(pVM, "mode",
1350	"Shows the current paging mode. "
1351	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1352	pgmR3InfoMode);
1353	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1354	"Dumps all the entries in the top level paging table. No arguments.",
1355	pgmR3InfoCr3);
1356	DBGFR3InfoRegisterInternal(pVM, "phys",
1357	"Dumps all the physical address ranges. No arguments.",
1358	pgmR3PhysInfo);
1359	DBGFR3InfoRegisterInternal(pVM, "handlers",
1360	"Dumps physical, virtual and hyper virtual handlers. "
1361	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1362	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1363	pgmR3InfoHandlers);
1364	DBGFR3InfoRegisterInternal(pVM, "mappings",
1365	"Dumps guest mappings.",
1366	pgmR3MapInfo);
1367
1368	pgmR3InitStats(pVM);
1369
1370	#ifdef VBOX_WITH_DEBUGGER
1371	/*
1372	* Debugger commands.
1373	*/
1374	static bool s_fRegisteredCmds = false;
1375	if (!s_fRegisteredCmds)
1376	{
1377	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1378	if (RT_SUCCESS(rc2))
1379	s_fRegisteredCmds = true;
1380	}
1381	#endif
1382	return VINF_SUCCESS;
1383	}
1384
1385	/* Almost no cleanup necessary, MM frees all memory. */
1386	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1387
1388	return rc;
1389	}
1390
1391
1392	/**
1393	* Initializes the per-VCPU PGM.
1394	*
1395	* @returns VBox status code.
1396	* @param pVM The VM to operate on.
1397	*/
1398	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1399	{
1400	LogFlow(("PGMR3InitCPU\n"));
1401	return VINF_SUCCESS;
1402	}
1403
1404
1405	/**
1406	* Init paging.
1407	*
1408	* Since we need to check what mode the host is operating in before we can choose
1409	* the right paging functions for the host we have to delay this until R0 has
1410	* been initialized.
1411	*
1412	* @returns VBox status code.
1413	* @param pVM VM handle.
1414	*/
1415	static int pgmR3InitPaging(PVM pVM)
1416	{
1417	/*
1418	* Force a recalculation of modes and switcher so everyone gets notified.
1419	*/
1420	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1421	{
1422	PVMCPU pVCpu = &pVM->aCpus[i];
1423
1424	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1425	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1426	}
1427
1428	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1429
1430	/*
1431	* Allocate static mapping space for whatever the cr3 register
1432	* points to and in the case of PAE mode to the 4 PDs.
1433	*/
1434	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1435	if (RT_FAILURE(rc))
1436	{
1437	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1438	return rc;
1439	}
1440	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1441
1442	/*
1443	* Allocate pages for the three possible intermediate contexts
1444	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1445	* for the sake of simplicity. The AMD64 uses the PAE for the
1446	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1447	*
1448	* We assume that two page tables will be enought for the core code
1449	* mappings (HC virtual and identity).
1450	*/
1451	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1452	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1453	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1454	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1455	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1456	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1457	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1458	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1459	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1460	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1463
1464	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1465	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1466	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1467	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1468	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1469	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1470
1471	/*
1472	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1473	*/
1474	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1475	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1476	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1477
1478	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1479	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1480
1481	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1482	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1483	{
1484	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1485	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1486	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1487	}
1488
1489	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1490	{
1491	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1492	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1493	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1494	}
1495
1496	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1497	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1498	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1499	\| HCPhysInterPaePDPT64;
1500
1501	/*
1502	* Initialize paging workers and mode from current host mode
1503	* and the guest running in real mode.
1504	*/
1505	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1506	switch (pVM->pgm.s.enmHostMode)
1507	{
1508	case SUPPAGINGMODE_32_BIT:
1509	case SUPPAGINGMODE_32_BIT_GLOBAL:
1510	case SUPPAGINGMODE_PAE:
1511	case SUPPAGINGMODE_PAE_GLOBAL:
1512	case SUPPAGINGMODE_PAE_NX:
1513	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1514	break;
1515
1516	case SUPPAGINGMODE_AMD64:
1517	case SUPPAGINGMODE_AMD64_GLOBAL:
1518	case SUPPAGINGMODE_AMD64_NX:
1519	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1520	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1521	if (ARCH_BITS != 64)
1522	{
1523	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1524	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1525	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1526	}
1527	#endif
1528	break;
1529	default:
1530	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1531	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1532	}
1533	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1534	if (RT_SUCCESS(rc))
1535	{
1536	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1537	#if HC_ARCH_BITS == 64
1538	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1539	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1540	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1541	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1542	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1543	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1544	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1545	#endif
1546
1547	return VINF_SUCCESS;
1548	}
1549
1550	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1551	return rc;
1552	}
1553
1554
1555	/**
1556	* Init statistics
1557	*/
1558	static void pgmR3InitStats(PVM pVM)
1559	{
1560	PPGM pPGM = &pVM->pgm.s;
1561	int rc;
1562
1563	/* Common - misc variables */
1564	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1565	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1566	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1567	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1568	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1569	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1570	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1571	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1572	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1573	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1574	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1575	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1576	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1577
1578	/* Live save */
1579	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1580	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1581	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1582	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1583	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1584	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1585	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1586	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1587	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1588	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1589	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1590	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1591	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1592	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1593	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1594	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1595	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1596	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1597
1598	#ifdef VBOX_WITH_STATISTICS
1599
1600	# define PGM_REG_COUNTER(a, b, c) \
1601	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1602	AssertRC(rc);
1603
1604	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1605	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1606	AssertRC(rc);
1607
1608	# define PGM_REG_PROFILE(a, b, c) \
1609	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1610	AssertRC(rc);
1611
1612	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1613	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1614	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1615	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1616	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1617	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1618	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1619	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1620	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1621	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1622
1623	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1624	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1625	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1626	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1627	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1628	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1629	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1630	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1631	PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1632	PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1633
1634	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1635	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1636	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1637	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1638
1639	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1640	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1641	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1642	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1643
1644	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1645	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1646	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1647	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1648	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1649	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1650
1651	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1652	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1653	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1654	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1655	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1656	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1657	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1658	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1659
1660	/* GC only: */
1661	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1662	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1663	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1664	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1665
1666	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1667	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1668	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1669	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1670	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1671	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1672	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1673	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1674
1675	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1676	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1677	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1678	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1679	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1680	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1681	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1682	# endif
1683
1684	# undef PGM_REG_COUNTER
1685	# undef PGM_REG_PROFILE
1686	#endif
1687
1688	/*
1689	* Note! The layout below matches the member layout exactly!
1690	*/
1691
1692	/*
1693	* Common - stats
1694	*/
1695	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1696	{
1697	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1698
1699	#define PGM_REG_COUNTER(a, b, c) \
1700	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1701	AssertRC(rc);
1702	#define PGM_REG_PROFILE(a, b, c) \
1703	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1704	AssertRC(rc);
1705
1706	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1707
1708	#ifdef VBOX_WITH_STATISTICS
1709
1710	# if 0 /* rarely useful; leave for debugging. */
1711	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1712	STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1713	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1714	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPagePD); j++)
1715	STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1716	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1717	# endif
1718	/* R0 only: */
1719	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapMigrateInvlPg, "/PGM/CPU%u/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1720	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapGCPageInl, "/PGM/CPU%u/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1721	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1722	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1723	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1724	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1725	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPageInl, "/PGM/CPU%u/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1726	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlHits, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1727	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1728	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPage, "/PGM/CPU%u/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1729	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetOptimize, "/PGM/CPU%u/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1730	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchFlushes, "/PGM/CPU%u/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1731	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchHits, "/PGM/CPU%u/R0/DynMapPage/SetSearchHits", "Set search hits.");
1732	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchMisses, "/PGM/CPU%u/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1733	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPage, "/PGM/CPU%u/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1734	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits0, "/PGM/CPU%u/R0/DynMapPage/Hits0", "Hits at iPage+0");
1735	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits1, "/PGM/CPU%u/R0/DynMapPage/Hits1", "Hits at iPage+1");
1736	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits2, "/PGM/CPU%u/R0/DynMapPage/Hits2", "Hits at iPage+2");
1737	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageInvlPg, "/PGM/CPU%u/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1738	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlow, "/PGM/CPU%u/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1739	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%u/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1740	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%u/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1741	//PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMapPage/SlowLostHits", "Lost hits.");
1742	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSubsets, "/PGM/CPU%u/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1743	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPopFlushes, "/PGM/CPU%u/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1744	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[0], "/PGM/CPU%u/R0/SetSize000..09", "00-09% filled");
1745	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[1], "/PGM/CPU%u/R0/SetSize010..19", "10-19% filled");
1746	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[2], "/PGM/CPU%u/R0/SetSize020..29", "20-29% filled");
1747	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[3], "/PGM/CPU%u/R0/SetSize030..39", "30-39% filled");
1748	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[4], "/PGM/CPU%u/R0/SetSize040..49", "40-49% filled");
1749	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[5], "/PGM/CPU%u/R0/SetSize050..59", "50-59% filled");
1750	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[6], "/PGM/CPU%u/R0/SetSize060..69", "60-69% filled");
1751	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[7], "/PGM/CPU%u/R0/SetSize070..79", "70-79% filled");
1752	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[8], "/PGM/CPU%u/R0/SetSize080..89", "80-89% filled");
1753	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[9], "/PGM/CPU%u/R0/SetSize090..99", "90-99% filled");
1754	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[10], "/PGM/CPU%u/R0/SetSize100", "100% filled");
1755
1756	/* RZ only: */
1757	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1758	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%u/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1759	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeSyncPT, "/PGM/CPU%u/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1760	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeMapping, "/PGM/CPU%u/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1761	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1762	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeHandlers, "/PGM/CPU%u/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1763	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1764	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1765	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1766	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1767	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1768	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1769	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1770	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1771	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1772	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1773	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1774	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1775	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1776	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1777	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1778	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersPhysical, "/PGM/CPU%u/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1779	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1780	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1781	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1782	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1783	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1784	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1785	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1786	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1787	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1788	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1789	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1790	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1791	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1792	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1793	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1794	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1795	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1796	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFUnh, "/PGM/CPU%u/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1797	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1798	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1799	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1800	#if 0 /* rarely useful; leave for debugging. */
1801	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatRZTrap0ePD); j++)
1802	STAMR3RegisterF(pVM, &pPgmCpu->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1803	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1804	#endif
1805	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1806	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1807	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1808	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1809	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1810
1811	/* HC only: */
1812
1813	/* RZ & R3: */
1814	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1815	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1816	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1817	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1818	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1819	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1820	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1821	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1822	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1823	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1824	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1825	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1826	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1827	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1828	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1829	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1830	PGM_REG_COUNTER(&pPgmCpu->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1831	PGM_REG_PROFILE(&pPgmCpu->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1832	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1833	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1834	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1835	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1836	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1837	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1838	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1839	PGM_REG_COUNTER(&pPgmCpu->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1840	PGM_REG_PROFILE(&pPgmCpu->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1841	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1842	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1843	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1844	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1845	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1846	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1847	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1848	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1849	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1850	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1851	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1852	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1853	PGM_REG_PROFILE(&pPgmCpu->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1854	PGM_REG_PROFILE(&pPgmCpu->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1855	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1856	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1857	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1858	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1859	PGM_REG_PROFILE(&pPgmCpu->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1860
1861	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1862	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1863	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1864	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1865	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1866	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1867	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1868	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1869	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1870	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1871	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1872	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1873	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1874	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1875	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1876	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1877	PGM_REG_COUNTER(&pPgmCpu->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1878	PGM_REG_PROFILE(&pPgmCpu->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1879	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1880	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1881	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1882	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1883	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1884	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1885	PGM_REG_COUNTER(&pPgmCpu->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1886	PGM_REG_PROFILE(&pPgmCpu->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1887	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1888	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1889	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1890	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1891	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1892	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1893	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1894	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1895	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1896	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1897	PGM_REG_PROFILE(&pPgmCpu->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1898	PGM_REG_PROFILE(&pPgmCpu->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1899	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1900	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1901	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1902	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1903	PGM_REG_PROFILE(&pPgmCpu->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1904	#endif /* VBOX_WITH_STATISTICS */
1905
1906	#undef PGM_REG_PROFILE
1907	#undef PGM_REG_COUNTER
1908
1909	}
1910	}
1911
1912
1913	/**
1914	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1915	*
1916	* The dynamic mapping area will also be allocated and initialized at this
1917	* time. We could allocate it during PGMR3Init of course, but the mapping
1918	* wouldn't be allocated at that time preventing us from setting up the
1919	* page table entries with the dummy page.
1920	*
1921	* @returns VBox status code.
1922	* @param pVM VM handle.
1923	*/
1924	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1925	{
1926	RTGCPTR GCPtr;
1927	int rc;
1928
1929	/*
1930	* Reserve space for the dynamic mappings.
1931	*/
1932	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1933	if (RT_SUCCESS(rc))
1934	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1935
1936	if ( RT_SUCCESS(rc)
1937	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1938	{
1939	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1940	if (RT_SUCCESS(rc))
1941	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1942	}
1943	if (RT_SUCCESS(rc))
1944	{
1945	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1946	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1947	}
1948	return rc;
1949	}
1950
1951
1952	/**
1953	* Ring-3 init finalizing.
1954	*
1955	* @returns VBox status code.
1956	* @param pVM The VM handle.
1957	*/
1958	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1959	{
1960	int rc;
1961
1962	/*
1963	* Reserve space for the dynamic mappings.
1964	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1965	*/
1966	/* get the pointer to the page table entries. */
1967	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1968	AssertRelease(pMapping);
1969	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1970	const unsigned iPT = off >> X86_PD_SHIFT;
1971	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1972	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1973	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1974
1975	/* init cache */
1976	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1977	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1978	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1979
1980	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1981	{
1982	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1983	AssertRCReturn(rc, rc);
1984	}
1985
1986	/*
1987	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1988	* Intel only goes up to 36 bits, so we stick to 36 as well.
1989	*/
1990	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1991	uint32_t u32Dummy, u32Features;
1992	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1993
1994	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1995	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1996	else
1997	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1998
1999	/*
2000	* Allocate memory if we're supposed to do that.
2001	*/
2002	if (pVM->pgm.s.fRamPreAlloc)
2003	rc = pgmR3PhysRamPreAllocate(pVM);
2004
2005	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2006	return rc;
2007	}
2008
2009
2010	/**
2011	* Applies relocations to data and code managed by this component.
2012	*
2013	* This function will be called at init and whenever the VMM need to relocate it
2014	* self inside the GC.
2015	*
2016	* @param pVM The VM.
2017	* @param offDelta Relocation delta relative to old location.
2018	*/
2019	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2020	{
2021	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2022
2023	/*
2024	* Paging stuff.
2025	*/
2026	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2027
2028	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2029
2030	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2031	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2032	{
2033	PVMCPU pVCpu = &pVM->aCpus[i];
2034
2035	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2036
2037	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2038	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2039	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2040	}
2041
2042	/*
2043	* Trees.
2044	*/
2045	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2046
2047	/*
2048	* Ram ranges.
2049	*/
2050	if (pVM->pgm.s.pRamRangesR3)
2051	{
2052	/* Update the pSelfRC pointers and relink them. */
2053	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2054	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2055	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2056	pgmR3PhysRelinkRamRanges(pVM);
2057	}
2058
2059	/*
2060	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2061	* be mapped and thus not included in the above exercise.
2062	*/
2063	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2064	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2065	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2066
2067	/*
2068	* Update the two page directories with all page table mappings.
2069	* (One or more of them have changed, that's why we're here.)
2070	*/
2071	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2072	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2073	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2074
2075	/* Relocate GC addresses of Page Tables. */
2076	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2077	{
2078	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2079	{
2080	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2081	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2082	}
2083	}
2084
2085	/*
2086	* Dynamic page mapping area.
2087	*/
2088	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2089	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2090	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2091
2092	/*
2093	* The Zero page.
2094	*/
2095	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2096	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2097	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2098	#else
2099	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2100	#endif
2101
2102	/*
2103	* Physical and virtual handlers.
2104	*/
2105	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2106	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2107	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2108
2109	/*
2110	* The page pool.
2111	*/
2112	pgmR3PoolRelocate(pVM);
2113	}
2114
2115
2116	/**
2117	* Callback function for relocating a physical access handler.
2118	*
2119	* @returns 0 (continue enum)
2120	* @param pNode Pointer to a PGMPHYSHANDLER node.
2121	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2122	* not certain the delta will fit in a void pointer for all possible configs.
2123	*/
2124	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2125	{
2126	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2127	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2128	if (pHandler->pfnHandlerRC)
2129	pHandler->pfnHandlerRC += offDelta;
2130	if (pHandler->pvUserRC >= 0x10000)
2131	pHandler->pvUserRC += offDelta;
2132	return 0;
2133	}
2134
2135
2136	/**
2137	* Callback function for relocating a virtual access handler.
2138	*
2139	* @returns 0 (continue enum)
2140	* @param pNode Pointer to a PGMVIRTHANDLER node.
2141	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2142	* not certain the delta will fit in a void pointer for all possible configs.
2143	*/
2144	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2145	{
2146	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2147	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2148	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2149	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2150	Assert(pHandler->pfnHandlerRC);
2151	pHandler->pfnHandlerRC += offDelta;
2152	return 0;
2153	}
2154
2155
2156	/**
2157	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2158	*
2159	* @returns 0 (continue enum)
2160	* @param pNode Pointer to a PGMVIRTHANDLER node.
2161	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2162	* not certain the delta will fit in a void pointer for all possible configs.
2163	*/
2164	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2165	{
2166	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2167	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2168	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2169	Assert(pHandler->pfnHandlerRC);
2170	pHandler->pfnHandlerRC += offDelta;
2171	return 0;
2172	}
2173
2174
2175	/**
2176	* Resets a virtual CPU when unplugged.
2177	*
2178	* @param pVM The VM handle.
2179	* @param pVCpu The virtual CPU handle.
2180	*/
2181	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2182	{
2183	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2184	AssertRC(rc);
2185
2186	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2187	AssertRC(rc);
2188
2189	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2190
2191	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2192
2193	/*
2194	* Re-init other members.
2195	*/
2196	pVCpu->pgm.s.fA20Enabled = true;
2197
2198	/*
2199	* Clear the FFs PGM owns.
2200	*/
2201	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2202	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2203	}
2204
2205
2206	/**
2207	* The VM is being reset.
2208	*
2209	* For the PGM component this means that any PD write monitors
2210	* needs to be removed.
2211	*
2212	* @param pVM VM handle.
2213	*/
2214	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2215	{
2216	int rc;
2217
2218	LogFlow(("PGMR3Reset:\n"));
2219	VM_ASSERT_EMT(pVM);
2220
2221	pgmLock(pVM);
2222
2223	/*
2224	* Unfix any fixed mappings and disable CR3 monitoring.
2225	*/
2226	pVM->pgm.s.fMappingsFixed = false;
2227	pVM->pgm.s.fMappingsFixedRestored = false;
2228	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2229	pVM->pgm.s.cbMappingFixed = 0;
2230
2231	/*
2232	* Exit the guest paging mode before the pgm pool gets reset.
2233	* Important to clean up the amd64 case.
2234	*/
2235	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2236	{
2237	PVMCPU pVCpu = &pVM->aCpus[i];
2238	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2239	AssertRC(rc);
2240	}
2241
2242	#ifdef DEBUG
2243	DBGFR3InfoLog(pVM, "mappings", NULL);
2244	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2245	#endif
2246
2247	/*
2248	* Switch mode back to real mode. (before resetting the pgm pool!)
2249	*/
2250	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2251	{
2252	PVMCPU pVCpu = &pVM->aCpus[i];
2253
2254	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2255	AssertRC(rc);
2256
2257	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2258	}
2259
2260	/*
2261	* Reset the shadow page pool.
2262	*/
2263	pgmR3PoolReset(pVM);
2264
2265	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2266	{
2267	PVMCPU pVCpu = &pVM->aCpus[i];
2268
2269	/*
2270	* Re-init other members.
2271	*/
2272	pVCpu->pgm.s.fA20Enabled = true;
2273
2274	/*
2275	* Clear the FFs PGM owns.
2276	*/
2277	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2278	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2279	}
2280
2281	/*
2282	* Reset (zero) RAM pages.
2283	*/
2284	rc = pgmR3PhysRamReset(pVM);
2285	if (RT_SUCCESS(rc))
2286	{
2287	/*
2288	* Reset (zero) shadow ROM pages.
2289	*/
2290	rc = pgmR3PhysRomReset(pVM);
2291	}
2292
2293	pgmUnlock(pVM);
2294	//return rc;
2295	AssertReleaseRC(rc);
2296	}
2297
2298
2299	#ifdef VBOX_STRICT
2300	/**
2301	* VM state change callback for clearing fNoMorePhysWrites after
2302	* a snapshot has been created.
2303	*/
2304	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2305	{
2306	if ( enmState == VMSTATE_RUNNING
2307	\|\| enmState == VMSTATE_RESUMING)
2308	pVM->pgm.s.fNoMorePhysWrites = false;
2309	}
2310	#endif
2311
2312
2313	/**
2314	* Terminates the PGM.
2315	*
2316	* @returns VBox status code.
2317	* @param pVM Pointer to VM structure.
2318	*/
2319	VMMR3DECL(int) PGMR3Term(PVM pVM)
2320	{
2321	PGMDeregisterStringFormatTypes();
2322	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2323	}
2324
2325
2326	/**
2327	* Terminates the per-VCPU PGM.
2328	*
2329	* Termination means cleaning up and freeing all resources,
2330	* the VM it self is at this point powered off or suspended.
2331	*
2332	* @returns VBox status code.
2333	* @param pVM The VM to operate on.
2334	*/
2335	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2336	{
2337	return 0;
2338	}
2339
2340
2341	/**
2342	* Show paging mode.
2343	*
2344	* @param pVM VM Handle.
2345	* @param pHlp The info helpers.
2346	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2347	*/
2348	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2349	{
2350	/* digest argument. */
2351	bool fGuest, fShadow, fHost;
2352	if (pszArgs)
2353	pszArgs = RTStrStripL(pszArgs);
2354	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2355	fShadow = fHost = fGuest = true;
2356	else
2357	{
2358	fShadow = fHost = fGuest = false;
2359	if (strstr(pszArgs, "guest"))
2360	fGuest = true;
2361	if (strstr(pszArgs, "shadow"))
2362	fShadow = true;
2363	if (strstr(pszArgs, "host"))
2364	fHost = true;
2365	}
2366
2367	/** @todo SMP support! */
2368	/* print info. */
2369	if (fGuest)
2370	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2371	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2372	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2373	if (fShadow)
2374	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2375	if (fHost)
2376	{
2377	const char *psz;
2378	switch (pVM->pgm.s.enmHostMode)
2379	{
2380	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2381	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2382	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2383	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2384	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2385	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2386	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2387	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2388	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2389	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2390	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2391	default: psz = "unknown"; break;
2392	}
2393	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2394	}
2395	}
2396
2397
2398	/**
2399	* Dump registered MMIO ranges to the log.
2400	*
2401	* @param pVM VM Handle.
2402	* @param pHlp The info helpers.
2403	* @param pszArgs Arguments, ignored.
2404	*/
2405	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2406	{
2407	NOREF(pszArgs);
2408	pHlp->pfnPrintf(pHlp,
2409	"RAM ranges (pVM=%p)\n"
2410	"%.s %.s\n",
2411	pVM,
2412	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2413	sizeof(RTHCPTR) * 2, "pvHC ");
2414
2415	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2416	pHlp->pfnPrintf(pHlp,
2417	"%RGp-%RGp %RHv %s\n",
2418	pCur->GCPhys,
2419	pCur->GCPhysLast,
2420	pCur->pvR3,
2421	pCur->pszDesc);
2422	}
2423
2424	/**
2425	* Dump the page directory to the log.
2426	*
2427	* @param pVM VM Handle.
2428	* @param pHlp The info helpers.
2429	* @param pszArgs Arguments, ignored.
2430	*/
2431	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2432	{
2433	/** @todo SMP support!! */
2434	PVMCPU pVCpu = &pVM->aCpus[0];
2435
2436	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2437	/* Big pages supported? */
2438	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2439
2440	/* Global pages supported? */
2441	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2442
2443	NOREF(pszArgs);
2444
2445	/*
2446	* Get page directory addresses.
2447	*/
2448	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2449	Assert(pPDSrc);
2450	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2451
2452	/*
2453	* Iterate the page directory.
2454	*/
2455	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2456	{
2457	X86PDE PdeSrc = pPDSrc->a[iPD];
2458	if (PdeSrc.n.u1Present)
2459	{
2460	if (PdeSrc.b.u1Size && fPSE)
2461	pHlp->pfnPrintf(pHlp,
2462	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2463	iPD,
2464	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2465	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2466	else
2467	pHlp->pfnPrintf(pHlp,
2468	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2469	iPD,
2470	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2471	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2472	}
2473	}
2474	}
2475
2476
2477	/**
2478	* Service a VMMCALLRING3_PGM_LOCK call.
2479	*
2480	* @returns VBox status code.
2481	* @param pVM The VM handle.
2482	*/
2483	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2484	{
2485	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2486	AssertRC(rc);
2487	return rc;
2488	}
2489
2490
2491	/**
2492	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2493	*
2494	* @returns PGM_TYPE_*.
2495	* @param pgmMode The mode value to convert.
2496	*/
2497	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2498	{
2499	switch (pgmMode)
2500	{
2501	case PGMMODE_REAL: return PGM_TYPE_REAL;
2502	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2503	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2504	case PGMMODE_PAE:
2505	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2506	case PGMMODE_AMD64:
2507	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2508	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2509	case PGMMODE_EPT: return PGM_TYPE_EPT;
2510	default:
2511	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2512	}
2513	}
2514
2515
2516	/**
2517	* Gets the index into the paging mode data array of a SHW+GST mode.
2518	*
2519	* @returns PGM::paPagingData index.
2520	* @param uShwType The shadow paging mode type.
2521	* @param uGstType The guest paging mode type.
2522	*/
2523	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2524	{
2525	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2526	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2527	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2528	+ (uGstType - PGM_TYPE_REAL);
2529	}
2530
2531
2532	/**
2533	* Gets the index into the paging mode data array of a SHW+GST mode.
2534	*
2535	* @returns PGM::paPagingData index.
2536	* @param enmShw The shadow paging mode.
2537	* @param enmGst The guest paging mode.
2538	*/
2539	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2540	{
2541	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2542	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2543	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2544	}
2545
2546
2547	/**
2548	* Calculates the max data index.
2549	* @returns The number of entries in the paging data array.
2550	*/
2551	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2552	{
2553	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2554	}
2555
2556
2557	/**
2558	* Initializes the paging mode data kept in PGM::paModeData.
2559	*
2560	* @param pVM The VM handle.
2561	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2562	* This is used early in the init process to avoid trouble with PDM
2563	* not being initialized yet.
2564	*/
2565	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2566	{
2567	PPGMMODEDATA pModeData;
2568	int rc;
2569
2570	/*
2571	* Allocate the array on the first call.
2572	*/
2573	if (!pVM->pgm.s.paModeData)
2574	{
2575	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2576	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2577	}
2578
2579	/*
2580	* Initialize the array entries.
2581	*/
2582	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2583	pModeData->uShwType = PGM_TYPE_32BIT;
2584	pModeData->uGstType = PGM_TYPE_REAL;
2585	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2586	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2587	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2588
2589	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2590	pModeData->uShwType = PGM_TYPE_32BIT;
2591	pModeData->uGstType = PGM_TYPE_PROT;
2592	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2593	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2594	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2595
2596	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2597	pModeData->uShwType = PGM_TYPE_32BIT;
2598	pModeData->uGstType = PGM_TYPE_32BIT;
2599	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2600	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2601	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2602
2603	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2604	pModeData->uShwType = PGM_TYPE_PAE;
2605	pModeData->uGstType = PGM_TYPE_REAL;
2606	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2607	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2608	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2609
2610	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2611	pModeData->uShwType = PGM_TYPE_PAE;
2612	pModeData->uGstType = PGM_TYPE_PROT;
2613	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2614	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2615	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2616
2617	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2618	pModeData->uShwType = PGM_TYPE_PAE;
2619	pModeData->uGstType = PGM_TYPE_32BIT;
2620	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2621	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2622	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2623
2624	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2625	pModeData->uShwType = PGM_TYPE_PAE;
2626	pModeData->uGstType = PGM_TYPE_PAE;
2627	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2628	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2629	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2630
2631	#ifdef VBOX_WITH_64_BITS_GUESTS
2632	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2633	pModeData->uShwType = PGM_TYPE_AMD64;
2634	pModeData->uGstType = PGM_TYPE_AMD64;
2635	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2636	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2637	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2638	#endif
2639
2640	/* The nested paging mode. */
2641	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2642	pModeData->uShwType = PGM_TYPE_NESTED;
2643	pModeData->uGstType = PGM_TYPE_REAL;
2644	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2645	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2646
2647	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2648	pModeData->uShwType = PGM_TYPE_NESTED;
2649	pModeData->uGstType = PGM_TYPE_PROT;
2650	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2651	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2652
2653	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2654	pModeData->uShwType = PGM_TYPE_NESTED;
2655	pModeData->uGstType = PGM_TYPE_32BIT;
2656	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2657	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2658
2659	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2660	pModeData->uShwType = PGM_TYPE_NESTED;
2661	pModeData->uGstType = PGM_TYPE_PAE;
2662	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2663	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2664
2665	#ifdef VBOX_WITH_64_BITS_GUESTS
2666	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2667	pModeData->uShwType = PGM_TYPE_NESTED;
2668	pModeData->uGstType = PGM_TYPE_AMD64;
2669	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2670	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2671	#endif
2672
2673	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2674	switch (pVM->pgm.s.enmHostMode)
2675	{
2676	#if HC_ARCH_BITS == 32
2677	case SUPPAGINGMODE_32_BIT:
2678	case SUPPAGINGMODE_32_BIT_GLOBAL:
2679	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2680	{
2681	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2682	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2683	}
2684	# ifdef VBOX_WITH_64_BITS_GUESTS
2685	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2686	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2687	# endif
2688	break;
2689
2690	case SUPPAGINGMODE_PAE:
2691	case SUPPAGINGMODE_PAE_NX:
2692	case SUPPAGINGMODE_PAE_GLOBAL:
2693	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2694	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2695	{
2696	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2697	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2698	}
2699	# ifdef VBOX_WITH_64_BITS_GUESTS
2700	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2701	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2702	# endif
2703	break;
2704	#endif /* HC_ARCH_BITS == 32 */
2705
2706	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2707	case SUPPAGINGMODE_AMD64:
2708	case SUPPAGINGMODE_AMD64_GLOBAL:
2709	case SUPPAGINGMODE_AMD64_NX:
2710	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2711	# ifdef VBOX_WITH_64_BITS_GUESTS
2712	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2713	# else
2714	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2715	# endif
2716	{
2717	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2718	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2719	}
2720	break;
2721	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2722
2723	default:
2724	AssertFailed();
2725	break;
2726	}
2727
2728	/* Extended paging (EPT) / Intel VT-x */
2729	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2730	pModeData->uShwType = PGM_TYPE_EPT;
2731	pModeData->uGstType = PGM_TYPE_REAL;
2732	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2733	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2734	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2735
2736	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2737	pModeData->uShwType = PGM_TYPE_EPT;
2738	pModeData->uGstType = PGM_TYPE_PROT;
2739	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2740	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2741	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2742
2743	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2744	pModeData->uShwType = PGM_TYPE_EPT;
2745	pModeData->uGstType = PGM_TYPE_32BIT;
2746	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2747	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2748	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2749
2750	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2751	pModeData->uShwType = PGM_TYPE_EPT;
2752	pModeData->uGstType = PGM_TYPE_PAE;
2753	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2756
2757	#ifdef VBOX_WITH_64_BITS_GUESTS
2758	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2759	pModeData->uShwType = PGM_TYPE_EPT;
2760	pModeData->uGstType = PGM_TYPE_AMD64;
2761	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2762	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2763	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2764	#endif
2765	return VINF_SUCCESS;
2766	}
2767
2768
2769	/**
2770	* Switch to different (or relocated in the relocate case) mode data.
2771	*
2772	* @param pVM The VM handle.
2773	* @param pVCpu The VMCPU to operate on.
2774	* @param enmShw The the shadow paging mode.
2775	* @param enmGst The the guest paging mode.
2776	*/
2777	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2778	{
2779	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2780
2781	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2782	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2783
2784	/* shadow */
2785	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2786	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2787	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2788	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2789	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2790
2791	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2792	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2793
2794	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2795	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2796
2797
2798	/* guest */
2799	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2800	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2801	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2802	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2803	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2804	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2805	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2806	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2807	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2808	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2809	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2810	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2811
2812	/* both */
2813	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2814	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2815	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2816	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2817	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2818	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2819	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2820	#ifdef VBOX_STRICT
2821	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2822	#endif
2823	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2824	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2825
2826	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2827	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2828	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2829	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2830	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2831	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2832	#ifdef VBOX_STRICT
2833	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2834	#endif
2835	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2836	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2837
2838	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2839	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2840	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2841	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2842	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2843	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2844	#ifdef VBOX_STRICT
2845	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2846	#endif
2847	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2848	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
2849	}
2850
2851
2852	/**
2853	* Calculates the shadow paging mode.
2854	*
2855	* @returns The shadow paging mode.
2856	* @param pVM VM handle.
2857	* @param enmGuestMode The guest mode.
2858	* @param enmHostMode The host mode.
2859	* @param enmShadowMode The current shadow mode.
2860	* @param penmSwitcher Where to store the switcher to use.
2861	* VMMSWITCHER_INVALID means no change.
2862	*/
2863	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2864	{
2865	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2866	switch (enmGuestMode)
2867	{
2868	/*
2869	* When switching to real or protected mode we don't change
2870	* anything since it's likely that we'll switch back pretty soon.
2871	*
2872	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2873	* and is supposed to determine which shadow paging and switcher to
2874	* use during init.
2875	*/
2876	case PGMMODE_REAL:
2877	case PGMMODE_PROTECTED:
2878	if ( enmShadowMode != PGMMODE_INVALID
2879	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2880	break; /* (no change) */
2881
2882	switch (enmHostMode)
2883	{
2884	case SUPPAGINGMODE_32_BIT:
2885	case SUPPAGINGMODE_32_BIT_GLOBAL:
2886	enmShadowMode = PGMMODE_32_BIT;
2887	enmSwitcher = VMMSWITCHER_32_TO_32;
2888	break;
2889
2890	case SUPPAGINGMODE_PAE:
2891	case SUPPAGINGMODE_PAE_NX:
2892	case SUPPAGINGMODE_PAE_GLOBAL:
2893	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2894	enmShadowMode = PGMMODE_PAE;
2895	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2896	#ifdef DEBUG_bird
2897	if (RTEnvExist("VBOX_32BIT"))
2898	{
2899	enmShadowMode = PGMMODE_32_BIT;
2900	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2901	}
2902	#endif
2903	break;
2904
2905	case SUPPAGINGMODE_AMD64:
2906	case SUPPAGINGMODE_AMD64_GLOBAL:
2907	case SUPPAGINGMODE_AMD64_NX:
2908	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2909	enmShadowMode = PGMMODE_PAE;
2910	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2911	#ifdef DEBUG_bird
2912	if (RTEnvExist("VBOX_32BIT"))
2913	{
2914	enmShadowMode = PGMMODE_32_BIT;
2915	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2916	}
2917	#endif
2918	break;
2919
2920	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2921	}
2922	break;
2923
2924	case PGMMODE_32_BIT:
2925	switch (enmHostMode)
2926	{
2927	case SUPPAGINGMODE_32_BIT:
2928	case SUPPAGINGMODE_32_BIT_GLOBAL:
2929	enmShadowMode = PGMMODE_32_BIT;
2930	enmSwitcher = VMMSWITCHER_32_TO_32;
2931	break;
2932
2933	case SUPPAGINGMODE_PAE:
2934	case SUPPAGINGMODE_PAE_NX:
2935	case SUPPAGINGMODE_PAE_GLOBAL:
2936	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2937	enmShadowMode = PGMMODE_PAE;
2938	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2939	#ifdef DEBUG_bird
2940	if (RTEnvExist("VBOX_32BIT"))
2941	{
2942	enmShadowMode = PGMMODE_32_BIT;
2943	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2944	}
2945	#endif
2946	break;
2947
2948	case SUPPAGINGMODE_AMD64:
2949	case SUPPAGINGMODE_AMD64_GLOBAL:
2950	case SUPPAGINGMODE_AMD64_NX:
2951	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2952	enmShadowMode = PGMMODE_PAE;
2953	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2954	#ifdef DEBUG_bird
2955	if (RTEnvExist("VBOX_32BIT"))
2956	{
2957	enmShadowMode = PGMMODE_32_BIT;
2958	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2959	}
2960	#endif
2961	break;
2962
2963	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2964	}
2965	break;
2966
2967	case PGMMODE_PAE:
2968	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2969	switch (enmHostMode)
2970	{
2971	case SUPPAGINGMODE_32_BIT:
2972	case SUPPAGINGMODE_32_BIT_GLOBAL:
2973	enmShadowMode = PGMMODE_PAE;
2974	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2975	break;
2976
2977	case SUPPAGINGMODE_PAE:
2978	case SUPPAGINGMODE_PAE_NX:
2979	case SUPPAGINGMODE_PAE_GLOBAL:
2980	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2981	enmShadowMode = PGMMODE_PAE;
2982	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2983	break;
2984
2985	case SUPPAGINGMODE_AMD64:
2986	case SUPPAGINGMODE_AMD64_GLOBAL:
2987	case SUPPAGINGMODE_AMD64_NX:
2988	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2989	enmShadowMode = PGMMODE_PAE;
2990	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2991	break;
2992
2993	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2994	}
2995	break;
2996
2997	case PGMMODE_AMD64:
2998	case PGMMODE_AMD64_NX:
2999	switch (enmHostMode)
3000	{
3001	case SUPPAGINGMODE_32_BIT:
3002	case SUPPAGINGMODE_32_BIT_GLOBAL:
3003	enmShadowMode = PGMMODE_AMD64;
3004	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3005	break;
3006
3007	case SUPPAGINGMODE_PAE:
3008	case SUPPAGINGMODE_PAE_NX:
3009	case SUPPAGINGMODE_PAE_GLOBAL:
3010	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3011	enmShadowMode = PGMMODE_AMD64;
3012	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3013	break;
3014
3015	case SUPPAGINGMODE_AMD64:
3016	case SUPPAGINGMODE_AMD64_GLOBAL:
3017	case SUPPAGINGMODE_AMD64_NX:
3018	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3019	enmShadowMode = PGMMODE_AMD64;
3020	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3021	break;
3022
3023	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3024	}
3025	break;
3026
3027
3028	default:
3029	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3030	*penmSwitcher = VMMSWITCHER_INVALID;
3031	return PGMMODE_INVALID;
3032	}
3033	/* Override the shadow mode is nested paging is active. */
3034	if (HWACCMIsNestedPagingActive(pVM))
3035	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3036
3037	*penmSwitcher = enmSwitcher;
3038	return enmShadowMode;
3039	}
3040
3041
3042	/**
3043	* Performs the actual mode change.
3044	* This is called by PGMChangeMode and pgmR3InitPaging().
3045	*
3046	* @returns VBox status code. May suspend or power off the VM on error, but this
3047	* will trigger using FFs and not status codes.
3048	*
3049	* @param pVM VM handle.
3050	* @param pVCpu The VMCPU to operate on.
3051	* @param enmGuestMode The new guest mode. This is assumed to be different from
3052	* the current mode.
3053	*/
3054	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3055	{
3056	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3057	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3058
3059	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3060	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3061
3062	/*
3063	* Calc the shadow mode and switcher.
3064	*/
3065	VMMSWITCHER enmSwitcher;
3066	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3067	if (enmSwitcher != VMMSWITCHER_INVALID)
3068	{
3069	/*
3070	* Select new switcher.
3071	*/
3072	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3073	if (RT_FAILURE(rc))
3074	{
3075	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3076	return rc;
3077	}
3078	}
3079
3080	/*
3081	* Exit old mode(s).
3082	*/
3083	#if HC_ARCH_BITS == 32
3084	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3085	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3086	&& enmShadowMode == PGMMODE_NESTED);
3087	#else
3088	const bool fForceShwEnterExit = false;
3089	#endif
3090	/* shadow */
3091	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3092	\|\| fForceShwEnterExit)
3093	{
3094	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3095	if (PGM_SHW_PFN(Exit, pVCpu))
3096	{
3097	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3098	if (RT_FAILURE(rc))
3099	{
3100	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3101	return rc;
3102	}
3103	}
3104
3105	}
3106	else
3107	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3108
3109	/* guest */
3110	if (PGM_GST_PFN(Exit, pVCpu))
3111	{
3112	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3113	if (RT_FAILURE(rc))
3114	{
3115	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3116	return rc;
3117	}
3118	}
3119
3120	/*
3121	* Load new paging mode data.
3122	*/
3123	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3124
3125	/*
3126	* Enter new shadow mode (if changed).
3127	*/
3128	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3129	\|\| fForceShwEnterExit)
3130	{
3131	int rc;
3132	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3133	switch (enmShadowMode)
3134	{
3135	case PGMMODE_32_BIT:
3136	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3137	break;
3138	case PGMMODE_PAE:
3139	case PGMMODE_PAE_NX:
3140	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3141	break;
3142	case PGMMODE_AMD64:
3143	case PGMMODE_AMD64_NX:
3144	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3145	break;
3146	case PGMMODE_NESTED:
3147	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3148	break;
3149	case PGMMODE_EPT:
3150	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3151	break;
3152	case PGMMODE_REAL:
3153	case PGMMODE_PROTECTED:
3154	default:
3155	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3156	return VERR_INTERNAL_ERROR;
3157	}
3158	if (RT_FAILURE(rc))
3159	{
3160	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3161	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3162	return rc;
3163	}
3164	}
3165
3166	/*
3167	* Always flag the necessary updates
3168	*/
3169	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3170
3171	/*
3172	* Enter the new guest and shadow+guest modes.
3173	*/
3174	int rc = -1;
3175	int rc2 = -1;
3176	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3177	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3178	switch (enmGuestMode)
3179	{
3180	case PGMMODE_REAL:
3181	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3182	switch (pVCpu->pgm.s.enmShadowMode)
3183	{
3184	case PGMMODE_32_BIT:
3185	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3186	break;
3187	case PGMMODE_PAE:
3188	case PGMMODE_PAE_NX:
3189	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3190	break;
3191	case PGMMODE_NESTED:
3192	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3193	break;
3194	case PGMMODE_EPT:
3195	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3196	break;
3197	case PGMMODE_AMD64:
3198	case PGMMODE_AMD64_NX:
3199	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3200	default: AssertFailed(); break;
3201	}
3202	break;
3203
3204	case PGMMODE_PROTECTED:
3205	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3206	switch (pVCpu->pgm.s.enmShadowMode)
3207	{
3208	case PGMMODE_32_BIT:
3209	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3210	break;
3211	case PGMMODE_PAE:
3212	case PGMMODE_PAE_NX:
3213	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3214	break;
3215	case PGMMODE_NESTED:
3216	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3217	break;
3218	case PGMMODE_EPT:
3219	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3220	break;
3221	case PGMMODE_AMD64:
3222	case PGMMODE_AMD64_NX:
3223	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3224	default: AssertFailed(); break;
3225	}
3226	break;
3227
3228	case PGMMODE_32_BIT:
3229	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3230	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3231	switch (pVCpu->pgm.s.enmShadowMode)
3232	{
3233	case PGMMODE_32_BIT:
3234	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3235	break;
3236	case PGMMODE_PAE:
3237	case PGMMODE_PAE_NX:
3238	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3239	break;
3240	case PGMMODE_NESTED:
3241	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3242	break;
3243	case PGMMODE_EPT:
3244	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3245	break;
3246	case PGMMODE_AMD64:
3247	case PGMMODE_AMD64_NX:
3248	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3249	default: AssertFailed(); break;
3250	}
3251	break;
3252
3253	case PGMMODE_PAE_NX:
3254	case PGMMODE_PAE:
3255	{
3256	uint32_t u32Dummy, u32Features;
3257
3258	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3259	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3260	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3261	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3262
3263	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3264	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3265	switch (pVCpu->pgm.s.enmShadowMode)
3266	{
3267	case PGMMODE_PAE:
3268	case PGMMODE_PAE_NX:
3269	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3270	break;
3271	case PGMMODE_NESTED:
3272	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3273	break;
3274	case PGMMODE_EPT:
3275	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3276	break;
3277	case PGMMODE_32_BIT:
3278	case PGMMODE_AMD64:
3279	case PGMMODE_AMD64_NX:
3280	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3281	default: AssertFailed(); break;
3282	}
3283	break;
3284	}
3285
3286	#ifdef VBOX_WITH_64_BITS_GUESTS
3287	case PGMMODE_AMD64_NX:
3288	case PGMMODE_AMD64:
3289	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3290	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3291	switch (pVCpu->pgm.s.enmShadowMode)
3292	{
3293	case PGMMODE_AMD64:
3294	case PGMMODE_AMD64_NX:
3295	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3296	break;
3297	case PGMMODE_NESTED:
3298	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3299	break;
3300	case PGMMODE_EPT:
3301	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3302	break;
3303	case PGMMODE_32_BIT:
3304	case PGMMODE_PAE:
3305	case PGMMODE_PAE_NX:
3306	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3307	default: AssertFailed(); break;
3308	}
3309	break;
3310	#endif
3311
3312	default:
3313	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3314	rc = VERR_NOT_IMPLEMENTED;
3315	break;
3316	}
3317
3318	/* status codes. */
3319	AssertRC(rc);
3320	AssertRC(rc2);
3321	if (RT_SUCCESS(rc))
3322	{
3323	rc = rc2;
3324	if (RT_SUCCESS(rc)) /* no informational status codes. */
3325	rc = VINF_SUCCESS;
3326	}
3327
3328	/* Notify HWACCM as well. */
3329	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3330	return rc;
3331	}
3332
3333	/**
3334	* Release the pgm lock if owned by the current VCPU
3335	*
3336	* @param pVM The VM to operate on.
3337	*/
3338	VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
3339	{
3340	while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
3341	PDMCritSectLeave(&pVM->pgm.s.CritSect);
3342	}
3343
3344	/**
3345	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3346	*
3347	* @returns VBox status code, fully asserted.
3348	* @param pVM The VM handle.
3349	* @param pVCpu The VMCPU to operate on.
3350	*/
3351	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3352	{
3353	/* Unmap the old CR3 value before flushing everything. */
3354	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3355	AssertRC(rc);
3356
3357	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3358	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3359	AssertRC(rc);
3360	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3361	return rc;
3362	}
3363
3364
3365	/**
3366	* Called by pgmPoolFlushAllInt after flushing the pool.
3367	*
3368	* @returns VBox status code, fully asserted.
3369	* @param pVM The VM handle.
3370	* @param pVCpu The VMCPU to operate on.
3371	*/
3372	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3373	{
3374	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3375	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3376	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3377	AssertRCReturn(rc, rc);
3378	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3379
3380	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3381	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3382	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3383	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3384	return rc;
3385	}
3386
3387
3388	/**
3389	* Dumps a PAE shadow page table.
3390	*
3391	* @returns VBox status code (VINF_SUCCESS).
3392	* @param pVM The VM handle.
3393	* @param pPT Pointer to the page table.
3394	* @param u64Address The virtual address of the page table starts.
3395	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3396	* @param cMaxDepth The maxium depth.
3397	* @param pHlp Pointer to the output functions.
3398	*/
3399	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3400	{
3401	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3402	{
3403	X86PTEPAE Pte = pPT->a[i];
3404	if (Pte.n.u1Present)
3405	{
3406	pHlp->pfnPrintf(pHlp,
3407	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3408	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3409	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3410	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3411	Pte.n.u1Write ? 'W' : 'R',
3412	Pte.n.u1User ? 'U' : 'S',
3413	Pte.n.u1Accessed ? 'A' : '-',
3414	Pte.n.u1Dirty ? 'D' : '-',
3415	Pte.n.u1Global ? 'G' : '-',
3416	Pte.n.u1WriteThru ? "WT" : "--",
3417	Pte.n.u1CacheDisable? "CD" : "--",
3418	Pte.n.u1PAT ? "AT" : "--",
3419	Pte.n.u1NoExecute ? "NX" : "--",
3420	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3421	Pte.u & RT_BIT(10) ? '1' : '0',
3422	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3423	Pte.u & X86_PTE_PAE_PG_MASK);
3424	}
3425	}
3426	return VINF_SUCCESS;
3427	}
3428
3429
3430	/**
3431	* Dumps a PAE shadow page directory table.
3432	*
3433	* @returns VBox status code (VINF_SUCCESS).
3434	* @param pVM The VM handle.
3435	* @param HCPhys The physical address of the page directory table.
3436	* @param u64Address The virtual address of the page table starts.
3437	* @param cr4 The CR4, PSE is currently used.
3438	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3439	* @param cMaxDepth The maxium depth.
3440	* @param pHlp Pointer to the output functions.
3441	*/
3442	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3443	{
3444	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3445	if (!pPD)
3446	{
3447	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3448	fLongMode ? 16 : 8, u64Address, HCPhys);
3449	return VERR_INVALID_PARAMETER;
3450	}
3451	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3452
3453	int rc = VINF_SUCCESS;
3454	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3455	{
3456	X86PDEPAE Pde = pPD->a[i];
3457	if (Pde.n.u1Present)
3458	{
3459	if (fBigPagesSupported && Pde.b.u1Size)
3460	pHlp->pfnPrintf(pHlp,
3461	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3462	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3463	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3464	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3465	Pde.b.u1Write ? 'W' : 'R',
3466	Pde.b.u1User ? 'U' : 'S',
3467	Pde.b.u1Accessed ? 'A' : '-',
3468	Pde.b.u1Dirty ? 'D' : '-',
3469	Pde.b.u1Global ? 'G' : '-',
3470	Pde.b.u1WriteThru ? "WT" : "--",
3471	Pde.b.u1CacheDisable? "CD" : "--",
3472	Pde.b.u1PAT ? "AT" : "--",
3473	Pde.b.u1NoExecute ? "NX" : "--",
3474	Pde.u & RT_BIT_64(9) ? '1' : '0',
3475	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3476	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3477	Pde.u & X86_PDE_PAE_PG_MASK);
3478	else
3479	{
3480	pHlp->pfnPrintf(pHlp,
3481	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3482	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3483	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3484	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3485	Pde.n.u1Write ? 'W' : 'R',
3486	Pde.n.u1User ? 'U' : 'S',
3487	Pde.n.u1Accessed ? 'A' : '-',
3488	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3489	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3490	Pde.n.u1WriteThru ? "WT" : "--",
3491	Pde.n.u1CacheDisable? "CD" : "--",
3492	Pde.n.u1NoExecute ? "NX" : "--",
3493	Pde.u & RT_BIT_64(9) ? '1' : '0',
3494	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3495	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3496	Pde.u & X86_PDE_PAE_PG_MASK);
3497	if (cMaxDepth >= 1)
3498	{
3499	/** @todo what about using the page pool for mapping PTs? */
3500	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3501	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3502	PX86PTPAE pPT = NULL;
3503	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3504	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3505	else
3506	{
3507	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3508	{
3509	uint64_t off = u64AddressPT - pMap->GCPtr;
3510	if (off < pMap->cb)
3511	{
3512	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3513	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3514	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3515	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3516	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3517	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3518	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3519	}
3520	}
3521	}
3522	int rc2 = VERR_INVALID_PARAMETER;
3523	if (pPT)
3524	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3525	else
3526	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3527	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3528	if (rc2 < rc && RT_SUCCESS(rc))
3529	rc = rc2;
3530	}
3531	}
3532	}
3533	}
3534	return rc;
3535	}
3536
3537
3538	/**
3539	* Dumps a PAE shadow page directory pointer table.
3540	*
3541	* @returns VBox status code (VINF_SUCCESS).
3542	* @param pVM The VM handle.
3543	* @param HCPhys The physical address of the page directory pointer table.
3544	* @param u64Address The virtual address of the page table starts.
3545	* @param cr4 The CR4, PSE is currently used.
3546	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3547	* @param cMaxDepth The maxium depth.
3548	* @param pHlp Pointer to the output functions.
3549	*/
3550	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3551	{
3552	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3553	if (!pPDPT)
3554	{
3555	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3556	fLongMode ? 16 : 8, u64Address, HCPhys);
3557	return VERR_INVALID_PARAMETER;
3558	}
3559
3560	int rc = VINF_SUCCESS;
3561	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3562	for (unsigned i = 0; i < c; i++)
3563	{
3564	X86PDPE Pdpe = pPDPT->a[i];
3565	if (Pdpe.n.u1Present)
3566	{
3567	if (fLongMode)
3568	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3569	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3570	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3571	Pdpe.lm.u1Write ? 'W' : 'R',
3572	Pdpe.lm.u1User ? 'U' : 'S',
3573	Pdpe.lm.u1Accessed ? 'A' : '-',
3574	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3575	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3576	Pdpe.lm.u1WriteThru ? "WT" : "--",
3577	Pdpe.lm.u1CacheDisable? "CD" : "--",
3578	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3579	Pdpe.lm.u1NoExecute ? "NX" : "--",
3580	Pdpe.u & RT_BIT(9) ? '1' : '0',
3581	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3582	Pdpe.u & RT_BIT(11) ? '1' : '0',
3583	Pdpe.u & X86_PDPE_PG_MASK);
3584	else
3585	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3586	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3587	i << X86_PDPT_SHIFT,
3588	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3589	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3590	Pdpe.n.u1WriteThru ? "WT" : "--",
3591	Pdpe.n.u1CacheDisable? "CD" : "--",
3592	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3593	Pdpe.u & RT_BIT(9) ? '1' : '0',
3594	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3595	Pdpe.u & RT_BIT(11) ? '1' : '0',
3596	Pdpe.u & X86_PDPE_PG_MASK);
3597	if (cMaxDepth >= 1)
3598	{
3599	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3600	cr4, fLongMode, cMaxDepth - 1, pHlp);
3601	if (rc2 < rc && RT_SUCCESS(rc))
3602	rc = rc2;
3603	}
3604	}
3605	}
3606	return rc;
3607	}
3608
3609
3610	/**
3611	* Dumps a 32-bit shadow page table.
3612	*
3613	* @returns VBox status code (VINF_SUCCESS).
3614	* @param pVM The VM handle.
3615	* @param HCPhys The physical address of the table.
3616	* @param cr4 The CR4, PSE is currently used.
3617	* @param cMaxDepth The maxium depth.
3618	* @param pHlp Pointer to the output functions.
3619	*/
3620	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3621	{
3622	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3623	if (!pPML4)
3624	{
3625	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3626	return VERR_INVALID_PARAMETER;
3627	}
3628
3629	int rc = VINF_SUCCESS;
3630	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3631	{
3632	X86PML4E Pml4e = pPML4->a[i];
3633	if (Pml4e.n.u1Present)
3634	{
3635	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3636	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3637	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3638	u64Address,
3639	Pml4e.n.u1Write ? 'W' : 'R',
3640	Pml4e.n.u1User ? 'U' : 'S',
3641	Pml4e.n.u1Accessed ? 'A' : '-',
3642	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3643	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3644	Pml4e.n.u1WriteThru ? "WT" : "--",
3645	Pml4e.n.u1CacheDisable? "CD" : "--",
3646	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3647	Pml4e.n.u1NoExecute ? "NX" : "--",
3648	Pml4e.u & RT_BIT(9) ? '1' : '0',
3649	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3650	Pml4e.u & RT_BIT(11) ? '1' : '0',
3651	Pml4e.u & X86_PML4E_PG_MASK);
3652
3653	if (cMaxDepth >= 1)
3654	{
3655	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3656	if (rc2 < rc && RT_SUCCESS(rc))
3657	rc = rc2;
3658	}
3659	}
3660	}
3661	return rc;
3662	}
3663
3664
3665	/**
3666	* Dumps a 32-bit shadow page table.
3667	*
3668	* @returns VBox status code (VINF_SUCCESS).
3669	* @param pVM The VM handle.
3670	* @param pPT Pointer to the page table.
3671	* @param u32Address The virtual address this table starts at.
3672	* @param pHlp Pointer to the output functions.
3673	*/
3674	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3675	{
3676	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3677	{
3678	X86PTE Pte = pPT->a[i];
3679	if (Pte.n.u1Present)
3680	{
3681	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3682	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3683	u32Address + (i << X86_PT_SHIFT),
3684	Pte.n.u1Write ? 'W' : 'R',
3685	Pte.n.u1User ? 'U' : 'S',
3686	Pte.n.u1Accessed ? 'A' : '-',
3687	Pte.n.u1Dirty ? 'D' : '-',
3688	Pte.n.u1Global ? 'G' : '-',
3689	Pte.n.u1WriteThru ? "WT" : "--",
3690	Pte.n.u1CacheDisable? "CD" : "--",
3691	Pte.n.u1PAT ? "AT" : "--",
3692	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3693	Pte.u & RT_BIT(10) ? '1' : '0',
3694	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3695	Pte.u & X86_PDE_PG_MASK);
3696	}
3697	}
3698	return VINF_SUCCESS;
3699	}
3700
3701
3702	/**
3703	* Dumps a 32-bit shadow page directory and page tables.
3704	*
3705	* @returns VBox status code (VINF_SUCCESS).
3706	* @param pVM The VM handle.
3707	* @param cr3 The root of the hierarchy.
3708	* @param cr4 The CR4, PSE is currently used.
3709	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3710	* @param pHlp Pointer to the output functions.
3711	*/
3712	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3713	{
3714	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3715	if (!pPD)
3716	{
3717	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3718	return VERR_INVALID_PARAMETER;
3719	}
3720
3721	int rc = VINF_SUCCESS;
3722	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3723	{
3724	X86PDE Pde = pPD->a[i];
3725	if (Pde.n.u1Present)
3726	{
3727	const uint32_t u32Address = i << X86_PD_SHIFT;
3728	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3729	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3730	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3731	u32Address,
3732	Pde.b.u1Write ? 'W' : 'R',
3733	Pde.b.u1User ? 'U' : 'S',
3734	Pde.b.u1Accessed ? 'A' : '-',
3735	Pde.b.u1Dirty ? 'D' : '-',
3736	Pde.b.u1Global ? 'G' : '-',
3737	Pde.b.u1WriteThru ? "WT" : "--",
3738	Pde.b.u1CacheDisable? "CD" : "--",
3739	Pde.b.u1PAT ? "AT" : "--",
3740	Pde.u & RT_BIT_64(9) ? '1' : '0',
3741	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3742	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3743	Pde.u & X86_PDE4M_PG_MASK);
3744	else
3745	{
3746	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3747	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3748	u32Address,
3749	Pde.n.u1Write ? 'W' : 'R',
3750	Pde.n.u1User ? 'U' : 'S',
3751	Pde.n.u1Accessed ? 'A' : '-',
3752	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3753	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3754	Pde.n.u1WriteThru ? "WT" : "--",
3755	Pde.n.u1CacheDisable? "CD" : "--",
3756	Pde.u & RT_BIT_64(9) ? '1' : '0',
3757	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3758	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3759	Pde.u & X86_PDE_PG_MASK);
3760	if (cMaxDepth >= 1)
3761	{
3762	/** @todo what about using the page pool for mapping PTs? */
3763	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3764	PX86PT pPT = NULL;
3765	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3766	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3767	else
3768	{
3769	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3770	if (u32Address - pMap->GCPtr < pMap->cb)
3771	{
3772	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3773	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3774	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3775	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3776	pPT = pMap->aPTs[iPDE].pPTR3;
3777	}
3778	}
3779	int rc2 = VERR_INVALID_PARAMETER;
3780	if (pPT)
3781	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3782	else
3783	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3784	if (rc2 < rc && RT_SUCCESS(rc))
3785	rc = rc2;
3786	}
3787	}
3788	}
3789	}
3790
3791	return rc;
3792	}
3793
3794
3795	/**
3796	* Dumps a 32-bit shadow page table.
3797	*
3798	* @returns VBox status code (VINF_SUCCESS).
3799	* @param pVM The VM handle.
3800	* @param pPT Pointer to the page table.
3801	* @param u32Address The virtual address this table starts at.
3802	* @param PhysSearch Address to search for.
3803	*/
3804	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3805	{
3806	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3807	{
3808	X86PTE Pte = pPT->a[i];
3809	if (Pte.n.u1Present)
3810	{
3811	Log(( /P R S A D G WT CD AT NX 4M a m d /
3812	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3813	u32Address + (i << X86_PT_SHIFT),
3814	Pte.n.u1Write ? 'W' : 'R',
3815	Pte.n.u1User ? 'U' : 'S',
3816	Pte.n.u1Accessed ? 'A' : '-',
3817	Pte.n.u1Dirty ? 'D' : '-',
3818	Pte.n.u1Global ? 'G' : '-',
3819	Pte.n.u1WriteThru ? "WT" : "--",
3820	Pte.n.u1CacheDisable? "CD" : "--",
3821	Pte.n.u1PAT ? "AT" : "--",
3822	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3823	Pte.u & RT_BIT(10) ? '1' : '0',
3824	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3825	Pte.u & X86_PDE_PG_MASK));
3826
3827	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3828	{
3829	uint64_t fPageShw = 0;
3830	RTHCPHYS pPhysHC = 0;
3831
3832	/** @todo SMP support!! */
3833	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3834	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3835	}
3836	}
3837	}
3838	return VINF_SUCCESS;
3839	}
3840
3841
3842	/**
3843	* Dumps a 32-bit guest page directory and page tables.
3844	*
3845	* @returns VBox status code (VINF_SUCCESS).
3846	* @param pVM The VM handle.
3847	* @param cr3 The root of the hierarchy.
3848	* @param cr4 The CR4, PSE is currently used.
3849	* @param PhysSearch Address to search for.
3850	*/
3851	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3852	{
3853	bool fLongMode = false;
3854	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3855	PX86PD pPD = 0;
3856
3857	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3858	if (RT_FAILURE(rc) \|\| !pPD)
3859	{
3860	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3861	return VERR_INVALID_PARAMETER;
3862	}
3863
3864	Log(("cr3=%08x cr4=%08x%s\n"
3865	"%-*s P - Present\n"
3866	"%-*s \| R/W - Read (0) / Write (1)\n"
3867	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3868	"%-*s \| \| \| A - Accessed\n"
3869	"%-*s \| \| \| \| D - Dirty\n"
3870	"%-*s \| \| \| \| \| G - Global\n"
3871	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3872	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3873	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3874	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3875	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3876	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3877	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3878	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3879	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3880	- W U - - - -- -- -- -- -- 010 */
3881	, cr3, cr4, fLongMode ? " Long Mode" : "",
3882	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3883	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3884
3885	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3886	{
3887	X86PDE Pde = pPD->a[i];
3888	if (Pde.n.u1Present)
3889	{
3890	const uint32_t u32Address = i << X86_PD_SHIFT;
3891
3892	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3893	Log(( /P R S A D G WT CD AT NX 4M a m d /
3894	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3895	u32Address,
3896	Pde.b.u1Write ? 'W' : 'R',
3897	Pde.b.u1User ? 'U' : 'S',
3898	Pde.b.u1Accessed ? 'A' : '-',
3899	Pde.b.u1Dirty ? 'D' : '-',
3900	Pde.b.u1Global ? 'G' : '-',
3901	Pde.b.u1WriteThru ? "WT" : "--",
3902	Pde.b.u1CacheDisable? "CD" : "--",
3903	Pde.b.u1PAT ? "AT" : "--",
3904	Pde.u & RT_BIT(9) ? '1' : '0',
3905	Pde.u & RT_BIT(10) ? '1' : '0',
3906	Pde.u & RT_BIT(11) ? '1' : '0',
3907	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3908	/** @todo PhysSearch */
3909	else
3910	{
3911	Log(( /P R S A D G WT CD AT NX 4M a m d /
3912	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3913	u32Address,
3914	Pde.n.u1Write ? 'W' : 'R',
3915	Pde.n.u1User ? 'U' : 'S',
3916	Pde.n.u1Accessed ? 'A' : '-',
3917	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3918	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3919	Pde.n.u1WriteThru ? "WT" : "--",
3920	Pde.n.u1CacheDisable? "CD" : "--",
3921	Pde.u & RT_BIT(9) ? '1' : '0',
3922	Pde.u & RT_BIT(10) ? '1' : '0',
3923	Pde.u & RT_BIT(11) ? '1' : '0',
3924	Pde.u & X86_PDE_PG_MASK));
3925	////if (cMaxDepth >= 1)
3926	{
3927	/** @todo what about using the page pool for mapping PTs? */
3928	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3929	PX86PT pPT = NULL;
3930
3931	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3932
3933	int rc2 = VERR_INVALID_PARAMETER;
3934	if (pPT)
3935	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3936	else
3937	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3938	if (rc2 < rc && RT_SUCCESS(rc))
3939	rc = rc2;
3940	}
3941	}
3942	}
3943	}
3944
3945	return rc;
3946	}
3947
3948
3949	/**
3950	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3951	*
3952	* @returns VBox status code (VINF_SUCCESS).
3953	* @param pVM The VM handle.
3954	* @param cr3 The root of the hierarchy.
3955	* @param cr4 The cr4, only PAE and PSE is currently used.
3956	* @param fLongMode Set if long mode, false if not long mode.
3957	* @param cMaxDepth Number of levels to dump.
3958	* @param pHlp Pointer to the output functions.
3959	*/
3960	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3961	{
3962	if (!pHlp)
3963	pHlp = DBGFR3InfoLogHlp();
3964	if (!cMaxDepth)
3965	return VINF_SUCCESS;
3966	const unsigned cch = fLongMode ? 16 : 8;
3967	pHlp->pfnPrintf(pHlp,
3968	"cr3=%08x cr4=%08x%s\n"
3969	"%-*s P - Present\n"
3970	"%-*s \| R/W - Read (0) / Write (1)\n"
3971	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3972	"%-*s \| \| \| A - Accessed\n"
3973	"%-*s \| \| \| \| D - Dirty\n"
3974	"%-*s \| \| \| \| \| G - Global\n"
3975	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3976	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3977	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3978	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3979	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3980	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3981	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3982	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3983	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3984	- W U - - - -- -- -- -- -- 010 */
3985	, cr3, cr4, fLongMode ? " Long Mode" : "",
3986	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3987	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3988	if (cr4 & X86_CR4_PAE)
3989	{
3990	if (fLongMode)
3991	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3992	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3993	}
3994	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3995	}
3996
3997	#ifdef VBOX_WITH_DEBUGGER
3998
3999	/**
4000	* The '.pgmram' command.
4001	*
4002	* @returns VBox status.
4003	* @param pCmd Pointer to the command descriptor (as registered).
4004	* @param pCmdHlp Pointer to command helper functions.
4005	* @param pVM Pointer to the current VM (if any).
4006	* @param paArgs Pointer to (readonly) array of arguments.
4007	* @param cArgs Number of arguments in the array.
4008	*/
4009	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4010	{
4011	/*
4012	* Validate input.
4013	*/
4014	if (!pVM)
4015	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4016	if (!pVM->pgm.s.pRamRangesRC)
4017	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4018
4019	/*
4020	* Dump the ranges.
4021	*/
4022	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4023	PPGMRAMRANGE pRam;
4024	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4025	{
4026	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4027	"%RGp - %RGp %p\n",
4028	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4029	if (RT_FAILURE(rc))
4030	return rc;
4031	}
4032
4033	return VINF_SUCCESS;
4034	}
4035
4036
4037	/**
4038	* The '.pgmerror' and '.pgmerroroff' commands.
4039	*
4040	* @returns VBox status.
4041	* @param pCmd Pointer to the command descriptor (as registered).
4042	* @param pCmdHlp Pointer to command helper functions.
4043	* @param pVM Pointer to the current VM (if any).
4044	* @param paArgs Pointer to (readonly) array of arguments.
4045	* @param cArgs Number of arguments in the array.
4046	*/
4047	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4048	{
4049	/*
4050	* Validate input.
4051	*/
4052	if (!pVM)
4053	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4054	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4055	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4056
4057	if (!cArgs)
4058	{
4059	/*
4060	* Print the list of error injection locations with status.
4061	*/
4062	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4063	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4064	}
4065	else
4066	{
4067
4068	/*
4069	* String switch on where to inject the error.
4070	*/
4071	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4072	const char *pszWhere = paArgs[0].u.pszString;
4073	if (!strcmp(pszWhere, "handy"))
4074	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4075	else
4076	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4077	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4078	}
4079	return VINF_SUCCESS;
4080	}
4081
4082
4083	/**
4084	* The '.pgmsync' command.
4085	*
4086	* @returns VBox status.
4087	* @param pCmd Pointer to the command descriptor (as registered).
4088	* @param pCmdHlp Pointer to command helper functions.
4089	* @param pVM Pointer to the current VM (if any).
4090	* @param paArgs Pointer to (readonly) array of arguments.
4091	* @param cArgs Number of arguments in the array.
4092	*/
4093	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4094	{
4095	/** @todo SMP support */
4096	PVMCPU pVCpu = &pVM->aCpus[0];
4097
4098	/*
4099	* Validate input.
4100	*/
4101	if (!pVM)
4102	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4103
4104	/*
4105	* Force page directory sync.
4106	*/
4107	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4108
4109	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4110	if (RT_FAILURE(rc))
4111	return rc;
4112
4113	return VINF_SUCCESS;
4114	}
4115
4116
4117	#ifdef VBOX_STRICT
4118	/**
4119	* The '.pgmassertcr3' command.
4120	*
4121	* @returns VBox status.
4122	* @param pCmd Pointer to the command descriptor (as registered).
4123	* @param pCmdHlp Pointer to command helper functions.
4124	* @param pVM Pointer to the current VM (if any).
4125	* @param paArgs Pointer to (readonly) array of arguments.
4126	* @param cArgs Number of arguments in the array.
4127	*/
4128	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4129	{
4130	/** @todo SMP support!! */
4131	PVMCPU pVCpu = &pVM->aCpus[0];
4132
4133	/*
4134	* Validate input.
4135	*/
4136	if (!pVM)
4137	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4138
4139	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4140	if (RT_FAILURE(rc))
4141	return rc;
4142
4143	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4144
4145	return VINF_SUCCESS;
4146	}
4147	#endif /* VBOX_STRICT */
4148
4149
4150	/**
4151	* The '.pgmsyncalways' command.
4152	*
4153	* @returns VBox status.
4154	* @param pCmd Pointer to the command descriptor (as registered).
4155	* @param pCmdHlp Pointer to command helper functions.
4156	* @param pVM Pointer to the current VM (if any).
4157	* @param paArgs Pointer to (readonly) array of arguments.
4158	* @param cArgs Number of arguments in the array.
4159	*/
4160	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4161	{
4162	/** @todo SMP support!! */
4163	PVMCPU pVCpu = &pVM->aCpus[0];
4164
4165	/*
4166	* Validate input.
4167	*/
4168	if (!pVM)
4169	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4170
4171	/*
4172	* Force page directory sync.
4173	*/
4174	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4175	{
4176	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4177	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4178	}
4179	else
4180	{
4181	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4182	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4183	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4184	}
4185	}
4186
4187
4188	/**
4189	* The '.pgmsyncalways' command.
4190	*
4191	* @returns VBox status.
4192	* @param pCmd Pointer to the command descriptor (as registered).
4193	* @param pCmdHlp Pointer to command helper functions.
4194	* @param pVM Pointer to the current VM (if any).
4195	* @param paArgs Pointer to (readonly) array of arguments.
4196	* @param cArgs Number of arguments in the array.
4197	*/
4198	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4199	{
4200	/*
4201	* Validate input.
4202	*/
4203	if (!pVM)
4204	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4205	if ( cArgs < 1
4206	\|\| cArgs > 2
4207	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4208	\|\| ( cArgs > 1
4209	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4210	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4211	if ( cArgs >= 2
4212	&& strcmp(paArgs[1].u.pszString, "nozero"))
4213	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4214	bool fIncZeroPgs = cArgs < 2;
4215
4216	/*
4217	* Open the output file and get the ram parameters.
4218	*/
4219	RTFILE hFile;
4220	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
4221	if (RT_FAILURE(rc))
4222	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4223
4224	uint32_t cbRamHole = 0;
4225	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4226	uint64_t cbRam = 0;
4227	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4228	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4229
4230	/*
4231	* Dump the physical memory, page by page.
4232	*/
4233	RTGCPHYS GCPhys = 0;
4234	char abZeroPg[PAGE_SIZE];
4235	RT_ZERO(abZeroPg);
4236
4237	pgmLock(pVM);
4238	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4239	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4240	pRam = pRam->pNextR3)
4241	{
4242	/* fill the gap */
4243	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4244	{
4245	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4246	{
4247	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4248	GCPhys += PAGE_SIZE;
4249	}
4250	}
4251
4252	PCPGMPAGE pPage = &pRam->aPages[0];
4253	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4254	{
4255	if (PGM_PAGE_IS_ZERO(pPage))
4256	{
4257	if (fIncZeroPgs)
4258	{
4259	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4260	if (RT_FAILURE(rc))
4261	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4262	}
4263	}
4264	else
4265	{
4266	switch (PGM_PAGE_GET_TYPE(pPage))
4267	{
4268	case PGMPAGETYPE_RAM:
4269	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4270	case PGMPAGETYPE_ROM:
4271	case PGMPAGETYPE_MMIO2:
4272	{
4273	void const *pvPage;
4274	PGMPAGEMAPLOCK Lock;
4275	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4276	if (RT_SUCCESS(rc))
4277	{
4278	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4279	PGMPhysReleasePageMappingLock(pVM, &Lock);
4280	if (RT_FAILURE(rc))
4281	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4282	}
4283	else
4284	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4285	break;
4286	}
4287
4288	default:
4289	AssertFailed();
4290	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4291	case PGMPAGETYPE_MMIO:
4292	if (fIncZeroPgs)
4293	{
4294	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4295	if (RT_FAILURE(rc))
4296	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4297	}
4298	break;
4299	}
4300	}
4301
4302
4303	/* advance */
4304	GCPhys += PAGE_SIZE;
4305	pPage++;
4306	}
4307	}
4308	pgmUnlock(pVM);
4309
4310	RTFileClose(hFile);
4311	if (RT_SUCCESS(rc))
4312	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4313	return VINF_SUCCESS;
4314	}
4315
4316	#endif /* VBOX_WITH_DEBUGGER */
4317
4318	/**
4319	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4320	*/
4321	typedef struct PGMCHECKINTARGS
4322	{
4323	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4324	PPGMPHYSHANDLER pPrevPhys;
4325	PPGMVIRTHANDLER pPrevVirt;
4326	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4327	PVM pVM;
4328	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4329
4330	/**
4331	* Validate a node in the physical handler tree.
4332	*
4333	* @returns 0 on if ok, other wise 1.
4334	* @param pNode The handler node.
4335	* @param pvUser pVM.
4336	*/
4337	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4338	{
4339	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4340	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4341	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4342	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4343	AssertReleaseMsg( !pArgs->pPrevPhys
4344	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4345	("pPrevPhys=%p %RGp-%RGp %s\n"
4346	" pCur=%p %RGp-%RGp %s\n",
4347	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4348	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4349	pArgs->pPrevPhys = pCur;
4350	return 0;
4351	}
4352
4353
4354	/**
4355	* Validate a node in the virtual handler tree.
4356	*
4357	* @returns 0 on if ok, other wise 1.
4358	* @param pNode The handler node.
4359	* @param pvUser pVM.
4360	*/
4361	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4362	{
4363	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4364	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4365	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4366	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4367	AssertReleaseMsg( !pArgs->pPrevVirt
4368	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4369	("pPrevVirt=%p %RGv-%RGv %s\n"
4370	" pCur=%p %RGv-%RGv %s\n",
4371	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4372	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4373	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4374	{
4375	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4376	("pCur=%p %RGv-%RGv %s\n"
4377	"iPage=%d offVirtHandle=%#x expected %#x\n",
4378	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4379	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4380	}
4381	pArgs->pPrevVirt = pCur;
4382	return 0;
4383	}
4384
4385
4386	/**
4387	* Validate a node in the virtual handler tree.
4388	*
4389	* @returns 0 on if ok, other wise 1.
4390	* @param pNode The handler node.
4391	* @param pvUser pVM.
4392	*/
4393	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4394	{
4395	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4396	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4397	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4398	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4399	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4400	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4401	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4402	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4403	" pCur=%p %RGp-%RGp\n",
4404	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4405	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4406	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4407	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4408	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4409	" pCur=%p %RGp-%RGp\n",
4410	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4411	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4412	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4413	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4414	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4415	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4416	{
4417	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4418	for (;;)
4419	{
4420	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4421	AssertReleaseMsg(pCur2 != pCur,
4422	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4423	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4424	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4425	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4426	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4427	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4428	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4429	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4430	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4431	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4432	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4433	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4434	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4435	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4436	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4437	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4438	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4439	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4440	break;
4441	}
4442	}
4443
4444	pArgs->pPrevPhys2Virt = pCur;
4445	return 0;
4446	}
4447
4448
4449	/**
4450	* Perform an integrity check on the PGM component.
4451	*
4452	* @returns VINF_SUCCESS if everything is fine.
4453	* @returns VBox error status after asserting on integrity breach.
4454	* @param pVM The VM handle.
4455	*/
4456	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4457	{
4458	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4459
4460	/*
4461	* Check the trees.
4462	*/
4463	int cErrors = 0;
4464	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4465	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4466	PGMCHECKINTARGS Args = s_LeftToRight;
4467	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4468	Args = s_RightToLeft;
4469	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4470	Args = s_LeftToRight;
4471	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4472	Args = s_RightToLeft;
4473	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4474	Args = s_LeftToRight;
4475	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4476	Args = s_RightToLeft;
4477	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4478	Args = s_LeftToRight;
4479	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4480	Args = s_RightToLeft;
4481	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4482
4483	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4484	}
4485
4486

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 26234

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