VirtualBox

source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 24442

Last change on this file since 24442 was 24077, checked in by vboxsync, 15 years ago

Fixed nested paging for 64 bits guests on 32 bits hosts (AMD-V only).

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1/* $Id: PGM.cpp 24077 2009-10-26 14:08:59Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/** @page pg_pgm PGM - The Page Manager and Monitor
24 *
25 * @see grp_pgm,
26 * @ref pg_pgm_pool,
27 * @ref pg_pgm_phys.
28 *
29 *
30 * @section sec_pgm_modes Paging Modes
31 *
32 * There are three memory contexts: Host Context (HC), Guest Context (GC)
33 * and intermediate context. When talking about paging HC can also be refered to
34 * as "host paging", and GC refered to as "shadow paging".
35 *
36 * We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37 * is defined by the host operating system. The mode used in the shadow paging mode
38 * depends on the host paging mode and what the mode the guest is currently in. The
39 * following relation between the two is defined:
40 *
41 * @verbatim
42 Host > 32-bit | PAE | AMD64 |
43 Guest | | | |
44 ==v================================
45 32-bit 32-bit PAE PAE
46 -------|--------|--------|--------|
47 PAE PAE PAE PAE
48 -------|--------|--------|--------|
49 AMD64 AMD64 AMD64 AMD64
50 -------|--------|--------|--------| @endverbatim
51 *
52 * All configuration except those in the diagonal (upper left) are expected to
53 * require special effort from the switcher (i.e. a bit slower).
54 *
55 *
56 *
57 *
58 * @section sec_pgm_shw The Shadow Memory Context
59 *
60 *
61 * [..]
62 *
63 * Because of guest context mappings requires PDPT and PML4 entries to allow
64 * writing on AMD64, the two upper levels will have fixed flags whatever the
65 * guest is thinking of using there. So, when shadowing the PD level we will
66 * calculate the effective flags of PD and all the higher levels. In legacy
67 * PAE mode this only applies to the PWT and PCD bits (the rest are
68 * ignored/reserved/MBZ). We will ignore those bits for the present.
69 *
70 *
71 *
72 * @section sec_pgm_int The Intermediate Memory Context
73 *
74 * The world switch goes thru an intermediate memory context which purpose it is
75 * to provide different mappings of the switcher code. All guest mappings are also
76 * present in this context.
77 *
78 * The switcher code is mapped at the same location as on the host, at an
79 * identity mapped location (physical equals virtual address), and at the
80 * hypervisor location. The identity mapped location is for when the world
81 * switches that involves disabling paging.
82 *
83 * PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84 * simplifies switching guest CPU mode and consistency at the cost of more
85 * code to do the work. All memory use for those page tables is located below
86 * 4GB (this includes page tables for guest context mappings).
87 *
88 *
89 * @subsection subsec_pgm_int_gc Guest Context Mappings
90 *
91 * During assignment and relocation of a guest context mapping the intermediate
92 * memory context is used to verify the new location.
93 *
94 * Guest context mappings are currently restricted to below 4GB, for reasons
95 * of simplicity. This may change when we implement AMD64 support.
96 *
97 *
98 *
99 *
100 * @section sec_pgm_misc Misc
101 *
102 * @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103 *
104 * The differences between legacy PAE and long mode PAE are:
105 * -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106 * all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107 * usual meanings while 6 is ignored (AMD). This means that upon switching to
108 * legacy PAE mode we'll have to clear these bits and when going to long mode
109 * they must be set. This applies to both intermediate and shadow contexts,
110 * however we don't need to do it for the intermediate one since we're
111 * executing with CR0.WP at that time.
112 * -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113 * a page aligned one is required.
114 *
115 *
116 * @section sec_pgm_handlers Access Handlers
117 *
118 * Placeholder.
119 *
120 *
121 * @subsection sec_pgm_handlers_virt Virtual Access Handlers
122 *
123 * Placeholder.
124 *
125 *
126 * @subsection sec_pgm_handlers_virt Virtual Access Handlers
127 *
128 * We currently implement three types of virtual access handlers: ALL, WRITE
129 * and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130 *
131 * The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132 * to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133 * a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134 * rest of this section is going to be about these handlers.
135 *
136 * We'll go thru the life cycle of a handler and try make sense of it all, don't know
137 * how successfull this is gonna be...
138 *
139 * 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140 * PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141 * and create a new node that is inserted into the AVL tree (range key). Then
142 * a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143 *
144 * 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145 *
146 * 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147 * via the current guest CR3 and update the physical page -> virtual handler
148 * translation. Needless to say, this doesn't exactly scale very well. If any changes
149 * are detected, it will flag a virtual bit update just like we did on registration.
150 * PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151 *
152 * 2b. The virtual bit update process will iterate all the pages covered by all the
153 * virtual handlers and update the PGMPAGE virtual handler state to the max of all
154 * virtual handlers on that page.
155 *
156 * 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157 * we don't miss any alias mappings of the monitored pages.
158 *
159 * 2d. SyncCR3 will then proceed with syncing the CR3 table.
160 *
161 * 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162 * read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163 * will call the handlers like in the next step. If the physical mapping has
164 * changed we will - some time in the future - perform a handler callback
165 * (optional) and update the physical -> virtual handler cache.
166 *
167 * 4. \#PF(,write) on a page in the range. This will cause the handler to
168 * be invoked.
169 *
170 * 5. The guest invalidates the page and changes the physical backing or
171 * unmaps it. This should cause the invalidation callback to be invoked
172 * (it might not yet be 100% perfect). Exactly what happens next... is
173 * this where we mess up and end up out of sync for a while?
174 *
175 * 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176 * We will then set all PGMPAGEs in the physical -> virtual handler cache for
177 * this handler to NONE and trigger a full PGM resync (basically the same
178 * as int step 1). Which means 2 is executed again.
179 *
180 *
181 * @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182 *
183 * There is a bunch of things that needs to be done to make the virtual handlers
184 * work 100% correctly and work more efficiently.
185 *
186 * The first bit hasn't been implemented yet because it's going to slow the
187 * whole mess down even more, and besides it seems to be working reliably for
188 * our current uses. OTOH, some of the optimizations might end up more or less
189 * implementing the missing bits, so we'll see.
190 *
191 * On the optimization side, the first thing to do is to try avoid unnecessary
192 * cache flushing. Then try team up with the shadowing code to track changes
193 * in mappings by means of access to them (shadow in), updates to shadows pages,
194 * invlpg, and shadow PT discarding (perhaps).
195 *
196 * Some idea that have popped up for optimization for current and new features:
197 * - bitmap indicating where there are virtual handlers installed.
198 * (4KB => 2**20 pages, page 2**12 => covers 32-bit address space 1:1!)
199 * - Further optimize this by min/max (needs min/max avl getters).
200 * - Shadow page table entry bit (if any left)?
201 *
202 */
203
204
205/** @page pg_pgm_phys PGM Physical Guest Memory Management
206 *
207 *
208 * Objectives:
209 * - Guest RAM over-commitment using memory ballooning,
210 * zero pages and general page sharing.
211 * - Moving or mirroring a VM onto a different physical machine.
212 *
213 *
214 * @subsection subsec_pgmPhys_Definitions Definitions
215 *
216 * Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217 * machinery assoicated with it.
218 *
219 *
220 *
221 *
222 * @subsection subsec_pgmPhys_AllocPage Allocating a page.
223 *
224 * Initially we map *all* guest memory to the (per VM) zero page, which
225 * means that none of the read functions will cause pages to be allocated.
226 *
227 * Exception, access bit in page tables that have been shared. This must
228 * be handled, but we must also make sure PGMGst*Modify doesn't make
229 * unnecessary modifications.
230 *
231 * Allocation points:
232 * - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233 * - Replacing a zero page mapping at \#PF.
234 * - Replacing a shared page mapping at \#PF.
235 * - ROM registration (currently MMR3RomRegister).
236 * - VM restore (pgmR3Load).
237 *
238 * For the first three it would make sense to keep a few pages handy
239 * until we've reached the max memory commitment for the VM.
240 *
241 * For the ROM registration, we know exactly how many pages we need
242 * and will request these from ring-0. For restore, we will save
243 * the number of non-zero pages in the saved state and allocate
244 * them up front. This would allow the ring-0 component to refuse
245 * the request if the isn't sufficient memory available for VM use.
246 *
247 * Btw. for both ROM and restore allocations we won't be requiring
248 * zeroed pages as they are going to be filled instantly.
249 *
250 *
251 * @subsection subsec_pgmPhys_FreePage Freeing a page
252 *
253 * There are a few points where a page can be freed:
254 * - After being replaced by the zero page.
255 * - After being replaced by a shared page.
256 * - After being ballooned by the guest additions.
257 * - At reset.
258 * - At restore.
259 *
260 * When freeing one or more pages they will be returned to the ring-0
261 * component and replaced by the zero page.
262 *
263 * The reasoning for clearing out all the pages on reset is that it will
264 * return us to the exact same state as on power on, and may thereby help
265 * us reduce the memory load on the system. Further it might have a
266 * (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267 *
268 * On restore, as mention under the allocation topic, pages should be
269 * freed / allocated depending on how many is actually required by the
270 * new VM state. The simplest approach is to do like on reset, and free
271 * all non-ROM pages and then allocate what we need.
272 *
273 * A measure to prevent some fragmentation, would be to let each allocation
274 * chunk have some affinity towards the VM having allocated the most pages
275 * from it. Also, try make sure to allocate from allocation chunks that
276 * are almost full. Admittedly, both these measures might work counter to
277 * our intentions and its probably not worth putting a lot of effort,
278 * cpu time or memory into this.
279 *
280 *
281 * @subsection subsec_pgmPhys_SharePage Sharing a page
282 *
283 * The basic idea is that there there will be a idle priority kernel
284 * thread walking the non-shared VM pages hashing them and looking for
285 * pages with the same checksum. If such pages are found, it will compare
286 * them byte-by-byte to see if they actually are identical. If found to be
287 * identical it will allocate a shared page, copy the content, check that
288 * the page didn't change while doing this, and finally request both the
289 * VMs to use the shared page instead. If the page is all zeros (special
290 * checksum and byte-by-byte check) it will request the VM that owns it
291 * to replace it with the zero page.
292 *
293 * To make this efficient, we will have to make sure not to try share a page
294 * that will change its contents soon. This part requires the most work.
295 * A simple idea would be to request the VM to write monitor the page for
296 * a while to make sure it isn't modified any time soon. Also, it may
297 * make sense to skip pages that are being write monitored since this
298 * information is readily available to the thread if it works on the
299 * per-VM guest memory structures (presently called PGMRAMRANGE).
300 *
301 *
302 * @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303 *
304 * The pages are organized in allocation chunks in ring-0, this is a necessity
305 * if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306 * could easily work on a page-by-page basis if we liked. Whether this is possible
307 * or efficient on NT I don't quite know.) Fragmentation within these chunks may
308 * become a problem as part of the idea here is that we wish to return memory to
309 * the host system.
310 *
311 * For instance, starting two VMs at the same time, they will both allocate the
312 * guest memory on-demand and if permitted their page allocations will be
313 * intermixed. Shut down one of the two VMs and it will be difficult to return
314 * any memory to the host system because the page allocation for the two VMs are
315 * mixed up in the same allocation chunks.
316 *
317 * To further complicate matters, when pages are freed because they have been
318 * ballooned or become shared/zero the whole idea is that the page is supposed
319 * to be reused by another VM or returned to the host system. This will cause
320 * allocation chunks to contain pages belonging to different VMs and prevent
321 * returning memory to the host when one of those VM shuts down.
322 *
323 * The only way to really deal with this problem is to move pages. This can
324 * either be done at VM shutdown and or by the idle priority worker thread
325 * that will be responsible for finding sharable/zero pages. The mechanisms
326 * involved for coercing a VM to move a page (or to do it for it) will be
327 * the same as when telling it to share/zero a page.
328 *
329 *
330 * @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331 *
332 * There's a difficult balance between keeping the per-page tracking structures
333 * (global and guest page) easy to use and keeping them from eating too much
334 * memory. We have limited virtual memory resources available when operating in
335 * 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336 * tracking structures will be attemted designed such that we can deal with up
337 * to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338 *
339 *
340 * @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341 *
342 * @see pg_GMM
343 *
344 * @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345 *
346 * Fixed info is the physical address of the page (HCPhys) and the page id
347 * (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348 * Today we've restricting ourselves to 40(-12) bits because this is the current
349 * restrictions of all AMD64 implementations (I think Barcelona will up this
350 * to 48(-12) bits, not that it really matters) and I needed the bits for
351 * tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352 * decent range for the page id: 2^(28+12) = 1024TB.
353 *
354 * In additions to these, we'll have to keep maintaining the page flags as we
355 * currently do. Although it wouldn't harm to optimize these quite a bit, like
356 * for instance the ROM shouldn't depend on having a write handler installed
357 * in order for it to become read-only. A RO/RW bit should be considered so
358 * that the page syncing code doesn't have to mess about checking multiple
359 * flag combinations (ROM || RW handler || write monitored) in order to
360 * figure out how to setup a shadow PTE. But this of course, is second
361 * priority at present. Current this requires 12 bits, but could probably
362 * be optimized to ~8.
363 *
364 * Then there's the 24 bits used to track which shadow page tables are
365 * currently mapping a page for the purpose of speeding up physical
366 * access handlers, and thereby the page pool cache. More bit for this
367 * purpose wouldn't hurt IIRC.
368 *
369 * Then there is a new bit in which we need to record what kind of page
370 * this is, shared, zero, normal or write-monitored-normal. This'll
371 * require 2 bits. One bit might be needed for indicating whether a
372 * write monitored page has been written to. And yet another one or
373 * two for tracking migration status. 3-4 bits total then.
374 *
375 * Whatever is left will can be used to record the sharabilitiy of a
376 * page. The page checksum will not be stored in the per-VM table as
377 * the idle thread will not be permitted to do modifications to it.
378 * It will instead have to keep its own working set of potentially
379 * shareable pages and their check sums and stuff.
380 *
381 * For the present we'll keep the current packing of the
382 * PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383 * we'll have to change it to a struct with a total of 128-bits at
384 * our disposal.
385 *
386 * The initial layout will be like this:
387 * @verbatim
388 RTHCPHYS HCPhys; The current stuff.
389 63:40 Current shadow PT tracking stuff.
390 39:12 The physical page frame number.
391 11:0 The current flags.
392 uint32_t u28PageId : 28; The page id.
393 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395 uint32_t u1Reserved : 1; Reserved for later.
396 uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397 @endverbatim
398 *
399 * The final layout will be something like this:
400 * @verbatim
401 RTHCPHYS HCPhys; The current stuff.
402 63:48 High page id (12+).
403 47:12 The physical page frame number.
404 11:0 Low page id.
405 uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406 uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407 uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408 uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411 uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412 uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413 @endverbatim
414 *
415 * Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416 * around that I'm afraid. It means that the cost of dealing out 32GB of memory
417 * to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418 * example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419 *
420 * A couple of cost examples for the total cost per-VM + kernel.
421 * 32-bit Windows and 32-bit linux:
422 * 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423 * 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424 * 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425 * 64-bit Windows and 64-bit linux:
426 * 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427 * 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428 * 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429 *
430 * UPDATE - 2007-09-27:
431 * Will need a ballooned flag/state too because we cannot
432 * trust the guest 100% and reporting the same page as ballooned more
433 * than once will put the GMM off balance.
434 *
435 *
436 * @subsection subsec_pgmPhys_Serializing Serializing Access
437 *
438 * Initially, we'll try a simple scheme:
439 *
440 * - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441 * by the EMT thread of that VM while in the pgm critsect.
442 * - Other threads in the VM process that needs to make reliable use of
443 * the per-VM RAM tracking structures will enter the critsect.
444 * - No process external thread or kernel thread will ever try enter
445 * the pgm critical section, as that just won't work.
446 * - The idle thread (and similar threads) doesn't not need 100% reliable
447 * data when performing it tasks as the EMT thread will be the one to
448 * do the actual changes later anyway. So, as long as it only accesses
449 * the main ram range, it can do so by somehow preventing the VM from
450 * being destroyed while it works on it...
451 *
452 * - The over-commitment management, including the allocating/freeing
453 * chunks, is serialized by a ring-0 mutex lock (a fast one since the
454 * more mundane mutex implementation is broken on Linux).
455 * - A separeate mutex is protecting the set of allocation chunks so
456 * that pages can be shared or/and freed up while some other VM is
457 * allocating more chunks. This mutex can be take from under the other
458 * one, but not the otherway around.
459 *
460 *
461 * @subsection subsec_pgmPhys_Request VM Request interface
462 *
463 * When in ring-0 it will become necessary to send requests to a VM so it can
464 * for instance move a page while defragmenting during VM destroy. The idle
465 * thread will make use of this interface to request VMs to setup shared
466 * pages and to perform write monitoring of pages.
467 *
468 * I would propose an interface similar to the current VMReq interface, similar
469 * in that it doesn't require locking and that the one sending the request may
470 * wait for completion if it wishes to. This shouldn't be very difficult to
471 * realize.
472 *
473 * The requests themselves are also pretty simple. They are basically:
474 * -# Check that some precondition is still true.
475 * -# Do the update.
476 * -# Update all shadow page tables involved with the page.
477 *
478 * The 3rd step is identical to what we're already doing when updating a
479 * physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480 *
481 *
482 *
483 * @section sec_pgmPhys_MappingCaches Mapping Caches
484 *
485 * In order to be able to map in and out memory and to be able to support
486 * guest with more RAM than we've got virtual address space, we'll employing
487 * a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488 * and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489 * memory context for the HWACCM execution.
490 *
491 *
492 * @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493 *
494 * We've considered implementing the ring-3 mapping cache page based but found
495 * that this was bother some when one had to take into account TLBs+SMP and
496 * portability (missing the necessary APIs on several platforms). There were
497 * also some performance concerns with this approach which hadn't quite been
498 * worked out.
499 *
500 * Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501 * matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502 * only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503 * compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504 * costly than a single page, although how much more costly is uncertain. We'll
505 * try address this by using a very big cache, preferably bigger than the actual
506 * VM RAM size if possible. The current VM RAM sizes should give some idea for
507 * 32-bit boxes, while on 64-bit we can probably get away with employing an
508 * unlimited cache.
509 *
510 * The cache have to parts, as already indicated, the ring-3 side and the
511 * ring-0 side.
512 *
513 * The ring-0 will be tied to the page allocator since it will operate on the
514 * memory objects it contains. It will therefore require the first ring-0 mutex
515 * discussed in @ref subsec_pgmPhys_Serializing. We
516 * some double house keeping wrt to who has mapped what I think, since both
517 * VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518 *
519 * The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520 * require anyone that desires to do changes to the mapping cache to do that
521 * from within this critsect. Alternatively, we could employ a separate critsect
522 * for serializing changes to the mapping cache as this would reduce potential
523 * contention with other threads accessing mappings unrelated to the changes
524 * that are in process. We can see about this later, contention will show
525 * up in the statistics anyway, so it'll be simple to tell.
526 *
527 * The organization of the ring-3 part will be very much like how the allocation
528 * chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529 * having to walk the tree all the time, we'll have a couple of lookaside entries
530 * like in we do for I/O ports and MMIO in IOM.
531 *
532 * The simplified flow of a PGMPhysRead/Write function:
533 * -# Enter the PGM critsect.
534 * -# Lookup GCPhys in the ram ranges and get the Page ID.
535 * -# Calc the Allocation Chunk ID from the Page ID.
536 * -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537 * If not found in cache:
538 * -# Call ring-0 and request it to be mapped and supply
539 * a chunk to be unmapped if the cache is maxed out already.
540 * -# Insert the new mapping into the AVL tree (id + R3 address).
541 * -# Update the relevant lookaside entry and return the mapping address.
542 * -# Do the read/write according to monitoring flags and everything.
543 * -# Leave the critsect.
544 *
545 *
546 * @section sec_pgmPhys_Fallback Fallback
547 *
548 * Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549 * API and thus require a fallback.
550 *
551 * So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552 * will return to the ring-3 caller (and later ring-0) and asking it to seed
553 * the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554 * then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555 * "SeededAllocPages" call to ring-0.
556 *
557 * The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558 * all page sharing (zero page detection will continue). It will also force
559 * all allocations to come from the VM which seeded the page. Both these
560 * measures are taken to make sure that there will never be any need for
561 * mapping anything into ring-3 - everything will be mapped already.
562 *
563 * Whether we'll continue to use the current MM locked memory management
564 * for this I don't quite know (I'd prefer not to and just ditch that all
565 * togther), we'll see what's simplest to do.
566 *
567 *
568 *
569 * @section sec_pgmPhys_Changes Changes
570 *
571 * Breakdown of the changes involved?
572 */
573
574/*******************************************************************************
575* Header Files *
576*******************************************************************************/
577#define LOG_GROUP LOG_GROUP_PGM
578#include <VBox/dbgf.h>
579#include <VBox/pgm.h>
580#include <VBox/cpum.h>
581#include <VBox/iom.h>
582#include <VBox/sup.h>
583#include <VBox/mm.h>
584#include <VBox/em.h>
585#include <VBox/stam.h>
586#include <VBox/rem.h>
587#include <VBox/selm.h>
588#include <VBox/ssm.h>
589#include <VBox/hwaccm.h>
590#include "PGMInternal.h"
591#include <VBox/vm.h>
592
593#include <VBox/dbg.h>
594#include <VBox/param.h>
595#include <VBox/err.h>
596
597#include <iprt/asm.h>
598#include <iprt/assert.h>
599#include <iprt/env.h>
600#include <iprt/mem.h>
601#include <iprt/file.h>
602#include <iprt/string.h>
603#include <iprt/thread.h>
604
605
606/*******************************************************************************
607* Defined Constants And Macros *
608*******************************************************************************/
609/** Saved state data unit version for 2.5.x and later. */
610#define PGM_SAVED_STATE_VERSION 9
611/** Saved state data unit version for 2.2.2 and later. */
612#define PGM_SAVED_STATE_VERSION_2_2_2 8
613/** Saved state data unit version for 2.2.0. */
614#define PGM_SAVED_STATE_VERSION_RR_DESC 7
615/** Saved state data unit version. */
616#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
617
618
619/*******************************************************************************
620* Internal Functions *
621*******************************************************************************/
622static int pgmR3InitPaging(PVM pVM);
623static void pgmR3InitStats(PVM pVM);
624static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
625static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
626static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
628static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
629static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
630#ifdef VBOX_STRICT
631static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
632#endif
633static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
634static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
635static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
636
637#ifdef VBOX_WITH_DEBUGGER
638/** @todo Convert the first two commands to 'info' items. */
639static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644# ifdef VBOX_STRICT
645static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646# endif
647static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648#endif
649
650
651/*******************************************************************************
652* Global Variables *
653*******************************************************************************/
654#ifdef VBOX_WITH_DEBUGGER
655/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
656static const DBGCVARDESC g_aPgmErrorArgs[] =
657{
658 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
659 { 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
660};
661
662static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
663{
664 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
665 { 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
666 { 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
667};
668
669/** Command descriptors. */
670static const DBGCCMD g_aCmds[] =
671{
672 /* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
673 { "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
674 { "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
675 { "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
676 { "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
677 { "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
678#ifdef VBOX_STRICT
679 { "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
680#endif
681 { "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
682 { "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
683};
684#endif
685
686
687
688
689/*
690 * Shadow - 32-bit mode
691 */
692#define PGM_SHW_TYPE PGM_TYPE_32BIT
693#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
694#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
695#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
696#include "PGMShw.h"
697
698/* Guest - real mode */
699#define PGM_GST_TYPE PGM_TYPE_REAL
700#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
701#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
702#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
703#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
704#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
705#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
706#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
707#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
708#include "PGMBth.h"
709#include "PGMGstDefs.h"
710#include "PGMGst.h"
711#undef BTH_PGMPOOLKIND_PT_FOR_PT
712#undef BTH_PGMPOOLKIND_ROOT
713#undef PGM_BTH_NAME
714#undef PGM_BTH_NAME_RC_STR
715#undef PGM_BTH_NAME_R0_STR
716#undef PGM_GST_TYPE
717#undef PGM_GST_NAME
718#undef PGM_GST_NAME_RC_STR
719#undef PGM_GST_NAME_R0_STR
720
721/* Guest - protected mode */
722#define PGM_GST_TYPE PGM_TYPE_PROT
723#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
724#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
725#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
726#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
727#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
728#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
729#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
730#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
731#include "PGMBth.h"
732#include "PGMGstDefs.h"
733#include "PGMGst.h"
734#undef BTH_PGMPOOLKIND_PT_FOR_PT
735#undef BTH_PGMPOOLKIND_ROOT
736#undef PGM_BTH_NAME
737#undef PGM_BTH_NAME_RC_STR
738#undef PGM_BTH_NAME_R0_STR
739#undef PGM_GST_TYPE
740#undef PGM_GST_NAME
741#undef PGM_GST_NAME_RC_STR
742#undef PGM_GST_NAME_R0_STR
743
744/* Guest - 32-bit mode */
745#define PGM_GST_TYPE PGM_TYPE_32BIT
746#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
747#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
748#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
749#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
750#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
751#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
752#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
753#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
754#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
755#include "PGMBth.h"
756#include "PGMGstDefs.h"
757#include "PGMGst.h"
758#undef BTH_PGMPOOLKIND_PT_FOR_BIG
759#undef BTH_PGMPOOLKIND_PT_FOR_PT
760#undef BTH_PGMPOOLKIND_ROOT
761#undef PGM_BTH_NAME
762#undef PGM_BTH_NAME_RC_STR
763#undef PGM_BTH_NAME_R0_STR
764#undef PGM_GST_TYPE
765#undef PGM_GST_NAME
766#undef PGM_GST_NAME_RC_STR
767#undef PGM_GST_NAME_R0_STR
768
769#undef PGM_SHW_TYPE
770#undef PGM_SHW_NAME
771#undef PGM_SHW_NAME_RC_STR
772#undef PGM_SHW_NAME_R0_STR
773
774
775/*
776 * Shadow - PAE mode
777 */
778#define PGM_SHW_TYPE PGM_TYPE_PAE
779#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
780#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
781#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
782#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
783#include "PGMShw.h"
784
785/* Guest - real mode */
786#define PGM_GST_TYPE PGM_TYPE_REAL
787#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
788#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
789#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
790#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
791#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
792#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
793#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
794#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
795#include "PGMGstDefs.h"
796#include "PGMBth.h"
797#undef BTH_PGMPOOLKIND_PT_FOR_PT
798#undef BTH_PGMPOOLKIND_ROOT
799#undef PGM_BTH_NAME
800#undef PGM_BTH_NAME_RC_STR
801#undef PGM_BTH_NAME_R0_STR
802#undef PGM_GST_TYPE
803#undef PGM_GST_NAME
804#undef PGM_GST_NAME_RC_STR
805#undef PGM_GST_NAME_R0_STR
806
807/* Guest - protected mode */
808#define PGM_GST_TYPE PGM_TYPE_PROT
809#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
810#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
811#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
812#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
813#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
814#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
815#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
816#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
817#include "PGMGstDefs.h"
818#include "PGMBth.h"
819#undef BTH_PGMPOOLKIND_PT_FOR_PT
820#undef BTH_PGMPOOLKIND_ROOT
821#undef PGM_BTH_NAME
822#undef PGM_BTH_NAME_RC_STR
823#undef PGM_BTH_NAME_R0_STR
824#undef PGM_GST_TYPE
825#undef PGM_GST_NAME
826#undef PGM_GST_NAME_RC_STR
827#undef PGM_GST_NAME_R0_STR
828
829/* Guest - 32-bit mode */
830#define PGM_GST_TYPE PGM_TYPE_32BIT
831#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
832#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
833#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
834#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
835#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
836#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
837#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
838#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
839#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
840#include "PGMGstDefs.h"
841#include "PGMBth.h"
842#undef BTH_PGMPOOLKIND_PT_FOR_BIG
843#undef BTH_PGMPOOLKIND_PT_FOR_PT
844#undef BTH_PGMPOOLKIND_ROOT
845#undef PGM_BTH_NAME
846#undef PGM_BTH_NAME_RC_STR
847#undef PGM_BTH_NAME_R0_STR
848#undef PGM_GST_TYPE
849#undef PGM_GST_NAME
850#undef PGM_GST_NAME_RC_STR
851#undef PGM_GST_NAME_R0_STR
852
853/* Guest - PAE mode */
854#define PGM_GST_TYPE PGM_TYPE_PAE
855#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
856#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
857#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
858#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
859#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
860#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
861#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
862#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
863#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
864#include "PGMBth.h"
865#include "PGMGstDefs.h"
866#include "PGMGst.h"
867#undef BTH_PGMPOOLKIND_PT_FOR_BIG
868#undef BTH_PGMPOOLKIND_PT_FOR_PT
869#undef BTH_PGMPOOLKIND_ROOT
870#undef PGM_BTH_NAME
871#undef PGM_BTH_NAME_RC_STR
872#undef PGM_BTH_NAME_R0_STR
873#undef PGM_GST_TYPE
874#undef PGM_GST_NAME
875#undef PGM_GST_NAME_RC_STR
876#undef PGM_GST_NAME_R0_STR
877
878#undef PGM_SHW_TYPE
879#undef PGM_SHW_NAME
880#undef PGM_SHW_NAME_RC_STR
881#undef PGM_SHW_NAME_R0_STR
882
883
884/*
885 * Shadow - AMD64 mode
886 */
887#define PGM_SHW_TYPE PGM_TYPE_AMD64
888#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
889#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
890#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
891#include "PGMShw.h"
892
893#ifdef VBOX_WITH_64_BITS_GUESTS
894/* Guest - AMD64 mode */
895# define PGM_GST_TYPE PGM_TYPE_AMD64
896# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
897# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
898# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
899# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
900# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
901# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
902# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
903# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
904# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
905# include "PGMBth.h"
906# include "PGMGstDefs.h"
907# include "PGMGst.h"
908# undef BTH_PGMPOOLKIND_PT_FOR_BIG
909# undef BTH_PGMPOOLKIND_PT_FOR_PT
910# undef BTH_PGMPOOLKIND_ROOT
911# undef PGM_BTH_NAME
912# undef PGM_BTH_NAME_RC_STR
913# undef PGM_BTH_NAME_R0_STR
914# undef PGM_GST_TYPE
915# undef PGM_GST_NAME
916# undef PGM_GST_NAME_RC_STR
917# undef PGM_GST_NAME_R0_STR
918#endif /* VBOX_WITH_64_BITS_GUESTS */
919
920#undef PGM_SHW_TYPE
921#undef PGM_SHW_NAME
922#undef PGM_SHW_NAME_RC_STR
923#undef PGM_SHW_NAME_R0_STR
924
925
926/*
927 * Shadow - Nested paging mode
928 */
929#define PGM_SHW_TYPE PGM_TYPE_NESTED
930#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
931#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
932#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
933#include "PGMShw.h"
934
935/* Guest - real mode */
936#define PGM_GST_TYPE PGM_TYPE_REAL
937#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
938#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
939#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
940#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
941#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
942#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
943#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
944#include "PGMGstDefs.h"
945#include "PGMBth.h"
946#undef BTH_PGMPOOLKIND_PT_FOR_PT
947#undef PGM_BTH_NAME
948#undef PGM_BTH_NAME_RC_STR
949#undef PGM_BTH_NAME_R0_STR
950#undef PGM_GST_TYPE
951#undef PGM_GST_NAME
952#undef PGM_GST_NAME_RC_STR
953#undef PGM_GST_NAME_R0_STR
954
955/* Guest - protected mode */
956#define PGM_GST_TYPE PGM_TYPE_PROT
957#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
958#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
959#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
960#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
961#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
962#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
963#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
964#include "PGMGstDefs.h"
965#include "PGMBth.h"
966#undef BTH_PGMPOOLKIND_PT_FOR_PT
967#undef PGM_BTH_NAME
968#undef PGM_BTH_NAME_RC_STR
969#undef PGM_BTH_NAME_R0_STR
970#undef PGM_GST_TYPE
971#undef PGM_GST_NAME
972#undef PGM_GST_NAME_RC_STR
973#undef PGM_GST_NAME_R0_STR
974
975/* Guest - 32-bit mode */
976#define PGM_GST_TYPE PGM_TYPE_32BIT
977#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
978#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
979#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
980#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
981#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
982#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
983#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
984#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
985#include "PGMGstDefs.h"
986#include "PGMBth.h"
987#undef BTH_PGMPOOLKIND_PT_FOR_BIG
988#undef BTH_PGMPOOLKIND_PT_FOR_PT
989#undef PGM_BTH_NAME
990#undef PGM_BTH_NAME_RC_STR
991#undef PGM_BTH_NAME_R0_STR
992#undef PGM_GST_TYPE
993#undef PGM_GST_NAME
994#undef PGM_GST_NAME_RC_STR
995#undef PGM_GST_NAME_R0_STR
996
997/* Guest - PAE mode */
998#define PGM_GST_TYPE PGM_TYPE_PAE
999#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1000#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1001#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1002#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1003#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1004#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1005#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1006#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1007#include "PGMGstDefs.h"
1008#include "PGMBth.h"
1009#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1010#undef BTH_PGMPOOLKIND_PT_FOR_PT
1011#undef PGM_BTH_NAME
1012#undef PGM_BTH_NAME_RC_STR
1013#undef PGM_BTH_NAME_R0_STR
1014#undef PGM_GST_TYPE
1015#undef PGM_GST_NAME
1016#undef PGM_GST_NAME_RC_STR
1017#undef PGM_GST_NAME_R0_STR
1018
1019#ifdef VBOX_WITH_64_BITS_GUESTS
1020/* Guest - AMD64 mode */
1021# define PGM_GST_TYPE PGM_TYPE_AMD64
1022# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1023# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1024# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1025# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1026# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1027# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1028# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1029# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1030# include "PGMGstDefs.h"
1031# include "PGMBth.h"
1032# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1033# undef BTH_PGMPOOLKIND_PT_FOR_PT
1034# undef PGM_BTH_NAME
1035# undef PGM_BTH_NAME_RC_STR
1036# undef PGM_BTH_NAME_R0_STR
1037# undef PGM_GST_TYPE
1038# undef PGM_GST_NAME
1039# undef PGM_GST_NAME_RC_STR
1040# undef PGM_GST_NAME_R0_STR
1041#endif /* VBOX_WITH_64_BITS_GUESTS */
1042
1043#undef PGM_SHW_TYPE
1044#undef PGM_SHW_NAME
1045#undef PGM_SHW_NAME_RC_STR
1046#undef PGM_SHW_NAME_R0_STR
1047
1048
1049/*
1050 * Shadow - EPT
1051 */
1052#define PGM_SHW_TYPE PGM_TYPE_EPT
1053#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1054#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1055#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1056#include "PGMShw.h"
1057
1058/* Guest - real mode */
1059#define PGM_GST_TYPE PGM_TYPE_REAL
1060#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1061#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1062#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1063#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1064#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1065#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1066#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1067#include "PGMGstDefs.h"
1068#include "PGMBth.h"
1069#undef BTH_PGMPOOLKIND_PT_FOR_PT
1070#undef PGM_BTH_NAME
1071#undef PGM_BTH_NAME_RC_STR
1072#undef PGM_BTH_NAME_R0_STR
1073#undef PGM_GST_TYPE
1074#undef PGM_GST_NAME
1075#undef PGM_GST_NAME_RC_STR
1076#undef PGM_GST_NAME_R0_STR
1077
1078/* Guest - protected mode */
1079#define PGM_GST_TYPE PGM_TYPE_PROT
1080#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1081#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1082#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1083#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1084#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1085#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1086#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1087#include "PGMGstDefs.h"
1088#include "PGMBth.h"
1089#undef BTH_PGMPOOLKIND_PT_FOR_PT
1090#undef PGM_BTH_NAME
1091#undef PGM_BTH_NAME_RC_STR
1092#undef PGM_BTH_NAME_R0_STR
1093#undef PGM_GST_TYPE
1094#undef PGM_GST_NAME
1095#undef PGM_GST_NAME_RC_STR
1096#undef PGM_GST_NAME_R0_STR
1097
1098/* Guest - 32-bit mode */
1099#define PGM_GST_TYPE PGM_TYPE_32BIT
1100#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1101#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1102#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1103#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1104#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1105#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1106#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1107#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1108#include "PGMGstDefs.h"
1109#include "PGMBth.h"
1110#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1111#undef BTH_PGMPOOLKIND_PT_FOR_PT
1112#undef PGM_BTH_NAME
1113#undef PGM_BTH_NAME_RC_STR
1114#undef PGM_BTH_NAME_R0_STR
1115#undef PGM_GST_TYPE
1116#undef PGM_GST_NAME
1117#undef PGM_GST_NAME_RC_STR
1118#undef PGM_GST_NAME_R0_STR
1119
1120/* Guest - PAE mode */
1121#define PGM_GST_TYPE PGM_TYPE_PAE
1122#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1123#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1124#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1125#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1126#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1127#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1128#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1129#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1130#include "PGMGstDefs.h"
1131#include "PGMBth.h"
1132#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1133#undef BTH_PGMPOOLKIND_PT_FOR_PT
1134#undef PGM_BTH_NAME
1135#undef PGM_BTH_NAME_RC_STR
1136#undef PGM_BTH_NAME_R0_STR
1137#undef PGM_GST_TYPE
1138#undef PGM_GST_NAME
1139#undef PGM_GST_NAME_RC_STR
1140#undef PGM_GST_NAME_R0_STR
1141
1142#ifdef VBOX_WITH_64_BITS_GUESTS
1143/* Guest - AMD64 mode */
1144# define PGM_GST_TYPE PGM_TYPE_AMD64
1145# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1146# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1147# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1148# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1149# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1150# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1151# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1152# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1153# include "PGMGstDefs.h"
1154# include "PGMBth.h"
1155# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1156# undef BTH_PGMPOOLKIND_PT_FOR_PT
1157# undef PGM_BTH_NAME
1158# undef PGM_BTH_NAME_RC_STR
1159# undef PGM_BTH_NAME_R0_STR
1160# undef PGM_GST_TYPE
1161# undef PGM_GST_NAME
1162# undef PGM_GST_NAME_RC_STR
1163# undef PGM_GST_NAME_R0_STR
1164#endif /* VBOX_WITH_64_BITS_GUESTS */
1165
1166#undef PGM_SHW_TYPE
1167#undef PGM_SHW_NAME
1168#undef PGM_SHW_NAME_RC_STR
1169#undef PGM_SHW_NAME_R0_STR
1170
1171
1172
1173/**
1174 * Initiates the paging of VM.
1175 *
1176 * @returns VBox status code.
1177 * @param pVM Pointer to VM structure.
1178 */
1179VMMR3DECL(int) PGMR3Init(PVM pVM)
1180{
1181 LogFlow(("PGMR3Init:\n"));
1182 PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1183 int rc;
1184
1185 /*
1186 * Assert alignment and sizes.
1187 */
1188 AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1189 AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1190
1191 /*
1192 * Init the structure.
1193 */
1194 pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1195 pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1196
1197 /* Init the per-CPU part. */
1198 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1199 {
1200 PVMCPU pVCpu = &pVM->aCpus[i];
1201 PPGMCPU pPGM = &pVCpu->pgm.s;
1202
1203 pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1204 pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1205 pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1206
1207 pPGM->enmShadowMode = PGMMODE_INVALID;
1208 pPGM->enmGuestMode = PGMMODE_INVALID;
1209
1210 pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1211
1212 pPGM->pGstPaePdptR3 = NULL;
1213#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1214 pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1215#endif
1216 pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1217 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1218 {
1219 pPGM->apGstPaePDsR3[i] = NULL;
1220#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1221 pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1222#endif
1223 pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1224 pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1225 pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1226 }
1227
1228 pPGM->fA20Enabled = true;
1229 }
1230
1231 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1232 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1233 pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1234
1235 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1236#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1237 true
1238#else
1239 false
1240#endif
1241 );
1242 AssertLogRelRCReturn(rc, rc);
1243
1244#if HC_ARCH_BITS == 64 || 1 /** @todo 4GB/32-bit: remove || 1 later and adjust the limit. */
1245 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1246#else
1247 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1248#endif
1249 AssertLogRelRCReturn(rc, rc);
1250 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1251 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1252
1253 /*
1254 * Get the configured RAM size - to estimate saved state size.
1255 */
1256 uint64_t cbRam;
1257 rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1258 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1259 cbRam = 0;
1260 else if (RT_SUCCESS(rc))
1261 {
1262 if (cbRam < PAGE_SIZE)
1263 cbRam = 0;
1264 cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1265 }
1266 else
1267 {
1268 AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1269 return rc;
1270 }
1271
1272 /*
1273 * Register callbacks, string formatters and the saved state data unit.
1274 */
1275#ifdef VBOX_STRICT
1276 VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1277#endif
1278 PGMRegisterStringFormatTypes();
1279
1280 rc = pgmR3InitSavedState(pVM, cbRam);
1281 if (RT_FAILURE(rc))
1282 return rc;
1283
1284 /*
1285 * Initialize the PGM critical section and flush the phys TLBs
1286 */
1287 rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1288 AssertRCReturn(rc, rc);
1289
1290 PGMR3PhysChunkInvalidateTLB(pVM);
1291 PGMPhysInvalidatePageR3MapTLB(pVM);
1292 PGMPhysInvalidatePageR0MapTLB(pVM);
1293 PGMPhysInvalidatePageGCMapTLB(pVM);
1294
1295 /*
1296 * For the time being we sport a full set of handy pages in addition to the base
1297 * memory to simplify things.
1298 */
1299 rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1300 AssertRCReturn(rc, rc);
1301
1302 /*
1303 * Trees
1304 */
1305 rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1306 if (RT_SUCCESS(rc))
1307 {
1308 pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1309 pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1310
1311 /*
1312 * Alocate the zero page.
1313 */
1314 rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1315 }
1316 if (RT_SUCCESS(rc))
1317 {
1318 pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1319 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1320 pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1321 AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1322
1323 /*
1324 * Init the paging.
1325 */
1326 rc = pgmR3InitPaging(pVM);
1327 }
1328 if (RT_SUCCESS(rc))
1329 {
1330 /*
1331 * Init the page pool.
1332 */
1333 rc = pgmR3PoolInit(pVM);
1334 }
1335 if (RT_SUCCESS(rc))
1336 {
1337 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1338 {
1339 PVMCPU pVCpu = &pVM->aCpus[i];
1340 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1341 if (RT_FAILURE(rc))
1342 break;
1343 }
1344 }
1345
1346 if (RT_SUCCESS(rc))
1347 {
1348 /*
1349 * Info & statistics
1350 */
1351 DBGFR3InfoRegisterInternal(pVM, "mode",
1352 "Shows the current paging mode. "
1353 "Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1354 pgmR3InfoMode);
1355 DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1356 "Dumps all the entries in the top level paging table. No arguments.",
1357 pgmR3InfoCr3);
1358 DBGFR3InfoRegisterInternal(pVM, "phys",
1359 "Dumps all the physical address ranges. No arguments.",
1360 pgmR3PhysInfo);
1361 DBGFR3InfoRegisterInternal(pVM, "handlers",
1362 "Dumps physical, virtual and hyper virtual handlers. "
1363 "Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1364 "Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1365 pgmR3InfoHandlers);
1366 DBGFR3InfoRegisterInternal(pVM, "mappings",
1367 "Dumps guest mappings.",
1368 pgmR3MapInfo);
1369
1370 pgmR3InitStats(pVM);
1371
1372#ifdef VBOX_WITH_DEBUGGER
1373 /*
1374 * Debugger commands.
1375 */
1376 static bool s_fRegisteredCmds = false;
1377 if (!s_fRegisteredCmds)
1378 {
1379 int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1380 if (RT_SUCCESS(rc))
1381 s_fRegisteredCmds = true;
1382 }
1383#endif
1384 return VINF_SUCCESS;
1385 }
1386
1387 /* Almost no cleanup necessary, MM frees all memory. */
1388 PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1389
1390 return rc;
1391}
1392
1393
1394/**
1395 * Initializes the per-VCPU PGM.
1396 *
1397 * @returns VBox status code.
1398 * @param pVM The VM to operate on.
1399 */
1400VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1401{
1402 LogFlow(("PGMR3InitCPU\n"));
1403 return VINF_SUCCESS;
1404}
1405
1406
1407/**
1408 * Init paging.
1409 *
1410 * Since we need to check what mode the host is operating in before we can choose
1411 * the right paging functions for the host we have to delay this until R0 has
1412 * been initialized.
1413 *
1414 * @returns VBox status code.
1415 * @param pVM VM handle.
1416 */
1417static int pgmR3InitPaging(PVM pVM)
1418{
1419 /*
1420 * Force a recalculation of modes and switcher so everyone gets notified.
1421 */
1422 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1423 {
1424 PVMCPU pVCpu = &pVM->aCpus[i];
1425
1426 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1427 pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1428 }
1429
1430 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1431
1432 /*
1433 * Allocate static mapping space for whatever the cr3 register
1434 * points to and in the case of PAE mode to the 4 PDs.
1435 */
1436 int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1437 if (RT_FAILURE(rc))
1438 {
1439 AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1440 return rc;
1441 }
1442 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1443
1444 /*
1445 * Allocate pages for the three possible intermediate contexts
1446 * (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1447 * for the sake of simplicity. The AMD64 uses the PAE for the
1448 * lower levels, making the total number of pages 11 (3 + 7 + 1).
1449 *
1450 * We assume that two page tables will be enought for the core code
1451 * mappings (HC virtual and identity).
1452 */
1453 pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1454 pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1455 pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1456 pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1457 pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1458 pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1459 pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1460 pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1461 pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1462 pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1463 pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1464 pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1465
1466 pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1467 AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1468 pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1469 AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1470 pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1471 AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1472
1473 /*
1474 * Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1475 */
1476 ASMMemZeroPage(pVM->pgm.s.pInterPD);
1477 ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1478 ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1479
1480 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1481 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1482
1483 ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1484 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1485 {
1486 ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1487 pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P | PGM_PLXFLAGS_PERMANENT
1488 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1489 }
1490
1491 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1492 {
1493 const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1494 pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A | PGM_PLXFLAGS_PERMANENT
1495 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1496 }
1497
1498 RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1499 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1500 pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A | PGM_PLXFLAGS_PERMANENT
1501 | HCPhysInterPaePDPT64;
1502
1503 /*
1504 * Initialize paging workers and mode from current host mode
1505 * and the guest running in real mode.
1506 */
1507 pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1508 switch (pVM->pgm.s.enmHostMode)
1509 {
1510 case SUPPAGINGMODE_32_BIT:
1511 case SUPPAGINGMODE_32_BIT_GLOBAL:
1512 case SUPPAGINGMODE_PAE:
1513 case SUPPAGINGMODE_PAE_GLOBAL:
1514 case SUPPAGINGMODE_PAE_NX:
1515 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1516 break;
1517
1518 case SUPPAGINGMODE_AMD64:
1519 case SUPPAGINGMODE_AMD64_GLOBAL:
1520 case SUPPAGINGMODE_AMD64_NX:
1521 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1522#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1523 if (ARCH_BITS != 64)
1524 {
1525 AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1526 LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1527 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1528 }
1529#endif
1530 break;
1531 default:
1532 AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1533 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1534 }
1535 rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1536 if (RT_SUCCESS(rc))
1537 {
1538 LogFlow(("pgmR3InitPaging: returns successfully\n"));
1539#if HC_ARCH_BITS == 64
1540 LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1541 pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1542 LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1543 MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1544 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1545 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1546 MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1547#endif
1548
1549 return VINF_SUCCESS;
1550 }
1551
1552 LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1553 return rc;
1554}
1555
1556
1557/**
1558 * Init statistics
1559 */
1560static void pgmR3InitStats(PVM pVM)
1561{
1562 PPGM pPGM = &pVM->pgm.s;
1563 int rc;
1564
1565 /* Common - misc variables */
1566 STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1567 STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1568 STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1569 STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1570 STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_OCCURENCES, "The number of write monitored pages.");
1571 STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_OCCURENCES, "The number of previously write monitored pages that have been written to.");
1572 STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_OCCURENCES, "The number of write(/read) locked pages.");
1573 STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_OCCURENCES, "The number of read (only) locked pages.");
1574 STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1575 STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1576 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1577 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1578
1579#ifdef VBOX_WITH_STATISTICS
1580
1581# define PGM_REG_COUNTER(a, b, c) \
1582 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1583 AssertRC(rc);
1584
1585# define PGM_REG_COUNTER_BYTES(a, b, c) \
1586 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1587 AssertRC(rc);
1588
1589# define PGM_REG_PROFILE(a, b, c) \
1590 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1591 AssertRC(rc);
1592
1593 PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1594 PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1595 PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1596 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1597 PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1598 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1599 PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1600 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1601 PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1602 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1603
1604 PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1605 PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1606 PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1607 PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1608 PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1609 PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1610 PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1611 PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1612
1613 PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1614 PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1615 PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1616 PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1617
1618 PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1619 PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1620 PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1621 PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1622
1623 PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1624 PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1625/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1626 PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1627 PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1628/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1629
1630 PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1631 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1632 PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1633 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1634 PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1635 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1636 PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1637 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1638
1639 /* GC only: */
1640 PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1641 PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1642 PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1643 PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1644
1645 PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1646 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1647 PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1648 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1649 PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1650 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1651 PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1652 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1653
1654# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1655 PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1656 PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1657 PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1658 PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1659 PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1660 PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1661# endif
1662
1663# undef PGM_REG_COUNTER
1664# undef PGM_REG_PROFILE
1665#endif
1666
1667 /*
1668 * Note! The layout below matches the member layout exactly!
1669 */
1670
1671 /*
1672 * Common - stats
1673 */
1674 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1675 {
1676 PVMCPU pVCpu = &pVM->aCpus[i];
1677 PPGMCPU pPGM = &pVCpu->pgm.s;
1678
1679#define PGM_REG_COUNTER(a, b, c) \
1680 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
1681 AssertRC(rc);
1682#define PGM_REG_PROFILE(a, b, c) \
1683 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
1684 AssertRC(rc);
1685
1686 PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
1687
1688#ifdef VBOX_WITH_STATISTICS
1689
1690# if 0 /* rarely useful; leave for debugging. */
1691 for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPtPD); j++)
1692 STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1693 "The number of SyncPT per PD n.", "/PGM/CPU%d/PDSyncPT/%04X", i, j);
1694 for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPagePD); j++)
1695 STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1696 "The number of SyncPage per PD n.", "/PGM/CPU%d/PDSyncPage/%04X", i, j);
1697# endif
1698 /* R0 only: */
1699 PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1700 PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1701 PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1702 PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1703 PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1704 PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1705 PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1706 PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1707 PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1708 PGM_REG_COUNTER(&pPGM->StatR0DynMapPage, "/PGM/CPU%d/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1709 PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1710 PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1711 PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
1712 PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1713 PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1714 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits0, "/PGM/CPU%d/R0/DynMapPage/Hits0", "Hits at iPage+0");
1715 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits1, "/PGM/CPU%d/R0/DynMapPage/Hits1", "Hits at iPage+1");
1716 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits2, "/PGM/CPU%d/R0/DynMapPage/Hits2", "Hits at iPage+2");
1717 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1718 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1719 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1720 PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1721 //PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
1722 PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1723 PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1724 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[0], "/PGM/CPU%d/R0/SetSize000..09", "00-09% filled");
1725 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[1], "/PGM/CPU%d/R0/SetSize010..19", "10-19% filled");
1726 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[2], "/PGM/CPU%d/R0/SetSize020..29", "20-29% filled");
1727 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[3], "/PGM/CPU%d/R0/SetSize030..39", "30-39% filled");
1728 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[4], "/PGM/CPU%d/R0/SetSize040..49", "40-49% filled");
1729 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[5], "/PGM/CPU%d/R0/SetSize050..59", "50-59% filled");
1730 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[6], "/PGM/CPU%d/R0/SetSize060..69", "60-69% filled");
1731 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[7], "/PGM/CPU%d/R0/SetSize070..79", "70-79% filled");
1732 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[8], "/PGM/CPU%d/R0/SetSize080..89", "80-89% filled");
1733 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[9], "/PGM/CPU%d/R0/SetSize090..99", "90-99% filled");
1734 PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[10], "/PGM/CPU%d/R0/SetSize100", "100% filled");
1735
1736 /* RZ only: */
1737 PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1738 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1739 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1740 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1741 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1742 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1743 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1744 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1745 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1746 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1747 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1748 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1749 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1750 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1751 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1752 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1753 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1754 PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1755 PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1756 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1757 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1758 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1759 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1760 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1761 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1762 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1763 PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1764 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1765 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1766 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1767 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1768 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1769 PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1770 PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1771 PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1772 PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1773 PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1774 PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1775 PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1776 PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1777 PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1778 PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1779 PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1780#if 0 /* rarely useful; leave for debugging. */
1781 for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatRZTrap0ePD); j++)
1782 STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1783 "The number of traps in page directory n.", "/PGM/CPU%d/RZ/Trap0e/PD/%04X", i, j);
1784#endif
1785 PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1786 PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1787 PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1788 PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1789 PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1790
1791 /* HC only: */
1792
1793 /* RZ & R3: */
1794 PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1795 PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1796 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1797 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1798 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1799 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1800 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1801 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1802 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1803 PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1804 PGM_REG_PROFILE(&pPGM->StatRZSyncPT, "/PGM/CPU%d/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1805 PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1806 PGM_REG_COUNTER(&pPGM->StatRZSyncPT4K, "/PGM/CPU%d/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1807 PGM_REG_COUNTER(&pPGM->StatRZSyncPT4M, "/PGM/CPU%d/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1808 PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1809 PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1810 PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1811 PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1812 PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1813 PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1814 PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1815 PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1816 PGM_REG_COUNTER(&pPGM->StatRZDirtyPageStale, "/PGM/CPU%d/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1817 PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1818 PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1819 PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1820 PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1821 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1822 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1823 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1824 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1825 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1826 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1827 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1828 PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1829 PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1830 PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1831 PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%d/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1832 PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%d/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1833 PGM_REG_PROFILE(&pPGM->StatRZPrefetch, "/PGM/CPU%d/RZ/Prefetch", "PGMPrefetchPage profiling.");
1834 PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1835 PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1836 PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1837 PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1838 PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1839 PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1840
1841 PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1842 PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1843 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1844 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1845 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1846 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1847 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1848 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1849 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1850 PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1851 PGM_REG_PROFILE(&pPGM->StatR3SyncPT, "/PGM/CPU%d/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1852 PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1853 PGM_REG_COUNTER(&pPGM->StatR3SyncPT4K, "/PGM/CPU%d/R3/SyncPT/4K", "Nr of 4K PT syncs");
1854 PGM_REG_COUNTER(&pPGM->StatR3SyncPT4M, "/PGM/CPU%d/R3/SyncPT/4M", "Nr of 4M PT syncs");
1855 PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1856 PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1857 PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1858 PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1859 PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1860 PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1861 PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1862 PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1863 PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1864 PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1865 PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1866 PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1867 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1868 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1869 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1870 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1871 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1872 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1873 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1874 PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1875 PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1876 PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1877 PGM_REG_PROFILE(&pPGM->StatR3Prefetch, "/PGM/CPU%d/R3/Prefetch", "PGMPrefetchPage profiling.");
1878 PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1879 PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1880 PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1881 PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1882 PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1883 PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1884#endif /* VBOX_WITH_STATISTICS */
1885
1886#undef PGM_REG_PROFILE
1887#undef PGM_REG_COUNTER
1888
1889 }
1890}
1891
1892
1893/**
1894 * Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1895 *
1896 * The dynamic mapping area will also be allocated and initialized at this
1897 * time. We could allocate it during PGMR3Init of course, but the mapping
1898 * wouldn't be allocated at that time preventing us from setting up the
1899 * page table entries with the dummy page.
1900 *
1901 * @returns VBox status code.
1902 * @param pVM VM handle.
1903 */
1904VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1905{
1906 RTGCPTR GCPtr;
1907 int rc;
1908
1909 /*
1910 * Reserve space for the dynamic mappings.
1911 */
1912 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1913 if (RT_SUCCESS(rc))
1914 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1915
1916 if ( RT_SUCCESS(rc)
1917 && (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1918 {
1919 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1920 if (RT_SUCCESS(rc))
1921 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1922 }
1923 if (RT_SUCCESS(rc))
1924 {
1925 AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1926 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1927 }
1928 return rc;
1929}
1930
1931
1932/**
1933 * Ring-3 init finalizing.
1934 *
1935 * @returns VBox status code.
1936 * @param pVM The VM handle.
1937 */
1938VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1939{
1940 int rc;
1941
1942 /*
1943 * Reserve space for the dynamic mappings.
1944 * Initialize the dynamic mapping pages with dummy pages to simply the cache.
1945 */
1946 /* get the pointer to the page table entries. */
1947 PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1948 AssertRelease(pMapping);
1949 const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1950 const unsigned iPT = off >> X86_PD_SHIFT;
1951 const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1952 pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1953 pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1954
1955 /* init cache */
1956 RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1957 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1958 pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1959
1960 for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1961 {
1962 rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1963 AssertRCReturn(rc, rc);
1964 }
1965
1966 /*
1967 * Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1968 * Intel only goes up to 36 bits, so we stick to 36 as well.
1969 */
1970 /** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1971 uint32_t u32Dummy, u32Features;
1972 CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1973
1974 if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1975 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1976 else
1977 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1978
1979 /*
1980 * Allocate memory if we're supposed to do that.
1981 */
1982 if (pVM->pgm.s.fRamPreAlloc)
1983 rc = pgmR3PhysRamPreAllocate(pVM);
1984
1985 LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1986 return rc;
1987}
1988
1989
1990/**
1991 * Applies relocations to data and code managed by this component.
1992 *
1993 * This function will be called at init and whenever the VMM need to relocate it
1994 * self inside the GC.
1995 *
1996 * @param pVM The VM.
1997 * @param offDelta Relocation delta relative to old location.
1998 */
1999VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2000{
2001 LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2002
2003 /*
2004 * Paging stuff.
2005 */
2006 pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2007
2008 pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2009
2010 /* Shadow, guest and both mode switch & relocation for each VCPU. */
2011 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2012 {
2013 PVMCPU pVCpu = &pVM->aCpus[i];
2014
2015 pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2016
2017 PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2018 PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2019 PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2020 }
2021
2022 /*
2023 * Trees.
2024 */
2025 pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2026
2027 /*
2028 * Ram ranges.
2029 */
2030 if (pVM->pgm.s.pRamRangesR3)
2031 {
2032 /* Update the pSelfRC pointers and relink them. */
2033 for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2034 if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2035 pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2036 pgmR3PhysRelinkRamRanges(pVM);
2037 }
2038
2039 /*
2040 * Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2041 * be mapped and thus not included in the above exercise.
2042 */
2043 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2044 if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2045 pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2046
2047 /*
2048 * Update the two page directories with all page table mappings.
2049 * (One or more of them have changed, that's why we're here.)
2050 */
2051 pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2052 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2053 pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2054
2055 /* Relocate GC addresses of Page Tables. */
2056 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2057 {
2058 for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2059 {
2060 pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2061 pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2062 }
2063 }
2064
2065 /*
2066 * Dynamic page mapping area.
2067 */
2068 pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2069 pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2070 pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2071
2072 /*
2073 * The Zero page.
2074 */
2075 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2076#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2077 AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
2078#else
2079 AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2080#endif
2081
2082 /*
2083 * Physical and virtual handlers.
2084 */
2085 RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2086 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2087 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2088
2089 /*
2090 * The page pool.
2091 */
2092 pgmR3PoolRelocate(pVM);
2093}
2094
2095
2096/**
2097 * Callback function for relocating a physical access handler.
2098 *
2099 * @returns 0 (continue enum)
2100 * @param pNode Pointer to a PGMPHYSHANDLER node.
2101 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2102 * not certain the delta will fit in a void pointer for all possible configs.
2103 */
2104static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2105{
2106 PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2107 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2108 if (pHandler->pfnHandlerRC)
2109 pHandler->pfnHandlerRC += offDelta;
2110 if (pHandler->pvUserRC >= 0x10000)
2111 pHandler->pvUserRC += offDelta;
2112 return 0;
2113}
2114
2115
2116/**
2117 * Callback function for relocating a virtual access handler.
2118 *
2119 * @returns 0 (continue enum)
2120 * @param pNode Pointer to a PGMVIRTHANDLER node.
2121 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2122 * not certain the delta will fit in a void pointer for all possible configs.
2123 */
2124static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2125{
2126 PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2127 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2128 Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2129 || pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2130 Assert(pHandler->pfnHandlerRC);
2131 pHandler->pfnHandlerRC += offDelta;
2132 return 0;
2133}
2134
2135
2136/**
2137 * Callback function for relocating a virtual access handler for the hypervisor mapping.
2138 *
2139 * @returns 0 (continue enum)
2140 * @param pNode Pointer to a PGMVIRTHANDLER node.
2141 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2142 * not certain the delta will fit in a void pointer for all possible configs.
2143 */
2144static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2145{
2146 PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2147 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2148 Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2149 Assert(pHandler->pfnHandlerRC);
2150 pHandler->pfnHandlerRC += offDelta;
2151 return 0;
2152}
2153
2154
2155/**
2156 * The VM is being reset.
2157 *
2158 * For the PGM component this means that any PD write monitors
2159 * needs to be removed.
2160 *
2161 * @param pVM VM handle.
2162 */
2163VMMR3DECL(void) PGMR3Reset(PVM pVM)
2164{
2165 int rc;
2166
2167 LogFlow(("PGMR3Reset:\n"));
2168 VM_ASSERT_EMT(pVM);
2169
2170 pgmLock(pVM);
2171
2172 /*
2173 * Unfix any fixed mappings and disable CR3 monitoring.
2174 */
2175 pVM->pgm.s.fMappingsFixed = false;
2176 pVM->pgm.s.GCPtrMappingFixed = 0;
2177 pVM->pgm.s.cbMappingFixed = 0;
2178
2179 /* Exit the guest paging mode before the pgm pool gets reset.
2180 * Important to clean up the amd64 case.
2181 */
2182 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2183 {
2184 PVMCPU pVCpu = &pVM->aCpus[i];
2185 rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2186 AssertRC(rc);
2187 }
2188
2189#ifdef DEBUG
2190 DBGFR3InfoLog(pVM, "mappings", NULL);
2191 DBGFR3InfoLog(pVM, "handlers", "all nostat");
2192#endif
2193
2194 /*
2195 * Switch mode back to real mode. (before resetting the pgm pool!)
2196 */
2197 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2198 {
2199 PVMCPU pVCpu = &pVM->aCpus[i];
2200
2201 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2202 AssertRC(rc);
2203
2204 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2205 }
2206
2207 /*
2208 * Reset the shadow page pool.
2209 */
2210 pgmR3PoolReset(pVM);
2211
2212 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2213 {
2214 PVMCPU pVCpu = &pVM->aCpus[i];
2215
2216 /*
2217 * Re-init other members.
2218 */
2219 pVCpu->pgm.s.fA20Enabled = true;
2220
2221 /*
2222 * Clear the FFs PGM owns.
2223 */
2224 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2225 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2226 }
2227
2228 /*
2229 * Reset (zero) RAM pages.
2230 */
2231 rc = pgmR3PhysRamReset(pVM);
2232 if (RT_SUCCESS(rc))
2233 {
2234 /*
2235 * Reset (zero) shadow ROM pages.
2236 */
2237 rc = pgmR3PhysRomReset(pVM);
2238 }
2239
2240 pgmUnlock(pVM);
2241 //return rc;
2242 AssertReleaseRC(rc);
2243}
2244
2245
2246#ifdef VBOX_STRICT
2247/**
2248 * VM state change callback for clearing fNoMorePhysWrites after
2249 * a snapshot has been created.
2250 */
2251static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2252{
2253 if (enmState == VMSTATE_RUNNING)
2254 pVM->pgm.s.fNoMorePhysWrites = false;
2255}
2256#endif
2257
2258
2259/**
2260 * Terminates the PGM.
2261 *
2262 * @returns VBox status code.
2263 * @param pVM Pointer to VM structure.
2264 */
2265VMMR3DECL(int) PGMR3Term(PVM pVM)
2266{
2267 PGMDeregisterStringFormatTypes();
2268 return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2269}
2270
2271
2272/**
2273 * Terminates the per-VCPU PGM.
2274 *
2275 * Termination means cleaning up and freeing all resources,
2276 * the VM it self is at this point powered off or suspended.
2277 *
2278 * @returns VBox status code.
2279 * @param pVM The VM to operate on.
2280 */
2281VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2282{
2283 return 0;
2284}
2285
2286
2287/**
2288 * Show paging mode.
2289 *
2290 * @param pVM VM Handle.
2291 * @param pHlp The info helpers.
2292 * @param pszArgs "all" (default), "guest", "shadow" or "host".
2293 */
2294static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2295{
2296 /* digest argument. */
2297 bool fGuest, fShadow, fHost;
2298 if (pszArgs)
2299 pszArgs = RTStrStripL(pszArgs);
2300 if (!pszArgs || !*pszArgs || strstr(pszArgs, "all"))
2301 fShadow = fHost = fGuest = true;
2302 else
2303 {
2304 fShadow = fHost = fGuest = false;
2305 if (strstr(pszArgs, "guest"))
2306 fGuest = true;
2307 if (strstr(pszArgs, "shadow"))
2308 fShadow = true;
2309 if (strstr(pszArgs, "host"))
2310 fHost = true;
2311 }
2312
2313 /** @todo SMP support! */
2314 /* print info. */
2315 if (fGuest)
2316 pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2317 PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2318 pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2319 if (fShadow)
2320 pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2321 if (fHost)
2322 {
2323 const char *psz;
2324 switch (pVM->pgm.s.enmHostMode)
2325 {
2326 case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2327 case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2328 case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2329 case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2330 case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2331 case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2332 case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2333 case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2334 case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2335 case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2336 case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2337 default: psz = "unknown"; break;
2338 }
2339 pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2340 }
2341}
2342
2343
2344/**
2345 * Dump registered MMIO ranges to the log.
2346 *
2347 * @param pVM VM Handle.
2348 * @param pHlp The info helpers.
2349 * @param pszArgs Arguments, ignored.
2350 */
2351static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2352{
2353 NOREF(pszArgs);
2354 pHlp->pfnPrintf(pHlp,
2355 "RAM ranges (pVM=%p)\n"
2356 "%.*s %.*s\n",
2357 pVM,
2358 sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2359 sizeof(RTHCPTR) * 2, "pvHC ");
2360
2361 for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2362 pHlp->pfnPrintf(pHlp,
2363 "%RGp-%RGp %RHv %s\n",
2364 pCur->GCPhys,
2365 pCur->GCPhysLast,
2366 pCur->pvR3,
2367 pCur->pszDesc);
2368}
2369
2370/**
2371 * Dump the page directory to the log.
2372 *
2373 * @param pVM VM Handle.
2374 * @param pHlp The info helpers.
2375 * @param pszArgs Arguments, ignored.
2376 */
2377static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2378{
2379 /** @todo SMP support!! */
2380 PVMCPU pVCpu = &pVM->aCpus[0];
2381
2382/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2383 /* Big pages supported? */
2384 const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2385
2386 /* Global pages supported? */
2387 const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2388
2389 NOREF(pszArgs);
2390
2391 /*
2392 * Get page directory addresses.
2393 */
2394 PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2395 Assert(pPDSrc);
2396 Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2397
2398 /*
2399 * Iterate the page directory.
2400 */
2401 for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2402 {
2403 X86PDE PdeSrc = pPDSrc->a[iPD];
2404 if (PdeSrc.n.u1Present)
2405 {
2406 if (PdeSrc.b.u1Size && fPSE)
2407 pHlp->pfnPrintf(pHlp,
2408 "%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2409 iPD,
2410 pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2411 PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2412 else
2413 pHlp->pfnPrintf(pHlp,
2414 "%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2415 iPD,
2416 (RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2417 PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2418 }
2419 }
2420}
2421
2422
2423/**
2424 * Service a VMMCALLRING3_PGM_LOCK call.
2425 *
2426 * @returns VBox status code.
2427 * @param pVM The VM handle.
2428 */
2429VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2430{
2431 int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2432 AssertRC(rc);
2433 return rc;
2434}
2435
2436
2437/**
2438 * Converts a PGMMODE value to a PGM_TYPE_* \#define.
2439 *
2440 * @returns PGM_TYPE_*.
2441 * @param pgmMode The mode value to convert.
2442 */
2443DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2444{
2445 switch (pgmMode)
2446 {
2447 case PGMMODE_REAL: return PGM_TYPE_REAL;
2448 case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2449 case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2450 case PGMMODE_PAE:
2451 case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2452 case PGMMODE_AMD64:
2453 case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2454 case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2455 case PGMMODE_EPT: return PGM_TYPE_EPT;
2456 default:
2457 AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2458 }
2459}
2460
2461
2462/**
2463 * Gets the index into the paging mode data array of a SHW+GST mode.
2464 *
2465 * @returns PGM::paPagingData index.
2466 * @param uShwType The shadow paging mode type.
2467 * @param uGstType The guest paging mode type.
2468 */
2469DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2470{
2471 Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2472 Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2473 return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2474 + (uGstType - PGM_TYPE_REAL);
2475}
2476
2477
2478/**
2479 * Gets the index into the paging mode data array of a SHW+GST mode.
2480 *
2481 * @returns PGM::paPagingData index.
2482 * @param enmShw The shadow paging mode.
2483 * @param enmGst The guest paging mode.
2484 */
2485DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2486{
2487 Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2488 Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2489 return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2490}
2491
2492
2493/**
2494 * Calculates the max data index.
2495 * @returns The number of entries in the paging data array.
2496 */
2497DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2498{
2499 return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2500}
2501
2502
2503/**
2504 * Initializes the paging mode data kept in PGM::paModeData.
2505 *
2506 * @param pVM The VM handle.
2507 * @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2508 * This is used early in the init process to avoid trouble with PDM
2509 * not being initialized yet.
2510 */
2511static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2512{
2513 PPGMMODEDATA pModeData;
2514 int rc;
2515
2516 /*
2517 * Allocate the array on the first call.
2518 */
2519 if (!pVM->pgm.s.paModeData)
2520 {
2521 pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2522 AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2523 }
2524
2525 /*
2526 * Initialize the array entries.
2527 */
2528 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2529 pModeData->uShwType = PGM_TYPE_32BIT;
2530 pModeData->uGstType = PGM_TYPE_REAL;
2531 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2532 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2533 rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2534
2535 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2536 pModeData->uShwType = PGM_TYPE_32BIT;
2537 pModeData->uGstType = PGM_TYPE_PROT;
2538 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2539 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2540 rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2541
2542 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2543 pModeData->uShwType = PGM_TYPE_32BIT;
2544 pModeData->uGstType = PGM_TYPE_32BIT;
2545 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2546 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2547 rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2548
2549 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2550 pModeData->uShwType = PGM_TYPE_PAE;
2551 pModeData->uGstType = PGM_TYPE_REAL;
2552 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2553 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2554 rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2555
2556 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2557 pModeData->uShwType = PGM_TYPE_PAE;
2558 pModeData->uGstType = PGM_TYPE_PROT;
2559 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2560 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2561 rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2562
2563 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2564 pModeData->uShwType = PGM_TYPE_PAE;
2565 pModeData->uGstType = PGM_TYPE_32BIT;
2566 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2567 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2568 rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2569
2570 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2571 pModeData->uShwType = PGM_TYPE_PAE;
2572 pModeData->uGstType = PGM_TYPE_PAE;
2573 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2574 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2575 rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2576
2577#ifdef VBOX_WITH_64_BITS_GUESTS
2578 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2579 pModeData->uShwType = PGM_TYPE_AMD64;
2580 pModeData->uGstType = PGM_TYPE_AMD64;
2581 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2582 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2583 rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2584#endif
2585
2586 /* The nested paging mode. */
2587 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2588 pModeData->uShwType = PGM_TYPE_NESTED;
2589 pModeData->uGstType = PGM_TYPE_REAL;
2590 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2591 rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2592
2593 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2594 pModeData->uShwType = PGM_TYPE_NESTED;
2595 pModeData->uGstType = PGM_TYPE_PROT;
2596 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2597 rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2598
2599 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2600 pModeData->uShwType = PGM_TYPE_NESTED;
2601 pModeData->uGstType = PGM_TYPE_32BIT;
2602 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2603 rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2604
2605 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2606 pModeData->uShwType = PGM_TYPE_NESTED;
2607 pModeData->uGstType = PGM_TYPE_PAE;
2608 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2609 rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2610
2611#ifdef VBOX_WITH_64_BITS_GUESTS
2612 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2613 pModeData->uShwType = PGM_TYPE_NESTED;
2614 pModeData->uGstType = PGM_TYPE_AMD64;
2615 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2616 rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2617#endif
2618
2619 /* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2620 switch (pVM->pgm.s.enmHostMode)
2621 {
2622#if HC_ARCH_BITS == 32
2623 case SUPPAGINGMODE_32_BIT:
2624 case SUPPAGINGMODE_32_BIT_GLOBAL:
2625 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2626 {
2627 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2628 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2629 }
2630# ifdef VBOX_WITH_64_BITS_GUESTS
2631 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2632 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2633# endif
2634 break;
2635
2636 case SUPPAGINGMODE_PAE:
2637 case SUPPAGINGMODE_PAE_NX:
2638 case SUPPAGINGMODE_PAE_GLOBAL:
2639 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2640 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2641 {
2642 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2643 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2644 }
2645# ifdef VBOX_WITH_64_BITS_GUESTS
2646 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2647 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2648# endif
2649 break;
2650#endif /* HC_ARCH_BITS == 32 */
2651
2652#if HC_ARCH_BITS == 64 || defined(RT_OS_DARWIN)
2653 case SUPPAGINGMODE_AMD64:
2654 case SUPPAGINGMODE_AMD64_GLOBAL:
2655 case SUPPAGINGMODE_AMD64_NX:
2656 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2657# ifdef VBOX_WITH_64_BITS_GUESTS
2658 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2659# else
2660 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2661# endif
2662 {
2663 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2664 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2665 }
2666 break;
2667#endif /* HC_ARCH_BITS == 64 || RT_OS_DARWIN */
2668
2669 default:
2670 AssertFailed();
2671 break;
2672 }
2673
2674 /* Extended paging (EPT) / Intel VT-x */
2675 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2676 pModeData->uShwType = PGM_TYPE_EPT;
2677 pModeData->uGstType = PGM_TYPE_REAL;
2678 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2679 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2680 rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2681
2682 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2683 pModeData->uShwType = PGM_TYPE_EPT;
2684 pModeData->uGstType = PGM_TYPE_PROT;
2685 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2686 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2687 rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2688
2689 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2690 pModeData->uShwType = PGM_TYPE_EPT;
2691 pModeData->uGstType = PGM_TYPE_32BIT;
2692 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2693 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2694 rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2695
2696 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2697 pModeData->uShwType = PGM_TYPE_EPT;
2698 pModeData->uGstType = PGM_TYPE_PAE;
2699 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2700 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2701 rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2702
2703#ifdef VBOX_WITH_64_BITS_GUESTS
2704 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2705 pModeData->uShwType = PGM_TYPE_EPT;
2706 pModeData->uGstType = PGM_TYPE_AMD64;
2707 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2708 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2709 rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2710#endif
2711 return VINF_SUCCESS;
2712}
2713
2714
2715/**
2716 * Switch to different (or relocated in the relocate case) mode data.
2717 *
2718 * @param pVM The VM handle.
2719 * @param pVCpu The VMCPU to operate on.
2720 * @param enmShw The the shadow paging mode.
2721 * @param enmGst The the guest paging mode.
2722 */
2723static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2724{
2725 PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2726
2727 Assert(pModeData->uGstType == pgmModeToType(enmGst));
2728 Assert(pModeData->uShwType == pgmModeToType(enmShw));
2729
2730 /* shadow */
2731 pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2732 pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2733 pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2734 Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2735 pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2736
2737 pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2738 pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2739
2740 pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2741 pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2742
2743
2744 /* guest */
2745 pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2746 pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2747 pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2748 Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2749 pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2750 pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2751 pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2752 pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2753 pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2754 pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2755 pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2756 pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2757
2758 /* both */
2759 pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2760 pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2761 pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2762 Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2763 pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2764 pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2765 pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2766#ifdef VBOX_STRICT
2767 pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2768#endif
2769 pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2770 pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2771
2772 pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2773 pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2774 pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2775 pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2776 pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2777 pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2778#ifdef VBOX_STRICT
2779 pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2780#endif
2781 pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2782 pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2783
2784 pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2785 pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2786 pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2787 pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2788 pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2789 pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2790#ifdef VBOX_STRICT
2791 pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2792#endif
2793 pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2794 pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
2795}
2796
2797
2798/**
2799 * Calculates the shadow paging mode.
2800 *
2801 * @returns The shadow paging mode.
2802 * @param pVM VM handle.
2803 * @param enmGuestMode The guest mode.
2804 * @param enmHostMode The host mode.
2805 * @param enmShadowMode The current shadow mode.
2806 * @param penmSwitcher Where to store the switcher to use.
2807 * VMMSWITCHER_INVALID means no change.
2808 */
2809static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2810{
2811 VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2812 switch (enmGuestMode)
2813 {
2814 /*
2815 * When switching to real or protected mode we don't change
2816 * anything since it's likely that we'll switch back pretty soon.
2817 *
2818 * During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2819 * and is supposed to determine which shadow paging and switcher to
2820 * use during init.
2821 */
2822 case PGMMODE_REAL:
2823 case PGMMODE_PROTECTED:
2824 if ( enmShadowMode != PGMMODE_INVALID
2825 && !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2826 break; /* (no change) */
2827
2828 switch (enmHostMode)
2829 {
2830 case SUPPAGINGMODE_32_BIT:
2831 case SUPPAGINGMODE_32_BIT_GLOBAL:
2832 enmShadowMode = PGMMODE_32_BIT;
2833 enmSwitcher = VMMSWITCHER_32_TO_32;
2834 break;
2835
2836 case SUPPAGINGMODE_PAE:
2837 case SUPPAGINGMODE_PAE_NX:
2838 case SUPPAGINGMODE_PAE_GLOBAL:
2839 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2840 enmShadowMode = PGMMODE_PAE;
2841 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2842#ifdef DEBUG_bird
2843 if (RTEnvExist("VBOX_32BIT"))
2844 {
2845 enmShadowMode = PGMMODE_32_BIT;
2846 enmSwitcher = VMMSWITCHER_PAE_TO_32;
2847 }
2848#endif
2849 break;
2850
2851 case SUPPAGINGMODE_AMD64:
2852 case SUPPAGINGMODE_AMD64_GLOBAL:
2853 case SUPPAGINGMODE_AMD64_NX:
2854 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2855 enmShadowMode = PGMMODE_PAE;
2856 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2857#ifdef DEBUG_bird
2858 if (RTEnvExist("VBOX_32BIT"))
2859 {
2860 enmShadowMode = PGMMODE_32_BIT;
2861 enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2862 }
2863#endif
2864 break;
2865
2866 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2867 }
2868 break;
2869
2870 case PGMMODE_32_BIT:
2871 switch (enmHostMode)
2872 {
2873 case SUPPAGINGMODE_32_BIT:
2874 case SUPPAGINGMODE_32_BIT_GLOBAL:
2875 enmShadowMode = PGMMODE_32_BIT;
2876 enmSwitcher = VMMSWITCHER_32_TO_32;
2877 break;
2878
2879 case SUPPAGINGMODE_PAE:
2880 case SUPPAGINGMODE_PAE_NX:
2881 case SUPPAGINGMODE_PAE_GLOBAL:
2882 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2883 enmShadowMode = PGMMODE_PAE;
2884 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2885#ifdef DEBUG_bird
2886 if (RTEnvExist("VBOX_32BIT"))
2887 {
2888 enmShadowMode = PGMMODE_32_BIT;
2889 enmSwitcher = VMMSWITCHER_PAE_TO_32;
2890 }
2891#endif
2892 break;
2893
2894 case SUPPAGINGMODE_AMD64:
2895 case SUPPAGINGMODE_AMD64_GLOBAL:
2896 case SUPPAGINGMODE_AMD64_NX:
2897 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2898 enmShadowMode = PGMMODE_PAE;
2899 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2900#ifdef DEBUG_bird
2901 if (RTEnvExist("VBOX_32BIT"))
2902 {
2903 enmShadowMode = PGMMODE_32_BIT;
2904 enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2905 }
2906#endif
2907 break;
2908
2909 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2910 }
2911 break;
2912
2913 case PGMMODE_PAE:
2914 case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2915 switch (enmHostMode)
2916 {
2917 case SUPPAGINGMODE_32_BIT:
2918 case SUPPAGINGMODE_32_BIT_GLOBAL:
2919 enmShadowMode = PGMMODE_PAE;
2920 enmSwitcher = VMMSWITCHER_32_TO_PAE;
2921 break;
2922
2923 case SUPPAGINGMODE_PAE:
2924 case SUPPAGINGMODE_PAE_NX:
2925 case SUPPAGINGMODE_PAE_GLOBAL:
2926 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2927 enmShadowMode = PGMMODE_PAE;
2928 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2929 break;
2930
2931 case SUPPAGINGMODE_AMD64:
2932 case SUPPAGINGMODE_AMD64_GLOBAL:
2933 case SUPPAGINGMODE_AMD64_NX:
2934 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2935 enmShadowMode = PGMMODE_PAE;
2936 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2937 break;
2938
2939 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2940 }
2941 break;
2942
2943 case PGMMODE_AMD64:
2944 case PGMMODE_AMD64_NX:
2945 switch (enmHostMode)
2946 {
2947 case SUPPAGINGMODE_32_BIT:
2948 case SUPPAGINGMODE_32_BIT_GLOBAL:
2949 enmShadowMode = PGMMODE_AMD64;
2950 enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2951 break;
2952
2953 case SUPPAGINGMODE_PAE:
2954 case SUPPAGINGMODE_PAE_NX:
2955 case SUPPAGINGMODE_PAE_GLOBAL:
2956 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2957 enmShadowMode = PGMMODE_AMD64;
2958 enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2959 break;
2960
2961 case SUPPAGINGMODE_AMD64:
2962 case SUPPAGINGMODE_AMD64_GLOBAL:
2963 case SUPPAGINGMODE_AMD64_NX:
2964 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2965 enmShadowMode = PGMMODE_AMD64;
2966 enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2967 break;
2968
2969 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2970 }
2971 break;
2972
2973
2974 default:
2975 AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2976 return PGMMODE_INVALID;
2977 }
2978 /* Override the shadow mode is nested paging is active. */
2979 if (HWACCMIsNestedPagingActive(pVM))
2980 enmShadowMode = HWACCMGetShwPagingMode(pVM);
2981
2982 *penmSwitcher = enmSwitcher;
2983 return enmShadowMode;
2984}
2985
2986
2987/**
2988 * Performs the actual mode change.
2989 * This is called by PGMChangeMode and pgmR3InitPaging().
2990 *
2991 * @returns VBox status code. May suspend or power off the VM on error, but this
2992 * will trigger using FFs and not status codes.
2993 *
2994 * @param pVM VM handle.
2995 * @param pVCpu The VMCPU to operate on.
2996 * @param enmGuestMode The new guest mode. This is assumed to be different from
2997 * the current mode.
2998 */
2999VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3000{
3001 bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3002 bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3003
3004 Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3005 STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3006
3007 /*
3008 * Calc the shadow mode and switcher.
3009 */
3010 VMMSWITCHER enmSwitcher;
3011 PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3012 if (enmSwitcher != VMMSWITCHER_INVALID)
3013 {
3014 /*
3015 * Select new switcher.
3016 */
3017 int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3018 if (RT_FAILURE(rc))
3019 {
3020 AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3021 return rc;
3022 }
3023 }
3024
3025 /*
3026 * Exit old mode(s).
3027 */
3028#if HC_ARCH_BITS == 32
3029 /* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3030 const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3031 && enmShadowMode == PGMMODE_NESTED);
3032#else
3033 const bool fForceShwEnterExit = false;
3034#endif
3035 /* shadow */
3036 if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3037 || fForceShwEnterExit)
3038 {
3039 LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3040 if (PGM_SHW_PFN(Exit, pVCpu))
3041 {
3042 int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3043 if (RT_FAILURE(rc))
3044 {
3045 AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3046 return rc;
3047 }
3048 }
3049
3050 }
3051 else
3052 LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3053
3054 /* guest */
3055 if (PGM_GST_PFN(Exit, pVCpu))
3056 {
3057 int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3058 if (RT_FAILURE(rc))
3059 {
3060 AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3061 return rc;
3062 }
3063 }
3064
3065 /*
3066 * Load new paging mode data.
3067 */
3068 pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3069
3070 /*
3071 * Enter new shadow mode (if changed).
3072 */
3073 if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3074 || fForceShwEnterExit)
3075 {
3076 int rc;
3077 pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3078 switch (enmShadowMode)
3079 {
3080 case PGMMODE_32_BIT:
3081 rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3082 break;
3083 case PGMMODE_PAE:
3084 case PGMMODE_PAE_NX:
3085 rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3086 break;
3087 case PGMMODE_AMD64:
3088 case PGMMODE_AMD64_NX:
3089 rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3090 break;
3091 case PGMMODE_NESTED:
3092 rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3093 break;
3094 case PGMMODE_EPT:
3095 rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3096 break;
3097 case PGMMODE_REAL:
3098 case PGMMODE_PROTECTED:
3099 default:
3100 AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3101 return VERR_INTERNAL_ERROR;
3102 }
3103 if (RT_FAILURE(rc))
3104 {
3105 AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3106 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3107 return rc;
3108 }
3109 }
3110
3111 /*
3112 * Always flag the necessary updates
3113 */
3114 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3115
3116 /*
3117 * Enter the new guest and shadow+guest modes.
3118 */
3119 int rc = -1;
3120 int rc2 = -1;
3121 RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3122 pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3123 switch (enmGuestMode)
3124 {
3125 case PGMMODE_REAL:
3126 rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3127 switch (pVCpu->pgm.s.enmShadowMode)
3128 {
3129 case PGMMODE_32_BIT:
3130 rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3131 break;
3132 case PGMMODE_PAE:
3133 case PGMMODE_PAE_NX:
3134 rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3135 break;
3136 case PGMMODE_NESTED:
3137 rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3138 break;
3139 case PGMMODE_EPT:
3140 rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3141 break;
3142 case PGMMODE_AMD64:
3143 case PGMMODE_AMD64_NX:
3144 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3145 default: AssertFailed(); break;
3146 }
3147 break;
3148
3149 case PGMMODE_PROTECTED:
3150 rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3151 switch (pVCpu->pgm.s.enmShadowMode)
3152 {
3153 case PGMMODE_32_BIT:
3154 rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3155 break;
3156 case PGMMODE_PAE:
3157 case PGMMODE_PAE_NX:
3158 rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3159 break;
3160 case PGMMODE_NESTED:
3161 rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3162 break;
3163 case PGMMODE_EPT:
3164 rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3165 break;
3166 case PGMMODE_AMD64:
3167 case PGMMODE_AMD64_NX:
3168 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3169 default: AssertFailed(); break;
3170 }
3171 break;
3172
3173 case PGMMODE_32_BIT:
3174 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3175 rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3176 switch (pVCpu->pgm.s.enmShadowMode)
3177 {
3178 case PGMMODE_32_BIT:
3179 rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3180 break;
3181 case PGMMODE_PAE:
3182 case PGMMODE_PAE_NX:
3183 rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3184 break;
3185 case PGMMODE_NESTED:
3186 rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3187 break;
3188 case PGMMODE_EPT:
3189 rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3190 break;
3191 case PGMMODE_AMD64:
3192 case PGMMODE_AMD64_NX:
3193 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3194 default: AssertFailed(); break;
3195 }
3196 break;
3197
3198 case PGMMODE_PAE_NX:
3199 case PGMMODE_PAE:
3200 {
3201 uint32_t u32Dummy, u32Features;
3202
3203 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3204 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3205 return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3206 N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3207
3208 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3209 rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3210 switch (pVCpu->pgm.s.enmShadowMode)
3211 {
3212 case PGMMODE_PAE:
3213 case PGMMODE_PAE_NX:
3214 rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3215 break;
3216 case PGMMODE_NESTED:
3217 rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3218 break;
3219 case PGMMODE_EPT:
3220 rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3221 break;
3222 case PGMMODE_32_BIT:
3223 case PGMMODE_AMD64:
3224 case PGMMODE_AMD64_NX:
3225 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3226 default: AssertFailed(); break;
3227 }
3228 break;
3229 }
3230
3231#ifdef VBOX_WITH_64_BITS_GUESTS
3232 case PGMMODE_AMD64_NX:
3233 case PGMMODE_AMD64:
3234 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3235 rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3236 switch (pVCpu->pgm.s.enmShadowMode)
3237 {
3238 case PGMMODE_AMD64:
3239 case PGMMODE_AMD64_NX:
3240 rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3241 break;
3242 case PGMMODE_NESTED:
3243 rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3244 break;
3245 case PGMMODE_EPT:
3246 rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3247 break;
3248 case PGMMODE_32_BIT:
3249 case PGMMODE_PAE:
3250 case PGMMODE_PAE_NX:
3251 AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3252 default: AssertFailed(); break;
3253 }
3254 break;
3255#endif
3256
3257 default:
3258 AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3259 rc = VERR_NOT_IMPLEMENTED;
3260 break;
3261 }
3262
3263 /* status codes. */
3264 AssertRC(rc);
3265 AssertRC(rc2);
3266 if (RT_SUCCESS(rc))
3267 {
3268 rc = rc2;
3269 if (RT_SUCCESS(rc)) /* no informational status codes. */
3270 rc = VINF_SUCCESS;
3271 }
3272
3273 /* Notify HWACCM as well. */
3274 HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3275 return rc;
3276}
3277
3278/**
3279 * Release the pgm lock if owned by the current VCPU
3280 *
3281 * @param pVM The VM to operate on.
3282 */
3283VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
3284{
3285 while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
3286 PDMCritSectLeave(&pVM->pgm.s.CritSect);
3287}
3288
3289/**
3290 * Called by pgmPoolFlushAllInt prior to flushing the pool.
3291 *
3292 * @returns VBox status code, fully asserted.
3293 * @param pVM The VM handle.
3294 * @param pVCpu The VMCPU to operate on.
3295 */
3296int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3297{
3298 /* Unmap the old CR3 value before flushing everything. */
3299 int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3300 AssertRC(rc);
3301
3302 /* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3303 rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3304 AssertRC(rc);
3305 Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3306 return rc;
3307}
3308
3309
3310/**
3311 * Called by pgmPoolFlushAllInt after flushing the pool.
3312 *
3313 * @returns VBox status code, fully asserted.
3314 * @param pVM The VM handle.
3315 * @param pVCpu The VMCPU to operate on.
3316 */
3317int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3318{
3319 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3320 int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3321 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3322 AssertRCReturn(rc, rc);
3323 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3324
3325 Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3326 AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3327 || CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3328 ("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3329 return rc;
3330}
3331
3332
3333/**
3334 * Dumps a PAE shadow page table.
3335 *
3336 * @returns VBox status code (VINF_SUCCESS).
3337 * @param pVM The VM handle.
3338 * @param pPT Pointer to the page table.
3339 * @param u64Address The virtual address of the page table starts.
3340 * @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3341 * @param cMaxDepth The maxium depth.
3342 * @param pHlp Pointer to the output functions.
3343 */
3344static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3345{
3346 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3347 {
3348 X86PTEPAE Pte = pPT->a[i];
3349 if (Pte.n.u1Present)
3350 {
3351 pHlp->pfnPrintf(pHlp,
3352 fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
3353 ? "%016llx 3 | P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3354 : "%08llx 2 | P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3355 u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3356 Pte.n.u1Write ? 'W' : 'R',
3357 Pte.n.u1User ? 'U' : 'S',
3358 Pte.n.u1Accessed ? 'A' : '-',
3359 Pte.n.u1Dirty ? 'D' : '-',
3360 Pte.n.u1Global ? 'G' : '-',
3361 Pte.n.u1WriteThru ? "WT" : "--",
3362 Pte.n.u1CacheDisable? "CD" : "--",
3363 Pte.n.u1PAT ? "AT" : "--",
3364 Pte.n.u1NoExecute ? "NX" : "--",
3365 Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3366 Pte.u & RT_BIT(10) ? '1' : '0',
3367 Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3368 Pte.u & X86_PTE_PAE_PG_MASK);
3369 }
3370 }
3371 return VINF_SUCCESS;
3372}
3373
3374
3375/**
3376 * Dumps a PAE shadow page directory table.
3377 *
3378 * @returns VBox status code (VINF_SUCCESS).
3379 * @param pVM The VM handle.
3380 * @param HCPhys The physical address of the page directory table.
3381 * @param u64Address The virtual address of the page table starts.
3382 * @param cr4 The CR4, PSE is currently used.
3383 * @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3384 * @param cMaxDepth The maxium depth.
3385 * @param pHlp Pointer to the output functions.
3386 */
3387static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3388{
3389 PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3390 if (!pPD)
3391 {
3392 pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3393 fLongMode ? 16 : 8, u64Address, HCPhys);
3394 return VERR_INVALID_PARAMETER;
3395 }
3396 const bool fBigPagesSupported = fLongMode || !!(cr4 & X86_CR4_PSE);
3397
3398 int rc = VINF_SUCCESS;
3399 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3400 {
3401 X86PDEPAE Pde = pPD->a[i];
3402 if (Pde.n.u1Present)
3403 {
3404 if (fBigPagesSupported && Pde.b.u1Size)
3405 pHlp->pfnPrintf(pHlp,
3406 fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
3407 ? "%016llx 2 | P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3408 : "%08llx 1 | P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3409 u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3410 Pde.b.u1Write ? 'W' : 'R',
3411 Pde.b.u1User ? 'U' : 'S',
3412 Pde.b.u1Accessed ? 'A' : '-',
3413 Pde.b.u1Dirty ? 'D' : '-',
3414 Pde.b.u1Global ? 'G' : '-',
3415 Pde.b.u1WriteThru ? "WT" : "--",
3416 Pde.b.u1CacheDisable? "CD" : "--",
3417 Pde.b.u1PAT ? "AT" : "--",
3418 Pde.b.u1NoExecute ? "NX" : "--",
3419 Pde.u & RT_BIT_64(9) ? '1' : '0',
3420 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3421 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3422 Pde.u & X86_PDE_PAE_PG_MASK);
3423 else
3424 {
3425 pHlp->pfnPrintf(pHlp,
3426 fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
3427 ? "%016llx 2 | P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3428 : "%08llx 1 | P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3429 u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3430 Pde.n.u1Write ? 'W' : 'R',
3431 Pde.n.u1User ? 'U' : 'S',
3432 Pde.n.u1Accessed ? 'A' : '-',
3433 Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3434 Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3435 Pde.n.u1WriteThru ? "WT" : "--",
3436 Pde.n.u1CacheDisable? "CD" : "--",
3437 Pde.n.u1NoExecute ? "NX" : "--",
3438 Pde.u & RT_BIT_64(9) ? '1' : '0',
3439 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3440 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3441 Pde.u & X86_PDE_PAE_PG_MASK);
3442 if (cMaxDepth >= 1)
3443 {
3444 /** @todo what about using the page pool for mapping PTs? */
3445 uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3446 RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3447 PX86PTPAE pPT = NULL;
3448 if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3449 pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3450 else
3451 {
3452 for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3453 {
3454 uint64_t off = u64AddressPT - pMap->GCPtr;
3455 if (off < pMap->cb)
3456 {
3457 const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3458 const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3459 if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3460 pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3461 fLongMode ? 16 : 8, u64AddressPT, iPDE,
3462 iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3463 pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3464 }
3465 }
3466 }
3467 int rc2 = VERR_INVALID_PARAMETER;
3468 if (pPT)
3469 rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3470 else
3471 pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3472 fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3473 if (rc2 < rc && RT_SUCCESS(rc))
3474 rc = rc2;
3475 }
3476 }
3477 }
3478 }
3479 return rc;
3480}
3481
3482
3483/**
3484 * Dumps a PAE shadow page directory pointer table.
3485 *
3486 * @returns VBox status code (VINF_SUCCESS).
3487 * @param pVM The VM handle.
3488 * @param HCPhys The physical address of the page directory pointer table.
3489 * @param u64Address The virtual address of the page table starts.
3490 * @param cr4 The CR4, PSE is currently used.
3491 * @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3492 * @param cMaxDepth The maxium depth.
3493 * @param pHlp Pointer to the output functions.
3494 */
3495static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3496{
3497 PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3498 if (!pPDPT)
3499 {
3500 pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3501 fLongMode ? 16 : 8, u64Address, HCPhys);
3502 return VERR_INVALID_PARAMETER;
3503 }
3504
3505 int rc = VINF_SUCCESS;
3506 const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3507 for (unsigned i = 0; i < c; i++)
3508 {
3509 X86PDPE Pdpe = pPDPT->a[i];
3510 if (Pdpe.n.u1Present)
3511 {
3512 if (fLongMode)
3513 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a p ? */
3514 "%016llx 1 | P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3515 u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3516 Pdpe.lm.u1Write ? 'W' : 'R',
3517 Pdpe.lm.u1User ? 'U' : 'S',
3518 Pdpe.lm.u1Accessed ? 'A' : '-',
3519 Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3520 Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3521 Pdpe.lm.u1WriteThru ? "WT" : "--",
3522 Pdpe.lm.u1CacheDisable? "CD" : "--",
3523 Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3524 Pdpe.lm.u1NoExecute ? "NX" : "--",
3525 Pdpe.u & RT_BIT(9) ? '1' : '0',
3526 Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3527 Pdpe.u & RT_BIT(11) ? '1' : '0',
3528 Pdpe.u & X86_PDPE_PG_MASK);
3529 else
3530 pHlp->pfnPrintf(pHlp, /*P G WT CD AT NX 4M a p ? */
3531 "%08x 0 | P %c %s %s %s %s .. %c%c%c %016llx\n",
3532 i << X86_PDPT_SHIFT,
3533 Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3534 Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3535 Pdpe.n.u1WriteThru ? "WT" : "--",
3536 Pdpe.n.u1CacheDisable? "CD" : "--",
3537 Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3538 Pdpe.u & RT_BIT(9) ? '1' : '0',
3539 Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3540 Pdpe.u & RT_BIT(11) ? '1' : '0',
3541 Pdpe.u & X86_PDPE_PG_MASK);
3542 if (cMaxDepth >= 1)
3543 {
3544 int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3545 cr4, fLongMode, cMaxDepth - 1, pHlp);
3546 if (rc2 < rc && RT_SUCCESS(rc))
3547 rc = rc2;
3548 }
3549 }
3550 }
3551 return rc;
3552}
3553
3554
3555/**
3556 * Dumps a 32-bit shadow page table.
3557 *
3558 * @returns VBox status code (VINF_SUCCESS).
3559 * @param pVM The VM handle.
3560 * @param HCPhys The physical address of the table.
3561 * @param cr4 The CR4, PSE is currently used.
3562 * @param cMaxDepth The maxium depth.
3563 * @param pHlp Pointer to the output functions.
3564 */
3565static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3566{
3567 PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3568 if (!pPML4)
3569 {
3570 pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3571 return VERR_INVALID_PARAMETER;
3572 }
3573
3574 int rc = VINF_SUCCESS;
3575 for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3576 {
3577 X86PML4E Pml4e = pPML4->a[i];
3578 if (Pml4e.n.u1Present)
3579 {
3580 uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) | (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3581 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a p ? */
3582 "%016llx 0 | P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3583 u64Address,
3584 Pml4e.n.u1Write ? 'W' : 'R',
3585 Pml4e.n.u1User ? 'U' : 'S',
3586 Pml4e.n.u1Accessed ? 'A' : '-',
3587 Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3588 Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3589 Pml4e.n.u1WriteThru ? "WT" : "--",
3590 Pml4e.n.u1CacheDisable? "CD" : "--",
3591 Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3592 Pml4e.n.u1NoExecute ? "NX" : "--",
3593 Pml4e.u & RT_BIT(9) ? '1' : '0',
3594 Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3595 Pml4e.u & RT_BIT(11) ? '1' : '0',
3596 Pml4e.u & X86_PML4E_PG_MASK);
3597
3598 if (cMaxDepth >= 1)
3599 {
3600 int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3601 if (rc2 < rc && RT_SUCCESS(rc))
3602 rc = rc2;
3603 }
3604 }
3605 }
3606 return rc;
3607}
3608
3609
3610/**
3611 * Dumps a 32-bit shadow page table.
3612 *
3613 * @returns VBox status code (VINF_SUCCESS).
3614 * @param pVM The VM handle.
3615 * @param pPT Pointer to the page table.
3616 * @param u32Address The virtual address this table starts at.
3617 * @param pHlp Pointer to the output functions.
3618 */
3619int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3620{
3621 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3622 {
3623 X86PTE Pte = pPT->a[i];
3624 if (Pte.n.u1Present)
3625 {
3626 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a m d */
3627 "%08x 1 | P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3628 u32Address + (i << X86_PT_SHIFT),
3629 Pte.n.u1Write ? 'W' : 'R',
3630 Pte.n.u1User ? 'U' : 'S',
3631 Pte.n.u1Accessed ? 'A' : '-',
3632 Pte.n.u1Dirty ? 'D' : '-',
3633 Pte.n.u1Global ? 'G' : '-',
3634 Pte.n.u1WriteThru ? "WT" : "--",
3635 Pte.n.u1CacheDisable? "CD" : "--",
3636 Pte.n.u1PAT ? "AT" : "--",
3637 Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3638 Pte.u & RT_BIT(10) ? '1' : '0',
3639 Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3640 Pte.u & X86_PDE_PG_MASK);
3641 }
3642 }
3643 return VINF_SUCCESS;
3644}
3645
3646
3647/**
3648 * Dumps a 32-bit shadow page directory and page tables.
3649 *
3650 * @returns VBox status code (VINF_SUCCESS).
3651 * @param pVM The VM handle.
3652 * @param cr3 The root of the hierarchy.
3653 * @param cr4 The CR4, PSE is currently used.
3654 * @param cMaxDepth How deep into the hierarchy the dumper should go.
3655 * @param pHlp Pointer to the output functions.
3656 */
3657int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3658{
3659 PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3660 if (!pPD)
3661 {
3662 pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3663 return VERR_INVALID_PARAMETER;
3664 }
3665
3666 int rc = VINF_SUCCESS;
3667 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3668 {
3669 X86PDE Pde = pPD->a[i];
3670 if (Pde.n.u1Present)
3671 {
3672 const uint32_t u32Address = i << X86_PD_SHIFT;
3673 if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3674 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a m d */
3675 "%08x 0 | P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3676 u32Address,
3677 Pde.b.u1Write ? 'W' : 'R',
3678 Pde.b.u1User ? 'U' : 'S',
3679 Pde.b.u1Accessed ? 'A' : '-',
3680 Pde.b.u1Dirty ? 'D' : '-',
3681 Pde.b.u1Global ? 'G' : '-',
3682 Pde.b.u1WriteThru ? "WT" : "--",
3683 Pde.b.u1CacheDisable? "CD" : "--",
3684 Pde.b.u1PAT ? "AT" : "--",
3685 Pde.u & RT_BIT_64(9) ? '1' : '0',
3686 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3687 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3688 Pde.u & X86_PDE4M_PG_MASK);
3689 else
3690 {
3691 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a m d */
3692 "%08x 0 | P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3693 u32Address,
3694 Pde.n.u1Write ? 'W' : 'R',
3695 Pde.n.u1User ? 'U' : 'S',
3696 Pde.n.u1Accessed ? 'A' : '-',
3697 Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3698 Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3699 Pde.n.u1WriteThru ? "WT" : "--",
3700 Pde.n.u1CacheDisable? "CD" : "--",
3701 Pde.u & RT_BIT_64(9) ? '1' : '0',
3702 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3703 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3704 Pde.u & X86_PDE_PG_MASK);
3705 if (cMaxDepth >= 1)
3706 {
3707 /** @todo what about using the page pool for mapping PTs? */
3708 RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3709 PX86PT pPT = NULL;
3710 if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3711 pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3712 else
3713 {
3714 for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3715 if (u32Address - pMap->GCPtr < pMap->cb)
3716 {
3717 int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3718 if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3719 pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3720 u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3721 pPT = pMap->aPTs[iPDE].pPTR3;
3722 }
3723 }
3724 int rc2 = VERR_INVALID_PARAMETER;
3725 if (pPT)
3726 rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3727 else
3728 pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3729 if (rc2 < rc && RT_SUCCESS(rc))
3730 rc = rc2;
3731 }
3732 }
3733 }
3734 }
3735
3736 return rc;
3737}
3738
3739
3740/**
3741 * Dumps a 32-bit shadow page table.
3742 *
3743 * @returns VBox status code (VINF_SUCCESS).
3744 * @param pVM The VM handle.
3745 * @param pPT Pointer to the page table.
3746 * @param u32Address The virtual address this table starts at.
3747 * @param PhysSearch Address to search for.
3748 */
3749int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3750{
3751 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3752 {
3753 X86PTE Pte = pPT->a[i];
3754 if (Pte.n.u1Present)
3755 {
3756 Log(( /*P R S A D G WT CD AT NX 4M a m d */
3757 "%08x 1 | P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3758 u32Address + (i << X86_PT_SHIFT),
3759 Pte.n.u1Write ? 'W' : 'R',
3760 Pte.n.u1User ? 'U' : 'S',
3761 Pte.n.u1Accessed ? 'A' : '-',
3762 Pte.n.u1Dirty ? 'D' : '-',
3763 Pte.n.u1Global ? 'G' : '-',
3764 Pte.n.u1WriteThru ? "WT" : "--",
3765 Pte.n.u1CacheDisable? "CD" : "--",
3766 Pte.n.u1PAT ? "AT" : "--",
3767 Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3768 Pte.u & RT_BIT(10) ? '1' : '0',
3769 Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3770 Pte.u & X86_PDE_PG_MASK));
3771
3772 if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3773 {
3774 uint64_t fPageShw = 0;
3775 RTHCPHYS pPhysHC = 0;
3776
3777 /** @todo SMP support!! */
3778 PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3779 Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3780 }
3781 }
3782 }
3783 return VINF_SUCCESS;
3784}
3785
3786
3787/**
3788 * Dumps a 32-bit guest page directory and page tables.
3789 *
3790 * @returns VBox status code (VINF_SUCCESS).
3791 * @param pVM The VM handle.
3792 * @param cr3 The root of the hierarchy.
3793 * @param cr4 The CR4, PSE is currently used.
3794 * @param PhysSearch Address to search for.
3795 */
3796VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3797{
3798 bool fLongMode = false;
3799 const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3800 PX86PD pPD = 0;
3801
3802 int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3803 if (RT_FAILURE(rc) || !pPD)
3804 {
3805 Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3806 return VERR_INVALID_PARAMETER;
3807 }
3808
3809 Log(("cr3=%08x cr4=%08x%s\n"
3810 "%-*s P - Present\n"
3811 "%-*s | R/W - Read (0) / Write (1)\n"
3812 "%-*s | | U/S - User (1) / Supervisor (0)\n"
3813 "%-*s | | | A - Accessed\n"
3814 "%-*s | | | | D - Dirty\n"
3815 "%-*s | | | | | G - Global\n"
3816 "%-*s | | | | | | WT - Write thru\n"
3817 "%-*s | | | | | | | CD - Cache disable\n"
3818 "%-*s | | | | | | | | AT - Attribute table (PAT)\n"
3819 "%-*s | | | | | | | | | NX - No execute (K8)\n"
3820 "%-*s | | | | | | | | | | 4K/4M/2M - Page size.\n"
3821 "%-*s | | | | | | | | | | | AVL - a=allocated; m=mapping; d=track dirty;\n"
3822 "%-*s | | | | | | | | | | | | p=permanent; v=validated;\n"
3823 "%-*s Level | | | | | | | | | | | | Page\n"
3824 /* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3825 - W U - - - -- -- -- -- -- 010 */
3826 , cr3, cr4, fLongMode ? " Long Mode" : "",
3827 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3828 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3829
3830 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3831 {
3832 X86PDE Pde = pPD->a[i];
3833 if (Pde.n.u1Present)
3834 {
3835 const uint32_t u32Address = i << X86_PD_SHIFT;
3836
3837 if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3838 Log(( /*P R S A D G WT CD AT NX 4M a m d */
3839 "%08x 0 | P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3840 u32Address,
3841 Pde.b.u1Write ? 'W' : 'R',
3842 Pde.b.u1User ? 'U' : 'S',
3843 Pde.b.u1Accessed ? 'A' : '-',
3844 Pde.b.u1Dirty ? 'D' : '-',
3845 Pde.b.u1Global ? 'G' : '-',
3846 Pde.b.u1WriteThru ? "WT" : "--",
3847 Pde.b.u1CacheDisable? "CD" : "--",
3848 Pde.b.u1PAT ? "AT" : "--",
3849 Pde.u & RT_BIT(9) ? '1' : '0',
3850 Pde.u & RT_BIT(10) ? '1' : '0',
3851 Pde.u & RT_BIT(11) ? '1' : '0',
3852 pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3853 /** @todo PhysSearch */
3854 else
3855 {
3856 Log(( /*P R S A D G WT CD AT NX 4M a m d */
3857 "%08x 0 | P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3858 u32Address,
3859 Pde.n.u1Write ? 'W' : 'R',
3860 Pde.n.u1User ? 'U' : 'S',
3861 Pde.n.u1Accessed ? 'A' : '-',
3862 Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3863 Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3864 Pde.n.u1WriteThru ? "WT" : "--",
3865 Pde.n.u1CacheDisable? "CD" : "--",
3866 Pde.u & RT_BIT(9) ? '1' : '0',
3867 Pde.u & RT_BIT(10) ? '1' : '0',
3868 Pde.u & RT_BIT(11) ? '1' : '0',
3869 Pde.u & X86_PDE_PG_MASK));
3870 ////if (cMaxDepth >= 1)
3871 {
3872 /** @todo what about using the page pool for mapping PTs? */
3873 RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3874 PX86PT pPT = NULL;
3875
3876 rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3877
3878 int rc2 = VERR_INVALID_PARAMETER;
3879 if (pPT)
3880 rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3881 else
3882 Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3883 if (rc2 < rc && RT_SUCCESS(rc))
3884 rc = rc2;
3885 }
3886 }
3887 }
3888 }
3889
3890 return rc;
3891}
3892
3893
3894/**
3895 * Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3896 *
3897 * @returns VBox status code (VINF_SUCCESS).
3898 * @param pVM The VM handle.
3899 * @param cr3 The root of the hierarchy.
3900 * @param cr4 The cr4, only PAE and PSE is currently used.
3901 * @param fLongMode Set if long mode, false if not long mode.
3902 * @param cMaxDepth Number of levels to dump.
3903 * @param pHlp Pointer to the output functions.
3904 */
3905VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3906{
3907 if (!pHlp)
3908 pHlp = DBGFR3InfoLogHlp();
3909 if (!cMaxDepth)
3910 return VINF_SUCCESS;
3911 const unsigned cch = fLongMode ? 16 : 8;
3912 pHlp->pfnPrintf(pHlp,
3913 "cr3=%08x cr4=%08x%s\n"
3914 "%-*s P - Present\n"
3915 "%-*s | R/W - Read (0) / Write (1)\n"
3916 "%-*s | | U/S - User (1) / Supervisor (0)\n"
3917 "%-*s | | | A - Accessed\n"
3918 "%-*s | | | | D - Dirty\n"
3919 "%-*s | | | | | G - Global\n"
3920 "%-*s | | | | | | WT - Write thru\n"
3921 "%-*s | | | | | | | CD - Cache disable\n"
3922 "%-*s | | | | | | | | AT - Attribute table (PAT)\n"
3923 "%-*s | | | | | | | | | NX - No execute (K8)\n"
3924 "%-*s | | | | | | | | | | 4K/4M/2M - Page size.\n"
3925 "%-*s | | | | | | | | | | | AVL - a=allocated; m=mapping; d=track dirty;\n"
3926 "%-*s | | | | | | | | | | | | p=permanent; v=validated;\n"
3927 "%-*s Level | | | | | | | | | | | | Page\n"
3928 /* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3929 - W U - - - -- -- -- -- -- 010 */
3930 , cr3, cr4, fLongMode ? " Long Mode" : "",
3931 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3932 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3933 if (cr4 & X86_CR4_PAE)
3934 {
3935 if (fLongMode)
3936 return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3937 return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3938 }
3939 return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3940}
3941
3942#ifdef VBOX_WITH_DEBUGGER
3943
3944/**
3945 * The '.pgmram' command.
3946 *
3947 * @returns VBox status.
3948 * @param pCmd Pointer to the command descriptor (as registered).
3949 * @param pCmdHlp Pointer to command helper functions.
3950 * @param pVM Pointer to the current VM (if any).
3951 * @param paArgs Pointer to (readonly) array of arguments.
3952 * @param cArgs Number of arguments in the array.
3953 */
3954static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3955{
3956 /*
3957 * Validate input.
3958 */
3959 if (!pVM)
3960 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3961 if (!pVM->pgm.s.pRamRangesRC)
3962 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3963
3964 /*
3965 * Dump the ranges.
3966 */
3967 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3968 PPGMRAMRANGE pRam;
3969 for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
3970 {
3971 rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3972 "%RGp - %RGp %p\n",
3973 pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
3974 if (RT_FAILURE(rc))
3975 return rc;
3976 }
3977
3978 return VINF_SUCCESS;
3979}
3980
3981
3982/**
3983 * The '.pgmmap' command.
3984 *
3985 * @returns VBox status.
3986 * @param pCmd Pointer to the command descriptor (as registered).
3987 * @param pCmdHlp Pointer to command helper functions.
3988 * @param pVM Pointer to the current VM (if any).
3989 * @param paArgs Pointer to (readonly) array of arguments.
3990 * @param cArgs Number of arguments in the array.
3991 */
3992static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3993{
3994 /*
3995 * Validate input.
3996 */
3997 if (!pVM)
3998 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3999 if (!pVM->pgm.s.pMappingsR3)
4000 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4001
4002 /*
4003 * Print message about the fixedness of the mappings.
4004 */
4005 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4006 if (RT_FAILURE(rc))
4007 return rc;
4008
4009 /*
4010 * Dump the ranges.
4011 */
4012 PPGMMAPPING pCur;
4013 for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4014 {
4015 rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4016 "%08x - %08x %s\n",
4017 pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4018 if (RT_FAILURE(rc))
4019 return rc;
4020 }
4021
4022 return VINF_SUCCESS;
4023}
4024
4025
4026/**
4027 * The '.pgmerror' and '.pgmerroroff' commands.
4028 *
4029 * @returns VBox status.
4030 * @param pCmd Pointer to the command descriptor (as registered).
4031 * @param pCmdHlp Pointer to command helper functions.
4032 * @param pVM Pointer to the current VM (if any).
4033 * @param paArgs Pointer to (readonly) array of arguments.
4034 * @param cArgs Number of arguments in the array.
4035 */
4036static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4037{
4038 /*
4039 * Validate input.
4040 */
4041 if (!pVM)
4042 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4043 AssertReturn(cArgs == 0 || (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4044 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4045
4046 if (!cArgs)
4047 {
4048 /*
4049 * Print the list of error injection locations with status.
4050 */
4051 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4052 pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4053 }
4054 else
4055 {
4056
4057 /*
4058 * String switch on where to inject the error.
4059 */
4060 bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4061 const char *pszWhere = paArgs[0].u.pszString;
4062 if (!strcmp(pszWhere, "handy"))
4063 ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4064 else
4065 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4066 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4067 }
4068 return VINF_SUCCESS;
4069}
4070
4071
4072/**
4073 * The '.pgmsync' command.
4074 *
4075 * @returns VBox status.
4076 * @param pCmd Pointer to the command descriptor (as registered).
4077 * @param pCmdHlp Pointer to command helper functions.
4078 * @param pVM Pointer to the current VM (if any).
4079 * @param paArgs Pointer to (readonly) array of arguments.
4080 * @param cArgs Number of arguments in the array.
4081 */
4082static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4083{
4084 /** @todo SMP support */
4085 PVMCPU pVCpu = &pVM->aCpus[0];
4086
4087 /*
4088 * Validate input.
4089 */
4090 if (!pVM)
4091 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4092
4093 /*
4094 * Force page directory sync.
4095 */
4096 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4097
4098 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4099 if (RT_FAILURE(rc))
4100 return rc;
4101
4102 return VINF_SUCCESS;
4103}
4104
4105
4106#ifdef VBOX_STRICT
4107/**
4108 * The '.pgmassertcr3' command.
4109 *
4110 * @returns VBox status.
4111 * @param pCmd Pointer to the command descriptor (as registered).
4112 * @param pCmdHlp Pointer to command helper functions.
4113 * @param pVM Pointer to the current VM (if any).
4114 * @param paArgs Pointer to (readonly) array of arguments.
4115 * @param cArgs Number of arguments in the array.
4116 */
4117static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4118{
4119 /** @todo SMP support!! */
4120 PVMCPU pVCpu = &pVM->aCpus[0];
4121
4122 /*
4123 * Validate input.
4124 */
4125 if (!pVM)
4126 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4127
4128 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4129 if (RT_FAILURE(rc))
4130 return rc;
4131
4132 PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4133
4134 return VINF_SUCCESS;
4135}
4136#endif /* VBOX_STRICT */
4137
4138
4139/**
4140 * The '.pgmsyncalways' command.
4141 *
4142 * @returns VBox status.
4143 * @param pCmd Pointer to the command descriptor (as registered).
4144 * @param pCmdHlp Pointer to command helper functions.
4145 * @param pVM Pointer to the current VM (if any).
4146 * @param paArgs Pointer to (readonly) array of arguments.
4147 * @param cArgs Number of arguments in the array.
4148 */
4149static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4150{
4151 /** @todo SMP support!! */
4152 PVMCPU pVCpu = &pVM->aCpus[0];
4153
4154 /*
4155 * Validate input.
4156 */
4157 if (!pVM)
4158 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4159
4160 /*
4161 * Force page directory sync.
4162 */
4163 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4164 {
4165 ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4166 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4167 }
4168 else
4169 {
4170 ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4171 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4172 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4173 }
4174}
4175
4176
4177/**
4178 * The '.pgmsyncalways' command.
4179 *
4180 * @returns VBox status.
4181 * @param pCmd Pointer to the command descriptor (as registered).
4182 * @param pCmdHlp Pointer to command helper functions.
4183 * @param pVM Pointer to the current VM (if any).
4184 * @param paArgs Pointer to (readonly) array of arguments.
4185 * @param cArgs Number of arguments in the array.
4186 */
4187static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4188{
4189 /*
4190 * Validate input.
4191 */
4192 if (!pVM)
4193 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4194 if ( cArgs < 1
4195 || cArgs > 2
4196 || paArgs[0].enmType != DBGCVAR_TYPE_STRING
4197 || ( cArgs > 1
4198 && paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4199 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4200 if ( cArgs >= 2
4201 && strcmp(paArgs[1].u.pszString, "nozero"))
4202 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4203 bool fIncZeroPgs = cArgs < 2;
4204
4205 /*
4206 * Open the output file and get the ram parameters.
4207 */
4208 RTFILE hFile;
4209 int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE | RTFILE_O_CREATE_REPLACE | RTFILE_O_DENY_WRITE);
4210 if (RT_FAILURE(rc))
4211 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4212
4213 uint32_t cbRamHole = 0;
4214 CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4215 uint64_t cbRam = 0;
4216 CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4217 RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4218
4219 /*
4220 * Dump the physical memory, page by page.
4221 */
4222 RTGCPHYS GCPhys = 0;
4223 char abZeroPg[PAGE_SIZE];
4224 RT_ZERO(abZeroPg);
4225
4226 pgmLock(pVM);
4227 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4228 pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4229 pRam = pRam->pNextR3)
4230 {
4231 /* fill the gap */
4232 if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4233 {
4234 while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4235 {
4236 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4237 GCPhys += PAGE_SIZE;
4238 }
4239 }
4240
4241 PCPGMPAGE pPage = &pRam->aPages[0];
4242 while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4243 {
4244 if (PGM_PAGE_IS_ZERO(pPage))
4245 {
4246 if (fIncZeroPgs)
4247 {
4248 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4249 if (RT_FAILURE(rc))
4250 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4251 }
4252 }
4253 else
4254 {
4255 switch (PGM_PAGE_GET_TYPE(pPage))
4256 {
4257 case PGMPAGETYPE_RAM:
4258 case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4259 case PGMPAGETYPE_ROM:
4260 case PGMPAGETYPE_MMIO2:
4261 {
4262 void const *pvPage;
4263 PGMPAGEMAPLOCK Lock;
4264 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4265 if (RT_SUCCESS(rc))
4266 {
4267 rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4268 PGMPhysReleasePageMappingLock(pVM, &Lock);
4269 if (RT_FAILURE(rc))
4270 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4271 }
4272 else
4273 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4274 break;
4275 }
4276
4277 default:
4278 AssertFailed();
4279 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4280 case PGMPAGETYPE_MMIO:
4281 if (fIncZeroPgs)
4282 {
4283 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4284 if (RT_FAILURE(rc))
4285 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4286 }
4287 break;
4288 }
4289 }
4290
4291
4292 /* advance */
4293 GCPhys += PAGE_SIZE;
4294 pPage++;
4295 }
4296 }
4297 pgmUnlock(pVM);
4298
4299 RTFileClose(hFile);
4300 if (RT_SUCCESS(rc))
4301 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4302 return VINF_SUCCESS;
4303}
4304
4305#endif /* VBOX_WITH_DEBUGGER */
4306
4307/**
4308 * pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4309 */
4310typedef struct PGMCHECKINTARGS
4311{
4312 bool fLeftToRight; /**< true: left-to-right; false: right-to-left. */
4313 PPGMPHYSHANDLER pPrevPhys;
4314 PPGMVIRTHANDLER pPrevVirt;
4315 PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4316 PVM pVM;
4317} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4318
4319/**
4320 * Validate a node in the physical handler tree.
4321 *
4322 * @returns 0 on if ok, other wise 1.
4323 * @param pNode The handler node.
4324 * @param pvUser pVM.
4325 */
4326static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4327{
4328 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4329 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4330 AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4331 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4332 AssertReleaseMsg( !pArgs->pPrevPhys
4333 || (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4334 ("pPrevPhys=%p %RGp-%RGp %s\n"
4335 " pCur=%p %RGp-%RGp %s\n",
4336 pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4337 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4338 pArgs->pPrevPhys = pCur;
4339 return 0;
4340}
4341
4342
4343/**
4344 * Validate a node in the virtual handler tree.
4345 *
4346 * @returns 0 on if ok, other wise 1.
4347 * @param pNode The handler node.
4348 * @param pvUser pVM.
4349 */
4350static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4351{
4352 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4353 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4354 AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4355 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4356 AssertReleaseMsg( !pArgs->pPrevVirt
4357 || (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4358 ("pPrevVirt=%p %RGv-%RGv %s\n"
4359 " pCur=%p %RGv-%RGv %s\n",
4360 pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4361 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4362 for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4363 {
4364 AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4365 ("pCur=%p %RGv-%RGv %s\n"
4366 "iPage=%d offVirtHandle=%#x expected %#x\n",
4367 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4368 iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4369 }
4370 pArgs->pPrevVirt = pCur;
4371 return 0;
4372}
4373
4374
4375/**
4376 * Validate a node in the virtual handler tree.
4377 *
4378 * @returns 0 on if ok, other wise 1.
4379 * @param pNode The handler node.
4380 * @param pvUser pVM.
4381 */
4382static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4383{
4384 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4385 PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4386 AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4387 AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4388 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4389 AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4390 || (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4391 ("pPrevPhys2Virt=%p %RGp-%RGp\n"
4392 " pCur=%p %RGp-%RGp\n",
4393 pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4394 pCur, pCur->Core.Key, pCur->Core.KeyLast));
4395 AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4396 || (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4397 ("pPrevPhys2Virt=%p %RGp-%RGp\n"
4398 " pCur=%p %RGp-%RGp\n",
4399 pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4400 pCur, pCur->Core.Key, pCur->Core.KeyLast));
4401 AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD),
4402 ("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4403 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4404 if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4405 {
4406 PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4407 for (;;)
4408 {
4409 pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4410 AssertReleaseMsg(pCur2 != pCur,
4411 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4412 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4413 AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4414 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4415 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4416 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4417 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4418 AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4419 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4420 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4421 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4422 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4423 AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4424 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4425 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4426 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4427 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4428 if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4429 break;
4430 }
4431 }
4432
4433 pArgs->pPrevPhys2Virt = pCur;
4434 return 0;
4435}
4436
4437
4438/**
4439 * Perform an integrity check on the PGM component.
4440 *
4441 * @returns VINF_SUCCESS if everything is fine.
4442 * @returns VBox error status after asserting on integrity breach.
4443 * @param pVM The VM handle.
4444 */
4445VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4446{
4447 AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4448
4449 /*
4450 * Check the trees.
4451 */
4452 int cErrors = 0;
4453 const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4454 const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4455 PGMCHECKINTARGS Args = s_LeftToRight;
4456 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4457 Args = s_RightToLeft;
4458 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4459 Args = s_LeftToRight;
4460 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4461 Args = s_RightToLeft;
4462 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4463 Args = s_LeftToRight;
4464 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4465 Args = s_RightToLeft;
4466 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4467 Args = s_LeftToRight;
4468 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4469 Args = s_RightToLeft;
4470 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4471
4472 return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4473}
4474
4475
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