PGM.cpp@ 22793

Last change on this file since 22793 was 22793, checked in by vboxsync, 15 years ago
SSM,*: Renamed phase to pass (uPhase/SSM_PHASE_FINAL) and wrote the remainder of the live snapshot / migration SSM code.
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1	/* $Id: PGM.cpp 22793 2009-09-05 01:29:24Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/selm.h>
588	#include <VBox/ssm.h>
589	#include <VBox/hwaccm.h>
590	#include "PGMInternal.h"
591	#include <VBox/vm.h>
592
593	#include <VBox/dbg.h>
594	#include <VBox/param.h>
595	#include <VBox/err.h>
596
597	#include <iprt/asm.h>
598	#include <iprt/assert.h>
599	#include <iprt/env.h>
600	#include <iprt/mem.h>
601	#include <iprt/file.h>
602	#include <iprt/string.h>
603	#include <iprt/thread.h>
604
605
606	/*******************************************************************************
607	* Defined Constants And Macros *
608	*******************************************************************************/
609	/** Saved state data unit version for 2.5.x and later. */
610	#define PGM_SAVED_STATE_VERSION 9
611	/** Saved state data unit version for 2.2.2 and later. */
612	#define PGM_SAVED_STATE_VERSION_2_2_2 8
613	/** Saved state data unit version for 2.2.0. */
614	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
615	/** Saved state data unit version. */
616	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
617
618
619	/*******************************************************************************
620	* Internal Functions *
621	*******************************************************************************/
622	static int pgmR3InitPaging(PVM pVM);
623	static void pgmR3InitStats(PVM pVM);
624	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
625	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
626	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
628	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
629	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
630	#ifdef VBOX_STRICT
631	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
632	#endif
633	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
634	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
635	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
636	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
637	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
638
639	#ifdef VBOX_WITH_DEBUGGER
640	/** @todo Convert the first two commands to 'info' items. */
641	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
645	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	# ifdef VBOX_STRICT
647	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	# endif
649	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
650	#endif
651
652
653	/*******************************************************************************
654	* Global Variables *
655	*******************************************************************************/
656	#ifdef VBOX_WITH_DEBUGGER
657	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
658	static const DBGCVARDESC g_aPgmErrorArgs[] =
659	{
660	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
661	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
662	};
663
664	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
665	{
666	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
667	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
668	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
669	};
670
671	/** Command descriptors. */
672	static const DBGCCMD g_aCmds[] =
673	{
674	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
675	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
676	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
677	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
678	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
679	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
680	#ifdef VBOX_STRICT
681	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
682	#endif
683	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
684	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
685	};
686	#endif
687
688
689
690
691	/*
692	* Shadow - 32-bit mode
693	*/
694	#define PGM_SHW_TYPE PGM_TYPE_32BIT
695	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
696	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
697	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
698	#include "PGMShw.h"
699
700	/* Guest - real mode */
701	#define PGM_GST_TYPE PGM_TYPE_REAL
702	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
703	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
704	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
705	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
706	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
707	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
708	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
709	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
710	#include "PGMBth.h"
711	#include "PGMGstDefs.h"
712	#include "PGMGst.h"
713	#undef BTH_PGMPOOLKIND_PT_FOR_PT
714	#undef BTH_PGMPOOLKIND_ROOT
715	#undef PGM_BTH_NAME
716	#undef PGM_BTH_NAME_RC_STR
717	#undef PGM_BTH_NAME_R0_STR
718	#undef PGM_GST_TYPE
719	#undef PGM_GST_NAME
720	#undef PGM_GST_NAME_RC_STR
721	#undef PGM_GST_NAME_R0_STR
722
723	/* Guest - protected mode */
724	#define PGM_GST_TYPE PGM_TYPE_PROT
725	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
726	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
727	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
728	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
729	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
730	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
731	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
732	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
733	#include "PGMBth.h"
734	#include "PGMGstDefs.h"
735	#include "PGMGst.h"
736	#undef BTH_PGMPOOLKIND_PT_FOR_PT
737	#undef BTH_PGMPOOLKIND_ROOT
738	#undef PGM_BTH_NAME
739	#undef PGM_BTH_NAME_RC_STR
740	#undef PGM_BTH_NAME_R0_STR
741	#undef PGM_GST_TYPE
742	#undef PGM_GST_NAME
743	#undef PGM_GST_NAME_RC_STR
744	#undef PGM_GST_NAME_R0_STR
745
746	/* Guest - 32-bit mode */
747	#define PGM_GST_TYPE PGM_TYPE_32BIT
748	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
749	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
750	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
751	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
752	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
753	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
754	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
755	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
756	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
757	#include "PGMBth.h"
758	#include "PGMGstDefs.h"
759	#include "PGMGst.h"
760	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
761	#undef BTH_PGMPOOLKIND_PT_FOR_PT
762	#undef BTH_PGMPOOLKIND_ROOT
763	#undef PGM_BTH_NAME
764	#undef PGM_BTH_NAME_RC_STR
765	#undef PGM_BTH_NAME_R0_STR
766	#undef PGM_GST_TYPE
767	#undef PGM_GST_NAME
768	#undef PGM_GST_NAME_RC_STR
769	#undef PGM_GST_NAME_R0_STR
770
771	#undef PGM_SHW_TYPE
772	#undef PGM_SHW_NAME
773	#undef PGM_SHW_NAME_RC_STR
774	#undef PGM_SHW_NAME_R0_STR
775
776
777	/*
778	* Shadow - PAE mode
779	*/
780	#define PGM_SHW_TYPE PGM_TYPE_PAE
781	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
782	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
783	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
784	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
785	#include "PGMShw.h"
786
787	/* Guest - real mode */
788	#define PGM_GST_TYPE PGM_TYPE_REAL
789	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
790	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
791	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
792	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
793	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
794	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
795	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
796	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
797	#include "PGMGstDefs.h"
798	#include "PGMBth.h"
799	#undef BTH_PGMPOOLKIND_PT_FOR_PT
800	#undef BTH_PGMPOOLKIND_ROOT
801	#undef PGM_BTH_NAME
802	#undef PGM_BTH_NAME_RC_STR
803	#undef PGM_BTH_NAME_R0_STR
804	#undef PGM_GST_TYPE
805	#undef PGM_GST_NAME
806	#undef PGM_GST_NAME_RC_STR
807	#undef PGM_GST_NAME_R0_STR
808
809	/* Guest - protected mode */
810	#define PGM_GST_TYPE PGM_TYPE_PROT
811	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
812	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
813	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
814	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
815	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
816	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
817	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
818	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
819	#include "PGMGstDefs.h"
820	#include "PGMBth.h"
821	#undef BTH_PGMPOOLKIND_PT_FOR_PT
822	#undef BTH_PGMPOOLKIND_ROOT
823	#undef PGM_BTH_NAME
824	#undef PGM_BTH_NAME_RC_STR
825	#undef PGM_BTH_NAME_R0_STR
826	#undef PGM_GST_TYPE
827	#undef PGM_GST_NAME
828	#undef PGM_GST_NAME_RC_STR
829	#undef PGM_GST_NAME_R0_STR
830
831	/* Guest - 32-bit mode */
832	#define PGM_GST_TYPE PGM_TYPE_32BIT
833	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
834	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
835	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
836	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
837	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
838	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
839	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
840	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
841	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
842	#include "PGMGstDefs.h"
843	#include "PGMBth.h"
844	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
845	#undef BTH_PGMPOOLKIND_PT_FOR_PT
846	#undef BTH_PGMPOOLKIND_ROOT
847	#undef PGM_BTH_NAME
848	#undef PGM_BTH_NAME_RC_STR
849	#undef PGM_BTH_NAME_R0_STR
850	#undef PGM_GST_TYPE
851	#undef PGM_GST_NAME
852	#undef PGM_GST_NAME_RC_STR
853	#undef PGM_GST_NAME_R0_STR
854
855	/* Guest - PAE mode */
856	#define PGM_GST_TYPE PGM_TYPE_PAE
857	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
858	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
859	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
860	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
861	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
862	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
863	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
864	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
865	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
866	#include "PGMBth.h"
867	#include "PGMGstDefs.h"
868	#include "PGMGst.h"
869	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
870	#undef BTH_PGMPOOLKIND_PT_FOR_PT
871	#undef BTH_PGMPOOLKIND_ROOT
872	#undef PGM_BTH_NAME
873	#undef PGM_BTH_NAME_RC_STR
874	#undef PGM_BTH_NAME_R0_STR
875	#undef PGM_GST_TYPE
876	#undef PGM_GST_NAME
877	#undef PGM_GST_NAME_RC_STR
878	#undef PGM_GST_NAME_R0_STR
879
880	#undef PGM_SHW_TYPE
881	#undef PGM_SHW_NAME
882	#undef PGM_SHW_NAME_RC_STR
883	#undef PGM_SHW_NAME_R0_STR
884
885
886	/*
887	* Shadow - AMD64 mode
888	*/
889	#define PGM_SHW_TYPE PGM_TYPE_AMD64
890	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
891	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
892	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
893	#include "PGMShw.h"
894
895	#ifdef VBOX_WITH_64_BITS_GUESTS
896	/* Guest - AMD64 mode */
897	# define PGM_GST_TYPE PGM_TYPE_AMD64
898	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
899	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
900	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
901	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
902	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
903	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
904	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
905	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
906	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
907	# include "PGMBth.h"
908	# include "PGMGstDefs.h"
909	# include "PGMGst.h"
910	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
911	# undef BTH_PGMPOOLKIND_PT_FOR_PT
912	# undef BTH_PGMPOOLKIND_ROOT
913	# undef PGM_BTH_NAME
914	# undef PGM_BTH_NAME_RC_STR
915	# undef PGM_BTH_NAME_R0_STR
916	# undef PGM_GST_TYPE
917	# undef PGM_GST_NAME
918	# undef PGM_GST_NAME_RC_STR
919	# undef PGM_GST_NAME_R0_STR
920	#endif /* VBOX_WITH_64_BITS_GUESTS */
921
922	#undef PGM_SHW_TYPE
923	#undef PGM_SHW_NAME
924	#undef PGM_SHW_NAME_RC_STR
925	#undef PGM_SHW_NAME_R0_STR
926
927
928	/*
929	* Shadow - Nested paging mode
930	*/
931	#define PGM_SHW_TYPE PGM_TYPE_NESTED
932	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
933	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
934	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
935	#include "PGMShw.h"
936
937	/* Guest - real mode */
938	#define PGM_GST_TYPE PGM_TYPE_REAL
939	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
940	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
941	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
942	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
943	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
944	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
945	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
946	#include "PGMGstDefs.h"
947	#include "PGMBth.h"
948	#undef BTH_PGMPOOLKIND_PT_FOR_PT
949	#undef PGM_BTH_NAME
950	#undef PGM_BTH_NAME_RC_STR
951	#undef PGM_BTH_NAME_R0_STR
952	#undef PGM_GST_TYPE
953	#undef PGM_GST_NAME
954	#undef PGM_GST_NAME_RC_STR
955	#undef PGM_GST_NAME_R0_STR
956
957	/* Guest - protected mode */
958	#define PGM_GST_TYPE PGM_TYPE_PROT
959	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
960	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
961	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
962	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
963	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
964	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
965	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
966	#include "PGMGstDefs.h"
967	#include "PGMBth.h"
968	#undef BTH_PGMPOOLKIND_PT_FOR_PT
969	#undef PGM_BTH_NAME
970	#undef PGM_BTH_NAME_RC_STR
971	#undef PGM_BTH_NAME_R0_STR
972	#undef PGM_GST_TYPE
973	#undef PGM_GST_NAME
974	#undef PGM_GST_NAME_RC_STR
975	#undef PGM_GST_NAME_R0_STR
976
977	/* Guest - 32-bit mode */
978	#define PGM_GST_TYPE PGM_TYPE_32BIT
979	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
980	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
981	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
982	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
983	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
984	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
985	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
986	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
987	#include "PGMGstDefs.h"
988	#include "PGMBth.h"
989	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
990	#undef BTH_PGMPOOLKIND_PT_FOR_PT
991	#undef PGM_BTH_NAME
992	#undef PGM_BTH_NAME_RC_STR
993	#undef PGM_BTH_NAME_R0_STR
994	#undef PGM_GST_TYPE
995	#undef PGM_GST_NAME
996	#undef PGM_GST_NAME_RC_STR
997	#undef PGM_GST_NAME_R0_STR
998
999	/* Guest - PAE mode */
1000	#define PGM_GST_TYPE PGM_TYPE_PAE
1001	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1002	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1003	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1004	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1005	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1006	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1007	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1008	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1009	#include "PGMGstDefs.h"
1010	#include "PGMBth.h"
1011	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1012	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1013	#undef PGM_BTH_NAME
1014	#undef PGM_BTH_NAME_RC_STR
1015	#undef PGM_BTH_NAME_R0_STR
1016	#undef PGM_GST_TYPE
1017	#undef PGM_GST_NAME
1018	#undef PGM_GST_NAME_RC_STR
1019	#undef PGM_GST_NAME_R0_STR
1020
1021	#ifdef VBOX_WITH_64_BITS_GUESTS
1022	/* Guest - AMD64 mode */
1023	# define PGM_GST_TYPE PGM_TYPE_AMD64
1024	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1025	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1026	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1027	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1028	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1029	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1030	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1031	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1032	# include "PGMGstDefs.h"
1033	# include "PGMBth.h"
1034	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1035	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1036	# undef PGM_BTH_NAME
1037	# undef PGM_BTH_NAME_RC_STR
1038	# undef PGM_BTH_NAME_R0_STR
1039	# undef PGM_GST_TYPE
1040	# undef PGM_GST_NAME
1041	# undef PGM_GST_NAME_RC_STR
1042	# undef PGM_GST_NAME_R0_STR
1043	#endif /* VBOX_WITH_64_BITS_GUESTS */
1044
1045	#undef PGM_SHW_TYPE
1046	#undef PGM_SHW_NAME
1047	#undef PGM_SHW_NAME_RC_STR
1048	#undef PGM_SHW_NAME_R0_STR
1049
1050
1051	/*
1052	* Shadow - EPT
1053	*/
1054	#define PGM_SHW_TYPE PGM_TYPE_EPT
1055	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1056	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1057	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1058	#include "PGMShw.h"
1059
1060	/* Guest - real mode */
1061	#define PGM_GST_TYPE PGM_TYPE_REAL
1062	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1063	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1064	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1065	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1066	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1067	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1068	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1069	#include "PGMGstDefs.h"
1070	#include "PGMBth.h"
1071	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1072	#undef PGM_BTH_NAME
1073	#undef PGM_BTH_NAME_RC_STR
1074	#undef PGM_BTH_NAME_R0_STR
1075	#undef PGM_GST_TYPE
1076	#undef PGM_GST_NAME
1077	#undef PGM_GST_NAME_RC_STR
1078	#undef PGM_GST_NAME_R0_STR
1079
1080	/* Guest - protected mode */
1081	#define PGM_GST_TYPE PGM_TYPE_PROT
1082	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1083	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1084	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1085	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1086	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1087	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1088	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1089	#include "PGMGstDefs.h"
1090	#include "PGMBth.h"
1091	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1092	#undef PGM_BTH_NAME
1093	#undef PGM_BTH_NAME_RC_STR
1094	#undef PGM_BTH_NAME_R0_STR
1095	#undef PGM_GST_TYPE
1096	#undef PGM_GST_NAME
1097	#undef PGM_GST_NAME_RC_STR
1098	#undef PGM_GST_NAME_R0_STR
1099
1100	/* Guest - 32-bit mode */
1101	#define PGM_GST_TYPE PGM_TYPE_32BIT
1102	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1103	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1104	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1105	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1106	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1107	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1108	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1109	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1110	#include "PGMGstDefs.h"
1111	#include "PGMBth.h"
1112	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1113	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1114	#undef PGM_BTH_NAME
1115	#undef PGM_BTH_NAME_RC_STR
1116	#undef PGM_BTH_NAME_R0_STR
1117	#undef PGM_GST_TYPE
1118	#undef PGM_GST_NAME
1119	#undef PGM_GST_NAME_RC_STR
1120	#undef PGM_GST_NAME_R0_STR
1121
1122	/* Guest - PAE mode */
1123	#define PGM_GST_TYPE PGM_TYPE_PAE
1124	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1125	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1126	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1127	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1128	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1129	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1130	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1131	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1132	#include "PGMGstDefs.h"
1133	#include "PGMBth.h"
1134	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1135	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1136	#undef PGM_BTH_NAME
1137	#undef PGM_BTH_NAME_RC_STR
1138	#undef PGM_BTH_NAME_R0_STR
1139	#undef PGM_GST_TYPE
1140	#undef PGM_GST_NAME
1141	#undef PGM_GST_NAME_RC_STR
1142	#undef PGM_GST_NAME_R0_STR
1143
1144	#ifdef VBOX_WITH_64_BITS_GUESTS
1145	/* Guest - AMD64 mode */
1146	# define PGM_GST_TYPE PGM_TYPE_AMD64
1147	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1148	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1149	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1150	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1151	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1152	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1153	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1154	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1155	# include "PGMGstDefs.h"
1156	# include "PGMBth.h"
1157	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1158	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1159	# undef PGM_BTH_NAME
1160	# undef PGM_BTH_NAME_RC_STR
1161	# undef PGM_BTH_NAME_R0_STR
1162	# undef PGM_GST_TYPE
1163	# undef PGM_GST_NAME
1164	# undef PGM_GST_NAME_RC_STR
1165	# undef PGM_GST_NAME_R0_STR
1166	#endif /* VBOX_WITH_64_BITS_GUESTS */
1167
1168	#undef PGM_SHW_TYPE
1169	#undef PGM_SHW_NAME
1170	#undef PGM_SHW_NAME_RC_STR
1171	#undef PGM_SHW_NAME_R0_STR
1172
1173
1174
1175	/**
1176	* Initiates the paging of VM.
1177	*
1178	* @returns VBox status code.
1179	* @param pVM Pointer to VM structure.
1180	*/
1181	VMMR3DECL(int) PGMR3Init(PVM pVM)
1182	{
1183	LogFlow(("PGMR3Init:\n"));
1184	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1185	int rc;
1186
1187	/*
1188	* Assert alignment and sizes.
1189	*/
1190	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1191	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1192
1193	/*
1194	* Init the structure.
1195	*/
1196	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1197	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1198
1199	/* Init the per-CPU part. */
1200	for (unsigned i=0;i<pVM->cCPUs;i++)
1201	{
1202	PVMCPU pVCpu = &pVM->aCpus[i];
1203	PPGMCPU pPGM = &pVCpu->pgm.s;
1204
1205	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1206	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1207	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1208
1209	pPGM->enmShadowMode = PGMMODE_INVALID;
1210	pPGM->enmGuestMode = PGMMODE_INVALID;
1211
1212	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1213
1214	pPGM->pGstPaePdptR3 = NULL;
1215	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1216	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1217	#endif
1218	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1219	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1220	{
1221	pPGM->apGstPaePDsR3[i] = NULL;
1222	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1223	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1224	#endif
1225	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1226	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1227	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1228	}
1229
1230	pPGM->fA20Enabled = true;
1231	}
1232
1233	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1234	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1235	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1236
1237	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1238	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1239	true
1240	#else
1241	false
1242	#endif
1243	);
1244	AssertLogRelRCReturn(rc, rc);
1245
1246	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1247	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1248	#else
1249	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1250	#endif
1251	AssertLogRelRCReturn(rc, rc);
1252	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1253	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1254
1255	/*
1256	* Get the configured RAM size - to estimate saved state size.
1257	*/
1258	uint64_t cbRam;
1259	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1260	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1261	cbRam = 0;
1262	else if (RT_SUCCESS(rc))
1263	{
1264	if (cbRam < PAGE_SIZE)
1265	cbRam = 0;
1266	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1267	}
1268	else
1269	{
1270	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1271	return rc;
1272	}
1273
1274	/*
1275	* Register callbacks, string formatters and the saved state data unit.
1276	*/
1277	#ifdef VBOX_STRICT
1278	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1279	#endif
1280	PGMRegisterStringFormatTypes();
1281
1282	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1283	NULL, NULL, NULL,
1284	NULL, pgmR3Save, NULL,
1285	NULL, pgmR3Load, NULL);
1286	if (RT_FAILURE(rc))
1287	return rc;
1288
1289	/*
1290	* Initialize the PGM critical section and flush the phys TLBs
1291	*/
1292	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1293	AssertRCReturn(rc, rc);
1294
1295	PGMR3PhysChunkInvalidateTLB(pVM);
1296	PGMPhysInvalidatePageR3MapTLB(pVM);
1297	PGMPhysInvalidatePageR0MapTLB(pVM);
1298	PGMPhysInvalidatePageGCMapTLB(pVM);
1299
1300	/*
1301	* For the time being we sport a full set of handy pages in addition to the base
1302	* memory to simplify things.
1303	*/
1304	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1305	AssertRCReturn(rc, rc);
1306
1307	/*
1308	* Trees
1309	*/
1310	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1311	if (RT_SUCCESS(rc))
1312	{
1313	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1314	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1315
1316	/*
1317	* Alocate the zero page.
1318	*/
1319	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1320	}
1321	if (RT_SUCCESS(rc))
1322	{
1323	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1324	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1325	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1326	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1327
1328	/*
1329	* Init the paging.
1330	*/
1331	rc = pgmR3InitPaging(pVM);
1332	}
1333	if (RT_SUCCESS(rc))
1334	{
1335	/*
1336	* Init the page pool.
1337	*/
1338	rc = pgmR3PoolInit(pVM);
1339	}
1340	if (RT_SUCCESS(rc))
1341	{
1342	for (unsigned i=0;i<pVM->cCPUs;i++)
1343	{
1344	PVMCPU pVCpu = &pVM->aCpus[i];
1345
1346	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1347	if (RT_FAILURE(rc))
1348	break;
1349	}
1350	}
1351
1352	if (RT_SUCCESS(rc))
1353	{
1354	/*
1355	* Info & statistics
1356	*/
1357	DBGFR3InfoRegisterInternal(pVM, "mode",
1358	"Shows the current paging mode. "
1359	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1360	pgmR3InfoMode);
1361	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1362	"Dumps all the entries in the top level paging table. No arguments.",
1363	pgmR3InfoCr3);
1364	DBGFR3InfoRegisterInternal(pVM, "phys",
1365	"Dumps all the physical address ranges. No arguments.",
1366	pgmR3PhysInfo);
1367	DBGFR3InfoRegisterInternal(pVM, "handlers",
1368	"Dumps physical, virtual and hyper virtual handlers. "
1369	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1370	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1371	pgmR3InfoHandlers);
1372	DBGFR3InfoRegisterInternal(pVM, "mappings",
1373	"Dumps guest mappings.",
1374	pgmR3MapInfo);
1375
1376	pgmR3InitStats(pVM);
1377
1378	#ifdef VBOX_WITH_DEBUGGER
1379	/*
1380	* Debugger commands.
1381	*/
1382	static bool s_fRegisteredCmds = false;
1383	if (!s_fRegisteredCmds)
1384	{
1385	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1386	if (RT_SUCCESS(rc))
1387	s_fRegisteredCmds = true;
1388	}
1389	#endif
1390	return VINF_SUCCESS;
1391	}
1392
1393	/* Almost no cleanup necessary, MM frees all memory. */
1394	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1395
1396	return rc;
1397	}
1398
1399
1400	/**
1401	* Initializes the per-VCPU PGM.
1402	*
1403	* @returns VBox status code.
1404	* @param pVM The VM to operate on.
1405	*/
1406	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1407	{
1408	LogFlow(("PGMR3InitCPU\n"));
1409	return VINF_SUCCESS;
1410	}
1411
1412
1413	/**
1414	* Init paging.
1415	*
1416	* Since we need to check what mode the host is operating in before we can choose
1417	* the right paging functions for the host we have to delay this until R0 has
1418	* been initialized.
1419	*
1420	* @returns VBox status code.
1421	* @param pVM VM handle.
1422	*/
1423	static int pgmR3InitPaging(PVM pVM)
1424	{
1425	/*
1426	* Force a recalculation of modes and switcher so everyone gets notified.
1427	*/
1428	for (unsigned i=0;i<pVM->cCPUs;i++)
1429	{
1430	PVMCPU pVCpu = &pVM->aCpus[i];
1431
1432	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1433	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1434	}
1435
1436	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1437
1438	/*
1439	* Allocate static mapping space for whatever the cr3 register
1440	* points to and in the case of PAE mode to the 4 PDs.
1441	*/
1442	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1443	if (RT_FAILURE(rc))
1444	{
1445	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1446	return rc;
1447	}
1448	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1449
1450	/*
1451	* Allocate pages for the three possible intermediate contexts
1452	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1453	* for the sake of simplicity. The AMD64 uses the PAE for the
1454	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1455	*
1456	* We assume that two page tables will be enought for the core code
1457	* mappings (HC virtual and identity).
1458	*/
1459	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1460	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1463	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1464	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1465	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1466	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1467	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1468	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1469	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1470	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1471
1472	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1473	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1474	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1475	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1476	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1477	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1478
1479	/*
1480	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1481	*/
1482	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1483	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1484	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1485
1486	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1487	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1488
1489	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1490	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1491	{
1492	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1493	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1494	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1495	}
1496
1497	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1498	{
1499	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1500	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1501	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1502	}
1503
1504	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1505	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1506	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1507	\| HCPhysInterPaePDPT64;
1508
1509	/*
1510	* Initialize paging workers and mode from current host mode
1511	* and the guest running in real mode.
1512	*/
1513	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1514	switch (pVM->pgm.s.enmHostMode)
1515	{
1516	case SUPPAGINGMODE_32_BIT:
1517	case SUPPAGINGMODE_32_BIT_GLOBAL:
1518	case SUPPAGINGMODE_PAE:
1519	case SUPPAGINGMODE_PAE_GLOBAL:
1520	case SUPPAGINGMODE_PAE_NX:
1521	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1522	break;
1523
1524	case SUPPAGINGMODE_AMD64:
1525	case SUPPAGINGMODE_AMD64_GLOBAL:
1526	case SUPPAGINGMODE_AMD64_NX:
1527	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1528	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1529	if (ARCH_BITS != 64)
1530	{
1531	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1532	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1533	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1534	}
1535	#endif
1536	break;
1537	default:
1538	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1539	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1540	}
1541	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1542	if (RT_SUCCESS(rc))
1543	{
1544	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1545	#if HC_ARCH_BITS == 64
1546	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1547	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1548	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1549	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1550	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1551	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1552	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1553	#endif
1554
1555	return VINF_SUCCESS;
1556	}
1557
1558	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1559	return rc;
1560	}
1561
1562
1563	/**
1564	* Init statistics
1565	*/
1566	static void pgmR3InitStats(PVM pVM)
1567	{
1568	PPGM pPGM = &pVM->pgm.s;
1569	int rc;
1570
1571	/* Common - misc variables */
1572	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1573	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1574	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1575	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1576	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1577	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1578	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1579	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1580
1581	#ifdef VBOX_WITH_STATISTICS
1582
1583	# define PGM_REG_COUNTER(a, b, c) \
1584	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1585	AssertRC(rc);
1586
1587	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1588	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1589	AssertRC(rc);
1590
1591	# define PGM_REG_PROFILE(a, b, c) \
1592	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1593	AssertRC(rc);
1594
1595	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1596	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1597	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1598	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1599	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1600	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1601	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1602	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1603	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1604	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1605
1606	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1607	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1608	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1609	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1610	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1611	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1612	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1613	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1614
1615	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1616	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1617	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1618	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1619
1620	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1621	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1622	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1623	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1624
1625	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1626	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1627	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1628	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1629	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1630	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1631
1632	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1633	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1634	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1635	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1636	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1637	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1638	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1639	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1640
1641	/* GC only: */
1642	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1643	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1644	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1645	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1646
1647	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1648	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1649	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1650	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1651	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1652	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1653	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1654	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1655
1656	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1657	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1658	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1659	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1660	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1661	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1662	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1663	# endif
1664
1665	# undef PGM_REG_COUNTER
1666	# undef PGM_REG_PROFILE
1667	#endif
1668
1669	/*
1670	* Note! The layout below matches the member layout exactly!
1671	*/
1672
1673	/*
1674	* Common - stats
1675	*/
1676	for (unsigned i=0;i<pVM->cCPUs;i++)
1677	{
1678	PVMCPU pVCpu = &pVM->aCpus[i];
1679	PPGMCPU pPGM = &pVCpu->pgm.s;
1680
1681	#define PGM_REG_COUNTER(a, b, c) \
1682	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
1683	AssertRC(rc);
1684	#define PGM_REG_PROFILE(a, b, c) \
1685	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
1686	AssertRC(rc);
1687
1688	PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
1689
1690	#ifdef VBOX_WITH_STATISTICS
1691
1692	# if 0 /* rarely useful; leave for debugging. */
1693	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPtPD); j++)
1694	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1695	"The number of SyncPT per PD n.", "/PGM/CPU%d/PDSyncPT/%04X", i, j);
1696	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPagePD); j++)
1697	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1698	"The number of SyncPage per PD n.", "/PGM/CPU%d/PDSyncPage/%04X", i, j);
1699	# endif
1700	/* R0 only: */
1701	PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1702	PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1703	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1704	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1705	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1706	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1707	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1708	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1709	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1710	PGM_REG_COUNTER(&pPGM->StatR0DynMapPage, "/PGM/CPU%d/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1711	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1712	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1713	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
1714	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1715	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1716	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits0, "/PGM/CPU%d/R0/DynMapPage/Hits0", "Hits at iPage+0");
1717	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits1, "/PGM/CPU%d/R0/DynMapPage/Hits1", "Hits at iPage+1");
1718	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits2, "/PGM/CPU%d/R0/DynMapPage/Hits2", "Hits at iPage+2");
1719	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1720	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1721	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1722	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1723	//PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
1724	PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1725	PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1726	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[0], "/PGM/CPU%d/R0/SetSize000..09", "00-09% filled");
1727	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[1], "/PGM/CPU%d/R0/SetSize010..19", "10-19% filled");
1728	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[2], "/PGM/CPU%d/R0/SetSize020..29", "20-29% filled");
1729	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[3], "/PGM/CPU%d/R0/SetSize030..39", "30-39% filled");
1730	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[4], "/PGM/CPU%d/R0/SetSize040..49", "40-49% filled");
1731	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[5], "/PGM/CPU%d/R0/SetSize050..59", "50-59% filled");
1732	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[6], "/PGM/CPU%d/R0/SetSize060..69", "60-69% filled");
1733	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[7], "/PGM/CPU%d/R0/SetSize070..79", "70-79% filled");
1734	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[8], "/PGM/CPU%d/R0/SetSize080..89", "80-89% filled");
1735	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[9], "/PGM/CPU%d/R0/SetSize090..99", "90-99% filled");
1736	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[10], "/PGM/CPU%d/R0/SetSize100", "100% filled");
1737
1738	/* RZ only: */
1739	PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1740	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1741	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1742	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1743	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1744	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1745	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1746	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1747	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1748	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1749	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1750	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1751	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1752	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1753	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1754	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1755	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1756	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1757	PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1758	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1759	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1760	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1761	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1762	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1763	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1764	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1765	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1766	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1767	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1768	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1769	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1770	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1771	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1772	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1773	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1774	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1775	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1776	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1777	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1778	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1779	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1780	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1781	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1782	#if 0 /* rarely useful; leave for debugging. */
1783	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatRZTrap0ePD); j++)
1784	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1785	"The number of traps in page directory n.", "/PGM/CPU%d/RZ/Trap0e/PD/%04X", i, j);
1786	#endif
1787	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1788	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1789	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1790	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1791	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1792
1793	/* HC only: */
1794
1795	/* RZ & R3: */
1796	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1797	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1798	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1799	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1800	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1801	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1802	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1803	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1804	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1805	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1806	PGM_REG_PROFILE(&pPGM->StatRZSyncPT, "/PGM/CPU%d/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1807	PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1808	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4K, "/PGM/CPU%d/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1809	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4M, "/PGM/CPU%d/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1810	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1811	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1812	PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1813	PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1814	PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1815	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1816	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1817	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1818	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageStale, "/PGM/CPU%d/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1819	PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1820	PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1821	PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1822	PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1823	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1824	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1825	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1826	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1827	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1828	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1829	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1830	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1831	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1832	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1833	PGM_REG_PROFILE(&pPGM->StatRZPrefetch, "/PGM/CPU%d/RZ/Prefetch", "PGMPrefetchPage profiling.");
1834	PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1835	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1836	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1837	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1838	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1839	PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1840
1841	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1842	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1843	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1844	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1845	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1846	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1847	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1848	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1849	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1850	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1851	PGM_REG_PROFILE(&pPGM->StatR3SyncPT, "/PGM/CPU%d/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1852	PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1853	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4K, "/PGM/CPU%d/R3/SyncPT/4K", "Nr of 4K PT syncs");
1854	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4M, "/PGM/CPU%d/R3/SyncPT/4M", "Nr of 4M PT syncs");
1855	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1856	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1857	PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1858	PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1859	PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1860	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1861	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1862	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1863	PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1864	PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1865	PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1866	PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1867	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1868	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1869	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1870	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1871	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1872	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1873	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1874	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1875	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1876	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1877	PGM_REG_PROFILE(&pPGM->StatR3Prefetch, "/PGM/CPU%d/R3/Prefetch", "PGMPrefetchPage profiling.");
1878	PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1879	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1880	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1881	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1882	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1883	PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1884	#endif /* VBOX_WITH_STATISTICS */
1885
1886	#undef PGM_REG_PROFILE
1887	#undef PGM_REG_COUNTER
1888
1889	}
1890	}
1891
1892
1893	/**
1894	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1895	*
1896	* The dynamic mapping area will also be allocated and initialized at this
1897	* time. We could allocate it during PGMR3Init of course, but the mapping
1898	* wouldn't be allocated at that time preventing us from setting up the
1899	* page table entries with the dummy page.
1900	*
1901	* @returns VBox status code.
1902	* @param pVM VM handle.
1903	*/
1904	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1905	{
1906	RTGCPTR GCPtr;
1907	int rc;
1908
1909	/*
1910	* Reserve space for the dynamic mappings.
1911	*/
1912	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1913	if (RT_SUCCESS(rc))
1914	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1915
1916	if ( RT_SUCCESS(rc)
1917	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1918	{
1919	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1920	if (RT_SUCCESS(rc))
1921	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1922	}
1923	if (RT_SUCCESS(rc))
1924	{
1925	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1926	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1927	}
1928	return rc;
1929	}
1930
1931
1932	/**
1933	* Ring-3 init finalizing.
1934	*
1935	* @returns VBox status code.
1936	* @param pVM The VM handle.
1937	*/
1938	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1939	{
1940	int rc;
1941
1942	/*
1943	* Reserve space for the dynamic mappings.
1944	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1945	*/
1946	/* get the pointer to the page table entries. */
1947	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1948	AssertRelease(pMapping);
1949	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1950	const unsigned iPT = off >> X86_PD_SHIFT;
1951	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1952	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1953	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1954
1955	/* init cache */
1956	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1957	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1958	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1959
1960	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1961	{
1962	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1963	AssertRCReturn(rc, rc);
1964	}
1965
1966	/*
1967	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1968	* Intel only goes up to 36 bits, so we stick to 36 as well.
1969	*/
1970	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1971	uint32_t u32Dummy, u32Features;
1972	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1973
1974	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1975	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1976	else
1977	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1978
1979	/*
1980	* Allocate memory if we're supposed to do that.
1981	*/
1982	if (pVM->pgm.s.fRamPreAlloc)
1983	rc = pgmR3PhysRamPreAllocate(pVM);
1984
1985	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1986	return rc;
1987	}
1988
1989
1990	/**
1991	* Applies relocations to data and code managed by this component.
1992	*
1993	* This function will be called at init and whenever the VMM need to relocate it
1994	* self inside the GC.
1995	*
1996	* @param pVM The VM.
1997	* @param offDelta Relocation delta relative to old location.
1998	*/
1999	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2000	{
2001	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2002
2003	/*
2004	* Paging stuff.
2005	*/
2006	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2007
2008	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2009
2010	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2011	for (unsigned i=0;i<pVM->cCPUs;i++)
2012	{
2013	PVMCPU pVCpu = &pVM->aCpus[i];
2014
2015	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2016
2017	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2018	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2019	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2020	}
2021
2022	/*
2023	* Trees.
2024	*/
2025	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2026
2027	/*
2028	* Ram ranges.
2029	*/
2030	if (pVM->pgm.s.pRamRangesR3)
2031	{
2032	/* Update the pSelfRC pointers and relink them. */
2033	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2034	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2035	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2036	pgmR3PhysRelinkRamRanges(pVM);
2037	}
2038
2039	/*
2040	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2041	* be mapped and thus not included in the above exercise.
2042	*/
2043	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2044	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2045	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2046
2047	/*
2048	* Update the two page directories with all page table mappings.
2049	* (One or more of them have changed, that's why we're here.)
2050	*/
2051	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2052	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2053	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2054
2055	/* Relocate GC addresses of Page Tables. */
2056	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2057	{
2058	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2059	{
2060	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2061	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2062	}
2063	}
2064
2065	/*
2066	* Dynamic page mapping area.
2067	*/
2068	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2069	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2070	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2071
2072	/*
2073	* The Zero page.
2074	*/
2075	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2076	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2077	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2078	#else
2079	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2080	#endif
2081
2082	/*
2083	* Physical and virtual handlers.
2084	*/
2085	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2086	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2087	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2088
2089	/*
2090	* The page pool.
2091	*/
2092	pgmR3PoolRelocate(pVM);
2093	}
2094
2095
2096	/**
2097	* Callback function for relocating a physical access handler.
2098	*
2099	* @returns 0 (continue enum)
2100	* @param pNode Pointer to a PGMPHYSHANDLER node.
2101	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2102	* not certain the delta will fit in a void pointer for all possible configs.
2103	*/
2104	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2105	{
2106	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2107	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2108	if (pHandler->pfnHandlerRC)
2109	pHandler->pfnHandlerRC += offDelta;
2110	if (pHandler->pvUserRC >= 0x10000)
2111	pHandler->pvUserRC += offDelta;
2112	return 0;
2113	}
2114
2115
2116	/**
2117	* Callback function for relocating a virtual access handler.
2118	*
2119	* @returns 0 (continue enum)
2120	* @param pNode Pointer to a PGMVIRTHANDLER node.
2121	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2122	* not certain the delta will fit in a void pointer for all possible configs.
2123	*/
2124	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2125	{
2126	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2127	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2128	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2129	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2130	Assert(pHandler->pfnHandlerRC);
2131	pHandler->pfnHandlerRC += offDelta;
2132	return 0;
2133	}
2134
2135
2136	/**
2137	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2138	*
2139	* @returns 0 (continue enum)
2140	* @param pNode Pointer to a PGMVIRTHANDLER node.
2141	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2142	* not certain the delta will fit in a void pointer for all possible configs.
2143	*/
2144	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2145	{
2146	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2147	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2148	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2149	Assert(pHandler->pfnHandlerRC);
2150	pHandler->pfnHandlerRC += offDelta;
2151	return 0;
2152	}
2153
2154
2155	/**
2156	* The VM is being reset.
2157	*
2158	* For the PGM component this means that any PD write monitors
2159	* needs to be removed.
2160	*
2161	* @param pVM VM handle.
2162	*/
2163	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2164	{
2165	int rc;
2166
2167	LogFlow(("PGMR3Reset:\n"));
2168	VM_ASSERT_EMT(pVM);
2169
2170	pgmLock(pVM);
2171
2172	/*
2173	* Unfix any fixed mappings and disable CR3 monitoring.
2174	*/
2175	pVM->pgm.s.fMappingsFixed = false;
2176	pVM->pgm.s.GCPtrMappingFixed = 0;
2177	pVM->pgm.s.cbMappingFixed = 0;
2178
2179	/* Exit the guest paging mode before the pgm pool gets reset.
2180	* Important to clean up the amd64 case.
2181	*/
2182	for (unsigned i=0;i<pVM->cCPUs;i++)
2183	{
2184	PVMCPU pVCpu = &pVM->aCpus[i];
2185
2186	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2187	AssertRC(rc);
2188	}
2189
2190	#ifdef DEBUG
2191	DBGFR3InfoLog(pVM, "mappings", NULL);
2192	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2193	#endif
2194
2195	/*
2196	* Switch mode back to real mode. (before resetting the pgm pool!)
2197	*/
2198	for (unsigned i=0;i<pVM->cCPUs;i++)
2199	{
2200	PVMCPU pVCpu = &pVM->aCpus[i];
2201
2202	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2203	AssertRC(rc);
2204
2205	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2206	}
2207
2208	/*
2209	* Reset the shadow page pool.
2210	*/
2211	pgmR3PoolReset(pVM);
2212
2213	for (unsigned i=0;i<pVM->cCPUs;i++)
2214	{
2215	PVMCPU pVCpu = &pVM->aCpus[i];
2216
2217	/*
2218	* Re-init other members.
2219	*/
2220	pVCpu->pgm.s.fA20Enabled = true;
2221
2222	/*
2223	* Clear the FFs PGM owns.
2224	*/
2225	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2226	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2227	}
2228
2229	/*
2230	* Reset (zero) RAM pages.
2231	*/
2232	rc = pgmR3PhysRamReset(pVM);
2233	if (RT_SUCCESS(rc))
2234	{
2235	/*
2236	* Reset (zero) shadow ROM pages.
2237	*/
2238	rc = pgmR3PhysRomReset(pVM);
2239	}
2240
2241	pgmUnlock(pVM);
2242	//return rc;
2243	AssertReleaseRC(rc);
2244	}
2245
2246
2247	#ifdef VBOX_STRICT
2248	/**
2249	* VM state change callback for clearing fNoMorePhysWrites after
2250	* a snapshot has been created.
2251	*/
2252	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2253	{
2254	if (enmState == VMSTATE_RUNNING)
2255	pVM->pgm.s.fNoMorePhysWrites = false;
2256	}
2257	#endif
2258
2259
2260	/**
2261	* Terminates the PGM.
2262	*
2263	* @returns VBox status code.
2264	* @param pVM Pointer to VM structure.
2265	*/
2266	VMMR3DECL(int) PGMR3Term(PVM pVM)
2267	{
2268	PGMDeregisterStringFormatTypes();
2269	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2270	}
2271
2272
2273	/**
2274	* Terminates the per-VCPU PGM.
2275	*
2276	* Termination means cleaning up and freeing all resources,
2277	* the VM it self is at this point powered off or suspended.
2278	*
2279	* @returns VBox status code.
2280	* @param pVM The VM to operate on.
2281	*/
2282	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2283	{
2284	return 0;
2285	}
2286
2287
2288	/**
2289	* Find the ROM tracking structure for the given page.
2290	*
2291	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
2292	* that it's a ROM page.
2293	* @param pVM The VM handle.
2294	* @param GCPhys The address of the ROM page.
2295	*/
2296	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys)
2297	{
2298	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
2299	pRomRange;
2300	pRomRange = pRomRange->CTX_SUFF(pNext))
2301	{
2302	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
2303	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
2304	return &pRomRange->aPages[off >> PAGE_SHIFT];
2305	}
2306	return NULL;
2307	}
2308
2309
2310	/**
2311	* Save zero indicator + bits for the specified page.
2312	*
2313	* @returns VBox status code, errors are logged/asserted before returning.
2314	* @param pVM The VM handle.
2315	* @param pSSH The saved state handle.
2316	* @param pPage The page to save.
2317	* @param GCPhys The address of the page.
2318	* @param pRam The ram range (for error logging).
2319	*/
2320	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2321	{
2322	int rc;
2323	if (PGM_PAGE_IS_ZERO(pPage))
2324	rc = SSMR3PutU8(pSSM, 0);
2325	else
2326	{
2327	void const *pvPage;
2328	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
2329	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2330
2331	SSMR3PutU8(pSSM, 1);
2332	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
2333	}
2334	return rc;
2335	}
2336
2337
2338	/**
2339	* Save a shadowed ROM page.
2340	*
2341	* Format: Type, protection, and two pages with zero indicators.
2342	*
2343	* @returns VBox status code, errors are logged/asserted before returning.
2344	* @param pVM The VM handle.
2345	* @param pSSH The saved state handle.
2346	* @param pPage The page to save.
2347	* @param GCPhys The address of the page.
2348	* @param pRam The ram range (for error logging).
2349	*/
2350	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2351	{
2352	/* Need to save both pages and the current state. */
2353	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2354	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2355
2356	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
2357	SSMR3PutU8(pSSM, pRomPage->enmProt);
2358
2359	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
2360	if (RT_SUCCESS(rc))
2361	{
2362	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2363	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
2364	}
2365	return rc;
2366	}
2367
2368	/** PGM fields to save/load. */
2369	static const SSMFIELD s_aPGMFields[] =
2370	{
2371	SSMFIELD_ENTRY( PGM, fMappingsFixed),
2372	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
2373	SSMFIELD_ENTRY( PGM, cbMappingFixed),
2374	SSMFIELD_ENTRY_TERM()
2375	};
2376
2377	static const SSMFIELD s_aPGMCpuFields[] =
2378	{
2379	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
2380	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
2381	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
2382	SSMFIELD_ENTRY_TERM()
2383	};
2384
2385	/* For loading old saved states. (pre-smp) */
2386	typedef struct
2387	{
2388	/** If set no conflict checks are required. (boolean) */
2389	bool fMappingsFixed;
2390	/** Size of fixed mapping */
2391	uint32_t cbMappingFixed;
2392	/** Base address (GC) of fixed mapping */
2393	RTGCPTR GCPtrMappingFixed;
2394	/** A20 gate mask.
2395	* Our current approach to A20 emulation is to let REM do it and don't bother
2396	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2397	* But whould need arrise, we'll subject physical addresses to this mask. */
2398	RTGCPHYS GCPhysA20Mask;
2399	/** A20 gate state - boolean! */
2400	bool fA20Enabled;
2401	/** The guest paging mode. */
2402	PGMMODE enmGuestMode;
2403	} PGMOLD;
2404
2405	static const SSMFIELD s_aPGMFields_Old[] =
2406	{
2407	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
2408	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
2409	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
2410	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
2411	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
2412	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
2413	SSMFIELD_ENTRY_TERM()
2414	};
2415
2416
2417	/**
2418	* Execute state save operation.
2419	*
2420	* @returns VBox status code.
2421	* @param pVM VM Handle.
2422	* @param pSSM SSM operation handle.
2423	*/
2424	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2425	{
2426	int rc;
2427	unsigned i;
2428	PPGM pPGM = &pVM->pgm.s;
2429
2430	/*
2431	* Lock PGM and set the no-more-writes indicator.
2432	*/
2433	pgmLock(pVM);
2434	pVM->pgm.s.fNoMorePhysWrites = true;
2435
2436	/*
2437	* Save basic data (required / unaffected by relocation).
2438	*/
2439	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2440
2441	for (i=0;i<pVM->cCPUs;i++)
2442	{
2443	PVMCPU pVCpu = &pVM->aCpus[i];
2444
2445	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
2446	}
2447
2448	/*
2449	* The guest mappings.
2450	*/
2451	i = 0;
2452	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2453	{
2454	SSMR3PutU32( pSSM, i);
2455	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2456	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2457	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2458	}
2459	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2460
2461	/*
2462	* Ram ranges and the memory they describe.
2463	*/
2464	i = 0;
2465	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2466	{
2467	/*
2468	* Save the ram range details.
2469	*/
2470	SSMR3PutU32(pSSM, i);
2471	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2472	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2473	SSMR3PutGCPhys(pSSM, pRam->cb);
2474	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
2475	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
2476
2477	/*
2478	* Iterate the pages, only two special case.
2479	*/
2480	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
2481	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2482	{
2483	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2484	PPGMPAGE pPage = &pRam->aPages[iPage];
2485	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
2486
2487	if (uType == PGMPAGETYPE_ROM_SHADOW)
2488	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2489	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
2490	{
2491	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
2492	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
2493	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
2494	}
2495	else
2496	{
2497	SSMR3PutU8(pSSM, uType);
2498	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
2499	}
2500	if (RT_FAILURE(rc))
2501	break;
2502	}
2503	if (RT_FAILURE(rc))
2504	break;
2505	}
2506
2507	pgmUnlock(pVM);
2508	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2509	}
2510
2511
2512	/**
2513	* Load an ignored page.
2514	*
2515	* @returns VBox status code.
2516	* @param pSSM The saved state handle.
2517	*/
2518	static int pgmR3LoadPageToDevNull(PSSMHANDLE pSSM)
2519	{
2520	uint8_t abPage[PAGE_SIZE];
2521	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2522	}
2523
2524
2525	/**
2526	* Loads a page without any bits in the saved state, i.e. making sure it's
2527	* really zero.
2528	*
2529	* @returns VBox status code.
2530	* @param pVM The VM handle.
2531	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2532	* state).
2533	* @param pPage The guest page tracking structure.
2534	* @param GCPhys The page address.
2535	* @param pRam The ram range (logging).
2536	*/
2537	static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2538	{
2539	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2540	&& uType != PGMPAGETYPE_INVALID)
2541	return VERR_SSM_UNEXPECTED_DATA;
2542
2543	/* I think this should be sufficient. */
2544	if (!PGM_PAGE_IS_ZERO(pPage))
2545	return VERR_SSM_UNEXPECTED_DATA;
2546
2547	NOREF(pVM);
2548	NOREF(GCPhys);
2549	NOREF(pRam);
2550	return VINF_SUCCESS;
2551	}
2552
2553
2554	/**
2555	* Loads a page from the saved state.
2556	*
2557	* @returns VBox status code.
2558	* @param pVM The VM handle.
2559	* @param pSSM The SSM handle.
2560	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2561	* state).
2562	* @param pPage The guest page tracking structure.
2563	* @param GCPhys The page address.
2564	* @param pRam The ram range (logging).
2565	*/
2566	static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2567	{
2568	int rc;
2569
2570	/*
2571	* Match up the type, dealing with MMIO2 aliases (dropped).
2572	*/
2573	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2574	\|\| uType == PGMPAGETYPE_INVALID,
2575	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2576	VERR_SSM_UNEXPECTED_DATA);
2577
2578	/*
2579	* Load the page.
2580	*/
2581	void *pvPage;
2582	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2583	if (RT_SUCCESS(rc))
2584	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2585
2586	return rc;
2587	}
2588
2589
2590	/**
2591	* Loads a page (counter part to pgmR3SavePage).
2592	*
2593	* @returns VBox status code, fully bitched errors.
2594	* @param pVM The VM handle.
2595	* @param pSSM The SSM handle.
2596	* @param uType The page type.
2597	* @param pPage The page.
2598	* @param GCPhys The page address.
2599	* @param pRam The RAM range (for error messages).
2600	*/
2601	static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2602	{
2603	uint8_t uState;
2604	int rc = SSMR3GetU8(pSSM, &uState);
2605	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2606	if (uState == 0 /* zero */)
2607	rc = pgmR3LoadPageZero(pVM, uType, pPage, GCPhys, pRam);
2608	else if (uState == 1)
2609	rc = pgmR3LoadPageBits(pVM, pSSM, uType, pPage, GCPhys, pRam);
2610	else
2611	rc = VERR_INTERNAL_ERROR;
2612	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2613	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2614	rc);
2615	return VINF_SUCCESS;
2616	}
2617
2618
2619	/**
2620	* Loads a shadowed ROM page.
2621	*
2622	* @returns VBox status code, errors are fully bitched.
2623	* @param pVM The VM handle.
2624	* @param pSSM The saved state handle.
2625	* @param pPage The page.
2626	* @param GCPhys The page address.
2627	* @param pRam The RAM range (for error messages).
2628	*/
2629	static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2630	{
2631	/*
2632	* Load and set the protection first, then load the two pages, the first
2633	* one is the active the other is the passive.
2634	*/
2635	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2636	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2637
2638	uint8_t uProt;
2639	int rc = SSMR3GetU8(pSSM, &uProt);
2640	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2641	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2642	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2643	&& enmProt < PGMROMPROT_END,
2644	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2645	VERR_SSM_UNEXPECTED_DATA);
2646
2647	if (pRomPage->enmProt != enmProt)
2648	{
2649	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2650	AssertLogRelRCReturn(rc, rc);
2651	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2652	}
2653
2654	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2655	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2656	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2657	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2658
2659	rc = pgmR3LoadPage(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2660	if (RT_SUCCESS(rc))
2661	{
2662	pPageActive = pPage;
2663	rc = pgmR3LoadPage(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2664	}
2665	return rc;
2666	}
2667
2668
2669	/**
2670	* Worker for pgmR3Load.
2671	*
2672	* @returns VBox status code.
2673	*
2674	* @param pVM The VM handle.
2675	* @param pSSM The SSM handle.
2676	* @param uVersion The saved state version.
2677	*/
2678	static int pgmR3LoadLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2679	{
2680	PPGM pPGM = &pVM->pgm.s;
2681	int rc;
2682	uint32_t u32Sep;
2683
2684	/*
2685	* Load basic data (required / unaffected by relocation).
2686	*/
2687	if (uVersion >= PGM_SAVED_STATE_VERSION)
2688	{
2689	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2690	AssertLogRelRCReturn(rc, rc);
2691
2692	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
2693	{
2694	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2695	AssertLogRelRCReturn(rc, rc);
2696	}
2697	}
2698	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2699	{
2700	AssertRelease(pVM->cCPUs == 1);
2701
2702	PGMOLD pgmOld;
2703	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2704	AssertLogRelRCReturn(rc, rc);
2705
2706	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2707	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2708	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2709
2710	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2711	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2712	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2713	}
2714	else
2715	{
2716	AssertRelease(pVM->cCPUs == 1);
2717
2718	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2719	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2720	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2721
2722	uint32_t cbRamSizeIgnored;
2723	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2724	if (RT_FAILURE(rc))
2725	return rc;
2726	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2727
2728	uint32_t u32 = 0;
2729	SSMR3GetUInt(pSSM, &u32);
2730	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2731	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2732	RTUINT uGuestMode;
2733	SSMR3GetUInt(pSSM, &uGuestMode);
2734	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2735
2736	/* check separator. */
2737	SSMR3GetU32(pSSM, &u32Sep);
2738	if (RT_FAILURE(rc))
2739	return rc;
2740	if (u32Sep != (uint32_t)~0)
2741	{
2742	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2743	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2744	}
2745	}
2746
2747	/*
2748	* The guest mappings.
2749	*/
2750	uint32_t i = 0;
2751	for (;; i++)
2752	{
2753	/* Check the seqence number / separator. */
2754	rc = SSMR3GetU32(pSSM, &u32Sep);
2755	if (RT_FAILURE(rc))
2756	return rc;
2757	if (u32Sep == ~0U)
2758	break;
2759	if (u32Sep != i)
2760	{
2761	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2762	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2763	}
2764
2765	/* get the mapping details. */
2766	char szDesc[256];
2767	szDesc[0] = '\0';
2768	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2769	if (RT_FAILURE(rc))
2770	return rc;
2771	RTGCPTR GCPtr;
2772	SSMR3GetGCPtr(pSSM, &GCPtr);
2773	RTGCPTR cPTs;
2774	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2775	if (RT_FAILURE(rc))
2776	return rc;
2777
2778	/* find matching range. */
2779	PPGMMAPPING pMapping;
2780	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2781	if ( pMapping->cPTs == cPTs
2782	&& !strcmp(pMapping->pszDesc, szDesc))
2783	break;
2784	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2785	cPTs, szDesc, GCPtr),
2786	VERR_SSM_LOAD_CONFIG_MISMATCH);
2787
2788	/* relocate it. */
2789	if (pMapping->GCPtr != GCPtr)
2790	{
2791	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2792	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2793	}
2794	else
2795	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2796	}
2797
2798	/*
2799	* Ram range flags and bits.
2800	*/
2801	i = 0;
2802	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2803	{
2804	/* Check the seqence number / separator. */
2805	rc = SSMR3GetU32(pSSM, &u32Sep);
2806	if (RT_FAILURE(rc))
2807	return rc;
2808	if (u32Sep == ~0U)
2809	break;
2810	if (u32Sep != i)
2811	{
2812	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2813	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2814	}
2815	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2816
2817	/* Get the range details. */
2818	RTGCPHYS GCPhys;
2819	SSMR3GetGCPhys(pSSM, &GCPhys);
2820	RTGCPHYS GCPhysLast;
2821	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2822	RTGCPHYS cb;
2823	SSMR3GetGCPhys(pSSM, &cb);
2824	uint8_t fHaveBits;
2825	rc = SSMR3GetU8(pSSM, &fHaveBits);
2826	if (RT_FAILURE(rc))
2827	return rc;
2828	if (fHaveBits & ~1)
2829	{
2830	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2831	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2832	}
2833	size_t cchDesc = 0;
2834	char szDesc[256];
2835	szDesc[0] = '\0';
2836	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2837	{
2838	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2839	if (RT_FAILURE(rc))
2840	return rc;
2841	/* Since we've modified the description strings in r45878, only compare
2842	them if the saved state is more recent. */
2843	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2844	cchDesc = strlen(szDesc);
2845	}
2846
2847	/*
2848	* Match it up with the current range.
2849	*
2850	* Note there is a hack for dealing with the high BIOS mapping
2851	* in the old saved state format, this means we might not have
2852	* a 1:1 match on success.
2853	*/
2854	if ( ( GCPhys != pRam->GCPhys
2855	\|\| GCPhysLast != pRam->GCPhysLast
2856	\|\| cb != pRam->cb
2857	\|\| ( cchDesc
2858	&& strcmp(szDesc, pRam->pszDesc)) )
2859	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2860	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2861	\|\| GCPhys != UINT32_C(0xfff80000)
2862	\|\| GCPhysLast != UINT32_C(0xffffffff)
2863	\|\| pRam->GCPhysLast != GCPhysLast
2864	\|\| pRam->GCPhys < GCPhys
2865	\|\| !fHaveBits)
2866	)
2867	{
2868	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2869	"State : %RGp-%RGp %RGp bytes %s %s\n",
2870	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2871	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2872	/*
2873	* If we're loading a state for debugging purpose, don't make a fuss if
2874	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2875	*/
2876	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2877	\|\| GCPhys < 8 * _1M)
2878	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2879
2880	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2881	continue;
2882	}
2883
2884	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2885	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2886	{
2887	/*
2888	* Load the pages one by one.
2889	*/
2890	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2891	{
2892	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2893	PPGMPAGE pPage = &pRam->aPages[iPage];
2894	uint8_t uType;
2895	rc = SSMR3GetU8(pSSM, &uType);
2896	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2897	if (uType == PGMPAGETYPE_ROM_SHADOW)
2898	rc = pgmR3LoadShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2899	else
2900	rc = pgmR3LoadPage(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2901	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2902	}
2903	}
2904	else
2905	{
2906	/*
2907	* Old format.
2908	*/
2909	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2910
2911	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2912	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2913	uint32_t fFlags = 0;
2914	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2915	{
2916	uint16_t u16Flags;
2917	rc = SSMR3GetU16(pSSM, &u16Flags);
2918	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2919	fFlags \|= u16Flags;
2920	}
2921
2922	/* Load the bits */
2923	if ( !fHaveBits
2924	&& GCPhysLast < UINT32_C(0xe0000000))
2925	{
2926	/*
2927	* Dynamic chunks.
2928	*/
2929	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2930	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2931	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2932	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2933
2934	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2935	{
2936	uint8_t fPresent;
2937	rc = SSMR3GetU8(pSSM, &fPresent);
2938	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2939	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2940	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2941	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2942
2943	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2944	{
2945	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2946	PPGMPAGE pPage = &pRam->aPages[iPage];
2947	if (fPresent)
2948	{
2949	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2950	rc = pgmR3LoadPageToDevNull(pSSM);
2951	else
2952	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2953	}
2954	else
2955	rc = pgmR3LoadPageZero(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2956	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2957	}
2958	}
2959	}
2960	else if (pRam->pvR3)
2961	{
2962	/*
2963	* MMIO2.
2964	*/
2965	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2966	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2967	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2968	AssertLogRelMsgReturn(pRam->pvR3,
2969	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2970	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2971
2972	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2973	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2974	}
2975	else if (GCPhysLast < UINT32_C(0xfff80000))
2976	{
2977	/*
2978	* PCI MMIO, no pages saved.
2979	*/
2980	}
2981	else
2982	{
2983	/*
2984	* Load the 0xfff80000..0xffffffff BIOS range.
2985	* It starts with X reserved pages that we have to skip over since
2986	* the RAMRANGE create by the new code won't include those.
2987	*/
2988	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2989	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2990	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2991	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2992	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2993	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2994	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2995
2996	/* Skip wasted reserved pages before the ROM. */
2997	while (GCPhys < pRam->GCPhys)
2998	{
2999	rc = pgmR3LoadPageToDevNull(pSSM);
3000	GCPhys += PAGE_SIZE;
3001	}
3002
3003	/* Load the bios pages. */
3004	cPages = pRam->cb >> PAGE_SHIFT;
3005	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3006	{
3007	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
3008	PPGMPAGE pPage = &pRam->aPages[iPage];
3009
3010	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
3011	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
3012	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3013	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
3014	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
3015	}
3016	}
3017	}
3018	}
3019
3020	return rc;
3021	}
3022
3023
3024	/**
3025	* Execute state load operation.
3026	*
3027	* @returns VBox status code.
3028	* @param pVM VM Handle.
3029	* @param pSSM SSM operation handle.
3030	* @param uVersion Data layout version.
3031	* @param uPass The data pass.
3032	*/
3033	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3034	{
3035	int rc;
3036	PPGM pPGM = &pVM->pgm.s;
3037	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3038
3039	/*
3040	* Validate version.
3041	*/
3042	if ( uVersion != PGM_SAVED_STATE_VERSION
3043	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
3044	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
3045	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3046	{
3047	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
3048	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3049	}
3050
3051	/*
3052	* Call the reset function to make sure all the memory is cleared.
3053	*/
3054	PGMR3Reset(pVM);
3055
3056	/*
3057	* Do the loading while owning the lock because a bunch of the functions
3058	* we're using requires this.
3059	*/
3060	pgmLock(pVM);
3061	rc = pgmR3LoadLocked(pVM, pSSM, uVersion);
3062	pgmUnlock(pVM);
3063	if (RT_SUCCESS(rc))
3064	{
3065	/*
3066	* We require a full resync now.
3067	*/
3068	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
3069	{
3070	PVMCPU pVCpu = &pVM->aCpus[i];
3071	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3072	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3073
3074	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3075	}
3076
3077	pgmR3HandlerPhysicalUpdateAll(pVM);
3078
3079	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
3080	{
3081	PVMCPU pVCpu = &pVM->aCpus[i];
3082
3083	/*
3084	* Change the paging mode.
3085	*/
3086	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3087
3088	/* Restore pVM->pgm.s.GCPhysCR3. */
3089	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3090	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3091	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3092	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3093	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3094	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3095	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3096	else
3097	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3098	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3099	}
3100	}
3101
3102	return rc;
3103	}
3104
3105
3106	/**
3107	* Show paging mode.
3108	*
3109	* @param pVM VM Handle.
3110	* @param pHlp The info helpers.
3111	* @param pszArgs "all" (default), "guest", "shadow" or "host".
3112	*/
3113	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3114	{
3115	/* digest argument. */
3116	bool fGuest, fShadow, fHost;
3117	if (pszArgs)
3118	pszArgs = RTStrStripL(pszArgs);
3119	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
3120	fShadow = fHost = fGuest = true;
3121	else
3122	{
3123	fShadow = fHost = fGuest = false;
3124	if (strstr(pszArgs, "guest"))
3125	fGuest = true;
3126	if (strstr(pszArgs, "shadow"))
3127	fShadow = true;
3128	if (strstr(pszArgs, "host"))
3129	fHost = true;
3130	}
3131
3132	/** @todo SMP support! */
3133	/* print info. */
3134	if (fGuest)
3135	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
3136	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
3137	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
3138	if (fShadow)
3139	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
3140	if (fHost)
3141	{
3142	const char *psz;
3143	switch (pVM->pgm.s.enmHostMode)
3144	{
3145	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
3146	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
3147	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
3148	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
3149	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
3150	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
3151	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
3152	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
3153	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
3154	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
3155	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
3156	default: psz = "unknown"; break;
3157	}
3158	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
3159	}
3160	}
3161
3162
3163	/**
3164	* Dump registered MMIO ranges to the log.
3165	*
3166	* @param pVM VM Handle.
3167	* @param pHlp The info helpers.
3168	* @param pszArgs Arguments, ignored.
3169	*/
3170	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3171	{
3172	NOREF(pszArgs);
3173	pHlp->pfnPrintf(pHlp,
3174	"RAM ranges (pVM=%p)\n"
3175	"%.s %.s\n",
3176	pVM,
3177	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
3178	sizeof(RTHCPTR) * 2, "pvHC ");
3179
3180	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
3181	pHlp->pfnPrintf(pHlp,
3182	"%RGp-%RGp %RHv %s\n",
3183	pCur->GCPhys,
3184	pCur->GCPhysLast,
3185	pCur->pvR3,
3186	pCur->pszDesc);
3187	}
3188
3189	/**
3190	* Dump the page directory to the log.
3191	*
3192	* @param pVM VM Handle.
3193	* @param pHlp The info helpers.
3194	* @param pszArgs Arguments, ignored.
3195	*/
3196	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3197	{
3198	/** @todo SMP support!! */
3199	PVMCPU pVCpu = &pVM->aCpus[0];
3200
3201	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
3202	/* Big pages supported? */
3203	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3204
3205	/* Global pages supported? */
3206	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
3207
3208	NOREF(pszArgs);
3209
3210	/*
3211	* Get page directory addresses.
3212	*/
3213	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3214	Assert(pPDSrc);
3215	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3216
3217	/*
3218	* Iterate the page directory.
3219	*/
3220	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3221	{
3222	X86PDE PdeSrc = pPDSrc->a[iPD];
3223	if (PdeSrc.n.u1Present)
3224	{
3225	if (PdeSrc.b.u1Size && fPSE)
3226	pHlp->pfnPrintf(pHlp,
3227	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3228	iPD,
3229	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
3230	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3231	else
3232	pHlp->pfnPrintf(pHlp,
3233	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3234	iPD,
3235	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3236	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3237	}
3238	}
3239	}
3240
3241
3242	/**
3243	* Service a VMMCALLRING3_PGM_LOCK call.
3244	*
3245	* @returns VBox status code.
3246	* @param pVM The VM handle.
3247	*/
3248	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3249	{
3250	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
3251	AssertRC(rc);
3252	return rc;
3253	}
3254
3255
3256	/**
3257	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3258	*
3259	* @returns PGM_TYPE_*.
3260	* @param pgmMode The mode value to convert.
3261	*/
3262	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3263	{
3264	switch (pgmMode)
3265	{
3266	case PGMMODE_REAL: return PGM_TYPE_REAL;
3267	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3268	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3269	case PGMMODE_PAE:
3270	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3271	case PGMMODE_AMD64:
3272	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3273	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
3274	case PGMMODE_EPT: return PGM_TYPE_EPT;
3275	default:
3276	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3277	}
3278	}
3279
3280
3281	/**
3282	* Gets the index into the paging mode data array of a SHW+GST mode.
3283	*
3284	* @returns PGM::paPagingData index.
3285	* @param uShwType The shadow paging mode type.
3286	* @param uGstType The guest paging mode type.
3287	*/
3288	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3289	{
3290	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3291	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3292	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3293	+ (uGstType - PGM_TYPE_REAL);
3294	}
3295
3296
3297	/**
3298	* Gets the index into the paging mode data array of a SHW+GST mode.
3299	*
3300	* @returns PGM::paPagingData index.
3301	* @param enmShw The shadow paging mode.
3302	* @param enmGst The guest paging mode.
3303	*/
3304	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3305	{
3306	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3307	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3308	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3309	}
3310
3311
3312	/**
3313	* Calculates the max data index.
3314	* @returns The number of entries in the paging data array.
3315	*/
3316	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3317	{
3318	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3319	}
3320
3321
3322	/**
3323	* Initializes the paging mode data kept in PGM::paModeData.
3324	*
3325	* @param pVM The VM handle.
3326	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
3327	* This is used early in the init process to avoid trouble with PDM
3328	* not being initialized yet.
3329	*/
3330	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
3331	{
3332	PPGMMODEDATA pModeData;
3333	int rc;
3334
3335	/*
3336	* Allocate the array on the first call.
3337	*/
3338	if (!pVM->pgm.s.paModeData)
3339	{
3340	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
3341	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
3342	}
3343
3344	/*
3345	* Initialize the array entries.
3346	*/
3347	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
3348	pModeData->uShwType = PGM_TYPE_32BIT;
3349	pModeData->uGstType = PGM_TYPE_REAL;
3350	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3351	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3352	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3353
3354	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
3355	pModeData->uShwType = PGM_TYPE_32BIT;
3356	pModeData->uGstType = PGM_TYPE_PROT;
3357	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3358	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3359	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3360
3361	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
3362	pModeData->uShwType = PGM_TYPE_32BIT;
3363	pModeData->uGstType = PGM_TYPE_32BIT;
3364	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3365	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3366	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3367
3368	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
3369	pModeData->uShwType = PGM_TYPE_PAE;
3370	pModeData->uGstType = PGM_TYPE_REAL;
3371	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3372	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3373	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3374
3375	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
3376	pModeData->uShwType = PGM_TYPE_PAE;
3377	pModeData->uGstType = PGM_TYPE_PROT;
3378	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3379	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3380	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3381
3382	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
3383	pModeData->uShwType = PGM_TYPE_PAE;
3384	pModeData->uGstType = PGM_TYPE_32BIT;
3385	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3386	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3387	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3388
3389	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
3390	pModeData->uShwType = PGM_TYPE_PAE;
3391	pModeData->uGstType = PGM_TYPE_PAE;
3392	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3393	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3394	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3395
3396	#ifdef VBOX_WITH_64_BITS_GUESTS
3397	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
3398	pModeData->uShwType = PGM_TYPE_AMD64;
3399	pModeData->uGstType = PGM_TYPE_AMD64;
3400	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3401	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3402	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3403	#endif
3404
3405	/* The nested paging mode. */
3406	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3407	pModeData->uShwType = PGM_TYPE_NESTED;
3408	pModeData->uGstType = PGM_TYPE_REAL;
3409	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3410	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3411
3412	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3413	pModeData->uShwType = PGM_TYPE_NESTED;
3414	pModeData->uGstType = PGM_TYPE_PROT;
3415	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3416	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3417
3418	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3419	pModeData->uShwType = PGM_TYPE_NESTED;
3420	pModeData->uGstType = PGM_TYPE_32BIT;
3421	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3422	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3423
3424	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3425	pModeData->uShwType = PGM_TYPE_NESTED;
3426	pModeData->uGstType = PGM_TYPE_PAE;
3427	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3428	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3429
3430	#ifdef VBOX_WITH_64_BITS_GUESTS
3431	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3432	pModeData->uShwType = PGM_TYPE_NESTED;
3433	pModeData->uGstType = PGM_TYPE_AMD64;
3434	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3435	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3436	#endif
3437
3438	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3439	switch (pVM->pgm.s.enmHostMode)
3440	{
3441	#if HC_ARCH_BITS == 32
3442	case SUPPAGINGMODE_32_BIT:
3443	case SUPPAGINGMODE_32_BIT_GLOBAL:
3444	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3445	{
3446	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3447	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3448	}
3449	# ifdef VBOX_WITH_64_BITS_GUESTS
3450	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3451	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3452	# endif
3453	break;
3454
3455	case SUPPAGINGMODE_PAE:
3456	case SUPPAGINGMODE_PAE_NX:
3457	case SUPPAGINGMODE_PAE_GLOBAL:
3458	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3459	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3460	{
3461	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3462	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3463	}
3464	# ifdef VBOX_WITH_64_BITS_GUESTS
3465	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3466	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3467	# endif
3468	break;
3469	#endif /* HC_ARCH_BITS == 32 */
3470
3471	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3472	case SUPPAGINGMODE_AMD64:
3473	case SUPPAGINGMODE_AMD64_GLOBAL:
3474	case SUPPAGINGMODE_AMD64_NX:
3475	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3476	# ifdef VBOX_WITH_64_BITS_GUESTS
3477	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3478	# else
3479	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3480	# endif
3481	{
3482	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3483	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3484	}
3485	break;
3486	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3487
3488	default:
3489	AssertFailed();
3490	break;
3491	}
3492
3493	/* Extended paging (EPT) / Intel VT-x */
3494	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3495	pModeData->uShwType = PGM_TYPE_EPT;
3496	pModeData->uGstType = PGM_TYPE_REAL;
3497	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3498	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3499	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3500
3501	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3502	pModeData->uShwType = PGM_TYPE_EPT;
3503	pModeData->uGstType = PGM_TYPE_PROT;
3504	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3505	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3506	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3507
3508	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3509	pModeData->uShwType = PGM_TYPE_EPT;
3510	pModeData->uGstType = PGM_TYPE_32BIT;
3511	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3512	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3513	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3514
3515	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3516	pModeData->uShwType = PGM_TYPE_EPT;
3517	pModeData->uGstType = PGM_TYPE_PAE;
3518	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3519	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3520	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3521
3522	#ifdef VBOX_WITH_64_BITS_GUESTS
3523	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3524	pModeData->uShwType = PGM_TYPE_EPT;
3525	pModeData->uGstType = PGM_TYPE_AMD64;
3526	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3527	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3528	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3529	#endif
3530	return VINF_SUCCESS;
3531	}
3532
3533
3534	/**
3535	* Switch to different (or relocated in the relocate case) mode data.
3536	*
3537	* @param pVM The VM handle.
3538	* @param pVCpu The VMCPU to operate on.
3539	* @param enmShw The the shadow paging mode.
3540	* @param enmGst The the guest paging mode.
3541	*/
3542	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3543	{
3544	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3545
3546	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3547	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3548
3549	/* shadow */
3550	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3551	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3552	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3553	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3554	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3555
3556	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3557	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3558
3559	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3560	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3561
3562
3563	/* guest */
3564	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3565	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3566	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3567	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3568	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3569	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3570	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3571	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3572	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3573	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3574	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3575	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3576
3577	/* both */
3578	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3579	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3580	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3581	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3582	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3583	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3584	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3585	#ifdef VBOX_STRICT
3586	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3587	#endif
3588	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3589	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3590
3591	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3592	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3593	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3594	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3595	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3596	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3597	#ifdef VBOX_STRICT
3598	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3599	#endif
3600	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3601	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3602
3603	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3604	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3605	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3606	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3607	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3608	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3609	#ifdef VBOX_STRICT
3610	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3611	#endif
3612	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3613	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3614	}
3615
3616
3617	/**
3618	* Calculates the shadow paging mode.
3619	*
3620	* @returns The shadow paging mode.
3621	* @param pVM VM handle.
3622	* @param enmGuestMode The guest mode.
3623	* @param enmHostMode The host mode.
3624	* @param enmShadowMode The current shadow mode.
3625	* @param penmSwitcher Where to store the switcher to use.
3626	* VMMSWITCHER_INVALID means no change.
3627	*/
3628	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3629	{
3630	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3631	switch (enmGuestMode)
3632	{
3633	/*
3634	* When switching to real or protected mode we don't change
3635	* anything since it's likely that we'll switch back pretty soon.
3636	*
3637	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3638	* and is supposed to determine which shadow paging and switcher to
3639	* use during init.
3640	*/
3641	case PGMMODE_REAL:
3642	case PGMMODE_PROTECTED:
3643	if ( enmShadowMode != PGMMODE_INVALID
3644	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3645	break; /* (no change) */
3646
3647	switch (enmHostMode)
3648	{
3649	case SUPPAGINGMODE_32_BIT:
3650	case SUPPAGINGMODE_32_BIT_GLOBAL:
3651	enmShadowMode = PGMMODE_32_BIT;
3652	enmSwitcher = VMMSWITCHER_32_TO_32;
3653	break;
3654
3655	case SUPPAGINGMODE_PAE:
3656	case SUPPAGINGMODE_PAE_NX:
3657	case SUPPAGINGMODE_PAE_GLOBAL:
3658	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3659	enmShadowMode = PGMMODE_PAE;
3660	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3661	#ifdef DEBUG_bird
3662	if (RTEnvExist("VBOX_32BIT"))
3663	{
3664	enmShadowMode = PGMMODE_32_BIT;
3665	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3666	}
3667	#endif
3668	break;
3669
3670	case SUPPAGINGMODE_AMD64:
3671	case SUPPAGINGMODE_AMD64_GLOBAL:
3672	case SUPPAGINGMODE_AMD64_NX:
3673	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3674	enmShadowMode = PGMMODE_PAE;
3675	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3676	#ifdef DEBUG_bird
3677	if (RTEnvExist("VBOX_32BIT"))
3678	{
3679	enmShadowMode = PGMMODE_32_BIT;
3680	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3681	}
3682	#endif
3683	break;
3684
3685	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3686	}
3687	break;
3688
3689	case PGMMODE_32_BIT:
3690	switch (enmHostMode)
3691	{
3692	case SUPPAGINGMODE_32_BIT:
3693	case SUPPAGINGMODE_32_BIT_GLOBAL:
3694	enmShadowMode = PGMMODE_32_BIT;
3695	enmSwitcher = VMMSWITCHER_32_TO_32;
3696	break;
3697
3698	case SUPPAGINGMODE_PAE:
3699	case SUPPAGINGMODE_PAE_NX:
3700	case SUPPAGINGMODE_PAE_GLOBAL:
3701	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3702	enmShadowMode = PGMMODE_PAE;
3703	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3704	#ifdef DEBUG_bird
3705	if (RTEnvExist("VBOX_32BIT"))
3706	{
3707	enmShadowMode = PGMMODE_32_BIT;
3708	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3709	}
3710	#endif
3711	break;
3712
3713	case SUPPAGINGMODE_AMD64:
3714	case SUPPAGINGMODE_AMD64_GLOBAL:
3715	case SUPPAGINGMODE_AMD64_NX:
3716	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3717	enmShadowMode = PGMMODE_PAE;
3718	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3719	#ifdef DEBUG_bird
3720	if (RTEnvExist("VBOX_32BIT"))
3721	{
3722	enmShadowMode = PGMMODE_32_BIT;
3723	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3724	}
3725	#endif
3726	break;
3727
3728	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3729	}
3730	break;
3731
3732	case PGMMODE_PAE:
3733	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3734	switch (enmHostMode)
3735	{
3736	case SUPPAGINGMODE_32_BIT:
3737	case SUPPAGINGMODE_32_BIT_GLOBAL:
3738	enmShadowMode = PGMMODE_PAE;
3739	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3740	break;
3741
3742	case SUPPAGINGMODE_PAE:
3743	case SUPPAGINGMODE_PAE_NX:
3744	case SUPPAGINGMODE_PAE_GLOBAL:
3745	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3746	enmShadowMode = PGMMODE_PAE;
3747	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3748	break;
3749
3750	case SUPPAGINGMODE_AMD64:
3751	case SUPPAGINGMODE_AMD64_GLOBAL:
3752	case SUPPAGINGMODE_AMD64_NX:
3753	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3754	enmShadowMode = PGMMODE_PAE;
3755	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3756	break;
3757
3758	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3759	}
3760	break;
3761
3762	case PGMMODE_AMD64:
3763	case PGMMODE_AMD64_NX:
3764	switch (enmHostMode)
3765	{
3766	case SUPPAGINGMODE_32_BIT:
3767	case SUPPAGINGMODE_32_BIT_GLOBAL:
3768	enmShadowMode = PGMMODE_AMD64;
3769	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3770	break;
3771
3772	case SUPPAGINGMODE_PAE:
3773	case SUPPAGINGMODE_PAE_NX:
3774	case SUPPAGINGMODE_PAE_GLOBAL:
3775	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3776	enmShadowMode = PGMMODE_AMD64;
3777	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3778	break;
3779
3780	case SUPPAGINGMODE_AMD64:
3781	case SUPPAGINGMODE_AMD64_GLOBAL:
3782	case SUPPAGINGMODE_AMD64_NX:
3783	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3784	enmShadowMode = PGMMODE_AMD64;
3785	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3786	break;
3787
3788	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3789	}
3790	break;
3791
3792
3793	default:
3794	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3795	return PGMMODE_INVALID;
3796	}
3797	/* Override the shadow mode is nested paging is active. */
3798	if (HWACCMIsNestedPagingActive(pVM))
3799	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3800
3801	*penmSwitcher = enmSwitcher;
3802	return enmShadowMode;
3803	}
3804
3805
3806	/**
3807	* Performs the actual mode change.
3808	* This is called by PGMChangeMode and pgmR3InitPaging().
3809	*
3810	* @returns VBox status code. May suspend or power off the VM on error, but this
3811	* will trigger using FFs and not status codes.
3812	*
3813	* @param pVM VM handle.
3814	* @param pVCpu The VMCPU to operate on.
3815	* @param enmGuestMode The new guest mode. This is assumed to be different from
3816	* the current mode.
3817	*/
3818	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3819	{
3820	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3821	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3822
3823	/*
3824	* Calc the shadow mode and switcher.
3825	*/
3826	VMMSWITCHER enmSwitcher;
3827	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3828	if (enmSwitcher != VMMSWITCHER_INVALID)
3829	{
3830	/*
3831	* Select new switcher.
3832	*/
3833	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3834	if (RT_FAILURE(rc))
3835	{
3836	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3837	return rc;
3838	}
3839	}
3840
3841	/*
3842	* Exit old mode(s).
3843	*/
3844	/* shadow */
3845	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3846	{
3847	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3848	if (PGM_SHW_PFN(Exit, pVCpu))
3849	{
3850	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3851	if (RT_FAILURE(rc))
3852	{
3853	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3854	return rc;
3855	}
3856	}
3857
3858	}
3859	else
3860	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3861
3862	/* guest */
3863	if (PGM_GST_PFN(Exit, pVCpu))
3864	{
3865	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3866	if (RT_FAILURE(rc))
3867	{
3868	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3869	return rc;
3870	}
3871	}
3872
3873	/*
3874	* Load new paging mode data.
3875	*/
3876	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3877
3878	/*
3879	* Enter new shadow mode (if changed).
3880	*/
3881	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3882	{
3883	int rc;
3884	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3885	switch (enmShadowMode)
3886	{
3887	case PGMMODE_32_BIT:
3888	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu);
3889	break;
3890	case PGMMODE_PAE:
3891	case PGMMODE_PAE_NX:
3892	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu);
3893	break;
3894	case PGMMODE_AMD64:
3895	case PGMMODE_AMD64_NX:
3896	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu);
3897	break;
3898	case PGMMODE_NESTED:
3899	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu);
3900	break;
3901	case PGMMODE_EPT:
3902	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu);
3903	break;
3904	case PGMMODE_REAL:
3905	case PGMMODE_PROTECTED:
3906	default:
3907	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3908	return VERR_INTERNAL_ERROR;
3909	}
3910	if (RT_FAILURE(rc))
3911	{
3912	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3913	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3914	return rc;
3915	}
3916	}
3917
3918	/*
3919	* Always flag the necessary updates
3920	*/
3921	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3922
3923	/*
3924	* Enter the new guest and shadow+guest modes.
3925	*/
3926	int rc = -1;
3927	int rc2 = -1;
3928	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3929	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3930	switch (enmGuestMode)
3931	{
3932	case PGMMODE_REAL:
3933	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3934	switch (pVCpu->pgm.s.enmShadowMode)
3935	{
3936	case PGMMODE_32_BIT:
3937	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3938	break;
3939	case PGMMODE_PAE:
3940	case PGMMODE_PAE_NX:
3941	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3942	break;
3943	case PGMMODE_NESTED:
3944	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3945	break;
3946	case PGMMODE_EPT:
3947	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3948	break;
3949	case PGMMODE_AMD64:
3950	case PGMMODE_AMD64_NX:
3951	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3952	default: AssertFailed(); break;
3953	}
3954	break;
3955
3956	case PGMMODE_PROTECTED:
3957	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3958	switch (pVCpu->pgm.s.enmShadowMode)
3959	{
3960	case PGMMODE_32_BIT:
3961	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3962	break;
3963	case PGMMODE_PAE:
3964	case PGMMODE_PAE_NX:
3965	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3966	break;
3967	case PGMMODE_NESTED:
3968	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3969	break;
3970	case PGMMODE_EPT:
3971	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3972	break;
3973	case PGMMODE_AMD64:
3974	case PGMMODE_AMD64_NX:
3975	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3976	default: AssertFailed(); break;
3977	}
3978	break;
3979
3980	case PGMMODE_32_BIT:
3981	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3982	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3983	switch (pVCpu->pgm.s.enmShadowMode)
3984	{
3985	case PGMMODE_32_BIT:
3986	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3987	break;
3988	case PGMMODE_PAE:
3989	case PGMMODE_PAE_NX:
3990	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3991	break;
3992	case PGMMODE_NESTED:
3993	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3994	break;
3995	case PGMMODE_EPT:
3996	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3997	break;
3998	case PGMMODE_AMD64:
3999	case PGMMODE_AMD64_NX:
4000	AssertMsgFailed(("Should use PAE shadow mode!\n"));
4001	default: AssertFailed(); break;
4002	}
4003	break;
4004
4005	case PGMMODE_PAE_NX:
4006	case PGMMODE_PAE:
4007	{
4008	uint32_t u32Dummy, u32Features;
4009
4010	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
4011	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
4012	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
4013	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
4014
4015	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
4016	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
4017	switch (pVCpu->pgm.s.enmShadowMode)
4018	{
4019	case PGMMODE_PAE:
4020	case PGMMODE_PAE_NX:
4021	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
4022	break;
4023	case PGMMODE_NESTED:
4024	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
4025	break;
4026	case PGMMODE_EPT:
4027	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
4028	break;
4029	case PGMMODE_32_BIT:
4030	case PGMMODE_AMD64:
4031	case PGMMODE_AMD64_NX:
4032	AssertMsgFailed(("Should use PAE shadow mode!\n"));
4033	default: AssertFailed(); break;
4034	}
4035	break;
4036	}
4037
4038	#ifdef VBOX_WITH_64_BITS_GUESTS
4039	case PGMMODE_AMD64_NX:
4040	case PGMMODE_AMD64:
4041	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
4042	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
4043	switch (pVCpu->pgm.s.enmShadowMode)
4044	{
4045	case PGMMODE_AMD64:
4046	case PGMMODE_AMD64_NX:
4047	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
4048	break;
4049	case PGMMODE_NESTED:
4050	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
4051	break;
4052	case PGMMODE_EPT:
4053	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
4054	break;
4055	case PGMMODE_32_BIT:
4056	case PGMMODE_PAE:
4057	case PGMMODE_PAE_NX:
4058	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
4059	default: AssertFailed(); break;
4060	}
4061	break;
4062	#endif
4063
4064	default:
4065	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
4066	rc = VERR_NOT_IMPLEMENTED;
4067	break;
4068	}
4069
4070	/* status codes. */
4071	AssertRC(rc);
4072	AssertRC(rc2);
4073	if (RT_SUCCESS(rc))
4074	{
4075	rc = rc2;
4076	if (RT_SUCCESS(rc)) /* no informational status codes. */
4077	rc = VINF_SUCCESS;
4078	}
4079
4080	/* Notify HWACCM as well. */
4081	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
4082	return rc;
4083	}
4084
4085	/**
4086	* Release the pgm lock if owned by the current VCPU
4087	*
4088	* @param pVM The VM to operate on.
4089	*/
4090	VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
4091	{
4092	while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
4093	PDMCritSectLeave(&pVM->pgm.s.CritSect);
4094	}
4095
4096	/**
4097	* Called by pgmPoolFlushAllInt prior to flushing the pool.
4098	*
4099	* @returns VBox status code, fully asserted.
4100	* @param pVM The VM handle.
4101	* @param pVCpu The VMCPU to operate on.
4102	*/
4103	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
4104	{
4105	/* Unmap the old CR3 value before flushing everything. */
4106	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
4107	AssertRC(rc);
4108
4109	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
4110	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
4111	AssertRC(rc);
4112	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
4113	return rc;
4114	}
4115
4116
4117	/**
4118	* Called by pgmPoolFlushAllInt after flushing the pool.
4119	*
4120	* @returns VBox status code, fully asserted.
4121	* @param pVM The VM handle.
4122	* @param pVCpu The VMCPU to operate on.
4123	*/
4124	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
4125	{
4126	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
4127	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
4128	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4129	AssertRCReturn(rc, rc);
4130	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
4131
4132	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
4133	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
4134	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
4135	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
4136	return rc;
4137	}
4138
4139
4140	/**
4141	* Dumps a PAE shadow page table.
4142	*
4143	* @returns VBox status code (VINF_SUCCESS).
4144	* @param pVM The VM handle.
4145	* @param pPT Pointer to the page table.
4146	* @param u64Address The virtual address of the page table starts.
4147	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4148	* @param cMaxDepth The maxium depth.
4149	* @param pHlp Pointer to the output functions.
4150	*/
4151	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4152	{
4153	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4154	{
4155	X86PTEPAE Pte = pPT->a[i];
4156	if (Pte.n.u1Present)
4157	{
4158	pHlp->pfnPrintf(pHlp,
4159	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4160	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
4161	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
4162	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
4163	Pte.n.u1Write ? 'W' : 'R',
4164	Pte.n.u1User ? 'U' : 'S',
4165	Pte.n.u1Accessed ? 'A' : '-',
4166	Pte.n.u1Dirty ? 'D' : '-',
4167	Pte.n.u1Global ? 'G' : '-',
4168	Pte.n.u1WriteThru ? "WT" : "--",
4169	Pte.n.u1CacheDisable? "CD" : "--",
4170	Pte.n.u1PAT ? "AT" : "--",
4171	Pte.n.u1NoExecute ? "NX" : "--",
4172	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4173	Pte.u & RT_BIT(10) ? '1' : '0',
4174	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
4175	Pte.u & X86_PTE_PAE_PG_MASK);
4176	}
4177	}
4178	return VINF_SUCCESS;
4179	}
4180
4181
4182	/**
4183	* Dumps a PAE shadow page directory table.
4184	*
4185	* @returns VBox status code (VINF_SUCCESS).
4186	* @param pVM The VM handle.
4187	* @param HCPhys The physical address of the page directory table.
4188	* @param u64Address The virtual address of the page table starts.
4189	* @param cr4 The CR4, PSE is currently used.
4190	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4191	* @param cMaxDepth The maxium depth.
4192	* @param pHlp Pointer to the output functions.
4193	*/
4194	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4195	{
4196	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
4197	if (!pPD)
4198	{
4199	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
4200	fLongMode ? 16 : 8, u64Address, HCPhys);
4201	return VERR_INVALID_PARAMETER;
4202	}
4203	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
4204
4205	int rc = VINF_SUCCESS;
4206	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4207	{
4208	X86PDEPAE Pde = pPD->a[i];
4209	if (Pde.n.u1Present)
4210	{
4211	if (fBigPagesSupported && Pde.b.u1Size)
4212	pHlp->pfnPrintf(pHlp,
4213	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4214	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
4215	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
4216	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4217	Pde.b.u1Write ? 'W' : 'R',
4218	Pde.b.u1User ? 'U' : 'S',
4219	Pde.b.u1Accessed ? 'A' : '-',
4220	Pde.b.u1Dirty ? 'D' : '-',
4221	Pde.b.u1Global ? 'G' : '-',
4222	Pde.b.u1WriteThru ? "WT" : "--",
4223	Pde.b.u1CacheDisable? "CD" : "--",
4224	Pde.b.u1PAT ? "AT" : "--",
4225	Pde.b.u1NoExecute ? "NX" : "--",
4226	Pde.u & RT_BIT_64(9) ? '1' : '0',
4227	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4228	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4229	Pde.u & X86_PDE_PAE_PG_MASK);
4230	else
4231	{
4232	pHlp->pfnPrintf(pHlp,
4233	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4234	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
4235	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
4236	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4237	Pde.n.u1Write ? 'W' : 'R',
4238	Pde.n.u1User ? 'U' : 'S',
4239	Pde.n.u1Accessed ? 'A' : '-',
4240	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4241	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4242	Pde.n.u1WriteThru ? "WT" : "--",
4243	Pde.n.u1CacheDisable? "CD" : "--",
4244	Pde.n.u1NoExecute ? "NX" : "--",
4245	Pde.u & RT_BIT_64(9) ? '1' : '0',
4246	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4247	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4248	Pde.u & X86_PDE_PAE_PG_MASK);
4249	if (cMaxDepth >= 1)
4250	{
4251	/** @todo what about using the page pool for mapping PTs? */
4252	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
4253	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
4254	PX86PTPAE pPT = NULL;
4255	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4256	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
4257	else
4258	{
4259	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4260	{
4261	uint64_t off = u64AddressPT - pMap->GCPtr;
4262	if (off < pMap->cb)
4263	{
4264	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
4265	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
4266	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
4267	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4268	fLongMode ? 16 : 8, u64AddressPT, iPDE,
4269	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
4270	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
4271	}
4272	}
4273	}
4274	int rc2 = VERR_INVALID_PARAMETER;
4275	if (pPT)
4276	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
4277	else
4278	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
4279	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
4280	if (rc2 < rc && RT_SUCCESS(rc))
4281	rc = rc2;
4282	}
4283	}
4284	}
4285	}
4286	return rc;
4287	}
4288
4289
4290	/**
4291	* Dumps a PAE shadow page directory pointer table.
4292	*
4293	* @returns VBox status code (VINF_SUCCESS).
4294	* @param pVM The VM handle.
4295	* @param HCPhys The physical address of the page directory pointer table.
4296	* @param u64Address The virtual address of the page table starts.
4297	* @param cr4 The CR4, PSE is currently used.
4298	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4299	* @param cMaxDepth The maxium depth.
4300	* @param pHlp Pointer to the output functions.
4301	*/
4302	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4303	{
4304	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
4305	if (!pPDPT)
4306	{
4307	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
4308	fLongMode ? 16 : 8, u64Address, HCPhys);
4309	return VERR_INVALID_PARAMETER;
4310	}
4311
4312	int rc = VINF_SUCCESS;
4313	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
4314	for (unsigned i = 0; i < c; i++)
4315	{
4316	X86PDPE Pdpe = pPDPT->a[i];
4317	if (Pdpe.n.u1Present)
4318	{
4319	if (fLongMode)
4320	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4321	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4322	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4323	Pdpe.lm.u1Write ? 'W' : 'R',
4324	Pdpe.lm.u1User ? 'U' : 'S',
4325	Pdpe.lm.u1Accessed ? 'A' : '-',
4326	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
4327	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
4328	Pdpe.lm.u1WriteThru ? "WT" : "--",
4329	Pdpe.lm.u1CacheDisable? "CD" : "--",
4330	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
4331	Pdpe.lm.u1NoExecute ? "NX" : "--",
4332	Pdpe.u & RT_BIT(9) ? '1' : '0',
4333	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4334	Pdpe.u & RT_BIT(11) ? '1' : '0',
4335	Pdpe.u & X86_PDPE_PG_MASK);
4336	else
4337	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
4338	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
4339	i << X86_PDPT_SHIFT,
4340	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
4341	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
4342	Pdpe.n.u1WriteThru ? "WT" : "--",
4343	Pdpe.n.u1CacheDisable? "CD" : "--",
4344	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
4345	Pdpe.u & RT_BIT(9) ? '1' : '0',
4346	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4347	Pdpe.u & RT_BIT(11) ? '1' : '0',
4348	Pdpe.u & X86_PDPE_PG_MASK);
4349	if (cMaxDepth >= 1)
4350	{
4351	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4352	cr4, fLongMode, cMaxDepth - 1, pHlp);
4353	if (rc2 < rc && RT_SUCCESS(rc))
4354	rc = rc2;
4355	}
4356	}
4357	}
4358	return rc;
4359	}
4360
4361
4362	/**
4363	* Dumps a 32-bit shadow page table.
4364	*
4365	* @returns VBox status code (VINF_SUCCESS).
4366	* @param pVM The VM handle.
4367	* @param HCPhys The physical address of the table.
4368	* @param cr4 The CR4, PSE is currently used.
4369	* @param cMaxDepth The maxium depth.
4370	* @param pHlp Pointer to the output functions.
4371	*/
4372	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4373	{
4374	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
4375	if (!pPML4)
4376	{
4377	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
4378	return VERR_INVALID_PARAMETER;
4379	}
4380
4381	int rc = VINF_SUCCESS;
4382	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
4383	{
4384	X86PML4E Pml4e = pPML4->a[i];
4385	if (Pml4e.n.u1Present)
4386	{
4387	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
4388	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4389	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4390	u64Address,
4391	Pml4e.n.u1Write ? 'W' : 'R',
4392	Pml4e.n.u1User ? 'U' : 'S',
4393	Pml4e.n.u1Accessed ? 'A' : '-',
4394	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
4395	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
4396	Pml4e.n.u1WriteThru ? "WT" : "--",
4397	Pml4e.n.u1CacheDisable? "CD" : "--",
4398	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
4399	Pml4e.n.u1NoExecute ? "NX" : "--",
4400	Pml4e.u & RT_BIT(9) ? '1' : '0',
4401	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4402	Pml4e.u & RT_BIT(11) ? '1' : '0',
4403	Pml4e.u & X86_PML4E_PG_MASK);
4404
4405	if (cMaxDepth >= 1)
4406	{
4407	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
4408	if (rc2 < rc && RT_SUCCESS(rc))
4409	rc = rc2;
4410	}
4411	}
4412	}
4413	return rc;
4414	}
4415
4416
4417	/**
4418	* Dumps a 32-bit shadow page table.
4419	*
4420	* @returns VBox status code (VINF_SUCCESS).
4421	* @param pVM The VM handle.
4422	* @param pPT Pointer to the page table.
4423	* @param u32Address The virtual address this table starts at.
4424	* @param pHlp Pointer to the output functions.
4425	*/
4426	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
4427	{
4428	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4429	{
4430	X86PTE Pte = pPT->a[i];
4431	if (Pte.n.u1Present)
4432	{
4433	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4434	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4435	u32Address + (i << X86_PT_SHIFT),
4436	Pte.n.u1Write ? 'W' : 'R',
4437	Pte.n.u1User ? 'U' : 'S',
4438	Pte.n.u1Accessed ? 'A' : '-',
4439	Pte.n.u1Dirty ? 'D' : '-',
4440	Pte.n.u1Global ? 'G' : '-',
4441	Pte.n.u1WriteThru ? "WT" : "--",
4442	Pte.n.u1CacheDisable? "CD" : "--",
4443	Pte.n.u1PAT ? "AT" : "--",
4444	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4445	Pte.u & RT_BIT(10) ? '1' : '0',
4446	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4447	Pte.u & X86_PDE_PG_MASK);
4448	}
4449	}
4450	return VINF_SUCCESS;
4451	}
4452
4453
4454	/**
4455	* Dumps a 32-bit shadow page directory and page tables.
4456	*
4457	* @returns VBox status code (VINF_SUCCESS).
4458	* @param pVM The VM handle.
4459	* @param cr3 The root of the hierarchy.
4460	* @param cr4 The CR4, PSE is currently used.
4461	* @param cMaxDepth How deep into the hierarchy the dumper should go.
4462	* @param pHlp Pointer to the output functions.
4463	*/
4464	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4465	{
4466	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
4467	if (!pPD)
4468	{
4469	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4470	return VERR_INVALID_PARAMETER;
4471	}
4472
4473	int rc = VINF_SUCCESS;
4474	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4475	{
4476	X86PDE Pde = pPD->a[i];
4477	if (Pde.n.u1Present)
4478	{
4479	const uint32_t u32Address = i << X86_PD_SHIFT;
4480	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4481	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4482	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4483	u32Address,
4484	Pde.b.u1Write ? 'W' : 'R',
4485	Pde.b.u1User ? 'U' : 'S',
4486	Pde.b.u1Accessed ? 'A' : '-',
4487	Pde.b.u1Dirty ? 'D' : '-',
4488	Pde.b.u1Global ? 'G' : '-',
4489	Pde.b.u1WriteThru ? "WT" : "--",
4490	Pde.b.u1CacheDisable? "CD" : "--",
4491	Pde.b.u1PAT ? "AT" : "--",
4492	Pde.u & RT_BIT_64(9) ? '1' : '0',
4493	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4494	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4495	Pde.u & X86_PDE4M_PG_MASK);
4496	else
4497	{
4498	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4499	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4500	u32Address,
4501	Pde.n.u1Write ? 'W' : 'R',
4502	Pde.n.u1User ? 'U' : 'S',
4503	Pde.n.u1Accessed ? 'A' : '-',
4504	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4505	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4506	Pde.n.u1WriteThru ? "WT" : "--",
4507	Pde.n.u1CacheDisable? "CD" : "--",
4508	Pde.u & RT_BIT_64(9) ? '1' : '0',
4509	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4510	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4511	Pde.u & X86_PDE_PG_MASK);
4512	if (cMaxDepth >= 1)
4513	{
4514	/** @todo what about using the page pool for mapping PTs? */
4515	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4516	PX86PT pPT = NULL;
4517	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4518	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4519	else
4520	{
4521	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4522	if (u32Address - pMap->GCPtr < pMap->cb)
4523	{
4524	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4525	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4526	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4527	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4528	pPT = pMap->aPTs[iPDE].pPTR3;
4529	}
4530	}
4531	int rc2 = VERR_INVALID_PARAMETER;
4532	if (pPT)
4533	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4534	else
4535	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4536	if (rc2 < rc && RT_SUCCESS(rc))
4537	rc = rc2;
4538	}
4539	}
4540	}
4541	}
4542
4543	return rc;
4544	}
4545
4546
4547	/**
4548	* Dumps a 32-bit shadow page table.
4549	*
4550	* @returns VBox status code (VINF_SUCCESS).
4551	* @param pVM The VM handle.
4552	* @param pPT Pointer to the page table.
4553	* @param u32Address The virtual address this table starts at.
4554	* @param PhysSearch Address to search for.
4555	*/
4556	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4557	{
4558	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4559	{
4560	X86PTE Pte = pPT->a[i];
4561	if (Pte.n.u1Present)
4562	{
4563	Log(( /P R S A D G WT CD AT NX 4M a m d /
4564	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4565	u32Address + (i << X86_PT_SHIFT),
4566	Pte.n.u1Write ? 'W' : 'R',
4567	Pte.n.u1User ? 'U' : 'S',
4568	Pte.n.u1Accessed ? 'A' : '-',
4569	Pte.n.u1Dirty ? 'D' : '-',
4570	Pte.n.u1Global ? 'G' : '-',
4571	Pte.n.u1WriteThru ? "WT" : "--",
4572	Pte.n.u1CacheDisable? "CD" : "--",
4573	Pte.n.u1PAT ? "AT" : "--",
4574	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4575	Pte.u & RT_BIT(10) ? '1' : '0',
4576	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4577	Pte.u & X86_PDE_PG_MASK));
4578
4579	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4580	{
4581	uint64_t fPageShw = 0;
4582	RTHCPHYS pPhysHC = 0;
4583
4584	/** @todo SMP support!! */
4585	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4586	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4587	}
4588	}
4589	}
4590	return VINF_SUCCESS;
4591	}
4592
4593
4594	/**
4595	* Dumps a 32-bit guest page directory and page tables.
4596	*
4597	* @returns VBox status code (VINF_SUCCESS).
4598	* @param pVM The VM handle.
4599	* @param cr3 The root of the hierarchy.
4600	* @param cr4 The CR4, PSE is currently used.
4601	* @param PhysSearch Address to search for.
4602	*/
4603	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4604	{
4605	bool fLongMode = false;
4606	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4607	PX86PD pPD = 0;
4608
4609	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4610	if (RT_FAILURE(rc) \|\| !pPD)
4611	{
4612	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4613	return VERR_INVALID_PARAMETER;
4614	}
4615
4616	Log(("cr3=%08x cr4=%08x%s\n"
4617	"%-*s P - Present\n"
4618	"%-*s \| R/W - Read (0) / Write (1)\n"
4619	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4620	"%-*s \| \| \| A - Accessed\n"
4621	"%-*s \| \| \| \| D - Dirty\n"
4622	"%-*s \| \| \| \| \| G - Global\n"
4623	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4624	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4625	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4626	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4627	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4628	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4629	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4630	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4631	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4632	- W U - - - -- -- -- -- -- 010 */
4633	, cr3, cr4, fLongMode ? " Long Mode" : "",
4634	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4635	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4636
4637	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4638	{
4639	X86PDE Pde = pPD->a[i];
4640	if (Pde.n.u1Present)
4641	{
4642	const uint32_t u32Address = i << X86_PD_SHIFT;
4643
4644	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4645	Log(( /P R S A D G WT CD AT NX 4M a m d /
4646	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4647	u32Address,
4648	Pde.b.u1Write ? 'W' : 'R',
4649	Pde.b.u1User ? 'U' : 'S',
4650	Pde.b.u1Accessed ? 'A' : '-',
4651	Pde.b.u1Dirty ? 'D' : '-',
4652	Pde.b.u1Global ? 'G' : '-',
4653	Pde.b.u1WriteThru ? "WT" : "--",
4654	Pde.b.u1CacheDisable? "CD" : "--",
4655	Pde.b.u1PAT ? "AT" : "--",
4656	Pde.u & RT_BIT(9) ? '1' : '0',
4657	Pde.u & RT_BIT(10) ? '1' : '0',
4658	Pde.u & RT_BIT(11) ? '1' : '0',
4659	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4660	/** @todo PhysSearch */
4661	else
4662	{
4663	Log(( /P R S A D G WT CD AT NX 4M a m d /
4664	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4665	u32Address,
4666	Pde.n.u1Write ? 'W' : 'R',
4667	Pde.n.u1User ? 'U' : 'S',
4668	Pde.n.u1Accessed ? 'A' : '-',
4669	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4670	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4671	Pde.n.u1WriteThru ? "WT" : "--",
4672	Pde.n.u1CacheDisable? "CD" : "--",
4673	Pde.u & RT_BIT(9) ? '1' : '0',
4674	Pde.u & RT_BIT(10) ? '1' : '0',
4675	Pde.u & RT_BIT(11) ? '1' : '0',
4676	Pde.u & X86_PDE_PG_MASK));
4677	////if (cMaxDepth >= 1)
4678	{
4679	/** @todo what about using the page pool for mapping PTs? */
4680	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4681	PX86PT pPT = NULL;
4682
4683	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4684
4685	int rc2 = VERR_INVALID_PARAMETER;
4686	if (pPT)
4687	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4688	else
4689	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4690	if (rc2 < rc && RT_SUCCESS(rc))
4691	rc = rc2;
4692	}
4693	}
4694	}
4695	}
4696
4697	return rc;
4698	}
4699
4700
4701	/**
4702	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4703	*
4704	* @returns VBox status code (VINF_SUCCESS).
4705	* @param pVM The VM handle.
4706	* @param cr3 The root of the hierarchy.
4707	* @param cr4 The cr4, only PAE and PSE is currently used.
4708	* @param fLongMode Set if long mode, false if not long mode.
4709	* @param cMaxDepth Number of levels to dump.
4710	* @param pHlp Pointer to the output functions.
4711	*/
4712	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4713	{
4714	if (!pHlp)
4715	pHlp = DBGFR3InfoLogHlp();
4716	if (!cMaxDepth)
4717	return VINF_SUCCESS;
4718	const unsigned cch = fLongMode ? 16 : 8;
4719	pHlp->pfnPrintf(pHlp,
4720	"cr3=%08x cr4=%08x%s\n"
4721	"%-*s P - Present\n"
4722	"%-*s \| R/W - Read (0) / Write (1)\n"
4723	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4724	"%-*s \| \| \| A - Accessed\n"
4725	"%-*s \| \| \| \| D - Dirty\n"
4726	"%-*s \| \| \| \| \| G - Global\n"
4727	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4728	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4729	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4730	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4731	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4732	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4733	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4734	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4735	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4736	- W U - - - -- -- -- -- -- 010 */
4737	, cr3, cr4, fLongMode ? " Long Mode" : "",
4738	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4739	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4740	if (cr4 & X86_CR4_PAE)
4741	{
4742	if (fLongMode)
4743	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4744	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4745	}
4746	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4747	}
4748
4749	#ifdef VBOX_WITH_DEBUGGER
4750
4751	/**
4752	* The '.pgmram' command.
4753	*
4754	* @returns VBox status.
4755	* @param pCmd Pointer to the command descriptor (as registered).
4756	* @param pCmdHlp Pointer to command helper functions.
4757	* @param pVM Pointer to the current VM (if any).
4758	* @param paArgs Pointer to (readonly) array of arguments.
4759	* @param cArgs Number of arguments in the array.
4760	*/
4761	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4762	{
4763	/*
4764	* Validate input.
4765	*/
4766	if (!pVM)
4767	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4768	if (!pVM->pgm.s.pRamRangesRC)
4769	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4770
4771	/*
4772	* Dump the ranges.
4773	*/
4774	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4775	PPGMRAMRANGE pRam;
4776	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4777	{
4778	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4779	"%RGp - %RGp %p\n",
4780	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4781	if (RT_FAILURE(rc))
4782	return rc;
4783	}
4784
4785	return VINF_SUCCESS;
4786	}
4787
4788
4789	/**
4790	* The '.pgmmap' command.
4791	*
4792	* @returns VBox status.
4793	* @param pCmd Pointer to the command descriptor (as registered).
4794	* @param pCmdHlp Pointer to command helper functions.
4795	* @param pVM Pointer to the current VM (if any).
4796	* @param paArgs Pointer to (readonly) array of arguments.
4797	* @param cArgs Number of arguments in the array.
4798	*/
4799	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4800	{
4801	/*
4802	* Validate input.
4803	*/
4804	if (!pVM)
4805	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4806	if (!pVM->pgm.s.pMappingsR3)
4807	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4808
4809	/*
4810	* Print message about the fixedness of the mappings.
4811	*/
4812	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4813	if (RT_FAILURE(rc))
4814	return rc;
4815
4816	/*
4817	* Dump the ranges.
4818	*/
4819	PPGMMAPPING pCur;
4820	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4821	{
4822	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4823	"%08x - %08x %s\n",
4824	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4825	if (RT_FAILURE(rc))
4826	return rc;
4827	}
4828
4829	return VINF_SUCCESS;
4830	}
4831
4832
4833	/**
4834	* The '.pgmerror' and '.pgmerroroff' commands.
4835	*
4836	* @returns VBox status.
4837	* @param pCmd Pointer to the command descriptor (as registered).
4838	* @param pCmdHlp Pointer to command helper functions.
4839	* @param pVM Pointer to the current VM (if any).
4840	* @param paArgs Pointer to (readonly) array of arguments.
4841	* @param cArgs Number of arguments in the array.
4842	*/
4843	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4844	{
4845	/*
4846	* Validate input.
4847	*/
4848	if (!pVM)
4849	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4850	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4851	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4852
4853	if (!cArgs)
4854	{
4855	/*
4856	* Print the list of error injection locations with status.
4857	*/
4858	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4859	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4860	}
4861	else
4862	{
4863
4864	/*
4865	* String switch on where to inject the error.
4866	*/
4867	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4868	const char *pszWhere = paArgs[0].u.pszString;
4869	if (!strcmp(pszWhere, "handy"))
4870	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4871	else
4872	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4873	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4874	}
4875	return VINF_SUCCESS;
4876	}
4877
4878
4879	/**
4880	* The '.pgmsync' command.
4881	*
4882	* @returns VBox status.
4883	* @param pCmd Pointer to the command descriptor (as registered).
4884	* @param pCmdHlp Pointer to command helper functions.
4885	* @param pVM Pointer to the current VM (if any).
4886	* @param paArgs Pointer to (readonly) array of arguments.
4887	* @param cArgs Number of arguments in the array.
4888	*/
4889	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4890	{
4891	/** @todo SMP support */
4892	PVMCPU pVCpu = &pVM->aCpus[0];
4893
4894	/*
4895	* Validate input.
4896	*/
4897	if (!pVM)
4898	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4899
4900	/*
4901	* Force page directory sync.
4902	*/
4903	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4904
4905	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4906	if (RT_FAILURE(rc))
4907	return rc;
4908
4909	return VINF_SUCCESS;
4910	}
4911
4912
4913	#ifdef VBOX_STRICT
4914	/**
4915	* The '.pgmassertcr3' command.
4916	*
4917	* @returns VBox status.
4918	* @param pCmd Pointer to the command descriptor (as registered).
4919	* @param pCmdHlp Pointer to command helper functions.
4920	* @param pVM Pointer to the current VM (if any).
4921	* @param paArgs Pointer to (readonly) array of arguments.
4922	* @param cArgs Number of arguments in the array.
4923	*/
4924	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4925	{
4926	/** @todo SMP support!! */
4927	PVMCPU pVCpu = &pVM->aCpus[0];
4928
4929	/*
4930	* Validate input.
4931	*/
4932	if (!pVM)
4933	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4934
4935	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4936	if (RT_FAILURE(rc))
4937	return rc;
4938
4939	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4940
4941	return VINF_SUCCESS;
4942	}
4943	#endif /* VBOX_STRICT */
4944
4945
4946	/**
4947	* The '.pgmsyncalways' command.
4948	*
4949	* @returns VBox status.
4950	* @param pCmd Pointer to the command descriptor (as registered).
4951	* @param pCmdHlp Pointer to command helper functions.
4952	* @param pVM Pointer to the current VM (if any).
4953	* @param paArgs Pointer to (readonly) array of arguments.
4954	* @param cArgs Number of arguments in the array.
4955	*/
4956	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4957	{
4958	/** @todo SMP support!! */
4959	PVMCPU pVCpu = &pVM->aCpus[0];
4960
4961	/*
4962	* Validate input.
4963	*/
4964	if (!pVM)
4965	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4966
4967	/*
4968	* Force page directory sync.
4969	*/
4970	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4971	{
4972	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4973	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4974	}
4975	else
4976	{
4977	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4978	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4979	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4980	}
4981	}
4982
4983
4984	/**
4985	* The '.pgmsyncalways' command.
4986	*
4987	* @returns VBox status.
4988	* @param pCmd Pointer to the command descriptor (as registered).
4989	* @param pCmdHlp Pointer to command helper functions.
4990	* @param pVM Pointer to the current VM (if any).
4991	* @param paArgs Pointer to (readonly) array of arguments.
4992	* @param cArgs Number of arguments in the array.
4993	*/
4994	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4995	{
4996	/*
4997	* Validate input.
4998	*/
4999	if (!pVM)
5000	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
5001	if ( cArgs < 1
5002	\|\| cArgs > 2
5003	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
5004	\|\| ( cArgs > 1
5005	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
5006	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
5007	if ( cArgs >= 2
5008	&& strcmp(paArgs[1].u.pszString, "nozero"))
5009	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
5010	bool fIncZeroPgs = cArgs < 2;
5011
5012	/*
5013	* Open the output file and get the ram parameters.
5014	*/
5015	RTFILE hFile;
5016	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
5017	if (RT_FAILURE(rc))
5018	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
5019
5020	uint32_t cbRamHole = 0;
5021	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
5022	uint64_t cbRam = 0;
5023	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
5024	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
5025
5026	/*
5027	* Dump the physical memory, page by page.
5028	*/
5029	RTGCPHYS GCPhys = 0;
5030	char abZeroPg[PAGE_SIZE];
5031	RT_ZERO(abZeroPg);
5032
5033	pgmLock(pVM);
5034	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
5035	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
5036	pRam = pRam->pNextR3)
5037	{
5038	/* fill the gap */
5039	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
5040	{
5041	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
5042	{
5043	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5044	GCPhys += PAGE_SIZE;
5045	}
5046	}
5047
5048	PCPGMPAGE pPage = &pRam->aPages[0];
5049	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
5050	{
5051	if (PGM_PAGE_IS_ZERO(pPage))
5052	{
5053	if (fIncZeroPgs)
5054	{
5055	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5056	if (RT_FAILURE(rc))
5057	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5058	}
5059	}
5060	else
5061	{
5062	switch (PGM_PAGE_GET_TYPE(pPage))
5063	{
5064	case PGMPAGETYPE_RAM:
5065	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
5066	case PGMPAGETYPE_ROM:
5067	case PGMPAGETYPE_MMIO2:
5068	{
5069	void const *pvPage;
5070	PGMPAGEMAPLOCK Lock;
5071	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
5072	if (RT_SUCCESS(rc))
5073	{
5074	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
5075	PGMPhysReleasePageMappingLock(pVM, &Lock);
5076	if (RT_FAILURE(rc))
5077	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5078	}
5079	else
5080	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5081	break;
5082	}
5083
5084	default:
5085	AssertFailed();
5086	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
5087	case PGMPAGETYPE_MMIO:
5088	if (fIncZeroPgs)
5089	{
5090	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5091	if (RT_FAILURE(rc))
5092	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5093	}
5094	break;
5095	}
5096	}
5097
5098
5099	/* advance */
5100	GCPhys += PAGE_SIZE;
5101	pPage++;
5102	}
5103	}
5104	pgmUnlock(pVM);
5105
5106	RTFileClose(hFile);
5107	if (RT_SUCCESS(rc))
5108	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
5109	return VINF_SUCCESS;
5110	}
5111
5112	#endif /* VBOX_WITH_DEBUGGER */
5113
5114	/**
5115	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
5116	*/
5117	typedef struct PGMCHECKINTARGS
5118	{
5119	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
5120	PPGMPHYSHANDLER pPrevPhys;
5121	PPGMVIRTHANDLER pPrevVirt;
5122	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
5123	PVM pVM;
5124	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
5125
5126	/**
5127	* Validate a node in the physical handler tree.
5128	*
5129	* @returns 0 on if ok, other wise 1.
5130	* @param pNode The handler node.
5131	* @param pvUser pVM.
5132	*/
5133	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5134	{
5135	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5136	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
5137	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5138	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5139	AssertReleaseMsg( !pArgs->pPrevPhys
5140	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
5141	("pPrevPhys=%p %RGp-%RGp %s\n"
5142	" pCur=%p %RGp-%RGp %s\n",
5143	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
5144	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5145	pArgs->pPrevPhys = pCur;
5146	return 0;
5147	}
5148
5149
5150	/**
5151	* Validate a node in the virtual handler tree.
5152	*
5153	* @returns 0 on if ok, other wise 1.
5154	* @param pNode The handler node.
5155	* @param pvUser pVM.
5156	*/
5157	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
5158	{
5159	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5160	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
5161	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5162	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5163	AssertReleaseMsg( !pArgs->pPrevVirt
5164	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
5165	("pPrevVirt=%p %RGv-%RGv %s\n"
5166	" pCur=%p %RGv-%RGv %s\n",
5167	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
5168	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5169	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
5170	{
5171	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
5172	("pCur=%p %RGv-%RGv %s\n"
5173	"iPage=%d offVirtHandle=%#x expected %#x\n",
5174	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
5175	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
5176	}
5177	pArgs->pPrevVirt = pCur;
5178	return 0;
5179	}
5180
5181
5182	/**
5183	* Validate a node in the virtual handler tree.
5184	*
5185	* @returns 0 on if ok, other wise 1.
5186	* @param pNode The handler node.
5187	* @param pvUser pVM.
5188	*/
5189	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5190	{
5191	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5192	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
5193	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
5194	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
5195	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
5196	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5197	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5198	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5199	" pCur=%p %RGp-%RGp\n",
5200	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5201	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5202	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5203	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5204	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5205	" pCur=%p %RGp-%RGp\n",
5206	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5207	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5208	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
5209	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5210	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5211	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
5212	{
5213	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
5214	for (;;)
5215	{
5216	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
5217	AssertReleaseMsg(pCur2 != pCur,
5218	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5219	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5220	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
5221	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5222	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5223	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5224	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5225	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
5226	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5227	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5228	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5229	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5230	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
5231	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5232	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5233	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5234	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5235	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
5236	break;
5237	}
5238	}
5239
5240	pArgs->pPrevPhys2Virt = pCur;
5241	return 0;
5242	}
5243
5244
5245	/**
5246	* Perform an integrity check on the PGM component.
5247	*
5248	* @returns VINF_SUCCESS if everything is fine.
5249	* @returns VBox error status after asserting on integrity breach.
5250	* @param pVM The VM handle.
5251	*/
5252	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
5253	{
5254	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
5255
5256	/*
5257	* Check the trees.
5258	*/
5259	int cErrors = 0;
5260	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
5261	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
5262	PGMCHECKINTARGS Args = s_LeftToRight;
5263	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5264	Args = s_RightToLeft;
5265	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5266	Args = s_LeftToRight;
5267	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5268	Args = s_RightToLeft;
5269	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5270	Args = s_LeftToRight;
5271	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5272	Args = s_RightToLeft;
5273	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5274	Args = s_LeftToRight;
5275	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5276	Args = s_RightToLeft;
5277	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5278
5279	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
5280	}
5281
5282

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 22793

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