PGM.cpp@ 21164

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1	/* $Id: PGM.cpp 21164 2009-07-02 14:08:29Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#ifdef DEBUG_bird
602	# include <iprt/env.h>
603	#endif
604	#include <VBox/param.h>
605	#include <VBox/err.h>
606
607
608	/*******************************************************************************
609	* Defined Constants And Macros *
610	*******************************************************************************/
611	/** Saved state data unit version for 2.5.x and later. */
612	#define PGM_SAVED_STATE_VERSION 9
613	/** Saved state data unit version for 2.2.2 and later. */
614	#define PGM_SAVED_STATE_VERSION_2_2_2 8
615	/** Saved state data unit version for 2.2.0. */
616	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
617	/** Saved state data unit version. */
618	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
619
620
621	/*******************************************************************************
622	* Internal Functions *
623	*******************************************************************************/
624	static int pgmR3InitPaging(PVM pVM);
625	static void pgmR3InitStats(PVM pVM);
626	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
628	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
629	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
630	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
631	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
632	#ifdef VBOX_STRICT
633	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
634	#endif
635	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
636	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
637	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
638	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
639	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
640
641	#ifdef VBOX_WITH_DEBUGGER
642	/** @todo Convert the first two commands to 'info' items. */
643	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
645	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
647	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	# ifdef VBOX_STRICT
649	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
650	# endif
651	#endif
652
653
654	/*******************************************************************************
655	* Global Variables *
656	*******************************************************************************/
657	#ifdef VBOX_WITH_DEBUGGER
658	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
659	static const DBGCVARDESC g_aPgmErrorArgs[] =
660	{
661	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
662	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
663	};
664
665	/** Command descriptors. */
666	static const DBGCCMD g_aCmds[] =
667	{
668	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
669	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
670	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
671	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
672	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0],1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
673	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0],1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
674	#ifdef VBOX_STRICT
675	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
676	#endif
677	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
678	};
679	#endif
680
681
682
683
684	/*
685	* Shadow - 32-bit mode
686	*/
687	#define PGM_SHW_TYPE PGM_TYPE_32BIT
688	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
689	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
690	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
691	#include "PGMShw.h"
692
693	/* Guest - real mode */
694	#define PGM_GST_TYPE PGM_TYPE_REAL
695	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
696	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
697	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
698	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
699	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
700	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
701	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
702	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
703	#include "PGMBth.h"
704	#include "PGMGstDefs.h"
705	#include "PGMGst.h"
706	#undef BTH_PGMPOOLKIND_PT_FOR_PT
707	#undef BTH_PGMPOOLKIND_ROOT
708	#undef PGM_BTH_NAME
709	#undef PGM_BTH_NAME_RC_STR
710	#undef PGM_BTH_NAME_R0_STR
711	#undef PGM_GST_TYPE
712	#undef PGM_GST_NAME
713	#undef PGM_GST_NAME_RC_STR
714	#undef PGM_GST_NAME_R0_STR
715
716	/* Guest - protected mode */
717	#define PGM_GST_TYPE PGM_TYPE_PROT
718	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
719	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
720	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
721	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
722	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
723	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
724	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
725	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
726	#include "PGMBth.h"
727	#include "PGMGstDefs.h"
728	#include "PGMGst.h"
729	#undef BTH_PGMPOOLKIND_PT_FOR_PT
730	#undef BTH_PGMPOOLKIND_ROOT
731	#undef PGM_BTH_NAME
732	#undef PGM_BTH_NAME_RC_STR
733	#undef PGM_BTH_NAME_R0_STR
734	#undef PGM_GST_TYPE
735	#undef PGM_GST_NAME
736	#undef PGM_GST_NAME_RC_STR
737	#undef PGM_GST_NAME_R0_STR
738
739	/* Guest - 32-bit mode */
740	#define PGM_GST_TYPE PGM_TYPE_32BIT
741	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
742	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
743	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
744	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
745	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
746	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
747	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
748	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
749	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
750	#include "PGMBth.h"
751	#include "PGMGstDefs.h"
752	#include "PGMGst.h"
753	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
754	#undef BTH_PGMPOOLKIND_PT_FOR_PT
755	#undef BTH_PGMPOOLKIND_ROOT
756	#undef PGM_BTH_NAME
757	#undef PGM_BTH_NAME_RC_STR
758	#undef PGM_BTH_NAME_R0_STR
759	#undef PGM_GST_TYPE
760	#undef PGM_GST_NAME
761	#undef PGM_GST_NAME_RC_STR
762	#undef PGM_GST_NAME_R0_STR
763
764	#undef PGM_SHW_TYPE
765	#undef PGM_SHW_NAME
766	#undef PGM_SHW_NAME_RC_STR
767	#undef PGM_SHW_NAME_R0_STR
768
769
770	/*
771	* Shadow - PAE mode
772	*/
773	#define PGM_SHW_TYPE PGM_TYPE_PAE
774	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
775	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
776	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
777	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
778	#include "PGMShw.h"
779
780	/* Guest - real mode */
781	#define PGM_GST_TYPE PGM_TYPE_REAL
782	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
783	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
784	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
785	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
786	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
787	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
788	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
789	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
790	#include "PGMGstDefs.h"
791	#include "PGMBth.h"
792	#undef BTH_PGMPOOLKIND_PT_FOR_PT
793	#undef BTH_PGMPOOLKIND_ROOT
794	#undef PGM_BTH_NAME
795	#undef PGM_BTH_NAME_RC_STR
796	#undef PGM_BTH_NAME_R0_STR
797	#undef PGM_GST_TYPE
798	#undef PGM_GST_NAME
799	#undef PGM_GST_NAME_RC_STR
800	#undef PGM_GST_NAME_R0_STR
801
802	/* Guest - protected mode */
803	#define PGM_GST_TYPE PGM_TYPE_PROT
804	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
805	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
806	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
807	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
808	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
809	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
810	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
811	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
812	#include "PGMGstDefs.h"
813	#include "PGMBth.h"
814	#undef BTH_PGMPOOLKIND_PT_FOR_PT
815	#undef BTH_PGMPOOLKIND_ROOT
816	#undef PGM_BTH_NAME
817	#undef PGM_BTH_NAME_RC_STR
818	#undef PGM_BTH_NAME_R0_STR
819	#undef PGM_GST_TYPE
820	#undef PGM_GST_NAME
821	#undef PGM_GST_NAME_RC_STR
822	#undef PGM_GST_NAME_R0_STR
823
824	/* Guest - 32-bit mode */
825	#define PGM_GST_TYPE PGM_TYPE_32BIT
826	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
827	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
828	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
829	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
830	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
831	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
832	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
833	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
834	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
835	#include "PGMGstDefs.h"
836	#include "PGMBth.h"
837	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
838	#undef BTH_PGMPOOLKIND_PT_FOR_PT
839	#undef BTH_PGMPOOLKIND_ROOT
840	#undef PGM_BTH_NAME
841	#undef PGM_BTH_NAME_RC_STR
842	#undef PGM_BTH_NAME_R0_STR
843	#undef PGM_GST_TYPE
844	#undef PGM_GST_NAME
845	#undef PGM_GST_NAME_RC_STR
846	#undef PGM_GST_NAME_R0_STR
847
848	/* Guest - PAE mode */
849	#define PGM_GST_TYPE PGM_TYPE_PAE
850	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
851	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
852	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
853	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
854	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
855	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
856	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
857	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
858	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
859	#include "PGMBth.h"
860	#include "PGMGstDefs.h"
861	#include "PGMGst.h"
862	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
863	#undef BTH_PGMPOOLKIND_PT_FOR_PT
864	#undef BTH_PGMPOOLKIND_ROOT
865	#undef PGM_BTH_NAME
866	#undef PGM_BTH_NAME_RC_STR
867	#undef PGM_BTH_NAME_R0_STR
868	#undef PGM_GST_TYPE
869	#undef PGM_GST_NAME
870	#undef PGM_GST_NAME_RC_STR
871	#undef PGM_GST_NAME_R0_STR
872
873	#undef PGM_SHW_TYPE
874	#undef PGM_SHW_NAME
875	#undef PGM_SHW_NAME_RC_STR
876	#undef PGM_SHW_NAME_R0_STR
877
878
879	/*
880	* Shadow - AMD64 mode
881	*/
882	#define PGM_SHW_TYPE PGM_TYPE_AMD64
883	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
884	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
885	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
886	#include "PGMShw.h"
887
888	#ifdef VBOX_WITH_64_BITS_GUESTS
889	/* Guest - AMD64 mode */
890	# define PGM_GST_TYPE PGM_TYPE_AMD64
891	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
892	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
893	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
894	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
895	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
896	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
897	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
898	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
899	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
900	# include "PGMBth.h"
901	# include "PGMGstDefs.h"
902	# include "PGMGst.h"
903	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
904	# undef BTH_PGMPOOLKIND_PT_FOR_PT
905	# undef BTH_PGMPOOLKIND_ROOT
906	# undef PGM_BTH_NAME
907	# undef PGM_BTH_NAME_RC_STR
908	# undef PGM_BTH_NAME_R0_STR
909	# undef PGM_GST_TYPE
910	# undef PGM_GST_NAME
911	# undef PGM_GST_NAME_RC_STR
912	# undef PGM_GST_NAME_R0_STR
913	#endif /* VBOX_WITH_64_BITS_GUESTS */
914
915	#undef PGM_SHW_TYPE
916	#undef PGM_SHW_NAME
917	#undef PGM_SHW_NAME_RC_STR
918	#undef PGM_SHW_NAME_R0_STR
919
920
921	/*
922	* Shadow - Nested paging mode
923	*/
924	#define PGM_SHW_TYPE PGM_TYPE_NESTED
925	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
926	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
927	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
928	#include "PGMShw.h"
929
930	/* Guest - real mode */
931	#define PGM_GST_TYPE PGM_TYPE_REAL
932	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
933	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
934	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
935	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
936	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
937	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
938	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
939	#include "PGMGstDefs.h"
940	#include "PGMBth.h"
941	#undef BTH_PGMPOOLKIND_PT_FOR_PT
942	#undef PGM_BTH_NAME
943	#undef PGM_BTH_NAME_RC_STR
944	#undef PGM_BTH_NAME_R0_STR
945	#undef PGM_GST_TYPE
946	#undef PGM_GST_NAME
947	#undef PGM_GST_NAME_RC_STR
948	#undef PGM_GST_NAME_R0_STR
949
950	/* Guest - protected mode */
951	#define PGM_GST_TYPE PGM_TYPE_PROT
952	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
953	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
954	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
955	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
956	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
957	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
958	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
959	#include "PGMGstDefs.h"
960	#include "PGMBth.h"
961	#undef BTH_PGMPOOLKIND_PT_FOR_PT
962	#undef PGM_BTH_NAME
963	#undef PGM_BTH_NAME_RC_STR
964	#undef PGM_BTH_NAME_R0_STR
965	#undef PGM_GST_TYPE
966	#undef PGM_GST_NAME
967	#undef PGM_GST_NAME_RC_STR
968	#undef PGM_GST_NAME_R0_STR
969
970	/* Guest - 32-bit mode */
971	#define PGM_GST_TYPE PGM_TYPE_32BIT
972	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
973	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
974	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
975	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
976	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
977	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
978	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
979	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
980	#include "PGMGstDefs.h"
981	#include "PGMBth.h"
982	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
983	#undef BTH_PGMPOOLKIND_PT_FOR_PT
984	#undef PGM_BTH_NAME
985	#undef PGM_BTH_NAME_RC_STR
986	#undef PGM_BTH_NAME_R0_STR
987	#undef PGM_GST_TYPE
988	#undef PGM_GST_NAME
989	#undef PGM_GST_NAME_RC_STR
990	#undef PGM_GST_NAME_R0_STR
991
992	/* Guest - PAE mode */
993	#define PGM_GST_TYPE PGM_TYPE_PAE
994	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
995	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
996	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
997	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
998	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
999	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1000	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1001	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1002	#include "PGMGstDefs.h"
1003	#include "PGMBth.h"
1004	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1005	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1006	#undef PGM_BTH_NAME
1007	#undef PGM_BTH_NAME_RC_STR
1008	#undef PGM_BTH_NAME_R0_STR
1009	#undef PGM_GST_TYPE
1010	#undef PGM_GST_NAME
1011	#undef PGM_GST_NAME_RC_STR
1012	#undef PGM_GST_NAME_R0_STR
1013
1014	#ifdef VBOX_WITH_64_BITS_GUESTS
1015	/* Guest - AMD64 mode */
1016	# define PGM_GST_TYPE PGM_TYPE_AMD64
1017	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1018	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1019	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1020	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1021	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1022	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1023	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1024	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1025	# include "PGMGstDefs.h"
1026	# include "PGMBth.h"
1027	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1028	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1029	# undef PGM_BTH_NAME
1030	# undef PGM_BTH_NAME_RC_STR
1031	# undef PGM_BTH_NAME_R0_STR
1032	# undef PGM_GST_TYPE
1033	# undef PGM_GST_NAME
1034	# undef PGM_GST_NAME_RC_STR
1035	# undef PGM_GST_NAME_R0_STR
1036	#endif /* VBOX_WITH_64_BITS_GUESTS */
1037
1038	#undef PGM_SHW_TYPE
1039	#undef PGM_SHW_NAME
1040	#undef PGM_SHW_NAME_RC_STR
1041	#undef PGM_SHW_NAME_R0_STR
1042
1043
1044	/*
1045	* Shadow - EPT
1046	*/
1047	#define PGM_SHW_TYPE PGM_TYPE_EPT
1048	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1049	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1050	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1051	#include "PGMShw.h"
1052
1053	/* Guest - real mode */
1054	#define PGM_GST_TYPE PGM_TYPE_REAL
1055	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1056	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1057	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1058	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1059	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1060	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1061	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1062	#include "PGMGstDefs.h"
1063	#include "PGMBth.h"
1064	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1065	#undef PGM_BTH_NAME
1066	#undef PGM_BTH_NAME_RC_STR
1067	#undef PGM_BTH_NAME_R0_STR
1068	#undef PGM_GST_TYPE
1069	#undef PGM_GST_NAME
1070	#undef PGM_GST_NAME_RC_STR
1071	#undef PGM_GST_NAME_R0_STR
1072
1073	/* Guest - protected mode */
1074	#define PGM_GST_TYPE PGM_TYPE_PROT
1075	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1076	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1077	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1078	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1079	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1080	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1081	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1082	#include "PGMGstDefs.h"
1083	#include "PGMBth.h"
1084	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1085	#undef PGM_BTH_NAME
1086	#undef PGM_BTH_NAME_RC_STR
1087	#undef PGM_BTH_NAME_R0_STR
1088	#undef PGM_GST_TYPE
1089	#undef PGM_GST_NAME
1090	#undef PGM_GST_NAME_RC_STR
1091	#undef PGM_GST_NAME_R0_STR
1092
1093	/* Guest - 32-bit mode */
1094	#define PGM_GST_TYPE PGM_TYPE_32BIT
1095	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1096	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1097	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1098	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1099	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1100	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1101	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1102	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1103	#include "PGMGstDefs.h"
1104	#include "PGMBth.h"
1105	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1106	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1107	#undef PGM_BTH_NAME
1108	#undef PGM_BTH_NAME_RC_STR
1109	#undef PGM_BTH_NAME_R0_STR
1110	#undef PGM_GST_TYPE
1111	#undef PGM_GST_NAME
1112	#undef PGM_GST_NAME_RC_STR
1113	#undef PGM_GST_NAME_R0_STR
1114
1115	/* Guest - PAE mode */
1116	#define PGM_GST_TYPE PGM_TYPE_PAE
1117	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1118	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1119	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1120	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1121	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1122	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1123	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1124	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1125	#include "PGMGstDefs.h"
1126	#include "PGMBth.h"
1127	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1128	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1129	#undef PGM_BTH_NAME
1130	#undef PGM_BTH_NAME_RC_STR
1131	#undef PGM_BTH_NAME_R0_STR
1132	#undef PGM_GST_TYPE
1133	#undef PGM_GST_NAME
1134	#undef PGM_GST_NAME_RC_STR
1135	#undef PGM_GST_NAME_R0_STR
1136
1137	#ifdef VBOX_WITH_64_BITS_GUESTS
1138	/* Guest - AMD64 mode */
1139	# define PGM_GST_TYPE PGM_TYPE_AMD64
1140	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1141	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1142	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1143	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1144	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1145	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1146	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1147	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1148	# include "PGMGstDefs.h"
1149	# include "PGMBth.h"
1150	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1151	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1152	# undef PGM_BTH_NAME
1153	# undef PGM_BTH_NAME_RC_STR
1154	# undef PGM_BTH_NAME_R0_STR
1155	# undef PGM_GST_TYPE
1156	# undef PGM_GST_NAME
1157	# undef PGM_GST_NAME_RC_STR
1158	# undef PGM_GST_NAME_R0_STR
1159	#endif /* VBOX_WITH_64_BITS_GUESTS */
1160
1161	#undef PGM_SHW_TYPE
1162	#undef PGM_SHW_NAME
1163	#undef PGM_SHW_NAME_RC_STR
1164	#undef PGM_SHW_NAME_R0_STR
1165
1166
1167
1168	/**
1169	* Initiates the paging of VM.
1170	*
1171	* @returns VBox status code.
1172	* @param pVM Pointer to VM structure.
1173	*/
1174	VMMR3DECL(int) PGMR3Init(PVM pVM)
1175	{
1176	LogFlow(("PGMR3Init:\n"));
1177	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1178	int rc;
1179
1180	/*
1181	* Assert alignment and sizes.
1182	*/
1183	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1184	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1185
1186	/*
1187	* Init the structure.
1188	*/
1189	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1190	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1191
1192	/* Init the per-CPU part. */
1193	for (unsigned i=0;i<pVM->cCPUs;i++)
1194	{
1195	PVMCPU pVCpu = &pVM->aCpus[i];
1196	PPGMCPU pPGM = &pVCpu->pgm.s;
1197
1198	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1199	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1200	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1201
1202	pPGM->enmShadowMode = PGMMODE_INVALID;
1203	pPGM->enmGuestMode = PGMMODE_INVALID;
1204
1205	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1206
1207	pPGM->pGstPaePdptR3 = NULL;
1208	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1209	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1210	#endif
1211	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1212	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1213	{
1214	pPGM->apGstPaePDsR3[i] = NULL;
1215	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1216	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1217	#endif
1218	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1219	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1220	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1221	}
1222
1223	pPGM->fA20Enabled = true;
1224	}
1225
1226	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1227	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1228	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1229
1230	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1231	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1232	true
1233	#else
1234	false
1235	#endif
1236	);
1237	AssertLogRelRCReturn(rc, rc);
1238
1239	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1240	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1241	#else
1242	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1243	#endif
1244	AssertLogRelRCReturn(rc, rc);
1245	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1246	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1247
1248	/*
1249	* Get the configured RAM size - to estimate saved state size.
1250	*/
1251	uint64_t cbRam;
1252	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1253	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1254	cbRam = 0;
1255	else if (RT_SUCCESS(rc))
1256	{
1257	if (cbRam < PAGE_SIZE)
1258	cbRam = 0;
1259	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1260	}
1261	else
1262	{
1263	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1264	return rc;
1265	}
1266
1267	/*
1268	* Register callbacks, string formatters and the saved state data unit.
1269	*/
1270	#ifdef VBOX_STRICT
1271	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1272	#endif
1273	PGMRegisterStringFormatTypes();
1274
1275	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1276	NULL, pgmR3Save, NULL,
1277	NULL, pgmR3Load, NULL);
1278	if (RT_FAILURE(rc))
1279	return rc;
1280
1281	/*
1282	* Initialize the PGM critical section and flush the phys TLBs
1283	*/
1284	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1285	AssertRCReturn(rc, rc);
1286
1287	PGMR3PhysChunkInvalidateTLB(pVM);
1288	PGMPhysInvalidatePageR3MapTLB(pVM);
1289	PGMPhysInvalidatePageR0MapTLB(pVM);
1290	PGMPhysInvalidatePageGCMapTLB(pVM);
1291
1292	/*
1293	* For the time being we sport a full set of handy pages in addition to the base
1294	* memory to simplify things.
1295	*/
1296	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1297	AssertRCReturn(rc, rc);
1298
1299	/*
1300	* Trees
1301	*/
1302	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1303	if (RT_SUCCESS(rc))
1304	{
1305	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1306	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1307
1308	/*
1309	* Alocate the zero page.
1310	*/
1311	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1312	}
1313	if (RT_SUCCESS(rc))
1314	{
1315	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1316	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1317	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1318	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1319
1320	/*
1321	* Init the paging.
1322	*/
1323	rc = pgmR3InitPaging(pVM);
1324	}
1325	if (RT_SUCCESS(rc))
1326	{
1327	/*
1328	* Init the page pool.
1329	*/
1330	rc = pgmR3PoolInit(pVM);
1331	}
1332	if (RT_SUCCESS(rc))
1333	{
1334	for (unsigned i=0;i<pVM->cCPUs;i++)
1335	{
1336	PVMCPU pVCpu = &pVM->aCpus[i];
1337
1338	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1339	if (RT_FAILURE(rc))
1340	break;
1341	}
1342	}
1343
1344	if (RT_SUCCESS(rc))
1345	{
1346	/*
1347	* Info & statistics
1348	*/
1349	DBGFR3InfoRegisterInternal(pVM, "mode",
1350	"Shows the current paging mode. "
1351	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1352	pgmR3InfoMode);
1353	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1354	"Dumps all the entries in the top level paging table. No arguments.",
1355	pgmR3InfoCr3);
1356	DBGFR3InfoRegisterInternal(pVM, "phys",
1357	"Dumps all the physical address ranges. No arguments.",
1358	pgmR3PhysInfo);
1359	DBGFR3InfoRegisterInternal(pVM, "handlers",
1360	"Dumps physical, virtual and hyper virtual handlers. "
1361	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1362	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1363	pgmR3InfoHandlers);
1364	DBGFR3InfoRegisterInternal(pVM, "mappings",
1365	"Dumps guest mappings.",
1366	pgmR3MapInfo);
1367
1368	pgmR3InitStats(pVM);
1369
1370	#ifdef VBOX_WITH_DEBUGGER
1371	/*
1372	* Debugger commands.
1373	*/
1374	static bool s_fRegisteredCmds = false;
1375	if (!s_fRegisteredCmds)
1376	{
1377	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1378	if (RT_SUCCESS(rc))
1379	s_fRegisteredCmds = true;
1380	}
1381	#endif
1382	return VINF_SUCCESS;
1383	}
1384
1385	/* Almost no cleanup necessary, MM frees all memory. */
1386	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1387
1388	return rc;
1389	}
1390
1391
1392	/**
1393	* Initializes the per-VCPU PGM.
1394	*
1395	* @returns VBox status code.
1396	* @param pVM The VM to operate on.
1397	*/
1398	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1399	{
1400	LogFlow(("PGMR3InitCPU\n"));
1401	return VINF_SUCCESS;
1402	}
1403
1404
1405	/**
1406	* Init paging.
1407	*
1408	* Since we need to check what mode the host is operating in before we can choose
1409	* the right paging functions for the host we have to delay this until R0 has
1410	* been initialized.
1411	*
1412	* @returns VBox status code.
1413	* @param pVM VM handle.
1414	*/
1415	static int pgmR3InitPaging(PVM pVM)
1416	{
1417	/*
1418	* Force a recalculation of modes and switcher so everyone gets notified.
1419	*/
1420	for (unsigned i=0;i<pVM->cCPUs;i++)
1421	{
1422	PVMCPU pVCpu = &pVM->aCpus[i];
1423
1424	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1425	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1426	}
1427
1428	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1429
1430	/*
1431	* Allocate static mapping space for whatever the cr3 register
1432	* points to and in the case of PAE mode to the 4 PDs.
1433	*/
1434	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1435	if (RT_FAILURE(rc))
1436	{
1437	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1438	return rc;
1439	}
1440	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1441
1442	/*
1443	* Allocate pages for the three possible intermediate contexts
1444	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1445	* for the sake of simplicity. The AMD64 uses the PAE for the
1446	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1447	*
1448	* We assume that two page tables will be enought for the core code
1449	* mappings (HC virtual and identity).
1450	*/
1451	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1452	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1453	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1454	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1455	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1456	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1457	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1458	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1459	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1460	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1463
1464	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1465	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1466	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1467	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1468	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1469	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1470
1471	/*
1472	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1473	*/
1474	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1475	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1476	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1477
1478	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1479	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1480
1481	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1482	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1483	{
1484	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1485	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1486	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1487	}
1488
1489	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1490	{
1491	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1492	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1493	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1494	}
1495
1496	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1497	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1498	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1499	\| HCPhysInterPaePDPT64;
1500
1501	/*
1502	* Initialize paging workers and mode from current host mode
1503	* and the guest running in real mode.
1504	*/
1505	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1506	switch (pVM->pgm.s.enmHostMode)
1507	{
1508	case SUPPAGINGMODE_32_BIT:
1509	case SUPPAGINGMODE_32_BIT_GLOBAL:
1510	case SUPPAGINGMODE_PAE:
1511	case SUPPAGINGMODE_PAE_GLOBAL:
1512	case SUPPAGINGMODE_PAE_NX:
1513	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1514	break;
1515
1516	case SUPPAGINGMODE_AMD64:
1517	case SUPPAGINGMODE_AMD64_GLOBAL:
1518	case SUPPAGINGMODE_AMD64_NX:
1519	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1520	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1521	if (ARCH_BITS != 64)
1522	{
1523	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1524	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1525	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1526	}
1527	#endif
1528	break;
1529	default:
1530	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1531	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1532	}
1533	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1534	if (RT_SUCCESS(rc))
1535	{
1536	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1537	#if HC_ARCH_BITS == 64
1538	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1539	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1540	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1541	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1542	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1543	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1544	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1545	#endif
1546
1547	return VINF_SUCCESS;
1548	}
1549
1550	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1551	return rc;
1552	}
1553
1554
1555	/**
1556	* Init statistics
1557	*/
1558	static void pgmR3InitStats(PVM pVM)
1559	{
1560	PPGM pPGM = &pVM->pgm.s;
1561	int rc;
1562
1563	/* Common - misc variables */
1564	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1565	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1566	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1567	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1568	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1569	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1570	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1571	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1572
1573	#ifdef VBOX_WITH_STATISTICS
1574
1575	# define PGM_REG_COUNTER(a, b, c) \
1576	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1577	AssertRC(rc);
1578
1579	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1580	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1581	AssertRC(rc);
1582
1583	# define PGM_REG_PROFILE(a, b, c) \
1584	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1585	AssertRC(rc);
1586
1587	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1588	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1589	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1590	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1591	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1592	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1593
1594	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1595	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1596	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1597	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1598	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1599	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1600	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1601	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1602
1603	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1604	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1605	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1606	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1607
1608	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1609	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1610	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1611	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1612
1613	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1614	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1615	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1616	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1617	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1618	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1619
1620	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1621	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1622	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1623	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1624
1625	/* GC only: */
1626	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1627	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1628	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1629	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1630
1631	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1632	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1633	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1634	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1635
1636	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1637	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1638	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1639	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1640	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1641	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1642	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1643	# endif
1644
1645	# undef PGM_REG_COUNTER
1646	# undef PGM_REG_PROFILE
1647	#endif
1648
1649	/*
1650	* Note! The layout below matches the member layout exactly!
1651	*/
1652
1653	/*
1654	* Common - stats
1655	*/
1656	for (unsigned i=0;i<pVM->cCPUs;i++)
1657	{
1658	PVMCPU pVCpu = &pVM->aCpus[i];
1659	PPGMCPU pPGM = &pVCpu->pgm.s;
1660
1661	#define PGM_REG_COUNTER(a, b, c) \
1662	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
1663	AssertRC(rc);
1664	#define PGM_REG_PROFILE(a, b, c) \
1665	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
1666	AssertRC(rc);
1667
1668	PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
1669
1670	#ifdef VBOX_WITH_STATISTICS
1671	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPtPD); j++)
1672	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1673	"The number of SyncPT per PD n.", "/PGM/CPU%d/PDSyncPT/%04X", i, j);
1674	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPagePD); j++)
1675	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1676	"The number of SyncPage per PD n.", "/PGM/CPU%d/PDSyncPage/%04X", i, j);
1677
1678	/* R0 only: */
1679	PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1680	PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1681	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1682	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1683	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1684	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1685	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1686	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1687	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1688	PGM_REG_COUNTER(&pPGM->StatR0DynMapPage, "/PGM/CPU%d/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1689	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1690	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1691	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
1692	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1693	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1694	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits0, "/PGM/CPU%d/R0/DynMapPage/Hits0", "Hits at iPage+0");
1695	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits1, "/PGM/CPU%d/R0/DynMapPage/Hits1", "Hits at iPage+1");
1696	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits2, "/PGM/CPU%d/R0/DynMapPage/Hits2", "Hits at iPage+2");
1697	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1698	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1699	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1700	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1701	//PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
1702	PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1703	PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1704	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[0], "/PGM/CPU%d/R0/SetSize000..09", "00-09% filled");
1705	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[1], "/PGM/CPU%d/R0/SetSize010..19", "10-19% filled");
1706	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[2], "/PGM/CPU%d/R0/SetSize020..29", "20-29% filled");
1707	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[3], "/PGM/CPU%d/R0/SetSize030..39", "30-39% filled");
1708	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[4], "/PGM/CPU%d/R0/SetSize040..49", "40-49% filled");
1709	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[5], "/PGM/CPU%d/R0/SetSize050..59", "50-59% filled");
1710	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[6], "/PGM/CPU%d/R0/SetSize060..69", "60-69% filled");
1711	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[7], "/PGM/CPU%d/R0/SetSize070..79", "70-79% filled");
1712	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[8], "/PGM/CPU%d/R0/SetSize080..89", "80-89% filled");
1713	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[9], "/PGM/CPU%d/R0/SetSize090..99", "90-99% filled");
1714	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[10], "/PGM/CPU%d/R0/SetSize100", "100% filled");
1715
1716	/* RZ only: */
1717	PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1718	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1719	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1720	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1721	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1722	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1723	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1724	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1725	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1726	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1727	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1728	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1729	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1730	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1731	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1732	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1733	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1734	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1735	PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1736	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1737	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1738	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1739	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1740	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1741	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1742	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1743	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1744	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1745	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1746	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1747	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1748	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1749	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1750	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1751	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1752	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1753	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1754	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1755	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1756	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1757	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1758	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1759	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1760	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatRZTrap0ePD); j++)
1761	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1762	"The number of traps in page directory n.", "/PGM/CPU%d/RZ/Trap0e/PD/%04X", i, j);
1763
1764	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1765	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1766	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1767	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1768	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1769
1770	/* HC only: */
1771
1772	/* RZ & R3: */
1773	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1774	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1775	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1776	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1777	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1778	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1779	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1780	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1781	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1782	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1783	PGM_REG_PROFILE(&pPGM->StatRZSyncPT, "/PGM/CPU%d/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1784	PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1785	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4K, "/PGM/CPU%d/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1786	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4M, "/PGM/CPU%d/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1787	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1788	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1789	PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1790	PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1791	PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1792	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1793	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1794	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1795	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageStale, "/PGM/CPU%d/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1796	PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1797	PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1798	PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1799	PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1800	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1801	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1802	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1803	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1804	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1805	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1806	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1807	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1808	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1809	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1810	PGM_REG_PROFILE(&pPGM->StatRZPrefetch, "/PGM/CPU%d/RZ/Prefetch", "PGMPrefetchPage profiling.");
1811	PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1812	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1813	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1814	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1815	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1816	PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1817
1818	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1819	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1820	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1821	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1822	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1823	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1824	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1825	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1826	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1827	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1828	PGM_REG_PROFILE(&pPGM->StatR3SyncPT, "/PGM/CPU%d/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1829	PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1830	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4K, "/PGM/CPU%d/R3/SyncPT/4K", "Nr of 4K PT syncs");
1831	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4M, "/PGM/CPU%d/R3/SyncPT/4M", "Nr of 4M PT syncs");
1832	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1833	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1834	PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1835	PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1836	PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1837	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1838	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1839	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1840	PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1841	PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1842	PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1843	PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1844	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1845	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1846	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1847	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1848	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1849	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1850	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1851	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1852	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1853	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1854	PGM_REG_PROFILE(&pPGM->StatR3Prefetch, "/PGM/CPU%d/R3/Prefetch", "PGMPrefetchPage profiling.");
1855	PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1856	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1857	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1858	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1859	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1860	PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1861	#endif /* VBOX_WITH_STATISTICS */
1862
1863	#undef PGM_REG_PROFILE
1864	#undef PGM_REG_COUNTER
1865
1866	}
1867	}
1868
1869
1870	/**
1871	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1872	*
1873	* The dynamic mapping area will also be allocated and initialized at this
1874	* time. We could allocate it during PGMR3Init of course, but the mapping
1875	* wouldn't be allocated at that time preventing us from setting up the
1876	* page table entries with the dummy page.
1877	*
1878	* @returns VBox status code.
1879	* @param pVM VM handle.
1880	*/
1881	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1882	{
1883	RTGCPTR GCPtr;
1884	int rc;
1885
1886	/*
1887	* Reserve space for the dynamic mappings.
1888	*/
1889	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1890	if (RT_SUCCESS(rc))
1891	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1892
1893	if ( RT_SUCCESS(rc)
1894	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1895	{
1896	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1897	if (RT_SUCCESS(rc))
1898	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1899	}
1900	if (RT_SUCCESS(rc))
1901	{
1902	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1903	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1904	}
1905	return rc;
1906	}
1907
1908
1909	/**
1910	* Ring-3 init finalizing.
1911	*
1912	* @returns VBox status code.
1913	* @param pVM The VM handle.
1914	*/
1915	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1916	{
1917	int rc;
1918
1919	/*
1920	* Reserve space for the dynamic mappings.
1921	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1922	*/
1923	/* get the pointer to the page table entries. */
1924	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1925	AssertRelease(pMapping);
1926	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1927	const unsigned iPT = off >> X86_PD_SHIFT;
1928	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1929	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1930	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1931
1932	/* init cache */
1933	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1934	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1935	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1936
1937	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1938	{
1939	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1940	AssertRCReturn(rc, rc);
1941	}
1942
1943	/*
1944	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1945	* Intel only goes up to 36 bits, so we stick to 36 as well.
1946	*/
1947	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1948	uint32_t u32Dummy, u32Features;
1949	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1950
1951	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1952	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1953	else
1954	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1955
1956	/*
1957	* Allocate memory if we're supposed to do that.
1958	*/
1959	if (pVM->pgm.s.fRamPreAlloc)
1960	rc = pgmR3PhysRamPreAllocate(pVM);
1961
1962	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1963	return rc;
1964	}
1965
1966
1967	/**
1968	* Applies relocations to data and code managed by this component.
1969	*
1970	* This function will be called at init and whenever the VMM need to relocate it
1971	* self inside the GC.
1972	*
1973	* @param pVM The VM.
1974	* @param offDelta Relocation delta relative to old location.
1975	*/
1976	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1977	{
1978	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
1979
1980	/*
1981	* Paging stuff.
1982	*/
1983	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1984
1985	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1986
1987	/* Shadow, guest and both mode switch & relocation for each VCPU. */
1988	for (unsigned i=0;i<pVM->cCPUs;i++)
1989	{
1990	PVMCPU pVCpu = &pVM->aCpus[i];
1991
1992	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
1993
1994	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
1995	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
1996	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
1997	}
1998
1999	/*
2000	* Trees.
2001	*/
2002	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2003
2004	/*
2005	* Ram ranges.
2006	*/
2007	if (pVM->pgm.s.pRamRangesR3)
2008	{
2009	/* Update the pSelfRC pointers and relink them. */
2010	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2011	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2012	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2013	pgmR3PhysRelinkRamRanges(pVM);
2014	}
2015
2016	/*
2017	* Update the two page directories with all page table mappings.
2018	* (One or more of them have changed, that's why we're here.)
2019	*/
2020	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2021	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2022	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2023
2024	/* Relocate GC addresses of Page Tables. */
2025	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2026	{
2027	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2028	{
2029	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2030	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2031	}
2032	}
2033
2034	/*
2035	* Dynamic page mapping area.
2036	*/
2037	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2038	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2039	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2040
2041	/*
2042	* The Zero page.
2043	*/
2044	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2045	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2046	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2047	#else
2048	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2049	#endif
2050
2051	/*
2052	* Physical and virtual handlers.
2053	*/
2054	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2055	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2056	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2057
2058	/*
2059	* The page pool.
2060	*/
2061	pgmR3PoolRelocate(pVM);
2062	}
2063
2064
2065	/**
2066	* Callback function for relocating a physical access handler.
2067	*
2068	* @returns 0 (continue enum)
2069	* @param pNode Pointer to a PGMPHYSHANDLER node.
2070	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2071	* not certain the delta will fit in a void pointer for all possible configs.
2072	*/
2073	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2074	{
2075	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2076	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2077	if (pHandler->pfnHandlerRC)
2078	pHandler->pfnHandlerRC += offDelta;
2079	if (pHandler->pvUserRC >= 0x10000)
2080	pHandler->pvUserRC += offDelta;
2081	return 0;
2082	}
2083
2084
2085	/**
2086	* Callback function for relocating a virtual access handler.
2087	*
2088	* @returns 0 (continue enum)
2089	* @param pNode Pointer to a PGMVIRTHANDLER node.
2090	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2091	* not certain the delta will fit in a void pointer for all possible configs.
2092	*/
2093	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2094	{
2095	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2096	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2097	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2098	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2099	Assert(pHandler->pfnHandlerRC);
2100	pHandler->pfnHandlerRC += offDelta;
2101	return 0;
2102	}
2103
2104
2105	/**
2106	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2107	*
2108	* @returns 0 (continue enum)
2109	* @param pNode Pointer to a PGMVIRTHANDLER node.
2110	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2111	* not certain the delta will fit in a void pointer for all possible configs.
2112	*/
2113	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2114	{
2115	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2116	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2117	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2118	Assert(pHandler->pfnHandlerRC);
2119	pHandler->pfnHandlerRC += offDelta;
2120	return 0;
2121	}
2122
2123
2124	/**
2125	* The VM is being reset.
2126	*
2127	* For the PGM component this means that any PD write monitors
2128	* needs to be removed.
2129	*
2130	* @param pVM VM handle.
2131	*/
2132	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2133	{
2134	int rc;
2135
2136	LogFlow(("PGMR3Reset:\n"));
2137	VM_ASSERT_EMT(pVM);
2138
2139	pgmLock(pVM);
2140
2141	/*
2142	* Unfix any fixed mappings and disable CR3 monitoring.
2143	*/
2144	pVM->pgm.s.fMappingsFixed = false;
2145	pVM->pgm.s.GCPtrMappingFixed = 0;
2146	pVM->pgm.s.cbMappingFixed = 0;
2147
2148	/* Exit the guest paging mode before the pgm pool gets reset.
2149	* Important to clean up the amd64 case.
2150	*/
2151	for (unsigned i=0;i<pVM->cCPUs;i++)
2152	{
2153	PVMCPU pVCpu = &pVM->aCpus[i];
2154
2155	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2156	AssertRC(rc);
2157	}
2158
2159	#ifdef DEBUG
2160	DBGFR3InfoLog(pVM, "mappings", NULL);
2161	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2162	#endif
2163
2164	/*
2165	* Switch mode back to real mode. (before resetting the pgm pool!)
2166	*/
2167	for (unsigned i=0;i<pVM->cCPUs;i++)
2168	{
2169	PVMCPU pVCpu = &pVM->aCpus[i];
2170
2171	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2172	AssertRC(rc);
2173
2174	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2175	}
2176
2177	/*
2178	* Reset the shadow page pool.
2179	*/
2180	pgmR3PoolReset(pVM);
2181
2182	for (unsigned i=0;i<pVM->cCPUs;i++)
2183	{
2184	PVMCPU pVCpu = &pVM->aCpus[i];
2185
2186	/*
2187	* Re-init other members.
2188	*/
2189	pVCpu->pgm.s.fA20Enabled = true;
2190
2191	/*
2192	* Clear the FFs PGM owns.
2193	*/
2194	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2195	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2196	}
2197
2198	/*
2199	* Reset (zero) RAM pages.
2200	*/
2201	rc = pgmR3PhysRamReset(pVM);
2202	if (RT_SUCCESS(rc))
2203	{
2204	/*
2205	* Reset (zero) shadow ROM pages.
2206	*/
2207	rc = pgmR3PhysRomReset(pVM);
2208	}
2209
2210	pgmUnlock(pVM);
2211	//return rc;
2212	AssertReleaseRC(rc);
2213	}
2214
2215
2216	#ifdef VBOX_STRICT
2217	/**
2218	* VM state change callback for clearing fNoMorePhysWrites after
2219	* a snapshot has been created.
2220	*/
2221	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2222	{
2223	if (enmState == VMSTATE_RUNNING)
2224	pVM->pgm.s.fNoMorePhysWrites = false;
2225	}
2226	#endif
2227
2228
2229	/**
2230	* Terminates the PGM.
2231	*
2232	* @returns VBox status code.
2233	* @param pVM Pointer to VM structure.
2234	*/
2235	VMMR3DECL(int) PGMR3Term(PVM pVM)
2236	{
2237	PGMDeregisterStringFormatTypes();
2238	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2239	}
2240
2241
2242	/**
2243	* Terminates the per-VCPU PGM.
2244	*
2245	* Termination means cleaning up and freeing all resources,
2246	* the VM it self is at this point powered off or suspended.
2247	*
2248	* @returns VBox status code.
2249	* @param pVM The VM to operate on.
2250	*/
2251	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2252	{
2253	return 0;
2254	}
2255
2256
2257	/**
2258	* Find the ROM tracking structure for the given page.
2259	*
2260	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
2261	* that it's a ROM page.
2262	* @param pVM The VM handle.
2263	* @param GCPhys The address of the ROM page.
2264	*/
2265	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys)
2266	{
2267	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
2268	pRomRange;
2269	pRomRange = pRomRange->CTX_SUFF(pNext))
2270	{
2271	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
2272	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
2273	return &pRomRange->aPages[off >> PAGE_SHIFT];
2274	}
2275	return NULL;
2276	}
2277
2278
2279	/**
2280	* Save zero indicator + bits for the specified page.
2281	*
2282	* @returns VBox status code, errors are logged/asserted before returning.
2283	* @param pVM The VM handle.
2284	* @param pSSH The saved state handle.
2285	* @param pPage The page to save.
2286	* @param GCPhys The address of the page.
2287	* @param pRam The ram range (for error logging).
2288	*/
2289	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2290	{
2291	int rc;
2292	if (PGM_PAGE_IS_ZERO(pPage))
2293	rc = SSMR3PutU8(pSSM, 0);
2294	else
2295	{
2296	void const *pvPage;
2297	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
2298	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2299
2300	SSMR3PutU8(pSSM, 1);
2301	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
2302	}
2303	return rc;
2304	}
2305
2306
2307	/**
2308	* Save a shadowed ROM page.
2309	*
2310	* Format: Type, protection, and two pages with zero indicators.
2311	*
2312	* @returns VBox status code, errors are logged/asserted before returning.
2313	* @param pVM The VM handle.
2314	* @param pSSH The saved state handle.
2315	* @param pPage The page to save.
2316	* @param GCPhys The address of the page.
2317	* @param pRam The ram range (for error logging).
2318	*/
2319	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2320	{
2321	/* Need to save both pages and the current state. */
2322	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2323	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2324
2325	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
2326	SSMR3PutU8(pSSM, pRomPage->enmProt);
2327
2328	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
2329	if (RT_SUCCESS(rc))
2330	{
2331	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2332	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
2333	}
2334	return rc;
2335	}
2336
2337	/** PGM fields to save/load. */
2338	static const SSMFIELD s_aPGMFields[] =
2339	{
2340	SSMFIELD_ENTRY( PGM, fMappingsFixed),
2341	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
2342	SSMFIELD_ENTRY( PGM, cbMappingFixed),
2343	SSMFIELD_ENTRY_TERM()
2344	};
2345
2346	static const SSMFIELD s_aPGMCpuFields[] =
2347	{
2348	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
2349	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
2350	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
2351	SSMFIELD_ENTRY_TERM()
2352	};
2353
2354	/* For loading old saved states. (pre-smp) */
2355	typedef struct
2356	{
2357	/** If set no conflict checks are required. (boolean) */
2358	bool fMappingsFixed;
2359	/** Size of fixed mapping */
2360	uint32_t cbMappingFixed;
2361	/** Base address (GC) of fixed mapping */
2362	RTGCPTR GCPtrMappingFixed;
2363	/** A20 gate mask.
2364	* Our current approach to A20 emulation is to let REM do it and don't bother
2365	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2366	* But whould need arrise, we'll subject physical addresses to this mask. */
2367	RTGCPHYS GCPhysA20Mask;
2368	/** A20 gate state - boolean! */
2369	bool fA20Enabled;
2370	/** The guest paging mode. */
2371	PGMMODE enmGuestMode;
2372	} PGMOLD;
2373
2374	static const SSMFIELD s_aPGMFields_Old[] =
2375	{
2376	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
2377	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
2378	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
2379	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
2380	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
2381	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
2382	SSMFIELD_ENTRY_TERM()
2383	};
2384
2385
2386	/**
2387	* Execute state save operation.
2388	*
2389	* @returns VBox status code.
2390	* @param pVM VM Handle.
2391	* @param pSSM SSM operation handle.
2392	*/
2393	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2394	{
2395	int rc;
2396	unsigned i;
2397	PPGM pPGM = &pVM->pgm.s;
2398
2399	/*
2400	* Lock PGM and set the no-more-writes indicator.
2401	*/
2402	pgmLock(pVM);
2403	pVM->pgm.s.fNoMorePhysWrites = true;
2404
2405	/*
2406	* Save basic data (required / unaffected by relocation).
2407	*/
2408	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2409
2410	for (i=0;i<pVM->cCPUs;i++)
2411	{
2412	PVMCPU pVCpu = &pVM->aCpus[i];
2413
2414	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
2415	}
2416
2417	/*
2418	* The guest mappings.
2419	*/
2420	i = 0;
2421	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2422	{
2423	SSMR3PutU32( pSSM, i);
2424	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2425	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2426	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2427	}
2428	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2429
2430	/*
2431	* Ram ranges and the memory they describe.
2432	*/
2433	i = 0;
2434	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2435	{
2436	/*
2437	* Save the ram range details.
2438	*/
2439	SSMR3PutU32(pSSM, i);
2440	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2441	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2442	SSMR3PutGCPhys(pSSM, pRam->cb);
2443	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
2444	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
2445
2446	/*
2447	* Iterate the pages, only two special case.
2448	*/
2449	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
2450	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2451	{
2452	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2453	PPGMPAGE pPage = &pRam->aPages[iPage];
2454	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
2455
2456	if (uType == PGMPAGETYPE_ROM_SHADOW)
2457	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2458	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
2459	{
2460	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
2461	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
2462	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
2463	}
2464	else
2465	{
2466	SSMR3PutU8(pSSM, uType);
2467	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
2468	}
2469	if (RT_FAILURE(rc))
2470	break;
2471	}
2472	if (RT_FAILURE(rc))
2473	break;
2474	}
2475
2476	pgmUnlock(pVM);
2477	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2478	}
2479
2480
2481	/**
2482	* Load an ignored page.
2483	*
2484	* @returns VBox status code.
2485	* @param pSSM The saved state handle.
2486	*/
2487	static int pgmR3LoadPageToDevNull(PSSMHANDLE pSSM)
2488	{
2489	uint8_t abPage[PAGE_SIZE];
2490	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2491	}
2492
2493
2494	/**
2495	* Loads a page without any bits in the saved state, i.e. making sure it's
2496	* really zero.
2497	*
2498	* @returns VBox status code.
2499	* @param pVM The VM handle.
2500	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2501	* state).
2502	* @param pPage The guest page tracking structure.
2503	* @param GCPhys The page address.
2504	* @param pRam The ram range (logging).
2505	*/
2506	static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2507	{
2508	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2509	&& uType != PGMPAGETYPE_INVALID)
2510	return VERR_SSM_UNEXPECTED_DATA;
2511
2512	/* I think this should be sufficient. */
2513	if (!PGM_PAGE_IS_ZERO(pPage))
2514	return VERR_SSM_UNEXPECTED_DATA;
2515
2516	NOREF(pVM);
2517	NOREF(GCPhys);
2518	NOREF(pRam);
2519	return VINF_SUCCESS;
2520	}
2521
2522
2523	/**
2524	* Loads a page from the saved state.
2525	*
2526	* @returns VBox status code.
2527	* @param pVM The VM handle.
2528	* @param pSSM The SSM handle.
2529	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2530	* state).
2531	* @param pPage The guest page tracking structure.
2532	* @param GCPhys The page address.
2533	* @param pRam The ram range (logging).
2534	*/
2535	static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2536	{
2537	int rc;
2538
2539	/*
2540	* Match up the type, dealing with MMIO2 aliases (dropped).
2541	*/
2542	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2543	\|\| uType == PGMPAGETYPE_INVALID,
2544	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2545	VERR_SSM_UNEXPECTED_DATA);
2546
2547	/*
2548	* Load the page.
2549	*/
2550	void *pvPage;
2551	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2552	if (RT_SUCCESS(rc))
2553	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2554
2555	return rc;
2556	}
2557
2558
2559	/**
2560	* Loads a page (counter part to pgmR3SavePage).
2561	*
2562	* @returns VBox status code, fully bitched errors.
2563	* @param pVM The VM handle.
2564	* @param pSSM The SSM handle.
2565	* @param uType The page type.
2566	* @param pPage The page.
2567	* @param GCPhys The page address.
2568	* @param pRam The RAM range (for error messages).
2569	*/
2570	static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2571	{
2572	uint8_t uState;
2573	int rc = SSMR3GetU8(pSSM, &uState);
2574	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2575	if (uState == 0 /* zero */)
2576	rc = pgmR3LoadPageZero(pVM, uType, pPage, GCPhys, pRam);
2577	else if (uState == 1)
2578	rc = pgmR3LoadPageBits(pVM, pSSM, uType, pPage, GCPhys, pRam);
2579	else
2580	rc = VERR_INTERNAL_ERROR;
2581	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2582	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2583	rc);
2584	return VINF_SUCCESS;
2585	}
2586
2587
2588	/**
2589	* Loads a shadowed ROM page.
2590	*
2591	* @returns VBox status code, errors are fully bitched.
2592	* @param pVM The VM handle.
2593	* @param pSSM The saved state handle.
2594	* @param pPage The page.
2595	* @param GCPhys The page address.
2596	* @param pRam The RAM range (for error messages).
2597	*/
2598	static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2599	{
2600	/*
2601	* Load and set the protection first, then load the two pages, the first
2602	* one is the active the other is the passive.
2603	*/
2604	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2605	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2606
2607	uint8_t uProt;
2608	int rc = SSMR3GetU8(pSSM, &uProt);
2609	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2610	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2611	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2612	&& enmProt < PGMROMPROT_END,
2613	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2614	VERR_SSM_UNEXPECTED_DATA);
2615
2616	if (pRomPage->enmProt != enmProt)
2617	{
2618	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2619	AssertLogRelRCReturn(rc, rc);
2620	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2621	}
2622
2623	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2624	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2625	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2626	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2627
2628	rc = pgmR3LoadPage(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2629	if (RT_SUCCESS(rc))
2630	{
2631	pPageActive = pPage;
2632	rc = pgmR3LoadPage(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2633	}
2634	return rc;
2635	}
2636
2637
2638	/**
2639	* Worker for pgmR3Load.
2640	*
2641	* @returns VBox status code.
2642	*
2643	* @param pVM The VM handle.
2644	* @param pSSM The SSM handle.
2645	* @param u32Version The saved state version.
2646	*/
2647	static int pgmR3LoadLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2648	{
2649	int rc;
2650	PPGM pPGM = &pVM->pgm.s;
2651	uint32_t u32Sep;
2652
2653	/*
2654	* Load basic data (required / unaffected by relocation).
2655	*/
2656	if (u32Version >= PGM_SAVED_STATE_VERSION)
2657	{
2658	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2659	AssertLogRelRCReturn(rc, rc);
2660
2661	for (unsigned i=0;i<pVM->cCPUs;i++)
2662	{
2663	PVMCPU pVCpu = &pVM->aCpus[i];
2664
2665	rc = SSMR3GetStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
2666	AssertLogRelRCReturn(rc, rc);
2667	}
2668	}
2669	else
2670	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2671	{
2672	PGMOLD pgmOld;
2673
2674	AssertRelease(pVM->cCPUs == 1);
2675
2676	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2677	AssertLogRelRCReturn(rc, rc);
2678
2679	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2680	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2681	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2682
2683	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2684	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2685	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2686	}
2687	else
2688	{
2689	AssertRelease(pVM->cCPUs == 1);
2690
2691	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2692	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2693	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2694
2695	uint32_t cbRamSizeIgnored;
2696	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2697	if (RT_FAILURE(rc))
2698	return rc;
2699	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2700
2701	uint32_t u32 = 0;
2702	SSMR3GetUInt(pSSM, &u32);
2703	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2704	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2705	RTUINT uGuestMode;
2706	SSMR3GetUInt(pSSM, &uGuestMode);
2707	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2708
2709	/* check separator. */
2710	SSMR3GetU32(pSSM, &u32Sep);
2711	if (RT_FAILURE(rc))
2712	return rc;
2713	if (u32Sep != (uint32_t)~0)
2714	{
2715	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2716	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2717	}
2718	}
2719
2720	/*
2721	* The guest mappings.
2722	*/
2723	uint32_t i = 0;
2724	for (;; i++)
2725	{
2726	/* Check the seqence number / separator. */
2727	rc = SSMR3GetU32(pSSM, &u32Sep);
2728	if (RT_FAILURE(rc))
2729	return rc;
2730	if (u32Sep == ~0U)
2731	break;
2732	if (u32Sep != i)
2733	{
2734	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2735	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2736	}
2737
2738	/* get the mapping details. */
2739	char szDesc[256];
2740	szDesc[0] = '\0';
2741	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2742	if (RT_FAILURE(rc))
2743	return rc;
2744	RTGCPTR GCPtr;
2745	SSMR3GetGCPtr(pSSM, &GCPtr);
2746	RTGCPTR cPTs;
2747	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2748	if (RT_FAILURE(rc))
2749	return rc;
2750
2751	/* find matching range. */
2752	PPGMMAPPING pMapping;
2753	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2754	if ( pMapping->cPTs == cPTs
2755	&& !strcmp(pMapping->pszDesc, szDesc))
2756	break;
2757	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2758	cPTs, szDesc, GCPtr),
2759	VERR_SSM_LOAD_CONFIG_MISMATCH);
2760
2761	/* relocate it. */
2762	if (pMapping->GCPtr != GCPtr)
2763	{
2764	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2765	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2766	}
2767	else
2768	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2769	}
2770
2771	/*
2772	* Ram range flags and bits.
2773	*/
2774	i = 0;
2775	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2776	{
2777	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2778
2779	/* Check the seqence number / separator. */
2780	rc = SSMR3GetU32(pSSM, &u32Sep);
2781	if (RT_FAILURE(rc))
2782	return rc;
2783	if (u32Sep == ~0U)
2784	break;
2785	if (u32Sep != i)
2786	{
2787	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2788	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2789	}
2790
2791	/* Get the range details. */
2792	RTGCPHYS GCPhys;
2793	SSMR3GetGCPhys(pSSM, &GCPhys);
2794	RTGCPHYS GCPhysLast;
2795	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2796	RTGCPHYS cb;
2797	SSMR3GetGCPhys(pSSM, &cb);
2798	uint8_t fHaveBits;
2799	rc = SSMR3GetU8(pSSM, &fHaveBits);
2800	if (RT_FAILURE(rc))
2801	return rc;
2802	if (fHaveBits & ~1)
2803	{
2804	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2805	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2806	}
2807	size_t cchDesc = 0;
2808	char szDesc[256];
2809	szDesc[0] = '\0';
2810	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2811	{
2812	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2813	if (RT_FAILURE(rc))
2814	return rc;
2815	/* Since we've modified the description strings in r45878, only compare
2816	them if the saved state is more recent. */
2817	if (u32Version != PGM_SAVED_STATE_VERSION_RR_DESC)
2818	cchDesc = strlen(szDesc);
2819	}
2820
2821	/*
2822	* Match it up with the current range.
2823	*
2824	* Note there is a hack for dealing with the high BIOS mapping
2825	* in the old saved state format, this means we might not have
2826	* a 1:1 match on success.
2827	*/
2828	if ( ( GCPhys != pRam->GCPhys
2829	\|\| GCPhysLast != pRam->GCPhysLast
2830	\|\| cb != pRam->cb
2831	\|\| ( cchDesc
2832	&& strcmp(szDesc, pRam->pszDesc)) )
2833	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2834	&& ( u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2835	\|\| GCPhys != UINT32_C(0xfff80000)
2836	\|\| GCPhysLast != UINT32_C(0xffffffff)
2837	\|\| pRam->GCPhysLast != GCPhysLast
2838	\|\| pRam->GCPhys < GCPhys
2839	\|\| !fHaveBits)
2840	)
2841	{
2842	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2843	"State : %RGp-%RGp %RGp bytes %s %s\n",
2844	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2845	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2846	/*
2847	* If we're loading a state for debugging purpose, don't make a fuss if
2848	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2849	*/
2850	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2851	\|\| GCPhys < 8 * _1M)
2852	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2853
2854	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2855	continue;
2856	}
2857
2858	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2859	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2860	{
2861	/*
2862	* Load the pages one by one.
2863	*/
2864	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2865	{
2866	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2867	PPGMPAGE pPage = &pRam->aPages[iPage];
2868	uint8_t uType;
2869	rc = SSMR3GetU8(pSSM, &uType);
2870	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2871	if (uType == PGMPAGETYPE_ROM_SHADOW)
2872	rc = pgmR3LoadShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2873	else
2874	rc = pgmR3LoadPage(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2875	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2876	}
2877	}
2878	else
2879	{
2880	/*
2881	* Old format.
2882	*/
2883	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2884
2885	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2886	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2887	uint32_t fFlags = 0;
2888	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2889	{
2890	uint16_t u16Flags;
2891	rc = SSMR3GetU16(pSSM, &u16Flags);
2892	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2893	fFlags \|= u16Flags;
2894	}
2895
2896	/* Load the bits */
2897	if ( !fHaveBits
2898	&& GCPhysLast < UINT32_C(0xe0000000))
2899	{
2900	/*
2901	* Dynamic chunks.
2902	*/
2903	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2904	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2905	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2906	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2907
2908	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2909	{
2910	uint8_t fPresent;
2911	rc = SSMR3GetU8(pSSM, &fPresent);
2912	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2913	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2914	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2915	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2916
2917	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2918	{
2919	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2920	PPGMPAGE pPage = &pRam->aPages[iPage];
2921	if (fPresent)
2922	{
2923	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2924	rc = pgmR3LoadPageToDevNull(pSSM);
2925	else
2926	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2927	}
2928	else
2929	rc = pgmR3LoadPageZero(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2930	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2931	}
2932	}
2933	}
2934	else if (pRam->pvR3)
2935	{
2936	/*
2937	* MMIO2.
2938	*/
2939	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2940	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2941	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2942	AssertLogRelMsgReturn(pRam->pvR3,
2943	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2944	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2945
2946	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2947	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2948	}
2949	else if (GCPhysLast < UINT32_C(0xfff80000))
2950	{
2951	/*
2952	* PCI MMIO, no pages saved.
2953	*/
2954	}
2955	else
2956	{
2957	/*
2958	* Load the 0xfff80000..0xffffffff BIOS range.
2959	* It starts with X reserved pages that we have to skip over since
2960	* the RAMRANGE create by the new code won't include those.
2961	*/
2962	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2963	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2964	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2965	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2966	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2967	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2968	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2969
2970	/* Skip wasted reserved pages before the ROM. */
2971	while (GCPhys < pRam->GCPhys)
2972	{
2973	rc = pgmR3LoadPageToDevNull(pSSM);
2974	GCPhys += PAGE_SIZE;
2975	}
2976
2977	/* Load the bios pages. */
2978	cPages = pRam->cb >> PAGE_SHIFT;
2979	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2980	{
2981	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2982	PPGMPAGE pPage = &pRam->aPages[iPage];
2983
2984	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2985	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2986	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2987	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2988	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2989	}
2990	}
2991	}
2992	}
2993
2994	return rc;
2995	}
2996
2997
2998	/**
2999	* Execute state load operation.
3000	*
3001	* @returns VBox status code.
3002	* @param pVM VM Handle.
3003	* @param pSSM SSM operation handle.
3004	* @param u32Version Data layout version.
3005	*/
3006	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
3007	{
3008	int rc;
3009	PPGM pPGM = &pVM->pgm.s;
3010
3011	/*
3012	* Validate version.
3013	*/
3014	if ( u32Version != PGM_SAVED_STATE_VERSION
3015	&& u32Version != PGM_SAVED_STATE_VERSION_2_2_2
3016	&& u32Version != PGM_SAVED_STATE_VERSION_RR_DESC
3017	&& u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3018	{
3019	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
3020	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3021	}
3022
3023	/*
3024	* Call the reset function to make sure all the memory is cleared.
3025	*/
3026	PGMR3Reset(pVM);
3027
3028	/*
3029	* Do the loading while owning the lock because a bunch of the functions
3030	* we're using requires this.
3031	*/
3032	pgmLock(pVM);
3033	rc = pgmR3LoadLocked(pVM, pSSM, u32Version);
3034	pgmUnlock(pVM);
3035	if (RT_SUCCESS(rc))
3036	{
3037	/*
3038	* We require a full resync now.
3039	*/
3040	for (unsigned i=0;i<pVM->cCPUs;i++)
3041	{
3042	PVMCPU pVCpu = &pVM->aCpus[i];
3043	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3044	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3045
3046	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3047	}
3048
3049	pgmR3HandlerPhysicalUpdateAll(pVM);
3050
3051	for (unsigned i=0;i<pVM->cCPUs;i++)
3052	{
3053	PVMCPU pVCpu = &pVM->aCpus[i];
3054
3055	/*
3056	* Change the paging mode.
3057	*/
3058	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3059
3060	/* Restore pVM->pgm.s.GCPhysCR3. */
3061	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3062	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3063	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3064	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3065	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3066	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3067	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3068	else
3069	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3070	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3071	}
3072	}
3073
3074	return rc;
3075	}
3076
3077
3078	/**
3079	* Show paging mode.
3080	*
3081	* @param pVM VM Handle.
3082	* @param pHlp The info helpers.
3083	* @param pszArgs "all" (default), "guest", "shadow" or "host".
3084	*/
3085	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3086	{
3087	/* digest argument. */
3088	bool fGuest, fShadow, fHost;
3089	if (pszArgs)
3090	pszArgs = RTStrStripL(pszArgs);
3091	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
3092	fShadow = fHost = fGuest = true;
3093	else
3094	{
3095	fShadow = fHost = fGuest = false;
3096	if (strstr(pszArgs, "guest"))
3097	fGuest = true;
3098	if (strstr(pszArgs, "shadow"))
3099	fShadow = true;
3100	if (strstr(pszArgs, "host"))
3101	fHost = true;
3102	}
3103
3104	/** @todo SMP support! */
3105	/* print info. */
3106	if (fGuest)
3107	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
3108	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
3109	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
3110	if (fShadow)
3111	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
3112	if (fHost)
3113	{
3114	const char *psz;
3115	switch (pVM->pgm.s.enmHostMode)
3116	{
3117	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
3118	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
3119	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
3120	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
3121	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
3122	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
3123	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
3124	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
3125	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
3126	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
3127	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
3128	default: psz = "unknown"; break;
3129	}
3130	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
3131	}
3132	}
3133
3134
3135	/**
3136	* Dump registered MMIO ranges to the log.
3137	*
3138	* @param pVM VM Handle.
3139	* @param pHlp The info helpers.
3140	* @param pszArgs Arguments, ignored.
3141	*/
3142	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3143	{
3144	NOREF(pszArgs);
3145	pHlp->pfnPrintf(pHlp,
3146	"RAM ranges (pVM=%p)\n"
3147	"%.s %.s\n",
3148	pVM,
3149	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
3150	sizeof(RTHCPTR) * 2, "pvHC ");
3151
3152	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
3153	pHlp->pfnPrintf(pHlp,
3154	"%RGp-%RGp %RHv %s\n",
3155	pCur->GCPhys,
3156	pCur->GCPhysLast,
3157	pCur->pvR3,
3158	pCur->pszDesc);
3159	}
3160
3161	/**
3162	* Dump the page directory to the log.
3163	*
3164	* @param pVM VM Handle.
3165	* @param pHlp The info helpers.
3166	* @param pszArgs Arguments, ignored.
3167	*/
3168	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3169	{
3170	/** @todo SMP support!! */
3171	PVMCPU pVCpu = &pVM->aCpus[0];
3172
3173	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
3174	/* Big pages supported? */
3175	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3176
3177	/* Global pages supported? */
3178	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
3179
3180	NOREF(pszArgs);
3181
3182	/*
3183	* Get page directory addresses.
3184	*/
3185	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3186	Assert(pPDSrc);
3187	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3188
3189	/*
3190	* Iterate the page directory.
3191	*/
3192	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3193	{
3194	X86PDE PdeSrc = pPDSrc->a[iPD];
3195	if (PdeSrc.n.u1Present)
3196	{
3197	if (PdeSrc.b.u1Size && fPSE)
3198	pHlp->pfnPrintf(pHlp,
3199	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3200	iPD,
3201	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
3202	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3203	else
3204	pHlp->pfnPrintf(pHlp,
3205	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3206	iPD,
3207	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3208	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3209	}
3210	}
3211	}
3212
3213
3214	/**
3215	* Service a VMMCALLRING3_PGM_LOCK call.
3216	*
3217	* @returns VBox status code.
3218	* @param pVM The VM handle.
3219	*/
3220	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3221	{
3222	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
3223	AssertRC(rc);
3224	return rc;
3225	}
3226
3227
3228	/**
3229	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3230	*
3231	* @returns PGM_TYPE_*.
3232	* @param pgmMode The mode value to convert.
3233	*/
3234	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3235	{
3236	switch (pgmMode)
3237	{
3238	case PGMMODE_REAL: return PGM_TYPE_REAL;
3239	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3240	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3241	case PGMMODE_PAE:
3242	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3243	case PGMMODE_AMD64:
3244	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3245	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
3246	case PGMMODE_EPT: return PGM_TYPE_EPT;
3247	default:
3248	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3249	}
3250	}
3251
3252
3253	/**
3254	* Gets the index into the paging mode data array of a SHW+GST mode.
3255	*
3256	* @returns PGM::paPagingData index.
3257	* @param uShwType The shadow paging mode type.
3258	* @param uGstType The guest paging mode type.
3259	*/
3260	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3261	{
3262	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3263	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3264	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3265	+ (uGstType - PGM_TYPE_REAL);
3266	}
3267
3268
3269	/**
3270	* Gets the index into the paging mode data array of a SHW+GST mode.
3271	*
3272	* @returns PGM::paPagingData index.
3273	* @param enmShw The shadow paging mode.
3274	* @param enmGst The guest paging mode.
3275	*/
3276	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3277	{
3278	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3279	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3280	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3281	}
3282
3283
3284	/**
3285	* Calculates the max data index.
3286	* @returns The number of entries in the paging data array.
3287	*/
3288	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3289	{
3290	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3291	}
3292
3293
3294	/**
3295	* Initializes the paging mode data kept in PGM::paModeData.
3296	*
3297	* @param pVM The VM handle.
3298	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
3299	* This is used early in the init process to avoid trouble with PDM
3300	* not being initialized yet.
3301	*/
3302	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
3303	{
3304	PPGMMODEDATA pModeData;
3305	int rc;
3306
3307	/*
3308	* Allocate the array on the first call.
3309	*/
3310	if (!pVM->pgm.s.paModeData)
3311	{
3312	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
3313	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
3314	}
3315
3316	/*
3317	* Initialize the array entries.
3318	*/
3319	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
3320	pModeData->uShwType = PGM_TYPE_32BIT;
3321	pModeData->uGstType = PGM_TYPE_REAL;
3322	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3323	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3324	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3325
3326	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
3327	pModeData->uShwType = PGM_TYPE_32BIT;
3328	pModeData->uGstType = PGM_TYPE_PROT;
3329	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3330	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3331	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3332
3333	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
3334	pModeData->uShwType = PGM_TYPE_32BIT;
3335	pModeData->uGstType = PGM_TYPE_32BIT;
3336	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3337	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3338	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3339
3340	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
3341	pModeData->uShwType = PGM_TYPE_PAE;
3342	pModeData->uGstType = PGM_TYPE_REAL;
3343	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3344	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3345	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3346
3347	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
3348	pModeData->uShwType = PGM_TYPE_PAE;
3349	pModeData->uGstType = PGM_TYPE_PROT;
3350	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3351	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3352	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3353
3354	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
3355	pModeData->uShwType = PGM_TYPE_PAE;
3356	pModeData->uGstType = PGM_TYPE_32BIT;
3357	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3358	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3359	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3360
3361	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
3362	pModeData->uShwType = PGM_TYPE_PAE;
3363	pModeData->uGstType = PGM_TYPE_PAE;
3364	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3365	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3366	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3367
3368	#ifdef VBOX_WITH_64_BITS_GUESTS
3369	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
3370	pModeData->uShwType = PGM_TYPE_AMD64;
3371	pModeData->uGstType = PGM_TYPE_AMD64;
3372	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3373	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3374	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3375	#endif
3376
3377	/* The nested paging mode. */
3378	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3379	pModeData->uShwType = PGM_TYPE_NESTED;
3380	pModeData->uGstType = PGM_TYPE_REAL;
3381	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3382	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3383
3384	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3385	pModeData->uShwType = PGM_TYPE_NESTED;
3386	pModeData->uGstType = PGM_TYPE_PROT;
3387	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3388	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3389
3390	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3391	pModeData->uShwType = PGM_TYPE_NESTED;
3392	pModeData->uGstType = PGM_TYPE_32BIT;
3393	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3394	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3395
3396	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3397	pModeData->uShwType = PGM_TYPE_NESTED;
3398	pModeData->uGstType = PGM_TYPE_PAE;
3399	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3400	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3401
3402	#ifdef VBOX_WITH_64_BITS_GUESTS
3403	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3404	pModeData->uShwType = PGM_TYPE_NESTED;
3405	pModeData->uGstType = PGM_TYPE_AMD64;
3406	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3407	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3408	#endif
3409
3410	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3411	switch (pVM->pgm.s.enmHostMode)
3412	{
3413	#if HC_ARCH_BITS == 32
3414	case SUPPAGINGMODE_32_BIT:
3415	case SUPPAGINGMODE_32_BIT_GLOBAL:
3416	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3417	{
3418	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3419	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3420	}
3421	# ifdef VBOX_WITH_64_BITS_GUESTS
3422	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3423	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3424	# endif
3425	break;
3426
3427	case SUPPAGINGMODE_PAE:
3428	case SUPPAGINGMODE_PAE_NX:
3429	case SUPPAGINGMODE_PAE_GLOBAL:
3430	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3431	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3432	{
3433	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3434	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3435	}
3436	# ifdef VBOX_WITH_64_BITS_GUESTS
3437	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3438	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3439	# endif
3440	break;
3441	#endif /* HC_ARCH_BITS == 32 */
3442
3443	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3444	case SUPPAGINGMODE_AMD64:
3445	case SUPPAGINGMODE_AMD64_GLOBAL:
3446	case SUPPAGINGMODE_AMD64_NX:
3447	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3448	# ifdef VBOX_WITH_64_BITS_GUESTS
3449	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3450	# else
3451	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3452	# endif
3453	{
3454	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3455	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3456	}
3457	break;
3458	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3459
3460	default:
3461	AssertFailed();
3462	break;
3463	}
3464
3465	/* Extended paging (EPT) / Intel VT-x */
3466	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3467	pModeData->uShwType = PGM_TYPE_EPT;
3468	pModeData->uGstType = PGM_TYPE_REAL;
3469	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3470	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3471	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3472
3473	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3474	pModeData->uShwType = PGM_TYPE_EPT;
3475	pModeData->uGstType = PGM_TYPE_PROT;
3476	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3477	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3478	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3479
3480	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3481	pModeData->uShwType = PGM_TYPE_EPT;
3482	pModeData->uGstType = PGM_TYPE_32BIT;
3483	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3484	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3485	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3486
3487	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3488	pModeData->uShwType = PGM_TYPE_EPT;
3489	pModeData->uGstType = PGM_TYPE_PAE;
3490	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3491	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3492	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3493
3494	#ifdef VBOX_WITH_64_BITS_GUESTS
3495	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3496	pModeData->uShwType = PGM_TYPE_EPT;
3497	pModeData->uGstType = PGM_TYPE_AMD64;
3498	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3499	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3500	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3501	#endif
3502	return VINF_SUCCESS;
3503	}
3504
3505
3506	/**
3507	* Switch to different (or relocated in the relocate case) mode data.
3508	*
3509	* @param pVM The VM handle.
3510	* @param pVCpu The VMCPU to operate on.
3511	* @param enmShw The the shadow paging mode.
3512	* @param enmGst The the guest paging mode.
3513	*/
3514	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3515	{
3516	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3517
3518	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3519	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3520
3521	/* shadow */
3522	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3523	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3524	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3525	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3526	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3527
3528	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3529	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3530
3531	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3532	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3533
3534
3535	/* guest */
3536	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3537	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3538	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3539	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3540	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3541	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3542	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3543	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3544	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3545	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3546	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3547	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3548
3549	/* both */
3550	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3551	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3552	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3553	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3554	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3555	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3556	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3557	#ifdef VBOX_STRICT
3558	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3559	#endif
3560	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3561	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3562
3563	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3564	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3565	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3566	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3567	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3568	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3569	#ifdef VBOX_STRICT
3570	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3571	#endif
3572	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3573	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3574
3575	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3576	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3577	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3578	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3579	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3580	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3581	#ifdef VBOX_STRICT
3582	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3583	#endif
3584	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3585	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3586	}
3587
3588
3589	/**
3590	* Calculates the shadow paging mode.
3591	*
3592	* @returns The shadow paging mode.
3593	* @param pVM VM handle.
3594	* @param enmGuestMode The guest mode.
3595	* @param enmHostMode The host mode.
3596	* @param enmShadowMode The current shadow mode.
3597	* @param penmSwitcher Where to store the switcher to use.
3598	* VMMSWITCHER_INVALID means no change.
3599	*/
3600	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3601	{
3602	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3603	switch (enmGuestMode)
3604	{
3605	/*
3606	* When switching to real or protected mode we don't change
3607	* anything since it's likely that we'll switch back pretty soon.
3608	*
3609	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3610	* and is supposed to determine which shadow paging and switcher to
3611	* use during init.
3612	*/
3613	case PGMMODE_REAL:
3614	case PGMMODE_PROTECTED:
3615	if ( enmShadowMode != PGMMODE_INVALID
3616	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3617	break; /* (no change) */
3618
3619	switch (enmHostMode)
3620	{
3621	case SUPPAGINGMODE_32_BIT:
3622	case SUPPAGINGMODE_32_BIT_GLOBAL:
3623	enmShadowMode = PGMMODE_32_BIT;
3624	enmSwitcher = VMMSWITCHER_32_TO_32;
3625	break;
3626
3627	case SUPPAGINGMODE_PAE:
3628	case SUPPAGINGMODE_PAE_NX:
3629	case SUPPAGINGMODE_PAE_GLOBAL:
3630	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3631	enmShadowMode = PGMMODE_PAE;
3632	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3633	#ifdef DEBUG_bird
3634	if (RTEnvExist("VBOX_32BIT"))
3635	{
3636	enmShadowMode = PGMMODE_32_BIT;
3637	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3638	}
3639	#endif
3640	break;
3641
3642	case SUPPAGINGMODE_AMD64:
3643	case SUPPAGINGMODE_AMD64_GLOBAL:
3644	case SUPPAGINGMODE_AMD64_NX:
3645	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3646	enmShadowMode = PGMMODE_PAE;
3647	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3648	#ifdef DEBUG_bird
3649	if (RTEnvExist("VBOX_32BIT"))
3650	{
3651	enmShadowMode = PGMMODE_32_BIT;
3652	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3653	}
3654	#endif
3655	break;
3656
3657	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3658	}
3659	break;
3660
3661	case PGMMODE_32_BIT:
3662	switch (enmHostMode)
3663	{
3664	case SUPPAGINGMODE_32_BIT:
3665	case SUPPAGINGMODE_32_BIT_GLOBAL:
3666	enmShadowMode = PGMMODE_32_BIT;
3667	enmSwitcher = VMMSWITCHER_32_TO_32;
3668	break;
3669
3670	case SUPPAGINGMODE_PAE:
3671	case SUPPAGINGMODE_PAE_NX:
3672	case SUPPAGINGMODE_PAE_GLOBAL:
3673	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3674	enmShadowMode = PGMMODE_PAE;
3675	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3676	#ifdef DEBUG_bird
3677	if (RTEnvExist("VBOX_32BIT"))
3678	{
3679	enmShadowMode = PGMMODE_32_BIT;
3680	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3681	}
3682	#endif
3683	break;
3684
3685	case SUPPAGINGMODE_AMD64:
3686	case SUPPAGINGMODE_AMD64_GLOBAL:
3687	case SUPPAGINGMODE_AMD64_NX:
3688	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3689	enmShadowMode = PGMMODE_PAE;
3690	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3691	#ifdef DEBUG_bird
3692	if (RTEnvExist("VBOX_32BIT"))
3693	{
3694	enmShadowMode = PGMMODE_32_BIT;
3695	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3696	}
3697	#endif
3698	break;
3699
3700	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3701	}
3702	break;
3703
3704	case PGMMODE_PAE:
3705	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3706	switch (enmHostMode)
3707	{
3708	case SUPPAGINGMODE_32_BIT:
3709	case SUPPAGINGMODE_32_BIT_GLOBAL:
3710	enmShadowMode = PGMMODE_PAE;
3711	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3712	break;
3713
3714	case SUPPAGINGMODE_PAE:
3715	case SUPPAGINGMODE_PAE_NX:
3716	case SUPPAGINGMODE_PAE_GLOBAL:
3717	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3718	enmShadowMode = PGMMODE_PAE;
3719	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3720	break;
3721
3722	case SUPPAGINGMODE_AMD64:
3723	case SUPPAGINGMODE_AMD64_GLOBAL:
3724	case SUPPAGINGMODE_AMD64_NX:
3725	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3726	enmShadowMode = PGMMODE_PAE;
3727	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3728	break;
3729
3730	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3731	}
3732	break;
3733
3734	case PGMMODE_AMD64:
3735	case PGMMODE_AMD64_NX:
3736	switch (enmHostMode)
3737	{
3738	case SUPPAGINGMODE_32_BIT:
3739	case SUPPAGINGMODE_32_BIT_GLOBAL:
3740	enmShadowMode = PGMMODE_AMD64;
3741	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3742	break;
3743
3744	case SUPPAGINGMODE_PAE:
3745	case SUPPAGINGMODE_PAE_NX:
3746	case SUPPAGINGMODE_PAE_GLOBAL:
3747	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3748	enmShadowMode = PGMMODE_AMD64;
3749	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3750	break;
3751
3752	case SUPPAGINGMODE_AMD64:
3753	case SUPPAGINGMODE_AMD64_GLOBAL:
3754	case SUPPAGINGMODE_AMD64_NX:
3755	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3756	enmShadowMode = PGMMODE_AMD64;
3757	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3758	break;
3759
3760	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3761	}
3762	break;
3763
3764
3765	default:
3766	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3767	return PGMMODE_INVALID;
3768	}
3769	/* Override the shadow mode is nested paging is active. */
3770	if (HWACCMIsNestedPagingActive(pVM))
3771	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3772
3773	*penmSwitcher = enmSwitcher;
3774	return enmShadowMode;
3775	}
3776
3777
3778	/**
3779	* Performs the actual mode change.
3780	* This is called by PGMChangeMode and pgmR3InitPaging().
3781	*
3782	* @returns VBox status code. May suspend or power off the VM on error, but this
3783	* will trigger using FFs and not status codes.
3784	*
3785	* @param pVM VM handle.
3786	* @param pVCpu The VMCPU to operate on.
3787	* @param enmGuestMode The new guest mode. This is assumed to be different from
3788	* the current mode.
3789	*/
3790	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3791	{
3792	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3793	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3794
3795	/*
3796	* Calc the shadow mode and switcher.
3797	*/
3798	VMMSWITCHER enmSwitcher;
3799	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3800	if (enmSwitcher != VMMSWITCHER_INVALID)
3801	{
3802	/*
3803	* Select new switcher.
3804	*/
3805	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3806	if (RT_FAILURE(rc))
3807	{
3808	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3809	return rc;
3810	}
3811	}
3812
3813	/*
3814	* Exit old mode(s).
3815	*/
3816	/* shadow */
3817	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3818	{
3819	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3820	if (PGM_SHW_PFN(Exit, pVCpu))
3821	{
3822	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3823	if (RT_FAILURE(rc))
3824	{
3825	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3826	return rc;
3827	}
3828	}
3829
3830	}
3831	else
3832	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3833
3834	/* guest */
3835	if (PGM_GST_PFN(Exit, pVCpu))
3836	{
3837	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3838	if (RT_FAILURE(rc))
3839	{
3840	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3841	return rc;
3842	}
3843	}
3844
3845	/*
3846	* Load new paging mode data.
3847	*/
3848	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3849
3850	/*
3851	* Enter new shadow mode (if changed).
3852	*/
3853	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3854	{
3855	int rc;
3856	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3857	switch (enmShadowMode)
3858	{
3859	case PGMMODE_32_BIT:
3860	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu);
3861	break;
3862	case PGMMODE_PAE:
3863	case PGMMODE_PAE_NX:
3864	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu);
3865	break;
3866	case PGMMODE_AMD64:
3867	case PGMMODE_AMD64_NX:
3868	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu);
3869	break;
3870	case PGMMODE_NESTED:
3871	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu);
3872	break;
3873	case PGMMODE_EPT:
3874	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu);
3875	break;
3876	case PGMMODE_REAL:
3877	case PGMMODE_PROTECTED:
3878	default:
3879	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3880	return VERR_INTERNAL_ERROR;
3881	}
3882	if (RT_FAILURE(rc))
3883	{
3884	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3885	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3886	return rc;
3887	}
3888	}
3889
3890	/*
3891	* Always flag the necessary updates
3892	*/
3893	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3894
3895	/*
3896	* Enter the new guest and shadow+guest modes.
3897	*/
3898	int rc = -1;
3899	int rc2 = -1;
3900	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3901	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3902	switch (enmGuestMode)
3903	{
3904	case PGMMODE_REAL:
3905	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3906	switch (pVCpu->pgm.s.enmShadowMode)
3907	{
3908	case PGMMODE_32_BIT:
3909	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3910	break;
3911	case PGMMODE_PAE:
3912	case PGMMODE_PAE_NX:
3913	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3914	break;
3915	case PGMMODE_NESTED:
3916	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3917	break;
3918	case PGMMODE_EPT:
3919	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3920	break;
3921	case PGMMODE_AMD64:
3922	case PGMMODE_AMD64_NX:
3923	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3924	default: AssertFailed(); break;
3925	}
3926	break;
3927
3928	case PGMMODE_PROTECTED:
3929	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3930	switch (pVCpu->pgm.s.enmShadowMode)
3931	{
3932	case PGMMODE_32_BIT:
3933	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3934	break;
3935	case PGMMODE_PAE:
3936	case PGMMODE_PAE_NX:
3937	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3938	break;
3939	case PGMMODE_NESTED:
3940	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3941	break;
3942	case PGMMODE_EPT:
3943	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3944	break;
3945	case PGMMODE_AMD64:
3946	case PGMMODE_AMD64_NX:
3947	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3948	default: AssertFailed(); break;
3949	}
3950	break;
3951
3952	case PGMMODE_32_BIT:
3953	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3954	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3955	switch (pVCpu->pgm.s.enmShadowMode)
3956	{
3957	case PGMMODE_32_BIT:
3958	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3959	break;
3960	case PGMMODE_PAE:
3961	case PGMMODE_PAE_NX:
3962	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3963	break;
3964	case PGMMODE_NESTED:
3965	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3966	break;
3967	case PGMMODE_EPT:
3968	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3969	break;
3970	case PGMMODE_AMD64:
3971	case PGMMODE_AMD64_NX:
3972	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3973	default: AssertFailed(); break;
3974	}
3975	break;
3976
3977	case PGMMODE_PAE_NX:
3978	case PGMMODE_PAE:
3979	{
3980	uint32_t u32Dummy, u32Features;
3981
3982	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3983	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3984	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3985	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3986
3987	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3988	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3989	switch (pVCpu->pgm.s.enmShadowMode)
3990	{
3991	case PGMMODE_PAE:
3992	case PGMMODE_PAE_NX:
3993	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3994	break;
3995	case PGMMODE_NESTED:
3996	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3997	break;
3998	case PGMMODE_EPT:
3999	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
4000	break;
4001	case PGMMODE_32_BIT:
4002	case PGMMODE_AMD64:
4003	case PGMMODE_AMD64_NX:
4004	AssertMsgFailed(("Should use PAE shadow mode!\n"));
4005	default: AssertFailed(); break;
4006	}
4007	break;
4008	}
4009
4010	#ifdef VBOX_WITH_64_BITS_GUESTS
4011	case PGMMODE_AMD64_NX:
4012	case PGMMODE_AMD64:
4013	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
4014	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
4015	switch (pVCpu->pgm.s.enmShadowMode)
4016	{
4017	case PGMMODE_AMD64:
4018	case PGMMODE_AMD64_NX:
4019	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
4020	break;
4021	case PGMMODE_NESTED:
4022	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
4023	break;
4024	case PGMMODE_EPT:
4025	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
4026	break;
4027	case PGMMODE_32_BIT:
4028	case PGMMODE_PAE:
4029	case PGMMODE_PAE_NX:
4030	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
4031	default: AssertFailed(); break;
4032	}
4033	break;
4034	#endif
4035
4036	default:
4037	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
4038	rc = VERR_NOT_IMPLEMENTED;
4039	break;
4040	}
4041
4042	/* status codes. */
4043	AssertRC(rc);
4044	AssertRC(rc2);
4045	if (RT_SUCCESS(rc))
4046	{
4047	rc = rc2;
4048	if (RT_SUCCESS(rc)) /* no informational status codes. */
4049	rc = VINF_SUCCESS;
4050	}
4051
4052	/* Notify HWACCM as well. */
4053	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
4054	return rc;
4055	}
4056
4057	/**
4058	* Release the pgm lock if owned by the current VCPU
4059	*
4060	* @param pVM The VM to operate on.
4061	*/
4062	VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
4063	{
4064	while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
4065	PDMCritSectLeave(&pVM->pgm.s.CritSect);
4066	}
4067
4068	/**
4069	* Called by pgmPoolFlushAllInt prior to flushing the pool.
4070	*
4071	* @returns VBox status code, fully asserted.
4072	* @param pVM The VM handle.
4073	* @param pVCpu The VMCPU to operate on.
4074	*/
4075	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
4076	{
4077	/* Unmap the old CR3 value before flushing everything. */
4078	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
4079	AssertRC(rc);
4080
4081	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
4082	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
4083	AssertRC(rc);
4084	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
4085	return rc;
4086	}
4087
4088
4089	/**
4090	* Called by pgmPoolFlushAllInt after flushing the pool.
4091	*
4092	* @returns VBox status code, fully asserted.
4093	* @param pVM The VM handle.
4094	* @param pVCpu The VMCPU to operate on.
4095	*/
4096	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
4097	{
4098	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
4099	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
4100	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4101	AssertRCReturn(rc, rc);
4102	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
4103
4104	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
4105	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
4106	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
4107	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
4108	return rc;
4109	}
4110
4111
4112	/**
4113	* Dumps a PAE shadow page table.
4114	*
4115	* @returns VBox status code (VINF_SUCCESS).
4116	* @param pVM The VM handle.
4117	* @param pPT Pointer to the page table.
4118	* @param u64Address The virtual address of the page table starts.
4119	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4120	* @param cMaxDepth The maxium depth.
4121	* @param pHlp Pointer to the output functions.
4122	*/
4123	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4124	{
4125	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4126	{
4127	X86PTEPAE Pte = pPT->a[i];
4128	if (Pte.n.u1Present)
4129	{
4130	pHlp->pfnPrintf(pHlp,
4131	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4132	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
4133	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
4134	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
4135	Pte.n.u1Write ? 'W' : 'R',
4136	Pte.n.u1User ? 'U' : 'S',
4137	Pte.n.u1Accessed ? 'A' : '-',
4138	Pte.n.u1Dirty ? 'D' : '-',
4139	Pte.n.u1Global ? 'G' : '-',
4140	Pte.n.u1WriteThru ? "WT" : "--",
4141	Pte.n.u1CacheDisable? "CD" : "--",
4142	Pte.n.u1PAT ? "AT" : "--",
4143	Pte.n.u1NoExecute ? "NX" : "--",
4144	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4145	Pte.u & RT_BIT(10) ? '1' : '0',
4146	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
4147	Pte.u & X86_PTE_PAE_PG_MASK);
4148	}
4149	}
4150	return VINF_SUCCESS;
4151	}
4152
4153
4154	/**
4155	* Dumps a PAE shadow page directory table.
4156	*
4157	* @returns VBox status code (VINF_SUCCESS).
4158	* @param pVM The VM handle.
4159	* @param HCPhys The physical address of the page directory table.
4160	* @param u64Address The virtual address of the page table starts.
4161	* @param cr4 The CR4, PSE is currently used.
4162	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4163	* @param cMaxDepth The maxium depth.
4164	* @param pHlp Pointer to the output functions.
4165	*/
4166	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4167	{
4168	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
4169	if (!pPD)
4170	{
4171	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
4172	fLongMode ? 16 : 8, u64Address, HCPhys);
4173	return VERR_INVALID_PARAMETER;
4174	}
4175	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
4176
4177	int rc = VINF_SUCCESS;
4178	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4179	{
4180	X86PDEPAE Pde = pPD->a[i];
4181	if (Pde.n.u1Present)
4182	{
4183	if (fBigPagesSupported && Pde.b.u1Size)
4184	pHlp->pfnPrintf(pHlp,
4185	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4186	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
4187	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
4188	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4189	Pde.b.u1Write ? 'W' : 'R',
4190	Pde.b.u1User ? 'U' : 'S',
4191	Pde.b.u1Accessed ? 'A' : '-',
4192	Pde.b.u1Dirty ? 'D' : '-',
4193	Pde.b.u1Global ? 'G' : '-',
4194	Pde.b.u1WriteThru ? "WT" : "--",
4195	Pde.b.u1CacheDisable? "CD" : "--",
4196	Pde.b.u1PAT ? "AT" : "--",
4197	Pde.b.u1NoExecute ? "NX" : "--",
4198	Pde.u & RT_BIT_64(9) ? '1' : '0',
4199	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4200	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4201	Pde.u & X86_PDE_PAE_PG_MASK);
4202	else
4203	{
4204	pHlp->pfnPrintf(pHlp,
4205	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4206	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
4207	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
4208	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4209	Pde.n.u1Write ? 'W' : 'R',
4210	Pde.n.u1User ? 'U' : 'S',
4211	Pde.n.u1Accessed ? 'A' : '-',
4212	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4213	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4214	Pde.n.u1WriteThru ? "WT" : "--",
4215	Pde.n.u1CacheDisable? "CD" : "--",
4216	Pde.n.u1NoExecute ? "NX" : "--",
4217	Pde.u & RT_BIT_64(9) ? '1' : '0',
4218	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4219	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4220	Pde.u & X86_PDE_PAE_PG_MASK);
4221	if (cMaxDepth >= 1)
4222	{
4223	/** @todo what about using the page pool for mapping PTs? */
4224	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
4225	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
4226	PX86PTPAE pPT = NULL;
4227	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4228	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
4229	else
4230	{
4231	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4232	{
4233	uint64_t off = u64AddressPT - pMap->GCPtr;
4234	if (off < pMap->cb)
4235	{
4236	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
4237	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
4238	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
4239	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4240	fLongMode ? 16 : 8, u64AddressPT, iPDE,
4241	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
4242	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
4243	}
4244	}
4245	}
4246	int rc2 = VERR_INVALID_PARAMETER;
4247	if (pPT)
4248	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
4249	else
4250	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
4251	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
4252	if (rc2 < rc && RT_SUCCESS(rc))
4253	rc = rc2;
4254	}
4255	}
4256	}
4257	}
4258	return rc;
4259	}
4260
4261
4262	/**
4263	* Dumps a PAE shadow page directory pointer table.
4264	*
4265	* @returns VBox status code (VINF_SUCCESS).
4266	* @param pVM The VM handle.
4267	* @param HCPhys The physical address of the page directory pointer table.
4268	* @param u64Address The virtual address of the page table starts.
4269	* @param cr4 The CR4, PSE is currently used.
4270	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4271	* @param cMaxDepth The maxium depth.
4272	* @param pHlp Pointer to the output functions.
4273	*/
4274	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4275	{
4276	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
4277	if (!pPDPT)
4278	{
4279	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
4280	fLongMode ? 16 : 8, u64Address, HCPhys);
4281	return VERR_INVALID_PARAMETER;
4282	}
4283
4284	int rc = VINF_SUCCESS;
4285	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
4286	for (unsigned i = 0; i < c; i++)
4287	{
4288	X86PDPE Pdpe = pPDPT->a[i];
4289	if (Pdpe.n.u1Present)
4290	{
4291	if (fLongMode)
4292	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4293	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4294	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4295	Pdpe.lm.u1Write ? 'W' : 'R',
4296	Pdpe.lm.u1User ? 'U' : 'S',
4297	Pdpe.lm.u1Accessed ? 'A' : '-',
4298	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
4299	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
4300	Pdpe.lm.u1WriteThru ? "WT" : "--",
4301	Pdpe.lm.u1CacheDisable? "CD" : "--",
4302	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
4303	Pdpe.lm.u1NoExecute ? "NX" : "--",
4304	Pdpe.u & RT_BIT(9) ? '1' : '0',
4305	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4306	Pdpe.u & RT_BIT(11) ? '1' : '0',
4307	Pdpe.u & X86_PDPE_PG_MASK);
4308	else
4309	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
4310	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
4311	i << X86_PDPT_SHIFT,
4312	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
4313	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
4314	Pdpe.n.u1WriteThru ? "WT" : "--",
4315	Pdpe.n.u1CacheDisable? "CD" : "--",
4316	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
4317	Pdpe.u & RT_BIT(9) ? '1' : '0',
4318	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4319	Pdpe.u & RT_BIT(11) ? '1' : '0',
4320	Pdpe.u & X86_PDPE_PG_MASK);
4321	if (cMaxDepth >= 1)
4322	{
4323	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4324	cr4, fLongMode, cMaxDepth - 1, pHlp);
4325	if (rc2 < rc && RT_SUCCESS(rc))
4326	rc = rc2;
4327	}
4328	}
4329	}
4330	return rc;
4331	}
4332
4333
4334	/**
4335	* Dumps a 32-bit shadow page table.
4336	*
4337	* @returns VBox status code (VINF_SUCCESS).
4338	* @param pVM The VM handle.
4339	* @param HCPhys The physical address of the table.
4340	* @param cr4 The CR4, PSE is currently used.
4341	* @param cMaxDepth The maxium depth.
4342	* @param pHlp Pointer to the output functions.
4343	*/
4344	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4345	{
4346	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
4347	if (!pPML4)
4348	{
4349	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
4350	return VERR_INVALID_PARAMETER;
4351	}
4352
4353	int rc = VINF_SUCCESS;
4354	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
4355	{
4356	X86PML4E Pml4e = pPML4->a[i];
4357	if (Pml4e.n.u1Present)
4358	{
4359	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
4360	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4361	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4362	u64Address,
4363	Pml4e.n.u1Write ? 'W' : 'R',
4364	Pml4e.n.u1User ? 'U' : 'S',
4365	Pml4e.n.u1Accessed ? 'A' : '-',
4366	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
4367	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
4368	Pml4e.n.u1WriteThru ? "WT" : "--",
4369	Pml4e.n.u1CacheDisable? "CD" : "--",
4370	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
4371	Pml4e.n.u1NoExecute ? "NX" : "--",
4372	Pml4e.u & RT_BIT(9) ? '1' : '0',
4373	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4374	Pml4e.u & RT_BIT(11) ? '1' : '0',
4375	Pml4e.u & X86_PML4E_PG_MASK);
4376
4377	if (cMaxDepth >= 1)
4378	{
4379	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
4380	if (rc2 < rc && RT_SUCCESS(rc))
4381	rc = rc2;
4382	}
4383	}
4384	}
4385	return rc;
4386	}
4387
4388
4389	/**
4390	* Dumps a 32-bit shadow page table.
4391	*
4392	* @returns VBox status code (VINF_SUCCESS).
4393	* @param pVM The VM handle.
4394	* @param pPT Pointer to the page table.
4395	* @param u32Address The virtual address this table starts at.
4396	* @param pHlp Pointer to the output functions.
4397	*/
4398	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
4399	{
4400	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4401	{
4402	X86PTE Pte = pPT->a[i];
4403	if (Pte.n.u1Present)
4404	{
4405	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4406	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4407	u32Address + (i << X86_PT_SHIFT),
4408	Pte.n.u1Write ? 'W' : 'R',
4409	Pte.n.u1User ? 'U' : 'S',
4410	Pte.n.u1Accessed ? 'A' : '-',
4411	Pte.n.u1Dirty ? 'D' : '-',
4412	Pte.n.u1Global ? 'G' : '-',
4413	Pte.n.u1WriteThru ? "WT" : "--",
4414	Pte.n.u1CacheDisable? "CD" : "--",
4415	Pte.n.u1PAT ? "AT" : "--",
4416	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4417	Pte.u & RT_BIT(10) ? '1' : '0',
4418	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4419	Pte.u & X86_PDE_PG_MASK);
4420	}
4421	}
4422	return VINF_SUCCESS;
4423	}
4424
4425
4426	/**
4427	* Dumps a 32-bit shadow page directory and page tables.
4428	*
4429	* @returns VBox status code (VINF_SUCCESS).
4430	* @param pVM The VM handle.
4431	* @param cr3 The root of the hierarchy.
4432	* @param cr4 The CR4, PSE is currently used.
4433	* @param cMaxDepth How deep into the hierarchy the dumper should go.
4434	* @param pHlp Pointer to the output functions.
4435	*/
4436	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4437	{
4438	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
4439	if (!pPD)
4440	{
4441	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4442	return VERR_INVALID_PARAMETER;
4443	}
4444
4445	int rc = VINF_SUCCESS;
4446	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4447	{
4448	X86PDE Pde = pPD->a[i];
4449	if (Pde.n.u1Present)
4450	{
4451	const uint32_t u32Address = i << X86_PD_SHIFT;
4452	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4453	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4454	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4455	u32Address,
4456	Pde.b.u1Write ? 'W' : 'R',
4457	Pde.b.u1User ? 'U' : 'S',
4458	Pde.b.u1Accessed ? 'A' : '-',
4459	Pde.b.u1Dirty ? 'D' : '-',
4460	Pde.b.u1Global ? 'G' : '-',
4461	Pde.b.u1WriteThru ? "WT" : "--",
4462	Pde.b.u1CacheDisable? "CD" : "--",
4463	Pde.b.u1PAT ? "AT" : "--",
4464	Pde.u & RT_BIT_64(9) ? '1' : '0',
4465	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4466	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4467	Pde.u & X86_PDE4M_PG_MASK);
4468	else
4469	{
4470	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4471	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4472	u32Address,
4473	Pde.n.u1Write ? 'W' : 'R',
4474	Pde.n.u1User ? 'U' : 'S',
4475	Pde.n.u1Accessed ? 'A' : '-',
4476	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4477	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4478	Pde.n.u1WriteThru ? "WT" : "--",
4479	Pde.n.u1CacheDisable? "CD" : "--",
4480	Pde.u & RT_BIT_64(9) ? '1' : '0',
4481	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4482	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4483	Pde.u & X86_PDE_PG_MASK);
4484	if (cMaxDepth >= 1)
4485	{
4486	/** @todo what about using the page pool for mapping PTs? */
4487	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4488	PX86PT pPT = NULL;
4489	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4490	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4491	else
4492	{
4493	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4494	if (u32Address - pMap->GCPtr < pMap->cb)
4495	{
4496	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4497	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4498	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4499	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4500	pPT = pMap->aPTs[iPDE].pPTR3;
4501	}
4502	}
4503	int rc2 = VERR_INVALID_PARAMETER;
4504	if (pPT)
4505	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4506	else
4507	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4508	if (rc2 < rc && RT_SUCCESS(rc))
4509	rc = rc2;
4510	}
4511	}
4512	}
4513	}
4514
4515	return rc;
4516	}
4517
4518
4519	/**
4520	* Dumps a 32-bit shadow page table.
4521	*
4522	* @returns VBox status code (VINF_SUCCESS).
4523	* @param pVM The VM handle.
4524	* @param pPT Pointer to the page table.
4525	* @param u32Address The virtual address this table starts at.
4526	* @param PhysSearch Address to search for.
4527	*/
4528	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4529	{
4530	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4531	{
4532	X86PTE Pte = pPT->a[i];
4533	if (Pte.n.u1Present)
4534	{
4535	Log(( /P R S A D G WT CD AT NX 4M a m d /
4536	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4537	u32Address + (i << X86_PT_SHIFT),
4538	Pte.n.u1Write ? 'W' : 'R',
4539	Pte.n.u1User ? 'U' : 'S',
4540	Pte.n.u1Accessed ? 'A' : '-',
4541	Pte.n.u1Dirty ? 'D' : '-',
4542	Pte.n.u1Global ? 'G' : '-',
4543	Pte.n.u1WriteThru ? "WT" : "--",
4544	Pte.n.u1CacheDisable? "CD" : "--",
4545	Pte.n.u1PAT ? "AT" : "--",
4546	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4547	Pte.u & RT_BIT(10) ? '1' : '0',
4548	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4549	Pte.u & X86_PDE_PG_MASK));
4550
4551	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4552	{
4553	uint64_t fPageShw = 0;
4554	RTHCPHYS pPhysHC = 0;
4555
4556	/** @todo SMP support!! */
4557	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4558	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4559	}
4560	}
4561	}
4562	return VINF_SUCCESS;
4563	}
4564
4565
4566	/**
4567	* Dumps a 32-bit guest page directory and page tables.
4568	*
4569	* @returns VBox status code (VINF_SUCCESS).
4570	* @param pVM The VM handle.
4571	* @param cr3 The root of the hierarchy.
4572	* @param cr4 The CR4, PSE is currently used.
4573	* @param PhysSearch Address to search for.
4574	*/
4575	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4576	{
4577	bool fLongMode = false;
4578	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4579	PX86PD pPD = 0;
4580
4581	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4582	if (RT_FAILURE(rc) \|\| !pPD)
4583	{
4584	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4585	return VERR_INVALID_PARAMETER;
4586	}
4587
4588	Log(("cr3=%08x cr4=%08x%s\n"
4589	"%-*s P - Present\n"
4590	"%-*s \| R/W - Read (0) / Write (1)\n"
4591	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4592	"%-*s \| \| \| A - Accessed\n"
4593	"%-*s \| \| \| \| D - Dirty\n"
4594	"%-*s \| \| \| \| \| G - Global\n"
4595	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4596	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4597	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4598	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4599	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4600	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4601	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4602	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4603	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4604	- W U - - - -- -- -- -- -- 010 */
4605	, cr3, cr4, fLongMode ? " Long Mode" : "",
4606	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4607	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4608
4609	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4610	{
4611	X86PDE Pde = pPD->a[i];
4612	if (Pde.n.u1Present)
4613	{
4614	const uint32_t u32Address = i << X86_PD_SHIFT;
4615
4616	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4617	Log(( /P R S A D G WT CD AT NX 4M a m d /
4618	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4619	u32Address,
4620	Pde.b.u1Write ? 'W' : 'R',
4621	Pde.b.u1User ? 'U' : 'S',
4622	Pde.b.u1Accessed ? 'A' : '-',
4623	Pde.b.u1Dirty ? 'D' : '-',
4624	Pde.b.u1Global ? 'G' : '-',
4625	Pde.b.u1WriteThru ? "WT" : "--",
4626	Pde.b.u1CacheDisable? "CD" : "--",
4627	Pde.b.u1PAT ? "AT" : "--",
4628	Pde.u & RT_BIT(9) ? '1' : '0',
4629	Pde.u & RT_BIT(10) ? '1' : '0',
4630	Pde.u & RT_BIT(11) ? '1' : '0',
4631	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4632	/** @todo PhysSearch */
4633	else
4634	{
4635	Log(( /P R S A D G WT CD AT NX 4M a m d /
4636	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4637	u32Address,
4638	Pde.n.u1Write ? 'W' : 'R',
4639	Pde.n.u1User ? 'U' : 'S',
4640	Pde.n.u1Accessed ? 'A' : '-',
4641	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4642	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4643	Pde.n.u1WriteThru ? "WT" : "--",
4644	Pde.n.u1CacheDisable? "CD" : "--",
4645	Pde.u & RT_BIT(9) ? '1' : '0',
4646	Pde.u & RT_BIT(10) ? '1' : '0',
4647	Pde.u & RT_BIT(11) ? '1' : '0',
4648	Pde.u & X86_PDE_PG_MASK));
4649	////if (cMaxDepth >= 1)
4650	{
4651	/** @todo what about using the page pool for mapping PTs? */
4652	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4653	PX86PT pPT = NULL;
4654
4655	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4656
4657	int rc2 = VERR_INVALID_PARAMETER;
4658	if (pPT)
4659	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4660	else
4661	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4662	if (rc2 < rc && RT_SUCCESS(rc))
4663	rc = rc2;
4664	}
4665	}
4666	}
4667	}
4668
4669	return rc;
4670	}
4671
4672
4673	/**
4674	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4675	*
4676	* @returns VBox status code (VINF_SUCCESS).
4677	* @param pVM The VM handle.
4678	* @param cr3 The root of the hierarchy.
4679	* @param cr4 The cr4, only PAE and PSE is currently used.
4680	* @param fLongMode Set if long mode, false if not long mode.
4681	* @param cMaxDepth Number of levels to dump.
4682	* @param pHlp Pointer to the output functions.
4683	*/
4684	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4685	{
4686	if (!pHlp)
4687	pHlp = DBGFR3InfoLogHlp();
4688	if (!cMaxDepth)
4689	return VINF_SUCCESS;
4690	const unsigned cch = fLongMode ? 16 : 8;
4691	pHlp->pfnPrintf(pHlp,
4692	"cr3=%08x cr4=%08x%s\n"
4693	"%-*s P - Present\n"
4694	"%-*s \| R/W - Read (0) / Write (1)\n"
4695	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4696	"%-*s \| \| \| A - Accessed\n"
4697	"%-*s \| \| \| \| D - Dirty\n"
4698	"%-*s \| \| \| \| \| G - Global\n"
4699	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4700	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4701	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4702	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4703	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4704	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4705	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4706	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4707	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4708	- W U - - - -- -- -- -- -- 010 */
4709	, cr3, cr4, fLongMode ? " Long Mode" : "",
4710	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4711	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4712	if (cr4 & X86_CR4_PAE)
4713	{
4714	if (fLongMode)
4715	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4716	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4717	}
4718	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4719	}
4720
4721	#ifdef VBOX_WITH_DEBUGGER
4722
4723	/**
4724	* The '.pgmram' command.
4725	*
4726	* @returns VBox status.
4727	* @param pCmd Pointer to the command descriptor (as registered).
4728	* @param pCmdHlp Pointer to command helper functions.
4729	* @param pVM Pointer to the current VM (if any).
4730	* @param paArgs Pointer to (readonly) array of arguments.
4731	* @param cArgs Number of arguments in the array.
4732	*/
4733	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4734	{
4735	/*
4736	* Validate input.
4737	*/
4738	if (!pVM)
4739	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4740	if (!pVM->pgm.s.pRamRangesRC)
4741	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4742
4743	/*
4744	* Dump the ranges.
4745	*/
4746	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4747	PPGMRAMRANGE pRam;
4748	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4749	{
4750	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4751	"%RGp - %RGp %p\n",
4752	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4753	if (RT_FAILURE(rc))
4754	return rc;
4755	}
4756
4757	return VINF_SUCCESS;
4758	}
4759
4760
4761	/**
4762	* The '.pgmmap' command.
4763	*
4764	* @returns VBox status.
4765	* @param pCmd Pointer to the command descriptor (as registered).
4766	* @param pCmdHlp Pointer to command helper functions.
4767	* @param pVM Pointer to the current VM (if any).
4768	* @param paArgs Pointer to (readonly) array of arguments.
4769	* @param cArgs Number of arguments in the array.
4770	*/
4771	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4772	{
4773	/*
4774	* Validate input.
4775	*/
4776	if (!pVM)
4777	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4778	if (!pVM->pgm.s.pMappingsR3)
4779	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4780
4781	/*
4782	* Print message about the fixedness of the mappings.
4783	*/
4784	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4785	if (RT_FAILURE(rc))
4786	return rc;
4787
4788	/*
4789	* Dump the ranges.
4790	*/
4791	PPGMMAPPING pCur;
4792	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4793	{
4794	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4795	"%08x - %08x %s\n",
4796	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4797	if (RT_FAILURE(rc))
4798	return rc;
4799	}
4800
4801	return VINF_SUCCESS;
4802	}
4803
4804
4805	/**
4806	* The '.pgmerror' and '.pgmerroroff' commands.
4807	*
4808	* @returns VBox status.
4809	* @param pCmd Pointer to the command descriptor (as registered).
4810	* @param pCmdHlp Pointer to command helper functions.
4811	* @param pVM Pointer to the current VM (if any).
4812	* @param paArgs Pointer to (readonly) array of arguments.
4813	* @param cArgs Number of arguments in the array.
4814	*/
4815	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4816	{
4817	/*
4818	* Validate input.
4819	*/
4820	if (!pVM)
4821	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4822	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4823	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4824
4825	if (!cArgs)
4826	{
4827	/*
4828	* Print the list of error injection locations with status.
4829	*/
4830	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4831	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4832	}
4833	else
4834	{
4835
4836	/*
4837	* String switch on where to inject the error.
4838	*/
4839	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4840	const char *pszWhere = paArgs[0].u.pszString;
4841	if (!strcmp(pszWhere, "handy"))
4842	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4843	else
4844	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4845	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4846	}
4847	return VINF_SUCCESS;
4848	}
4849
4850
4851	/**
4852	* The '.pgmsync' command.
4853	*
4854	* @returns VBox status.
4855	* @param pCmd Pointer to the command descriptor (as registered).
4856	* @param pCmdHlp Pointer to command helper functions.
4857	* @param pVM Pointer to the current VM (if any).
4858	* @param paArgs Pointer to (readonly) array of arguments.
4859	* @param cArgs Number of arguments in the array.
4860	*/
4861	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4862	{
4863	/** @todo SMP support */
4864	PVMCPU pVCpu = &pVM->aCpus[0];
4865
4866	/*
4867	* Validate input.
4868	*/
4869	if (!pVM)
4870	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4871
4872	/*
4873	* Force page directory sync.
4874	*/
4875	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4876
4877	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4878	if (RT_FAILURE(rc))
4879	return rc;
4880
4881	return VINF_SUCCESS;
4882	}
4883
4884
4885	#ifdef VBOX_STRICT
4886	/**
4887	* The '.pgmassertcr3' command.
4888	*
4889	* @returns VBox status.
4890	* @param pCmd Pointer to the command descriptor (as registered).
4891	* @param pCmdHlp Pointer to command helper functions.
4892	* @param pVM Pointer to the current VM (if any).
4893	* @param paArgs Pointer to (readonly) array of arguments.
4894	* @param cArgs Number of arguments in the array.
4895	*/
4896	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4897	{
4898	/** @todo SMP support!! */
4899	PVMCPU pVCpu = &pVM->aCpus[0];
4900
4901	/*
4902	* Validate input.
4903	*/
4904	if (!pVM)
4905	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4906
4907	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4908	if (RT_FAILURE(rc))
4909	return rc;
4910
4911	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4912
4913	return VINF_SUCCESS;
4914	}
4915	#endif /* VBOX_STRICT */
4916
4917
4918	/**
4919	* The '.pgmsyncalways' command.
4920	*
4921	* @returns VBox status.
4922	* @param pCmd Pointer to the command descriptor (as registered).
4923	* @param pCmdHlp Pointer to command helper functions.
4924	* @param pVM Pointer to the current VM (if any).
4925	* @param paArgs Pointer to (readonly) array of arguments.
4926	* @param cArgs Number of arguments in the array.
4927	*/
4928	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4929	{
4930	/** @todo SMP support!! */
4931	PVMCPU pVCpu = &pVM->aCpus[0];
4932
4933	/*
4934	* Validate input.
4935	*/
4936	if (!pVM)
4937	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4938
4939	/*
4940	* Force page directory sync.
4941	*/
4942	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4943	{
4944	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4945	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4946	}
4947	else
4948	{
4949	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4950	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4951	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4952	}
4953	}
4954
4955	#endif /* VBOX_WITH_DEBUGGER */
4956
4957	/**
4958	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4959	*/
4960	typedef struct PGMCHECKINTARGS
4961	{
4962	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4963	PPGMPHYSHANDLER pPrevPhys;
4964	PPGMVIRTHANDLER pPrevVirt;
4965	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4966	PVM pVM;
4967	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4968
4969	/**
4970	* Validate a node in the physical handler tree.
4971	*
4972	* @returns 0 on if ok, other wise 1.
4973	* @param pNode The handler node.
4974	* @param pvUser pVM.
4975	*/
4976	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4977	{
4978	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4979	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4980	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4981	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4982	AssertReleaseMsg( !pArgs->pPrevPhys
4983	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4984	("pPrevPhys=%p %RGp-%RGp %s\n"
4985	" pCur=%p %RGp-%RGp %s\n",
4986	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4987	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4988	pArgs->pPrevPhys = pCur;
4989	return 0;
4990	}
4991
4992
4993	/**
4994	* Validate a node in the virtual handler tree.
4995	*
4996	* @returns 0 on if ok, other wise 1.
4997	* @param pNode The handler node.
4998	* @param pvUser pVM.
4999	*/
5000	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
5001	{
5002	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5003	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
5004	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5005	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5006	AssertReleaseMsg( !pArgs->pPrevVirt
5007	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
5008	("pPrevVirt=%p %RGv-%RGv %s\n"
5009	" pCur=%p %RGv-%RGv %s\n",
5010	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
5011	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5012	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
5013	{
5014	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
5015	("pCur=%p %RGv-%RGv %s\n"
5016	"iPage=%d offVirtHandle=%#x expected %#x\n",
5017	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
5018	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
5019	}
5020	pArgs->pPrevVirt = pCur;
5021	return 0;
5022	}
5023
5024
5025	/**
5026	* Validate a node in the virtual handler tree.
5027	*
5028	* @returns 0 on if ok, other wise 1.
5029	* @param pNode The handler node.
5030	* @param pvUser pVM.
5031	*/
5032	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5033	{
5034	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5035	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
5036	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
5037	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
5038	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
5039	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5040	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5041	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5042	" pCur=%p %RGp-%RGp\n",
5043	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5044	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5045	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5046	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5047	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5048	" pCur=%p %RGp-%RGp\n",
5049	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5050	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5051	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
5052	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5053	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5054	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
5055	{
5056	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
5057	for (;;)
5058	{
5059	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
5060	AssertReleaseMsg(pCur2 != pCur,
5061	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5062	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5063	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
5064	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5065	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5066	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5067	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5068	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
5069	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5070	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5071	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5072	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5073	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
5074	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5075	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5076	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5077	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5078	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
5079	break;
5080	}
5081	}
5082
5083	pArgs->pPrevPhys2Virt = pCur;
5084	return 0;
5085	}
5086
5087
5088	/**
5089	* Perform an integrity check on the PGM component.
5090	*
5091	* @returns VINF_SUCCESS if everything is fine.
5092	* @returns VBox error status after asserting on integrity breach.
5093	* @param pVM The VM handle.
5094	*/
5095	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
5096	{
5097	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
5098
5099	/*
5100	* Check the trees.
5101	*/
5102	int cErrors = 0;
5103	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
5104	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
5105	PGMCHECKINTARGS Args = s_LeftToRight;
5106	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5107	Args = s_RightToLeft;
5108	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5109	Args = s_LeftToRight;
5110	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5111	Args = s_RightToLeft;
5112	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5113	Args = s_LeftToRight;
5114	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5115	Args = s_RightToLeft;
5116	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5117	Args = s_LeftToRight;
5118	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5119	Args = s_RightToLeft;
5120	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5121
5122	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
5123	}
5124
5125

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 21164

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