PGM.cpp@ 14755

Last change on this file since 14755 was 14755, checked in by vboxsync, 16 years ago
#1865: Converted 4 PGM2HC conversion functions to RTR3PTR.
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1	/* $Id: PGM.cpp 14755 2008-11-28 02:58:01Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574
575	/** Saved state data unit version. */
576	#define PGM_SAVED_STATE_VERSION 6
577
578	/*******************************************************************************
579	* Header Files *
580	*******************************************************************************/
581	#define LOG_GROUP LOG_GROUP_PGM
582	#include <VBox/dbgf.h>
583	#include <VBox/pgm.h>
584	#include <VBox/cpum.h>
585	#include <VBox/iom.h>
586	#include <VBox/sup.h>
587	#include <VBox/mm.h>
588	#include <VBox/em.h>
589	#include <VBox/stam.h>
590	#include <VBox/rem.h>
591	#include <VBox/dbgf.h>
592	#include <VBox/rem.h>
593	#include <VBox/selm.h>
594	#include <VBox/ssm.h>
595	#include "PGMInternal.h"
596	#include <VBox/vm.h>
597	#include <VBox/dbg.h>
598	#include <VBox/hwaccm.h>
599
600	#include <iprt/assert.h>
601	#include <iprt/alloc.h>
602	#include <iprt/asm.h>
603	#include <iprt/thread.h>
604	#include <iprt/string.h>
605	#ifdef DEBUG_bird
606	# include <iprt/env.h>
607	#endif
608	#include <VBox/param.h>
609	#include <VBox/err.h>
610
611
612
613	/*******************************************************************************
614	* Internal Functions *
615	*******************************************************************************/
616	static int pgmR3InitPaging(PVM pVM);
617	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
620	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
623	#ifdef VBOX_STRICT
624	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
625	#endif
626	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
627	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
628	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
629	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
630	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
631
632	#ifdef VBOX_WITH_STATISTICS
633	static void pgmR3InitStats(PVM pVM);
634	#endif
635
636	#ifdef VBOX_WITH_DEBUGGER
637	/** @todo all but the two last commands must be converted to 'info'. */
638	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# ifdef VBOX_STRICT
643	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# endif
645	#endif
646
647
648	/*******************************************************************************
649	* Global Variables *
650	*******************************************************************************/
651	#ifdef VBOX_WITH_DEBUGGER
652	/** Command descriptors. */
653	static const DBGCCMD g_aCmds[] =
654	{
655	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
656	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
657	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
658	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
659	#ifdef VBOX_STRICT
660	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
661	#endif
662	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
663	};
664	#endif
665
666
667
668
669	/*
670	* Shadow - 32-bit mode
671	*/
672	#define PGM_SHW_TYPE PGM_TYPE_32BIT
673	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
674	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
675	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
676	#include "PGMShw.h"
677
678	/* Guest - real mode */
679	#define PGM_GST_TYPE PGM_TYPE_REAL
680	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
681	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
682	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
683	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
684	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
685	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
686	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
687	#include "PGMGst.h"
688	#include "PGMBth.h"
689	#undef BTH_PGMPOOLKIND_PT_FOR_PT
690	#undef PGM_BTH_NAME
691	#undef PGM_BTH_NAME_RC_STR
692	#undef PGM_BTH_NAME_R0_STR
693	#undef PGM_GST_TYPE
694	#undef PGM_GST_NAME
695	#undef PGM_GST_NAME_RC_STR
696	#undef PGM_GST_NAME_R0_STR
697
698	/* Guest - protected mode */
699	#define PGM_GST_TYPE PGM_TYPE_PROT
700	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
701	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
702	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
703	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
704	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
705	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
706	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
707	#include "PGMGst.h"
708	#include "PGMBth.h"
709	#undef BTH_PGMPOOLKIND_PT_FOR_PT
710	#undef PGM_BTH_NAME
711	#undef PGM_BTH_NAME_RC_STR
712	#undef PGM_BTH_NAME_R0_STR
713	#undef PGM_GST_TYPE
714	#undef PGM_GST_NAME
715	#undef PGM_GST_NAME_RC_STR
716	#undef PGM_GST_NAME_R0_STR
717
718	/* Guest - 32-bit mode */
719	#define PGM_GST_TYPE PGM_TYPE_32BIT
720	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
721	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
722	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
723	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
724	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
725	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
726	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
727	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
728	#include "PGMGst.h"
729	#include "PGMBth.h"
730	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
731	#undef BTH_PGMPOOLKIND_PT_FOR_PT
732	#undef PGM_BTH_NAME
733	#undef PGM_BTH_NAME_RC_STR
734	#undef PGM_BTH_NAME_R0_STR
735	#undef PGM_GST_TYPE
736	#undef PGM_GST_NAME
737	#undef PGM_GST_NAME_RC_STR
738	#undef PGM_GST_NAME_R0_STR
739
740	#undef PGM_SHW_TYPE
741	#undef PGM_SHW_NAME
742	#undef PGM_SHW_NAME_RC_STR
743	#undef PGM_SHW_NAME_R0_STR
744
745
746	/*
747	* Shadow - PAE mode
748	*/
749	#define PGM_SHW_TYPE PGM_TYPE_PAE
750	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
751	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
752	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
753	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
754	#include "PGMShw.h"
755
756	/* Guest - real mode */
757	#define PGM_GST_TYPE PGM_TYPE_REAL
758	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
759	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
760	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
761	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
762	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
763	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
764	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
765	#include "PGMBth.h"
766	#undef BTH_PGMPOOLKIND_PT_FOR_PT
767	#undef PGM_BTH_NAME
768	#undef PGM_BTH_NAME_RC_STR
769	#undef PGM_BTH_NAME_R0_STR
770	#undef PGM_GST_TYPE
771	#undef PGM_GST_NAME
772	#undef PGM_GST_NAME_RC_STR
773	#undef PGM_GST_NAME_R0_STR
774
775	/* Guest - protected mode */
776	#define PGM_GST_TYPE PGM_TYPE_PROT
777	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
778	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
779	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
780	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
781	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
782	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
783	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
784	#include "PGMBth.h"
785	#undef BTH_PGMPOOLKIND_PT_FOR_PT
786	#undef PGM_BTH_NAME
787	#undef PGM_BTH_NAME_RC_STR
788	#undef PGM_BTH_NAME_R0_STR
789	#undef PGM_GST_TYPE
790	#undef PGM_GST_NAME
791	#undef PGM_GST_NAME_RC_STR
792	#undef PGM_GST_NAME_R0_STR
793
794	/* Guest - 32-bit mode */
795	#define PGM_GST_TYPE PGM_TYPE_32BIT
796	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
797	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
798	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
799	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
800	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
801	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
802	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
803	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
804	#include "PGMBth.h"
805	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
806	#undef BTH_PGMPOOLKIND_PT_FOR_PT
807	#undef PGM_BTH_NAME
808	#undef PGM_BTH_NAME_RC_STR
809	#undef PGM_BTH_NAME_R0_STR
810	#undef PGM_GST_TYPE
811	#undef PGM_GST_NAME
812	#undef PGM_GST_NAME_RC_STR
813	#undef PGM_GST_NAME_R0_STR
814
815	/* Guest - PAE mode */
816	#define PGM_GST_TYPE PGM_TYPE_PAE
817	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
818	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
819	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
820	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
821	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
822	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
823	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
824	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
825	#include "PGMGst.h"
826	#include "PGMBth.h"
827	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
828	#undef BTH_PGMPOOLKIND_PT_FOR_PT
829	#undef PGM_BTH_NAME
830	#undef PGM_BTH_NAME_RC_STR
831	#undef PGM_BTH_NAME_R0_STR
832	#undef PGM_GST_TYPE
833	#undef PGM_GST_NAME
834	#undef PGM_GST_NAME_RC_STR
835	#undef PGM_GST_NAME_R0_STR
836
837	#undef PGM_SHW_TYPE
838	#undef PGM_SHW_NAME
839	#undef PGM_SHW_NAME_RC_STR
840	#undef PGM_SHW_NAME_R0_STR
841
842
843	/*
844	* Shadow - AMD64 mode
845	*/
846	#define PGM_SHW_TYPE PGM_TYPE_AMD64
847	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
848	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
849	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
850	#include "PGMShw.h"
851
852	#ifdef VBOX_WITH_64_BITS_GUESTS
853	/* Guest - AMD64 mode */
854	# define PGM_GST_TYPE PGM_TYPE_AMD64
855	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
856	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
857	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
858	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
859	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
860	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
861	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
862	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
863	# include "PGMGst.h"
864	# include "PGMBth.h"
865	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
866	# undef BTH_PGMPOOLKIND_PT_FOR_PT
867	# undef PGM_BTH_NAME
868	# undef PGM_BTH_NAME_RC_STR
869	# undef PGM_BTH_NAME_R0_STR
870	# undef PGM_GST_TYPE
871	# undef PGM_GST_NAME
872	# undef PGM_GST_NAME_RC_STR
873	# undef PGM_GST_NAME_R0_STR
874	#endif /* VBOX_WITH_64_BITS_GUESTS */
875
876	#undef PGM_SHW_TYPE
877	#undef PGM_SHW_NAME
878	#undef PGM_SHW_NAME_RC_STR
879	#undef PGM_SHW_NAME_R0_STR
880
881
882	/*
883	* Shadow - Nested paging mode
884	*/
885	#define PGM_SHW_TYPE PGM_TYPE_NESTED
886	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
887	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
888	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
889	#include "PGMShw.h"
890
891	/* Guest - real mode */
892	#define PGM_GST_TYPE PGM_TYPE_REAL
893	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
894	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
895	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
896	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
897	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
898	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
899	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
900	#include "PGMBth.h"
901	#undef BTH_PGMPOOLKIND_PT_FOR_PT
902	#undef PGM_BTH_NAME
903	#undef PGM_BTH_NAME_RC_STR
904	#undef PGM_BTH_NAME_R0_STR
905	#undef PGM_GST_TYPE
906	#undef PGM_GST_NAME
907	#undef PGM_GST_NAME_RC_STR
908	#undef PGM_GST_NAME_R0_STR
909
910	/* Guest - protected mode */
911	#define PGM_GST_TYPE PGM_TYPE_PROT
912	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
913	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
914	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
915	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
916	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
917	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
918	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
919	#include "PGMBth.h"
920	#undef BTH_PGMPOOLKIND_PT_FOR_PT
921	#undef PGM_BTH_NAME
922	#undef PGM_BTH_NAME_RC_STR
923	#undef PGM_BTH_NAME_R0_STR
924	#undef PGM_GST_TYPE
925	#undef PGM_GST_NAME
926	#undef PGM_GST_NAME_RC_STR
927	#undef PGM_GST_NAME_R0_STR
928
929	/* Guest - 32-bit mode */
930	#define PGM_GST_TYPE PGM_TYPE_32BIT
931	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
932	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
933	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
934	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
935	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
936	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
937	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
938	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
939	#include "PGMBth.h"
940	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
941	#undef BTH_PGMPOOLKIND_PT_FOR_PT
942	#undef PGM_BTH_NAME
943	#undef PGM_BTH_NAME_RC_STR
944	#undef PGM_BTH_NAME_R0_STR
945	#undef PGM_GST_TYPE
946	#undef PGM_GST_NAME
947	#undef PGM_GST_NAME_RC_STR
948	#undef PGM_GST_NAME_R0_STR
949
950	/* Guest - PAE mode */
951	#define PGM_GST_TYPE PGM_TYPE_PAE
952	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
953	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
954	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
955	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
956	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
957	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
958	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
959	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
960	#include "PGMBth.h"
961	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
962	#undef BTH_PGMPOOLKIND_PT_FOR_PT
963	#undef PGM_BTH_NAME
964	#undef PGM_BTH_NAME_RC_STR
965	#undef PGM_BTH_NAME_R0_STR
966	#undef PGM_GST_TYPE
967	#undef PGM_GST_NAME
968	#undef PGM_GST_NAME_RC_STR
969	#undef PGM_GST_NAME_R0_STR
970
971	#ifdef VBOX_WITH_64_BITS_GUESTS
972	/* Guest - AMD64 mode */
973	# define PGM_GST_TYPE PGM_TYPE_AMD64
974	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
975	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
976	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
977	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
978	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
979	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
980	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
981	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
982	# include "PGMBth.h"
983	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
984	# undef BTH_PGMPOOLKIND_PT_FOR_PT
985	# undef PGM_BTH_NAME
986	# undef PGM_BTH_NAME_RC_STR
987	# undef PGM_BTH_NAME_R0_STR
988	# undef PGM_GST_TYPE
989	# undef PGM_GST_NAME
990	# undef PGM_GST_NAME_RC_STR
991	# undef PGM_GST_NAME_R0_STR
992	#endif /* VBOX_WITH_64_BITS_GUESTS */
993
994	#undef PGM_SHW_TYPE
995	#undef PGM_SHW_NAME
996	#undef PGM_SHW_NAME_RC_STR
997	#undef PGM_SHW_NAME_R0_STR
998
999
1000	/*
1001	* Shadow - EPT
1002	*/
1003	#define PGM_SHW_TYPE PGM_TYPE_EPT
1004	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1005	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1006	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1007	#include "PGMShw.h"
1008
1009	/* Guest - real mode */
1010	#define PGM_GST_TYPE PGM_TYPE_REAL
1011	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1012	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1013	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1014	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1015	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1016	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1017	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1018	#include "PGMBth.h"
1019	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1020	#undef PGM_BTH_NAME
1021	#undef PGM_BTH_NAME_RC_STR
1022	#undef PGM_BTH_NAME_R0_STR
1023	#undef PGM_GST_TYPE
1024	#undef PGM_GST_NAME
1025	#undef PGM_GST_NAME_RC_STR
1026	#undef PGM_GST_NAME_R0_STR
1027
1028	/* Guest - protected mode */
1029	#define PGM_GST_TYPE PGM_TYPE_PROT
1030	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1031	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1032	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1033	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1034	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1035	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1036	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1037	#include "PGMBth.h"
1038	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1039	#undef PGM_BTH_NAME
1040	#undef PGM_BTH_NAME_RC_STR
1041	#undef PGM_BTH_NAME_R0_STR
1042	#undef PGM_GST_TYPE
1043	#undef PGM_GST_NAME
1044	#undef PGM_GST_NAME_RC_STR
1045	#undef PGM_GST_NAME_R0_STR
1046
1047	/* Guest - 32-bit mode */
1048	#define PGM_GST_TYPE PGM_TYPE_32BIT
1049	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1050	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1051	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1052	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1053	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1054	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1055	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1056	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1057	#include "PGMBth.h"
1058	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1059	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1060	#undef PGM_BTH_NAME
1061	#undef PGM_BTH_NAME_RC_STR
1062	#undef PGM_BTH_NAME_R0_STR
1063	#undef PGM_GST_TYPE
1064	#undef PGM_GST_NAME
1065	#undef PGM_GST_NAME_RC_STR
1066	#undef PGM_GST_NAME_R0_STR
1067
1068	/* Guest - PAE mode */
1069	#define PGM_GST_TYPE PGM_TYPE_PAE
1070	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1071	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1072	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1073	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1074	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1075	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1076	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1077	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1078	#include "PGMBth.h"
1079	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1080	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1081	#undef PGM_BTH_NAME
1082	#undef PGM_BTH_NAME_RC_STR
1083	#undef PGM_BTH_NAME_R0_STR
1084	#undef PGM_GST_TYPE
1085	#undef PGM_GST_NAME
1086	#undef PGM_GST_NAME_RC_STR
1087	#undef PGM_GST_NAME_R0_STR
1088
1089	#ifdef VBOX_WITH_64_BITS_GUESTS
1090	/* Guest - AMD64 mode */
1091	# define PGM_GST_TYPE PGM_TYPE_AMD64
1092	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1093	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1094	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1095	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1096	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1097	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1098	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1099	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1100	# include "PGMBth.h"
1101	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1102	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1103	# undef PGM_BTH_NAME
1104	# undef PGM_BTH_NAME_RC_STR
1105	# undef PGM_BTH_NAME_R0_STR
1106	# undef PGM_GST_TYPE
1107	# undef PGM_GST_NAME
1108	# undef PGM_GST_NAME_RC_STR
1109	# undef PGM_GST_NAME_R0_STR
1110	#endif /* VBOX_WITH_64_BITS_GUESTS */
1111
1112	#undef PGM_SHW_TYPE
1113	#undef PGM_SHW_NAME
1114	#undef PGM_SHW_NAME_RC_STR
1115	#undef PGM_SHW_NAME_R0_STR
1116
1117
1118
1119	/**
1120	* Initiates the paging of VM.
1121	*
1122	* @returns VBox status code.
1123	* @param pVM Pointer to VM structure.
1124	*/
1125	VMMR3DECL(int) PGMR3Init(PVM pVM)
1126	{
1127	LogFlow(("PGMR3Init:\n"));
1128
1129	/*
1130	* Assert alignment and sizes.
1131	*/
1132	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1133
1134	/*
1135	* Init the structure.
1136	*/
1137	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1138	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1139	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1140	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1141	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1142	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1143	pVM->pgm.s.fA20Enabled = true;
1144	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1145	pVM->pgm.s.pGstPaePdptR3 = NULL;
1146	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1147	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1148	#endif
1149	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1150	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1151	{
1152	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1153	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1154	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1155	#endif
1156	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1157	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1158	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1159	}
1160
1161	#ifdef VBOX_STRICT
1162	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1163	#endif
1164
1165	/*
1166	* Get the configured RAM size - to estimate saved state size.
1167	*/
1168	uint64_t cbRam;
1169	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1170	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1171	cbRam = pVM->pgm.s.cbRamSize = 0;
1172	else if (RT_SUCCESS(rc))
1173	{
1174	if (cbRam < PAGE_SIZE)
1175	cbRam = 0;
1176	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1177	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1178	}
1179	else
1180	{
1181	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1182	return rc;
1183	}
1184
1185	/*
1186	* Register saved state data unit.
1187	*/
1188	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1189	NULL, pgmR3Save, NULL,
1190	NULL, pgmR3Load, NULL);
1191	if (RT_FAILURE(rc))
1192	return rc;
1193
1194	/*
1195	* Initialize the PGM critical section and flush the phys TLBs
1196	*/
1197	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1198	AssertRCReturn(rc, rc);
1199
1200	PGMR3PhysChunkInvalidateTLB(pVM);
1201	PGMPhysInvalidatePageR3MapTLB(pVM);
1202	PGMPhysInvalidatePageR0MapTLB(pVM);
1203	PGMPhysInvalidatePageGCMapTLB(pVM);
1204
1205	/*
1206	* Trees
1207	*/
1208	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1209	if (RT_SUCCESS(rc))
1210	{
1211	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1212	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1213
1214	/*
1215	* Alocate the zero page.
1216	*/
1217	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1218	}
1219	if (RT_SUCCESS(rc))
1220	{
1221	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1222	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1223	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1224	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1225	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1226
1227	/*
1228	* Init the paging.
1229	*/
1230	rc = pgmR3InitPaging(pVM);
1231	}
1232	if (RT_SUCCESS(rc))
1233	{
1234	/*
1235	* Init the page pool.
1236	*/
1237	rc = pgmR3PoolInit(pVM);
1238	}
1239	if (RT_SUCCESS(rc))
1240	{
1241	/*
1242	* Info & statistics
1243	*/
1244	DBGFR3InfoRegisterInternal(pVM, "mode",
1245	"Shows the current paging mode. "
1246	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1247	pgmR3InfoMode);
1248	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1249	"Dumps all the entries in the top level paging table. No arguments.",
1250	pgmR3InfoCr3);
1251	DBGFR3InfoRegisterInternal(pVM, "phys",
1252	"Dumps all the physical address ranges. No arguments.",
1253	pgmR3PhysInfo);
1254	DBGFR3InfoRegisterInternal(pVM, "handlers",
1255	"Dumps physical, virtual and hyper virtual handlers. "
1256	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1257	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1258	pgmR3InfoHandlers);
1259	DBGFR3InfoRegisterInternal(pVM, "mappings",
1260	"Dumps guest mappings.",
1261	pgmR3MapInfo);
1262
1263	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1264	#ifdef VBOX_WITH_STATISTICS
1265	pgmR3InitStats(pVM);
1266	#endif
1267	#ifdef VBOX_WITH_DEBUGGER
1268	/*
1269	* Debugger commands.
1270	*/
1271	static bool fRegisteredCmds = false;
1272	if (!fRegisteredCmds)
1273	{
1274	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1275	if (RT_SUCCESS(rc))
1276	fRegisteredCmds = true;
1277	}
1278	#endif
1279	return VINF_SUCCESS;
1280	}
1281
1282	/* Almost no cleanup necessary, MM frees all memory. */
1283	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1284
1285	return rc;
1286	}
1287
1288
1289	/**
1290	* Initializes the per-VCPU PGM.
1291	*
1292	* @returns VBox status code.
1293	* @param pVM The VM to operate on.
1294	*/
1295	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1296	{
1297	LogFlow(("PGMR3InitCPU\n"));
1298	return VINF_SUCCESS;
1299	}
1300
1301
1302	/**
1303	* Init paging.
1304	*
1305	* Since we need to check what mode the host is operating in before we can choose
1306	* the right paging functions for the host we have to delay this until R0 has
1307	* been initialized.
1308	*
1309	* @returns VBox status code.
1310	* @param pVM VM handle.
1311	*/
1312	static int pgmR3InitPaging(PVM pVM)
1313	{
1314	/*
1315	* Force a recalculation of modes and switcher so everyone gets notified.
1316	*/
1317	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1318	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1319	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1320
1321	/*
1322	* Allocate static mapping space for whatever the cr3 register
1323	* points to and in the case of PAE mode to the 4 PDs.
1324	*/
1325	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1326	if (RT_FAILURE(rc))
1327	{
1328	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1329	return rc;
1330	}
1331	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1332
1333	/*
1334	* Allocate pages for the three possible intermediate contexts
1335	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1336	* for the sake of simplicity. The AMD64 uses the PAE for the
1337	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1338	*
1339	* We assume that two page tables will be enought for the core code
1340	* mappings (HC virtual and identity).
1341	*/
1342	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1343	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1344	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1345	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1346	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1347	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1348	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1349	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1350	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1351	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1352	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1353	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1354	if ( !pVM->pgm.s.pInterPD
1355	\|\| !pVM->pgm.s.apInterPTs[0]
1356	\|\| !pVM->pgm.s.apInterPTs[1]
1357	\|\| !pVM->pgm.s.apInterPaePTs[0]
1358	\|\| !pVM->pgm.s.apInterPaePTs[1]
1359	\|\| !pVM->pgm.s.apInterPaePDs[0]
1360	\|\| !pVM->pgm.s.apInterPaePDs[1]
1361	\|\| !pVM->pgm.s.apInterPaePDs[2]
1362	\|\| !pVM->pgm.s.apInterPaePDs[3]
1363	\|\| !pVM->pgm.s.pInterPaePDPT
1364	\|\| !pVM->pgm.s.pInterPaePDPT64
1365	\|\| !pVM->pgm.s.pInterPaePML4)
1366	{
1367	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1368	return VERR_NO_PAGE_MEMORY;
1369	}
1370
1371	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1372	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1373	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1374	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1375	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1376	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1377
1378	/*
1379	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1380	*/
1381	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1382	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1383	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1384
1385	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1386	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1387
1388	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1389	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1390	{
1391	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1392	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1393	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1394	}
1395
1396	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1397	{
1398	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1399	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1400	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1401	}
1402
1403	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1404	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1405	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1406	\| HCPhysInterPaePDPT64;
1407
1408	/*
1409	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1410	* We allocate pages for all three posibilities in order to simplify mappings and
1411	* avoid resource failure during mode switches. So, we need to cover all levels of the
1412	* of the first 4GB down to PD level.
1413	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1414	*/
1415	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1416	pVM->pgm.s.pShw32BitPdR3 = (PX86PD)MMR3PageAllocLow(pVM);
1417	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1418	pVM->pgm.s.pShw32BitPdR0 = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
1419	# endif
1420	pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1421	pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1422	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1]);
1423	pVM->pgm.s.apShwPaePDsR3[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1424	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2]);
1425	pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1426	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
1427	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1428	pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
1429	pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
1430	pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
1431	pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
1432	# endif
1433	pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
1434	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1435	pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
1436	# endif
1437	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
1438	pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
1439	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1440	pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
1441	#endif
1442
1443	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1444	if (!pVM->pgm.s.pShwNestedRootR3)
1445	#else
1446	if ( !pVM->pgm.s.pShw32BitPdR3
1447	\|\| !pVM->pgm.s.apShwPaePDsR3[0]
1448	\|\| !pVM->pgm.s.apShwPaePDsR3[1]
1449	\|\| !pVM->pgm.s.apShwPaePDsR3[2]
1450	\|\| !pVM->pgm.s.apShwPaePDsR3[3]
1451	\|\| !pVM->pgm.s.pShwPaePdptR3
1452	\|\| !pVM->pgm.s.pShwNestedRootR3)
1453	#endif
1454	{
1455	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1456	return VERR_NO_PAGE_MEMORY;
1457	}
1458
1459	/* get physical addresses. */
1460	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1461	pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
1462	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
1463	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[0]);
1464	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[1]);
1465	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[2]);
1466	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
1467	pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
1468	#endif
1469	pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
1470
1471	/*
1472	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1473	*/
1474	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1475	ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
1476	ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
1477	#endif
1478	ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
1479	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1480	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1481	{
1482	ASMMemZero32(pVM->pgm.s.apShwPaePDsR3[i], PAGE_SIZE);
1483	pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1484	/* The flags will be corrected when entering and leaving long mode. */
1485	}
1486
1487	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhysShw32BitPD);
1488	#endif
1489
1490	/*
1491	* Initialize paging workers and mode from current host mode
1492	* and the guest running in real mode.
1493	*/
1494	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1495	switch (pVM->pgm.s.enmHostMode)
1496	{
1497	case SUPPAGINGMODE_32_BIT:
1498	case SUPPAGINGMODE_32_BIT_GLOBAL:
1499	case SUPPAGINGMODE_PAE:
1500	case SUPPAGINGMODE_PAE_GLOBAL:
1501	case SUPPAGINGMODE_PAE_NX:
1502	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1503	break;
1504
1505	case SUPPAGINGMODE_AMD64:
1506	case SUPPAGINGMODE_AMD64_GLOBAL:
1507	case SUPPAGINGMODE_AMD64_NX:
1508	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1509	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1510	if (ARCH_BITS != 64)
1511	{
1512	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1513	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1514	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1515	}
1516	#endif
1517	break;
1518	default:
1519	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1520	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1521	}
1522	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1523	if (RT_SUCCESS(rc))
1524	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1525	if (RT_SUCCESS(rc))
1526	{
1527	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1528	#if HC_ARCH_BITS == 64
1529	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1530	LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp HCPhysShwPaePml4=%RHp\n",
1531	pVM->pgm.s.HCPhysShw32BitPD,
1532	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1533	pVM->pgm.s.HCPhysShwPaePdpt,
1534	pVM->pgm.s.HCPhysShwPaePml4));
1535	# endif
1536	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1537	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1538	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1539	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1540	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1541	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1542	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1543	#endif
1544
1545	return VINF_SUCCESS;
1546	}
1547
1548	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1549	return rc;
1550	}
1551
1552
1553	#ifdef VBOX_WITH_STATISTICS
1554	/**
1555	* Init statistics
1556	*/
1557	static void pgmR3InitStats(PVM pVM)
1558	{
1559	PPGM pPGM = &pVM->pgm.s;
1560	unsigned i;
1561
1562	/*
1563	* Note! The layout of this function matches the member layout exactly!
1564	*/
1565
1566	/* Common - misc variables */
1567	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1568	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1569	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1570	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1571	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1572	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1573
1574	/* Common - stats */
1575	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1576	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1577	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1578	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1579	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1580	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1581	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1582	#endif
1583	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1584	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1585	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1586	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1587	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1588	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1589
1590	/* R3 only: */
1591	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1592	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1593	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1594	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1595	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1596	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1597
1598	/* GC only: */
1599	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1600	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1601	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1602	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1603
1604	/* RZ only: */
1605	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1606	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1607	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1608	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1609	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1610	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1611	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1612	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1613	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1614	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1615	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1616	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1617	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1618	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1619	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1620	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1621	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1622	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1623	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1624	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1625	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1626	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1627	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1628	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1629	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1630	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1631	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1632	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1633	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1634	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1635	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1636	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1637	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1638	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1639	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1640	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1641	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1642	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1643	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1644	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1645	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1646	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1647	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1648	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1649	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1650	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1651	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1652	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1653	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1654	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1655	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1656
1657	/* HC only: */
1658
1659	/* RZ & R3: */
1660	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1661	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1662	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1663	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1664	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1665	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1666	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1667	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1668	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1669	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1670	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1671	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1672	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1673	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1674	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1675	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1676	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1677	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1678	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1679	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1680	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1681	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1682	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1683	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1684	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1685	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1686	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1687	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1688	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1689	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1690	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1691	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1692	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1693	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1694	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1695	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1696	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1697	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1698	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1699	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1700	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1701	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1702	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1703	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1704	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1705	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1706	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1707	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1708	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1709	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1710	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1711	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1712	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1713	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1714
1715	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1716	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1717	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1718	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1719	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1720	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1721	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1722	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1723	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1724	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1725	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1726	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1727	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1728	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1729	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1730	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1731	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1732	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1733	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1734	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1735	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1736	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1737	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1738	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1739	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1740	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1741	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1742	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1743	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1744	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1745	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1746	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1747	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1748	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1749	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1750	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1751	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1752	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1753	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1754	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1755	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1756	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1757	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1758	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1759	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1760	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1761	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1762	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1763	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1764	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1765	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1766	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1767	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1768	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1769
1770	}
1771	#endif /* VBOX_WITH_STATISTICS */
1772
1773
1774	/**
1775	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1776	*
1777	* The dynamic mapping area will also be allocated and initialized at this
1778	* time. We could allocate it during PGMR3Init of course, but the mapping
1779	* wouldn't be allocated at that time preventing us from setting up the
1780	* page table entries with the dummy page.
1781	*
1782	* @returns VBox status code.
1783	* @param pVM VM handle.
1784	*/
1785	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1786	{
1787	RTGCPTR GCPtr;
1788	int rc;
1789
1790	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1791	/*
1792	* Reserve space for mapping the paging pages into guest context.
1793	*/
1794	rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
1795	AssertRCReturn(rc, rc);
1796	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1797	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1798	#endif
1799
1800	/*
1801	* Reserve space for the dynamic mappings.
1802	*/
1803	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1804	if (RT_SUCCESS(rc))
1805	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1806
1807	if ( RT_SUCCESS(rc)
1808	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1809	{
1810	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1811	if (RT_SUCCESS(rc))
1812	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1813	}
1814	if (RT_SUCCESS(rc))
1815	{
1816	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1817	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1818	}
1819	return rc;
1820	}
1821
1822
1823	/**
1824	* Ring-3 init finalizing.
1825	*
1826	* @returns VBox status code.
1827	* @param pVM The VM handle.
1828	*/
1829	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1830	{
1831	int rc;
1832
1833	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1834	/*
1835	* Map the paging pages into the guest context.
1836	*/
1837	RTGCPTR GCPtr = pVM->pgm.s.pShw32BitPdRC;
1838	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1839
1840	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
1841	AssertRCReturn(rc, rc);
1842	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1843	GCPtr += PAGE_SIZE;
1844	GCPtr += PAGE_SIZE; /* reserved page */
1845
1846	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1847	{
1848	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1849	AssertRCReturn(rc, rc);
1850	pVM->pgm.s.apShwPaePDsRC[i] = GCPtr;
1851	GCPtr += PAGE_SIZE;
1852	}
1853	/* A bit of paranoia is justified. */
1854	AssertRelease(pVM->pgm.s.apShwPaePDsRC[0] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[1]);
1855	AssertRelease(pVM->pgm.s.apShwPaePDsRC[1] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[2]);
1856	AssertRelease(pVM->pgm.s.apShwPaePDsRC[2] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[3]);
1857	GCPtr += PAGE_SIZE; /* reserved page */
1858
1859	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShwPaePdpt, PAGE_SIZE, 0);
1860	AssertRCReturn(rc, rc);
1861	pVM->pgm.s.pShwPaePdptRC = GCPtr;
1862	GCPtr += PAGE_SIZE;
1863	GCPtr += PAGE_SIZE; /* reserved page */
1864	#endif
1865
1866	/*
1867	* Reserve space for the dynamic mappings.
1868	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1869	*/
1870	/* get the pointer to the page table entries. */
1871	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1872	AssertRelease(pMapping);
1873	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1874	const unsigned iPT = off >> X86_PD_SHIFT;
1875	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1876	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1877	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1878
1879	/* init cache */
1880	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1881	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1882	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1883
1884	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1885	{
1886	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1887	AssertRCReturn(rc, rc);
1888	}
1889
1890	/*
1891	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1892	* Intel only goes up to 36 bits, so we stick to 36 as well.
1893	*/
1894	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1895	uint32_t u32Dummy, u32Features;
1896	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1897
1898	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1899	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1900	else
1901	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1902
1903	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1904
1905	return rc;
1906	}
1907
1908
1909	/**
1910	* Applies relocations to data and code managed by this component.
1911	*
1912	* This function will be called at init and whenever the VMM need to relocate it
1913	* self inside the GC.
1914	*
1915	* @param pVM The VM.
1916	* @param offDelta Relocation delta relative to old location.
1917	*/
1918	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1919	{
1920	LogFlow(("PGMR3Relocate\n"));
1921
1922	/*
1923	* Paging stuff.
1924	*/
1925	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1926	/** @todo move this into shadow and guest specific relocation functions. */
1927	AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
1928	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1929	pVM->pgm.s.pShw32BitPdRC += offDelta;
1930	#endif
1931	pVM->pgm.s.pGst32BitPdRC += offDelta;
1932	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
1933	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC); i++)
1934	{
1935	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1936	pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
1937	#endif
1938	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1939	}
1940	pVM->pgm.s.pGstPaePdptRC += offDelta;
1941	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1942	pVM->pgm.s.pShwPaePdptRC += offDelta;
1943	#endif
1944
1945	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1946	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1947
1948	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1949	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1950	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1951
1952	/*
1953	* Trees.
1954	*/
1955	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1956
1957	/*
1958	* Ram ranges.
1959	*/
1960	if (pVM->pgm.s.pRamRangesR3)
1961	{
1962	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1963	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1964	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1965	}
1966
1967	/*
1968	* Update the two page directories with all page table mappings.
1969	* (One or more of them have changed, that's why we're here.)
1970	*/
1971	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1972	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1973	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1974
1975	/* Relocate GC addresses of Page Tables. */
1976	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1977	{
1978	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1979	{
1980	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1981	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1982	}
1983	}
1984
1985	/*
1986	* Dynamic page mapping area.
1987	*/
1988	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1989	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1990	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1991
1992	/*
1993	* The Zero page.
1994	*/
1995	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1996	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1997
1998	/*
1999	* Physical and virtual handlers.
2000	*/
2001	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2002	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2003	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2004
2005	/*
2006	* The page pool.
2007	*/
2008	pgmR3PoolRelocate(pVM);
2009	}
2010
2011
2012	/**
2013	* Callback function for relocating a physical access handler.
2014	*
2015	* @returns 0 (continue enum)
2016	* @param pNode Pointer to a PGMPHYSHANDLER node.
2017	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2018	* not certain the delta will fit in a void pointer for all possible configs.
2019	*/
2020	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2021	{
2022	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2023	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2024	if (pHandler->pfnHandlerRC)
2025	pHandler->pfnHandlerRC += offDelta;
2026	if (pHandler->pvUserRC >= 0x10000)
2027	pHandler->pvUserRC += offDelta;
2028	return 0;
2029	}
2030
2031
2032	/**
2033	* Callback function for relocating a virtual access handler.
2034	*
2035	* @returns 0 (continue enum)
2036	* @param pNode Pointer to a PGMVIRTHANDLER node.
2037	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2038	* not certain the delta will fit in a void pointer for all possible configs.
2039	*/
2040	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2041	{
2042	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2043	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2044	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2045	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2046	Assert(pHandler->pfnHandlerRC);
2047	pHandler->pfnHandlerRC += offDelta;
2048	return 0;
2049	}
2050
2051
2052	/**
2053	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2054	*
2055	* @returns 0 (continue enum)
2056	* @param pNode Pointer to a PGMVIRTHANDLER node.
2057	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2058	* not certain the delta will fit in a void pointer for all possible configs.
2059	*/
2060	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2061	{
2062	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2063	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2064	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2065	Assert(pHandler->pfnHandlerRC);
2066	pHandler->pfnHandlerRC += offDelta;
2067	return 0;
2068	}
2069
2070
2071	/**
2072	* The VM is being reset.
2073	*
2074	* For the PGM component this means that any PD write monitors
2075	* needs to be removed.
2076	*
2077	* @param pVM VM handle.
2078	*/
2079	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2080	{
2081	LogFlow(("PGMR3Reset:\n"));
2082	VM_ASSERT_EMT(pVM);
2083
2084	pgmLock(pVM);
2085
2086	/*
2087	* Unfix any fixed mappings and disable CR3 monitoring.
2088	*/
2089	pVM->pgm.s.fMappingsFixed = false;
2090	pVM->pgm.s.GCPtrMappingFixed = 0;
2091	pVM->pgm.s.cbMappingFixed = 0;
2092
2093	/* Exit the guest paging mode before the pgm pool gets reset.
2094	* Important to clean up the amd64 case.
2095	*/
2096	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2097	AssertRC(rc);
2098	#ifdef DEBUG
2099	DBGFR3InfoLog(pVM, "mappings", NULL);
2100	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2101	#endif
2102
2103	/*
2104	* Reset the shadow page pool.
2105	*/
2106	pgmR3PoolReset(pVM);
2107
2108	/*
2109	* Re-init other members.
2110	*/
2111	pVM->pgm.s.fA20Enabled = true;
2112
2113	/*
2114	* Clear the FFs PGM owns.
2115	*/
2116	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2117	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2118
2119	/*
2120	* Reset (zero) RAM pages.
2121	*/
2122	rc = pgmR3PhysRamReset(pVM);
2123	if (RT_SUCCESS(rc))
2124	{
2125	#ifdef VBOX_WITH_NEW_PHYS_CODE
2126	/*
2127	* Reset (zero) shadow ROM pages.
2128	*/
2129	rc = pgmR3PhysRomReset(pVM);
2130	#endif
2131	if (RT_SUCCESS(rc))
2132	{
2133	/*
2134	* Switch mode back to real mode.
2135	*/
2136	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2137	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2138	}
2139	}
2140
2141	pgmUnlock(pVM);
2142	//return rc;
2143	AssertReleaseRC(rc);
2144	}
2145
2146
2147	#ifdef VBOX_STRICT
2148	/**
2149	* VM state change callback for clearing fNoMorePhysWrites after
2150	* a snapshot has been created.
2151	*/
2152	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2153	{
2154	if (enmState == VMSTATE_RUNNING)
2155	pVM->pgm.s.fNoMorePhysWrites = false;
2156	}
2157	#endif
2158
2159
2160	/**
2161	* Terminates the PGM.
2162	*
2163	* @returns VBox status code.
2164	* @param pVM Pointer to VM structure.
2165	*/
2166	VMMR3DECL(int) PGMR3Term(PVM pVM)
2167	{
2168	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2169	}
2170
2171
2172	/**
2173	* Terminates the per-VCPU PGM.
2174	*
2175	* Termination means cleaning up and freeing all resources,
2176	* the VM it self is at this point powered off or suspended.
2177	*
2178	* @returns VBox status code.
2179	* @param pVM The VM to operate on.
2180	*/
2181	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2182	{
2183	return 0;
2184	}
2185
2186
2187	/**
2188	* Execute state save operation.
2189	*
2190	* @returns VBox status code.
2191	* @param pVM VM Handle.
2192	* @param pSSM SSM operation handle.
2193	*/
2194	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2195	{
2196	PPGM pPGM = &pVM->pgm.s;
2197
2198	/* No more writes to physical memory after this point! */
2199	pVM->pgm.s.fNoMorePhysWrites = true;
2200
2201	/*
2202	* Save basic data (required / unaffected by relocation).
2203	*/
2204	#if 1
2205	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2206	#else
2207	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2208	#endif
2209	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2210	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2211	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2212	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2213	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2214	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2215	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2216	SSMR3PutU32(pSSM, ~0); /* Separator. */
2217
2218	/*
2219	* The guest mappings.
2220	*/
2221	uint32_t i = 0;
2222	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2223	{
2224	SSMR3PutU32(pSSM, i);
2225	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2226	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2227	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2228	/* flags are done by the mapping owners! */
2229	}
2230	SSMR3PutU32(pSSM, ~0); /* terminator. */
2231
2232	/*
2233	* Ram range flags and bits.
2234	*/
2235	i = 0;
2236	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2237	{
2238	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2239
2240	SSMR3PutU32(pSSM, i);
2241	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2242	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2243	SSMR3PutGCPhys(pSSM, pRam->cb);
2244	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2245
2246	/* Flags. */
2247	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2248	for (unsigned iPage = 0; iPage < cPages; iPage++)
2249	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2250
2251	/* any memory associated with the range. */
2252	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2253	{
2254	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2255	{
2256	if (pRam->paChunkR3Ptrs[iChunk])
2257	{
2258	SSMR3PutU8(pSSM, 1); /* chunk present */
2259	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2260	}
2261	else
2262	SSMR3PutU8(pSSM, 0); /* no chunk present */
2263	}
2264	}
2265	else if (pRam->pvR3)
2266	{
2267	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2268	if (RT_FAILURE(rc))
2269	{
2270	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2271	return rc;
2272	}
2273	}
2274	}
2275	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2276	}
2277
2278
2279	/**
2280	* Execute state load operation.
2281	*
2282	* @returns VBox status code.
2283	* @param pVM VM Handle.
2284	* @param pSSM SSM operation handle.
2285	* @param u32Version Data layout version.
2286	*/
2287	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2288	{
2289	/*
2290	* Validate version.
2291	*/
2292	if (u32Version != PGM_SAVED_STATE_VERSION)
2293	{
2294	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2295	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2296	}
2297
2298	/*
2299	* Call the reset function to make sure all the memory is cleared.
2300	*/
2301	PGMR3Reset(pVM);
2302
2303	/*
2304	* Load basic data (required / unaffected by relocation).
2305	*/
2306	PPGM pPGM = &pVM->pgm.s;
2307	#if 1
2308	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2309	#else
2310	uint32_t u;
2311	SSMR3GetU32(pSSM, &u);
2312	pPGM->fMappingsFixed = u;
2313	#endif
2314	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2315	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2316
2317	RTUINT cbRamSize;
2318	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2319	if (RT_FAILURE(rc))
2320	return rc;
2321	if (cbRamSize != pPGM->cbRamSize)
2322	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2323	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2324	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2325	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2326	RTUINT uGuestMode;
2327	SSMR3GetUInt(pSSM, &uGuestMode);
2328	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2329
2330	/* check separator. */
2331	uint32_t u32Sep;
2332	SSMR3GetU32(pSSM, &u32Sep);
2333	if (RT_FAILURE(rc))
2334	return rc;
2335	if (u32Sep != (uint32_t)~0)
2336	{
2337	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2338	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2339	}
2340
2341	/*
2342	* The guest mappings.
2343	*/
2344	uint32_t i = 0;
2345	for (;; i++)
2346	{
2347	/* Check the seqence number / separator. */
2348	rc = SSMR3GetU32(pSSM, &u32Sep);
2349	if (RT_FAILURE(rc))
2350	return rc;
2351	if (u32Sep == ~0U)
2352	break;
2353	if (u32Sep != i)
2354	{
2355	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2356	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2357	}
2358
2359	/* get the mapping details. */
2360	char szDesc[256];
2361	szDesc[0] = '\0';
2362	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2363	if (RT_FAILURE(rc))
2364	return rc;
2365	RTGCPTR GCPtr;
2366	SSMR3GetGCPtr(pSSM, &GCPtr);
2367	RTGCPTR cPTs;
2368	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2369	if (RT_FAILURE(rc))
2370	return rc;
2371
2372	/* find matching range. */
2373	PPGMMAPPING pMapping;
2374	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2375	if ( pMapping->cPTs == cPTs
2376	&& !strcmp(pMapping->pszDesc, szDesc))
2377	break;
2378	if (!pMapping)
2379	{
2380	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2381	cPTs, szDesc, GCPtr));
2382	AssertFailed();
2383	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2384	}
2385
2386	/* relocate it. */
2387	if (pMapping->GCPtr != GCPtr)
2388	{
2389	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2390	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2391	}
2392	else
2393	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2394	}
2395
2396	/*
2397	* Ram range flags and bits.
2398	*/
2399	i = 0;
2400	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2401	{
2402	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2403	/* Check the seqence number / separator. */
2404	rc = SSMR3GetU32(pSSM, &u32Sep);
2405	if (RT_FAILURE(rc))
2406	return rc;
2407	if (u32Sep == ~0U)
2408	break;
2409	if (u32Sep != i)
2410	{
2411	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2412	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2413	}
2414
2415	/* Get the range details. */
2416	RTGCPHYS GCPhys;
2417	SSMR3GetGCPhys(pSSM, &GCPhys);
2418	RTGCPHYS GCPhysLast;
2419	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2420	RTGCPHYS cb;
2421	SSMR3GetGCPhys(pSSM, &cb);
2422	uint8_t fHaveBits;
2423	rc = SSMR3GetU8(pSSM, &fHaveBits);
2424	if (RT_FAILURE(rc))
2425	return rc;
2426	if (fHaveBits & ~1)
2427	{
2428	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2429	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2430	}
2431
2432	/* Match it up with the current range. */
2433	if ( GCPhys != pRam->GCPhys
2434	\|\| GCPhysLast != pRam->GCPhysLast
2435	\|\| cb != pRam->cb
2436	\|\| fHaveBits != !!pRam->pvR3)
2437	{
2438	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2439	"State : %RGp-%RGp %RGp bytes %s\n",
2440	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2441	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2442	/*
2443	* If we're loading a state for debugging purpose, don't make a fuss if
2444	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2445	*/
2446	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2447	\|\| GCPhys < 8 * _1M)
2448	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2449
2450	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2451	while (cPages-- > 0)
2452	{
2453	uint16_t u16Ignore;
2454	SSMR3GetU16(pSSM, &u16Ignore);
2455	}
2456	continue;
2457	}
2458
2459	/* Flags. */
2460	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2461	for (unsigned iPage = 0; iPage < cPages; iPage++)
2462	{
2463	uint16_t u16 = 0;
2464	SSMR3GetU16(pSSM, &u16);
2465	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2466	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2467	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2468	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2469	}
2470
2471	/* any memory associated with the range. */
2472	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2473	{
2474	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2475	{
2476	uint8_t fValidChunk;
2477
2478	rc = SSMR3GetU8(pSSM, &fValidChunk);
2479	if (RT_FAILURE(rc))
2480	return rc;
2481	if (fValidChunk > 1)
2482	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2483
2484	if (fValidChunk)
2485	{
2486	if (!pRam->paChunkR3Ptrs[iChunk])
2487	{
2488	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2489	if (RT_FAILURE(rc))
2490	return rc;
2491	}
2492	Assert(pRam->paChunkR3Ptrs[iChunk]);
2493
2494	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2495	}
2496	/* else nothing to do */
2497	}
2498	}
2499	else if (pRam->pvR3)
2500	{
2501	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2502	if (RT_FAILURE(rc))
2503	{
2504	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2505	return rc;
2506	}
2507	}
2508	}
2509
2510	/*
2511	* We require a full resync now.
2512	*/
2513	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2514	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2515	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2516	pPGM->fPhysCacheFlushPending = true;
2517	pgmR3HandlerPhysicalUpdateAll(pVM);
2518
2519	/*
2520	* Change the paging mode.
2521	*/
2522	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2523
2524	/* Restore pVM->pgm.s.GCPhysCR3. */
2525	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2526	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2527	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2528	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2529	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2530	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2531	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2532	else
2533	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2534	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2535
2536	return rc;
2537	}
2538
2539
2540	/**
2541	* Show paging mode.
2542	*
2543	* @param pVM VM Handle.
2544	* @param pHlp The info helpers.
2545	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2546	*/
2547	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2548	{
2549	/* digest argument. */
2550	bool fGuest, fShadow, fHost;
2551	if (pszArgs)
2552	pszArgs = RTStrStripL(pszArgs);
2553	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2554	fShadow = fHost = fGuest = true;
2555	else
2556	{
2557	fShadow = fHost = fGuest = false;
2558	if (strstr(pszArgs, "guest"))
2559	fGuest = true;
2560	if (strstr(pszArgs, "shadow"))
2561	fShadow = true;
2562	if (strstr(pszArgs, "host"))
2563	fHost = true;
2564	}
2565
2566	/* print info. */
2567	if (fGuest)
2568	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2569	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2570	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2571	if (fShadow)
2572	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2573	if (fHost)
2574	{
2575	const char *psz;
2576	switch (pVM->pgm.s.enmHostMode)
2577	{
2578	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2579	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2580	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2581	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2582	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2583	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2584	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2585	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2586	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2587	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2588	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2589	default: psz = "unknown"; break;
2590	}
2591	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2592	}
2593	}
2594
2595
2596	/**
2597	* Dump registered MMIO ranges to the log.
2598	*
2599	* @param pVM VM Handle.
2600	* @param pHlp The info helpers.
2601	* @param pszArgs Arguments, ignored.
2602	*/
2603	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2604	{
2605	NOREF(pszArgs);
2606	pHlp->pfnPrintf(pHlp,
2607	"RAM ranges (pVM=%p)\n"
2608	"%.s %.s\n",
2609	pVM,
2610	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2611	sizeof(RTHCPTR) * 2, "pvHC ");
2612
2613	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2614	pHlp->pfnPrintf(pHlp,
2615	"%RGp-%RGp %RHv %s\n",
2616	pCur->GCPhys,
2617	pCur->GCPhysLast,
2618	pCur->pvR3,
2619	pCur->pszDesc);
2620	}
2621
2622	/**
2623	* Dump the page directory to the log.
2624	*
2625	* @param pVM VM Handle.
2626	* @param pHlp The info helpers.
2627	* @param pszArgs Arguments, ignored.
2628	*/
2629	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2630	{
2631	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2632	/* Big pages supported? */
2633	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2634
2635	/* Global pages supported? */
2636	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2637
2638	NOREF(pszArgs);
2639
2640	/*
2641	* Get page directory addresses.
2642	*/
2643	PX86PD pPDSrc = pVM->pgm.s.pGst32BitPdR3;
2644	Assert(pPDSrc);
2645	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2646
2647	/*
2648	* Iterate the page directory.
2649	*/
2650	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2651	{
2652	X86PDE PdeSrc = pPDSrc->a[iPD];
2653	if (PdeSrc.n.u1Present)
2654	{
2655	if (PdeSrc.b.u1Size && fPSE)
2656	pHlp->pfnPrintf(pHlp,
2657	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2658	iPD,
2659	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2660	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2661	else
2662	pHlp->pfnPrintf(pHlp,
2663	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2664	iPD,
2665	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2666	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2667	}
2668	}
2669	}
2670
2671
2672	/**
2673	* Serivce a VMMCALLHOST_PGM_LOCK call.
2674	*
2675	* @returns VBox status code.
2676	* @param pVM The VM handle.
2677	*/
2678	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2679	{
2680	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2681	AssertRC(rc);
2682	return rc;
2683	}
2684
2685
2686	/**
2687	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2688	*
2689	* @returns PGM_TYPE_*.
2690	* @param pgmMode The mode value to convert.
2691	*/
2692	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2693	{
2694	switch (pgmMode)
2695	{
2696	case PGMMODE_REAL: return PGM_TYPE_REAL;
2697	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2698	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2699	case PGMMODE_PAE:
2700	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2701	case PGMMODE_AMD64:
2702	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2703	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2704	case PGMMODE_EPT: return PGM_TYPE_EPT;
2705	default:
2706	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2707	}
2708	}
2709
2710
2711	/**
2712	* Gets the index into the paging mode data array of a SHW+GST mode.
2713	*
2714	* @returns PGM::paPagingData index.
2715	* @param uShwType The shadow paging mode type.
2716	* @param uGstType The guest paging mode type.
2717	*/
2718	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2719	{
2720	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2721	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2722	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2723	+ (uGstType - PGM_TYPE_REAL);
2724	}
2725
2726
2727	/**
2728	* Gets the index into the paging mode data array of a SHW+GST mode.
2729	*
2730	* @returns PGM::paPagingData index.
2731	* @param enmShw The shadow paging mode.
2732	* @param enmGst The guest paging mode.
2733	*/
2734	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2735	{
2736	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2737	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2738	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2739	}
2740
2741
2742	/**
2743	* Calculates the max data index.
2744	* @returns The number of entries in the paging data array.
2745	*/
2746	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2747	{
2748	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2749	}
2750
2751
2752	/**
2753	* Initializes the paging mode data kept in PGM::paModeData.
2754	*
2755	* @param pVM The VM handle.
2756	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2757	* This is used early in the init process to avoid trouble with PDM
2758	* not being initialized yet.
2759	*/
2760	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2761	{
2762	PPGMMODEDATA pModeData;
2763	int rc;
2764
2765	/*
2766	* Allocate the array on the first call.
2767	*/
2768	if (!pVM->pgm.s.paModeData)
2769	{
2770	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2771	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2772	}
2773
2774	/*
2775	* Initialize the array entries.
2776	*/
2777	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2778	pModeData->uShwType = PGM_TYPE_32BIT;
2779	pModeData->uGstType = PGM_TYPE_REAL;
2780	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2781	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2782	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2783
2784	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2785	pModeData->uShwType = PGM_TYPE_32BIT;
2786	pModeData->uGstType = PGM_TYPE_PROT;
2787	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2788	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2789	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2790
2791	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2792	pModeData->uShwType = PGM_TYPE_32BIT;
2793	pModeData->uGstType = PGM_TYPE_32BIT;
2794	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2795	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2796	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2797
2798	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2799	pModeData->uShwType = PGM_TYPE_PAE;
2800	pModeData->uGstType = PGM_TYPE_REAL;
2801	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2802	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2803	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2804
2805	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2806	pModeData->uShwType = PGM_TYPE_PAE;
2807	pModeData->uGstType = PGM_TYPE_PROT;
2808	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2809	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2810	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2811
2812	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2813	pModeData->uShwType = PGM_TYPE_PAE;
2814	pModeData->uGstType = PGM_TYPE_32BIT;
2815	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2816	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2817	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2818
2819	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2820	pModeData->uShwType = PGM_TYPE_PAE;
2821	pModeData->uGstType = PGM_TYPE_PAE;
2822	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2823	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2824	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2825
2826	#ifdef VBOX_WITH_64_BITS_GUESTS
2827	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2828	pModeData->uShwType = PGM_TYPE_AMD64;
2829	pModeData->uGstType = PGM_TYPE_AMD64;
2830	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2831	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2832	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2833	#endif
2834
2835	/* The nested paging mode. */
2836	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2837	pModeData->uShwType = PGM_TYPE_NESTED;
2838	pModeData->uGstType = PGM_TYPE_REAL;
2839	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2840	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2841
2842	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2843	pModeData->uShwType = PGM_TYPE_NESTED;
2844	pModeData->uGstType = PGM_TYPE_PROT;
2845	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2846	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2847
2848	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2849	pModeData->uShwType = PGM_TYPE_NESTED;
2850	pModeData->uGstType = PGM_TYPE_32BIT;
2851	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2852	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2853
2854	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2855	pModeData->uShwType = PGM_TYPE_NESTED;
2856	pModeData->uGstType = PGM_TYPE_PAE;
2857	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2858	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2859
2860	#ifdef VBOX_WITH_64_BITS_GUESTS
2861	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2862	pModeData->uShwType = PGM_TYPE_NESTED;
2863	pModeData->uGstType = PGM_TYPE_AMD64;
2864	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2865	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2866	#endif
2867
2868	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2869	switch(pVM->pgm.s.enmHostMode)
2870	{
2871	case SUPPAGINGMODE_32_BIT:
2872	case SUPPAGINGMODE_32_BIT_GLOBAL:
2873	#ifdef VBOX_WITH_64_BITS_GUESTS
2874	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2875	#else
2876	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2877	#endif
2878	{
2879	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2880	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2881	}
2882	break;
2883
2884	case SUPPAGINGMODE_PAE:
2885	case SUPPAGINGMODE_PAE_NX:
2886	case SUPPAGINGMODE_PAE_GLOBAL:
2887	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2888	#ifdef VBOX_WITH_64_BITS_GUESTS
2889	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2890	#else
2891	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2892	#endif
2893	{
2894	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2895	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2896	}
2897	break;
2898
2899	case SUPPAGINGMODE_AMD64:
2900	case SUPPAGINGMODE_AMD64_GLOBAL:
2901	case SUPPAGINGMODE_AMD64_NX:
2902	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2903	#ifdef VBOX_WITH_64_BITS_GUESTS
2904	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2905	#else
2906	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2907	#endif
2908	{
2909	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2910	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2911	}
2912	break;
2913	default:
2914	AssertFailed();
2915	break;
2916	}
2917
2918	/* Extended paging (EPT) / Intel VT-x */
2919	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2920	pModeData->uShwType = PGM_TYPE_EPT;
2921	pModeData->uGstType = PGM_TYPE_REAL;
2922	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2923	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2924	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2925
2926	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2927	pModeData->uShwType = PGM_TYPE_EPT;
2928	pModeData->uGstType = PGM_TYPE_PROT;
2929	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2930	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2931	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2932
2933	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2934	pModeData->uShwType = PGM_TYPE_EPT;
2935	pModeData->uGstType = PGM_TYPE_32BIT;
2936	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2937	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2938	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2939
2940	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2941	pModeData->uShwType = PGM_TYPE_EPT;
2942	pModeData->uGstType = PGM_TYPE_PAE;
2943	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2944	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2945	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2946
2947	#ifdef VBOX_WITH_64_BITS_GUESTS
2948	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2949	pModeData->uShwType = PGM_TYPE_EPT;
2950	pModeData->uGstType = PGM_TYPE_AMD64;
2951	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2952	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2953	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2954	#endif
2955	return VINF_SUCCESS;
2956	}
2957
2958
2959	/**
2960	* Switch to different (or relocated in the relocate case) mode data.
2961	*
2962	* @param pVM The VM handle.
2963	* @param enmShw The the shadow paging mode.
2964	* @param enmGst The the guest paging mode.
2965	*/
2966	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2967	{
2968	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2969
2970	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2971	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2972
2973	/* shadow */
2974	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2975	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2976	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2977	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2978	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2979
2980	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2981	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2982
2983	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2984	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2985
2986
2987	/* guest */
2988	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2989	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2990	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2991	Assert(pVM->pgm.s.pfnR3GstGetPage);
2992	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2993	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2994	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2995	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2996	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2997	#endif
2998	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2999	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
3000	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3001	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
3002	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
3003	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
3004	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
3005	#endif
3006	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3007	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3008	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3009	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3010	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
3011	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
3012	#endif
3013	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
3014	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
3015	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3016	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
3017	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
3018	#endif
3019	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3020	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3021	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3022	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3023	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
3024	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
3025	#endif
3026	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
3027	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
3028	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3029	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
3030	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
3031	#endif
3032
3033	/* both */
3034	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3035	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3036	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3037	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3038	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3039	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3040	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3041	#ifdef VBOX_STRICT
3042	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3043	#endif
3044
3045	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3046	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3047	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3048	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3049	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3050	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3051	#ifdef VBOX_STRICT
3052	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3053	#endif
3054
3055	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3056	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3057	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3058	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3059	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3060	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3061	#ifdef VBOX_STRICT
3062	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3063	#endif
3064	}
3065
3066
3067	/**
3068	* Calculates the shadow paging mode.
3069	*
3070	* @returns The shadow paging mode.
3071	* @param pVM VM handle.
3072	* @param enmGuestMode The guest mode.
3073	* @param enmHostMode The host mode.
3074	* @param enmShadowMode The current shadow mode.
3075	* @param penmSwitcher Where to store the switcher to use.
3076	* VMMSWITCHER_INVALID means no change.
3077	*/
3078	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3079	{
3080	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3081	switch (enmGuestMode)
3082	{
3083	/*
3084	* When switching to real or protected mode we don't change
3085	* anything since it's likely that we'll switch back pretty soon.
3086	*
3087	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3088	* and is supposed to determine which shadow paging and switcher to
3089	* use during init.
3090	*/
3091	case PGMMODE_REAL:
3092	case PGMMODE_PROTECTED:
3093	if ( enmShadowMode != PGMMODE_INVALID
3094	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3095	break; /* (no change) */
3096
3097	switch (enmHostMode)
3098	{
3099	case SUPPAGINGMODE_32_BIT:
3100	case SUPPAGINGMODE_32_BIT_GLOBAL:
3101	enmShadowMode = PGMMODE_32_BIT;
3102	enmSwitcher = VMMSWITCHER_32_TO_32;
3103	break;
3104
3105	case SUPPAGINGMODE_PAE:
3106	case SUPPAGINGMODE_PAE_NX:
3107	case SUPPAGINGMODE_PAE_GLOBAL:
3108	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3109	enmShadowMode = PGMMODE_PAE;
3110	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3111	#ifdef DEBUG_bird
3112	if (RTEnvExist("VBOX_32BIT"))
3113	{
3114	enmShadowMode = PGMMODE_32_BIT;
3115	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3116	}
3117	#endif
3118	break;
3119
3120	case SUPPAGINGMODE_AMD64:
3121	case SUPPAGINGMODE_AMD64_GLOBAL:
3122	case SUPPAGINGMODE_AMD64_NX:
3123	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3124	enmShadowMode = PGMMODE_PAE;
3125	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3126	#ifdef DEBUG_bird
3127	if (RTEnvExist("VBOX_32BIT"))
3128	{
3129	enmShadowMode = PGMMODE_32_BIT;
3130	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3131	}
3132	#endif
3133	break;
3134
3135	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3136	}
3137	break;
3138
3139	case PGMMODE_32_BIT:
3140	switch (enmHostMode)
3141	{
3142	case SUPPAGINGMODE_32_BIT:
3143	case SUPPAGINGMODE_32_BIT_GLOBAL:
3144	enmShadowMode = PGMMODE_32_BIT;
3145	enmSwitcher = VMMSWITCHER_32_TO_32;
3146	break;
3147
3148	case SUPPAGINGMODE_PAE:
3149	case SUPPAGINGMODE_PAE_NX:
3150	case SUPPAGINGMODE_PAE_GLOBAL:
3151	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3152	enmShadowMode = PGMMODE_PAE;
3153	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3154	#ifdef DEBUG_bird
3155	if (RTEnvExist("VBOX_32BIT"))
3156	{
3157	enmShadowMode = PGMMODE_32_BIT;
3158	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3159	}
3160	#endif
3161	break;
3162
3163	case SUPPAGINGMODE_AMD64:
3164	case SUPPAGINGMODE_AMD64_GLOBAL:
3165	case SUPPAGINGMODE_AMD64_NX:
3166	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3167	enmShadowMode = PGMMODE_PAE;
3168	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3169	#ifdef DEBUG_bird
3170	if (RTEnvExist("VBOX_32BIT"))
3171	{
3172	enmShadowMode = PGMMODE_32_BIT;
3173	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3174	}
3175	#endif
3176	break;
3177
3178	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3179	}
3180	break;
3181
3182	case PGMMODE_PAE:
3183	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3184	switch (enmHostMode)
3185	{
3186	case SUPPAGINGMODE_32_BIT:
3187	case SUPPAGINGMODE_32_BIT_GLOBAL:
3188	enmShadowMode = PGMMODE_PAE;
3189	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3190	break;
3191
3192	case SUPPAGINGMODE_PAE:
3193	case SUPPAGINGMODE_PAE_NX:
3194	case SUPPAGINGMODE_PAE_GLOBAL:
3195	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3196	enmShadowMode = PGMMODE_PAE;
3197	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3198	break;
3199
3200	case SUPPAGINGMODE_AMD64:
3201	case SUPPAGINGMODE_AMD64_GLOBAL:
3202	case SUPPAGINGMODE_AMD64_NX:
3203	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3204	enmShadowMode = PGMMODE_PAE;
3205	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3206	break;
3207
3208	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3209	}
3210	break;
3211
3212	case PGMMODE_AMD64:
3213	case PGMMODE_AMD64_NX:
3214	switch (enmHostMode)
3215	{
3216	case SUPPAGINGMODE_32_BIT:
3217	case SUPPAGINGMODE_32_BIT_GLOBAL:
3218	enmShadowMode = PGMMODE_PAE;
3219	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3220	break;
3221
3222	case SUPPAGINGMODE_PAE:
3223	case SUPPAGINGMODE_PAE_NX:
3224	case SUPPAGINGMODE_PAE_GLOBAL:
3225	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3226	enmShadowMode = PGMMODE_PAE;
3227	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3228	break;
3229
3230	case SUPPAGINGMODE_AMD64:
3231	case SUPPAGINGMODE_AMD64_GLOBAL:
3232	case SUPPAGINGMODE_AMD64_NX:
3233	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3234	enmShadowMode = PGMMODE_AMD64;
3235	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3236	break;
3237
3238	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3239	}
3240	break;
3241
3242
3243	default:
3244	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3245	return PGMMODE_INVALID;
3246	}
3247	/* Override the shadow mode is nested paging is active. */
3248	if (HWACCMIsNestedPagingActive(pVM))
3249	enmShadowMode = HWACCMGetPagingMode(pVM);
3250
3251	*penmSwitcher = enmSwitcher;
3252	return enmShadowMode;
3253	}
3254
3255
3256	/**
3257	* Performs the actual mode change.
3258	* This is called by PGMChangeMode and pgmR3InitPaging().
3259	*
3260	* @returns VBox status code.
3261	* @param pVM VM handle.
3262	* @param enmGuestMode The new guest mode. This is assumed to be different from
3263	* the current mode.
3264	*/
3265	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3266	{
3267	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3268	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3269
3270	/*
3271	* Calc the shadow mode and switcher.
3272	*/
3273	VMMSWITCHER enmSwitcher;
3274	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3275	if (enmSwitcher != VMMSWITCHER_INVALID)
3276	{
3277	/*
3278	* Select new switcher.
3279	*/
3280	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3281	if (RT_FAILURE(rc))
3282	{
3283	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3284	return rc;
3285	}
3286	}
3287
3288	/*
3289	* Exit old mode(s).
3290	*/
3291	/* shadow */
3292	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3293	{
3294	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3295	if (PGM_SHW_PFN(Exit, pVM))
3296	{
3297	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3298	if (RT_FAILURE(rc))
3299	{
3300	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3301	return rc;
3302	}
3303	}
3304
3305	}
3306	else
3307	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3308
3309	/* guest */
3310	if (PGM_GST_PFN(Exit, pVM))
3311	{
3312	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3313	if (RT_FAILURE(rc))
3314	{
3315	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3316	return rc;
3317	}
3318	}
3319
3320	/*
3321	* Load new paging mode data.
3322	*/
3323	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3324
3325	/*
3326	* Enter new shadow mode (if changed).
3327	*/
3328	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3329	{
3330	int rc;
3331	pVM->pgm.s.enmShadowMode = enmShadowMode;
3332	switch (enmShadowMode)
3333	{
3334	case PGMMODE_32_BIT:
3335	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3336	break;
3337	case PGMMODE_PAE:
3338	case PGMMODE_PAE_NX:
3339	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3340	break;
3341	case PGMMODE_AMD64:
3342	case PGMMODE_AMD64_NX:
3343	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3344	break;
3345	case PGMMODE_NESTED:
3346	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3347	break;
3348	case PGMMODE_EPT:
3349	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3350	break;
3351	case PGMMODE_REAL:
3352	case PGMMODE_PROTECTED:
3353	default:
3354	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3355	return VERR_INTERNAL_ERROR;
3356	}
3357	if (RT_FAILURE(rc))
3358	{
3359	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3360	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3361	return rc;
3362	}
3363	}
3364
3365	/** @todo This is a bug!
3366	*
3367	* We must flush the PGM pool cache if the guest mode changes; we don't always
3368	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3369	* the shadow page tables.
3370	*
3371	* That only applies when switching between paging and non-paging modes.
3372	*/
3373	/** @todo A20 setting */
3374	if ( pVM->pgm.s.CTX_SUFF(pPool)
3375	&& !HWACCMIsNestedPagingActive(pVM)
3376	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3377	{
3378	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3379	pgmPoolFlushAll(pVM);
3380	}
3381
3382	/*
3383	* Enter the new guest and shadow+guest modes.
3384	*/
3385	int rc = -1;
3386	int rc2 = -1;
3387	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3388	pVM->pgm.s.enmGuestMode = enmGuestMode;
3389	switch (enmGuestMode)
3390	{
3391	case PGMMODE_REAL:
3392	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3393	switch (pVM->pgm.s.enmShadowMode)
3394	{
3395	case PGMMODE_32_BIT:
3396	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3397	break;
3398	case PGMMODE_PAE:
3399	case PGMMODE_PAE_NX:
3400	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3401	break;
3402	case PGMMODE_NESTED:
3403	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3404	break;
3405	case PGMMODE_EPT:
3406	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3407	break;
3408	case PGMMODE_AMD64:
3409	case PGMMODE_AMD64_NX:
3410	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3411	default: AssertFailed(); break;
3412	}
3413	break;
3414
3415	case PGMMODE_PROTECTED:
3416	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3417	switch (pVM->pgm.s.enmShadowMode)
3418	{
3419	case PGMMODE_32_BIT:
3420	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3421	break;
3422	case PGMMODE_PAE:
3423	case PGMMODE_PAE_NX:
3424	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3425	break;
3426	case PGMMODE_NESTED:
3427	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3428	break;
3429	case PGMMODE_EPT:
3430	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3431	break;
3432	case PGMMODE_AMD64:
3433	case PGMMODE_AMD64_NX:
3434	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3435	default: AssertFailed(); break;
3436	}
3437	break;
3438
3439	case PGMMODE_32_BIT:
3440	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3441	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3442	switch (pVM->pgm.s.enmShadowMode)
3443	{
3444	case PGMMODE_32_BIT:
3445	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3446	break;
3447	case PGMMODE_PAE:
3448	case PGMMODE_PAE_NX:
3449	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3450	break;
3451	case PGMMODE_NESTED:
3452	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3453	break;
3454	case PGMMODE_EPT:
3455	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3456	break;
3457	case PGMMODE_AMD64:
3458	case PGMMODE_AMD64_NX:
3459	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3460	default: AssertFailed(); break;
3461	}
3462	break;
3463
3464	case PGMMODE_PAE_NX:
3465	case PGMMODE_PAE:
3466	{
3467	uint32_t u32Dummy, u32Features;
3468
3469	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3470	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3471	{
3472	/* Pause first, then inform Main. */
3473	rc = VMR3SuspendNoSave(pVM);
3474	AssertRC(rc);
3475
3476	VMSetRuntimeError(pVM, true, "PAEmode",
3477	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3478	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3479	return VINF_SUCCESS;
3480	}
3481	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3482	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3483	switch (pVM->pgm.s.enmShadowMode)
3484	{
3485	case PGMMODE_PAE:
3486	case PGMMODE_PAE_NX:
3487	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3488	break;
3489	case PGMMODE_NESTED:
3490	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3491	break;
3492	case PGMMODE_EPT:
3493	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3494	break;
3495	case PGMMODE_32_BIT:
3496	case PGMMODE_AMD64:
3497	case PGMMODE_AMD64_NX:
3498	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3499	default: AssertFailed(); break;
3500	}
3501	break;
3502	}
3503
3504	#ifdef VBOX_WITH_64_BITS_GUESTS
3505	case PGMMODE_AMD64_NX:
3506	case PGMMODE_AMD64:
3507	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3508	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3509	switch (pVM->pgm.s.enmShadowMode)
3510	{
3511	case PGMMODE_AMD64:
3512	case PGMMODE_AMD64_NX:
3513	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3514	break;
3515	case PGMMODE_NESTED:
3516	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3517	break;
3518	case PGMMODE_EPT:
3519	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3520	break;
3521	case PGMMODE_32_BIT:
3522	case PGMMODE_PAE:
3523	case PGMMODE_PAE_NX:
3524	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3525	default: AssertFailed(); break;
3526	}
3527	break;
3528	#endif
3529
3530	default:
3531	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3532	rc = VERR_NOT_IMPLEMENTED;
3533	break;
3534	}
3535
3536	/* status codes. */
3537	AssertRC(rc);
3538	AssertRC(rc2);
3539	if (RT_SUCCESS(rc))
3540	{
3541	rc = rc2;
3542	if (RT_SUCCESS(rc)) /* no informational status codes. */
3543	rc = VINF_SUCCESS;
3544	}
3545
3546	/*
3547	* Notify SELM so it can update the TSSes with correct CR3s.
3548	*/
3549	SELMR3PagingModeChanged(pVM);
3550
3551	/* Notify HWACCM as well. */
3552	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3553	return rc;
3554	}
3555
3556
3557	/**
3558	* Dumps a PAE shadow page table.
3559	*
3560	* @returns VBox status code (VINF_SUCCESS).
3561	* @param pVM The VM handle.
3562	* @param pPT Pointer to the page table.
3563	* @param u64Address The virtual address of the page table starts.
3564	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3565	* @param cMaxDepth The maxium depth.
3566	* @param pHlp Pointer to the output functions.
3567	*/
3568	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3569	{
3570	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3571	{
3572	X86PTEPAE Pte = pPT->a[i];
3573	if (Pte.n.u1Present)
3574	{
3575	pHlp->pfnPrintf(pHlp,
3576	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3577	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3578	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3579	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3580	Pte.n.u1Write ? 'W' : 'R',
3581	Pte.n.u1User ? 'U' : 'S',
3582	Pte.n.u1Accessed ? 'A' : '-',
3583	Pte.n.u1Dirty ? 'D' : '-',
3584	Pte.n.u1Global ? 'G' : '-',
3585	Pte.n.u1WriteThru ? "WT" : "--",
3586	Pte.n.u1CacheDisable? "CD" : "--",
3587	Pte.n.u1PAT ? "AT" : "--",
3588	Pte.n.u1NoExecute ? "NX" : "--",
3589	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3590	Pte.u & RT_BIT(10) ? '1' : '0',
3591	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3592	Pte.u & X86_PTE_PAE_PG_MASK);
3593	}
3594	}
3595	return VINF_SUCCESS;
3596	}
3597
3598
3599	/**
3600	* Dumps a PAE shadow page directory table.
3601	*
3602	* @returns VBox status code (VINF_SUCCESS).
3603	* @param pVM The VM handle.
3604	* @param HCPhys The physical address of the page directory table.
3605	* @param u64Address The virtual address of the page table starts.
3606	* @param cr4 The CR4, PSE is currently used.
3607	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3608	* @param cMaxDepth The maxium depth.
3609	* @param pHlp Pointer to the output functions.
3610	*/
3611	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3612	{
3613	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3614	if (!pPD)
3615	{
3616	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3617	fLongMode ? 16 : 8, u64Address, HCPhys);
3618	return VERR_INVALID_PARAMETER;
3619	}
3620	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3621
3622	int rc = VINF_SUCCESS;
3623	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3624	{
3625	X86PDEPAE Pde = pPD->a[i];
3626	if (Pde.n.u1Present)
3627	{
3628	if (fBigPagesSupported && Pde.b.u1Size)
3629	pHlp->pfnPrintf(pHlp,
3630	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3631	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3632	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3633	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3634	Pde.b.u1Write ? 'W' : 'R',
3635	Pde.b.u1User ? 'U' : 'S',
3636	Pde.b.u1Accessed ? 'A' : '-',
3637	Pde.b.u1Dirty ? 'D' : '-',
3638	Pde.b.u1Global ? 'G' : '-',
3639	Pde.b.u1WriteThru ? "WT" : "--",
3640	Pde.b.u1CacheDisable? "CD" : "--",
3641	Pde.b.u1PAT ? "AT" : "--",
3642	Pde.b.u1NoExecute ? "NX" : "--",
3643	Pde.u & RT_BIT_64(9) ? '1' : '0',
3644	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3645	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3646	Pde.u & X86_PDE_PAE_PG_MASK);
3647	else
3648	{
3649	pHlp->pfnPrintf(pHlp,
3650	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3651	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3652	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3653	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3654	Pde.n.u1Write ? 'W' : 'R',
3655	Pde.n.u1User ? 'U' : 'S',
3656	Pde.n.u1Accessed ? 'A' : '-',
3657	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3658	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3659	Pde.n.u1WriteThru ? "WT" : "--",
3660	Pde.n.u1CacheDisable? "CD" : "--",
3661	Pde.n.u1NoExecute ? "NX" : "--",
3662	Pde.u & RT_BIT_64(9) ? '1' : '0',
3663	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3664	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3665	Pde.u & X86_PDE_PAE_PG_MASK);
3666	if (cMaxDepth >= 1)
3667	{
3668	/** @todo what about using the page pool for mapping PTs? */
3669	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3670	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3671	PX86PTPAE pPT = NULL;
3672	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3673	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3674	else
3675	{
3676	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3677	{
3678	uint64_t off = u64AddressPT - pMap->GCPtr;
3679	if (off < pMap->cb)
3680	{
3681	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3682	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3683	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3684	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3685	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3686	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3687	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3688	}
3689	}
3690	}
3691	int rc2 = VERR_INVALID_PARAMETER;
3692	if (pPT)
3693	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3694	else
3695	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3696	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3697	if (rc2 < rc && RT_SUCCESS(rc))
3698	rc = rc2;
3699	}
3700	}
3701	}
3702	}
3703	return rc;
3704	}
3705
3706
3707	/**
3708	* Dumps a PAE shadow page directory pointer table.
3709	*
3710	* @returns VBox status code (VINF_SUCCESS).
3711	* @param pVM The VM handle.
3712	* @param HCPhys The physical address of the page directory pointer table.
3713	* @param u64Address The virtual address of the page table starts.
3714	* @param cr4 The CR4, PSE is currently used.
3715	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3716	* @param cMaxDepth The maxium depth.
3717	* @param pHlp Pointer to the output functions.
3718	*/
3719	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3720	{
3721	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3722	if (!pPDPT)
3723	{
3724	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3725	fLongMode ? 16 : 8, u64Address, HCPhys);
3726	return VERR_INVALID_PARAMETER;
3727	}
3728
3729	int rc = VINF_SUCCESS;
3730	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3731	for (unsigned i = 0; i < c; i++)
3732	{
3733	X86PDPE Pdpe = pPDPT->a[i];
3734	if (Pdpe.n.u1Present)
3735	{
3736	if (fLongMode)
3737	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3738	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3739	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3740	Pdpe.lm.u1Write ? 'W' : 'R',
3741	Pdpe.lm.u1User ? 'U' : 'S',
3742	Pdpe.lm.u1Accessed ? 'A' : '-',
3743	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3744	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3745	Pdpe.lm.u1WriteThru ? "WT" : "--",
3746	Pdpe.lm.u1CacheDisable? "CD" : "--",
3747	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3748	Pdpe.lm.u1NoExecute ? "NX" : "--",
3749	Pdpe.u & RT_BIT(9) ? '1' : '0',
3750	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3751	Pdpe.u & RT_BIT(11) ? '1' : '0',
3752	Pdpe.u & X86_PDPE_PG_MASK);
3753	else
3754	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3755	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3756	i << X86_PDPT_SHIFT,
3757	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3758	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3759	Pdpe.n.u1WriteThru ? "WT" : "--",
3760	Pdpe.n.u1CacheDisable? "CD" : "--",
3761	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3762	Pdpe.u & RT_BIT(9) ? '1' : '0',
3763	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3764	Pdpe.u & RT_BIT(11) ? '1' : '0',
3765	Pdpe.u & X86_PDPE_PG_MASK);
3766	if (cMaxDepth >= 1)
3767	{
3768	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3769	cr4, fLongMode, cMaxDepth - 1, pHlp);
3770	if (rc2 < rc && RT_SUCCESS(rc))
3771	rc = rc2;
3772	}
3773	}
3774	}
3775	return rc;
3776	}
3777
3778
3779	/**
3780	* Dumps a 32-bit shadow page table.
3781	*
3782	* @returns VBox status code (VINF_SUCCESS).
3783	* @param pVM The VM handle.
3784	* @param HCPhys The physical address of the table.
3785	* @param cr4 The CR4, PSE is currently used.
3786	* @param cMaxDepth The maxium depth.
3787	* @param pHlp Pointer to the output functions.
3788	*/
3789	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3790	{
3791	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3792	if (!pPML4)
3793	{
3794	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3795	return VERR_INVALID_PARAMETER;
3796	}
3797
3798	int rc = VINF_SUCCESS;
3799	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3800	{
3801	X86PML4E Pml4e = pPML4->a[i];
3802	if (Pml4e.n.u1Present)
3803	{
3804	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3805	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3806	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3807	u64Address,
3808	Pml4e.n.u1Write ? 'W' : 'R',
3809	Pml4e.n.u1User ? 'U' : 'S',
3810	Pml4e.n.u1Accessed ? 'A' : '-',
3811	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3812	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3813	Pml4e.n.u1WriteThru ? "WT" : "--",
3814	Pml4e.n.u1CacheDisable? "CD" : "--",
3815	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3816	Pml4e.n.u1NoExecute ? "NX" : "--",
3817	Pml4e.u & RT_BIT(9) ? '1' : '0',
3818	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3819	Pml4e.u & RT_BIT(11) ? '1' : '0',
3820	Pml4e.u & X86_PML4E_PG_MASK);
3821
3822	if (cMaxDepth >= 1)
3823	{
3824	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3825	if (rc2 < rc && RT_SUCCESS(rc))
3826	rc = rc2;
3827	}
3828	}
3829	}
3830	return rc;
3831	}
3832
3833
3834	/**
3835	* Dumps a 32-bit shadow page table.
3836	*
3837	* @returns VBox status code (VINF_SUCCESS).
3838	* @param pVM The VM handle.
3839	* @param pPT Pointer to the page table.
3840	* @param u32Address The virtual address this table starts at.
3841	* @param pHlp Pointer to the output functions.
3842	*/
3843	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3844	{
3845	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3846	{
3847	X86PTE Pte = pPT->a[i];
3848	if (Pte.n.u1Present)
3849	{
3850	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3851	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3852	u32Address + (i << X86_PT_SHIFT),
3853	Pte.n.u1Write ? 'W' : 'R',
3854	Pte.n.u1User ? 'U' : 'S',
3855	Pte.n.u1Accessed ? 'A' : '-',
3856	Pte.n.u1Dirty ? 'D' : '-',
3857	Pte.n.u1Global ? 'G' : '-',
3858	Pte.n.u1WriteThru ? "WT" : "--",
3859	Pte.n.u1CacheDisable? "CD" : "--",
3860	Pte.n.u1PAT ? "AT" : "--",
3861	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3862	Pte.u & RT_BIT(10) ? '1' : '0',
3863	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3864	Pte.u & X86_PDE_PG_MASK);
3865	}
3866	}
3867	return VINF_SUCCESS;
3868	}
3869
3870
3871	/**
3872	* Dumps a 32-bit shadow page directory and page tables.
3873	*
3874	* @returns VBox status code (VINF_SUCCESS).
3875	* @param pVM The VM handle.
3876	* @param cr3 The root of the hierarchy.
3877	* @param cr4 The CR4, PSE is currently used.
3878	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3879	* @param pHlp Pointer to the output functions.
3880	*/
3881	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3882	{
3883	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3884	if (!pPD)
3885	{
3886	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3887	return VERR_INVALID_PARAMETER;
3888	}
3889
3890	int rc = VINF_SUCCESS;
3891	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3892	{
3893	X86PDE Pde = pPD->a[i];
3894	if (Pde.n.u1Present)
3895	{
3896	const uint32_t u32Address = i << X86_PD_SHIFT;
3897	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3898	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3899	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3900	u32Address,
3901	Pde.b.u1Write ? 'W' : 'R',
3902	Pde.b.u1User ? 'U' : 'S',
3903	Pde.b.u1Accessed ? 'A' : '-',
3904	Pde.b.u1Dirty ? 'D' : '-',
3905	Pde.b.u1Global ? 'G' : '-',
3906	Pde.b.u1WriteThru ? "WT" : "--",
3907	Pde.b.u1CacheDisable? "CD" : "--",
3908	Pde.b.u1PAT ? "AT" : "--",
3909	Pde.u & RT_BIT_64(9) ? '1' : '0',
3910	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3911	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3912	Pde.u & X86_PDE4M_PG_MASK);
3913	else
3914	{
3915	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3916	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3917	u32Address,
3918	Pde.n.u1Write ? 'W' : 'R',
3919	Pde.n.u1User ? 'U' : 'S',
3920	Pde.n.u1Accessed ? 'A' : '-',
3921	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3922	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3923	Pde.n.u1WriteThru ? "WT" : "--",
3924	Pde.n.u1CacheDisable? "CD" : "--",
3925	Pde.u & RT_BIT_64(9) ? '1' : '0',
3926	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3927	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3928	Pde.u & X86_PDE_PG_MASK);
3929	if (cMaxDepth >= 1)
3930	{
3931	/** @todo what about using the page pool for mapping PTs? */
3932	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3933	PX86PT pPT = NULL;
3934	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3935	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3936	else
3937	{
3938	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3939	if (u32Address - pMap->GCPtr < pMap->cb)
3940	{
3941	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3942	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3943	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3944	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3945	pPT = pMap->aPTs[iPDE].pPTR3;
3946	}
3947	}
3948	int rc2 = VERR_INVALID_PARAMETER;
3949	if (pPT)
3950	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3951	else
3952	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3953	if (rc2 < rc && RT_SUCCESS(rc))
3954	rc = rc2;
3955	}
3956	}
3957	}
3958	}
3959
3960	return rc;
3961	}
3962
3963
3964	/**
3965	* Dumps a 32-bit shadow page table.
3966	*
3967	* @returns VBox status code (VINF_SUCCESS).
3968	* @param pVM The VM handle.
3969	* @param pPT Pointer to the page table.
3970	* @param u32Address The virtual address this table starts at.
3971	* @param PhysSearch Address to search for.
3972	*/
3973	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3974	{
3975	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3976	{
3977	X86PTE Pte = pPT->a[i];
3978	if (Pte.n.u1Present)
3979	{
3980	Log(( /P R S A D G WT CD AT NX 4M a m d /
3981	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3982	u32Address + (i << X86_PT_SHIFT),
3983	Pte.n.u1Write ? 'W' : 'R',
3984	Pte.n.u1User ? 'U' : 'S',
3985	Pte.n.u1Accessed ? 'A' : '-',
3986	Pte.n.u1Dirty ? 'D' : '-',
3987	Pte.n.u1Global ? 'G' : '-',
3988	Pte.n.u1WriteThru ? "WT" : "--",
3989	Pte.n.u1CacheDisable? "CD" : "--",
3990	Pte.n.u1PAT ? "AT" : "--",
3991	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3992	Pte.u & RT_BIT(10) ? '1' : '0',
3993	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3994	Pte.u & X86_PDE_PG_MASK));
3995
3996	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3997	{
3998	uint64_t fPageShw = 0;
3999	RTHCPHYS pPhysHC = 0;
4000
4001	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4002	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4003	}
4004	}
4005	}
4006	return VINF_SUCCESS;
4007	}
4008
4009
4010	/**
4011	* Dumps a 32-bit guest page directory and page tables.
4012	*
4013	* @returns VBox status code (VINF_SUCCESS).
4014	* @param pVM The VM handle.
4015	* @param cr3 The root of the hierarchy.
4016	* @param cr4 The CR4, PSE is currently used.
4017	* @param PhysSearch Address to search for.
4018	*/
4019	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4020	{
4021	bool fLongMode = false;
4022	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4023	PX86PD pPD = 0;
4024
4025	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4026	if (RT_FAILURE(rc) \|\| !pPD)
4027	{
4028	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4029	return VERR_INVALID_PARAMETER;
4030	}
4031
4032	Log(("cr3=%08x cr4=%08x%s\n"
4033	"%-*s P - Present\n"
4034	"%-*s \| R/W - Read (0) / Write (1)\n"
4035	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4036	"%-*s \| \| \| A - Accessed\n"
4037	"%-*s \| \| \| \| D - Dirty\n"
4038	"%-*s \| \| \| \| \| G - Global\n"
4039	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4040	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4041	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4042	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4043	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4044	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4045	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4046	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4047	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4048	- W U - - - -- -- -- -- -- 010 */
4049	, cr3, cr4, fLongMode ? " Long Mode" : "",
4050	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4051	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4052
4053	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4054	{
4055	X86PDE Pde = pPD->a[i];
4056	if (Pde.n.u1Present)
4057	{
4058	const uint32_t u32Address = i << X86_PD_SHIFT;
4059
4060	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4061	Log(( /P R S A D G WT CD AT NX 4M a m d /
4062	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4063	u32Address,
4064	Pde.b.u1Write ? 'W' : 'R',
4065	Pde.b.u1User ? 'U' : 'S',
4066	Pde.b.u1Accessed ? 'A' : '-',
4067	Pde.b.u1Dirty ? 'D' : '-',
4068	Pde.b.u1Global ? 'G' : '-',
4069	Pde.b.u1WriteThru ? "WT" : "--",
4070	Pde.b.u1CacheDisable? "CD" : "--",
4071	Pde.b.u1PAT ? "AT" : "--",
4072	Pde.u & RT_BIT(9) ? '1' : '0',
4073	Pde.u & RT_BIT(10) ? '1' : '0',
4074	Pde.u & RT_BIT(11) ? '1' : '0',
4075	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4076	/** @todo PhysSearch */
4077	else
4078	{
4079	Log(( /P R S A D G WT CD AT NX 4M a m d /
4080	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4081	u32Address,
4082	Pde.n.u1Write ? 'W' : 'R',
4083	Pde.n.u1User ? 'U' : 'S',
4084	Pde.n.u1Accessed ? 'A' : '-',
4085	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4086	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4087	Pde.n.u1WriteThru ? "WT" : "--",
4088	Pde.n.u1CacheDisable? "CD" : "--",
4089	Pde.u & RT_BIT(9) ? '1' : '0',
4090	Pde.u & RT_BIT(10) ? '1' : '0',
4091	Pde.u & RT_BIT(11) ? '1' : '0',
4092	Pde.u & X86_PDE_PG_MASK));
4093	////if (cMaxDepth >= 1)
4094	{
4095	/** @todo what about using the page pool for mapping PTs? */
4096	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4097	PX86PT pPT = NULL;
4098
4099	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4100
4101	int rc2 = VERR_INVALID_PARAMETER;
4102	if (pPT)
4103	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4104	else
4105	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4106	if (rc2 < rc && RT_SUCCESS(rc))
4107	rc = rc2;
4108	}
4109	}
4110	}
4111	}
4112
4113	return rc;
4114	}
4115
4116
4117	/**
4118	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4119	*
4120	* @returns VBox status code (VINF_SUCCESS).
4121	* @param pVM The VM handle.
4122	* @param cr3 The root of the hierarchy.
4123	* @param cr4 The cr4, only PAE and PSE is currently used.
4124	* @param fLongMode Set if long mode, false if not long mode.
4125	* @param cMaxDepth Number of levels to dump.
4126	* @param pHlp Pointer to the output functions.
4127	*/
4128	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4129	{
4130	if (!pHlp)
4131	pHlp = DBGFR3InfoLogHlp();
4132	if (!cMaxDepth)
4133	return VINF_SUCCESS;
4134	const unsigned cch = fLongMode ? 16 : 8;
4135	pHlp->pfnPrintf(pHlp,
4136	"cr3=%08x cr4=%08x%s\n"
4137	"%-*s P - Present\n"
4138	"%-*s \| R/W - Read (0) / Write (1)\n"
4139	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4140	"%-*s \| \| \| A - Accessed\n"
4141	"%-*s \| \| \| \| D - Dirty\n"
4142	"%-*s \| \| \| \| \| G - Global\n"
4143	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4144	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4145	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4146	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4147	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4148	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4149	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4150	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4151	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4152	- W U - - - -- -- -- -- -- 010 */
4153	, cr3, cr4, fLongMode ? " Long Mode" : "",
4154	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4155	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4156	if (cr4 & X86_CR4_PAE)
4157	{
4158	if (fLongMode)
4159	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4160	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4161	}
4162	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4163	}
4164
4165	#ifdef VBOX_WITH_DEBUGGER
4166
4167	/**
4168	* The '.pgmram' command.
4169	*
4170	* @returns VBox status.
4171	* @param pCmd Pointer to the command descriptor (as registered).
4172	* @param pCmdHlp Pointer to command helper functions.
4173	* @param pVM Pointer to the current VM (if any).
4174	* @param paArgs Pointer to (readonly) array of arguments.
4175	* @param cArgs Number of arguments in the array.
4176	*/
4177	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4178	{
4179	/*
4180	* Validate input.
4181	*/
4182	if (!pVM)
4183	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4184	if (!pVM->pgm.s.pRamRangesRC)
4185	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4186
4187	/*
4188	* Dump the ranges.
4189	*/
4190	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4191	PPGMRAMRANGE pRam;
4192	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4193	{
4194	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4195	"%RGp - %RGp %p\n",
4196	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4197	if (RT_FAILURE(rc))
4198	return rc;
4199	}
4200
4201	return VINF_SUCCESS;
4202	}
4203
4204
4205	/**
4206	* The '.pgmmap' command.
4207	*
4208	* @returns VBox status.
4209	* @param pCmd Pointer to the command descriptor (as registered).
4210	* @param pCmdHlp Pointer to command helper functions.
4211	* @param pVM Pointer to the current VM (if any).
4212	* @param paArgs Pointer to (readonly) array of arguments.
4213	* @param cArgs Number of arguments in the array.
4214	*/
4215	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4216	{
4217	/*
4218	* Validate input.
4219	*/
4220	if (!pVM)
4221	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4222	if (!pVM->pgm.s.pMappingsR3)
4223	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4224
4225	/*
4226	* Print message about the fixedness of the mappings.
4227	*/
4228	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4229	if (RT_FAILURE(rc))
4230	return rc;
4231
4232	/*
4233	* Dump the ranges.
4234	*/
4235	PPGMMAPPING pCur;
4236	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4237	{
4238	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4239	"%08x - %08x %s\n",
4240	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4241	if (RT_FAILURE(rc))
4242	return rc;
4243	}
4244
4245	return VINF_SUCCESS;
4246	}
4247
4248
4249	/**
4250	* The '.pgmsync' command.
4251	*
4252	* @returns VBox status.
4253	* @param pCmd Pointer to the command descriptor (as registered).
4254	* @param pCmdHlp Pointer to command helper functions.
4255	* @param pVM Pointer to the current VM (if any).
4256	* @param paArgs Pointer to (readonly) array of arguments.
4257	* @param cArgs Number of arguments in the array.
4258	*/
4259	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4260	{
4261	/*
4262	* Validate input.
4263	*/
4264	if (!pVM)
4265	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4266
4267	/*
4268	* Force page directory sync.
4269	*/
4270	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4271
4272	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4273	if (RT_FAILURE(rc))
4274	return rc;
4275
4276	return VINF_SUCCESS;
4277	}
4278
4279
4280	#ifdef VBOX_STRICT
4281	/**
4282	* The '.pgmassertcr3' command.
4283	*
4284	* @returns VBox status.
4285	* @param pCmd Pointer to the command descriptor (as registered).
4286	* @param pCmdHlp Pointer to command helper functions.
4287	* @param pVM Pointer to the current VM (if any).
4288	* @param paArgs Pointer to (readonly) array of arguments.
4289	* @param cArgs Number of arguments in the array.
4290	*/
4291	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4292	{
4293	/*
4294	* Validate input.
4295	*/
4296	if (!pVM)
4297	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4298
4299	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4300	if (RT_FAILURE(rc))
4301	return rc;
4302
4303	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4304
4305	return VINF_SUCCESS;
4306	}
4307	#endif /* VBOX_STRICT */
4308
4309
4310	/**
4311	* The '.pgmsyncalways' command.
4312	*
4313	* @returns VBox status.
4314	* @param pCmd Pointer to the command descriptor (as registered).
4315	* @param pCmdHlp Pointer to command helper functions.
4316	* @param pVM Pointer to the current VM (if any).
4317	* @param paArgs Pointer to (readonly) array of arguments.
4318	* @param cArgs Number of arguments in the array.
4319	*/
4320	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4321	{
4322	/*
4323	* Validate input.
4324	*/
4325	if (!pVM)
4326	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4327
4328	/*
4329	* Force page directory sync.
4330	*/
4331	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4332	{
4333	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4334	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4335	}
4336	else
4337	{
4338	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4339	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4340	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4341	}
4342	}
4343
4344	#endif /* VBOX_WITH_DEBUGGER */
4345
4346	/**
4347	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4348	*/
4349	typedef struct PGMCHECKINTARGS
4350	{
4351	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4352	PPGMPHYSHANDLER pPrevPhys;
4353	PPGMVIRTHANDLER pPrevVirt;
4354	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4355	PVM pVM;
4356	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4357
4358	/**
4359	* Validate a node in the physical handler tree.
4360	*
4361	* @returns 0 on if ok, other wise 1.
4362	* @param pNode The handler node.
4363	* @param pvUser pVM.
4364	*/
4365	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4366	{
4367	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4368	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4369	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4370	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4371	AssertReleaseMsg( !pArgs->pPrevPhys
4372	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4373	("pPrevPhys=%p %RGp-%RGp %s\n"
4374	" pCur=%p %RGp-%RGp %s\n",
4375	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4376	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4377	pArgs->pPrevPhys = pCur;
4378	return 0;
4379	}
4380
4381
4382	/**
4383	* Validate a node in the virtual handler tree.
4384	*
4385	* @returns 0 on if ok, other wise 1.
4386	* @param pNode The handler node.
4387	* @param pvUser pVM.
4388	*/
4389	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4390	{
4391	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4392	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4393	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4394	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4395	AssertReleaseMsg( !pArgs->pPrevVirt
4396	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4397	("pPrevVirt=%p %RGv-%RGv %s\n"
4398	" pCur=%p %RGv-%RGv %s\n",
4399	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4400	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4401	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4402	{
4403	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4404	("pCur=%p %RGv-%RGv %s\n"
4405	"iPage=%d offVirtHandle=%#x expected %#x\n",
4406	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4407	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4408	}
4409	pArgs->pPrevVirt = pCur;
4410	return 0;
4411	}
4412
4413
4414	/**
4415	* Validate a node in the virtual handler tree.
4416	*
4417	* @returns 0 on if ok, other wise 1.
4418	* @param pNode The handler node.
4419	* @param pvUser pVM.
4420	*/
4421	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4422	{
4423	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4424	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4425	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4426	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4427	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4428	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4429	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4430	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4431	" pCur=%p %RGp-%RGp\n",
4432	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4433	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4434	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4435	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4436	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4437	" pCur=%p %RGp-%RGp\n",
4438	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4439	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4440	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4441	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4442	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4443	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4444	{
4445	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4446	for (;;)
4447	{
4448	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4449	AssertReleaseMsg(pCur2 != pCur,
4450	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4451	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4452	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4453	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4454	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4455	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4456	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4457	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4458	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4459	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4460	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4461	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4462	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4463	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4464	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4465	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4466	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4467	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4468	break;
4469	}
4470	}
4471
4472	pArgs->pPrevPhys2Virt = pCur;
4473	return 0;
4474	}
4475
4476
4477	/**
4478	* Perform an integrity check on the PGM component.
4479	*
4480	* @returns VINF_SUCCESS if everything is fine.
4481	* @returns VBox error status after asserting on integrity breach.
4482	* @param pVM The VM handle.
4483	*/
4484	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4485	{
4486	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4487
4488	/*
4489	* Check the trees.
4490	*/
4491	int cErrors = 0;
4492	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4493	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4494	PGMCHECKINTARGS Args = s_LeftToRight;
4495	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4496	Args = s_RightToLeft;
4497	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4498	Args = s_LeftToRight;
4499	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4500	Args = s_RightToLeft;
4501	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4502	Args = s_LeftToRight;
4503	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4504	Args = s_RightToLeft;
4505	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4506	Args = s_LeftToRight;
4507	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4508	Args = s_RightToLeft;
4509	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4510
4511	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4512	}
4513
4514
4515	/**
4516	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4517	*
4518	* @returns VBox status code.
4519	* @param pVM VM handle.
4520	* @param fEnable Enable or disable shadow mappings
4521	*/
4522	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4523	{
4524	pVM->pgm.s.fDisableMappings = !fEnable;
4525
4526	uint32_t cb;
4527	int rc = PGMR3MappingsSize(pVM, &cb);
4528	AssertRCReturn(rc, rc);
4529
4530	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4531	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4532	AssertRCReturn(rc, rc);
4533
4534	return VINF_SUCCESS;
4535	}
4536

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 14755

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