PGM.cpp@ 13813

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1	/* $Id: PGM.cpp 13796 2008-11-04 18:37:33Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location.
81	*
82	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
83	* simplifies switching guest CPU mode and consistency at the cost of more
84	* code to do the work. All memory use for those page tables is located below
85	* 4GB (this includes page tables for guest context mappings).
86	*
87	*
88	* @subsection subsec_pgm_int_gc Guest Context Mappings
89	*
90	* During assignment and relocation of a guest context mapping the intermediate
91	* memory context is used to verify the new location.
92	*
93	* Guest context mappings are currently restricted to below 4GB, for reasons
94	* of simplicity. This may change when we implement AMD64 support.
95	*
96	*
97	*
98	*
99	* @section sec_pgm_misc Misc
100	*
101	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
102	*
103	* The differences between legacy PAE and long mode PAE are:
104	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
105	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
106	* usual meanings while 6 is ignored (AMD). This means that upon switching to
107	* legacy PAE mode we'll have to clear these bits and when going to long mode
108	* they must be set. This applies to both intermediate and shadow contexts,
109	* however we don't need to do it for the intermediate one since we're
110	* executing with CR0.WP at that time.
111	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
112	* a page aligned one is required.
113	*
114	*
115	* @section sec_pgm_handlers Access Handlers
116	*
117	* Placeholder.
118	*
119	*
120	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
121	*
122	* Placeholder.
123	*
124	*
125	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
126	*
127	* We currently implement three types of virtual access handlers: ALL, WRITE
128	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
129	*
130	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
131	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
132	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
133	* rest of this section is going to be about these handlers.
134	*
135	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
136	* how successfull this is gonna be...
137	*
138	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
139	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
140	* and create a new node that is inserted into the AVL tree (range key). Then
141	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
142	*
143	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
144	*
145	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
146	* via the current guest CR3 and update the physical page -> virtual handler
147	* translation. Needless to say, this doesn't exactly scale very well. If any changes
148	* are detected, it will flag a virtual bit update just like we did on registration.
149	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
150	*
151	* 2b. The virtual bit update process will iterate all the pages covered by all the
152	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
153	* virtual handlers on that page.
154	*
155	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
156	* we don't miss any alias mappings of the monitored pages.
157	*
158	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
159	*
160	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
161	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
162	* will call the handlers like in the next step. If the physical mapping has
163	* changed we will - some time in the future - perform a handler callback
164	* (optional) and update the physical -> virtual handler cache.
165	*
166	* 4. \#PF(,write) on a page in the range. This will cause the handler to
167	* be invoked.
168	*
169	* 5. The guest invalidates the page and changes the physical backing or
170	* unmaps it. This should cause the invalidation callback to be invoked
171	* (it might not yet be 100% perfect). Exactly what happens next... is
172	* this where we mess up and end up out of sync for a while?
173	*
174	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
175	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
176	* this handler to NONE and trigger a full PGM resync (basically the same
177	* as int step 1). Which means 2 is executed again.
178	*
179	*
180	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
181	*
182	* There is a bunch of things that needs to be done to make the virtual handlers
183	* work 100% correctly and work more efficiently.
184	*
185	* The first bit hasn't been implemented yet because it's going to slow the
186	* whole mess down even more, and besides it seems to be working reliably for
187	* our current uses. OTOH, some of the optimizations might end up more or less
188	* implementing the missing bits, so we'll see.
189	*
190	* On the optimization side, the first thing to do is to try avoid unnecessary
191	* cache flushing. Then try team up with the shadowing code to track changes
192	* in mappings by means of access to them (shadow in), updates to shadows pages,
193	* invlpg, and shadow PT discarding (perhaps).
194	*
195	* Some idea that have popped up for optimization for current and new features:
196	* - bitmap indicating where there are virtual handlers installed.
197	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
198	* - Further optimize this by min/max (needs min/max avl getters).
199	* - Shadow page table entry bit (if any left)?
200	*
201	*/
202
203
204	/** @page pg_pgm_phys PGM Physical Guest Memory Management
205	*
206	*
207	* Objectives:
208	* - Guest RAM over-commitment using memory ballooning,
209	* zero pages and general page sharing.
210	* - Moving or mirroring a VM onto a different physical machine.
211	*
212	*
213	* @subsection subsec_pgmPhys_Definitions Definitions
214	*
215	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
216	* machinery assoicated with it.
217	*
218	*
219	*
220	*
221	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
222	*
223	* Initially we map all guest memory to the (per VM) zero page, which
224	* means that none of the read functions will cause pages to be allocated.
225	*
226	* Exception, access bit in page tables that have been shared. This must
227	* be handled, but we must also make sure PGMGst*Modify doesn't make
228	* unnecessary modifications.
229	*
230	* Allocation points:
231	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
232	* - Replacing a zero page mapping at \#PF.
233	* - Replacing a shared page mapping at \#PF.
234	* - ROM registration (currently MMR3RomRegister).
235	* - VM restore (pgmR3Load).
236	*
237	* For the first three it would make sense to keep a few pages handy
238	* until we've reached the max memory commitment for the VM.
239	*
240	* For the ROM registration, we know exactly how many pages we need
241	* and will request these from ring-0. For restore, we will save
242	* the number of non-zero pages in the saved state and allocate
243	* them up front. This would allow the ring-0 component to refuse
244	* the request if the isn't sufficient memory available for VM use.
245	*
246	* Btw. for both ROM and restore allocations we won't be requiring
247	* zeroed pages as they are going to be filled instantly.
248	*
249	*
250	* @subsection subsec_pgmPhys_FreePage Freeing a page
251	*
252	* There are a few points where a page can be freed:
253	* - After being replaced by the zero page.
254	* - After being replaced by a shared page.
255	* - After being ballooned by the guest additions.
256	* - At reset.
257	* - At restore.
258	*
259	* When freeing one or more pages they will be returned to the ring-0
260	* component and replaced by the zero page.
261	*
262	* The reasoning for clearing out all the pages on reset is that it will
263	* return us to the exact same state as on power on, and may thereby help
264	* us reduce the memory load on the system. Further it might have a
265	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
266	*
267	* On restore, as mention under the allocation topic, pages should be
268	* freed / allocated depending on how many is actually required by the
269	* new VM state. The simplest approach is to do like on reset, and free
270	* all non-ROM pages and then allocate what we need.
271	*
272	* A measure to prevent some fragmentation, would be to let each allocation
273	* chunk have some affinity towards the VM having allocated the most pages
274	* from it. Also, try make sure to allocate from allocation chunks that
275	* are almost full. Admittedly, both these measures might work counter to
276	* our intentions and its probably not worth putting a lot of effort,
277	* cpu time or memory into this.
278	*
279	*
280	* @subsection subsec_pgmPhys_SharePage Sharing a page
281	*
282	* The basic idea is that there there will be a idle priority kernel
283	* thread walking the non-shared VM pages hashing them and looking for
284	* pages with the same checksum. If such pages are found, it will compare
285	* them byte-by-byte to see if they actually are identical. If found to be
286	* identical it will allocate a shared page, copy the content, check that
287	* the page didn't change while doing this, and finally request both the
288	* VMs to use the shared page instead. If the page is all zeros (special
289	* checksum and byte-by-byte check) it will request the VM that owns it
290	* to replace it with the zero page.
291	*
292	* To make this efficient, we will have to make sure not to try share a page
293	* that will change its contents soon. This part requires the most work.
294	* A simple idea would be to request the VM to write monitor the page for
295	* a while to make sure it isn't modified any time soon. Also, it may
296	* make sense to skip pages that are being write monitored since this
297	* information is readily available to the thread if it works on the
298	* per-VM guest memory structures (presently called PGMRAMRANGE).
299	*
300	*
301	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
302	*
303	* The pages are organized in allocation chunks in ring-0, this is a necessity
304	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
305	* could easily work on a page-by-page basis if we liked. Whether this is possible
306	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
307	* become a problem as part of the idea here is that we wish to return memory to
308	* the host system.
309	*
310	* For instance, starting two VMs at the same time, they will both allocate the
311	* guest memory on-demand and if permitted their page allocations will be
312	* intermixed. Shut down one of the two VMs and it will be difficult to return
313	* any memory to the host system because the page allocation for the two VMs are
314	* mixed up in the same allocation chunks.
315	*
316	* To further complicate matters, when pages are freed because they have been
317	* ballooned or become shared/zero the whole idea is that the page is supposed
318	* to be reused by another VM or returned to the host system. This will cause
319	* allocation chunks to contain pages belonging to different VMs and prevent
320	* returning memory to the host when one of those VM shuts down.
321	*
322	* The only way to really deal with this problem is to move pages. This can
323	* either be done at VM shutdown and or by the idle priority worker thread
324	* that will be responsible for finding sharable/zero pages. The mechanisms
325	* involved for coercing a VM to move a page (or to do it for it) will be
326	* the same as when telling it to share/zero a page.
327	*
328	*
329	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
330	*
331	* There's a difficult balance between keeping the per-page tracking structures
332	* (global and guest page) easy to use and keeping them from eating too much
333	* memory. We have limited virtual memory resources available when operating in
334	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
335	* tracking structures will be attemted designed such that we can deal with up
336	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
337	*
338	*
339	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
340	*
341	* @see pg_GMM
342	*
343	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
344	*
345	* Fixed info is the physical address of the page (HCPhys) and the page id
346	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
347	* Today we've restricting ourselves to 40(-12) bits because this is the current
348	* restrictions of all AMD64 implementations (I think Barcelona will up this
349	* to 48(-12) bits, not that it really matters) and I needed the bits for
350	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
351	* decent range for the page id: 2^(28+12) = 1024TB.
352	*
353	* In additions to these, we'll have to keep maintaining the page flags as we
354	* currently do. Although it wouldn't harm to optimize these quite a bit, like
355	* for instance the ROM shouldn't depend on having a write handler installed
356	* in order for it to become read-only. A RO/RW bit should be considered so
357	* that the page syncing code doesn't have to mess about checking multiple
358	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
359	* figure out how to setup a shadow PTE. But this of course, is second
360	* priority at present. Current this requires 12 bits, but could probably
361	* be optimized to ~8.
362	*
363	* Then there's the 24 bits used to track which shadow page tables are
364	* currently mapping a page for the purpose of speeding up physical
365	* access handlers, and thereby the page pool cache. More bit for this
366	* purpose wouldn't hurt IIRC.
367	*
368	* Then there is a new bit in which we need to record what kind of page
369	* this is, shared, zero, normal or write-monitored-normal. This'll
370	* require 2 bits. One bit might be needed for indicating whether a
371	* write monitored page has been written to. And yet another one or
372	* two for tracking migration status. 3-4 bits total then.
373	*
374	* Whatever is left will can be used to record the sharabilitiy of a
375	* page. The page checksum will not be stored in the per-VM table as
376	* the idle thread will not be permitted to do modifications to it.
377	* It will instead have to keep its own working set of potentially
378	* shareable pages and their check sums and stuff.
379	*
380	* For the present we'll keep the current packing of the
381	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
382	* we'll have to change it to a struct with a total of 128-bits at
383	* our disposal.
384	*
385	* The initial layout will be like this:
386	* @verbatim
387	RTHCPHYS HCPhys; The current stuff.
388	63:40 Current shadow PT tracking stuff.
389	39:12 The physical page frame number.
390	11:0 The current flags.
391	uint32_t u28PageId : 28; The page id.
392	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
393	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
394	uint32_t u1Reserved : 1; Reserved for later.
395	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
396	@endverbatim
397	*
398	* The final layout will be something like this:
399	* @verbatim
400	RTHCPHYS HCPhys; The current stuff.
401	63:48 High page id (12+).
402	47:12 The physical page frame number.
403	11:0 Low page id.
404	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
405	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
406	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
407	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
408	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
409	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
410	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
411	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
412	@endverbatim
413	*
414	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
415	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
416	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
417	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
418	*
419	* A couple of cost examples for the total cost per-VM + kernel.
420	* 32-bit Windows and 32-bit linux:
421	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
422	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
423	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
424	* 64-bit Windows and 64-bit linux:
425	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
426	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
427	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
428	*
429	* UPDATE - 2007-09-27:
430	* Will need a ballooned flag/state too because we cannot
431	* trust the guest 100% and reporting the same page as ballooned more
432	* than once will put the GMM off balance.
433	*
434	*
435	* @subsection subsec_pgmPhys_Serializing Serializing Access
436	*
437	* Initially, we'll try a simple scheme:
438	*
439	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
440	* by the EMT thread of that VM while in the pgm critsect.
441	* - Other threads in the VM process that needs to make reliable use of
442	* the per-VM RAM tracking structures will enter the critsect.
443	* - No process external thread or kernel thread will ever try enter
444	* the pgm critical section, as that just won't work.
445	* - The idle thread (and similar threads) doesn't not need 100% reliable
446	* data when performing it tasks as the EMT thread will be the one to
447	* do the actual changes later anyway. So, as long as it only accesses
448	* the main ram range, it can do so by somehow preventing the VM from
449	* being destroyed while it works on it...
450	*
451	* - The over-commitment management, including the allocating/freeing
452	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
453	* more mundane mutex implementation is broken on Linux).
454	* - A separeate mutex is protecting the set of allocation chunks so
455	* that pages can be shared or/and freed up while some other VM is
456	* allocating more chunks. This mutex can be take from under the other
457	* one, but not the otherway around.
458	*
459	*
460	* @subsection subsec_pgmPhys_Request VM Request interface
461	*
462	* When in ring-0 it will become necessary to send requests to a VM so it can
463	* for instance move a page while defragmenting during VM destroy. The idle
464	* thread will make use of this interface to request VMs to setup shared
465	* pages and to perform write monitoring of pages.
466	*
467	* I would propose an interface similar to the current VMReq interface, similar
468	* in that it doesn't require locking and that the one sending the request may
469	* wait for completion if it wishes to. This shouldn't be very difficult to
470	* realize.
471	*
472	* The requests themselves are also pretty simple. They are basically:
473	* -# Check that some precondition is still true.
474	* -# Do the update.
475	* -# Update all shadow page tables involved with the page.
476	*
477	* The 3rd step is identical to what we're already doing when updating a
478	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
479	*
480	*
481	*
482	* @section sec_pgmPhys_MappingCaches Mapping Caches
483	*
484	* In order to be able to map in and out memory and to be able to support
485	* guest with more RAM than we've got virtual address space, we'll employing
486	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
487	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
488	* memory context for the HWACCM execution.
489	*
490	*
491	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
492	*
493	* We've considered implementing the ring-3 mapping cache page based but found
494	* that this was bother some when one had to take into account TLBs+SMP and
495	* portability (missing the necessary APIs on several platforms). There were
496	* also some performance concerns with this approach which hadn't quite been
497	* worked out.
498	*
499	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
500	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
501	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
502	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
503	* costly than a single page, although how much more costly is uncertain. We'll
504	* try address this by using a very big cache, preferably bigger than the actual
505	* VM RAM size if possible. The current VM RAM sizes should give some idea for
506	* 32-bit boxes, while on 64-bit we can probably get away with employing an
507	* unlimited cache.
508	*
509	* The cache have to parts, as already indicated, the ring-3 side and the
510	* ring-0 side.
511	*
512	* The ring-0 will be tied to the page allocator since it will operate on the
513	* memory objects it contains. It will therefore require the first ring-0 mutex
514	* discussed in @ref subsec_pgmPhys_Serializing. We
515	* some double house keeping wrt to who has mapped what I think, since both
516	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
517	*
518	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
519	* require anyone that desires to do changes to the mapping cache to do that
520	* from within this critsect. Alternatively, we could employ a separate critsect
521	* for serializing changes to the mapping cache as this would reduce potential
522	* contention with other threads accessing mappings unrelated to the changes
523	* that are in process. We can see about this later, contention will show
524	* up in the statistics anyway, so it'll be simple to tell.
525	*
526	* The organization of the ring-3 part will be very much like how the allocation
527	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
528	* having to walk the tree all the time, we'll have a couple of lookaside entries
529	* like in we do for I/O ports and MMIO in IOM.
530	*
531	* The simplified flow of a PGMPhysRead/Write function:
532	* -# Enter the PGM critsect.
533	* -# Lookup GCPhys in the ram ranges and get the Page ID.
534	* -# Calc the Allocation Chunk ID from the Page ID.
535	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
536	* If not found in cache:
537	* -# Call ring-0 and request it to be mapped and supply
538	* a chunk to be unmapped if the cache is maxed out already.
539	* -# Insert the new mapping into the AVL tree (id + R3 address).
540	* -# Update the relevant lookaside entry and return the mapping address.
541	* -# Do the read/write according to monitoring flags and everything.
542	* -# Leave the critsect.
543	*
544	*
545	* @section sec_pgmPhys_Fallback Fallback
546	*
547	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
548	* API and thus require a fallback.
549	*
550	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
551	* will return to the ring-3 caller (and later ring-0) and asking it to seed
552	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
553	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
554	* "SeededAllocPages" call to ring-0.
555	*
556	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
557	* all page sharing (zero page detection will continue). It will also force
558	* all allocations to come from the VM which seeded the page. Both these
559	* measures are taken to make sure that there will never be any need for
560	* mapping anything into ring-3 - everything will be mapped already.
561	*
562	* Whether we'll continue to use the current MM locked memory management
563	* for this I don't quite know (I'd prefer not to and just ditch that all
564	* togther), we'll see what's simplest to do.
565	*
566	*
567	*
568	* @section sec_pgmPhys_Changes Changes
569	*
570	* Breakdown of the changes involved?
571	*/
572
573
574	/** Saved state data unit version. */
575	#define PGM_SAVED_STATE_VERSION 6
576
577	/*******************************************************************************
578	* Header Files *
579	*******************************************************************************/
580	#define LOG_GROUP LOG_GROUP_PGM
581	#include <VBox/dbgf.h>
582	#include <VBox/pgm.h>
583	#include <VBox/cpum.h>
584	#include <VBox/iom.h>
585	#include <VBox/sup.h>
586	#include <VBox/mm.h>
587	#include <VBox/em.h>
588	#include <VBox/stam.h>
589	#include <VBox/rem.h>
590	#include <VBox/dbgf.h>
591	#include <VBox/rem.h>
592	#include <VBox/selm.h>
593	#include <VBox/ssm.h>
594	#include "PGMInternal.h"
595	#include <VBox/vm.h>
596	#include <VBox/dbg.h>
597	#include <VBox/hwaccm.h>
598
599	#include <iprt/assert.h>
600	#include <iprt/alloc.h>
601	#include <iprt/asm.h>
602	#include <iprt/thread.h>
603	#include <iprt/string.h>
604	#ifdef DEBUG_bird
605	# include <iprt/env.h>
606	#endif
607	#include <VBox/param.h>
608	#include <VBox/err.h>
609
610
611
612	/*******************************************************************************
613	* Internal Functions *
614	*******************************************************************************/
615	static int pgmR3InitPaging(PVM pVM);
616	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
617	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
620	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	#ifdef VBOX_STRICT
623	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
624	#endif
625	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
626	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
627	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
628	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
629	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
630
631	#ifdef VBOX_WITH_STATISTICS
632	static void pgmR3InitStats(PVM pVM);
633	#endif
634
635	#ifdef VBOX_WITH_DEBUGGER
636	/** @todo all but the two last commands must be converted to 'info'. */
637	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	# ifdef VBOX_STRICT
642	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643	# endif
644	#endif
645
646
647	/*******************************************************************************
648	* Global Variables *
649	*******************************************************************************/
650	#ifdef VBOX_WITH_DEBUGGER
651	/** Command descriptors. */
652	static const DBGCCMD g_aCmds[] =
653	{
654	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
655	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
656	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
657	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
658	#ifdef VBOX_STRICT
659	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
660	#endif
661	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
662	};
663	#endif
664
665
666
667
668	/*
669	* Shadow - 32-bit mode
670	*/
671	#define PGM_SHW_TYPE PGM_TYPE_32BIT
672	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
673	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
674	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
675	#include "PGMShw.h"
676
677	/* Guest - real mode */
678	#define PGM_GST_TYPE PGM_TYPE_REAL
679	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
680	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
681	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
682	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
683	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
684	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
685	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
686	#include "PGMGst.h"
687	#include "PGMBth.h"
688	#undef BTH_PGMPOOLKIND_PT_FOR_PT
689	#undef PGM_BTH_NAME
690	#undef PGM_BTH_NAME_RC_STR
691	#undef PGM_BTH_NAME_R0_STR
692	#undef PGM_GST_TYPE
693	#undef PGM_GST_NAME
694	#undef PGM_GST_NAME_RC_STR
695	#undef PGM_GST_NAME_R0_STR
696
697	/* Guest - protected mode */
698	#define PGM_GST_TYPE PGM_TYPE_PROT
699	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
700	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
701	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
702	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
703	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
704	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
705	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
706	#include "PGMGst.h"
707	#include "PGMBth.h"
708	#undef BTH_PGMPOOLKIND_PT_FOR_PT
709	#undef PGM_BTH_NAME
710	#undef PGM_BTH_NAME_RC_STR
711	#undef PGM_BTH_NAME_R0_STR
712	#undef PGM_GST_TYPE
713	#undef PGM_GST_NAME
714	#undef PGM_GST_NAME_RC_STR
715	#undef PGM_GST_NAME_R0_STR
716
717	/* Guest - 32-bit mode */
718	#define PGM_GST_TYPE PGM_TYPE_32BIT
719	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
720	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
721	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
722	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
723	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
724	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
725	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
726	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
727	#include "PGMGst.h"
728	#include "PGMBth.h"
729	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
730	#undef BTH_PGMPOOLKIND_PT_FOR_PT
731	#undef PGM_BTH_NAME
732	#undef PGM_BTH_NAME_RC_STR
733	#undef PGM_BTH_NAME_R0_STR
734	#undef PGM_GST_TYPE
735	#undef PGM_GST_NAME
736	#undef PGM_GST_NAME_RC_STR
737	#undef PGM_GST_NAME_R0_STR
738
739	#undef PGM_SHW_TYPE
740	#undef PGM_SHW_NAME
741	#undef PGM_SHW_NAME_RC_STR
742	#undef PGM_SHW_NAME_R0_STR
743
744
745	/*
746	* Shadow - PAE mode
747	*/
748	#define PGM_SHW_TYPE PGM_TYPE_PAE
749	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
750	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
751	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
752	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
753	#include "PGMShw.h"
754
755	/* Guest - real mode */
756	#define PGM_GST_TYPE PGM_TYPE_REAL
757	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
758	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
759	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
760	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
761	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
762	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
763	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
764	#include "PGMBth.h"
765	#undef BTH_PGMPOOLKIND_PT_FOR_PT
766	#undef PGM_BTH_NAME
767	#undef PGM_BTH_NAME_RC_STR
768	#undef PGM_BTH_NAME_R0_STR
769	#undef PGM_GST_TYPE
770	#undef PGM_GST_NAME
771	#undef PGM_GST_NAME_RC_STR
772	#undef PGM_GST_NAME_R0_STR
773
774	/* Guest - protected mode */
775	#define PGM_GST_TYPE PGM_TYPE_PROT
776	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
777	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
778	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
779	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
780	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
781	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
782	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
783	#include "PGMBth.h"
784	#undef BTH_PGMPOOLKIND_PT_FOR_PT
785	#undef PGM_BTH_NAME
786	#undef PGM_BTH_NAME_RC_STR
787	#undef PGM_BTH_NAME_R0_STR
788	#undef PGM_GST_TYPE
789	#undef PGM_GST_NAME
790	#undef PGM_GST_NAME_RC_STR
791	#undef PGM_GST_NAME_R0_STR
792
793	/* Guest - 32-bit mode */
794	#define PGM_GST_TYPE PGM_TYPE_32BIT
795	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
796	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
797	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
798	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
799	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
800	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
801	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
802	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
803	#include "PGMBth.h"
804	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
805	#undef BTH_PGMPOOLKIND_PT_FOR_PT
806	#undef PGM_BTH_NAME
807	#undef PGM_BTH_NAME_RC_STR
808	#undef PGM_BTH_NAME_R0_STR
809	#undef PGM_GST_TYPE
810	#undef PGM_GST_NAME
811	#undef PGM_GST_NAME_RC_STR
812	#undef PGM_GST_NAME_R0_STR
813
814	/* Guest - PAE mode */
815	#define PGM_GST_TYPE PGM_TYPE_PAE
816	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
817	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
818	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
819	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
820	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
821	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
822	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
823	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
824	#include "PGMGst.h"
825	#include "PGMBth.h"
826	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
827	#undef BTH_PGMPOOLKIND_PT_FOR_PT
828	#undef PGM_BTH_NAME
829	#undef PGM_BTH_NAME_RC_STR
830	#undef PGM_BTH_NAME_R0_STR
831	#undef PGM_GST_TYPE
832	#undef PGM_GST_NAME
833	#undef PGM_GST_NAME_RC_STR
834	#undef PGM_GST_NAME_R0_STR
835
836	#undef PGM_SHW_TYPE
837	#undef PGM_SHW_NAME
838	#undef PGM_SHW_NAME_RC_STR
839	#undef PGM_SHW_NAME_R0_STR
840
841
842	/*
843	* Shadow - AMD64 mode
844	*/
845	#define PGM_SHW_TYPE PGM_TYPE_AMD64
846	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
847	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
848	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
849	#include "PGMShw.h"
850
851	#ifdef VBOX_WITH_64_BITS_GUESTS
852	/* Guest - AMD64 mode */
853	# define PGM_GST_TYPE PGM_TYPE_AMD64
854	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
855	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
856	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
857	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
858	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
859	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
860	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
861	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
862	# include "PGMGst.h"
863	# include "PGMBth.h"
864	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
865	# undef BTH_PGMPOOLKIND_PT_FOR_PT
866	# undef PGM_BTH_NAME
867	# undef PGM_BTH_NAME_RC_STR
868	# undef PGM_BTH_NAME_R0_STR
869	# undef PGM_GST_TYPE
870	# undef PGM_GST_NAME
871	# undef PGM_GST_NAME_RC_STR
872	# undef PGM_GST_NAME_R0_STR
873	#endif /* VBOX_WITH_64_BITS_GUESTS */
874
875	#undef PGM_SHW_TYPE
876	#undef PGM_SHW_NAME
877	#undef PGM_SHW_NAME_RC_STR
878	#undef PGM_SHW_NAME_R0_STR
879
880
881	/*
882	* Shadow - Nested paging mode
883	*/
884	#define PGM_SHW_TYPE PGM_TYPE_NESTED
885	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
886	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
887	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
888	#include "PGMShw.h"
889
890	/* Guest - real mode */
891	#define PGM_GST_TYPE PGM_TYPE_REAL
892	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
893	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
894	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
895	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
896	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
897	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
898	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
899	#include "PGMBth.h"
900	#undef BTH_PGMPOOLKIND_PT_FOR_PT
901	#undef PGM_BTH_NAME
902	#undef PGM_BTH_NAME_RC_STR
903	#undef PGM_BTH_NAME_R0_STR
904	#undef PGM_GST_TYPE
905	#undef PGM_GST_NAME
906	#undef PGM_GST_NAME_RC_STR
907	#undef PGM_GST_NAME_R0_STR
908
909	/* Guest - protected mode */
910	#define PGM_GST_TYPE PGM_TYPE_PROT
911	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
912	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
913	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
914	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
915	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
916	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
917	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
918	#include "PGMBth.h"
919	#undef BTH_PGMPOOLKIND_PT_FOR_PT
920	#undef PGM_BTH_NAME
921	#undef PGM_BTH_NAME_RC_STR
922	#undef PGM_BTH_NAME_R0_STR
923	#undef PGM_GST_TYPE
924	#undef PGM_GST_NAME
925	#undef PGM_GST_NAME_RC_STR
926	#undef PGM_GST_NAME_R0_STR
927
928	/* Guest - 32-bit mode */
929	#define PGM_GST_TYPE PGM_TYPE_32BIT
930	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
931	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
932	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
933	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
934	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
935	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
936	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
937	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
938	#include "PGMBth.h"
939	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
940	#undef BTH_PGMPOOLKIND_PT_FOR_PT
941	#undef PGM_BTH_NAME
942	#undef PGM_BTH_NAME_RC_STR
943	#undef PGM_BTH_NAME_R0_STR
944	#undef PGM_GST_TYPE
945	#undef PGM_GST_NAME
946	#undef PGM_GST_NAME_RC_STR
947	#undef PGM_GST_NAME_R0_STR
948
949	/* Guest - PAE mode */
950	#define PGM_GST_TYPE PGM_TYPE_PAE
951	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
952	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
953	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
954	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
955	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
956	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
957	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
958	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
959	#include "PGMBth.h"
960	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
961	#undef BTH_PGMPOOLKIND_PT_FOR_PT
962	#undef PGM_BTH_NAME
963	#undef PGM_BTH_NAME_RC_STR
964	#undef PGM_BTH_NAME_R0_STR
965	#undef PGM_GST_TYPE
966	#undef PGM_GST_NAME
967	#undef PGM_GST_NAME_RC_STR
968	#undef PGM_GST_NAME_R0_STR
969
970	#ifdef VBOX_WITH_64_BITS_GUESTS
971	/* Guest - AMD64 mode */
972	# define PGM_GST_TYPE PGM_TYPE_AMD64
973	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
974	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
975	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
976	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
977	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
978	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
979	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
980	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
981	# include "PGMBth.h"
982	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
983	# undef BTH_PGMPOOLKIND_PT_FOR_PT
984	# undef PGM_BTH_NAME
985	# undef PGM_BTH_NAME_RC_STR
986	# undef PGM_BTH_NAME_R0_STR
987	# undef PGM_GST_TYPE
988	# undef PGM_GST_NAME
989	# undef PGM_GST_NAME_RC_STR
990	# undef PGM_GST_NAME_R0_STR
991	#endif /* VBOX_WITH_64_BITS_GUESTS */
992
993	#undef PGM_SHW_TYPE
994	#undef PGM_SHW_NAME
995	#undef PGM_SHW_NAME_RC_STR
996	#undef PGM_SHW_NAME_R0_STR
997
998
999	/*
1000	* Shadow - EPT
1001	*/
1002	#define PGM_SHW_TYPE PGM_TYPE_EPT
1003	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1004	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1005	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1006	#include "PGMShw.h"
1007
1008	/* Guest - real mode */
1009	#define PGM_GST_TYPE PGM_TYPE_REAL
1010	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1011	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1012	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1013	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1014	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1015	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1016	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1017	#include "PGMBth.h"
1018	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1019	#undef PGM_BTH_NAME
1020	#undef PGM_BTH_NAME_RC_STR
1021	#undef PGM_BTH_NAME_R0_STR
1022	#undef PGM_GST_TYPE
1023	#undef PGM_GST_NAME
1024	#undef PGM_GST_NAME_RC_STR
1025	#undef PGM_GST_NAME_R0_STR
1026
1027	/* Guest - protected mode */
1028	#define PGM_GST_TYPE PGM_TYPE_PROT
1029	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1030	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1031	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1032	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1033	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1034	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1035	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1036	#include "PGMBth.h"
1037	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1038	#undef PGM_BTH_NAME
1039	#undef PGM_BTH_NAME_RC_STR
1040	#undef PGM_BTH_NAME_R0_STR
1041	#undef PGM_GST_TYPE
1042	#undef PGM_GST_NAME
1043	#undef PGM_GST_NAME_RC_STR
1044	#undef PGM_GST_NAME_R0_STR
1045
1046	/* Guest - 32-bit mode */
1047	#define PGM_GST_TYPE PGM_TYPE_32BIT
1048	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1049	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1050	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1051	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1052	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1053	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1054	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1055	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1056	#include "PGMBth.h"
1057	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1058	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1059	#undef PGM_BTH_NAME
1060	#undef PGM_BTH_NAME_RC_STR
1061	#undef PGM_BTH_NAME_R0_STR
1062	#undef PGM_GST_TYPE
1063	#undef PGM_GST_NAME
1064	#undef PGM_GST_NAME_RC_STR
1065	#undef PGM_GST_NAME_R0_STR
1066
1067	/* Guest - PAE mode */
1068	#define PGM_GST_TYPE PGM_TYPE_PAE
1069	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1070	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1071	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1072	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1073	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1074	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1075	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1076	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1077	#include "PGMBth.h"
1078	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1079	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1080	#undef PGM_BTH_NAME
1081	#undef PGM_BTH_NAME_RC_STR
1082	#undef PGM_BTH_NAME_R0_STR
1083	#undef PGM_GST_TYPE
1084	#undef PGM_GST_NAME
1085	#undef PGM_GST_NAME_RC_STR
1086	#undef PGM_GST_NAME_R0_STR
1087
1088	#ifdef VBOX_WITH_64_BITS_GUESTS
1089	/* Guest - AMD64 mode */
1090	# define PGM_GST_TYPE PGM_TYPE_AMD64
1091	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1092	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1093	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1094	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1095	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1096	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1097	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1098	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1099	# include "PGMBth.h"
1100	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1101	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1102	# undef PGM_BTH_NAME
1103	# undef PGM_BTH_NAME_RC_STR
1104	# undef PGM_BTH_NAME_R0_STR
1105	# undef PGM_GST_TYPE
1106	# undef PGM_GST_NAME
1107	# undef PGM_GST_NAME_RC_STR
1108	# undef PGM_GST_NAME_R0_STR
1109	#endif /* VBOX_WITH_64_BITS_GUESTS */
1110
1111	#undef PGM_SHW_TYPE
1112	#undef PGM_SHW_NAME
1113	#undef PGM_SHW_NAME_RC_STR
1114	#undef PGM_SHW_NAME_R0_STR
1115
1116
1117
1118	/**
1119	* Initiates the paging of VM.
1120	*
1121	* @returns VBox status code.
1122	* @param pVM Pointer to VM structure.
1123	*/
1124	VMMR3DECL(int) PGMR3Init(PVM pVM)
1125	{
1126	LogFlow(("PGMR3Init:\n"));
1127
1128	/*
1129	* Assert alignment and sizes.
1130	*/
1131	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1132
1133	/*
1134	* Init the structure.
1135	*/
1136	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1137	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1138	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1139	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1140	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1141	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1142	pVM->pgm.s.fA20Enabled = true;
1143	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1144	pVM->pgm.s.pGstPaePDPTHC = NULL;
1145	pVM->pgm.s.pGstPaePDPTGC = 0;
1146	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1147	{
1148	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1149	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1150	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1151	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1152	}
1153
1154	#ifdef VBOX_STRICT
1155	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1156	#endif
1157
1158	/*
1159	* Get the configured RAM size - to estimate saved state size.
1160	*/
1161	uint64_t cbRam;
1162	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1163	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1164	cbRam = pVM->pgm.s.cbRamSize = 0;
1165	else if (VBOX_SUCCESS(rc))
1166	{
1167	if (cbRam < PAGE_SIZE)
1168	cbRam = 0;
1169	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1170	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1171	}
1172	else
1173	{
1174	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1175	return rc;
1176	}
1177
1178	/*
1179	* Register saved state data unit.
1180	*/
1181	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1182	NULL, pgmR3Save, NULL,
1183	NULL, pgmR3Load, NULL);
1184	if (VBOX_FAILURE(rc))
1185	return rc;
1186
1187	/*
1188	* Initialize the PGM critical section and flush the phys TLBs
1189	*/
1190	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1191	AssertRCReturn(rc, rc);
1192
1193	PGMR3PhysChunkInvalidateTLB(pVM);
1194	PGMPhysInvalidatePageR3MapTLB(pVM);
1195	PGMPhysInvalidatePageR0MapTLB(pVM);
1196	PGMPhysInvalidatePageGCMapTLB(pVM);
1197
1198	/*
1199	* Trees
1200	*/
1201	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1202	if (VBOX_SUCCESS(rc))
1203	{
1204	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1205	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1206
1207	/*
1208	* Alocate the zero page.
1209	*/
1210	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1211	}
1212	if (VBOX_SUCCESS(rc))
1213	{
1214	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1215	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1216	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1217	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1218	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1219
1220	/*
1221	* Init the paging.
1222	*/
1223	rc = pgmR3InitPaging(pVM);
1224	}
1225	if (VBOX_SUCCESS(rc))
1226	{
1227	/*
1228	* Init the page pool.
1229	*/
1230	rc = pgmR3PoolInit(pVM);
1231	}
1232	if (VBOX_SUCCESS(rc))
1233	{
1234	/*
1235	* Info & statistics
1236	*/
1237	DBGFR3InfoRegisterInternal(pVM, "mode",
1238	"Shows the current paging mode. "
1239	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1240	pgmR3InfoMode);
1241	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1242	"Dumps all the entries in the top level paging table. No arguments.",
1243	pgmR3InfoCr3);
1244	DBGFR3InfoRegisterInternal(pVM, "phys",
1245	"Dumps all the physical address ranges. No arguments.",
1246	pgmR3PhysInfo);
1247	DBGFR3InfoRegisterInternal(pVM, "handlers",
1248	"Dumps physical, virtual and hyper virtual handlers. "
1249	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1250	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1251	pgmR3InfoHandlers);
1252	DBGFR3InfoRegisterInternal(pVM, "mappings",
1253	"Dumps guest mappings.",
1254	pgmR3MapInfo);
1255
1256	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1257	#ifdef VBOX_WITH_STATISTICS
1258	pgmR3InitStats(pVM);
1259	#endif
1260	#ifdef VBOX_WITH_DEBUGGER
1261	/*
1262	* Debugger commands.
1263	*/
1264	static bool fRegisteredCmds = false;
1265	if (!fRegisteredCmds)
1266	{
1267	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1268	if (VBOX_SUCCESS(rc))
1269	fRegisteredCmds = true;
1270	}
1271	#endif
1272	return VINF_SUCCESS;
1273	}
1274
1275	/* Almost no cleanup necessary, MM frees all memory. */
1276	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1277
1278	return rc;
1279	}
1280
1281
1282	/**
1283	* Initializes the per-VCPU PGM.
1284	*
1285	* @returns VBox status code.
1286	* @param pVM The VM to operate on.
1287	*/
1288	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1289	{
1290	LogFlow(("PGMR3InitCPU\n"));
1291	return VINF_SUCCESS;
1292	}
1293
1294
1295	/**
1296	* Init paging.
1297	*
1298	* Since we need to check what mode the host is operating in before we can choose
1299	* the right paging functions for the host we have to delay this until R0 has
1300	* been initialized.
1301	*
1302	* @returns VBox status code.
1303	* @param pVM VM handle.
1304	*/
1305	static int pgmR3InitPaging(PVM pVM)
1306	{
1307	/*
1308	* Force a recalculation of modes and switcher so everyone gets notified.
1309	*/
1310	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1311	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1312	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1313
1314	/*
1315	* Allocate static mapping space for whatever the cr3 register
1316	* points to and in the case of PAE mode to the 4 PDs.
1317	*/
1318	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1319	if (VBOX_FAILURE(rc))
1320	{
1321	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1322	return rc;
1323	}
1324	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1325
1326	/*
1327	* Allocate pages for the three possible intermediate contexts
1328	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1329	* for the sake of simplicity. The AMD64 uses the PAE for the
1330	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1331	*
1332	* We assume that two page tables will be enought for the core code
1333	* mappings (HC virtual and identity).
1334	*/
1335	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1336	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1337	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1338	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1339	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1340	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1341	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1342	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1343	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1344	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1345	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1346	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1347	if ( !pVM->pgm.s.pInterPD
1348	\|\| !pVM->pgm.s.apInterPTs[0]
1349	\|\| !pVM->pgm.s.apInterPTs[1]
1350	\|\| !pVM->pgm.s.apInterPaePTs[0]
1351	\|\| !pVM->pgm.s.apInterPaePTs[1]
1352	\|\| !pVM->pgm.s.apInterPaePDs[0]
1353	\|\| !pVM->pgm.s.apInterPaePDs[1]
1354	\|\| !pVM->pgm.s.apInterPaePDs[2]
1355	\|\| !pVM->pgm.s.apInterPaePDs[3]
1356	\|\| !pVM->pgm.s.pInterPaePDPT
1357	\|\| !pVM->pgm.s.pInterPaePDPT64
1358	\|\| !pVM->pgm.s.pInterPaePML4)
1359	{
1360	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1361	return VERR_NO_PAGE_MEMORY;
1362	}
1363
1364	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1365	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1366	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1367	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1368	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1369	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1370
1371	/*
1372	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1373	*/
1374	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1375	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1376	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1377
1378	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1379	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1380
1381	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1382	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1383	{
1384	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1385	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1386	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1387	}
1388
1389	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1390	{
1391	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1392	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1393	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1394	}
1395
1396	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1397	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1398	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1399	\| HCPhysInterPaePDPT64;
1400
1401	/*
1402	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1403	* We allocate pages for all three posibilities in order to simplify mappings and
1404	* avoid resource failure during mode switches. So, we need to cover all levels of the
1405	* of the first 4GB down to PD level.
1406	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1407	*/
1408	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1409	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1410	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1411	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1412	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1413	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1414	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1415	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1416	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1417	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1418
1419	if ( !pVM->pgm.s.pHC32BitPD
1420	\|\| !pVM->pgm.s.apHCPaePDs[0]
1421	\|\| !pVM->pgm.s.apHCPaePDs[1]
1422	\|\| !pVM->pgm.s.apHCPaePDs[2]
1423	\|\| !pVM->pgm.s.apHCPaePDs[3]
1424	\|\| !pVM->pgm.s.pHCPaePDPT
1425	\|\| !pVM->pgm.s.pHCNestedRoot)
1426	{
1427	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1428	return VERR_NO_PAGE_MEMORY;
1429	}
1430
1431	/* get physical addresses. */
1432	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1433	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1434	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1435	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1436	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1437	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1438	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1439	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1440
1441	/*
1442	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1443	*/
1444	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1445	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1446	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1447	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1448	{
1449	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1450	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1451	/* The flags will be corrected when entering and leaving long mode. */
1452	}
1453
1454	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1455
1456	/*
1457	* Initialize paging workers and mode from current host mode
1458	* and the guest running in real mode.
1459	*/
1460	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1461	switch (pVM->pgm.s.enmHostMode)
1462	{
1463	case SUPPAGINGMODE_32_BIT:
1464	case SUPPAGINGMODE_32_BIT_GLOBAL:
1465	case SUPPAGINGMODE_PAE:
1466	case SUPPAGINGMODE_PAE_GLOBAL:
1467	case SUPPAGINGMODE_PAE_NX:
1468	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1469	break;
1470
1471	case SUPPAGINGMODE_AMD64:
1472	case SUPPAGINGMODE_AMD64_GLOBAL:
1473	case SUPPAGINGMODE_AMD64_NX:
1474	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1475	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1476	if (ARCH_BITS != 64)
1477	{
1478	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1479	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1480	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1481	}
1482	#endif
1483	break;
1484	default:
1485	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1486	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1487	}
1488	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1489	if (VBOX_SUCCESS(rc))
1490	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1491	if (VBOX_SUCCESS(rc))
1492	{
1493	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1494	#if HC_ARCH_BITS == 64
1495	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysPaePDPT=%RHp HCPhysPaePML4=%RHp\n",
1496	pVM->pgm.s.HCPhys32BitPD,
1497	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1498	pVM->pgm.s.HCPhysPaePDPT,
1499	pVM->pgm.s.HCPhysPaePML4));
1500	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1501	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1502	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1503	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1504	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1505	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1506	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1507	#endif
1508
1509	return VINF_SUCCESS;
1510	}
1511
1512	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1513	return rc;
1514	}
1515
1516
1517	#ifdef VBOX_WITH_STATISTICS
1518	/**
1519	* Init statistics
1520	*/
1521	static void pgmR3InitStats(PVM pVM)
1522	{
1523	PPGM pPGM = &pVM->pgm.s;
1524	unsigned i;
1525
1526	/*
1527	* Note! The layout of this function matches the member layout exactly!
1528	*/
1529
1530	/* Common - misc variables */
1531	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1532	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1533	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1534	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1535	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1536	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1537
1538	/* Common - stats */
1539	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1540	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1541	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1542	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1543	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1544	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1545	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1546	#endif
1547	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1548	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1549	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1550	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1551	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1552	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1553
1554	/* R3 only: */
1555	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1556	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1557	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1558	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1559	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1560	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1561
1562	/* GC only: */
1563	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1564	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1565	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1566	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1567
1568	/* RZ only: */
1569	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1570	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1571	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1572	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1573	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1574	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1575	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1576	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1577	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1578	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1579	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1580	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1581	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1582	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1583	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1584	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1585	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1586	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1587	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1588	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1589	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1590	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1591	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1592	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1593	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1594	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1595	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1596	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1597	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1598	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1599	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1600	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1601	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1602	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1603	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1604	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1605	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1606	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1607	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1608	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1609	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1610	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1611	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1612	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1613	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1614	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1615	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1616	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1617	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1618	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1619	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1620
1621	/* HC only: */
1622
1623	/* RZ & R3: */
1624	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1625	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1626	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1627	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1628	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1629	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1630	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1631	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1632	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1633	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1634	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1635	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1636	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1637	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1638	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1639	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1640	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1641	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1642	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1643	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1644	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1645	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1646	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1647	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1648	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1649	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1650	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1651	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1652	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1653	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1654	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1655	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1656	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1657	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1658	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1659	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1660	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1661	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1662	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1663	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1664	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1665	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1666	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1667	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1668	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1669	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1670	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1671	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1672	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1673	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1674	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1675	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1676	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1677	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1678
1679	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1680	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1681	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1682	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1683	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1684	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1685	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1686	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1687	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1688	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1689	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1690	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1691	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1692	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1693	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1694	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1695	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1696	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1697	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1698	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1699	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1700	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1701	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1702	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1703	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1704	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1705	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1706	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1707	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1708	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1709	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1710	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1711	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1712	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1713	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1714	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1715	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1716	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1717	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1718	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1719	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1720	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1721	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1722	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1723	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1724	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1725	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1726	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1727	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1728	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1729	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1730	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1731	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1732	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1733
1734	}
1735	#endif /* VBOX_WITH_STATISTICS */
1736
1737
1738	/**
1739	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1740	*
1741	* The dynamic mapping area will also be allocated and initialized at this
1742	* time. We could allocate it during PGMR3Init of course, but the mapping
1743	* wouldn't be allocated at that time preventing us from setting up the
1744	* page table entries with the dummy page.
1745	*
1746	* @returns VBox status code.
1747	* @param pVM VM handle.
1748	*/
1749	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1750	{
1751	RTGCPTR GCPtr;
1752	/*
1753	* Reserve space for mapping the paging pages into guest context.
1754	*/
1755	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1756	AssertRCReturn(rc, rc);
1757	pVM->pgm.s.pGC32BitPD = GCPtr;
1758	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1759
1760	/*
1761	* Reserve space for the dynamic mappings.
1762	*/
1763	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1764	if (VBOX_SUCCESS(rc))
1765	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1766
1767	if ( VBOX_SUCCESS(rc)
1768	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1769	{
1770	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1771	if (VBOX_SUCCESS(rc))
1772	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1773	}
1774	if (VBOX_SUCCESS(rc))
1775	{
1776	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1777	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1778	}
1779	return rc;
1780	}
1781
1782
1783	/**
1784	* Ring-3 init finalizing.
1785	*
1786	* @returns VBox status code.
1787	* @param pVM The VM handle.
1788	*/
1789	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1790	{
1791	/*
1792	* Map the paging pages into the guest context.
1793	*/
1794	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1795	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1796
1797	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1798	AssertRCReturn(rc, rc);
1799	pVM->pgm.s.pGC32BitPD = GCPtr;
1800	GCPtr += PAGE_SIZE;
1801	GCPtr += PAGE_SIZE; /* reserved page */
1802
1803	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1804	{
1805	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1806	AssertRCReturn(rc, rc);
1807	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1808	GCPtr += PAGE_SIZE;
1809	}
1810	/* A bit of paranoia is justified. */
1811	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1812	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1813	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1814	GCPtr += PAGE_SIZE; /* reserved page */
1815
1816	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1817	AssertRCReturn(rc, rc);
1818	pVM->pgm.s.pGCPaePDPT = GCPtr;
1819	GCPtr += PAGE_SIZE;
1820	GCPtr += PAGE_SIZE; /* reserved page */
1821
1822
1823	/*
1824	* Reserve space for the dynamic mappings.
1825	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1826	*/
1827	/* get the pointer to the page table entries. */
1828	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1829	AssertRelease(pMapping);
1830	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1831	const unsigned iPT = off >> X86_PD_SHIFT;
1832	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1833	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1834	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1835
1836	/* init cache */
1837	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1838	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1839	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1840
1841	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1842	{
1843	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1844	AssertRCReturn(rc, rc);
1845	}
1846
1847	/*
1848	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1849	* Intel only goes up to 36 bits, so we stick to 36 as well.
1850	*/
1851	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1852	uint32_t u32Dummy, u32Features;
1853	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1854
1855	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1856	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1857	else
1858	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1859
1860	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1861
1862	return rc;
1863	}
1864
1865
1866	/**
1867	* Applies relocations to data and code managed by this component.
1868	*
1869	* This function will be called at init and whenever the VMM need to relocate it
1870	* self inside the GC.
1871	*
1872	* @param pVM The VM.
1873	* @param offDelta Relocation delta relative to old location.
1874	*/
1875	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1876	{
1877	LogFlow(("PGMR3Relocate\n"));
1878
1879	/*
1880	* Paging stuff.
1881	*/
1882	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1883	/** @todo move this into shadow and guest specific relocation functions. */
1884	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1885	pVM->pgm.s.pGC32BitPD += offDelta;
1886	pVM->pgm.s.pGuestPDGC += offDelta;
1887	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apGCPaePDs) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1888	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1889	{
1890	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1891	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1892	}
1893	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1894	pVM->pgm.s.pGCPaePDPT += offDelta;
1895
1896	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1897	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1898
1899	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1900	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1901	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1902
1903	/*
1904	* Trees.
1905	*/
1906	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1907
1908	/*
1909	* Ram ranges.
1910	*/
1911	if (pVM->pgm.s.pRamRangesR3)
1912	{
1913	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1914	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1915	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1916	}
1917
1918	/*
1919	* Update the two page directories with all page table mappings.
1920	* (One or more of them have changed, that's why we're here.)
1921	*/
1922	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1923	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1924	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1925
1926	/* Relocate GC addresses of Page Tables. */
1927	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1928	{
1929	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1930	{
1931	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1932	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1933	}
1934	}
1935
1936	/*
1937	* Dynamic page mapping area.
1938	*/
1939	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1940	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1941	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1942
1943	/*
1944	* The Zero page.
1945	*/
1946	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1947	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1948
1949	/*
1950	* Physical and virtual handlers.
1951	*/
1952	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1953	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1954	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1955
1956	/*
1957	* The page pool.
1958	*/
1959	pgmR3PoolRelocate(pVM);
1960	}
1961
1962
1963	/**
1964	* Callback function for relocating a physical access handler.
1965	*
1966	* @returns 0 (continue enum)
1967	* @param pNode Pointer to a PGMPHYSHANDLER node.
1968	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1969	* not certain the delta will fit in a void pointer for all possible configs.
1970	*/
1971	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1972	{
1973	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1974	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1975	if (pHandler->pfnHandlerRC)
1976	pHandler->pfnHandlerRC += offDelta;
1977	if (pHandler->pvUserRC >= 0x10000)
1978	pHandler->pvUserRC += offDelta;
1979	return 0;
1980	}
1981
1982
1983	/**
1984	* Callback function for relocating a virtual access handler.
1985	*
1986	* @returns 0 (continue enum)
1987	* @param pNode Pointer to a PGMVIRTHANDLER node.
1988	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1989	* not certain the delta will fit in a void pointer for all possible configs.
1990	*/
1991	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1992	{
1993	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1994	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1995	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1996	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1997	Assert(pHandler->pfnHandlerRC);
1998	pHandler->pfnHandlerRC += offDelta;
1999	return 0;
2000	}
2001
2002
2003	/**
2004	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2005	*
2006	* @returns 0 (continue enum)
2007	* @param pNode Pointer to a PGMVIRTHANDLER node.
2008	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2009	* not certain the delta will fit in a void pointer for all possible configs.
2010	*/
2011	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2012	{
2013	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2014	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2015	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2016	Assert(pHandler->pfnHandlerRC);
2017	pHandler->pfnHandlerRC += offDelta;
2018	return 0;
2019	}
2020
2021
2022	/**
2023	* The VM is being reset.
2024	*
2025	* For the PGM component this means that any PD write monitors
2026	* needs to be removed.
2027	*
2028	* @param pVM VM handle.
2029	*/
2030	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2031	{
2032	LogFlow(("PGMR3Reset:\n"));
2033	VM_ASSERT_EMT(pVM);
2034
2035	pgmLock(pVM);
2036
2037	/*
2038	* Unfix any fixed mappings and disable CR3 monitoring.
2039	*/
2040	pVM->pgm.s.fMappingsFixed = false;
2041	pVM->pgm.s.GCPtrMappingFixed = 0;
2042	pVM->pgm.s.cbMappingFixed = 0;
2043
2044	/* Exit the guest paging mode before the pgm pool gets reset.
2045	* Important to clean up the amd64 case.
2046	*/
2047	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2048	AssertRC(rc);
2049	#ifdef DEBUG
2050	DBGFR3InfoLog(pVM, "mappings", NULL);
2051	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2052	#endif
2053
2054	/*
2055	* Reset the shadow page pool.
2056	*/
2057	pgmR3PoolReset(pVM);
2058
2059	/*
2060	* Re-init other members.
2061	*/
2062	pVM->pgm.s.fA20Enabled = true;
2063
2064	/*
2065	* Clear the FFs PGM owns.
2066	*/
2067	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2068	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2069
2070	/*
2071	* Reset (zero) RAM pages.
2072	*/
2073	rc = pgmR3PhysRamReset(pVM);
2074	if (RT_SUCCESS(rc))
2075	{
2076	#ifdef VBOX_WITH_NEW_PHYS_CODE
2077	/*
2078	* Reset (zero) shadow ROM pages.
2079	*/
2080	rc = pgmR3PhysRomReset(pVM);
2081	#endif
2082	if (RT_SUCCESS(rc))
2083	{
2084	/*
2085	* Switch mode back to real mode.
2086	*/
2087	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2088	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2089	}
2090	}
2091
2092	pgmUnlock(pVM);
2093	//return rc;
2094	AssertReleaseRC(rc);
2095	}
2096
2097
2098	#ifdef VBOX_STRICT
2099	/**
2100	* VM state change callback for clearing fNoMorePhysWrites after
2101	* a snapshot has been created.
2102	*/
2103	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2104	{
2105	if (enmState == VMSTATE_RUNNING)
2106	pVM->pgm.s.fNoMorePhysWrites = false;
2107	}
2108	#endif
2109
2110
2111	/**
2112	* Terminates the PGM.
2113	*
2114	* @returns VBox status code.
2115	* @param pVM Pointer to VM structure.
2116	*/
2117	VMMR3DECL(int) PGMR3Term(PVM pVM)
2118	{
2119	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2120	}
2121
2122
2123	/**
2124	* Terminates the per-VCPU PGM.
2125	*
2126	* Termination means cleaning up and freeing all resources,
2127	* the VM it self is at this point powered off or suspended.
2128	*
2129	* @returns VBox status code.
2130	* @param pVM The VM to operate on.
2131	*/
2132	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2133	{
2134	return 0;
2135	}
2136
2137
2138	/**
2139	* Execute state save operation.
2140	*
2141	* @returns VBox status code.
2142	* @param pVM VM Handle.
2143	* @param pSSM SSM operation handle.
2144	*/
2145	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2146	{
2147	PPGM pPGM = &pVM->pgm.s;
2148
2149	/* No more writes to physical memory after this point! */
2150	pVM->pgm.s.fNoMorePhysWrites = true;
2151
2152	/*
2153	* Save basic data (required / unaffected by relocation).
2154	*/
2155	#if 1
2156	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2157	#else
2158	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2159	#endif
2160	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2161	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2162	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2163	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2164	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2165	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2166	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2167	SSMR3PutU32(pSSM, ~0); /* Separator. */
2168
2169	/*
2170	* The guest mappings.
2171	*/
2172	uint32_t i = 0;
2173	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2174	{
2175	SSMR3PutU32(pSSM, i);
2176	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2177	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2178	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2179	/* flags are done by the mapping owners! */
2180	}
2181	SSMR3PutU32(pSSM, ~0); /* terminator. */
2182
2183	/*
2184	* Ram range flags and bits.
2185	*/
2186	i = 0;
2187	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2188	{
2189	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2190
2191	SSMR3PutU32(pSSM, i);
2192	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2193	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2194	SSMR3PutGCPhys(pSSM, pRam->cb);
2195	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2196
2197	/* Flags. */
2198	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2199	for (unsigned iPage = 0; iPage < cPages; iPage++)
2200	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2201
2202	/* any memory associated with the range. */
2203	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2204	{
2205	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2206	{
2207	if (pRam->paChunkR3Ptrs[iChunk])
2208	{
2209	SSMR3PutU8(pSSM, 1); /* chunk present */
2210	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2211	}
2212	else
2213	SSMR3PutU8(pSSM, 0); /* no chunk present */
2214	}
2215	}
2216	else if (pRam->pvR3)
2217	{
2218	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2219	if (VBOX_FAILURE(rc))
2220	{
2221	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2222	return rc;
2223	}
2224	}
2225	}
2226	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2227	}
2228
2229
2230	/**
2231	* Execute state load operation.
2232	*
2233	* @returns VBox status code.
2234	* @param pVM VM Handle.
2235	* @param pSSM SSM operation handle.
2236	* @param u32Version Data layout version.
2237	*/
2238	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2239	{
2240	/*
2241	* Validate version.
2242	*/
2243	if (u32Version != PGM_SAVED_STATE_VERSION)
2244	{
2245	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2246	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2247	}
2248
2249	/*
2250	* Call the reset function to make sure all the memory is cleared.
2251	*/
2252	PGMR3Reset(pVM);
2253
2254	/*
2255	* Load basic data (required / unaffected by relocation).
2256	*/
2257	PPGM pPGM = &pVM->pgm.s;
2258	#if 1
2259	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2260	#else
2261	uint32_t u;
2262	SSMR3GetU32(pSSM, &u);
2263	pPGM->fMappingsFixed = u;
2264	#endif
2265	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2266	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2267
2268	RTUINT cbRamSize;
2269	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2270	if (VBOX_FAILURE(rc))
2271	return rc;
2272	if (cbRamSize != pPGM->cbRamSize)
2273	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2274	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2275	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2276	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2277	RTUINT uGuestMode;
2278	SSMR3GetUInt(pSSM, &uGuestMode);
2279	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2280
2281	/* check separator. */
2282	uint32_t u32Sep;
2283	SSMR3GetU32(pSSM, &u32Sep);
2284	if (VBOX_FAILURE(rc))
2285	return rc;
2286	if (u32Sep != (uint32_t)~0)
2287	{
2288	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2289	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2290	}
2291
2292	/*
2293	* The guest mappings.
2294	*/
2295	uint32_t i = 0;
2296	for (;; i++)
2297	{
2298	/* Check the seqence number / separator. */
2299	rc = SSMR3GetU32(pSSM, &u32Sep);
2300	if (VBOX_FAILURE(rc))
2301	return rc;
2302	if (u32Sep == ~0U)
2303	break;
2304	if (u32Sep != i)
2305	{
2306	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2307	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2308	}
2309
2310	/* get the mapping details. */
2311	char szDesc[256];
2312	szDesc[0] = '\0';
2313	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2314	if (VBOX_FAILURE(rc))
2315	return rc;
2316	RTGCPTR GCPtr;
2317	SSMR3GetGCPtr(pSSM, &GCPtr);
2318	RTGCUINTPTR cPTs;
2319	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2320	if (VBOX_FAILURE(rc))
2321	return rc;
2322
2323	/* find matching range. */
2324	PPGMMAPPING pMapping;
2325	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2326	if ( pMapping->cPTs == cPTs
2327	&& !strcmp(pMapping->pszDesc, szDesc))
2328	break;
2329	if (!pMapping)
2330	{
2331	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2332	cPTs, szDesc, GCPtr));
2333	AssertFailed();
2334	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2335	}
2336
2337	/* relocate it. */
2338	if (pMapping->GCPtr != GCPtr)
2339	{
2340	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2341	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2342	}
2343	else
2344	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2345	}
2346
2347	/*
2348	* Ram range flags and bits.
2349	*/
2350	i = 0;
2351	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2352	{
2353	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2354	/* Check the seqence number / separator. */
2355	rc = SSMR3GetU32(pSSM, &u32Sep);
2356	if (VBOX_FAILURE(rc))
2357	return rc;
2358	if (u32Sep == ~0U)
2359	break;
2360	if (u32Sep != i)
2361	{
2362	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2363	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2364	}
2365
2366	/* Get the range details. */
2367	RTGCPHYS GCPhys;
2368	SSMR3GetGCPhys(pSSM, &GCPhys);
2369	RTGCPHYS GCPhysLast;
2370	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2371	RTGCPHYS cb;
2372	SSMR3GetGCPhys(pSSM, &cb);
2373	uint8_t fHaveBits;
2374	rc = SSMR3GetU8(pSSM, &fHaveBits);
2375	if (VBOX_FAILURE(rc))
2376	return rc;
2377	if (fHaveBits & ~1)
2378	{
2379	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2380	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2381	}
2382
2383	/* Match it up with the current range. */
2384	if ( GCPhys != pRam->GCPhys
2385	\|\| GCPhysLast != pRam->GCPhysLast
2386	\|\| cb != pRam->cb
2387	\|\| fHaveBits != !!pRam->pvR3)
2388	{
2389	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2390	"State : %RGp-%RGp %RGp bytes %s\n",
2391	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2392	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2393	/*
2394	* If we're loading a state for debugging purpose, don't make a fuss if
2395	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2396	*/
2397	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2398	\|\| GCPhys < 8 * _1M)
2399	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2400
2401	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2402	while (cPages-- > 0)
2403	{
2404	uint16_t u16Ignore;
2405	SSMR3GetU16(pSSM, &u16Ignore);
2406	}
2407	continue;
2408	}
2409
2410	/* Flags. */
2411	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2412	for (unsigned iPage = 0; iPage < cPages; iPage++)
2413	{
2414	uint16_t u16 = 0;
2415	SSMR3GetU16(pSSM, &u16);
2416	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2417	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2418	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2419	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2420	}
2421
2422	/* any memory associated with the range. */
2423	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2424	{
2425	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2426	{
2427	uint8_t fValidChunk;
2428
2429	rc = SSMR3GetU8(pSSM, &fValidChunk);
2430	if (VBOX_FAILURE(rc))
2431	return rc;
2432	if (fValidChunk > 1)
2433	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2434
2435	if (fValidChunk)
2436	{
2437	if (!pRam->paChunkR3Ptrs[iChunk])
2438	{
2439	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2440	if (VBOX_FAILURE(rc))
2441	return rc;
2442	}
2443	Assert(pRam->paChunkR3Ptrs[iChunk]);
2444
2445	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2446	}
2447	/* else nothing to do */
2448	}
2449	}
2450	else if (pRam->pvR3)
2451	{
2452	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2453	if (VBOX_FAILURE(rc))
2454	{
2455	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2456	return rc;
2457	}
2458	}
2459	}
2460
2461	/*
2462	* We require a full resync now.
2463	*/
2464	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2465	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2466	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2467	pPGM->fPhysCacheFlushPending = true;
2468	pgmR3HandlerPhysicalUpdateAll(pVM);
2469
2470	/*
2471	* Change the paging mode.
2472	*/
2473	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2474
2475	/* Restore pVM->pgm.s.GCPhysCR3. */
2476	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2477	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2478	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2479	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2480	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2481	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2482	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2483	else
2484	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2485	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2486
2487	return rc;
2488	}
2489
2490
2491	/**
2492	* Show paging mode.
2493	*
2494	* @param pVM VM Handle.
2495	* @param pHlp The info helpers.
2496	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2497	*/
2498	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2499	{
2500	/* digest argument. */
2501	bool fGuest, fShadow, fHost;
2502	if (pszArgs)
2503	pszArgs = RTStrStripL(pszArgs);
2504	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2505	fShadow = fHost = fGuest = true;
2506	else
2507	{
2508	fShadow = fHost = fGuest = false;
2509	if (strstr(pszArgs, "guest"))
2510	fGuest = true;
2511	if (strstr(pszArgs, "shadow"))
2512	fShadow = true;
2513	if (strstr(pszArgs, "host"))
2514	fHost = true;
2515	}
2516
2517	/* print info. */
2518	if (fGuest)
2519	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2520	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2521	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2522	if (fShadow)
2523	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2524	if (fHost)
2525	{
2526	const char *psz;
2527	switch (pVM->pgm.s.enmHostMode)
2528	{
2529	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2530	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2531	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2532	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2533	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2534	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2535	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2536	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2537	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2538	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2539	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2540	default: psz = "unknown"; break;
2541	}
2542	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2543	}
2544	}
2545
2546
2547	/**
2548	* Dump registered MMIO ranges to the log.
2549	*
2550	* @param pVM VM Handle.
2551	* @param pHlp The info helpers.
2552	* @param pszArgs Arguments, ignored.
2553	*/
2554	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2555	{
2556	NOREF(pszArgs);
2557	pHlp->pfnPrintf(pHlp,
2558	"RAM ranges (pVM=%p)\n"
2559	"%.s %.s\n",
2560	pVM,
2561	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2562	sizeof(RTHCPTR) * 2, "pvHC ");
2563
2564	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2565	pHlp->pfnPrintf(pHlp,
2566	"%RGp-%RGp %RHv %s\n",
2567	pCur->GCPhys,
2568	pCur->GCPhysLast,
2569	pCur->pvR3,
2570	pCur->pszDesc);
2571	}
2572
2573	/**
2574	* Dump the page directory to the log.
2575	*
2576	* @param pVM VM Handle.
2577	* @param pHlp The info helpers.
2578	* @param pszArgs Arguments, ignored.
2579	*/
2580	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2581	{
2582	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2583	/* Big pages supported? */
2584	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2585
2586	/* Global pages supported? */
2587	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2588
2589	NOREF(pszArgs);
2590
2591	/*
2592	* Get page directory addresses.
2593	*/
2594	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2595	Assert(pPDSrc);
2596	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2597
2598	/*
2599	* Iterate the page directory.
2600	*/
2601	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2602	{
2603	X86PDE PdeSrc = pPDSrc->a[iPD];
2604	if (PdeSrc.n.u1Present)
2605	{
2606	if (PdeSrc.b.u1Size && fPSE)
2607	pHlp->pfnPrintf(pHlp,
2608	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2609	iPD,
2610	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2611	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2612	else
2613	pHlp->pfnPrintf(pHlp,
2614	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2615	iPD,
2616	PdeSrc.u & X86_PDE_PG_MASK,
2617	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2618	}
2619	}
2620	}
2621
2622
2623	/**
2624	* Serivce a VMMCALLHOST_PGM_LOCK call.
2625	*
2626	* @returns VBox status code.
2627	* @param pVM The VM handle.
2628	*/
2629	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2630	{
2631	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2632	AssertRC(rc);
2633	return rc;
2634	}
2635
2636
2637	/**
2638	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2639	*
2640	* @returns PGM_TYPE_*.
2641	* @param pgmMode The mode value to convert.
2642	*/
2643	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2644	{
2645	switch (pgmMode)
2646	{
2647	case PGMMODE_REAL: return PGM_TYPE_REAL;
2648	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2649	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2650	case PGMMODE_PAE:
2651	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2652	case PGMMODE_AMD64:
2653	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2654	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2655	case PGMMODE_EPT: return PGM_TYPE_EPT;
2656	default:
2657	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2658	}
2659	}
2660
2661
2662	/**
2663	* Gets the index into the paging mode data array of a SHW+GST mode.
2664	*
2665	* @returns PGM::paPagingData index.
2666	* @param uShwType The shadow paging mode type.
2667	* @param uGstType The guest paging mode type.
2668	*/
2669	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2670	{
2671	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2672	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2673	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2674	+ (uGstType - PGM_TYPE_REAL);
2675	}
2676
2677
2678	/**
2679	* Gets the index into the paging mode data array of a SHW+GST mode.
2680	*
2681	* @returns PGM::paPagingData index.
2682	* @param enmShw The shadow paging mode.
2683	* @param enmGst The guest paging mode.
2684	*/
2685	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2686	{
2687	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2688	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2689	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2690	}
2691
2692
2693	/**
2694	* Calculates the max data index.
2695	* @returns The number of entries in the paging data array.
2696	*/
2697	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2698	{
2699	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2700	}
2701
2702
2703	/**
2704	* Initializes the paging mode data kept in PGM::paModeData.
2705	*
2706	* @param pVM The VM handle.
2707	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2708	* This is used early in the init process to avoid trouble with PDM
2709	* not being initialized yet.
2710	*/
2711	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2712	{
2713	PPGMMODEDATA pModeData;
2714	int rc;
2715
2716	/*
2717	* Allocate the array on the first call.
2718	*/
2719	if (!pVM->pgm.s.paModeData)
2720	{
2721	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2722	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2723	}
2724
2725	/*
2726	* Initialize the array entries.
2727	*/
2728	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2729	pModeData->uShwType = PGM_TYPE_32BIT;
2730	pModeData->uGstType = PGM_TYPE_REAL;
2731	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2732	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2733	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2734
2735	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2736	pModeData->uShwType = PGM_TYPE_32BIT;
2737	pModeData->uGstType = PGM_TYPE_PROT;
2738	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2739	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2740	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2741
2742	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2743	pModeData->uShwType = PGM_TYPE_32BIT;
2744	pModeData->uGstType = PGM_TYPE_32BIT;
2745	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2746	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2747	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2748
2749	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2750	pModeData->uShwType = PGM_TYPE_PAE;
2751	pModeData->uGstType = PGM_TYPE_REAL;
2752	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2753	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755
2756	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2757	pModeData->uShwType = PGM_TYPE_PAE;
2758	pModeData->uGstType = PGM_TYPE_PROT;
2759	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2760	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2761	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2762
2763	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2764	pModeData->uShwType = PGM_TYPE_PAE;
2765	pModeData->uGstType = PGM_TYPE_32BIT;
2766	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2767	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2768	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2769
2770	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2771	pModeData->uShwType = PGM_TYPE_PAE;
2772	pModeData->uGstType = PGM_TYPE_PAE;
2773	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2774	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2775	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2776
2777	#ifdef VBOX_WITH_64_BITS_GUESTS
2778	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2779	pModeData->uShwType = PGM_TYPE_AMD64;
2780	pModeData->uGstType = PGM_TYPE_AMD64;
2781	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2782	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2783	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2784	#endif
2785
2786	/* The nested paging mode. */
2787	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2788	pModeData->uShwType = PGM_TYPE_NESTED;
2789	pModeData->uGstType = PGM_TYPE_REAL;
2790	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2791	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2792
2793	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2794	pModeData->uShwType = PGM_TYPE_NESTED;
2795	pModeData->uGstType = PGM_TYPE_PROT;
2796	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2797	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2798
2799	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2800	pModeData->uShwType = PGM_TYPE_NESTED;
2801	pModeData->uGstType = PGM_TYPE_32BIT;
2802	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2803	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2804
2805	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2806	pModeData->uShwType = PGM_TYPE_NESTED;
2807	pModeData->uGstType = PGM_TYPE_PAE;
2808	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2809	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2810
2811	#ifdef VBOX_WITH_64_BITS_GUESTS
2812	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2813	pModeData->uShwType = PGM_TYPE_NESTED;
2814	pModeData->uGstType = PGM_TYPE_AMD64;
2815	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2816	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2817	#endif
2818
2819	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2820	switch(pVM->pgm.s.enmHostMode)
2821	{
2822	case SUPPAGINGMODE_32_BIT:
2823	case SUPPAGINGMODE_32_BIT_GLOBAL:
2824	#ifdef VBOX_WITH_64_BITS_GUESTS
2825	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2826	#else
2827	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2828	#endif
2829	{
2830	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2831	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2832	}
2833	break;
2834
2835	case SUPPAGINGMODE_PAE:
2836	case SUPPAGINGMODE_PAE_NX:
2837	case SUPPAGINGMODE_PAE_GLOBAL:
2838	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2839	#ifdef VBOX_WITH_64_BITS_GUESTS
2840	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2841	#else
2842	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2843	#endif
2844	{
2845	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2846	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2847	}
2848	break;
2849
2850	case SUPPAGINGMODE_AMD64:
2851	case SUPPAGINGMODE_AMD64_GLOBAL:
2852	case SUPPAGINGMODE_AMD64_NX:
2853	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2854	#ifdef VBOX_WITH_64_BITS_GUESTS
2855	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2856	#else
2857	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2858	#endif
2859	{
2860	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2861	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2862	}
2863	break;
2864	default:
2865	AssertFailed();
2866	break;
2867	}
2868
2869	/* Extended paging (EPT) / Intel VT-x */
2870	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2871	pModeData->uShwType = PGM_TYPE_EPT;
2872	pModeData->uGstType = PGM_TYPE_REAL;
2873	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2874	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2875	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2876
2877	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2878	pModeData->uShwType = PGM_TYPE_EPT;
2879	pModeData->uGstType = PGM_TYPE_PROT;
2880	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2881	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2882	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2883
2884	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2885	pModeData->uShwType = PGM_TYPE_EPT;
2886	pModeData->uGstType = PGM_TYPE_32BIT;
2887	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2888	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2889	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2890
2891	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2892	pModeData->uShwType = PGM_TYPE_EPT;
2893	pModeData->uGstType = PGM_TYPE_PAE;
2894	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2896	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2897
2898	#ifdef VBOX_WITH_64_BITS_GUESTS
2899	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2900	pModeData->uShwType = PGM_TYPE_EPT;
2901	pModeData->uGstType = PGM_TYPE_AMD64;
2902	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2903	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2904	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2905	#endif
2906	return VINF_SUCCESS;
2907	}
2908
2909
2910	/**
2911	* Switch to different (or relocated in the relocate case) mode data.
2912	*
2913	* @param pVM The VM handle.
2914	* @param enmShw The the shadow paging mode.
2915	* @param enmGst The the guest paging mode.
2916	*/
2917	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2918	{
2919	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2920
2921	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2922	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2923
2924	/* shadow */
2925	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2926	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2927	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2928	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2929	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2930
2931	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2932	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2933
2934	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2935	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2936
2937
2938	/* guest */
2939	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2940	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2941	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2942	Assert(pVM->pgm.s.pfnR3GstGetPage);
2943	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2944	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2945	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2946	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2947	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2948	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2949	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2950	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2951	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2952	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2953
2954	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2955	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2956	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2957	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
2958	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
2959	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
2960	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
2961	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
2962	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
2963
2964	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2965	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2966	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2967	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2968	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2969	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2970	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2971	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2972	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2973
2974
2975	/* both */
2976	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2977	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2978	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2979	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2980	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2981	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2982	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2983	#ifdef VBOX_STRICT
2984	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2985	#endif
2986
2987	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2988	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2989	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2990	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2991	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2992	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2993	#ifdef VBOX_STRICT
2994	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2995	#endif
2996
2997	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2998	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2999	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3000	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3001	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3002	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3003	#ifdef VBOX_STRICT
3004	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3005	#endif
3006	}
3007
3008
3009	/**
3010	* Calculates the shadow paging mode.
3011	*
3012	* @returns The shadow paging mode.
3013	* @param pVM VM handle.
3014	* @param enmGuestMode The guest mode.
3015	* @param enmHostMode The host mode.
3016	* @param enmShadowMode The current shadow mode.
3017	* @param penmSwitcher Where to store the switcher to use.
3018	* VMMSWITCHER_INVALID means no change.
3019	*/
3020	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3021	{
3022	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3023	switch (enmGuestMode)
3024	{
3025	/*
3026	* When switching to real or protected mode we don't change
3027	* anything since it's likely that we'll switch back pretty soon.
3028	*
3029	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3030	* and is supposed to determine which shadow paging and switcher to
3031	* use during init.
3032	*/
3033	case PGMMODE_REAL:
3034	case PGMMODE_PROTECTED:
3035	if ( enmShadowMode != PGMMODE_INVALID
3036	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3037	break; /* (no change) */
3038
3039	switch (enmHostMode)
3040	{
3041	case SUPPAGINGMODE_32_BIT:
3042	case SUPPAGINGMODE_32_BIT_GLOBAL:
3043	enmShadowMode = PGMMODE_32_BIT;
3044	enmSwitcher = VMMSWITCHER_32_TO_32;
3045	break;
3046
3047	case SUPPAGINGMODE_PAE:
3048	case SUPPAGINGMODE_PAE_NX:
3049	case SUPPAGINGMODE_PAE_GLOBAL:
3050	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3051	enmShadowMode = PGMMODE_PAE;
3052	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3053	#ifdef DEBUG_bird
3054	if (RTEnvExist("VBOX_32BIT"))
3055	{
3056	enmShadowMode = PGMMODE_32_BIT;
3057	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3058	}
3059	#endif
3060	break;
3061
3062	case SUPPAGINGMODE_AMD64:
3063	case SUPPAGINGMODE_AMD64_GLOBAL:
3064	case SUPPAGINGMODE_AMD64_NX:
3065	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3066	enmShadowMode = PGMMODE_PAE;
3067	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3068	break;
3069
3070	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3071	}
3072	break;
3073
3074	case PGMMODE_32_BIT:
3075	switch (enmHostMode)
3076	{
3077	case SUPPAGINGMODE_32_BIT:
3078	case SUPPAGINGMODE_32_BIT_GLOBAL:
3079	enmShadowMode = PGMMODE_32_BIT;
3080	enmSwitcher = VMMSWITCHER_32_TO_32;
3081	break;
3082
3083	case SUPPAGINGMODE_PAE:
3084	case SUPPAGINGMODE_PAE_NX:
3085	case SUPPAGINGMODE_PAE_GLOBAL:
3086	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3087	enmShadowMode = PGMMODE_PAE;
3088	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3089	#ifdef DEBUG_bird
3090	if (RTEnvExist("VBOX_32BIT"))
3091	{
3092	enmShadowMode = PGMMODE_32_BIT;
3093	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3094	}
3095	#endif
3096	break;
3097
3098	case SUPPAGINGMODE_AMD64:
3099	case SUPPAGINGMODE_AMD64_GLOBAL:
3100	case SUPPAGINGMODE_AMD64_NX:
3101	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3102	enmShadowMode = PGMMODE_PAE;
3103	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3104	break;
3105
3106	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3107	}
3108	break;
3109
3110	case PGMMODE_PAE:
3111	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3112	switch (enmHostMode)
3113	{
3114	case SUPPAGINGMODE_32_BIT:
3115	case SUPPAGINGMODE_32_BIT_GLOBAL:
3116	enmShadowMode = PGMMODE_PAE;
3117	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3118	break;
3119
3120	case SUPPAGINGMODE_PAE:
3121	case SUPPAGINGMODE_PAE_NX:
3122	case SUPPAGINGMODE_PAE_GLOBAL:
3123	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3124	enmShadowMode = PGMMODE_PAE;
3125	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3126	break;
3127
3128	case SUPPAGINGMODE_AMD64:
3129	case SUPPAGINGMODE_AMD64_GLOBAL:
3130	case SUPPAGINGMODE_AMD64_NX:
3131	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3132	enmShadowMode = PGMMODE_PAE;
3133	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3134	break;
3135
3136	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3137	}
3138	break;
3139
3140	case PGMMODE_AMD64:
3141	case PGMMODE_AMD64_NX:
3142	switch (enmHostMode)
3143	{
3144	case SUPPAGINGMODE_32_BIT:
3145	case SUPPAGINGMODE_32_BIT_GLOBAL:
3146	enmShadowMode = PGMMODE_PAE;
3147	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3148	break;
3149
3150	case SUPPAGINGMODE_PAE:
3151	case SUPPAGINGMODE_PAE_NX:
3152	case SUPPAGINGMODE_PAE_GLOBAL:
3153	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3154	enmShadowMode = PGMMODE_PAE;
3155	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3156	break;
3157
3158	case SUPPAGINGMODE_AMD64:
3159	case SUPPAGINGMODE_AMD64_GLOBAL:
3160	case SUPPAGINGMODE_AMD64_NX:
3161	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3162	enmShadowMode = PGMMODE_AMD64;
3163	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3164	break;
3165
3166	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3167	}
3168	break;
3169
3170
3171	default:
3172	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3173	return PGMMODE_INVALID;
3174	}
3175	/* Override the shadow mode is nested paging is active. */
3176	if (HWACCMIsNestedPagingActive(pVM))
3177	enmShadowMode = HWACCMGetPagingMode(pVM);
3178
3179	*penmSwitcher = enmSwitcher;
3180	return enmShadowMode;
3181	}
3182
3183
3184	/**
3185	* Performs the actual mode change.
3186	* This is called by PGMChangeMode and pgmR3InitPaging().
3187	*
3188	* @returns VBox status code.
3189	* @param pVM VM handle.
3190	* @param enmGuestMode The new guest mode. This is assumed to be different from
3191	* the current mode.
3192	*/
3193	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3194	{
3195	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3196	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3197
3198	/*
3199	* Calc the shadow mode and switcher.
3200	*/
3201	VMMSWITCHER enmSwitcher;
3202	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3203	if (enmSwitcher != VMMSWITCHER_INVALID)
3204	{
3205	/*
3206	* Select new switcher.
3207	*/
3208	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3209	if (VBOX_FAILURE(rc))
3210	{
3211	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3212	return rc;
3213	}
3214	}
3215
3216	/*
3217	* Exit old mode(s).
3218	*/
3219	/* shadow */
3220	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3221	{
3222	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3223	if (PGM_SHW_PFN(Exit, pVM))
3224	{
3225	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3226	if (VBOX_FAILURE(rc))
3227	{
3228	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3229	return rc;
3230	}
3231	}
3232
3233	}
3234	else
3235	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3236
3237	/* guest */
3238	if (PGM_GST_PFN(Exit, pVM))
3239	{
3240	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3241	if (VBOX_FAILURE(rc))
3242	{
3243	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3244	return rc;
3245	}
3246	}
3247
3248	/*
3249	* Load new paging mode data.
3250	*/
3251	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3252
3253	/*
3254	* Enter new shadow mode (if changed).
3255	*/
3256	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3257	{
3258	int rc;
3259	pVM->pgm.s.enmShadowMode = enmShadowMode;
3260	switch (enmShadowMode)
3261	{
3262	case PGMMODE_32_BIT:
3263	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3264	break;
3265	case PGMMODE_PAE:
3266	case PGMMODE_PAE_NX:
3267	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3268	break;
3269	case PGMMODE_AMD64:
3270	case PGMMODE_AMD64_NX:
3271	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3272	break;
3273	case PGMMODE_NESTED:
3274	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3275	break;
3276	case PGMMODE_EPT:
3277	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3278	break;
3279	case PGMMODE_REAL:
3280	case PGMMODE_PROTECTED:
3281	default:
3282	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3283	return VERR_INTERNAL_ERROR;
3284	}
3285	if (VBOX_FAILURE(rc))
3286	{
3287	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3288	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3289	return rc;
3290	}
3291	}
3292
3293	/** @todo This is a bug!
3294	*
3295	* We must flush the PGM pool cache if the guest mode changes; we don't always
3296	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3297	* the shadow page tables.
3298	*
3299	* That only applies when switching between paging and non-paging modes.
3300	*/
3301	/** @todo A20 setting */
3302	if ( pVM->pgm.s.CTX_SUFF(pPool)
3303	&& !HWACCMIsNestedPagingActive(pVM)
3304	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3305	{
3306	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3307	pgmPoolFlushAll(pVM);
3308	}
3309
3310	/*
3311	* Enter the new guest and shadow+guest modes.
3312	*/
3313	int rc = -1;
3314	int rc2 = -1;
3315	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3316	pVM->pgm.s.enmGuestMode = enmGuestMode;
3317	switch (enmGuestMode)
3318	{
3319	case PGMMODE_REAL:
3320	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3321	switch (pVM->pgm.s.enmShadowMode)
3322	{
3323	case PGMMODE_32_BIT:
3324	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3325	break;
3326	case PGMMODE_PAE:
3327	case PGMMODE_PAE_NX:
3328	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3329	break;
3330	case PGMMODE_NESTED:
3331	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3332	break;
3333	case PGMMODE_EPT:
3334	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3335	break;
3336	case PGMMODE_AMD64:
3337	case PGMMODE_AMD64_NX:
3338	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3339	default: AssertFailed(); break;
3340	}
3341	break;
3342
3343	case PGMMODE_PROTECTED:
3344	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3345	switch (pVM->pgm.s.enmShadowMode)
3346	{
3347	case PGMMODE_32_BIT:
3348	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3349	break;
3350	case PGMMODE_PAE:
3351	case PGMMODE_PAE_NX:
3352	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3353	break;
3354	case PGMMODE_NESTED:
3355	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3356	break;
3357	case PGMMODE_EPT:
3358	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3359	break;
3360	case PGMMODE_AMD64:
3361	case PGMMODE_AMD64_NX:
3362	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3363	default: AssertFailed(); break;
3364	}
3365	break;
3366
3367	case PGMMODE_32_BIT:
3368	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3369	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3370	switch (pVM->pgm.s.enmShadowMode)
3371	{
3372	case PGMMODE_32_BIT:
3373	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3374	break;
3375	case PGMMODE_PAE:
3376	case PGMMODE_PAE_NX:
3377	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3378	break;
3379	case PGMMODE_NESTED:
3380	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3381	break;
3382	case PGMMODE_EPT:
3383	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3384	break;
3385	case PGMMODE_AMD64:
3386	case PGMMODE_AMD64_NX:
3387	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3388	default: AssertFailed(); break;
3389	}
3390	break;
3391
3392	case PGMMODE_PAE_NX:
3393	case PGMMODE_PAE:
3394	{
3395	uint32_t u32Dummy, u32Features;
3396
3397	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3398	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3399	{
3400	/* Pause first, then inform Main. */
3401	rc = VMR3SuspendNoSave(pVM);
3402	AssertRC(rc);
3403
3404	VMSetRuntimeError(pVM, true, "PAEmode",
3405	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage"));
3406	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3407	return VINF_SUCCESS;
3408	}
3409	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3410	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3411	switch (pVM->pgm.s.enmShadowMode)
3412	{
3413	case PGMMODE_PAE:
3414	case PGMMODE_PAE_NX:
3415	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3416	break;
3417	case PGMMODE_NESTED:
3418	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3419	break;
3420	case PGMMODE_EPT:
3421	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3422	break;
3423	case PGMMODE_32_BIT:
3424	case PGMMODE_AMD64:
3425	case PGMMODE_AMD64_NX:
3426	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3427	default: AssertFailed(); break;
3428	}
3429	break;
3430	}
3431
3432	#ifdef VBOX_WITH_64_BITS_GUESTS
3433	case PGMMODE_AMD64_NX:
3434	case PGMMODE_AMD64:
3435	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3436	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3437	switch (pVM->pgm.s.enmShadowMode)
3438	{
3439	case PGMMODE_AMD64:
3440	case PGMMODE_AMD64_NX:
3441	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3442	break;
3443	case PGMMODE_NESTED:
3444	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3445	break;
3446	case PGMMODE_EPT:
3447	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3448	break;
3449	case PGMMODE_32_BIT:
3450	case PGMMODE_PAE:
3451	case PGMMODE_PAE_NX:
3452	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3453	default: AssertFailed(); break;
3454	}
3455	break;
3456	#endif
3457
3458	default:
3459	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3460	rc = VERR_NOT_IMPLEMENTED;
3461	break;
3462	}
3463
3464	/* status codes. */
3465	AssertRC(rc);
3466	AssertRC(rc2);
3467	if (VBOX_SUCCESS(rc))
3468	{
3469	rc = rc2;
3470	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3471	rc = VINF_SUCCESS;
3472	}
3473
3474	/*
3475	* Notify SELM so it can update the TSSes with correct CR3s.
3476	*/
3477	SELMR3PagingModeChanged(pVM);
3478
3479	/* Notify HWACCM as well. */
3480	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3481	return rc;
3482	}
3483
3484
3485	/**
3486	* Dumps a PAE shadow page table.
3487	*
3488	* @returns VBox status code (VINF_SUCCESS).
3489	* @param pVM The VM handle.
3490	* @param pPT Pointer to the page table.
3491	* @param u64Address The virtual address of the page table starts.
3492	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3493	* @param cMaxDepth The maxium depth.
3494	* @param pHlp Pointer to the output functions.
3495	*/
3496	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3497	{
3498	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3499	{
3500	X86PTEPAE Pte = pPT->a[i];
3501	if (Pte.n.u1Present)
3502	{
3503	pHlp->pfnPrintf(pHlp,
3504	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3505	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3506	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3507	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3508	Pte.n.u1Write ? 'W' : 'R',
3509	Pte.n.u1User ? 'U' : 'S',
3510	Pte.n.u1Accessed ? 'A' : '-',
3511	Pte.n.u1Dirty ? 'D' : '-',
3512	Pte.n.u1Global ? 'G' : '-',
3513	Pte.n.u1WriteThru ? "WT" : "--",
3514	Pte.n.u1CacheDisable? "CD" : "--",
3515	Pte.n.u1PAT ? "AT" : "--",
3516	Pte.n.u1NoExecute ? "NX" : "--",
3517	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3518	Pte.u & RT_BIT(10) ? '1' : '0',
3519	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3520	Pte.u & X86_PTE_PAE_PG_MASK);
3521	}
3522	}
3523	return VINF_SUCCESS;
3524	}
3525
3526
3527	/**
3528	* Dumps a PAE shadow page directory table.
3529	*
3530	* @returns VBox status code (VINF_SUCCESS).
3531	* @param pVM The VM handle.
3532	* @param HCPhys The physical address of the page directory table.
3533	* @param u64Address The virtual address of the page table starts.
3534	* @param cr4 The CR4, PSE is currently used.
3535	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3536	* @param cMaxDepth The maxium depth.
3537	* @param pHlp Pointer to the output functions.
3538	*/
3539	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3540	{
3541	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3542	if (!pPD)
3543	{
3544	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3545	fLongMode ? 16 : 8, u64Address, HCPhys);
3546	return VERR_INVALID_PARAMETER;
3547	}
3548	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3549
3550	int rc = VINF_SUCCESS;
3551	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3552	{
3553	X86PDEPAE Pde = pPD->a[i];
3554	if (Pde.n.u1Present)
3555	{
3556	if (fBigPagesSupported && Pde.b.u1Size)
3557	pHlp->pfnPrintf(pHlp,
3558	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3559	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3560	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3561	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3562	Pde.b.u1Write ? 'W' : 'R',
3563	Pde.b.u1User ? 'U' : 'S',
3564	Pde.b.u1Accessed ? 'A' : '-',
3565	Pde.b.u1Dirty ? 'D' : '-',
3566	Pde.b.u1Global ? 'G' : '-',
3567	Pde.b.u1WriteThru ? "WT" : "--",
3568	Pde.b.u1CacheDisable? "CD" : "--",
3569	Pde.b.u1PAT ? "AT" : "--",
3570	Pde.b.u1NoExecute ? "NX" : "--",
3571	Pde.u & RT_BIT_64(9) ? '1' : '0',
3572	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3573	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3574	Pde.u & X86_PDE_PAE_PG_MASK);
3575	else
3576	{
3577	pHlp->pfnPrintf(pHlp,
3578	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3579	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3580	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3581	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3582	Pde.n.u1Write ? 'W' : 'R',
3583	Pde.n.u1User ? 'U' : 'S',
3584	Pde.n.u1Accessed ? 'A' : '-',
3585	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3586	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3587	Pde.n.u1WriteThru ? "WT" : "--",
3588	Pde.n.u1CacheDisable? "CD" : "--",
3589	Pde.n.u1NoExecute ? "NX" : "--",
3590	Pde.u & RT_BIT_64(9) ? '1' : '0',
3591	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3592	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3593	Pde.u & X86_PDE_PAE_PG_MASK);
3594	if (cMaxDepth >= 1)
3595	{
3596	/** @todo what about using the page pool for mapping PTs? */
3597	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3598	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3599	PX86PTPAE pPT = NULL;
3600	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3601	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3602	else
3603	{
3604	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3605	{
3606	uint64_t off = u64AddressPT - pMap->GCPtr;
3607	if (off < pMap->cb)
3608	{
3609	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3610	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3611	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3612	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3613	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3614	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3615	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3616	}
3617	}
3618	}
3619	int rc2 = VERR_INVALID_PARAMETER;
3620	if (pPT)
3621	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3622	else
3623	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3624	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3625	if (rc2 < rc && VBOX_SUCCESS(rc))
3626	rc = rc2;
3627	}
3628	}
3629	}
3630	}
3631	return rc;
3632	}
3633
3634
3635	/**
3636	* Dumps a PAE shadow page directory pointer table.
3637	*
3638	* @returns VBox status code (VINF_SUCCESS).
3639	* @param pVM The VM handle.
3640	* @param HCPhys The physical address of the page directory pointer table.
3641	* @param u64Address The virtual address of the page table starts.
3642	* @param cr4 The CR4, PSE is currently used.
3643	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3644	* @param cMaxDepth The maxium depth.
3645	* @param pHlp Pointer to the output functions.
3646	*/
3647	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3648	{
3649	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3650	if (!pPDPT)
3651	{
3652	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3653	fLongMode ? 16 : 8, u64Address, HCPhys);
3654	return VERR_INVALID_PARAMETER;
3655	}
3656
3657	int rc = VINF_SUCCESS;
3658	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3659	for (unsigned i = 0; i < c; i++)
3660	{
3661	X86PDPE Pdpe = pPDPT->a[i];
3662	if (Pdpe.n.u1Present)
3663	{
3664	if (fLongMode)
3665	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3666	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3667	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3668	Pdpe.lm.u1Write ? 'W' : 'R',
3669	Pdpe.lm.u1User ? 'U' : 'S',
3670	Pdpe.lm.u1Accessed ? 'A' : '-',
3671	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3672	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3673	Pdpe.lm.u1WriteThru ? "WT" : "--",
3674	Pdpe.lm.u1CacheDisable? "CD" : "--",
3675	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3676	Pdpe.lm.u1NoExecute ? "NX" : "--",
3677	Pdpe.u & RT_BIT(9) ? '1' : '0',
3678	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3679	Pdpe.u & RT_BIT(11) ? '1' : '0',
3680	Pdpe.u & X86_PDPE_PG_MASK);
3681	else
3682	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3683	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3684	i << X86_PDPT_SHIFT,
3685	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3686	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3687	Pdpe.n.u1WriteThru ? "WT" : "--",
3688	Pdpe.n.u1CacheDisable? "CD" : "--",
3689	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3690	Pdpe.u & RT_BIT(9) ? '1' : '0',
3691	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3692	Pdpe.u & RT_BIT(11) ? '1' : '0',
3693	Pdpe.u & X86_PDPE_PG_MASK);
3694	if (cMaxDepth >= 1)
3695	{
3696	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3697	cr4, fLongMode, cMaxDepth - 1, pHlp);
3698	if (rc2 < rc && VBOX_SUCCESS(rc))
3699	rc = rc2;
3700	}
3701	}
3702	}
3703	return rc;
3704	}
3705
3706
3707	/**
3708	* Dumps a 32-bit shadow page table.
3709	*
3710	* @returns VBox status code (VINF_SUCCESS).
3711	* @param pVM The VM handle.
3712	* @param HCPhys The physical address of the table.
3713	* @param cr4 The CR4, PSE is currently used.
3714	* @param cMaxDepth The maxium depth.
3715	* @param pHlp Pointer to the output functions.
3716	*/
3717	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3718	{
3719	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3720	if (!pPML4)
3721	{
3722	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3723	return VERR_INVALID_PARAMETER;
3724	}
3725
3726	int rc = VINF_SUCCESS;
3727	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3728	{
3729	X86PML4E Pml4e = pPML4->a[i];
3730	if (Pml4e.n.u1Present)
3731	{
3732	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3733	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3734	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3735	u64Address,
3736	Pml4e.n.u1Write ? 'W' : 'R',
3737	Pml4e.n.u1User ? 'U' : 'S',
3738	Pml4e.n.u1Accessed ? 'A' : '-',
3739	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3740	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3741	Pml4e.n.u1WriteThru ? "WT" : "--",
3742	Pml4e.n.u1CacheDisable? "CD" : "--",
3743	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3744	Pml4e.n.u1NoExecute ? "NX" : "--",
3745	Pml4e.u & RT_BIT(9) ? '1' : '0',
3746	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3747	Pml4e.u & RT_BIT(11) ? '1' : '0',
3748	Pml4e.u & X86_PML4E_PG_MASK);
3749
3750	if (cMaxDepth >= 1)
3751	{
3752	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3753	if (rc2 < rc && VBOX_SUCCESS(rc))
3754	rc = rc2;
3755	}
3756	}
3757	}
3758	return rc;
3759	}
3760
3761
3762	/**
3763	* Dumps a 32-bit shadow page table.
3764	*
3765	* @returns VBox status code (VINF_SUCCESS).
3766	* @param pVM The VM handle.
3767	* @param pPT Pointer to the page table.
3768	* @param u32Address The virtual address this table starts at.
3769	* @param pHlp Pointer to the output functions.
3770	*/
3771	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3772	{
3773	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3774	{
3775	X86PTE Pte = pPT->a[i];
3776	if (Pte.n.u1Present)
3777	{
3778	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3779	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3780	u32Address + (i << X86_PT_SHIFT),
3781	Pte.n.u1Write ? 'W' : 'R',
3782	Pte.n.u1User ? 'U' : 'S',
3783	Pte.n.u1Accessed ? 'A' : '-',
3784	Pte.n.u1Dirty ? 'D' : '-',
3785	Pte.n.u1Global ? 'G' : '-',
3786	Pte.n.u1WriteThru ? "WT" : "--",
3787	Pte.n.u1CacheDisable? "CD" : "--",
3788	Pte.n.u1PAT ? "AT" : "--",
3789	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3790	Pte.u & RT_BIT(10) ? '1' : '0',
3791	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3792	Pte.u & X86_PDE_PG_MASK);
3793	}
3794	}
3795	return VINF_SUCCESS;
3796	}
3797
3798
3799	/**
3800	* Dumps a 32-bit shadow page directory and page tables.
3801	*
3802	* @returns VBox status code (VINF_SUCCESS).
3803	* @param pVM The VM handle.
3804	* @param cr3 The root of the hierarchy.
3805	* @param cr4 The CR4, PSE is currently used.
3806	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3807	* @param pHlp Pointer to the output functions.
3808	*/
3809	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3810	{
3811	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3812	if (!pPD)
3813	{
3814	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3815	return VERR_INVALID_PARAMETER;
3816	}
3817
3818	int rc = VINF_SUCCESS;
3819	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3820	{
3821	X86PDE Pde = pPD->a[i];
3822	if (Pde.n.u1Present)
3823	{
3824	const uint32_t u32Address = i << X86_PD_SHIFT;
3825	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3826	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3827	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3828	u32Address,
3829	Pde.b.u1Write ? 'W' : 'R',
3830	Pde.b.u1User ? 'U' : 'S',
3831	Pde.b.u1Accessed ? 'A' : '-',
3832	Pde.b.u1Dirty ? 'D' : '-',
3833	Pde.b.u1Global ? 'G' : '-',
3834	Pde.b.u1WriteThru ? "WT" : "--",
3835	Pde.b.u1CacheDisable? "CD" : "--",
3836	Pde.b.u1PAT ? "AT" : "--",
3837	Pde.u & RT_BIT_64(9) ? '1' : '0',
3838	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3839	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3840	Pde.u & X86_PDE4M_PG_MASK);
3841	else
3842	{
3843	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3844	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3845	u32Address,
3846	Pde.n.u1Write ? 'W' : 'R',
3847	Pde.n.u1User ? 'U' : 'S',
3848	Pde.n.u1Accessed ? 'A' : '-',
3849	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3850	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3851	Pde.n.u1WriteThru ? "WT" : "--",
3852	Pde.n.u1CacheDisable? "CD" : "--",
3853	Pde.u & RT_BIT_64(9) ? '1' : '0',
3854	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3855	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3856	Pde.u & X86_PDE_PG_MASK);
3857	if (cMaxDepth >= 1)
3858	{
3859	/** @todo what about using the page pool for mapping PTs? */
3860	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3861	PX86PT pPT = NULL;
3862	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3863	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3864	else
3865	{
3866	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3867	if (u32Address - pMap->GCPtr < pMap->cb)
3868	{
3869	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3870	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3871	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3872	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3873	pPT = pMap->aPTs[iPDE].pPTR3;
3874	}
3875	}
3876	int rc2 = VERR_INVALID_PARAMETER;
3877	if (pPT)
3878	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3879	else
3880	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3881	if (rc2 < rc && VBOX_SUCCESS(rc))
3882	rc = rc2;
3883	}
3884	}
3885	}
3886	}
3887
3888	return rc;
3889	}
3890
3891
3892	/**
3893	* Dumps a 32-bit shadow page table.
3894	*
3895	* @returns VBox status code (VINF_SUCCESS).
3896	* @param pVM The VM handle.
3897	* @param pPT Pointer to the page table.
3898	* @param u32Address The virtual address this table starts at.
3899	* @param PhysSearch Address to search for.
3900	*/
3901	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3902	{
3903	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3904	{
3905	X86PTE Pte = pPT->a[i];
3906	if (Pte.n.u1Present)
3907	{
3908	Log(( /P R S A D G WT CD AT NX 4M a m d /
3909	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3910	u32Address + (i << X86_PT_SHIFT),
3911	Pte.n.u1Write ? 'W' : 'R',
3912	Pte.n.u1User ? 'U' : 'S',
3913	Pte.n.u1Accessed ? 'A' : '-',
3914	Pte.n.u1Dirty ? 'D' : '-',
3915	Pte.n.u1Global ? 'G' : '-',
3916	Pte.n.u1WriteThru ? "WT" : "--",
3917	Pte.n.u1CacheDisable? "CD" : "--",
3918	Pte.n.u1PAT ? "AT" : "--",
3919	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3920	Pte.u & RT_BIT(10) ? '1' : '0',
3921	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3922	Pte.u & X86_PDE_PG_MASK));
3923
3924	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3925	{
3926	uint64_t fPageShw = 0;
3927	RTHCPHYS pPhysHC = 0;
3928
3929	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3930	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3931	}
3932	}
3933	}
3934	return VINF_SUCCESS;
3935	}
3936
3937
3938	/**
3939	* Dumps a 32-bit guest page directory and page tables.
3940	*
3941	* @returns VBox status code (VINF_SUCCESS).
3942	* @param pVM The VM handle.
3943	* @param cr3 The root of the hierarchy.
3944	* @param cr4 The CR4, PSE is currently used.
3945	* @param PhysSearch Address to search for.
3946	*/
3947	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3948	{
3949	bool fLongMode = false;
3950	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3951	PX86PD pPD = 0;
3952
3953	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3954	if (VBOX_FAILURE(rc) \|\| !pPD)
3955	{
3956	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3957	return VERR_INVALID_PARAMETER;
3958	}
3959
3960	Log(("cr3=%08x cr4=%08x%s\n"
3961	"%-*s P - Present\n"
3962	"%-*s \| R/W - Read (0) / Write (1)\n"
3963	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3964	"%-*s \| \| \| A - Accessed\n"
3965	"%-*s \| \| \| \| D - Dirty\n"
3966	"%-*s \| \| \| \| \| G - Global\n"
3967	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3968	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3969	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3970	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3971	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3972	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3973	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3974	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3975	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3976	- W U - - - -- -- -- -- -- 010 */
3977	, cr3, cr4, fLongMode ? " Long Mode" : "",
3978	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3979	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3980
3981	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3982	{
3983	X86PDE Pde = pPD->a[i];
3984	if (Pde.n.u1Present)
3985	{
3986	const uint32_t u32Address = i << X86_PD_SHIFT;
3987
3988	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3989	Log(( /P R S A D G WT CD AT NX 4M a m d /
3990	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3991	u32Address,
3992	Pde.b.u1Write ? 'W' : 'R',
3993	Pde.b.u1User ? 'U' : 'S',
3994	Pde.b.u1Accessed ? 'A' : '-',
3995	Pde.b.u1Dirty ? 'D' : '-',
3996	Pde.b.u1Global ? 'G' : '-',
3997	Pde.b.u1WriteThru ? "WT" : "--",
3998	Pde.b.u1CacheDisable? "CD" : "--",
3999	Pde.b.u1PAT ? "AT" : "--",
4000	Pde.u & RT_BIT(9) ? '1' : '0',
4001	Pde.u & RT_BIT(10) ? '1' : '0',
4002	Pde.u & RT_BIT(11) ? '1' : '0',
4003	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4004	/** @todo PhysSearch */
4005	else
4006	{
4007	Log(( /P R S A D G WT CD AT NX 4M a m d /
4008	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4009	u32Address,
4010	Pde.n.u1Write ? 'W' : 'R',
4011	Pde.n.u1User ? 'U' : 'S',
4012	Pde.n.u1Accessed ? 'A' : '-',
4013	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4014	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4015	Pde.n.u1WriteThru ? "WT" : "--",
4016	Pde.n.u1CacheDisable? "CD" : "--",
4017	Pde.u & RT_BIT(9) ? '1' : '0',
4018	Pde.u & RT_BIT(10) ? '1' : '0',
4019	Pde.u & RT_BIT(11) ? '1' : '0',
4020	Pde.u & X86_PDE_PG_MASK));
4021	////if (cMaxDepth >= 1)
4022	{
4023	/** @todo what about using the page pool for mapping PTs? */
4024	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4025	PX86PT pPT = NULL;
4026
4027	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4028
4029	int rc2 = VERR_INVALID_PARAMETER;
4030	if (pPT)
4031	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4032	else
4033	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4034	if (rc2 < rc && VBOX_SUCCESS(rc))
4035	rc = rc2;
4036	}
4037	}
4038	}
4039	}
4040
4041	return rc;
4042	}
4043
4044
4045	/**
4046	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4047	*
4048	* @returns VBox status code (VINF_SUCCESS).
4049	* @param pVM The VM handle.
4050	* @param cr3 The root of the hierarchy.
4051	* @param cr4 The cr4, only PAE and PSE is currently used.
4052	* @param fLongMode Set if long mode, false if not long mode.
4053	* @param cMaxDepth Number of levels to dump.
4054	* @param pHlp Pointer to the output functions.
4055	*/
4056	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4057	{
4058	if (!pHlp)
4059	pHlp = DBGFR3InfoLogHlp();
4060	if (!cMaxDepth)
4061	return VINF_SUCCESS;
4062	const unsigned cch = fLongMode ? 16 : 8;
4063	pHlp->pfnPrintf(pHlp,
4064	"cr3=%08x cr4=%08x%s\n"
4065	"%-*s P - Present\n"
4066	"%-*s \| R/W - Read (0) / Write (1)\n"
4067	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4068	"%-*s \| \| \| A - Accessed\n"
4069	"%-*s \| \| \| \| D - Dirty\n"
4070	"%-*s \| \| \| \| \| G - Global\n"
4071	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4072	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4073	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4074	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4075	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4076	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4077	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4078	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4079	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4080	- W U - - - -- -- -- -- -- 010 */
4081	, cr3, cr4, fLongMode ? " Long Mode" : "",
4082	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4083	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4084	if (cr4 & X86_CR4_PAE)
4085	{
4086	if (fLongMode)
4087	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4088	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4089	}
4090	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4091	}
4092
4093	#ifdef VBOX_WITH_DEBUGGER
4094
4095	/**
4096	* The '.pgmram' command.
4097	*
4098	* @returns VBox status.
4099	* @param pCmd Pointer to the command descriptor (as registered).
4100	* @param pCmdHlp Pointer to command helper functions.
4101	* @param pVM Pointer to the current VM (if any).
4102	* @param paArgs Pointer to (readonly) array of arguments.
4103	* @param cArgs Number of arguments in the array.
4104	*/
4105	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4106	{
4107	/*
4108	* Validate input.
4109	*/
4110	if (!pVM)
4111	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4112	if (!pVM->pgm.s.pRamRangesRC)
4113	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4114
4115	/*
4116	* Dump the ranges.
4117	*/
4118	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4119	PPGMRAMRANGE pRam;
4120	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4121	{
4122	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4123	"%RGp - %RGp %p\n",
4124	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4125	if (VBOX_FAILURE(rc))
4126	return rc;
4127	}
4128
4129	return VINF_SUCCESS;
4130	}
4131
4132
4133	/**
4134	* The '.pgmmap' command.
4135	*
4136	* @returns VBox status.
4137	* @param pCmd Pointer to the command descriptor (as registered).
4138	* @param pCmdHlp Pointer to command helper functions.
4139	* @param pVM Pointer to the current VM (if any).
4140	* @param paArgs Pointer to (readonly) array of arguments.
4141	* @param cArgs Number of arguments in the array.
4142	*/
4143	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4144	{
4145	/*
4146	* Validate input.
4147	*/
4148	if (!pVM)
4149	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4150	if (!pVM->pgm.s.pMappingsR3)
4151	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4152
4153	/*
4154	* Print message about the fixedness of the mappings.
4155	*/
4156	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4157	if (VBOX_FAILURE(rc))
4158	return rc;
4159
4160	/*
4161	* Dump the ranges.
4162	*/
4163	PPGMMAPPING pCur;
4164	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4165	{
4166	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4167	"%08x - %08x %s\n",
4168	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4169	if (VBOX_FAILURE(rc))
4170	return rc;
4171	}
4172
4173	return VINF_SUCCESS;
4174	}
4175
4176
4177	/**
4178	* The '.pgmsync' command.
4179	*
4180	* @returns VBox status.
4181	* @param pCmd Pointer to the command descriptor (as registered).
4182	* @param pCmdHlp Pointer to command helper functions.
4183	* @param pVM Pointer to the current VM (if any).
4184	* @param paArgs Pointer to (readonly) array of arguments.
4185	* @param cArgs Number of arguments in the array.
4186	*/
4187	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4188	{
4189	/*
4190	* Validate input.
4191	*/
4192	if (!pVM)
4193	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4194
4195	/*
4196	* Force page directory sync.
4197	*/
4198	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4199
4200	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4201	if (VBOX_FAILURE(rc))
4202	return rc;
4203
4204	return VINF_SUCCESS;
4205	}
4206
4207
4208	#ifdef VBOX_STRICT
4209	/**
4210	* The '.pgmassertcr3' command.
4211	*
4212	* @returns VBox status.
4213	* @param pCmd Pointer to the command descriptor (as registered).
4214	* @param pCmdHlp Pointer to command helper functions.
4215	* @param pVM Pointer to the current VM (if any).
4216	* @param paArgs Pointer to (readonly) array of arguments.
4217	* @param cArgs Number of arguments in the array.
4218	*/
4219	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4220	{
4221	/*
4222	* Validate input.
4223	*/
4224	if (!pVM)
4225	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4226
4227	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4228	if (VBOX_FAILURE(rc))
4229	return rc;
4230
4231	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4232
4233	return VINF_SUCCESS;
4234	}
4235	#endif /* VBOX_STRICT */
4236
4237
4238	/**
4239	* The '.pgmsyncalways' command.
4240	*
4241	* @returns VBox status.
4242	* @param pCmd Pointer to the command descriptor (as registered).
4243	* @param pCmdHlp Pointer to command helper functions.
4244	* @param pVM Pointer to the current VM (if any).
4245	* @param paArgs Pointer to (readonly) array of arguments.
4246	* @param cArgs Number of arguments in the array.
4247	*/
4248	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4249	{
4250	/*
4251	* Validate input.
4252	*/
4253	if (!pVM)
4254	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4255
4256	/*
4257	* Force page directory sync.
4258	*/
4259	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4260	{
4261	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4262	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4263	}
4264	else
4265	{
4266	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4267	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4268	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4269	}
4270	}
4271
4272	#endif /* VBOX_WITH_DEBUGGER */
4273
4274	/**
4275	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4276	*/
4277	typedef struct PGMCHECKINTARGS
4278	{
4279	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4280	PPGMPHYSHANDLER pPrevPhys;
4281	PPGMVIRTHANDLER pPrevVirt;
4282	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4283	PVM pVM;
4284	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4285
4286	/**
4287	* Validate a node in the physical handler tree.
4288	*
4289	* @returns 0 on if ok, other wise 1.
4290	* @param pNode The handler node.
4291	* @param pvUser pVM.
4292	*/
4293	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4294	{
4295	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4296	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4297	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4298	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4299	AssertReleaseMsg( !pArgs->pPrevPhys
4300	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4301	("pPrevPhys=%p %VGp-%VGp %s\n"
4302	" pCur=%p %VGp-%VGp %s\n",
4303	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4304	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4305	pArgs->pPrevPhys = pCur;
4306	return 0;
4307	}
4308
4309
4310	/**
4311	* Validate a node in the virtual handler tree.
4312	*
4313	* @returns 0 on if ok, other wise 1.
4314	* @param pNode The handler node.
4315	* @param pvUser pVM.
4316	*/
4317	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4318	{
4319	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4320	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4321	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4322	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4323	AssertReleaseMsg( !pArgs->pPrevVirt
4324	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4325	("pPrevVirt=%p %VGv-%VGv %s\n"
4326	" pCur=%p %VGv-%VGv %s\n",
4327	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4328	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4329	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4330	{
4331	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4332	("pCur=%p %VGv-%VGv %s\n"
4333	"iPage=%d offVirtHandle=%#x expected %#x\n",
4334	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4335	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4336	}
4337	pArgs->pPrevVirt = pCur;
4338	return 0;
4339	}
4340
4341
4342	/**
4343	* Validate a node in the virtual handler tree.
4344	*
4345	* @returns 0 on if ok, other wise 1.
4346	* @param pNode The handler node.
4347	* @param pvUser pVM.
4348	*/
4349	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4350	{
4351	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4352	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4353	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4354	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4355	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4356	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4357	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4358	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4359	" pCur=%p %VGp-%VGp\n",
4360	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4361	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4362	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4363	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4364	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4365	" pCur=%p %VGp-%VGp\n",
4366	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4367	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4368	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4369	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4370	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4371	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4372	{
4373	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4374	for (;;)
4375	{
4376	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4377	AssertReleaseMsg(pCur2 != pCur,
4378	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4379	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4380	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4381	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4382	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4383	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4384	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4385	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4386	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4387	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4388	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4389	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4390	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4391	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4392	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4393	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4394	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4395	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4396	break;
4397	}
4398	}
4399
4400	pArgs->pPrevPhys2Virt = pCur;
4401	return 0;
4402	}
4403
4404
4405	/**
4406	* Perform an integrity check on the PGM component.
4407	*
4408	* @returns VINF_SUCCESS if everything is fine.
4409	* @returns VBox error status after asserting on integrity breach.
4410	* @param pVM The VM handle.
4411	*/
4412	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4413	{
4414	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4415
4416	/*
4417	* Check the trees.
4418	*/
4419	int cErrors = 0;
4420	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4421	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4422	PGMCHECKINTARGS Args = s_LeftToRight;
4423	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4424	Args = s_RightToLeft;
4425	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4426	Args = s_LeftToRight;
4427	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4428	Args = s_RightToLeft;
4429	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4430	Args = s_LeftToRight;
4431	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4432	Args = s_RightToLeft;
4433	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4434	Args = s_LeftToRight;
4435	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4436	Args = s_RightToLeft;
4437	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4438
4439	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4440	}
4441
4442
4443	/**
4444	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4445	*
4446	* @returns VBox status code.
4447	* @param pVM VM handle.
4448	* @param fEnable Enable or disable shadow mappings
4449	*/
4450	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4451	{
4452	pVM->pgm.s.fDisableMappings = !fEnable;
4453
4454	uint32_t cb;
4455	int rc = PGMR3MappingsSize(pVM, &cb);
4456	AssertRCReturn(rc, rc);
4457
4458	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4459	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4460	AssertRCReturn(rc, rc);
4461
4462	return VINF_SUCCESS;
4463	}
4464

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 13813

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