PGM.cpp@ 12681

Last change on this file since 12681 was 12681, checked in by vboxsync, 16 years ago
Updates for real and protected mode without paging shadow mode.
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1	/* $Id: PGM.cpp 12681 2008-09-24 11:51:10Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pgm_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pgm_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPT and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pgm_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgmPhys PGMPhys - Physical Guest Memory Management.
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485	* memory context for the HWACCM execution.
486	*
487	*
488	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489	*
490	* We've considered implementing the ring-3 mapping cache page based but found
491	* that this was bother some when one had to take into account TLBs+SMP and
492	* portability (missing the necessary APIs on several platforms). There were
493	* also some performance concerns with this approach which hadn't quite been
494	* worked out.
495	*
496	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500	* costly than a single page, although how much more costly is uncertain. We'll
501	* try address this by using a very big cache, preferably bigger than the actual
502	* VM RAM size if possible. The current VM RAM sizes should give some idea for
503	* 32-bit boxes, while on 64-bit we can probably get away with employing an
504	* unlimited cache.
505	*
506	* The cache have to parts, as already indicated, the ring-3 side and the
507	* ring-0 side.
508	*
509	* The ring-0 will be tied to the page allocator since it will operate on the
510	* memory objects it contains. It will therefore require the first ring-0 mutex
511	* discussed in @ref subsec_pgmPhys_Serializing. We
512	* some double house keeping wrt to who has mapped what I think, since both
513	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514	*
515	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516	* require anyone that desires to do changes to the mapping cache to do that
517	* from within this critsect. Alternatively, we could employ a separate critsect
518	* for serializing changes to the mapping cache as this would reduce potential
519	* contention with other threads accessing mappings unrelated to the changes
520	* that are in process. We can see about this later, contention will show
521	* up in the statistics anyway, so it'll be simple to tell.
522	*
523	* The organization of the ring-3 part will be very much like how the allocation
524	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525	* having to walk the tree all the time, we'll have a couple of lookaside entries
526	* like in we do for I/O ports and MMIO in IOM.
527	*
528	* The simplified flow of a PGMPhysRead/Write function:
529	* -# Enter the PGM critsect.
530	* -# Lookup GCPhys in the ram ranges and get the Page ID.
531	* -# Calc the Allocation Chunk ID from the Page ID.
532	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533	* If not found in cache:
534	* -# Call ring-0 and request it to be mapped and supply
535	* a chunk to be unmapped if the cache is maxed out already.
536	* -# Insert the new mapping into the AVL tree (id + R3 address).
537	* -# Update the relevant lookaside entry and return the mapping address.
538	* -# Do the read/write according to monitoring flags and everything.
539	* -# Leave the critsect.
540	*
541	*
542	* @section sec_pgmPhys_Fallback Fallback
543	*
544	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545	* API and thus require a fallback.
546	*
547	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548	* will return to the ring-3 caller (and later ring-0) and asking it to seed
549	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551	* "SeededAllocPages" call to ring-0.
552	*
553	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554	* all page sharing (zero page detection will continue). It will also force
555	* all allocations to come from the VM which seeded the page. Both these
556	* measures are taken to make sure that there will never be any need for
557	* mapping anything into ring-3 - everything will be mapped already.
558	*
559	* Whether we'll continue to use the current MM locked memory management
560	* for this I don't quite know (I'd prefer not to and just ditch that all
561	* togther), we'll see what's simplest to do.
562	*
563	*
564	*
565	* @section sec_pgmPhys_Changes Changes
566	*
567	* Breakdown of the changes involved?
568	*/
569
570
571	/** Saved state data unit version. */
572	#define PGM_SAVED_STATE_VERSION 6
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#include <VBox/param.h>
602	#include <VBox/err.h>
603
604
605
606	/*******************************************************************************
607	* Internal Functions *
608	*******************************************************************************/
609	static int pgmR3InitPaging(PVM pVM);
610	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
611	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
612	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
613	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
614	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
615	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
616	#ifdef VBOX_STRICT
617	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
618	#endif
619	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
620	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
621	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
622	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
623	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
624
625	#ifdef VBOX_WITH_STATISTICS
626	static void pgmR3InitStats(PVM pVM);
627	#endif
628
629	#ifdef VBOX_WITH_DEBUGGER
630	/** @todo all but the two last commands must be converted to 'info'. */
631	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
632	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
633	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
634	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	# ifdef VBOX_STRICT
636	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637	# endif
638	#endif
639
640
641	/*******************************************************************************
642	* Global Variables *
643	*******************************************************************************/
644	#ifdef VBOX_WITH_DEBUGGER
645	/** Command descriptors. */
646	static const DBGCCMD g_aCmds[] =
647	{
648	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
649	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
650	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
651	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
652	#ifdef VBOX_STRICT
653	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
654	#endif
655	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
656	};
657	#endif
658
659
660
661
662	/*
663	* Shadow - 32-bit mode
664	*/
665	#define PGM_SHW_TYPE PGM_TYPE_32BIT
666	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
667	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
668	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
669	#include "PGMShw.h"
670
671	/* Guest - real mode */
672	#define PGM_GST_TYPE PGM_TYPE_REAL
673	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
674	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
675	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
676	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
677	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
678	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
679	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
680	#include "PGMGst.h"
681	#include "PGMBth.h"
682	#undef BTH_PGMPOOLKIND_PT_FOR_PT
683	#undef PGM_BTH_NAME
684	#undef PGM_BTH_NAME_GC_STR
685	#undef PGM_BTH_NAME_R0_STR
686	#undef PGM_GST_TYPE
687	#undef PGM_GST_NAME
688	#undef PGM_GST_NAME_GC_STR
689	#undef PGM_GST_NAME_R0_STR
690
691	/* Guest - protected mode */
692	#define PGM_GST_TYPE PGM_TYPE_PROT
693	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
694	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
695	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
696	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
697	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
698	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
699	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
700	#include "PGMGst.h"
701	#include "PGMBth.h"
702	#undef BTH_PGMPOOLKIND_PT_FOR_PT
703	#undef PGM_BTH_NAME
704	#undef PGM_BTH_NAME_GC_STR
705	#undef PGM_BTH_NAME_R0_STR
706	#undef PGM_GST_TYPE
707	#undef PGM_GST_NAME
708	#undef PGM_GST_NAME_GC_STR
709	#undef PGM_GST_NAME_R0_STR
710
711	/* Guest - 32-bit mode */
712	#define PGM_GST_TYPE PGM_TYPE_32BIT
713	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
714	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
715	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
716	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
717	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
718	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
719	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
720	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
721	#include "PGMGst.h"
722	#include "PGMBth.h"
723	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
724	#undef BTH_PGMPOOLKIND_PT_FOR_PT
725	#undef PGM_BTH_NAME
726	#undef PGM_BTH_NAME_GC_STR
727	#undef PGM_BTH_NAME_R0_STR
728	#undef PGM_GST_TYPE
729	#undef PGM_GST_NAME
730	#undef PGM_GST_NAME_GC_STR
731	#undef PGM_GST_NAME_R0_STR
732
733	#undef PGM_SHW_TYPE
734	#undef PGM_SHW_NAME
735	#undef PGM_SHW_NAME_GC_STR
736	#undef PGM_SHW_NAME_R0_STR
737
738
739	/*
740	* Shadow - PAE mode
741	*/
742	#define PGM_SHW_TYPE PGM_TYPE_PAE
743	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
744	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
745	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
746	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
747	#include "PGMShw.h"
748
749	/* Guest - real mode */
750	#define PGM_GST_TYPE PGM_TYPE_REAL
751	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
752	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
753	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
754	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
755	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
756	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
757	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
758	#include "PGMBth.h"
759	#undef BTH_PGMPOOLKIND_PT_FOR_PT
760	#undef PGM_BTH_NAME
761	#undef PGM_BTH_NAME_GC_STR
762	#undef PGM_BTH_NAME_R0_STR
763	#undef PGM_GST_TYPE
764	#undef PGM_GST_NAME
765	#undef PGM_GST_NAME_GC_STR
766	#undef PGM_GST_NAME_R0_STR
767
768	/* Guest - protected mode */
769	#define PGM_GST_TYPE PGM_TYPE_PROT
770	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
771	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
772	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
773	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
774	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
775	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
776	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
777	#include "PGMBth.h"
778	#undef BTH_PGMPOOLKIND_PT_FOR_PT
779	#undef PGM_BTH_NAME
780	#undef PGM_BTH_NAME_GC_STR
781	#undef PGM_BTH_NAME_R0_STR
782	#undef PGM_GST_TYPE
783	#undef PGM_GST_NAME
784	#undef PGM_GST_NAME_GC_STR
785	#undef PGM_GST_NAME_R0_STR
786
787	/* Guest - 32-bit mode */
788	#define PGM_GST_TYPE PGM_TYPE_32BIT
789	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
790	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
791	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
792	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
793	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
794	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
795	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
796	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
797	#include "PGMBth.h"
798	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
799	#undef BTH_PGMPOOLKIND_PT_FOR_PT
800	#undef PGM_BTH_NAME
801	#undef PGM_BTH_NAME_GC_STR
802	#undef PGM_BTH_NAME_R0_STR
803	#undef PGM_GST_TYPE
804	#undef PGM_GST_NAME
805	#undef PGM_GST_NAME_GC_STR
806	#undef PGM_GST_NAME_R0_STR
807
808	/* Guest - PAE mode */
809	#define PGM_GST_TYPE PGM_TYPE_PAE
810	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
811	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
812	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
813	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
814	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
815	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
816	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
817	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
818	#include "PGMGst.h"
819	#include "PGMBth.h"
820	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
821	#undef BTH_PGMPOOLKIND_PT_FOR_PT
822	#undef PGM_BTH_NAME
823	#undef PGM_BTH_NAME_GC_STR
824	#undef PGM_BTH_NAME_R0_STR
825	#undef PGM_GST_TYPE
826	#undef PGM_GST_NAME
827	#undef PGM_GST_NAME_GC_STR
828	#undef PGM_GST_NAME_R0_STR
829
830	#undef PGM_SHW_TYPE
831	#undef PGM_SHW_NAME
832	#undef PGM_SHW_NAME_GC_STR
833	#undef PGM_SHW_NAME_R0_STR
834
835
836	/*
837	* Shadow - AMD64 mode
838	*/
839	#define PGM_SHW_TYPE PGM_TYPE_AMD64
840	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
841	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
842	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
843	#include "PGMShw.h"
844
845	/* Guest - AMD64 mode */
846	#define PGM_GST_TYPE PGM_TYPE_AMD64
847	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
848	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
849	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
850	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
851	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
852	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
853	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
854	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
855	#include "PGMGst.h"
856	#include "PGMBth.h"
857	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
858	#undef BTH_PGMPOOLKIND_PT_FOR_PT
859	#undef PGM_BTH_NAME
860	#undef PGM_BTH_NAME_GC_STR
861	#undef PGM_BTH_NAME_R0_STR
862	#undef PGM_GST_TYPE
863	#undef PGM_GST_NAME
864	#undef PGM_GST_NAME_GC_STR
865	#undef PGM_GST_NAME_R0_STR
866
867	#undef PGM_SHW_TYPE
868	#undef PGM_SHW_NAME
869	#undef PGM_SHW_NAME_GC_STR
870	#undef PGM_SHW_NAME_R0_STR
871
872	/*
873	* Shadow - Nested paging mode
874	*/
875	#define PGM_SHW_TYPE PGM_TYPE_NESTED
876	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
877	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_NESTED_STR(name)
878	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
879	#include "PGMShw.h"
880
881	/* Guest - real mode */
882	#define PGM_GST_TYPE PGM_TYPE_REAL
883	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
884	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
885	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
886	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
887	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_REAL_STR(name)
888	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
889	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
890	#include "PGMBth.h"
891	#undef BTH_PGMPOOLKIND_PT_FOR_PT
892	#undef PGM_BTH_NAME
893	#undef PGM_BTH_NAME_GC_STR
894	#undef PGM_BTH_NAME_R0_STR
895	#undef PGM_GST_TYPE
896	#undef PGM_GST_NAME
897	#undef PGM_GST_NAME_GC_STR
898	#undef PGM_GST_NAME_R0_STR
899
900	/* Guest - protected mode */
901	#define PGM_GST_TYPE PGM_TYPE_PROT
902	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
903	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
904	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
905	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
906	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PROT_STR(name)
907	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
908	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
909	#include "PGMBth.h"
910	#undef BTH_PGMPOOLKIND_PT_FOR_PT
911	#undef PGM_BTH_NAME
912	#undef PGM_BTH_NAME_GC_STR
913	#undef PGM_BTH_NAME_R0_STR
914	#undef PGM_GST_TYPE
915	#undef PGM_GST_NAME
916	#undef PGM_GST_NAME_GC_STR
917	#undef PGM_GST_NAME_R0_STR
918
919	/* Guest - 32-bit mode */
920	#define PGM_GST_TYPE PGM_TYPE_32BIT
921	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
922	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
923	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
924	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
925	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_32BIT_STR(name)
926	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
927	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
928	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
929	#include "PGMBth.h"
930	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
931	#undef BTH_PGMPOOLKIND_PT_FOR_PT
932	#undef PGM_BTH_NAME
933	#undef PGM_BTH_NAME_GC_STR
934	#undef PGM_BTH_NAME_R0_STR
935	#undef PGM_GST_TYPE
936	#undef PGM_GST_NAME
937	#undef PGM_GST_NAME_GC_STR
938	#undef PGM_GST_NAME_R0_STR
939
940	/* Guest - PAE mode */
941	#define PGM_GST_TYPE PGM_TYPE_PAE
942	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
943	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
944	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
945	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
946	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PAE_STR(name)
947	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
948	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
949	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
950	#include "PGMBth.h"
951	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
952	#undef BTH_PGMPOOLKIND_PT_FOR_PT
953	#undef PGM_BTH_NAME
954	#undef PGM_BTH_NAME_GC_STR
955	#undef PGM_BTH_NAME_R0_STR
956	#undef PGM_GST_TYPE
957	#undef PGM_GST_NAME
958	#undef PGM_GST_NAME_GC_STR
959	#undef PGM_GST_NAME_R0_STR
960
961	/* Guest - AMD64 mode */
962	#define PGM_GST_TYPE PGM_TYPE_AMD64
963	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
964	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
965	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
966	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
967	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_AMD64_STR(name)
968	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
969	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
970	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
971	#include "PGMBth.h"
972	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
973	#undef BTH_PGMPOOLKIND_PT_FOR_PT
974	#undef PGM_BTH_NAME
975	#undef PGM_BTH_NAME_GC_STR
976	#undef PGM_BTH_NAME_R0_STR
977	#undef PGM_GST_TYPE
978	#undef PGM_GST_NAME
979	#undef PGM_GST_NAME_GC_STR
980	#undef PGM_GST_NAME_R0_STR
981
982	#undef PGM_SHW_TYPE
983	#undef PGM_SHW_NAME
984	#undef PGM_SHW_NAME_GC_STR
985	#undef PGM_SHW_NAME_R0_STR
986
987
988	#ifdef PGM_WITH_EPT
989	/*
990	* Shadow - EPT
991	*/
992	#define PGM_SHW_TYPE PGM_TYPE_EPT
993	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
994	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_EPT_STR(name)
995	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
996	#include "PGMShw.h"
997
998	/* Guest - real mode */
999	#define PGM_GST_TYPE PGM_TYPE_REAL
1000	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1001	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
1002	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1003	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1004	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_REAL_STR(name)
1005	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1006	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1007	#include "PGMBth.h"
1008	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1009	#undef PGM_BTH_NAME
1010	#undef PGM_BTH_NAME_GC_STR
1011	#undef PGM_BTH_NAME_R0_STR
1012	#undef PGM_GST_TYPE
1013	#undef PGM_GST_NAME
1014	#undef PGM_GST_NAME_GC_STR
1015	#undef PGM_GST_NAME_R0_STR
1016
1017	/* Guest - protected mode */
1018	#define PGM_GST_TYPE PGM_TYPE_PROT
1019	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1020	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
1021	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1022	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1023	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_PROT_STR(name)
1024	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1025	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1026	#include "PGMBth.h"
1027	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1028	#undef PGM_BTH_NAME
1029	#undef PGM_BTH_NAME_GC_STR
1030	#undef PGM_BTH_NAME_R0_STR
1031	#undef PGM_GST_TYPE
1032	#undef PGM_GST_NAME
1033	#undef PGM_GST_NAME_GC_STR
1034	#undef PGM_GST_NAME_R0_STR
1035
1036	/* Guest - 32-bit mode */
1037	#define PGM_GST_TYPE PGM_TYPE_32BIT
1038	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1039	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
1040	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1041	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1042	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_32BIT_STR(name)
1043	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1044	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1045	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1046	#include "PGMBth.h"
1047	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1048	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1049	#undef PGM_BTH_NAME
1050	#undef PGM_BTH_NAME_GC_STR
1051	#undef PGM_BTH_NAME_R0_STR
1052	#undef PGM_GST_TYPE
1053	#undef PGM_GST_NAME
1054	#undef PGM_GST_NAME_GC_STR
1055	#undef PGM_GST_NAME_R0_STR
1056
1057	/* Guest - PAE mode */
1058	#define PGM_GST_TYPE PGM_TYPE_PAE
1059	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1060	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
1061	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1062	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1063	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_PAE_STR(name)
1064	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1065	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1066	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1067	#include "PGMBth.h"
1068	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1069	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1070	#undef PGM_BTH_NAME
1071	#undef PGM_BTH_NAME_GC_STR
1072	#undef PGM_BTH_NAME_R0_STR
1073	#undef PGM_GST_TYPE
1074	#undef PGM_GST_NAME
1075	#undef PGM_GST_NAME_GC_STR
1076	#undef PGM_GST_NAME_R0_STR
1077
1078	/* Guest - AMD64 mode */
1079	#define PGM_GST_TYPE PGM_TYPE_AMD64
1080	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1081	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
1082	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1083	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1084	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_AMD64_STR(name)
1085	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1086	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1087	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1088	#include "PGMBth.h"
1089	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1090	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1091	#undef PGM_BTH_NAME
1092	#undef PGM_BTH_NAME_GC_STR
1093	#undef PGM_BTH_NAME_R0_STR
1094	#undef PGM_GST_TYPE
1095	#undef PGM_GST_NAME
1096	#undef PGM_GST_NAME_GC_STR
1097	#undef PGM_GST_NAME_R0_STR
1098
1099	#undef PGM_SHW_TYPE
1100	#undef PGM_SHW_NAME
1101	#undef PGM_SHW_NAME_GC_STR
1102	#undef PGM_SHW_NAME_R0_STR
1103	#endif /* PGM_WITH_EPT */
1104
1105	/**
1106	* Initiates the paging of VM.
1107	*
1108	* @returns VBox status code.
1109	* @param pVM Pointer to VM structure.
1110	*/
1111	PGMR3DECL(int) PGMR3Init(PVM pVM)
1112	{
1113	LogFlow(("PGMR3Init:\n"));
1114
1115	/*
1116	* Assert alignment and sizes.
1117	*/
1118	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1119
1120	/*
1121	* Init the structure.
1122	*/
1123	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1124	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1125	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1126	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1127	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1128	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1129	pVM->pgm.s.fA20Enabled = true;
1130	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1131	pVM->pgm.s.pGstPaePDPTHC = NULL;
1132	pVM->pgm.s.pGstPaePDPTGC = 0;
1133	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1134	{
1135	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1136	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1137	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1138	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1139	}
1140
1141	#ifdef VBOX_STRICT
1142	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1143	#endif
1144
1145	/*
1146	* Get the configured RAM size - to estimate saved state size.
1147	*/
1148	uint64_t cbRam;
1149	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1150	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1151	cbRam = pVM->pgm.s.cbRamSize = 0;
1152	else if (VBOX_SUCCESS(rc))
1153	{
1154	if (cbRam < PAGE_SIZE)
1155	cbRam = 0;
1156	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1157	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1158	}
1159	else
1160	{
1161	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1162	return rc;
1163	}
1164
1165	/*
1166	* Register saved state data unit.
1167	*/
1168	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1169	NULL, pgmR3Save, NULL,
1170	NULL, pgmR3Load, NULL);
1171	if (VBOX_FAILURE(rc))
1172	return rc;
1173
1174	/*
1175	* Initialize the PGM critical section and flush the phys TLBs
1176	*/
1177	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1178	AssertRCReturn(rc, rc);
1179
1180	PGMR3PhysChunkInvalidateTLB(pVM);
1181	PGMPhysInvalidatePageR3MapTLB(pVM);
1182	PGMPhysInvalidatePageR0MapTLB(pVM);
1183	PGMPhysInvalidatePageGCMapTLB(pVM);
1184
1185	/*
1186	* Trees
1187	*/
1188	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
1189	if (VBOX_SUCCESS(rc))
1190	{
1191	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1192
1193	/*
1194	* Alocate the zero page.
1195	*/
1196	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1197	}
1198	if (VBOX_SUCCESS(rc))
1199	{
1200	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1201	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1202	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1203	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1204	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1205
1206	/*
1207	* Init the paging.
1208	*/
1209	rc = pgmR3InitPaging(pVM);
1210	}
1211	if (VBOX_SUCCESS(rc))
1212	{
1213	/*
1214	* Init the page pool.
1215	*/
1216	rc = pgmR3PoolInit(pVM);
1217	}
1218	if (VBOX_SUCCESS(rc))
1219	{
1220	/*
1221	* Info & statistics
1222	*/
1223	DBGFR3InfoRegisterInternal(pVM, "mode",
1224	"Shows the current paging mode. "
1225	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1226	pgmR3InfoMode);
1227	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1228	"Dumps all the entries in the top level paging table. No arguments.",
1229	pgmR3InfoCr3);
1230	DBGFR3InfoRegisterInternal(pVM, "phys",
1231	"Dumps all the physical address ranges. No arguments.",
1232	pgmR3PhysInfo);
1233	DBGFR3InfoRegisterInternal(pVM, "handlers",
1234	"Dumps physical, virtual and hyper virtual handlers. "
1235	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1236	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1237	pgmR3InfoHandlers);
1238	DBGFR3InfoRegisterInternal(pVM, "mappings",
1239	"Dumps guest mappings.",
1240	pgmR3MapInfo);
1241
1242	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1243	#ifdef VBOX_WITH_STATISTICS
1244	pgmR3InitStats(pVM);
1245	#endif
1246	#ifdef VBOX_WITH_DEBUGGER
1247	/*
1248	* Debugger commands.
1249	*/
1250	static bool fRegisteredCmds = false;
1251	if (!fRegisteredCmds)
1252	{
1253	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1254	if (VBOX_SUCCESS(rc))
1255	fRegisteredCmds = true;
1256	}
1257	#endif
1258	return VINF_SUCCESS;
1259	}
1260
1261	/* Almost no cleanup necessary, MM frees all memory. */
1262	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1263
1264	return rc;
1265	}
1266
1267
1268	/**
1269	* Init paging.
1270	*
1271	* Since we need to check what mode the host is operating in before we can choose
1272	* the right paging functions for the host we have to delay this until R0 has
1273	* been initialized.
1274	*
1275	* @returns VBox status code.
1276	* @param pVM VM handle.
1277	*/
1278	static int pgmR3InitPaging(PVM pVM)
1279	{
1280	/*
1281	* Force a recalculation of modes and switcher so everyone gets notified.
1282	*/
1283	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1284	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1285	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1286
1287	/*
1288	* Allocate static mapping space for whatever the cr3 register
1289	* points to and in the case of PAE mode to the 4 PDs.
1290	*/
1291	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1292	if (VBOX_FAILURE(rc))
1293	{
1294	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1295	return rc;
1296	}
1297	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1298
1299	/*
1300	* Allocate pages for the three possible intermediate contexts
1301	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1302	* for the sake of simplicity. The AMD64 uses the PAE for the
1303	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1304	*
1305	* We assume that two page tables will be enought for the core code
1306	* mappings (HC virtual and identity).
1307	*/
1308	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1309	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1310	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1311	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1312	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1313	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1314	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1315	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1316	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1317	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1318	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1319	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1320	if ( !pVM->pgm.s.pInterPD
1321	\|\| !pVM->pgm.s.apInterPTs[0]
1322	\|\| !pVM->pgm.s.apInterPTs[1]
1323	\|\| !pVM->pgm.s.apInterPaePTs[0]
1324	\|\| !pVM->pgm.s.apInterPaePTs[1]
1325	\|\| !pVM->pgm.s.apInterPaePDs[0]
1326	\|\| !pVM->pgm.s.apInterPaePDs[1]
1327	\|\| !pVM->pgm.s.apInterPaePDs[2]
1328	\|\| !pVM->pgm.s.apInterPaePDs[3]
1329	\|\| !pVM->pgm.s.pInterPaePDPT
1330	\|\| !pVM->pgm.s.pInterPaePDPT64
1331	\|\| !pVM->pgm.s.pInterPaePML4)
1332	{
1333	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1334	return VERR_NO_PAGE_MEMORY;
1335	}
1336
1337	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1338	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1339	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1340	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1341	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1342	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1343
1344	/*
1345	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1346	*/
1347	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1348	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1349	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1350
1351	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1352	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1353
1354	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1355	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1356	{
1357	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1358	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1359	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1360	}
1361
1362	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1363	{
1364	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1365	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1366	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1367	}
1368
1369	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1370	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1371	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1372	\| HCPhysInterPaePDPT64;
1373
1374	/*
1375	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1376	* We allocate pages for all three posibilities to in order to simplify mappings and
1377	* avoid resource failure during mode switches. So, we need to cover all levels of the
1378	* of the first 4GB down to PD level.
1379	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1380	*/
1381	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1382	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1383	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1384	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1385	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1386	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1387	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1388	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1389	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1390	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1391	pVM->pgm.s.pHCNoPaging32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1392
1393	if ( !pVM->pgm.s.pHC32BitPD
1394	\|\| !pVM->pgm.s.apHCPaePDs[0]
1395	\|\| !pVM->pgm.s.apHCPaePDs[1]
1396	\|\| !pVM->pgm.s.apHCPaePDs[2]
1397	\|\| !pVM->pgm.s.apHCPaePDs[3]
1398	\|\| !pVM->pgm.s.pHCPaePDPT
1399	\|\| !pVM->pgm.s.pHCNestedRoot
1400	\|\| !pVM->pgm.s.pHCNoPaging32BitPD)
1401	{
1402	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1403	return VERR_NO_PAGE_MEMORY;
1404	}
1405
1406	/* get physical addresses. */
1407	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1408	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1409	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1410	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1411	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1412	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1413	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1414	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1415	pVM->pgm.s.HCPhysNoPaging32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHCNoPaging32BitPD);
1416
1417	/*
1418	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1419	*/
1420	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1421	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1422	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1423	ASMMemZero32(pVM->pgm.s.pHCNoPaging32BitPD, PAGE_SIZE);
1424	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1425	{
1426	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1427	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1428	/* The flags will be corrected when entering and leaving long mode. */
1429	}
1430
1431	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1432
1433	/*
1434	* Initialize paging workers and mode from current host mode
1435	* and the guest running in real mode.
1436	*/
1437	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1438	switch (pVM->pgm.s.enmHostMode)
1439	{
1440	case SUPPAGINGMODE_32_BIT:
1441	case SUPPAGINGMODE_32_BIT_GLOBAL:
1442	case SUPPAGINGMODE_PAE:
1443	case SUPPAGINGMODE_PAE_GLOBAL:
1444	case SUPPAGINGMODE_PAE_NX:
1445	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1446	break;
1447
1448	case SUPPAGINGMODE_AMD64:
1449	case SUPPAGINGMODE_AMD64_GLOBAL:
1450	case SUPPAGINGMODE_AMD64_NX:
1451	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1452	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1453	if (ARCH_BITS != 64)
1454	{
1455	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1456	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1457	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1458	}
1459	#endif
1460	break;
1461	default:
1462	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1463	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1464	}
1465	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1466	if (VBOX_SUCCESS(rc))
1467	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1468	if (VBOX_SUCCESS(rc))
1469	{
1470	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1471	#if HC_ARCH_BITS == 64
1472	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPT=%VHp HCPhysPaePML4=%VHp\n",
1473	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1474	pVM->pgm.s.HCPhysPaePDPT, pVM->pgm.s.HCPhysPaePML4));
1475	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPT=%VHp HCPhysInterPaePML4=%VHp\n",
1476	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1477	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPT64=%VHp\n",
1478	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1479	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1480	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1481	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1482	#endif
1483
1484	return VINF_SUCCESS;
1485	}
1486
1487	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1488	return rc;
1489	}
1490
1491
1492	#ifdef VBOX_WITH_STATISTICS
1493	/**
1494	* Init statistics
1495	*/
1496	static void pgmR3InitStats(PVM pVM)
1497	{
1498	PPGM pPGM = &pVM->pgm.s;
1499	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1500	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
1501	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
1502	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
1503	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1504	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
1505	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
1506	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1507	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1508	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
1509	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1510	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1511	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1512	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1513	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1514	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1515	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1516	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1517	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1518	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
1519	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
1520	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
1521
1522	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
1523	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1524	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1525	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1526	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1527	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1528	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
1529	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1530	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1531	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1532	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1533	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1534	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1535	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1536	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1537	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1538	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1539	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1540	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1541
1542	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1543	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1544	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1545	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1546	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1547	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1548	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1549	STAM_REG(pVM, &pPGM->StatHandlersInvalid, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1550
1551	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1552	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1553	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1554	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1555	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1556	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1557	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1558
1559	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1560	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1561	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1562	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1563	STAM_REG(pVM, &pPGM->StatGCTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1564	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
1565	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
1566
1567	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulGC, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/InGC", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1568	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulR3, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1569
1570	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1571	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1572	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1573
1574	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1575	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1576
1577	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1578	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1579
1580	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1581	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1582
1583	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1584	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1585	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1586
1587	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
1588	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
1589	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
1590	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
1591	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1592	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
1593	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
1594	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1595	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1596	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1597	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1598
1599	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1600	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1601	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1602	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1603	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1604	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1605	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1606
1607	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1608	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1609	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1610	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1611
1612	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1613	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1614	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1615	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1616	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1617
1618	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1619	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1620	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1621	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1622	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1623	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1624	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1625	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1626	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1627	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1628	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1629	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1630
1631	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1632	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1633	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1634	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1635	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1636	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1637	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1638	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1639	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1640	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1641	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1642	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1643
1644	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
1645	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
1646	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
1647
1648	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1649	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1650
1651	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1652	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1653	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1654	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1655
1656	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1657	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1658
1659	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1660	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1661	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1662	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1663	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1664	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1665	STAM_REG(pVM, &pPGM->StatPageReplaceShared, STAMTYPE_COUNTER, "/PGM/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1666	STAM_REG(pVM, &pPGM->StatPageReplaceZero, STAMTYPE_COUNTER, "/PGM/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1667	STAM_REG(pVM, &pPGM->StatPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1668	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1669	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1670	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1671	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1672
1673	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1674	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1675	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1676	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1677	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1678	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1679	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1680	#endif
1681
1682	for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1683	{
1684	/** @todo r=bird: We need a STAMR3RegisterF()! */
1685	char szName[32];
1686
1687	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1688	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1689	AssertRC(rc);
1690
1691	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1692	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1693	AssertRC(rc);
1694
1695	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1696	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1697	AssertRC(rc);
1698	}
1699	}
1700	#endif /* VBOX_WITH_STATISTICS */
1701
1702	/**
1703	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1704	*
1705	* The dynamic mapping area will also be allocated and initialized at this
1706	* time. We could allocate it during PGMR3Init of course, but the mapping
1707	* wouldn't be allocated at that time preventing us from setting up the
1708	* page table entries with the dummy page.
1709	*
1710	* @returns VBox status code.
1711	* @param pVM VM handle.
1712	*/
1713	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1714	{
1715	RTGCPTR GCPtr;
1716	/*
1717	* Reserve space for mapping the paging pages into guest context.
1718	*/
1719	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1720	AssertRCReturn(rc, rc);
1721	pVM->pgm.s.pGC32BitPD = GCPtr;
1722	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1723
1724	/*
1725	* Reserve space for the dynamic mappings.
1726	*/
1727	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1728	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1729	if (VBOX_SUCCESS(rc))
1730	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1731
1732	if ( VBOX_SUCCESS(rc)
1733	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT))
1734	{
1735	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1736	if (VBOX_SUCCESS(rc))
1737	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1738	}
1739	if (VBOX_SUCCESS(rc))
1740	{
1741	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT));
1742	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1743	}
1744	return rc;
1745	}
1746
1747
1748	/**
1749	* Ring-3 init finalizing.
1750	*
1751	* @returns VBox status code.
1752	* @param pVM The VM handle.
1753	*/
1754	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1755	{
1756	/*
1757	* Map the paging pages into the guest context.
1758	*/
1759	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1760	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1761
1762	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1763	AssertRCReturn(rc, rc);
1764	pVM->pgm.s.pGC32BitPD = GCPtr;
1765	GCPtr += PAGE_SIZE;
1766	GCPtr += PAGE_SIZE; /* reserved page */
1767
1768	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1769	{
1770	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1771	AssertRCReturn(rc, rc);
1772	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1773	GCPtr += PAGE_SIZE;
1774	}
1775	/* A bit of paranoia is justified. */
1776	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1777	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1778	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1779	GCPtr += PAGE_SIZE; /* reserved page */
1780
1781	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1782	AssertRCReturn(rc, rc);
1783	pVM->pgm.s.pGCPaePDPT = GCPtr;
1784	GCPtr += PAGE_SIZE;
1785	GCPtr += PAGE_SIZE; /* reserved page */
1786
1787
1788	/*
1789	* Reserve space for the dynamic mappings.
1790	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1791	*/
1792	/* get the pointer to the page table entries. */
1793	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1794	AssertRelease(pMapping);
1795	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1796	const unsigned iPT = off >> X86_PD_SHIFT;
1797	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1798	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1799	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1800
1801	/* init cache */
1802	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1803	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1804	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1805
1806	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1807	{
1808	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1809	AssertRCReturn(rc, rc);
1810	}
1811
1812	/* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total); Intel only goes up to 36 bits, so
1813	* we stick to 36 as well.
1814	*
1815	* @todo How to test for the 40 bits support? Long mode seems to be the test criterium.
1816	*/
1817	uint32_t u32Dummy, u32Features;
1818	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1819
1820	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1821	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1822	else
1823	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1824
1825	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %VGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1826
1827	return rc;
1828	}
1829
1830
1831	/**
1832	* Applies relocations to data and code managed by this
1833	* component. This function will be called at init and
1834	* whenever the VMM need to relocate it self inside the GC.
1835	*
1836	* @param pVM The VM.
1837	* @param offDelta Relocation delta relative to old location.
1838	*/
1839	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1840	{
1841	LogFlow(("PGMR3Relocate\n"));
1842
1843	/*
1844	* Paging stuff.
1845	*/
1846	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1847	/** @todo move this into shadow and guest specific relocation functions. */
1848	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1849	pVM->pgm.s.pGC32BitPD += offDelta;
1850	pVM->pgm.s.pGuestPDGC += offDelta;
1851	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apGCPaePDs) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1852	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1853	{
1854	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1855	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1856	}
1857	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1858	pVM->pgm.s.pGCPaePDPT += offDelta;
1859
1860	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1861	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1862
1863	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1864	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1865	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1866
1867	/*
1868	* Trees.
1869	*/
1870	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1871
1872	/*
1873	* Ram ranges.
1874	*/
1875	if (pVM->pgm.s.pRamRangesR3)
1876	{
1877	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesR3);
1878	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1879	#ifdef VBOX_WITH_NEW_PHYS_CODE
1880	pCur->pNextGC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1881	#else
1882	{
1883	pCur->pNextGC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1884	if (pCur->pavHCChunkGC)
1885	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1886	}
1887	#endif
1888	}
1889
1890	/*
1891	* Update the two page directories with all page table mappings.
1892	* (One or more of them have changed, that's why we're here.)
1893	*/
1894	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1895	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1896	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1897
1898	/* Relocate GC addresses of Page Tables. */
1899	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1900	{
1901	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1902	{
1903	pCur->aPTs[i].pPTGC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1904	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1905	}
1906	}
1907
1908	/*
1909	* Dynamic page mapping area.
1910	*/
1911	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1912	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1913	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1914
1915	/*
1916	* The Zero page.
1917	*/
1918	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1919	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1920
1921	/*
1922	* Physical and virtual handlers.
1923	*/
1924	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1925	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1926	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1927
1928	/*
1929	* The page pool.
1930	*/
1931	pgmR3PoolRelocate(pVM);
1932	}
1933
1934
1935	/**
1936	* Callback function for relocating a physical access handler.
1937	*
1938	* @returns 0 (continue enum)
1939	* @param pNode Pointer to a PGMPHYSHANDLER node.
1940	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1941	* not certain the delta will fit in a void pointer for all possible configs.
1942	*/
1943	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1944	{
1945	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1946	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1947	if (pHandler->pfnHandlerGC)
1948	pHandler->pfnHandlerGC += offDelta;
1949	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1950	pHandler->pvUserGC += offDelta;
1951	return 0;
1952	}
1953
1954
1955	/**
1956	* Callback function for relocating a virtual access handler.
1957	*
1958	* @returns 0 (continue enum)
1959	* @param pNode Pointer to a PGMVIRTHANDLER node.
1960	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1961	* not certain the delta will fit in a void pointer for all possible configs.
1962	*/
1963	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1964	{
1965	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1966	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1967	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1968	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1969	Assert(pHandler->pfnHandlerGC);
1970	pHandler->pfnHandlerGC += offDelta;
1971	return 0;
1972	}
1973
1974
1975	/**
1976	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1977	*
1978	* @returns 0 (continue enum)
1979	* @param pNode Pointer to a PGMVIRTHANDLER node.
1980	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1981	* not certain the delta will fit in a void pointer for all possible configs.
1982	*/
1983	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1984	{
1985	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1986	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1987	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1988	Assert(pHandler->pfnHandlerGC);
1989	pHandler->pfnHandlerGC += offDelta;
1990	return 0;
1991	}
1992
1993
1994	/**
1995	* The VM is being reset.
1996	*
1997	* For the PGM component this means that any PD write monitors
1998	* needs to be removed.
1999	*
2000	* @param pVM VM handle.
2001	*/
2002	PGMR3DECL(void) PGMR3Reset(PVM pVM)
2003	{
2004	LogFlow(("PGMR3Reset:\n"));
2005	VM_ASSERT_EMT(pVM);
2006
2007	pgmLock(pVM);
2008
2009	/*
2010	* Unfix any fixed mappings and disable CR3 monitoring.
2011	*/
2012	pVM->pgm.s.fMappingsFixed = false;
2013	pVM->pgm.s.GCPtrMappingFixed = 0;
2014	pVM->pgm.s.cbMappingFixed = 0;
2015
2016	/* Exit the guest paging mode before the pgm pool gets reset.
2017	* Important to clean up the amd64 case.
2018	*/
2019	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2020	AssertRC(rc);
2021	#ifdef DEBUG
2022	DBGFR3InfoLog(pVM, "mappings", NULL);
2023	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2024	#endif
2025
2026	/*
2027	* Reset the shadow page pool.
2028	*/
2029	pgmR3PoolReset(pVM);
2030
2031	/*
2032	* Re-init other members.
2033	*/
2034	pVM->pgm.s.fA20Enabled = true;
2035
2036	/*
2037	* Clear the FFs PGM owns.
2038	*/
2039	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2040	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2041
2042	/*
2043	* Reset (zero) RAM pages.
2044	*/
2045	rc = pgmR3PhysRamReset(pVM);
2046	if (RT_SUCCESS(rc))
2047	{
2048	#ifdef VBOX_WITH_NEW_PHYS_CODE
2049	/*
2050	* Reset (zero) shadow ROM pages.
2051	*/
2052	rc = pgmR3PhysRomReset(pVM);
2053	#endif
2054	if (RT_SUCCESS(rc))
2055	{
2056	/*
2057	* Switch mode back to real mode.
2058	*/
2059	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2060	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2061	}
2062	}
2063
2064	pgmUnlock(pVM);
2065	//return rc;
2066	AssertReleaseRC(rc);
2067	}
2068
2069
2070	#ifdef VBOX_STRICT
2071	/**
2072	* VM state change callback for clearing fNoMorePhysWrites after
2073	* a snapshot has been created.
2074	*/
2075	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2076	{
2077	if (enmState == VMSTATE_RUNNING)
2078	pVM->pgm.s.fNoMorePhysWrites = false;
2079	}
2080	#endif
2081
2082
2083	/**
2084	* Terminates the PGM.
2085	*
2086	* @returns VBox status code.
2087	* @param pVM Pointer to VM structure.
2088	*/
2089	PGMR3DECL(int) PGMR3Term(PVM pVM)
2090	{
2091	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2092	}
2093
2094
2095	/**
2096	* Execute state save operation.
2097	*
2098	* @returns VBox status code.
2099	* @param pVM VM Handle.
2100	* @param pSSM SSM operation handle.
2101	*/
2102	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2103	{
2104	PPGM pPGM = &pVM->pgm.s;
2105
2106	/* No more writes to physical memory after this point! */
2107	pVM->pgm.s.fNoMorePhysWrites = true;
2108
2109	/*
2110	* Save basic data (required / unaffected by relocation).
2111	*/
2112	#if 1
2113	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2114	#else
2115	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2116	#endif
2117	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2118	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2119	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2120	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2121	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2122	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2123	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2124	SSMR3PutU32(pSSM, ~0); /* Separator. */
2125
2126	/*
2127	* The guest mappings.
2128	*/
2129	uint32_t i = 0;
2130	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2131	{
2132	SSMR3PutU32(pSSM, i);
2133	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2134	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2135	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2136	/* flags are done by the mapping owners! */
2137	}
2138	SSMR3PutU32(pSSM, ~0); /* terminator. */
2139
2140	/*
2141	* Ram range flags and bits.
2142	*/
2143	i = 0;
2144	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2145	{
2146	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2147
2148	SSMR3PutU32(pSSM, i);
2149	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2150	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2151	SSMR3PutGCPhys(pSSM, pRam->cb);
2152	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
2153
2154	/* Flags. */
2155	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2156	for (unsigned iPage = 0; iPage < cPages; iPage++)
2157	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2158
2159	/* any memory associated with the range. */
2160	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2161	{
2162	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2163	{
2164	if (pRam->pavHCChunkHC[iChunk])
2165	{
2166	SSMR3PutU8(pSSM, 1); /* chunk present */
2167	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2168	}
2169	else
2170	SSMR3PutU8(pSSM, 0); /* no chunk present */
2171	}
2172	}
2173	else if (pRam->pvHC)
2174	{
2175	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
2176	if (VBOX_FAILURE(rc))
2177	{
2178	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2179	return rc;
2180	}
2181	}
2182	}
2183	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2184	}
2185
2186
2187	/**
2188	* Execute state load operation.
2189	*
2190	* @returns VBox status code.
2191	* @param pVM VM Handle.
2192	* @param pSSM SSM operation handle.
2193	* @param u32Version Data layout version.
2194	*/
2195	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2196	{
2197	/*
2198	* Validate version.
2199	*/
2200	if (u32Version != PGM_SAVED_STATE_VERSION)
2201	{
2202	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2203	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2204	}
2205
2206	/*
2207	* Call the reset function to make sure all the memory is cleared.
2208	*/
2209	PGMR3Reset(pVM);
2210
2211	/*
2212	* Load basic data (required / unaffected by relocation).
2213	*/
2214	PPGM pPGM = &pVM->pgm.s;
2215	#if 1
2216	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2217	#else
2218	uint32_t u;
2219	SSMR3GetU32(pSSM, &u);
2220	pPGM->fMappingsFixed = u;
2221	#endif
2222	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2223	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2224
2225	RTUINT cbRamSize;
2226	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2227	if (VBOX_FAILURE(rc))
2228	return rc;
2229	if (cbRamSize != pPGM->cbRamSize)
2230	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2231	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2232	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2233	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2234	RTUINT uGuestMode;
2235	SSMR3GetUInt(pSSM, &uGuestMode);
2236	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2237
2238	/* check separator. */
2239	uint32_t u32Sep;
2240	SSMR3GetU32(pSSM, &u32Sep);
2241	if (VBOX_FAILURE(rc))
2242	return rc;
2243	if (u32Sep != (uint32_t)~0)
2244	{
2245	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2246	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2247	}
2248
2249	/*
2250	* The guest mappings.
2251	*/
2252	uint32_t i = 0;
2253	for (;; i++)
2254	{
2255	/* Check the seqence number / separator. */
2256	rc = SSMR3GetU32(pSSM, &u32Sep);
2257	if (VBOX_FAILURE(rc))
2258	return rc;
2259	if (u32Sep == ~0U)
2260	break;
2261	if (u32Sep != i)
2262	{
2263	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2264	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2265	}
2266
2267	/* get the mapping details. */
2268	char szDesc[256];
2269	szDesc[0] = '\0';
2270	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2271	if (VBOX_FAILURE(rc))
2272	return rc;
2273	RTGCPTR GCPtr;
2274	SSMR3GetGCPtr(pSSM, &GCPtr);
2275	RTGCUINTPTR cPTs;
2276	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2277	if (VBOX_FAILURE(rc))
2278	return rc;
2279
2280	/* find matching range. */
2281	PPGMMAPPING pMapping;
2282	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2283	if ( pMapping->cPTs == cPTs
2284	&& !strcmp(pMapping->pszDesc, szDesc))
2285	break;
2286	if (!pMapping)
2287	{
2288	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2289	cPTs, szDesc, GCPtr));
2290	AssertFailed();
2291	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2292	}
2293
2294	/* relocate it. */
2295	if (pMapping->GCPtr != GCPtr)
2296	{
2297	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2298	#if HC_ARCH_BITS == 64
2299	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2300	#endif
2301	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2302	}
2303	else
2304	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2305	}
2306
2307	/*
2308	* Ram range flags and bits.
2309	*/
2310	i = 0;
2311	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2312	{
2313	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2314	/* Check the seqence number / separator. */
2315	rc = SSMR3GetU32(pSSM, &u32Sep);
2316	if (VBOX_FAILURE(rc))
2317	return rc;
2318	if (u32Sep == ~0U)
2319	break;
2320	if (u32Sep != i)
2321	{
2322	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2323	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2324	}
2325
2326	/* Get the range details. */
2327	RTGCPHYS GCPhys;
2328	SSMR3GetGCPhys(pSSM, &GCPhys);
2329	RTGCPHYS GCPhysLast;
2330	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2331	RTGCPHYS cb;
2332	SSMR3GetGCPhys(pSSM, &cb);
2333	uint8_t fHaveBits;
2334	rc = SSMR3GetU8(pSSM, &fHaveBits);
2335	if (VBOX_FAILURE(rc))
2336	return rc;
2337	if (fHaveBits & ~1)
2338	{
2339	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2340	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2341	}
2342
2343	/* Match it up with the current range. */
2344	if ( GCPhys != pRam->GCPhys
2345	\|\| GCPhysLast != pRam->GCPhysLast
2346	\|\| cb != pRam->cb
2347	\|\| fHaveBits != !!pRam->pvHC)
2348	{
2349	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
2350	"State : %VGp-%VGp %VGp bytes %s\n",
2351	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
2352	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2353	/*
2354	* If we're loading a state for debugging purpose, don't make a fuss if
2355	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2356	*/
2357	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2358	\|\| GCPhys < 8 * _1M)
2359	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2360
2361	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2362	while (cPages-- > 0)
2363	{
2364	uint16_t u16Ignore;
2365	SSMR3GetU16(pSSM, &u16Ignore);
2366	}
2367	continue;
2368	}
2369
2370	/* Flags. */
2371	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2372	for (unsigned iPage = 0; iPage < cPages; iPage++)
2373	{
2374	uint16_t u16 = 0;
2375	SSMR3GetU16(pSSM, &u16);
2376	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2377	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2378	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2379	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2380	}
2381
2382	/* any memory associated with the range. */
2383	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2384	{
2385	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2386	{
2387	uint8_t fValidChunk;
2388
2389	rc = SSMR3GetU8(pSSM, &fValidChunk);
2390	if (VBOX_FAILURE(rc))
2391	return rc;
2392	if (fValidChunk > 1)
2393	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2394
2395	if (fValidChunk)
2396	{
2397	if (!pRam->pavHCChunkHC[iChunk])
2398	{
2399	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2400	if (VBOX_FAILURE(rc))
2401	return rc;
2402	}
2403	Assert(pRam->pavHCChunkHC[iChunk]);
2404
2405	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2406	}
2407	/* else nothing to do */
2408	}
2409	}
2410	else if (pRam->pvHC)
2411	{
2412	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
2413	if (VBOX_FAILURE(rc))
2414	{
2415	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2416	return rc;
2417	}
2418	}
2419	}
2420
2421	/*
2422	* We require a full resync now.
2423	*/
2424	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2425	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2426	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2427	pPGM->fPhysCacheFlushPending = true;
2428	pgmR3HandlerPhysicalUpdateAll(pVM);
2429
2430	/*
2431	* Change the paging mode.
2432	*/
2433	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2434
2435	/* Restore pVM->pgm.s.GCPhysCR3. */
2436	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2437	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2438	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2439	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2440	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2441	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2442	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2443	else
2444	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2445	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2446
2447	return rc;
2448	}
2449
2450
2451	/**
2452	* Show paging mode.
2453	*
2454	* @param pVM VM Handle.
2455	* @param pHlp The info helpers.
2456	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2457	*/
2458	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2459	{
2460	/* digest argument. */
2461	bool fGuest, fShadow, fHost;
2462	if (pszArgs)
2463	pszArgs = RTStrStripL(pszArgs);
2464	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2465	fShadow = fHost = fGuest = true;
2466	else
2467	{
2468	fShadow = fHost = fGuest = false;
2469	if (strstr(pszArgs, "guest"))
2470	fGuest = true;
2471	if (strstr(pszArgs, "shadow"))
2472	fShadow = true;
2473	if (strstr(pszArgs, "host"))
2474	fHost = true;
2475	}
2476
2477	/* print info. */
2478	if (fGuest)
2479	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2480	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2481	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2482	if (fShadow)
2483	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2484	if (fHost)
2485	{
2486	const char *psz;
2487	switch (pVM->pgm.s.enmHostMode)
2488	{
2489	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2490	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2491	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2492	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2493	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2494	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2495	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2496	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2497	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2498	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2499	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2500	default: psz = "unknown"; break;
2501	}
2502	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2503	}
2504	}
2505
2506
2507	/**
2508	* Dump registered MMIO ranges to the log.
2509	*
2510	* @param pVM VM Handle.
2511	* @param pHlp The info helpers.
2512	* @param pszArgs Arguments, ignored.
2513	*/
2514	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2515	{
2516	NOREF(pszArgs);
2517	pHlp->pfnPrintf(pHlp,
2518	"RAM ranges (pVM=%p)\n"
2519	"%.s %.s\n",
2520	pVM,
2521	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2522	sizeof(RTHCPTR) * 2, "pvHC ");
2523
2524	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2525	pHlp->pfnPrintf(pHlp,
2526	"%RGp-%RGp %RHv %s\n",
2527	pCur->GCPhys,
2528	pCur->GCPhysLast,
2529	pCur->pvHC,
2530	pCur->pszDesc);
2531	}
2532
2533	/**
2534	* Dump the page directory to the log.
2535	*
2536	* @param pVM VM Handle.
2537	* @param pHlp The info helpers.
2538	* @param pszArgs Arguments, ignored.
2539	*/
2540	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2541	{
2542	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2543	/* Big pages supported? */
2544	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2545
2546	/* Global pages supported? */
2547	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2548
2549	NOREF(pszArgs);
2550
2551	/*
2552	* Get page directory addresses.
2553	*/
2554	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2555	Assert(pPDSrc);
2556	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2557
2558	/*
2559	* Iterate the page directory.
2560	*/
2561	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2562	{
2563	X86PDE PdeSrc = pPDSrc->a[iPD];
2564	if (PdeSrc.n.u1Present)
2565	{
2566	if (PdeSrc.b.u1Size && fPSE)
2567	{
2568	pHlp->pfnPrintf(pHlp,
2569	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2570	iPD,
2571	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2572	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2573	}
2574	else
2575	{
2576	pHlp->pfnPrintf(pHlp,
2577	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2578	iPD,
2579	PdeSrc.u & X86_PDE_PG_MASK,
2580	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2581	}
2582	}
2583	}
2584	}
2585
2586
2587	/**
2588	* Serivce a VMMCALLHOST_PGM_LOCK call.
2589	*
2590	* @returns VBox status code.
2591	* @param pVM The VM handle.
2592	*/
2593	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
2594	{
2595	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2596	AssertRC(rc);
2597	return rc;
2598	}
2599
2600
2601	/**
2602	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2603	*
2604	* @returns PGM_TYPE_*.
2605	* @param pgmMode The mode value to convert.
2606	*/
2607	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2608	{
2609	switch (pgmMode)
2610	{
2611	case PGMMODE_REAL: return PGM_TYPE_REAL;
2612	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2613	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2614	case PGMMODE_PAE:
2615	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2616	case PGMMODE_AMD64:
2617	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2618	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2619	case PGMMODE_EPT: return PGM_TYPE_EPT;
2620	default:
2621	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2622	}
2623	}
2624
2625
2626	/**
2627	* Gets the index into the paging mode data array of a SHW+GST mode.
2628	*
2629	* @returns PGM::paPagingData index.
2630	* @param uShwType The shadow paging mode type.
2631	* @param uGstType The guest paging mode type.
2632	*/
2633	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2634	{
2635	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_NESTED);
2636	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2637	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2638	+ (uGstType - PGM_TYPE_REAL);
2639	}
2640
2641
2642	/**
2643	* Gets the index into the paging mode data array of a SHW+GST mode.
2644	*
2645	* @returns PGM::paPagingData index.
2646	* @param enmShw The shadow paging mode.
2647	* @param enmGst The guest paging mode.
2648	*/
2649	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2650	{
2651	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2652	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2653	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2654	}
2655
2656
2657	/**
2658	* Calculates the max data index.
2659	* @returns The number of entries in the paging data array.
2660	*/
2661	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2662	{
2663	return pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64) + 1;
2664	}
2665
2666
2667	/**
2668	* Initializes the paging mode data kept in PGM::paModeData.
2669	*
2670	* @param pVM The VM handle.
2671	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2672	* This is used early in the init process to avoid trouble with PDM
2673	* not being initialized yet.
2674	*/
2675	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2676	{
2677	PPGMMODEDATA pModeData;
2678	int rc;
2679
2680	/*
2681	* Allocate the array on the first call.
2682	*/
2683	if (!pVM->pgm.s.paModeData)
2684	{
2685	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2686	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2687	}
2688
2689	/*
2690	* Initialize the array entries.
2691	*/
2692	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2693	pModeData->uShwType = PGM_TYPE_32BIT;
2694	pModeData->uGstType = PGM_TYPE_REAL;
2695	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2696	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2697	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2698
2699	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2700	pModeData->uShwType = PGM_TYPE_32BIT;
2701	pModeData->uGstType = PGM_TYPE_PROT;
2702	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2703	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2704	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2705
2706	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2707	pModeData->uShwType = PGM_TYPE_32BIT;
2708	pModeData->uGstType = PGM_TYPE_32BIT;
2709	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2710	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2711	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2712
2713	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2714	pModeData->uShwType = PGM_TYPE_PAE;
2715	pModeData->uGstType = PGM_TYPE_REAL;
2716	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2717	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2718	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2719
2720	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2721	pModeData->uShwType = PGM_TYPE_PAE;
2722	pModeData->uGstType = PGM_TYPE_PROT;
2723	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2724	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2725	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2726
2727	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2728	pModeData->uShwType = PGM_TYPE_PAE;
2729	pModeData->uGstType = PGM_TYPE_32BIT;
2730	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2731	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2732	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2733
2734	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2735	pModeData->uShwType = PGM_TYPE_PAE;
2736	pModeData->uGstType = PGM_TYPE_PAE;
2737	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2738	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2739	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2740
2741	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2742	pModeData->uShwType = PGM_TYPE_AMD64;
2743	pModeData->uGstType = PGM_TYPE_AMD64;
2744	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2745	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2746	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2747
2748	/* The nested paging mode. */
2749	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2750	pModeData->uShwType = PGM_TYPE_NESTED;
2751	pModeData->uGstType = PGM_TYPE_REAL;
2752	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2753	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754
2755	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2756	pModeData->uShwType = PGM_TYPE_NESTED;
2757	pModeData->uGstType = PGM_TYPE_PROT;
2758	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2759	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2760
2761	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2762	pModeData->uShwType = PGM_TYPE_NESTED;
2763	pModeData->uGstType = PGM_TYPE_32BIT;
2764	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2765	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2766
2767	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2768	pModeData->uShwType = PGM_TYPE_NESTED;
2769	pModeData->uGstType = PGM_TYPE_PAE;
2770	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2771	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2772
2773	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2774	pModeData->uShwType = PGM_TYPE_NESTED;
2775	pModeData->uGstType = PGM_TYPE_AMD64;
2776	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2777	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2778
2779	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2780	switch(pVM->pgm.s.enmHostMode)
2781	{
2782	case SUPPAGINGMODE_32_BIT:
2783	case SUPPAGINGMODE_32_BIT_GLOBAL:
2784	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2785	{
2786	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2787	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2788	}
2789	break;
2790
2791	case SUPPAGINGMODE_PAE:
2792	case SUPPAGINGMODE_PAE_NX:
2793	case SUPPAGINGMODE_PAE_GLOBAL:
2794	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2795	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2796	{
2797	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2798	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2799	}
2800	break;
2801
2802	case SUPPAGINGMODE_AMD64:
2803	case SUPPAGINGMODE_AMD64_GLOBAL:
2804	case SUPPAGINGMODE_AMD64_NX:
2805	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2806	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2807	{
2808	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2809	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2810	}
2811	break;
2812	default:
2813	AssertFailed();
2814	break;
2815	}
2816
2817	#ifdef PGM_WITH_EPT
2818	/* Extended paging (EPT) / Intel VT-x */
2819	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2820	pModeData->uShwType = PGM_TYPE_EPT;
2821	pModeData->uGstType = PGM_TYPE_REAL;
2822	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2823	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2824	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2825
2826	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2827	pModeData->uShwType = PGM_TYPE_EPT;
2828	pModeData->uGstType = PGM_TYPE_PROT;
2829	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2830	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2831	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2832
2833	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2834	pModeData->uShwType = PGM_TYPE_EPT;
2835	pModeData->uGstType = PGM_TYPE_32BIT;
2836	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2837	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2838	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2839
2840	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2841	pModeData->uShwType = PGM_TYPE_EPT;
2842	pModeData->uGstType = PGM_TYPE_PAE;
2843	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2844	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2845	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2846
2847	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2848	pModeData->uShwType = PGM_TYPE_EPT;
2849	pModeData->uGstType = PGM_TYPE_AMD64;
2850	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2851	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2852	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2853	#endif /* PGM_WITH_EPT */
2854	return VINF_SUCCESS;
2855	}
2856
2857
2858	/**
2859	* Switch to different (or relocated in the relocate case) mode data.
2860	*
2861	* @param pVM The VM handle.
2862	* @param enmShw The the shadow paging mode.
2863	* @param enmGst The the guest paging mode.
2864	*/
2865	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2866	{
2867	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2868
2869	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2870	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2871
2872	/* shadow */
2873	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2874	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2875	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2876	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2877	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2878
2879	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2880	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2881
2882	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2883	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2884
2885
2886	/* guest */
2887	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2888	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2889	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2890	Assert(pVM->pgm.s.pfnR3GstGetPage);
2891	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2892	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2893	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2894	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2895	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2896	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2897	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2898	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2899	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2900	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2901
2902	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2903	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2904	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2905	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2906	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2907	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2908	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2909	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2910	pVM->pgm.s.pfnGCGstPAEWriteHandlerCR3 = pModeData->pfnGCGstPAEWriteHandlerCR3;
2911
2912	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2913	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2914	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2915	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2916	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2917	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2918	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2919	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2920	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2921
2922
2923	/* both */
2924	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2925	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2926	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2927	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2928	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2929	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2930	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2931	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2932	#ifdef VBOX_STRICT
2933	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2934	#endif
2935
2936	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2937	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2938	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2939	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2940	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2941	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2942	#ifdef VBOX_STRICT
2943	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2944	#endif
2945
2946	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2947	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2948	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2949	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2950	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2951	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2952	#ifdef VBOX_STRICT
2953	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2954	#endif
2955	}
2956
2957
2958	#ifdef DEBUG_bird
2959	#include <stdlib.h> /* getenv() remove me! */
2960	#endif
2961
2962	/**
2963	* Calculates the shadow paging mode.
2964	*
2965	* @returns The shadow paging mode.
2966	* @param pVM VM handle.
2967	* @param enmGuestMode The guest mode.
2968	* @param enmHostMode The host mode.
2969	* @param enmShadowMode The current shadow mode.
2970	* @param penmSwitcher Where to store the switcher to use.
2971	* VMMSWITCHER_INVALID means no change.
2972	*/
2973	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2974	{
2975	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2976	switch (enmGuestMode)
2977	{
2978	/*
2979	* When switching to real or protected mode we don't change
2980	* anything since it's likely that we'll switch back pretty soon.
2981	*
2982	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2983	* and is supposed to determine which shadow paging and switcher to
2984	* use during init.
2985	*/
2986	case PGMMODE_REAL:
2987	case PGMMODE_PROTECTED:
2988	if ( enmShadowMode != PGMMODE_INVALID
2989	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2990	break; /* (no change) */
2991
2992	/* Always use the 32 bits shadow mode for this case. We never execute real or protected mode without paging code
2993	* in raw mode.
2994	*/
2995	enmShadowMode = PGMMODE_32_BIT;
2996	enmSwitcher = VMMSWITCHER_INVALID;
2997	break;
2998
2999	case PGMMODE_32_BIT:
3000	switch (enmHostMode)
3001	{
3002	case SUPPAGINGMODE_32_BIT:
3003	case SUPPAGINGMODE_32_BIT_GLOBAL:
3004	enmShadowMode = PGMMODE_32_BIT;
3005	enmSwitcher = VMMSWITCHER_32_TO_32;
3006	break;
3007
3008	case SUPPAGINGMODE_PAE:
3009	case SUPPAGINGMODE_PAE_NX:
3010	case SUPPAGINGMODE_PAE_GLOBAL:
3011	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3012	enmShadowMode = PGMMODE_PAE;
3013	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3014	#ifdef DEBUG_bird
3015	if (getenv("VBOX_32BIT"))
3016	{
3017	enmShadowMode = PGMMODE_32_BIT;
3018	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3019	}
3020	#endif
3021	break;
3022
3023	case SUPPAGINGMODE_AMD64:
3024	case SUPPAGINGMODE_AMD64_GLOBAL:
3025	case SUPPAGINGMODE_AMD64_NX:
3026	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3027	enmShadowMode = PGMMODE_PAE;
3028	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3029	break;
3030
3031	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3032	}
3033	break;
3034
3035	case PGMMODE_PAE:
3036	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3037	switch (enmHostMode)
3038	{
3039	case SUPPAGINGMODE_32_BIT:
3040	case SUPPAGINGMODE_32_BIT_GLOBAL:
3041	enmShadowMode = PGMMODE_PAE;
3042	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3043	break;
3044
3045	case SUPPAGINGMODE_PAE:
3046	case SUPPAGINGMODE_PAE_NX:
3047	case SUPPAGINGMODE_PAE_GLOBAL:
3048	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3049	enmShadowMode = PGMMODE_PAE;
3050	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3051	break;
3052
3053	case SUPPAGINGMODE_AMD64:
3054	case SUPPAGINGMODE_AMD64_GLOBAL:
3055	case SUPPAGINGMODE_AMD64_NX:
3056	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3057	enmShadowMode = PGMMODE_PAE;
3058	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3059	break;
3060
3061	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3062	}
3063	break;
3064
3065	case PGMMODE_AMD64:
3066	case PGMMODE_AMD64_NX:
3067	switch (enmHostMode)
3068	{
3069	case SUPPAGINGMODE_32_BIT:
3070	case SUPPAGINGMODE_32_BIT_GLOBAL:
3071	enmShadowMode = PGMMODE_PAE;
3072	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3073	break;
3074
3075	case SUPPAGINGMODE_PAE:
3076	case SUPPAGINGMODE_PAE_NX:
3077	case SUPPAGINGMODE_PAE_GLOBAL:
3078	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3079	enmShadowMode = PGMMODE_PAE;
3080	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3081	break;
3082
3083	case SUPPAGINGMODE_AMD64:
3084	case SUPPAGINGMODE_AMD64_GLOBAL:
3085	case SUPPAGINGMODE_AMD64_NX:
3086	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3087	enmShadowMode = PGMMODE_AMD64;
3088	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3089	break;
3090
3091	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3092	}
3093	break;
3094
3095
3096	default:
3097	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3098	return PGMMODE_INVALID;
3099	}
3100	/* Override the shadow mode is nested paging is active. */
3101	if (HWACCMIsNestedPagingActive(pVM))
3102	enmShadowMode = HWACCMGetPagingMode(pVM);
3103
3104	*penmSwitcher = enmSwitcher;
3105	return enmShadowMode;
3106	}
3107
3108	/**
3109	* Performs the actual mode change.
3110	* This is called by PGMChangeMode and pgmR3InitPaging().
3111	*
3112	* @returns VBox status code.
3113	* @param pVM VM handle.
3114	* @param enmGuestMode The new guest mode. This is assumed to be different from
3115	* the current mode.
3116	*/
3117	PGMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3118	{
3119	LogFlow(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3120	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3121
3122	/*
3123	* Calc the shadow mode and switcher.
3124	*/
3125	VMMSWITCHER enmSwitcher;
3126	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3127	if (enmSwitcher != VMMSWITCHER_INVALID)
3128	{
3129	/*
3130	* Select new switcher.
3131	*/
3132	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3133	if (VBOX_FAILURE(rc))
3134	{
3135	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3136	return rc;
3137	}
3138	}
3139
3140	/*
3141	* Exit old mode(s).
3142	*/
3143	/* shadow */
3144	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3145	{
3146	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3147	if (PGM_SHW_PFN(Exit, pVM))
3148	{
3149	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3150	if (VBOX_FAILURE(rc))
3151	{
3152	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3153	return rc;
3154	}
3155	}
3156
3157	}
3158	else
3159	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3160
3161	/* guest */
3162	if (PGM_GST_PFN(Exit, pVM))
3163	{
3164	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3165	if (VBOX_FAILURE(rc))
3166	{
3167	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3168	return rc;
3169	}
3170	}
3171
3172	/*
3173	* Load new paging mode data.
3174	*/
3175	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3176
3177	/*
3178	* Enter new shadow mode (if changed).
3179	*/
3180	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3181	{
3182	int rc;
3183	pVM->pgm.s.enmShadowMode = enmShadowMode;
3184	switch (enmShadowMode)
3185	{
3186	case PGMMODE_32_BIT:
3187	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3188	break;
3189	case PGMMODE_PAE:
3190	case PGMMODE_PAE_NX:
3191	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3192	break;
3193	case PGMMODE_AMD64:
3194	case PGMMODE_AMD64_NX:
3195	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3196	break;
3197	case PGMMODE_NESTED:
3198	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3199	break;
3200	#ifdef PGM_WITH_EPT
3201	case PGMMODE_EPT:
3202	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3203	break;
3204	#endif
3205	case PGMMODE_REAL:
3206	case PGMMODE_PROTECTED:
3207	default:
3208	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3209	return VERR_INTERNAL_ERROR;
3210	}
3211	if (VBOX_FAILURE(rc))
3212	{
3213	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3214	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3215	return rc;
3216	}
3217	}
3218
3219	/* We must flush the PGM pool cache if the guest mode changes; we don't always
3220	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3221	* the shadow page tables.
3222	*
3223	* That only applies when switching between paging and non-paging modes.
3224	*
3225	* @todo A20 setting
3226	*/
3227	if ( pVM->pgm.s.CTXSUFF(pPool)
3228	&& !HWACCMIsNestedPagingActive(pVM)
3229	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3230	{
3231	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3232	pgmPoolFlushAll(pVM);
3233	}
3234
3235	/*
3236	* Enter the new guest and shadow+guest modes.
3237	*/
3238	int rc = -1;
3239	int rc2 = -1;
3240	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3241	pVM->pgm.s.enmGuestMode = enmGuestMode;
3242	switch (enmGuestMode)
3243	{
3244	case PGMMODE_REAL:
3245	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3246	switch (pVM->pgm.s.enmShadowMode)
3247	{
3248	case PGMMODE_32_BIT:
3249	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3250	break;
3251	case PGMMODE_PAE:
3252	case PGMMODE_PAE_NX:
3253	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3254	break;
3255	case PGMMODE_NESTED:
3256	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3257	break;
3258	#ifdef PGM_WITH_EPT
3259	case PGMMODE_EPT:
3260	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3261	break;
3262	#endif
3263	case PGMMODE_AMD64:
3264	case PGMMODE_AMD64_NX:
3265	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3266	default: AssertFailed(); break;
3267	}
3268	break;
3269
3270	case PGMMODE_PROTECTED:
3271	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3272	switch (pVM->pgm.s.enmShadowMode)
3273	{
3274	case PGMMODE_32_BIT:
3275	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3276	break;
3277	case PGMMODE_PAE:
3278	case PGMMODE_PAE_NX:
3279	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3280	break;
3281	case PGMMODE_NESTED:
3282	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3283	break;
3284	#ifdef PGM_WITH_EPT
3285	case PGMMODE_EPT:
3286	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3287	break;
3288	#endif
3289	case PGMMODE_AMD64:
3290	case PGMMODE_AMD64_NX:
3291	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3292	default: AssertFailed(); break;
3293	}
3294	break;
3295
3296	case PGMMODE_32_BIT:
3297	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3298	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3299	switch (pVM->pgm.s.enmShadowMode)
3300	{
3301	case PGMMODE_32_BIT:
3302	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3303	break;
3304	case PGMMODE_PAE:
3305	case PGMMODE_PAE_NX:
3306	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3307	break;
3308	case PGMMODE_NESTED:
3309	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3310	break;
3311	#ifdef PGM_WITH_EPT
3312	case PGMMODE_EPT:
3313	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3314	break;
3315	#endif
3316	case PGMMODE_AMD64:
3317	case PGMMODE_AMD64_NX:
3318	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3319	default: AssertFailed(); break;
3320	}
3321	break;
3322
3323	case PGMMODE_PAE_NX:
3324	case PGMMODE_PAE:
3325	{
3326	uint32_t u32Dummy, u32Features;
3327
3328	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3329	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3330	{
3331	/* Pause first, then inform Main. */
3332	rc = VMR3SuspendNoSave(pVM);
3333	AssertRC(rc);
3334
3335	VMSetRuntimeError(pVM, true, "PAEmode",
3336	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage"));
3337	/* we must return TRUE here otherwise the recompiler will assert */
3338	return VINF_SUCCESS;
3339	}
3340	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3341	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3342	switch (pVM->pgm.s.enmShadowMode)
3343	{
3344	case PGMMODE_PAE:
3345	case PGMMODE_PAE_NX:
3346	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3347	break;
3348	case PGMMODE_NESTED:
3349	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3350	break;
3351	#ifdef PGM_WITH_EPT
3352	case PGMMODE_EPT:
3353	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3354	break;
3355	#endif
3356	case PGMMODE_32_BIT:
3357	case PGMMODE_AMD64:
3358	case PGMMODE_AMD64_NX:
3359	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3360	default: AssertFailed(); break;
3361	}
3362	break;
3363	}
3364
3365	case PGMMODE_AMD64_NX:
3366	case PGMMODE_AMD64:
3367	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3368	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3369	switch (pVM->pgm.s.enmShadowMode)
3370	{
3371	case PGMMODE_AMD64:
3372	case PGMMODE_AMD64_NX:
3373	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3374	break;
3375	case PGMMODE_NESTED:
3376	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3377	break;
3378	#ifdef PGM_WITH_EPT
3379	case PGMMODE_EPT:
3380	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3381	break;
3382	#endif
3383	case PGMMODE_32_BIT:
3384	case PGMMODE_PAE:
3385	case PGMMODE_PAE_NX:
3386	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3387	default: AssertFailed(); break;
3388	}
3389	break;
3390
3391	default:
3392	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3393	rc = VERR_NOT_IMPLEMENTED;
3394	break;
3395	}
3396
3397	/* status codes. */
3398	AssertRC(rc);
3399	AssertRC(rc2);
3400	if (VBOX_SUCCESS(rc))
3401	{
3402	rc = rc2;
3403	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3404	rc = VINF_SUCCESS;
3405	}
3406
3407	/*
3408	* Notify SELM so it can update the TSSes with correct CR3s.
3409	*/
3410	SELMR3PagingModeChanged(pVM);
3411
3412	/* Notify HWACCM as well. */
3413	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3414	return rc;
3415	}
3416
3417
3418	/**
3419	* Dumps a PAE shadow page table.
3420	*
3421	* @returns VBox status code (VINF_SUCCESS).
3422	* @param pVM The VM handle.
3423	* @param pPT Pointer to the page table.
3424	* @param u64Address The virtual address of the page table starts.
3425	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3426	* @param cMaxDepth The maxium depth.
3427	* @param pHlp Pointer to the output functions.
3428	*/
3429	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3430	{
3431	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3432	{
3433	X86PTEPAE Pte = pPT->a[i];
3434	if (Pte.n.u1Present)
3435	{
3436	pHlp->pfnPrintf(pHlp,
3437	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3438	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3439	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3440	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3441	Pte.n.u1Write ? 'W' : 'R',
3442	Pte.n.u1User ? 'U' : 'S',
3443	Pte.n.u1Accessed ? 'A' : '-',
3444	Pte.n.u1Dirty ? 'D' : '-',
3445	Pte.n.u1Global ? 'G' : '-',
3446	Pte.n.u1WriteThru ? "WT" : "--",
3447	Pte.n.u1CacheDisable? "CD" : "--",
3448	Pte.n.u1PAT ? "AT" : "--",
3449	Pte.n.u1NoExecute ? "NX" : "--",
3450	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3451	Pte.u & RT_BIT(10) ? '1' : '0',
3452	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3453	Pte.u & X86_PTE_PAE_PG_MASK);
3454	}
3455	}
3456	return VINF_SUCCESS;
3457	}
3458
3459
3460	/**
3461	* Dumps a PAE shadow page directory table.
3462	*
3463	* @returns VBox status code (VINF_SUCCESS).
3464	* @param pVM The VM handle.
3465	* @param HCPhys The physical address of the page directory table.
3466	* @param u64Address The virtual address of the page table starts.
3467	* @param cr4 The CR4, PSE is currently used.
3468	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3469	* @param cMaxDepth The maxium depth.
3470	* @param pHlp Pointer to the output functions.
3471	*/
3472	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3473	{
3474	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3475	if (!pPD)
3476	{
3477	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3478	fLongMode ? 16 : 8, u64Address, HCPhys);
3479	return VERR_INVALID_PARAMETER;
3480	}
3481	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3482
3483	int rc = VINF_SUCCESS;
3484	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3485	{
3486	X86PDEPAE Pde = pPD->a[i];
3487	if (Pde.n.u1Present)
3488	{
3489	if (fBigPagesSupported && Pde.b.u1Size)
3490	pHlp->pfnPrintf(pHlp,
3491	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3492	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3493	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3494	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3495	Pde.b.u1Write ? 'W' : 'R',
3496	Pde.b.u1User ? 'U' : 'S',
3497	Pde.b.u1Accessed ? 'A' : '-',
3498	Pde.b.u1Dirty ? 'D' : '-',
3499	Pde.b.u1Global ? 'G' : '-',
3500	Pde.b.u1WriteThru ? "WT" : "--",
3501	Pde.b.u1CacheDisable? "CD" : "--",
3502	Pde.b.u1PAT ? "AT" : "--",
3503	Pde.b.u1NoExecute ? "NX" : "--",
3504	Pde.u & RT_BIT_64(9) ? '1' : '0',
3505	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3506	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3507	Pde.u & X86_PDE_PAE_PG_MASK);
3508	else
3509	{
3510	pHlp->pfnPrintf(pHlp,
3511	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3512	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3513	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3514	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3515	Pde.n.u1Write ? 'W' : 'R',
3516	Pde.n.u1User ? 'U' : 'S',
3517	Pde.n.u1Accessed ? 'A' : '-',
3518	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3519	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3520	Pde.n.u1WriteThru ? "WT" : "--",
3521	Pde.n.u1CacheDisable? "CD" : "--",
3522	Pde.n.u1NoExecute ? "NX" : "--",
3523	Pde.u & RT_BIT_64(9) ? '1' : '0',
3524	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3525	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3526	Pde.u & X86_PDE_PAE_PG_MASK);
3527	if (cMaxDepth >= 1)
3528	{
3529	/** @todo what about using the page pool for mapping PTs? */
3530	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3531	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3532	PX86PTPAE pPT = NULL;
3533	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3534	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3535	else
3536	{
3537	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3538	{
3539	uint64_t off = u64AddressPT - pMap->GCPtr;
3540	if (off < pMap->cb)
3541	{
3542	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3543	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3544	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3545	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3546	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3547	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3548	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3549	}
3550	}
3551	}
3552	int rc2 = VERR_INVALID_PARAMETER;
3553	if (pPT)
3554	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3555	else
3556	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3557	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3558	if (rc2 < rc && VBOX_SUCCESS(rc))
3559	rc = rc2;
3560	}
3561	}
3562	}
3563	}
3564	return rc;
3565	}
3566
3567
3568	/**
3569	* Dumps a PAE shadow page directory pointer table.
3570	*
3571	* @returns VBox status code (VINF_SUCCESS).
3572	* @param pVM The VM handle.
3573	* @param HCPhys The physical address of the page directory pointer table.
3574	* @param u64Address The virtual address of the page table starts.
3575	* @param cr4 The CR4, PSE is currently used.
3576	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3577	* @param cMaxDepth The maxium depth.
3578	* @param pHlp Pointer to the output functions.
3579	*/
3580	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3581	{
3582	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3583	if (!pPDPT)
3584	{
3585	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3586	fLongMode ? 16 : 8, u64Address, HCPhys);
3587	return VERR_INVALID_PARAMETER;
3588	}
3589
3590	int rc = VINF_SUCCESS;
3591	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3592	for (unsigned i = 0; i < c; i++)
3593	{
3594	X86PDPE Pdpe = pPDPT->a[i];
3595	if (Pdpe.n.u1Present)
3596	{
3597	if (fLongMode)
3598	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3599	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3600	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3601	Pdpe.lm.u1Write ? 'W' : 'R',
3602	Pdpe.lm.u1User ? 'U' : 'S',
3603	Pdpe.lm.u1Accessed ? 'A' : '-',
3604	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3605	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3606	Pdpe.lm.u1WriteThru ? "WT" : "--",
3607	Pdpe.lm.u1CacheDisable? "CD" : "--",
3608	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3609	Pdpe.lm.u1NoExecute ? "NX" : "--",
3610	Pdpe.u & RT_BIT(9) ? '1' : '0',
3611	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3612	Pdpe.u & RT_BIT(11) ? '1' : '0',
3613	Pdpe.u & X86_PDPE_PG_MASK);
3614	else
3615	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3616	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3617	i << X86_PDPT_SHIFT,
3618	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3619	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3620	Pdpe.n.u1WriteThru ? "WT" : "--",
3621	Pdpe.n.u1CacheDisable? "CD" : "--",
3622	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3623	Pdpe.u & RT_BIT(9) ? '1' : '0',
3624	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3625	Pdpe.u & RT_BIT(11) ? '1' : '0',
3626	Pdpe.u & X86_PDPE_PG_MASK);
3627	if (cMaxDepth >= 1)
3628	{
3629	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3630	cr4, fLongMode, cMaxDepth - 1, pHlp);
3631	if (rc2 < rc && VBOX_SUCCESS(rc))
3632	rc = rc2;
3633	}
3634	}
3635	}
3636	return rc;
3637	}
3638
3639
3640	/**
3641	* Dumps a 32-bit shadow page table.
3642	*
3643	* @returns VBox status code (VINF_SUCCESS).
3644	* @param pVM The VM handle.
3645	* @param HCPhys The physical address of the table.
3646	* @param cr4 The CR4, PSE is currently used.
3647	* @param cMaxDepth The maxium depth.
3648	* @param pHlp Pointer to the output functions.
3649	*/
3650	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3651	{
3652	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3653	if (!pPML4)
3654	{
3655	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3656	return VERR_INVALID_PARAMETER;
3657	}
3658
3659	int rc = VINF_SUCCESS;
3660	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3661	{
3662	X86PML4E Pml4e = pPML4->a[i];
3663	if (Pml4e.n.u1Present)
3664	{
3665	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3666	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3667	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3668	u64Address,
3669	Pml4e.n.u1Write ? 'W' : 'R',
3670	Pml4e.n.u1User ? 'U' : 'S',
3671	Pml4e.n.u1Accessed ? 'A' : '-',
3672	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3673	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3674	Pml4e.n.u1WriteThru ? "WT" : "--",
3675	Pml4e.n.u1CacheDisable? "CD" : "--",
3676	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3677	Pml4e.n.u1NoExecute ? "NX" : "--",
3678	Pml4e.u & RT_BIT(9) ? '1' : '0',
3679	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3680	Pml4e.u & RT_BIT(11) ? '1' : '0',
3681	Pml4e.u & X86_PML4E_PG_MASK);
3682
3683	if (cMaxDepth >= 1)
3684	{
3685	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3686	if (rc2 < rc && VBOX_SUCCESS(rc))
3687	rc = rc2;
3688	}
3689	}
3690	}
3691	return rc;
3692	}
3693
3694
3695	/**
3696	* Dumps a 32-bit shadow page table.
3697	*
3698	* @returns VBox status code (VINF_SUCCESS).
3699	* @param pVM The VM handle.
3700	* @param pPT Pointer to the page table.
3701	* @param u32Address The virtual address this table starts at.
3702	* @param pHlp Pointer to the output functions.
3703	*/
3704	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3705	{
3706	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3707	{
3708	X86PTE Pte = pPT->a[i];
3709	if (Pte.n.u1Present)
3710	{
3711	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3712	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3713	u32Address + (i << X86_PT_SHIFT),
3714	Pte.n.u1Write ? 'W' : 'R',
3715	Pte.n.u1User ? 'U' : 'S',
3716	Pte.n.u1Accessed ? 'A' : '-',
3717	Pte.n.u1Dirty ? 'D' : '-',
3718	Pte.n.u1Global ? 'G' : '-',
3719	Pte.n.u1WriteThru ? "WT" : "--",
3720	Pte.n.u1CacheDisable? "CD" : "--",
3721	Pte.n.u1PAT ? "AT" : "--",
3722	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3723	Pte.u & RT_BIT(10) ? '1' : '0',
3724	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3725	Pte.u & X86_PDE_PG_MASK);
3726	}
3727	}
3728	return VINF_SUCCESS;
3729	}
3730
3731
3732	/**
3733	* Dumps a 32-bit shadow page directory and page tables.
3734	*
3735	* @returns VBox status code (VINF_SUCCESS).
3736	* @param pVM The VM handle.
3737	* @param cr3 The root of the hierarchy.
3738	* @param cr4 The CR4, PSE is currently used.
3739	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3740	* @param pHlp Pointer to the output functions.
3741	*/
3742	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3743	{
3744	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3745	if (!pPD)
3746	{
3747	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3748	return VERR_INVALID_PARAMETER;
3749	}
3750
3751	int rc = VINF_SUCCESS;
3752	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3753	{
3754	X86PDE Pde = pPD->a[i];
3755	if (Pde.n.u1Present)
3756	{
3757	const uint32_t u32Address = i << X86_PD_SHIFT;
3758	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3759	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3760	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3761	u32Address,
3762	Pde.b.u1Write ? 'W' : 'R',
3763	Pde.b.u1User ? 'U' : 'S',
3764	Pde.b.u1Accessed ? 'A' : '-',
3765	Pde.b.u1Dirty ? 'D' : '-',
3766	Pde.b.u1Global ? 'G' : '-',
3767	Pde.b.u1WriteThru ? "WT" : "--",
3768	Pde.b.u1CacheDisable? "CD" : "--",
3769	Pde.b.u1PAT ? "AT" : "--",
3770	Pde.u & RT_BIT_64(9) ? '1' : '0',
3771	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3772	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3773	Pde.u & X86_PDE4M_PG_MASK);
3774	else
3775	{
3776	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3777	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3778	u32Address,
3779	Pde.n.u1Write ? 'W' : 'R',
3780	Pde.n.u1User ? 'U' : 'S',
3781	Pde.n.u1Accessed ? 'A' : '-',
3782	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3783	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3784	Pde.n.u1WriteThru ? "WT" : "--",
3785	Pde.n.u1CacheDisable? "CD" : "--",
3786	Pde.u & RT_BIT_64(9) ? '1' : '0',
3787	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3788	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3789	Pde.u & X86_PDE_PG_MASK);
3790	if (cMaxDepth >= 1)
3791	{
3792	/** @todo what about using the page pool for mapping PTs? */
3793	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3794	PX86PT pPT = NULL;
3795	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3796	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3797	else
3798	{
3799	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3800	if (u32Address - pMap->GCPtr < pMap->cb)
3801	{
3802	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3803	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3804	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3805	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3806	pPT = pMap->aPTs[iPDE].pPTR3;
3807	}
3808	}
3809	int rc2 = VERR_INVALID_PARAMETER;
3810	if (pPT)
3811	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3812	else
3813	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3814	if (rc2 < rc && VBOX_SUCCESS(rc))
3815	rc = rc2;
3816	}
3817	}
3818	}
3819	}
3820
3821	return rc;
3822	}
3823
3824
3825	/**
3826	* Dumps a 32-bit shadow page table.
3827	*
3828	* @returns VBox status code (VINF_SUCCESS).
3829	* @param pVM The VM handle.
3830	* @param pPT Pointer to the page table.
3831	* @param u32Address The virtual address this table starts at.
3832	* @param PhysSearch Address to search for.
3833	*/
3834	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3835	{
3836	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3837	{
3838	X86PTE Pte = pPT->a[i];
3839	if (Pte.n.u1Present)
3840	{
3841	Log(( /P R S A D G WT CD AT NX 4M a m d /
3842	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3843	u32Address + (i << X86_PT_SHIFT),
3844	Pte.n.u1Write ? 'W' : 'R',
3845	Pte.n.u1User ? 'U' : 'S',
3846	Pte.n.u1Accessed ? 'A' : '-',
3847	Pte.n.u1Dirty ? 'D' : '-',
3848	Pte.n.u1Global ? 'G' : '-',
3849	Pte.n.u1WriteThru ? "WT" : "--",
3850	Pte.n.u1CacheDisable? "CD" : "--",
3851	Pte.n.u1PAT ? "AT" : "--",
3852	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3853	Pte.u & RT_BIT(10) ? '1' : '0',
3854	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3855	Pte.u & X86_PDE_PG_MASK));
3856
3857	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3858	{
3859	uint64_t fPageShw = 0;
3860	RTHCPHYS pPhysHC = 0;
3861
3862	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3863	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3864	}
3865	}
3866	}
3867	return VINF_SUCCESS;
3868	}
3869
3870
3871	/**
3872	* Dumps a 32-bit guest page directory and page tables.
3873	*
3874	* @returns VBox status code (VINF_SUCCESS).
3875	* @param pVM The VM handle.
3876	* @param cr3 The root of the hierarchy.
3877	* @param cr4 The CR4, PSE is currently used.
3878	* @param PhysSearch Address to search for.
3879	*/
3880	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3881	{
3882	bool fLongMode = false;
3883	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3884	PX86PD pPD = 0;
3885
3886	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3887	if (VBOX_FAILURE(rc) \|\| !pPD)
3888	{
3889	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3890	return VERR_INVALID_PARAMETER;
3891	}
3892
3893	Log(("cr3=%08x cr4=%08x%s\n"
3894	"%-*s P - Present\n"
3895	"%-*s \| R/W - Read (0) / Write (1)\n"
3896	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3897	"%-*s \| \| \| A - Accessed\n"
3898	"%-*s \| \| \| \| D - Dirty\n"
3899	"%-*s \| \| \| \| \| G - Global\n"
3900	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3901	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3902	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3903	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3904	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3905	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3906	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3907	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3908	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3909	- W U - - - -- -- -- -- -- 010 */
3910	, cr3, cr4, fLongMode ? " Long Mode" : "",
3911	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3912	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3913
3914	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3915	{
3916	X86PDE Pde = pPD->a[i];
3917	if (Pde.n.u1Present)
3918	{
3919	const uint32_t u32Address = i << X86_PD_SHIFT;
3920
3921	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3922	Log(( /P R S A D G WT CD AT NX 4M a m d /
3923	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3924	u32Address,
3925	Pde.b.u1Write ? 'W' : 'R',
3926	Pde.b.u1User ? 'U' : 'S',
3927	Pde.b.u1Accessed ? 'A' : '-',
3928	Pde.b.u1Dirty ? 'D' : '-',
3929	Pde.b.u1Global ? 'G' : '-',
3930	Pde.b.u1WriteThru ? "WT" : "--",
3931	Pde.b.u1CacheDisable? "CD" : "--",
3932	Pde.b.u1PAT ? "AT" : "--",
3933	Pde.u & RT_BIT(9) ? '1' : '0',
3934	Pde.u & RT_BIT(10) ? '1' : '0',
3935	Pde.u & RT_BIT(11) ? '1' : '0',
3936	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3937	/** @todo PhysSearch */
3938	else
3939	{
3940	Log(( /P R S A D G WT CD AT NX 4M a m d /
3941	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3942	u32Address,
3943	Pde.n.u1Write ? 'W' : 'R',
3944	Pde.n.u1User ? 'U' : 'S',
3945	Pde.n.u1Accessed ? 'A' : '-',
3946	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3947	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3948	Pde.n.u1WriteThru ? "WT" : "--",
3949	Pde.n.u1CacheDisable? "CD" : "--",
3950	Pde.u & RT_BIT(9) ? '1' : '0',
3951	Pde.u & RT_BIT(10) ? '1' : '0',
3952	Pde.u & RT_BIT(11) ? '1' : '0',
3953	Pde.u & X86_PDE_PG_MASK));
3954	////if (cMaxDepth >= 1)
3955	{
3956	/** @todo what about using the page pool for mapping PTs? */
3957	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3958	PX86PT pPT = NULL;
3959
3960	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3961
3962	int rc2 = VERR_INVALID_PARAMETER;
3963	if (pPT)
3964	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3965	else
3966	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3967	if (rc2 < rc && VBOX_SUCCESS(rc))
3968	rc = rc2;
3969	}
3970	}
3971	}
3972	}
3973
3974	return rc;
3975	}
3976
3977
3978	/**
3979	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3980	*
3981	* @returns VBox status code (VINF_SUCCESS).
3982	* @param pVM The VM handle.
3983	* @param cr3 The root of the hierarchy.
3984	* @param cr4 The cr4, only PAE and PSE is currently used.
3985	* @param fLongMode Set if long mode, false if not long mode.
3986	* @param cMaxDepth Number of levels to dump.
3987	* @param pHlp Pointer to the output functions.
3988	*/
3989	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3990	{
3991	if (!pHlp)
3992	pHlp = DBGFR3InfoLogHlp();
3993	if (!cMaxDepth)
3994	return VINF_SUCCESS;
3995	const unsigned cch = fLongMode ? 16 : 8;
3996	pHlp->pfnPrintf(pHlp,
3997	"cr3=%08x cr4=%08x%s\n"
3998	"%-*s P - Present\n"
3999	"%-*s \| R/W - Read (0) / Write (1)\n"
4000	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4001	"%-*s \| \| \| A - Accessed\n"
4002	"%-*s \| \| \| \| D - Dirty\n"
4003	"%-*s \| \| \| \| \| G - Global\n"
4004	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4005	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4006	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4007	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4008	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4009	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4010	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4011	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4012	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4013	- W U - - - -- -- -- -- -- 010 */
4014	, cr3, cr4, fLongMode ? " Long Mode" : "",
4015	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4016	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4017	if (cr4 & X86_CR4_PAE)
4018	{
4019	if (fLongMode)
4020	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4021	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4022	}
4023	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4024	}
4025
4026
4027
4028	#ifdef VBOX_WITH_DEBUGGER
4029	/**
4030	* The '.pgmram' command.
4031	*
4032	* @returns VBox status.
4033	* @param pCmd Pointer to the command descriptor (as registered).
4034	* @param pCmdHlp Pointer to command helper functions.
4035	* @param pVM Pointer to the current VM (if any).
4036	* @param paArgs Pointer to (readonly) array of arguments.
4037	* @param cArgs Number of arguments in the array.
4038	*/
4039	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4040	{
4041	/*
4042	* Validate input.
4043	*/
4044	if (!pVM)
4045	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4046	if (!pVM->pgm.s.pRamRangesGC)
4047	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4048
4049	/*
4050	* Dump the ranges.
4051	*/
4052	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4053	PPGMRAMRANGE pRam;
4054	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4055	{
4056	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4057	"%VGp - %VGp %p\n",
4058	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
4059	if (VBOX_FAILURE(rc))
4060	return rc;
4061	}
4062
4063	return VINF_SUCCESS;
4064	}
4065
4066
4067	/**
4068	* The '.pgmmap' command.
4069	*
4070	* @returns VBox status.
4071	* @param pCmd Pointer to the command descriptor (as registered).
4072	* @param pCmdHlp Pointer to command helper functions.
4073	* @param pVM Pointer to the current VM (if any).
4074	* @param paArgs Pointer to (readonly) array of arguments.
4075	* @param cArgs Number of arguments in the array.
4076	*/
4077	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4078	{
4079	/*
4080	* Validate input.
4081	*/
4082	if (!pVM)
4083	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4084	if (!pVM->pgm.s.pMappingsR3)
4085	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4086
4087	/*
4088	* Print message about the fixedness of the mappings.
4089	*/
4090	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4091	if (VBOX_FAILURE(rc))
4092	return rc;
4093
4094	/*
4095	* Dump the ranges.
4096	*/
4097	PPGMMAPPING pCur;
4098	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4099	{
4100	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4101	"%08x - %08x %s\n",
4102	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4103	if (VBOX_FAILURE(rc))
4104	return rc;
4105	}
4106
4107	return VINF_SUCCESS;
4108	}
4109
4110
4111	/**
4112	* The '.pgmsync' command.
4113	*
4114	* @returns VBox status.
4115	* @param pCmd Pointer to the command descriptor (as registered).
4116	* @param pCmdHlp Pointer to command helper functions.
4117	* @param pVM Pointer to the current VM (if any).
4118	* @param paArgs Pointer to (readonly) array of arguments.
4119	* @param cArgs Number of arguments in the array.
4120	*/
4121	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4122	{
4123	/*
4124	* Validate input.
4125	*/
4126	if (!pVM)
4127	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4128
4129	/*
4130	* Force page directory sync.
4131	*/
4132	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4133
4134	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4135	if (VBOX_FAILURE(rc))
4136	return rc;
4137
4138	return VINF_SUCCESS;
4139	}
4140
4141
4142	#ifdef VBOX_STRICT
4143	/**
4144	* The '.pgmassertcr3' command.
4145	*
4146	* @returns VBox status.
4147	* @param pCmd Pointer to the command descriptor (as registered).
4148	* @param pCmdHlp Pointer to command helper functions.
4149	* @param pVM Pointer to the current VM (if any).
4150	* @param paArgs Pointer to (readonly) array of arguments.
4151	* @param cArgs Number of arguments in the array.
4152	*/
4153	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4154	{
4155	/*
4156	* Validate input.
4157	*/
4158	if (!pVM)
4159	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4160
4161	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4162	if (VBOX_FAILURE(rc))
4163	return rc;
4164
4165	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4166
4167	return VINF_SUCCESS;
4168	}
4169	#endif
4170
4171	/**
4172	* The '.pgmsyncalways' command.
4173	*
4174	* @returns VBox status.
4175	* @param pCmd Pointer to the command descriptor (as registered).
4176	* @param pCmdHlp Pointer to command helper functions.
4177	* @param pVM Pointer to the current VM (if any).
4178	* @param paArgs Pointer to (readonly) array of arguments.
4179	* @param cArgs Number of arguments in the array.
4180	*/
4181	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4182	{
4183	/*
4184	* Validate input.
4185	*/
4186	if (!pVM)
4187	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4188
4189	/*
4190	* Force page directory sync.
4191	*/
4192	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4193	{
4194	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4195	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4196	}
4197	else
4198	{
4199	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4200	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4201	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4202	}
4203	}
4204
4205	#endif
4206
4207	/**
4208	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4209	*/
4210	typedef struct PGMCHECKINTARGS
4211	{
4212	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4213	PPGMPHYSHANDLER pPrevPhys;
4214	PPGMVIRTHANDLER pPrevVirt;
4215	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4216	PVM pVM;
4217	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4218
4219	/**
4220	* Validate a node in the physical handler tree.
4221	*
4222	* @returns 0 on if ok, other wise 1.
4223	* @param pNode The handler node.
4224	* @param pvUser pVM.
4225	*/
4226	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4227	{
4228	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4229	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4230	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4231	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4232	AssertReleaseMsg( !pArgs->pPrevPhys
4233	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4234	("pPrevPhys=%p %VGp-%VGp %s\n"
4235	" pCur=%p %VGp-%VGp %s\n",
4236	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4237	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4238	pArgs->pPrevPhys = pCur;
4239	return 0;
4240	}
4241
4242
4243	/**
4244	* Validate a node in the virtual handler tree.
4245	*
4246	* @returns 0 on if ok, other wise 1.
4247	* @param pNode The handler node.
4248	* @param pvUser pVM.
4249	*/
4250	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4251	{
4252	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4253	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4254	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4255	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4256	AssertReleaseMsg( !pArgs->pPrevVirt
4257	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4258	("pPrevVirt=%p %VGv-%VGv %s\n"
4259	" pCur=%p %VGv-%VGv %s\n",
4260	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4261	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4262	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4263	{
4264	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4265	("pCur=%p %VGv-%VGv %s\n"
4266	"iPage=%d offVirtHandle=%#x expected %#x\n",
4267	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4268	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4269	}
4270	pArgs->pPrevVirt = pCur;
4271	return 0;
4272	}
4273
4274
4275	/**
4276	* Validate a node in the virtual handler tree.
4277	*
4278	* @returns 0 on if ok, other wise 1.
4279	* @param pNode The handler node.
4280	* @param pvUser pVM.
4281	*/
4282	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4283	{
4284	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4285	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4286	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4287	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4288	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4289	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4290	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4291	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4292	" pCur=%p %VGp-%VGp\n",
4293	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4294	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4295	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4296	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4297	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4298	" pCur=%p %VGp-%VGp\n",
4299	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4300	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4301	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4302	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4303	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4304	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4305	{
4306	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4307	for (;;)
4308	{
4309	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4310	AssertReleaseMsg(pCur2 != pCur,
4311	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4312	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4313	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4314	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4315	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4316	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4317	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4318	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4319	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4320	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4321	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4322	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4323	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4324	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4325	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4326	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4327	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4328	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4329	break;
4330	}
4331	}
4332
4333	pArgs->pPrevPhys2Virt = pCur;
4334	return 0;
4335	}
4336
4337
4338	/**
4339	* Perform an integrity check on the PGM component.
4340	*
4341	* @returns VINF_SUCCESS if everything is fine.
4342	* @returns VBox error status after asserting on integrity breach.
4343	* @param pVM The VM handle.
4344	*/
4345	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4346	{
4347	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4348
4349	/*
4350	* Check the trees.
4351	*/
4352	int cErrors = 0;
4353	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4354	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4355	PGMCHECKINTARGS Args = s_LeftToRight;
4356	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4357	Args = s_RightToLeft;
4358	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4359	Args = s_LeftToRight;
4360	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4361	Args = s_RightToLeft;
4362	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4363	Args = s_LeftToRight;
4364	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4365	Args = s_RightToLeft;
4366	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4367	Args = s_LeftToRight;
4368	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4369	Args = s_RightToLeft;
4370	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4371
4372	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4373	}
4374
4375
4376	/**
4377	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4378	*
4379	* @returns VBox status code.
4380	* @param pVM VM handle.
4381	* @param fEnable Enable or disable shadow mappings
4382	*/
4383	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4384	{
4385	pVM->pgm.s.fDisableMappings = !fEnable;
4386
4387	uint32_t cb;
4388	int rc = PGMR3MappingsSize(pVM, &cb);
4389	AssertRCReturn(rc, rc);
4390
4391	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4392	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4393	AssertRCReturn(rc, rc);
4394
4395	return VINF_SUCCESS;
4396	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 12681

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