PGM.cpp@ 5605

Last change on this file since 5605 was 5605, checked in by vboxsync, 17 years ago
BIT => RT_BIT, BIT64 => RT_BIT_64. BIT() is defined in Linux 2.6.24
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1	/* $Id: PGM.cpp 5605 2007-11-01 16:09:26Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	*
22	*
23	* @section sec_pgm_modes Paging Modes
24	*
25	* There are three memory contexts: Host Context (HC), Guest Context (GC)
26	* and intermediate context. When talking about paging HC can also be refered to
27	* as "host paging", and GC refered to as "shadow paging".
28	*
29	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
30	* is defined by the host operating system. The mode used in the shadow paging mode
31	* depends on the host paging mode and what the mode the guest is currently in. The
32	* following relation between the two is defined:
33	*
34	* @verbatim
35	Host > 32-bit \| PAE \| AMD64 \|
36	Guest \| \| \| \|
37	==v================================
38	32-bit 32-bit PAE PAE
39	-------\|--------\|--------\|--------\|
40	PAE PAE PAE PAE
41	-------\|--------\|--------\|--------\|
42	AMD64 AMD64 AMD64 AMD64
43	-------\|--------\|--------\|--------\| @endverbatim
44	*
45	* All configuration except those in the diagonal (upper left) are expected to
46	* require special effort from the switcher (i.e. a bit slower).
47	*
48	*
49	*
50	*
51	* @section sec_pgm_shw The Shadow Memory Context
52	*
53	*
54	* [..]
55	*
56	* Because of guest context mappings requires PDPTR and PML4 entries to allow
57	* writing on AMD64, the two upper levels will have fixed flags whatever the
58	* guest is thinking of using there. So, when shadowing the PD level we will
59	* calculate the effective flags of PD and all the higher levels. In legacy
60	* PAE mode this only applies to the PWT and PCD bits (the rest are
61	* ignored/reserved/MBZ). We will ignore those bits for the present.
62	*
63	*
64	*
65	* @section sec_pgm_int The Intermediate Memory Context
66	*
67	* The world switch goes thru an intermediate memory context which purpose it is
68	* to provide different mappings of the switcher code. All guest mappings are also
69	* present in this context.
70	*
71	* The switcher code is mapped at the same location as on the host, at an
72	* identity mapped location (physical equals virtual address), and at the
73	* hypervisor location.
74	*
75	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
76	* simplifies switching guest CPU mode and consistency at the cost of more
77	* code to do the work. All memory use for those page tables is located below
78	* 4GB (this includes page tables for guest context mappings).
79	*
80	*
81	* @subsection subsec_pgm_int_gc Guest Context Mappings
82	*
83	* During assignment and relocation of a guest context mapping the intermediate
84	* memory context is used to verify the new location.
85	*
86	* Guest context mappings are currently restricted to below 4GB, for reasons
87	* of simplicity. This may change when we implement AMD64 support.
88	*
89	*
90	*
91	*
92	* @section sec_pgm_misc Misc
93	*
94	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
95	*
96	* The differences between legacy PAE and long mode PAE are:
97	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
98	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
99	* usual meanings while 6 is ignored (AMD). This means that upon switching to
100	* legacy PAE mode we'll have to clear these bits and when going to long mode
101	* they must be set. This applies to both intermediate and shadow contexts,
102	* however we don't need to do it for the intermediate one since we're
103	* executing with CR0.WP at that time.
104	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
105	* a page aligned one is required.
106	*/
107
108
109	/** @page pg_pgmPhys PGMPhys - Physical Guest Memory Management.
110	*
111	*
112	* Objectives:
113	* - Guest RAM over-commitment using memory ballooning,
114	* zero pages and general page sharing.
115	* - Moving or mirroring a VM onto a different physical machine.
116	*
117	*
118	* @subsection subsec_pgmPhys_Definitions Definitions
119	*
120	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
121	* machinery assoicated with it.
122	*
123	*
124	*
125	*
126	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
127	*
128	* Initially we map all guest memory to the (per VM) zero page, which
129	* means that none of the read functions will cause pages to be allocated.
130	*
131	* Exception, access bit in page tables that have been shared. This must
132	* be handled, but we must also make sure PGMGst*Modify doesn't make
133	* unnecessary modifications.
134	*
135	* Allocation points:
136	* - PGMPhysWriteGCPhys and PGMPhysWrite.
137	* - Replacing a zero page mapping at \#PF.
138	* - Replacing a shared page mapping at \#PF.
139	* - ROM registration (currently MMR3RomRegister).
140	* - VM restore (pgmR3Load).
141	*
142	* For the first three it would make sense to keep a few pages handy
143	* until we've reached the max memory commitment for the VM.
144	*
145	* For the ROM registration, we know exactly how many pages we need
146	* and will request these from ring-0. For restore, we will save
147	* the number of non-zero pages in the saved state and allocate
148	* them up front. This would allow the ring-0 component to refuse
149	* the request if the isn't sufficient memory available for VM use.
150	*
151	* Btw. for both ROM and restore allocations we won't be requiring
152	* zeroed pages as they are going to be filled instantly.
153	*
154	*
155	* @subsection subsec_pgmPhys_FreePage Freeing a page
156	*
157	* There are a few points where a page can be freed:
158	* - After being replaced by the zero page.
159	* - After being replaced by a shared page.
160	* - After being ballooned by the guest additions.
161	* - At reset.
162	* - At restore.
163	*
164	* When freeing one or more pages they will be returned to the ring-0
165	* component and replaced by the zero page.
166	*
167	* The reasoning for clearing out all the pages on reset is that it will
168	* return us to the exact same state as on power on, and may thereby help
169	* us reduce the memory load on the system. Further it might have a
170	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
171	*
172	* On restore, as mention under the allocation topic, pages should be
173	* freed / allocated depending on how many is actually required by the
174	* new VM state. The simplest approach is to do like on reset, and free
175	* all non-ROM pages and then allocate what we need.
176	*
177	* A measure to prevent some fragmentation, would be to let each allocation
178	* chunk have some affinity towards the VM having allocated the most pages
179	* from it. Also, try make sure to allocate from allocation chunks that
180	* are almost full. Admittedly, both these measures might work counter to
181	* our intentions and its probably not worth putting a lot of effort,
182	* cpu time or memory into this.
183	*
184	*
185	* @subsection subsec_pgmPhys_SharePage Sharing a page
186	*
187	* The basic idea is that there there will be a idle priority kernel
188	* thread walking the non-shared VM pages hashing them and looking for
189	* pages with the same checksum. If such pages are found, it will compare
190	* them byte-by-byte to see if they actually are identical. If found to be
191	* identical it will allocate a shared page, copy the content, check that
192	* the page didn't change while doing this, and finally request both the
193	* VMs to use the shared page instead. If the page is all zeros (special
194	* checksum and byte-by-byte check) it will request the VM that owns it
195	* to replace it with the zero page.
196	*
197	* To make this efficient, we will have to make sure not to try share a page
198	* that will change its contents soon. This part requires the most work.
199	* A simple idea would be to request the VM to write monitor the page for
200	* a while to make sure it isn't modified any time soon. Also, it may
201	* make sense to skip pages that are being write monitored since this
202	* information is readily available to the thread if it works on the
203	* per-VM guest memory structures (presently called PGMRAMRANGE).
204	*
205	*
206	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
207	*
208	* The pages are organized in allocation chunks in ring-0, this is a necessity
209	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
210	* could easily work on a page-by-page basis if we liked. Whether this is possible
211	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
212	* become a problem as part of the idea here is that we wish to return memory to
213	* the host system.
214	*
215	* For instance, starting two VMs at the same time, they will both allocate the
216	* guest memory on-demand and if permitted their page allocations will be
217	* intermixed. Shut down one of the two VMs and it will be difficult to return
218	* any memory to the host system because the page allocation for the two VMs are
219	* mixed up in the same allocation chunks.
220	*
221	* To further complicate matters, when pages are freed because they have been
222	* ballooned or become shared/zero the whole idea is that the page is supposed
223	* to be reused by another VM or returned to the host system. This will cause
224	* allocation chunks to contain pages belonging to different VMs and prevent
225	* returning memory to the host when one of those VM shuts down.
226	*
227	* The only way to really deal with this problem is to move pages. This can
228	* either be done at VM shutdown and or by the idle priority worker thread
229	* that will be responsible for finding sharable/zero pages. The mechanisms
230	* involved for coercing a VM to move a page (or to do it for it) will be
231	* the same as when telling it to share/zero a page.
232	*
233	*
234	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
235	*
236	* There's a difficult balance between keeping the per-page tracking structures
237	* (global and guest page) easy to use and keeping them from eating too much
238	* memory. We have limited virtual memory resources available when operating in
239	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
240	* tracking structures will be attemted designed such that we can deal with up
241	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
242	*
243	*
244	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
245	*
246	* @see pg_GMM
247	*
248	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
249	*
250	* Fixed info is the physical address of the page (HCPhys) and the page id
251	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
252	* Today we've restricting ourselves to 40(-12) bits because this is the current
253	* restrictions of all AMD64 implementations (I think Barcelona will up this
254	* to 48(-12) bits, not that it really matters) and I needed the bits for
255	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
256	* decent range for the page id: 2^(28+12) = 1024TB.
257	*
258	* In additions to these, we'll have to keep maintaining the page flags as we
259	* currently do. Although it wouldn't harm to optimize these quite a bit, like
260	* for instance the ROM shouldn't depend on having a write handler installed
261	* in order for it to become read-only. A RO/RW bit should be considered so
262	* that the page syncing code doesn't have to mess about checking multiple
263	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
264	* figure out how to setup a shadow PTE. But this of course, is second
265	* priority at present. Current this requires 12 bits, but could probably
266	* be optimized to ~8.
267	*
268	* Then there's the 24 bits used to track which shadow page tables are
269	* currently mapping a page for the purpose of speeding up physical
270	* access handlers, and thereby the page pool cache. More bit for this
271	* purpose wouldn't hurt IIRC.
272	*
273	* Then there is a new bit in which we need to record what kind of page
274	* this is, shared, zero, normal or write-monitored-normal. This'll
275	* require 2 bits. One bit might be needed for indicating whether a
276	* write monitored page has been written to. And yet another one or
277	* two for tracking migration status. 3-4 bits total then.
278	*
279	* Whatever is left will can be used to record the sharabilitiy of a
280	* page. The page checksum will not be stored in the per-VM table as
281	* the idle thread will not be permitted to do modifications to it.
282	* It will instead have to keep its own working set of potentially
283	* shareable pages and their check sums and stuff.
284	*
285	* For the present we'll keep the current packing of the
286	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
287	* we'll have to change it to a struct with a total of 128-bits at
288	* our disposal.
289	*
290	* The initial layout will be like this:
291	* @verbatim
292	RTHCPHYS HCPhys; The current stuff.
293	63:40 Current shadow PT tracking stuff.
294	39:12 The physical page frame number.
295	11:0 The current flags.
296	uint32_t u28PageId : 28; The page id.
297	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
298	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
299	uint32_t u1Reserved : 1; Reserved for later.
300	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
301	@endverbatim
302	*
303	* The final layout will be something like this:
304	* @verbatim
305	RTHCPHYS HCPhys; The current stuff.
306	63:48 High page id (12+).
307	47:12 The physical page frame number.
308	11:0 Low page id.
309	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
310	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
311	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
312	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
313	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
314	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
315	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
316	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
317	@endverbatim
318	*
319	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
320	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
321	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
322	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
323	*
324	* A couple of cost examples for the total cost per-VM + kernel.
325	* 32-bit Windows and 32-bit linux:
326	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
327	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
328	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
329	* 64-bit Windows and 64-bit linux:
330	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
331	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
332	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
333	*
334	* UPDATE - 2007-09-27:
335	* Will need a ballooned flag/state too because we cannot
336	* trust the guest 100% and reporting the same page as ballooned more
337	* than once will put the GMM off balance.
338	*
339	*
340	* @subsection subsec_pgmPhys_Serializing Serializing Access
341	*
342	* Initially, we'll try a simple scheme:
343	*
344	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
345	* by the EMT thread of that VM while in the pgm critsect.
346	* - Other threads in the VM process that needs to make reliable use of
347	* the per-VM RAM tracking structures will enter the critsect.
348	* - No process external thread or kernel thread will ever try enter
349	* the pgm critical section, as that just won't work.
350	* - The idle thread (and similar threads) doesn't not need 100% reliable
351	* data when performing it tasks as the EMT thread will be the one to
352	* do the actual changes later anyway. So, as long as it only accesses
353	* the main ram range, it can do so by somehow preventing the VM from
354	* being destroyed while it works on it...
355	*
356	* - The over-commitment management, including the allocating/freeing
357	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
358	* more mundane mutex implementation is broken on Linux).
359	* - A separeate mutex is protecting the set of allocation chunks so
360	* that pages can be shared or/and freed up while some other VM is
361	* allocating more chunks. This mutex can be take from under the other
362	* one, but not the otherway around.
363	*
364	*
365	* @subsection subsec_pgmPhys_Request VM Request interface
366	*
367	* When in ring-0 it will become necessary to send requests to a VM so it can
368	* for instance move a page while defragmenting during VM destroy. The idle
369	* thread will make use of this interface to request VMs to setup shared
370	* pages and to perform write monitoring of pages.
371	*
372	* I would propose an interface similar to the current VMReq interface, similar
373	* in that it doesn't require locking and that the one sending the request may
374	* wait for completion if it wishes to. This shouldn't be very difficult to
375	* realize.
376	*
377	* The requests themselves are also pretty simple. They are basically:
378	* -# Check that some precondition is still true.
379	* -# Do the update.
380	* -# Update all shadow page tables involved with the page.
381	*
382	* The 3rd step is identical to what we're already doing when updating a
383	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
384	*
385	*
386	*
387	* @section sec_pgmPhys_MappingCaches Mapping Caches
388	*
389	* In order to be able to map in and out memory and to be able to support
390	* guest with more RAM than we've got virtual address space, we'll employing
391	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
392	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
393	* memory context for the HWACCM execution.
394	*
395	*
396	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
397	*
398	* We've considered implementing the ring-3 mapping cache page based but found
399	* that this was bother some when one had to take into account TLBs+SMP and
400	* portability (missing the necessary APIs on several platforms). There were
401	* also some performance concerns with this approach which hadn't quite been
402	* worked out.
403	*
404	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
405	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
406	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
407	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
408	* costly than a single page, although how much more costly is uncertain. We'll
409	* try address this by using a very big cache, preferably bigger than the actual
410	* VM RAM size if possible. The current VM RAM sizes should give some idea for
411	* 32-bit boxes, while on 64-bit we can probably get away with employing an
412	* unlimited cache.
413	*
414	* The cache have to parts, as already indicated, the ring-3 side and the
415	* ring-0 side.
416	*
417	* The ring-0 will be tied to the page allocator since it will operate on the
418	* memory objects it contains. It will therefore require the first ring-0 mutex
419	* discussed in @ref subsec_pgmPhys_Serializing. We
420	* some double house keeping wrt to who has mapped what I think, since both
421	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
422	*
423	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
424	* require anyone that desires to do changes to the mapping cache to do that
425	* from within this critsect. Alternatively, we could employ a separate critsect
426	* for serializing changes to the mapping cache as this would reduce potential
427	* contention with other threads accessing mappings unrelated to the changes
428	* that are in process. We can see about this later, contention will show
429	* up in the statistics anyway, so it'll be simple to tell.
430	*
431	* The organization of the ring-3 part will be very much like how the allocation
432	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
433	* having to walk the tree all the time, we'll have a couple of lookaside entries
434	* like in we do for I/O ports and MMIO in IOM.
435	*
436	* The simplified flow of a PGMPhysRead/Write function:
437	* -# Enter the PGM critsect.
438	* -# Lookup GCPhys in the ram ranges and get the Page ID.
439	* -# Calc the Allocation Chunk ID from the Page ID.
440	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
441	* If not found in cache:
442	* -# Call ring-0 and request it to be mapped and supply
443	* a chunk to be unmapped if the cache is maxed out already.
444	* -# Insert the new mapping into the AVL tree (id + R3 address).
445	* -# Update the relevant lookaside entry and return the mapping address.
446	* -# Do the read/write according to monitoring flags and everything.
447	* -# Leave the critsect.
448	*
449	*
450	* @section sec_pgmPhys_Fallback Fallback
451	*
452	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
453	* API and thus require a fallback.
454	*
455	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
456	* will return to the ring-3 caller (and later ring-0) and asking it to seed
457	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
458	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
459	* "SeededAllocPages" call to ring-0.
460	*
461	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
462	* all page sharing (zero page detection will continue). It will also force
463	* all allocations to come from the VM which seeded the page. Both these
464	* measures are taken to make sure that there will never be any need for
465	* mapping anything into ring-3 - everything will be mapped already.
466	*
467	* Whether we'll continue to use the current MM locked memory management
468	* for this I don't quite know (I'd prefer not to and just ditch that all
469	* togther), we'll see what's simplest to do.
470	*
471	*
472	*
473	* @section sec_pgmPhys_Changes Changes
474	*
475	* Breakdown of the changes involved?
476	*/
477
478
479	/** Saved state data unit version. */
480	#define PGM_SAVED_STATE_VERSION 5
481
482	/*******************************************************************************
483	* Header Files *
484	*******************************************************************************/
485	#define LOG_GROUP LOG_GROUP_PGM
486	#include <VBox/dbgf.h>
487	#include <VBox/pgm.h>
488	#include <VBox/cpum.h>
489	#include <VBox/iom.h>
490	#include <VBox/sup.h>
491	#include <VBox/mm.h>
492	#include <VBox/em.h>
493	#include <VBox/stam.h>
494	#include <VBox/rem.h>
495	#include <VBox/dbgf.h>
496	#include <VBox/rem.h>
497	#include <VBox/selm.h>
498	#include <VBox/ssm.h>
499	#include "PGMInternal.h"
500	#include <VBox/vm.h>
501	#include <VBox/dbg.h>
502	#include <VBox/hwaccm.h>
503
504	#include <iprt/assert.h>
505	#include <iprt/alloc.h>
506	#include <iprt/asm.h>
507	#include <iprt/thread.h>
508	#include <iprt/string.h>
509	#include <VBox/param.h>
510	#include <VBox/err.h>
511
512
513
514	/*******************************************************************************
515	* Internal Functions *
516	*******************************************************************************/
517	static int pgmR3InitPaging(PVM pVM);
518	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
519	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
520	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
521	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
522	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
523	#ifdef VBOX_STRICT
524	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
525	#endif
526	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
527	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
528	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
529	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
530	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
531
532	#ifdef VBOX_WITH_STATISTICS
533	static void pgmR3InitStats(PVM pVM);
534	#endif
535
536	#ifdef VBOX_WITH_DEBUGGER
537	/** @todo all but the two last commands must be converted to 'info'. */
538	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
539	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
540	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
541	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
542	#endif
543
544
545	/*******************************************************************************
546	* Global Variables *
547	*******************************************************************************/
548	#ifdef VBOX_WITH_DEBUGGER
549	/** Command descriptors. */
550	static const DBGCCMD g_aCmds[] =
551	{
552	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
553	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
554	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
555	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
556	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
557	};
558	#endif
559
560
561
562
563	#if 1/// @todo ndef RT_ARCH_AMD64
564	/*
565	* Shadow - 32-bit mode
566	*/
567	#define PGM_SHW_TYPE PGM_TYPE_32BIT
568	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
569	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
570	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
571	#include "PGMShw.h"
572
573	/* Guest - real mode */
574	#define PGM_GST_TYPE PGM_TYPE_REAL
575	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
576	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
577	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
578	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
579	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
580	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
581	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
582	#include "PGMGst.h"
583	#include "PGMBth.h"
584	#undef BTH_PGMPOOLKIND_PT_FOR_PT
585	#undef PGM_BTH_NAME
586	#undef PGM_BTH_NAME_GC_STR
587	#undef PGM_BTH_NAME_R0_STR
588	#undef PGM_GST_TYPE
589	#undef PGM_GST_NAME
590	#undef PGM_GST_NAME_GC_STR
591	#undef PGM_GST_NAME_R0_STR
592
593	/* Guest - protected mode */
594	#define PGM_GST_TYPE PGM_TYPE_PROT
595	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
596	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
597	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
598	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
599	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
600	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
601	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
602	#include "PGMGst.h"
603	#include "PGMBth.h"
604	#undef BTH_PGMPOOLKIND_PT_FOR_PT
605	#undef PGM_BTH_NAME
606	#undef PGM_BTH_NAME_GC_STR
607	#undef PGM_BTH_NAME_R0_STR
608	#undef PGM_GST_TYPE
609	#undef PGM_GST_NAME
610	#undef PGM_GST_NAME_GC_STR
611	#undef PGM_GST_NAME_R0_STR
612
613	/* Guest - 32-bit mode */
614	#define PGM_GST_TYPE PGM_TYPE_32BIT
615	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
616	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
617	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
618	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
619	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
620	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
621	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
622	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
623	#include "PGMGst.h"
624	#include "PGMBth.h"
625	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
626	#undef BTH_PGMPOOLKIND_PT_FOR_PT
627	#undef PGM_BTH_NAME
628	#undef PGM_BTH_NAME_GC_STR
629	#undef PGM_BTH_NAME_R0_STR
630	#undef PGM_GST_TYPE
631	#undef PGM_GST_NAME
632	#undef PGM_GST_NAME_GC_STR
633	#undef PGM_GST_NAME_R0_STR
634
635	#undef PGM_SHW_TYPE
636	#undef PGM_SHW_NAME
637	#undef PGM_SHW_NAME_GC_STR
638	#undef PGM_SHW_NAME_R0_STR
639	#endif /* !RT_ARCH_AMD64 */
640
641
642	/*
643	* Shadow - PAE mode
644	*/
645	#define PGM_SHW_TYPE PGM_TYPE_PAE
646	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
647	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
648	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
649	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
650	#include "PGMShw.h"
651
652	/* Guest - real mode */
653	#define PGM_GST_TYPE PGM_TYPE_REAL
654	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
655	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
656	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
657	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
658	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
659	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
660	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
661	#include "PGMBth.h"
662	#undef BTH_PGMPOOLKIND_PT_FOR_PT
663	#undef PGM_BTH_NAME
664	#undef PGM_BTH_NAME_GC_STR
665	#undef PGM_BTH_NAME_R0_STR
666	#undef PGM_GST_TYPE
667	#undef PGM_GST_NAME
668	#undef PGM_GST_NAME_GC_STR
669	#undef PGM_GST_NAME_R0_STR
670
671	/* Guest - protected mode */
672	#define PGM_GST_TYPE PGM_TYPE_PROT
673	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
674	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
675	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
676	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
677	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
678	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
679	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
680	#include "PGMBth.h"
681	#undef BTH_PGMPOOLKIND_PT_FOR_PT
682	#undef PGM_BTH_NAME
683	#undef PGM_BTH_NAME_GC_STR
684	#undef PGM_BTH_NAME_R0_STR
685	#undef PGM_GST_TYPE
686	#undef PGM_GST_NAME
687	#undef PGM_GST_NAME_GC_STR
688	#undef PGM_GST_NAME_R0_STR
689
690	/* Guest - 32-bit mode */
691	#define PGM_GST_TYPE PGM_TYPE_32BIT
692	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
693	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
694	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
695	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
696	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
697	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
698	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
699	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
700	#include "PGMBth.h"
701	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
702	#undef BTH_PGMPOOLKIND_PT_FOR_PT
703	#undef PGM_BTH_NAME
704	#undef PGM_BTH_NAME_GC_STR
705	#undef PGM_BTH_NAME_R0_STR
706	#undef PGM_GST_TYPE
707	#undef PGM_GST_NAME
708	#undef PGM_GST_NAME_GC_STR
709	#undef PGM_GST_NAME_R0_STR
710
711	/* Guest - PAE mode */
712	#define PGM_GST_TYPE PGM_TYPE_PAE
713	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
714	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
715	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
716	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
717	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
718	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
719	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
720	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
721	#include "PGMGst.h"
722	#include "PGMBth.h"
723	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
724	#undef BTH_PGMPOOLKIND_PT_FOR_PT
725	#undef PGM_BTH_NAME
726	#undef PGM_BTH_NAME_GC_STR
727	#undef PGM_BTH_NAME_R0_STR
728	#undef PGM_GST_TYPE
729	#undef PGM_GST_NAME
730	#undef PGM_GST_NAME_GC_STR
731	#undef PGM_GST_NAME_R0_STR
732
733	#undef PGM_SHW_TYPE
734	#undef PGM_SHW_NAME
735	#undef PGM_SHW_NAME_GC_STR
736	#undef PGM_SHW_NAME_R0_STR
737
738
739	/*
740	* Shadow - AMD64 mode
741	*/
742	#define PGM_SHW_TYPE PGM_TYPE_AMD64
743	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
744	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
745	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
746	#include "PGMShw.h"
747
748	/* Guest - real mode */
749	#define PGM_GST_TYPE PGM_TYPE_REAL
750	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
751	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
752	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
753	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
754	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_REAL_STR(name)
755	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_REAL_STR(name)
756	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
757	#include "PGMBth.h"
758	#undef BTH_PGMPOOLKIND_PT_FOR_PT
759	#undef PGM_BTH_NAME
760	#undef PGM_BTH_NAME_GC_STR
761	#undef PGM_BTH_NAME_R0_STR
762	#undef PGM_GST_TYPE
763	#undef PGM_GST_NAME
764	#undef PGM_GST_NAME_GC_STR
765	#undef PGM_GST_NAME_R0_STR
766
767	/* Guest - protected mode */
768	#define PGM_GST_TYPE PGM_TYPE_PROT
769	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
770	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
771	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
772	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
773	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_PROT_STR(name)
774	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_PROT_STR(name)
775	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
776	#include "PGMBth.h"
777	#undef BTH_PGMPOOLKIND_PT_FOR_PT
778	#undef PGM_BTH_NAME
779	#undef PGM_BTH_NAME_GC_STR
780	#undef PGM_BTH_NAME_R0_STR
781	#undef PGM_GST_TYPE
782	#undef PGM_GST_NAME
783	#undef PGM_GST_NAME_GC_STR
784	#undef PGM_GST_NAME_R0_STR
785
786	/* Guest - AMD64 mode */
787	#define PGM_GST_TYPE PGM_TYPE_AMD64
788	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
789	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
790	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
791	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
792	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
793	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
794	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
795	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
796	#include "PGMGst.h"
797	#include "PGMBth.h"
798	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
799	#undef BTH_PGMPOOLKIND_PT_FOR_PT
800	#undef PGM_BTH_NAME
801	#undef PGM_BTH_NAME_GC_STR
802	#undef PGM_BTH_NAME_R0_STR
803	#undef PGM_GST_TYPE
804	#undef PGM_GST_NAME
805	#undef PGM_GST_NAME_GC_STR
806	#undef PGM_GST_NAME_R0_STR
807
808	#undef PGM_SHW_TYPE
809	#undef PGM_SHW_NAME
810	#undef PGM_SHW_NAME_GC_STR
811	#undef PGM_SHW_NAME_R0_STR
812
813
814	/**
815	* Initiates the paging of VM.
816	*
817	* @returns VBox status code.
818	* @param pVM Pointer to VM structure.
819	*/
820	PGMR3DECL(int) PGMR3Init(PVM pVM)
821	{
822	LogFlow(("PGMR3Init:\n"));
823
824	/*
825	* Assert alignment and sizes.
826	*/
827	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
828
829	/*
830	* Init the structure.
831	*/
832	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
833	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
834	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
835	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
836	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
837	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
838	pVM->pgm.s.fA20Enabled = true;
839	pVM->pgm.s.pGstPaePDPTRHC = NULL;
840	pVM->pgm.s.pGstPaePDPTRGC = 0;
841	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
842	{
843	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
844	pVM->pgm.s.apGstPaePDsGC[i] = 0;
845	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
846	}
847
848	#ifdef VBOX_STRICT
849	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
850	#endif
851
852	/*
853	* Get the configured RAM size - to estimate saved state size.
854	*/
855	uint64_t cbRam;
856	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
857	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
858	cbRam = pVM->pgm.s.cbRamSize = 0;
859	else if (VBOX_SUCCESS(rc))
860	{
861	if (cbRam < PAGE_SIZE)
862	cbRam = 0;
863	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
864	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
865	}
866	else
867	{
868	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
869	return rc;
870	}
871
872	/*
873	* Register saved state data unit.
874	*/
875	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
876	NULL, pgmR3Save, NULL,
877	NULL, pgmR3Load, NULL);
878	if (VBOX_FAILURE(rc))
879	return rc;
880
881	/*
882	* Initialize the PGM critical section and flush the phys TLBs
883	*/
884	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
885	AssertRCReturn(rc, rc);
886
887	PGMR3PhysChunkInvalidateTLB(pVM);
888	PGMPhysInvalidatePageR3MapTLB(pVM);
889	PGMPhysInvalidatePageR0MapTLB(pVM);
890	PGMPhysInvalidatePageGCMapTLB(pVM);
891
892	/*
893	* Trees
894	*/
895	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
896	if (VBOX_SUCCESS(rc))
897	{
898	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
899
900	/*
901	* Alocate the zero page.
902	*/
903	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
904	}
905	if (VBOX_SUCCESS(rc))
906	{
907	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToGC(pVM, pVM->pgm.s.pvZeroPgR3);
908	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
909	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
910	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
911	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
912
913	/*
914	* Init the paging.
915	*/
916	rc = pgmR3InitPaging(pVM);
917	}
918	if (VBOX_SUCCESS(rc))
919	{
920	/*
921	* Init the page pool.
922	*/
923	rc = pgmR3PoolInit(pVM);
924	}
925	if (VBOX_SUCCESS(rc))
926	{
927	/*
928	* Info & statistics
929	*/
930	DBGFR3InfoRegisterInternal(pVM, "mode",
931	"Shows the current paging mode. "
932	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
933	pgmR3InfoMode);
934	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
935	"Dumps all the entries in the top level paging table. No arguments.",
936	pgmR3InfoCr3);
937	DBGFR3InfoRegisterInternal(pVM, "phys",
938	"Dumps all the physical address ranges. No arguments.",
939	pgmR3PhysInfo);
940	DBGFR3InfoRegisterInternal(pVM, "handlers",
941	"Dumps physical and virtual handlers. "
942	"Pass 'phys' or 'virt' as argument if only one kind is wanted.",
943	pgmR3InfoHandlers);
944
945	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
946	#ifdef VBOX_WITH_STATISTICS
947	pgmR3InitStats(pVM);
948	#endif
949	#ifdef VBOX_WITH_DEBUGGER
950	/*
951	* Debugger commands.
952	*/
953	static bool fRegisteredCmds = false;
954	if (!fRegisteredCmds)
955	{
956	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
957	if (VBOX_SUCCESS(rc))
958	fRegisteredCmds = true;
959	}
960	#endif
961	return VINF_SUCCESS;
962	}
963
964	/* Almost no cleanup necessary, MM frees all memory. */
965	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
966
967	return rc;
968	}
969
970
971	/**
972	* Init paging.
973	*
974	* Since we need to check what mode the host is operating in before we can choose
975	* the right paging functions for the host we have to delay this until R0 has
976	* been initialized.
977	*
978	* @returns VBox status code.
979	* @param pVM VM handle.
980	*/
981	static int pgmR3InitPaging(PVM pVM)
982	{
983	/*
984	* Force a recalculation of modes and switcher so everyone gets notified.
985	*/
986	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
987	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
988	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
989
990	/*
991	* Allocate static mapping space for whatever the cr3 register
992	* points to and in the case of PAE mode to the 4 PDs.
993	*/
994	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
995	if (VBOX_FAILURE(rc))
996	{
997	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
998	return rc;
999	}
1000	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1001
1002	/*
1003	* Allocate pages for the three possible intermediate contexts
1004	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1005	* for the sake of simplicity. The AMD64 uses the PAE for the
1006	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1007	*
1008	* We assume that two page tables will be enought for the core code
1009	* mappings (HC virtual and identity).
1010	*/
1011	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1012	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1013	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1014	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1015	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1016	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1017	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1018	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1019	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1020	pVM->pgm.s.pInterPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
1021	pVM->pgm.s.pInterPaePDPTR64 = (PX86PDPTR)MMR3PageAllocLow(pVM);
1022	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1023	if ( !pVM->pgm.s.pInterPD
1024	\|\| !pVM->pgm.s.apInterPTs[0]
1025	\|\| !pVM->pgm.s.apInterPTs[1]
1026	\|\| !pVM->pgm.s.apInterPaePTs[0]
1027	\|\| !pVM->pgm.s.apInterPaePTs[1]
1028	\|\| !pVM->pgm.s.apInterPaePDs[0]
1029	\|\| !pVM->pgm.s.apInterPaePDs[1]
1030	\|\| !pVM->pgm.s.apInterPaePDs[2]
1031	\|\| !pVM->pgm.s.apInterPaePDs[3]
1032	\|\| !pVM->pgm.s.pInterPaePDPTR
1033	\|\| !pVM->pgm.s.pInterPaePDPTR64
1034	\|\| !pVM->pgm.s.pInterPaePML4)
1035	{
1036	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1037	return VERR_NO_PAGE_MEMORY;
1038	}
1039
1040	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1041	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1042	pVM->pgm.s.HCPhysInterPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR);
1043	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPTR != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPTR & PAGE_OFFSET_MASK));
1044	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1045	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1046
1047	/*
1048	* Initialize the pages, setting up the PML4 and PDPTR for repetitive 4GB action.
1049	*/
1050	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1051	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1052	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1053
1054	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1055	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1056
1057	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPTR);
1058	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1059	{
1060	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1061	pVM->pgm.s.pInterPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1062	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1063	}
1064
1065	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPTR64->a); i++)
1066	{
1067	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
1068	pVM->pgm.s.pInterPaePDPTR64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1069	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1070	}
1071
1072	RTHCPHYS HCPhysInterPaePDPTR64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64);
1073	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1074	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1075	\| HCPhysInterPaePDPTR64;
1076
1077	/*
1078	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1079	* We allocate pages for all three posibilities to in order to simplify mappings and
1080	* avoid resource failure during mode switches. So, we need to cover all levels of the
1081	* of the first 4GB down to PD level.
1082	* As with the intermediate context, AMD64 uses the PAE PDPTR and PDs.
1083	*/
1084	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1085	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1086	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1087	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1088	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1089	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1090	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1091	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1092	pVM->pgm.s.pHCPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
1093	pVM->pgm.s.pHCPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1094	if ( !pVM->pgm.s.pHC32BitPD
1095	\|\| !pVM->pgm.s.apHCPaePDs[0]
1096	\|\| !pVM->pgm.s.apHCPaePDs[1]
1097	\|\| !pVM->pgm.s.apHCPaePDs[2]
1098	\|\| !pVM->pgm.s.apHCPaePDs[3]
1099	\|\| !pVM->pgm.s.pHCPaePDPTR
1100	\|\| !pVM->pgm.s.pHCPaePML4)
1101	{
1102	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1103	return VERR_NO_PAGE_MEMORY;
1104	}
1105
1106	/* get physical addresses. */
1107	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1108	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1109	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1110	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1111	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1112	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1113	pVM->pgm.s.HCPhysPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPTR);
1114	pVM->pgm.s.HCPhysPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePML4);
1115
1116	/*
1117	* Initialize the pages, setting up the PML4 and PDPTR for action below 4GB.
1118	*/
1119	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1120
1121	ASMMemZero32(pVM->pgm.s.pHCPaePDPTR, PAGE_SIZE);
1122	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1123	{
1124	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1125	pVM->pgm.s.pHCPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1126	/* The flags will be corrected when entering and leaving long mode. */
1127	}
1128
1129	ASMMemZero32(pVM->pgm.s.pHCPaePML4, PAGE_SIZE);
1130	pVM->pgm.s.pHCPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_A
1131	\| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.HCPhysPaePDPTR;
1132
1133	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1134
1135	/*
1136	* Initialize paging workers and mode from current host mode
1137	* and the guest running in real mode.
1138	*/
1139	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1140	switch (pVM->pgm.s.enmHostMode)
1141	{
1142	case SUPPAGINGMODE_32_BIT:
1143	case SUPPAGINGMODE_32_BIT_GLOBAL:
1144	case SUPPAGINGMODE_PAE:
1145	case SUPPAGINGMODE_PAE_GLOBAL:
1146	case SUPPAGINGMODE_PAE_NX:
1147	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1148	break;
1149
1150	case SUPPAGINGMODE_AMD64:
1151	case SUPPAGINGMODE_AMD64_GLOBAL:
1152	case SUPPAGINGMODE_AMD64_NX:
1153	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1154	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1155	if (ARCH_BITS != 64)
1156	{
1157	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1158	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1159	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1160	}
1161	#endif
1162	break;
1163	default:
1164	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1165	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1166	}
1167	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1168	if (VBOX_SUCCESS(rc))
1169	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1170	if (VBOX_SUCCESS(rc))
1171	{
1172	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1173	#if HC_ARCH_BITS == 64
1174	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPTR=%VHp HCPhysPaePML4=%VHp\n",
1175	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1176	pVM->pgm.s.HCPhysPaePDPTR, pVM->pgm.s.HCPhysPaePML4));
1177	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPTR=%VHp HCPhysInterPaePML4=%VHp\n",
1178	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPTR, pVM->pgm.s.HCPhysInterPaePML4));
1179	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPTR64=%VHp\n",
1180	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1181	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1182	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1183	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64)));
1184	#endif
1185
1186	return VINF_SUCCESS;
1187	}
1188
1189	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1190	return rc;
1191	}
1192
1193
1194	#ifdef VBOX_WITH_STATISTICS
1195	/**
1196	* Init statistics
1197	*/
1198	static void pgmR3InitStats(PVM pVM)
1199	{
1200	PPGM pPGM = &pVM->pgm.s;
1201	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1202	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
1203	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
1204	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
1205	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1206	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
1207	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
1208	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1209	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1210	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
1211	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1212	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1213	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1214	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1215	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1216	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1217	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1218	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1219	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1220	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
1221	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
1222	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
1223
1224	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
1225	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1226	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1227	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1228	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1229	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1230	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
1231	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1232	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1233	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1234	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1235	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1236	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1237	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1238	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1239	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1240	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1241	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1242	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1243
1244	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1245	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1246	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1247	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1248	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1249	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1250	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1251
1252	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1253	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1254	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1255	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1256	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1257	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1258
1259	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1260	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1261	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1262	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1263	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
1264	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
1265
1266
1267	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1268	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1269	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1270
1271	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1272	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1273
1274	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1275	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1276
1277	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1278	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1279
1280	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1281	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1282	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1283
1284	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
1285	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
1286	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
1287	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
1288	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1289	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
1290	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
1291	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1292	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1293	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1294	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1295
1296	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1297	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1298	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1299	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1300	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1301	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1302	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1303
1304	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1305	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1306	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1307	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1308
1309	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1310	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1311	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1312	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1313	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1314
1315	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1316	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1317	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1318	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1319	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1320	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1321	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1322	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1323	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1324	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1325	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1326	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1327
1328	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1329	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1330	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1331	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1332	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1333	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1334	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1335	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1336	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1337	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1338	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1339	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1340
1341	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
1342	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
1343	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
1344
1345	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1346	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1347
1348	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1349	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1350	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1351	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1352
1353	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1354	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1355
1356	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1357	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1358	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1359	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1360	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1361	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1362	STAM_REG(pVM, &pPGM->StatPageReplaceShared, STAMTYPE_COUNTER, "/PGM/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1363	STAM_REG(pVM, &pPGM->StatPageReplaceZero, STAMTYPE_COUNTER, "/PGM/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1364	STAM_REG(pVM, &pPGM->StatPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1365	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1366	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1367	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1368	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1369
1370	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1371	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1372	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1373	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1374	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1375	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1376	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1377	#endif
1378
1379	for (unsigned i = 0; i < PAGE_ENTRIES; i++)
1380	{
1381	/** @todo r=bird: We need a STAMR3RegisterF()! */
1382	char szName[32];
1383
1384	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1385	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1386	AssertRC(rc);
1387
1388	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1389	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1390	AssertRC(rc);
1391
1392	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1393	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1394	AssertRC(rc);
1395	}
1396	}
1397	#endif /* VBOX_WITH_STATISTICS */
1398
1399	/**
1400	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1401	*
1402	* The dynamic mapping area will also be allocated and initialized at this
1403	* time. We could allocate it during PGMR3Init of course, but the mapping
1404	* wouldn't be allocated at that time preventing us from setting up the
1405	* page table entries with the dummy page.
1406	*
1407	* @returns VBox status code.
1408	* @param pVM VM handle.
1409	*/
1410	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1411	{
1412	/*
1413	* Reserve space for mapping the paging pages into guest context.
1414	*/
1415	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &pVM->pgm.s.pGC32BitPD);
1416	AssertRCReturn(rc, rc);
1417	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1418
1419	/*
1420	* Reserve space for the dynamic mappings.
1421	*/
1422	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1423	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &pVM->pgm.s.pbDynPageMapBaseGC);
1424	if ( VBOX_SUCCESS(rc)
1425	&& (pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT))
1426	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &pVM->pgm.s.pbDynPageMapBaseGC);
1427	if (VBOX_SUCCESS(rc))
1428	{
1429	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT));
1430	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1431	}
1432	return rc;
1433	}
1434
1435
1436	/**
1437	* Ring-3 init finalizing.
1438	*
1439	* @returns VBox status code.
1440	* @param pVM The VM handle.
1441	*/
1442	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1443	{
1444	/*
1445	* Map the paging pages into the guest context.
1446	*/
1447	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1448	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1449
1450	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1451	AssertRCReturn(rc, rc);
1452	pVM->pgm.s.pGC32BitPD = GCPtr;
1453	GCPtr += PAGE_SIZE;
1454	GCPtr += PAGE_SIZE; /* reserved page */
1455
1456	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1457	{
1458	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1459	AssertRCReturn(rc, rc);
1460	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1461	GCPtr += PAGE_SIZE;
1462	}
1463	/* A bit of paranoia is justified. */
1464	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1465	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1466	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1467	GCPtr += PAGE_SIZE; /* reserved page */
1468
1469	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPTR, PAGE_SIZE, 0);
1470	AssertRCReturn(rc, rc);
1471	pVM->pgm.s.pGCPaePDPTR = GCPtr;
1472	GCPtr += PAGE_SIZE;
1473	GCPtr += PAGE_SIZE; /* reserved page */
1474
1475	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePML4, PAGE_SIZE, 0);
1476	AssertRCReturn(rc, rc);
1477	pVM->pgm.s.pGCPaePML4 = GCPtr;
1478	GCPtr += PAGE_SIZE;
1479	GCPtr += PAGE_SIZE; /* reserved page */
1480
1481
1482	/*
1483	* Reserve space for the dynamic mappings.
1484	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1485	*/
1486	/* get the pointer to the page table entries. */
1487	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1488	AssertRelease(pMapping);
1489	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1490	const unsigned iPT = off >> X86_PD_SHIFT;
1491	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1492	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1493	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1494
1495	/* init cache */
1496	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1497	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1498	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1499
1500	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1501	{
1502	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1503	AssertRCReturn(rc, rc);
1504	}
1505
1506	return rc;
1507	}
1508
1509
1510	/**
1511	* Applies relocations to data and code managed by this
1512	* component. This function will be called at init and
1513	* whenever the VMM need to relocate it self inside the GC.
1514	*
1515	* @param pVM The VM.
1516	* @param offDelta Relocation delta relative to old location.
1517	*/
1518	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1519	{
1520	LogFlow(("PGMR3Relocate\n"));
1521
1522	/*
1523	* Paging stuff.
1524	*/
1525	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1526	/** @todo move this into shadow and guest specific relocation functions. */
1527	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1528	pVM->pgm.s.pGC32BitPD += offDelta;
1529	pVM->pgm.s.pGuestPDGC += offDelta;
1530	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1531	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1532	pVM->pgm.s.pGCPaePDPTR += offDelta;
1533	pVM->pgm.s.pGCPaePML4 += offDelta;
1534
1535	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1536	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1537
1538	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1539	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1540	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1541
1542	/*
1543	* Trees.
1544	*/
1545	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1546
1547	/*
1548	* Ram ranges.
1549	*/
1550	if (pVM->pgm.s.pRamRangesHC)
1551	{
1552	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesHC);
1553	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur->pNextHC; pCur = pCur->pNextHC)
1554	{
1555	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1556	if (pCur->pavHCChunkGC)
1557	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1558	}
1559	}
1560
1561	/*
1562	* Update the two page directories with all page table mappings.
1563	* (One or more of them have changed, that's why we're here.)
1564	*/
1565	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1566	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1567	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1568
1569	/* Relocate GC addresses of Page Tables. */
1570	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1571	{
1572	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1573	{
1574	pCur->aPTs[i].pPTGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].pPTR3);
1575	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].paPaePTsR3);
1576	}
1577	}
1578
1579	/*
1580	* Dynamic page mapping area.
1581	*/
1582	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1583	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1584	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1585
1586	/*
1587	* The Zero page.
1588	*/
1589	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1590	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1591
1592	/*
1593	* Physical and virtual handlers.
1594	*/
1595	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1596	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1597
1598	/*
1599	* The page pool.
1600	*/
1601	pgmR3PoolRelocate(pVM);
1602	}
1603
1604
1605	/**
1606	* Callback function for relocating a physical access handler.
1607	*
1608	* @returns 0 (continue enum)
1609	* @param pNode Pointer to a PGMPHYSHANDLER node.
1610	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1611	* not certain the delta will fit in a void pointer for all possible configs.
1612	*/
1613	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1614	{
1615	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1616	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1617	if (pHandler->pfnHandlerGC)
1618	pHandler->pfnHandlerGC += offDelta;
1619	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1620	pHandler->pvUserGC += offDelta;
1621	return 0;
1622	}
1623
1624
1625	/**
1626	* Callback function for relocating a virtual access handler.
1627	*
1628	* @returns 0 (continue enum)
1629	* @param pNode Pointer to a PGMVIRTHANDLER node.
1630	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1631	* not certain the delta will fit in a void pointer for all possible configs.
1632	*/
1633	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1634	{
1635	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1636	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1637	Assert(pHandler->pfnHandlerGC);
1638	pHandler->pfnHandlerGC += offDelta;
1639	return 0;
1640	}
1641
1642
1643	/**
1644	* The VM is being reset.
1645	*
1646	* For the PGM component this means that any PD write monitors
1647	* needs to be removed.
1648	*
1649	* @param pVM VM handle.
1650	*/
1651	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1652	{
1653	LogFlow(("PGMR3Reset:\n"));
1654	VM_ASSERT_EMT(pVM);
1655
1656	/*
1657	* Unfix any fixed mappings and disable CR3 monitoring.
1658	*/
1659	pVM->pgm.s.fMappingsFixed = false;
1660	pVM->pgm.s.GCPtrMappingFixed = 0;
1661	pVM->pgm.s.cbMappingFixed = 0;
1662
1663	int rc = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
1664	AssertRC(rc);
1665	#ifdef DEBUG
1666	PGMR3DumpMappings(pVM);
1667	#endif
1668
1669	/*
1670	* Reset the shadow page pool.
1671	*/
1672	pgmR3PoolReset(pVM);
1673
1674	/*
1675	* Re-init other members.
1676	*/
1677	pVM->pgm.s.fA20Enabled = true;
1678
1679	/*
1680	* Clear the FFs PGM owns.
1681	*/
1682	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1683	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1684
1685	/*
1686	* Zero memory.
1687	*/
1688	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
1689	{
1690	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1691	while (iPage-- > 0)
1692	{
1693	if (pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2)) /** @todo PAGE FLAGS */
1694	{
1695	/* shadow ram is reloaded elsewhere. */
1696	Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO))); /** @todo PAGE FLAGS */
1697	continue;
1698	}
1699	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1700	{
1701	unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1702	if (pRam->pavHCChunkHC[iChunk])
1703	ASMMemZero32((char *)pRam->pavHCChunkHC[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
1704	}
1705	else
1706	ASMMemZero32((char *)pRam->pvHC + (iPage << PAGE_SHIFT), PAGE_SIZE);
1707	}
1708	}
1709
1710	/*
1711	* Switch mode back to real mode.
1712	*/
1713	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1714	AssertReleaseRC(rc);
1715	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1716	}
1717
1718
1719	/**
1720	* Terminates the PGM.
1721	*
1722	* @returns VBox status code.
1723	* @param pVM Pointer to VM structure.
1724	*/
1725	PGMR3DECL(int) PGMR3Term(PVM pVM)
1726	{
1727	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1728	}
1729
1730
1731	#ifdef VBOX_STRICT
1732	/**
1733	* VM state change callback for clearing fNoMorePhysWrites after
1734	* a snapshot has been created.
1735	*/
1736	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
1737	{
1738	if (enmState == VMSTATE_RUNNING)
1739	pVM->pgm.s.fNoMorePhysWrites = false;
1740	}
1741	#endif
1742
1743
1744	/**
1745	* Execute state save operation.
1746	*
1747	* @returns VBox status code.
1748	* @param pVM VM Handle.
1749	* @param pSSM SSM operation handle.
1750	*/
1751	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1752	{
1753	PPGM pPGM = &pVM->pgm.s;
1754
1755	/* No more writes to physical memory after this point! */
1756	pVM->pgm.s.fNoMorePhysWrites = true;
1757
1758	/*
1759	* Save basic data (required / unaffected by relocation).
1760	*/
1761	#if 1
1762	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1763	#else
1764	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1765	#endif
1766	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1767	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1768	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1769	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1770	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1771	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1772	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1773	SSMR3PutU32(pSSM, ~0); /* Separator. */
1774
1775	/*
1776	* The guest mappings.
1777	*/
1778	uint32_t i = 0;
1779	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1780	{
1781	SSMR3PutU32(pSSM, i);
1782	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1783	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1784	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1785	/* flags are done by the mapping owners! */
1786	}
1787	SSMR3PutU32(pSSM, ~0); /* terminator. */
1788
1789	/*
1790	* Ram range flags and bits.
1791	*/
1792	i = 0;
1793	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1794	{
1795	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1796
1797	SSMR3PutU32(pSSM, i);
1798	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1799	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1800	SSMR3PutGCPhys(pSSM, pRam->cb);
1801	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
1802
1803	/* Flags. */
1804	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1805	for (unsigned iPage = 0; iPage < cPages; iPage++)
1806	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
1807
1808	/* any memory associated with the range. */
1809	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1810	{
1811	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1812	{
1813	if (pRam->pavHCChunkHC[iChunk])
1814	{
1815	SSMR3PutU8(pSSM, 1); /* chunk present */
1816	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1817	}
1818	else
1819	SSMR3PutU8(pSSM, 0); /* no chunk present */
1820	}
1821	}
1822	else if (pRam->pvHC)
1823	{
1824	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
1825	if (VBOX_FAILURE(rc))
1826	{
1827	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1828	return rc;
1829	}
1830	}
1831	}
1832	return SSMR3PutU32(pSSM, ~0); /* terminator. */
1833	}
1834
1835
1836	/**
1837	* Execute state load operation.
1838	*
1839	* @returns VBox status code.
1840	* @param pVM VM Handle.
1841	* @param pSSM SSM operation handle.
1842	* @param u32Version Data layout version.
1843	*/
1844	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1845	{
1846	/*
1847	* Validate version.
1848	*/
1849	if (u32Version != PGM_SAVED_STATE_VERSION)
1850	{
1851	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
1852	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1853	}
1854
1855	/*
1856	* Call the reset function to make sure all the memory is cleared.
1857	*/
1858	PGMR3Reset(pVM);
1859
1860	/*
1861	* Load basic data (required / unaffected by relocation).
1862	*/
1863	PPGM pPGM = &pVM->pgm.s;
1864	#if 1
1865	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
1866	#else
1867	uint32_t u;
1868	SSMR3GetU32(pSSM, &u);
1869	pPGM->fMappingsFixed = u;
1870	#endif
1871	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
1872	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
1873
1874	RTUINT cbRamSize;
1875	int rc = SSMR3GetU32(pSSM, &cbRamSize);
1876	if (VBOX_FAILURE(rc))
1877	return rc;
1878	if (cbRamSize != pPGM->cbRamSize)
1879	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
1880	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
1881	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
1882	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
1883	RTUINT uGuestMode;
1884	SSMR3GetUInt(pSSM, &uGuestMode);
1885	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
1886
1887	/* check separator. */
1888	uint32_t u32Sep;
1889	SSMR3GetU32(pSSM, &u32Sep);
1890	if (VBOX_FAILURE(rc))
1891	return rc;
1892	if (u32Sep != (uint32_t)~0)
1893	{
1894	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1895	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1896	}
1897
1898	/*
1899	* The guest mappings.
1900	*/
1901	uint32_t i = 0;
1902	for (;; i++)
1903	{
1904	/* Check the seqence number / separator. */
1905	rc = SSMR3GetU32(pSSM, &u32Sep);
1906	if (VBOX_FAILURE(rc))
1907	return rc;
1908	if (u32Sep == ~0U)
1909	break;
1910	if (u32Sep != i)
1911	{
1912	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1913	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1914	}
1915
1916	/* get the mapping details. */
1917	char szDesc[256];
1918	szDesc[0] = '\0';
1919	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
1920	if (VBOX_FAILURE(rc))
1921	return rc;
1922	RTGCPTR GCPtr;
1923	SSMR3GetGCPtr(pSSM, &GCPtr);
1924	RTGCUINTPTR cPTs;
1925	rc = SSMR3GetU32(pSSM, &cPTs);
1926	if (VBOX_FAILURE(rc))
1927	return rc;
1928
1929	/* find matching range. */
1930	PPGMMAPPING pMapping;
1931	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
1932	if ( pMapping->cPTs == cPTs
1933	&& !strcmp(pMapping->pszDesc, szDesc))
1934	break;
1935	if (!pMapping)
1936	{
1937	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
1938	cPTs, szDesc, GCPtr));
1939	AssertFailed();
1940	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1941	}
1942
1943	/* relocate it. */
1944	if (pMapping->GCPtr != GCPtr)
1945	{
1946	AssertMsg((GCPtr >> PGDIR_SHIFT << PGDIR_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
1947	#if HC_ARCH_BITS == 64
1948	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
1949	#endif
1950	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr >> PGDIR_SHIFT, GCPtr >> PGDIR_SHIFT);
1951	}
1952	else
1953	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
1954	}
1955
1956	/*
1957	* Ram range flags and bits.
1958	*/
1959	i = 0;
1960	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1961	{
1962	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1963	/* Check the seqence number / separator. */
1964	rc = SSMR3GetU32(pSSM, &u32Sep);
1965	if (VBOX_FAILURE(rc))
1966	return rc;
1967	if (u32Sep == ~0U)
1968	break;
1969	if (u32Sep != i)
1970	{
1971	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1972	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1973	}
1974
1975	/* Get the range details. */
1976	RTGCPHYS GCPhys;
1977	SSMR3GetGCPhys(pSSM, &GCPhys);
1978	RTGCPHYS GCPhysLast;
1979	SSMR3GetGCPhys(pSSM, &GCPhysLast);
1980	RTGCPHYS cb;
1981	SSMR3GetGCPhys(pSSM, &cb);
1982	uint8_t fHaveBits;
1983	rc = SSMR3GetU8(pSSM, &fHaveBits);
1984	if (VBOX_FAILURE(rc))
1985	return rc;
1986	if (fHaveBits & ~1)
1987	{
1988	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1989	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1990	}
1991
1992	/* Match it up with the current range. */
1993	if ( GCPhys != pRam->GCPhys
1994	\|\| GCPhysLast != pRam->GCPhysLast
1995	\|\| cb != pRam->cb
1996	\|\| fHaveBits != !!pRam->pvHC)
1997	{
1998	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
1999	"State : %VGp-%VGp %VGp bytes %s\n",
2000	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
2001	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2002	/*
2003	* If we're loading a state for debugging purpose, don't make a fuss if
2004	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2005	*/
2006	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2007	\|\| GCPhys < 8 * _1M)
2008	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2009
2010	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2011	while (cPages-- > 0)
2012	{
2013	uint16_t u16Ignore;
2014	SSMR3GetU16(pSSM, &u16Ignore);
2015	}
2016	continue;
2017	}
2018
2019	/* Flags. */
2020	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2021	for (unsigned iPage = 0; iPage < cPages; iPage++)
2022	{
2023	uint16_t u16 = 0;
2024	SSMR3GetU16(pSSM, &u16);
2025	u16 &= PAGE_OFFSET_MASK & ~( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
2026	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL
2027	\| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF );
2028	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2029	}
2030
2031	/* any memory associated with the range. */
2032	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2033	{
2034	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2035	{
2036	uint8_t fValidChunk;
2037
2038	rc = SSMR3GetU8(pSSM, &fValidChunk);
2039	if (VBOX_FAILURE(rc))
2040	return rc;
2041	if (fValidChunk > 1)
2042	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2043
2044	if (fValidChunk)
2045	{
2046	if (!pRam->pavHCChunkHC[iChunk])
2047	{
2048	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2049	if (VBOX_FAILURE(rc))
2050	return rc;
2051	}
2052	Assert(pRam->pavHCChunkHC[iChunk]);
2053
2054	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2055	}
2056	/* else nothing to do */
2057	}
2058	}
2059	else if (pRam->pvHC)
2060	{
2061	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
2062	if (VBOX_FAILURE(rc))
2063	{
2064	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2065	return rc;
2066	}
2067	}
2068	}
2069
2070	/*
2071	* We require a full resync now.
2072	*/
2073	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2074	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2075	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2076	pPGM->fPhysCacheFlushPending = true;
2077	pgmR3HandlerPhysicalUpdateAll(pVM);
2078
2079	/*
2080	* Change the paging mode.
2081	*/
2082	return pgmR3ChangeMode(pVM, pPGM->enmGuestMode);
2083	}
2084
2085
2086	/**
2087	* Show paging mode.
2088	*
2089	* @param pVM VM Handle.
2090	* @param pHlp The info helpers.
2091	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2092	*/
2093	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2094	{
2095	/* digest argument. */
2096	bool fGuest, fShadow, fHost;
2097	if (pszArgs)
2098	pszArgs = RTStrStripL(pszArgs);
2099	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2100	fShadow = fHost = fGuest = true;
2101	else
2102	{
2103	fShadow = fHost = fGuest = false;
2104	if (strstr(pszArgs, "guest"))
2105	fGuest = true;
2106	if (strstr(pszArgs, "shadow"))
2107	fShadow = true;
2108	if (strstr(pszArgs, "host"))
2109	fHost = true;
2110	}
2111
2112	/* print info. */
2113	if (fGuest)
2114	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2115	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2116	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2117	if (fShadow)
2118	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2119	if (fHost)
2120	{
2121	const char *psz;
2122	switch (pVM->pgm.s.enmHostMode)
2123	{
2124	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2125	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2126	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2127	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2128	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2129	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2130	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2131	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2132	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2133	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2134	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2135	default: psz = "unknown"; break;
2136	}
2137	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2138	}
2139	}
2140
2141
2142	/**
2143	* Dump registered MMIO ranges to the log.
2144	*
2145	* @param pVM VM Handle.
2146	* @param pHlp The info helpers.
2147	* @param pszArgs Arguments, ignored.
2148	*/
2149	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2150	{
2151	NOREF(pszArgs);
2152	pHlp->pfnPrintf(pHlp,
2153	"RAM ranges (pVM=%p)\n"
2154	"%.s %.s\n",
2155	pVM,
2156	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2157	sizeof(RTHCPTR) * 2, "pvHC ");
2158
2159	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur; pCur = pCur->pNextHC)
2160	pHlp->pfnPrintf(pHlp,
2161	"%VGp-%VGp %VHv\n",
2162	pCur->GCPhys,
2163	pCur->GCPhysLast,
2164	pCur->pvHC);
2165	}
2166
2167	/**
2168	* Dump the page directory to the log.
2169	*
2170	* @param pVM VM Handle.
2171	* @param pHlp The info helpers.
2172	* @param pszArgs Arguments, ignored.
2173	*/
2174	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2175	{
2176	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2177	/* Big pages supported? */
2178	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2179	/* Global pages supported? */
2180	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2181
2182	NOREF(pszArgs);
2183
2184	/*
2185	* Get page directory addresses.
2186	*/
2187	PVBOXPD pPDSrc = pVM->pgm.s.pGuestPDHC;
2188	Assert(pPDSrc);
2189	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2190
2191	/*
2192	* Iterate the page directory.
2193	*/
2194	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2195	{
2196	VBOXPDE PdeSrc = pPDSrc->a[iPD];
2197	if (PdeSrc.n.u1Present)
2198	{
2199	if (PdeSrc.b.u1Size && fPSE)
2200	{
2201	pHlp->pfnPrintf(pHlp,
2202	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2203	iPD,
2204	PdeSrc.u & X86_PDE_PG_MASK,
2205	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2206	}
2207	else
2208	{
2209	pHlp->pfnPrintf(pHlp,
2210	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2211	iPD,
2212	PdeSrc.u & X86_PDE4M_PG_MASK,
2213	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2214	}
2215	}
2216	}
2217	}
2218
2219
2220	/**
2221	* Serivce a VMMCALLHOST_PGM_LOCK call.
2222	*
2223	* @returns VBox status code.
2224	* @param pVM The VM handle.
2225	*/
2226	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
2227	{
2228	return pgmLock(pVM);
2229	}
2230
2231
2232	/**
2233	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2234	*
2235	* @returns PGM_TYPE_*.
2236	* @param pgmMode The mode value to convert.
2237	*/
2238	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2239	{
2240	switch (pgmMode)
2241	{
2242	case PGMMODE_REAL: return PGM_TYPE_REAL;
2243	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2244	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2245	case PGMMODE_PAE:
2246	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2247	case PGMMODE_AMD64:
2248	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2249	default:
2250	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2251	}
2252	}
2253
2254
2255	/**
2256	* Gets the index into the paging mode data array of a SHW+GST mode.
2257	*
2258	* @returns PGM::paPagingData index.
2259	* @param uShwType The shadow paging mode type.
2260	* @param uGstType The guest paging mode type.
2261	*/
2262	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2263	{
2264	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_AMD64);
2265	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2266	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_32BIT + 1)
2267	+ (uGstType - PGM_TYPE_REAL);
2268	}
2269
2270
2271	/**
2272	* Gets the index into the paging mode data array of a SHW+GST mode.
2273	*
2274	* @returns PGM::paPagingData index.
2275	* @param enmShw The shadow paging mode.
2276	* @param enmGst The guest paging mode.
2277	*/
2278	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2279	{
2280	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2281	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2282	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2283	}
2284
2285
2286	/**
2287	* Calculates the max data index.
2288	* @returns The number of entries in the pagaing data array.
2289	*/
2290	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2291	{
2292	return pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64) + 1;
2293	}
2294
2295
2296	/**
2297	* Initializes the paging mode data kept in PGM::paModeData.
2298	*
2299	* @param pVM The VM handle.
2300	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2301	* This is used early in the init process to avoid trouble with PDM
2302	* not being initialized yet.
2303	*/
2304	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2305	{
2306	PPGMMODEDATA pModeData;
2307	int rc;
2308
2309	/*
2310	* Allocate the array on the first call.
2311	*/
2312	if (!pVM->pgm.s.paModeData)
2313	{
2314	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2315	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2316	}
2317
2318	/*
2319	* Initialize the array entries.
2320	*/
2321	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2322	pModeData->uShwType = PGM_TYPE_32BIT;
2323	pModeData->uGstType = PGM_TYPE_REAL;
2324	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2325	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2326	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2327
2328	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2329	pModeData->uShwType = PGM_TYPE_32BIT;
2330	pModeData->uGstType = PGM_TYPE_PROT;
2331	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2332	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2333	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2334
2335	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2336	pModeData->uShwType = PGM_TYPE_32BIT;
2337	pModeData->uGstType = PGM_TYPE_32BIT;
2338	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2339	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2340	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2341
2342	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2343	pModeData->uShwType = PGM_TYPE_PAE;
2344	pModeData->uGstType = PGM_TYPE_REAL;
2345	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2346	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2347	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2348
2349	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2350	pModeData->uShwType = PGM_TYPE_PAE;
2351	pModeData->uGstType = PGM_TYPE_PROT;
2352	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2353	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2354	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2355
2356	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2357	pModeData->uShwType = PGM_TYPE_PAE;
2358	pModeData->uGstType = PGM_TYPE_32BIT;
2359	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2360	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2361	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2362
2363	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2364	pModeData->uShwType = PGM_TYPE_PAE;
2365	pModeData->uGstType = PGM_TYPE_PAE;
2366	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2367	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2368	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2369
2370	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_REAL)];
2371	pModeData->uShwType = PGM_TYPE_AMD64;
2372	pModeData->uGstType = PGM_TYPE_REAL;
2373	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2374	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2375	rc = PGM_BTH_NAME_AMD64_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2376
2377	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_PROT)];
2378	pModeData->uShwType = PGM_TYPE_AMD64;
2379	pModeData->uGstType = PGM_TYPE_PROT;
2380	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2381	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2382	rc = PGM_BTH_NAME_AMD64_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2383
2384	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2385	pModeData->uShwType = PGM_TYPE_AMD64;
2386	pModeData->uGstType = PGM_TYPE_AMD64;
2387	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2388	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2389	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2390
2391	return VINF_SUCCESS;
2392	}
2393
2394
2395	/**
2396	* Swtich to different (or relocated in the relocate case) mode data.
2397	*
2398	* @param pVM The VM handle.
2399	* @param enmShw The the shadow paging mode.
2400	* @param enmGst The the guest paging mode.
2401	*/
2402	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2403	{
2404	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(enmShw, enmGst)];
2405
2406	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2407	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2408
2409	/* shadow */
2410	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2411	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2412	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2413	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2414	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2415	pVM->pgm.s.pfnR3ShwGetPDEByIndex = pModeData->pfnR3ShwGetPDEByIndex;
2416	pVM->pgm.s.pfnR3ShwSetPDEByIndex = pModeData->pfnR3ShwSetPDEByIndex;
2417	pVM->pgm.s.pfnR3ShwModifyPDEByIndex = pModeData->pfnR3ShwModifyPDEByIndex;
2418
2419	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2420	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2421	pVM->pgm.s.pfnGCShwGetPDEByIndex = pModeData->pfnGCShwGetPDEByIndex;
2422	pVM->pgm.s.pfnGCShwSetPDEByIndex = pModeData->pfnGCShwSetPDEByIndex;
2423	pVM->pgm.s.pfnGCShwModifyPDEByIndex = pModeData->pfnGCShwModifyPDEByIndex;
2424
2425	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2426	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2427	pVM->pgm.s.pfnR0ShwGetPDEByIndex = pModeData->pfnR0ShwGetPDEByIndex;
2428	pVM->pgm.s.pfnR0ShwSetPDEByIndex = pModeData->pfnR0ShwSetPDEByIndex;
2429	pVM->pgm.s.pfnR0ShwModifyPDEByIndex = pModeData->pfnR0ShwModifyPDEByIndex;
2430
2431
2432	/* guest */
2433	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2434	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2435	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2436	Assert(pVM->pgm.s.pfnR3GstGetPage);
2437	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2438	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2439	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2440	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2441	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2442	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2443	pVM->pgm.s.pfnHCGstWriteHandlerCR3 = pModeData->pfnHCGstWriteHandlerCR3;
2444	pVM->pgm.s.pszHCGstWriteHandlerCR3 = pModeData->pszHCGstWriteHandlerCR3;
2445
2446	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2447	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2448	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2449	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2450	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2451	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2452	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2453	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2454
2455	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2456	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2457	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2458	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2459	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2460	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2461	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2462	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2463
2464
2465	/* both */
2466	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2467	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2468	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2469	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2470	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2471	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2472	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2473	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2474	#ifdef VBOX_STRICT
2475	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2476	#endif
2477
2478	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2479	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2480	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2481	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2482	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2483	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2484	#ifdef VBOX_STRICT
2485	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2486	#endif
2487
2488	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2489	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2490	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2491	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2492	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2493	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2494	#ifdef VBOX_STRICT
2495	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2496	#endif
2497	}
2498
2499
2500	#ifdef DEBUG_bird
2501	#include <stdlib.h> /* getenv() remove me! */
2502	#endif
2503
2504	/**
2505	* Calculates the shadow paging mode.
2506	*
2507	* @returns The shadow paging mode.
2508	* @param enmGuestMode The guest mode.
2509	* @param enmHostMode The host mode.
2510	* @param enmShadowMode The current shadow mode.
2511	* @param penmSwitcher Where to store the switcher to use.
2512	* VMMSWITCHER_INVALID means no change.
2513	*/
2514	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2515	{
2516	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2517	switch (enmGuestMode)
2518	{
2519	/*
2520	* When switching to real or protected mode we don't change
2521	* anything since it's likely that we'll switch back pretty soon.
2522	*
2523	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2524	* and is supposed to determin which shadow paging and switcher to
2525	* use during init.
2526	*/
2527	case PGMMODE_REAL:
2528	case PGMMODE_PROTECTED:
2529	if (enmShadowMode != PGMMODE_INVALID)
2530	break; /* (no change) */
2531	switch (enmHostMode)
2532	{
2533	case SUPPAGINGMODE_32_BIT:
2534	case SUPPAGINGMODE_32_BIT_GLOBAL:
2535	enmShadowMode = PGMMODE_32_BIT;
2536	enmSwitcher = VMMSWITCHER_32_TO_32;
2537	break;
2538
2539	case SUPPAGINGMODE_PAE:
2540	case SUPPAGINGMODE_PAE_NX:
2541	case SUPPAGINGMODE_PAE_GLOBAL:
2542	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2543	enmShadowMode = PGMMODE_PAE;
2544	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2545	#ifdef DEBUG_bird
2546	if (getenv("VBOX_32BIT"))
2547	{
2548	enmShadowMode = PGMMODE_32_BIT;
2549	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2550	}
2551	#endif
2552	break;
2553
2554	case SUPPAGINGMODE_AMD64:
2555	case SUPPAGINGMODE_AMD64_GLOBAL:
2556	case SUPPAGINGMODE_AMD64_NX:
2557	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2558	enmShadowMode = PGMMODE_PAE;
2559	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2560	break;
2561
2562	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2563	}
2564	break;
2565
2566	case PGMMODE_32_BIT:
2567	switch (enmHostMode)
2568	{
2569	case SUPPAGINGMODE_32_BIT:
2570	case SUPPAGINGMODE_32_BIT_GLOBAL:
2571	enmShadowMode = PGMMODE_32_BIT;
2572	enmSwitcher = VMMSWITCHER_32_TO_32;
2573	break;
2574
2575	case SUPPAGINGMODE_PAE:
2576	case SUPPAGINGMODE_PAE_NX:
2577	case SUPPAGINGMODE_PAE_GLOBAL:
2578	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2579	enmShadowMode = PGMMODE_PAE;
2580	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2581	#ifdef DEBUG_bird
2582	if (getenv("VBOX_32BIT"))
2583	{
2584	enmShadowMode = PGMMODE_32_BIT;
2585	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2586	}
2587	#endif
2588	break;
2589
2590	case SUPPAGINGMODE_AMD64:
2591	case SUPPAGINGMODE_AMD64_GLOBAL:
2592	case SUPPAGINGMODE_AMD64_NX:
2593	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2594	enmShadowMode = PGMMODE_PAE;
2595	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2596	break;
2597
2598	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2599	}
2600	break;
2601
2602	case PGMMODE_PAE:
2603	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2604	switch (enmHostMode)
2605	{
2606	case SUPPAGINGMODE_32_BIT:
2607	case SUPPAGINGMODE_32_BIT_GLOBAL:
2608	enmShadowMode = PGMMODE_PAE;
2609	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2610	break;
2611
2612	case SUPPAGINGMODE_PAE:
2613	case SUPPAGINGMODE_PAE_NX:
2614	case SUPPAGINGMODE_PAE_GLOBAL:
2615	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2616	enmShadowMode = PGMMODE_PAE;
2617	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2618	break;
2619
2620	case SUPPAGINGMODE_AMD64:
2621	case SUPPAGINGMODE_AMD64_GLOBAL:
2622	case SUPPAGINGMODE_AMD64_NX:
2623	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2624	enmShadowMode = PGMMODE_PAE;
2625	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2626	break;
2627
2628	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2629	}
2630	break;
2631
2632	case PGMMODE_AMD64:
2633	case PGMMODE_AMD64_NX:
2634	switch (enmHostMode)
2635	{
2636	case SUPPAGINGMODE_32_BIT:
2637	case SUPPAGINGMODE_32_BIT_GLOBAL:
2638	enmShadowMode = PGMMODE_PAE;
2639	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2640	break;
2641
2642	case SUPPAGINGMODE_PAE:
2643	case SUPPAGINGMODE_PAE_NX:
2644	case SUPPAGINGMODE_PAE_GLOBAL:
2645	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2646	enmShadowMode = PGMMODE_PAE;
2647	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2648	break;
2649
2650	case SUPPAGINGMODE_AMD64:
2651	case SUPPAGINGMODE_AMD64_GLOBAL:
2652	case SUPPAGINGMODE_AMD64_NX:
2653	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2654	enmShadowMode = PGMMODE_PAE;
2655	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2656	break;
2657
2658	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2659	}
2660	break;
2661
2662
2663	default:
2664	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2665	return PGMMODE_INVALID;
2666	}
2667
2668	*penmSwitcher = enmSwitcher;
2669	return enmShadowMode;
2670	}
2671
2672
2673	/**
2674	* Performs the actual mode change.
2675	* This is called by PGMChangeMode and pgmR3InitPaging().
2676	*
2677	* @returns VBox status code.
2678	* @param pVM VM handle.
2679	* @param enmGuestMode The new guest mode. This is assumed to be different from
2680	* the current mode.
2681	*/
2682	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
2683	{
2684	LogFlow(("pgmR3ChangeMode: Guest mode: %d -> %d\n", pVM->pgm.s.enmGuestMode, enmGuestMode));
2685	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
2686
2687	/*
2688	* Calc the shadow mode and switcher.
2689	*/
2690	VMMSWITCHER enmSwitcher;
2691	PGMMODE enmShadowMode = pgmR3CalcShadowMode(enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
2692	if (enmSwitcher != VMMSWITCHER_INVALID)
2693	{
2694	/*
2695	* Select new switcher.
2696	*/
2697	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
2698	if (VBOX_FAILURE(rc))
2699	{
2700	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
2701	return rc;
2702	}
2703	}
2704
2705	/*
2706	* Exit old mode(s).
2707	*/
2708	/* shadow */
2709	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2710	{
2711	LogFlow(("pgmR3ChangeMode: Shadow mode: %d -> %d\n", pVM->pgm.s.enmShadowMode, enmShadowMode));
2712	if (PGM_SHW_PFN(Exit, pVM))
2713	{
2714	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
2715	if (VBOX_FAILURE(rc))
2716	{
2717	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
2718	return rc;
2719	}
2720	}
2721
2722	}
2723
2724	/* guest */
2725	if (PGM_GST_PFN(Exit, pVM))
2726	{
2727	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2728	if (VBOX_FAILURE(rc))
2729	{
2730	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
2731	return rc;
2732	}
2733	}
2734
2735	/*
2736	* Load new paging mode data.
2737	*/
2738	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
2739
2740	/*
2741	* Enter new shadow mode (if changed).
2742	*/
2743	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2744	{
2745	int rc;
2746	pVM->pgm.s.enmShadowMode = enmShadowMode;
2747	switch (enmShadowMode)
2748	{
2749	case PGMMODE_32_BIT:
2750	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
2751	break;
2752	case PGMMODE_PAE:
2753	case PGMMODE_PAE_NX:
2754	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
2755	break;
2756	case PGMMODE_AMD64:
2757	case PGMMODE_AMD64_NX:
2758	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
2759	break;
2760	case PGMMODE_REAL:
2761	case PGMMODE_PROTECTED:
2762	default:
2763	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
2764	return VERR_INTERNAL_ERROR;
2765	}
2766	if (VBOX_FAILURE(rc))
2767	{
2768	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
2769	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
2770	return rc;
2771	}
2772	}
2773
2774	/*
2775	* Enter the new guest and shadow+guest modes.
2776	*/
2777	int rc = -1;
2778	int rc2 = -1;
2779	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
2780	pVM->pgm.s.enmGuestMode = enmGuestMode;
2781	switch (enmGuestMode)
2782	{
2783	case PGMMODE_REAL:
2784	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
2785	switch (pVM->pgm.s.enmShadowMode)
2786	{
2787	case PGMMODE_32_BIT:
2788	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
2789	break;
2790	case PGMMODE_PAE:
2791	case PGMMODE_PAE_NX:
2792	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
2793	break;
2794	case PGMMODE_AMD64:
2795	case PGMMODE_AMD64_NX:
2796	rc2 = PGM_BTH_NAME_AMD64_REAL(Enter)(pVM, NIL_RTGCPHYS);
2797	break;
2798	default: AssertFailed(); break;
2799	}
2800	break;
2801
2802	case PGMMODE_PROTECTED:
2803	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
2804	switch (pVM->pgm.s.enmShadowMode)
2805	{
2806	case PGMMODE_32_BIT:
2807	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
2808	break;
2809	case PGMMODE_PAE:
2810	case PGMMODE_PAE_NX:
2811	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
2812	break;
2813	case PGMMODE_AMD64:
2814	case PGMMODE_AMD64_NX:
2815	rc2 = PGM_BTH_NAME_AMD64_PROT(Enter)(pVM, NIL_RTGCPHYS);
2816	break;
2817	default: AssertFailed(); break;
2818	}
2819	break;
2820
2821	case PGMMODE_32_BIT:
2822	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
2823	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
2824	switch (pVM->pgm.s.enmShadowMode)
2825	{
2826	case PGMMODE_32_BIT:
2827	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
2828	break;
2829	case PGMMODE_PAE:
2830	case PGMMODE_PAE_NX:
2831	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
2832	break;
2833	case PGMMODE_AMD64:
2834	case PGMMODE_AMD64_NX:
2835	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2836	default: AssertFailed(); break;
2837	}
2838	break;
2839
2840	//case PGMMODE_PAE_NX:
2841	case PGMMODE_PAE:
2842	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
2843	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
2844	switch (pVM->pgm.s.enmShadowMode)
2845	{
2846	case PGMMODE_PAE:
2847	case PGMMODE_PAE_NX:
2848	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
2849	break;
2850	case PGMMODE_32_BIT:
2851	case PGMMODE_AMD64:
2852	case PGMMODE_AMD64_NX:
2853	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2854	default: AssertFailed(); break;
2855	}
2856	break;
2857
2858	//case PGMMODE_AMD64_NX:
2859	case PGMMODE_AMD64:
2860	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask and make CR3 64-bit in this case! */
2861	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
2862	switch (pVM->pgm.s.enmShadowMode)
2863	{
2864	case PGMMODE_AMD64:
2865	case PGMMODE_AMD64_NX:
2866	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
2867	break;
2868	case PGMMODE_32_BIT:
2869	case PGMMODE_PAE:
2870	case PGMMODE_PAE_NX:
2871	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
2872	default: AssertFailed(); break;
2873	}
2874	break;
2875
2876	default:
2877	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2878	rc = VERR_NOT_IMPLEMENTED;
2879	break;
2880	}
2881
2882	/* status codes. */
2883	AssertRC(rc);
2884	AssertRC(rc2);
2885	if (VBOX_SUCCESS(rc))
2886	{
2887	rc = rc2;
2888	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
2889	rc = VINF_SUCCESS;
2890	}
2891
2892	/*
2893	* Notify SELM so it can update the TSSes with correct CR3s.
2894	*/
2895	SELMR3PagingModeChanged(pVM);
2896
2897	/* Notify HWACCM as well. */
2898	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
2899	return rc;
2900	}
2901
2902
2903	/**
2904	* Dumps a PAE shadow page table.
2905	*
2906	* @returns VBox status code (VINF_SUCCESS).
2907	* @param pVM The VM handle.
2908	* @param pPT Pointer to the page table.
2909	* @param u64Address The virtual address of the page table starts.
2910	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2911	* @param cMaxDepth The maxium depth.
2912	* @param pHlp Pointer to the output functions.
2913	*/
2914	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2915	{
2916	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2917	{
2918	X86PTEPAE Pte = pPT->a[i];
2919	if (Pte.n.u1Present)
2920	{
2921	pHlp->pfnPrintf(pHlp,
2922	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2923	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
2924	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
2925	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
2926	Pte.n.u1Write ? 'W' : 'R',
2927	Pte.n.u1User ? 'U' : 'S',
2928	Pte.n.u1Accessed ? 'A' : '-',
2929	Pte.n.u1Dirty ? 'D' : '-',
2930	Pte.n.u1Global ? 'G' : '-',
2931	Pte.n.u1WriteThru ? "WT" : "--",
2932	Pte.n.u1CacheDisable? "CD" : "--",
2933	Pte.n.u1PAT ? "AT" : "--",
2934	Pte.n.u1NoExecute ? "NX" : "--",
2935	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2936	Pte.u & RT_BIT(10) ? '1' : '0',
2937	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
2938	Pte.u & X86_PTE_PAE_PG_MASK);
2939	}
2940	}
2941	return VINF_SUCCESS;
2942	}
2943
2944
2945	/**
2946	* Dumps a PAE shadow page directory table.
2947	*
2948	* @returns VBox status code (VINF_SUCCESS).
2949	* @param pVM The VM handle.
2950	* @param HCPhys The physical address of the page directory table.
2951	* @param u64Address The virtual address of the page table starts.
2952	* @param cr4 The CR4, PSE is currently used.
2953	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2954	* @param cMaxDepth The maxium depth.
2955	* @param pHlp Pointer to the output functions.
2956	*/
2957	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2958	{
2959	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
2960	if (!pPD)
2961	{
2962	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
2963	fLongMode ? 16 : 8, u64Address, HCPhys);
2964	return VERR_INVALID_PARAMETER;
2965	}
2966	int rc = VINF_SUCCESS;
2967	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2968	{
2969	X86PDEPAE Pde = pPD->a[i];
2970	if (Pde.n.u1Present)
2971	{
2972	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2973	pHlp->pfnPrintf(pHlp,
2974	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2975	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
2976	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
2977	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2978	Pde.b.u1Write ? 'W' : 'R',
2979	Pde.b.u1User ? 'U' : 'S',
2980	Pde.b.u1Accessed ? 'A' : '-',
2981	Pde.b.u1Dirty ? 'D' : '-',
2982	Pde.b.u1Global ? 'G' : '-',
2983	Pde.b.u1WriteThru ? "WT" : "--",
2984	Pde.b.u1CacheDisable? "CD" : "--",
2985	Pde.b.u1PAT ? "AT" : "--",
2986	Pde.b.u1NoExecute ? "NX" : "--",
2987	Pde.u & RT_BIT_64(9) ? '1' : '0',
2988	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2989	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2990	Pde.u & X86_PDE_PAE_PG_MASK);
2991	else
2992	{
2993	pHlp->pfnPrintf(pHlp,
2994	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2995	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
2996	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
2997	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2998	Pde.n.u1Write ? 'W' : 'R',
2999	Pde.n.u1User ? 'U' : 'S',
3000	Pde.n.u1Accessed ? 'A' : '-',
3001	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3002	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3003	Pde.n.u1WriteThru ? "WT" : "--",
3004	Pde.n.u1CacheDisable? "CD" : "--",
3005	Pde.n.u1NoExecute ? "NX" : "--",
3006	Pde.u & RT_BIT_64(9) ? '1' : '0',
3007	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3008	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3009	Pde.u & X86_PDE_PAE_PG_MASK);
3010	if (cMaxDepth >= 1)
3011	{
3012	/** @todo what about using the page pool for mapping PTs? */
3013	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3014	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3015	PX86PTPAE pPT = NULL;
3016	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3017	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3018	else
3019	{
3020	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3021	{
3022	uint64_t off = u64AddressPT - pMap->GCPtr;
3023	if (off < pMap->cb)
3024	{
3025	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3026	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3027	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3028	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3029	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3030	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3031	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3032	}
3033	}
3034	}
3035	int rc2 = VERR_INVALID_PARAMETER;
3036	if (pPT)
3037	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3038	else
3039	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3040	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3041	if (rc2 < rc && VBOX_SUCCESS(rc))
3042	rc = rc2;
3043	}
3044	}
3045	}
3046	}
3047	return rc;
3048	}
3049
3050
3051	/**
3052	* Dumps a PAE shadow page directory pointer table.
3053	*
3054	* @returns VBox status code (VINF_SUCCESS).
3055	* @param pVM The VM handle.
3056	* @param HCPhys The physical address of the page directory pointer table.
3057	* @param u64Address The virtual address of the page table starts.
3058	* @param cr4 The CR4, PSE is currently used.
3059	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3060	* @param cMaxDepth The maxium depth.
3061	* @param pHlp Pointer to the output functions.
3062	*/
3063	static int pgmR3DumpHierarchyHCPaePDPTR(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3064	{
3065	PX86PDPTR pPDPTR = (PX86PDPTR)MMPagePhys2Page(pVM, HCPhys);
3066	if (!pPDPTR)
3067	{
3068	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3069	fLongMode ? 16 : 8, u64Address, HCPhys);
3070	return VERR_INVALID_PARAMETER;
3071	}
3072
3073	int rc = VINF_SUCCESS;
3074	const unsigned c = fLongMode ? ELEMENTS(pPDPTR->a) : 4;
3075	for (unsigned i = 0; i < c; i++)
3076	{
3077	X86PDPE Pdpe = pPDPTR->a[i];
3078	if (Pdpe.n.u1Present)
3079	{
3080	if (fLongMode)
3081	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3082	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3083	u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
3084	Pdpe.n.u1Write ? 'W' : 'R',
3085	Pdpe.n.u1User ? 'U' : 'S',
3086	Pdpe.n.u1Accessed ? 'A' : '-',
3087	Pdpe.n.u3Reserved & 1? '?' : '.', /* ignored */
3088	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
3089	Pdpe.n.u1WriteThru ? "WT" : "--",
3090	Pdpe.n.u1CacheDisable? "CD" : "--",
3091	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
3092	Pdpe.n.u1NoExecute ? "NX" : "--",
3093	Pdpe.u & RT_BIT(9) ? '1' : '0',
3094	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3095	Pdpe.u & RT_BIT(11) ? '1' : '0',
3096	Pdpe.u & X86_PDPE_PG_MASK);
3097	else
3098	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3099	"%08x 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3100	i << X86_PDPTR_SHIFT,
3101	Pdpe.n.u1Write ? '!' : '.', /* mbz */
3102	Pdpe.n.u1User ? '!' : '.', /* mbz */
3103	Pdpe.n.u1Accessed ? '!' : '.', /* mbz */
3104	Pdpe.n.u3Reserved & 1? '!' : '.', /* mbz */
3105	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
3106	Pdpe.n.u1WriteThru ? "WT" : "--",
3107	Pdpe.n.u1CacheDisable? "CD" : "--",
3108	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
3109	Pdpe.n.u1NoExecute ? "NX" : "--",
3110	Pdpe.u & RT_BIT(9) ? '1' : '0',
3111	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3112	Pdpe.u & RT_BIT(11) ? '1' : '0',
3113	Pdpe.u & X86_PDPE_PG_MASK);
3114	if (cMaxDepth >= 1)
3115	{
3116	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
3117	cr4, fLongMode, cMaxDepth - 1, pHlp);
3118	if (rc2 < rc && VBOX_SUCCESS(rc))
3119	rc = rc2;
3120	}
3121	}
3122	}
3123	return rc;
3124	}
3125
3126
3127	/**
3128	* Dumps a 32-bit shadow page table.
3129	*
3130	* @returns VBox status code (VINF_SUCCESS).
3131	* @param pVM The VM handle.
3132	* @param HCPhys The physical address of the table.
3133	* @param cr4 The CR4, PSE is currently used.
3134	* @param cMaxDepth The maxium depth.
3135	* @param pHlp Pointer to the output functions.
3136	*/
3137	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3138	{
3139	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3140	if (!pPML4)
3141	{
3142	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3143	return VERR_INVALID_PARAMETER;
3144	}
3145
3146	int rc = VINF_SUCCESS;
3147	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
3148	{
3149	X86PML4E Pml4e = pPML4->a[i];
3150	if (Pml4e.n.u1Present)
3151	{
3152	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPTR_SHIFT - 1)) * 0xffff000000000000ULL);
3153	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3154	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3155	u64Address,
3156	Pml4e.n.u1Write ? 'W' : 'R',
3157	Pml4e.n.u1User ? 'U' : 'S',
3158	Pml4e.n.u1Accessed ? 'A' : '-',
3159	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3160	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3161	Pml4e.n.u1WriteThru ? "WT" : "--",
3162	Pml4e.n.u1CacheDisable? "CD" : "--",
3163	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3164	Pml4e.n.u1NoExecute ? "NX" : "--",
3165	Pml4e.u & RT_BIT(9) ? '1' : '0',
3166	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3167	Pml4e.u & RT_BIT(11) ? '1' : '0',
3168	Pml4e.u & X86_PML4E_PG_MASK);
3169
3170	if (cMaxDepth >= 1)
3171	{
3172	int rc2 = pgmR3DumpHierarchyHCPaePDPTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3173	if (rc2 < rc && VBOX_SUCCESS(rc))
3174	rc = rc2;
3175	}
3176	}
3177	}
3178	return rc;
3179	}
3180
3181
3182	/**
3183	* Dumps a 32-bit shadow page table.
3184	*
3185	* @returns VBox status code (VINF_SUCCESS).
3186	* @param pVM The VM handle.
3187	* @param pPT Pointer to the page table.
3188	* @param u32Address The virtual address this table starts at.
3189	* @param pHlp Pointer to the output functions.
3190	*/
3191	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3192	{
3193	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3194	{
3195	X86PTE Pte = pPT->a[i];
3196	if (Pte.n.u1Present)
3197	{
3198	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3199	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3200	u32Address + (i << X86_PT_SHIFT),
3201	Pte.n.u1Write ? 'W' : 'R',
3202	Pte.n.u1User ? 'U' : 'S',
3203	Pte.n.u1Accessed ? 'A' : '-',
3204	Pte.n.u1Dirty ? 'D' : '-',
3205	Pte.n.u1Global ? 'G' : '-',
3206	Pte.n.u1WriteThru ? "WT" : "--",
3207	Pte.n.u1CacheDisable? "CD" : "--",
3208	Pte.n.u1PAT ? "AT" : "--",
3209	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3210	Pte.u & RT_BIT(10) ? '1' : '0',
3211	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3212	Pte.u & X86_PDE_PG_MASK);
3213	}
3214	}
3215	return VINF_SUCCESS;
3216	}
3217
3218
3219	/**
3220	* Dumps a 32-bit shadow page directory and page tables.
3221	*
3222	* @returns VBox status code (VINF_SUCCESS).
3223	* @param pVM The VM handle.
3224	* @param cr3 The root of the hierarchy.
3225	* @param cr4 The CR4, PSE is currently used.
3226	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3227	* @param pHlp Pointer to the output functions.
3228	*/
3229	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3230	{
3231	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3232	if (!pPD)
3233	{
3234	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3235	return VERR_INVALID_PARAMETER;
3236	}
3237
3238	int rc = VINF_SUCCESS;
3239	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3240	{
3241	X86PDE Pde = pPD->a[i];
3242	if (Pde.n.u1Present)
3243	{
3244	const uint32_t u32Address = i << X86_PD_SHIFT;
3245	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3246	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3247	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3248	u32Address,
3249	Pde.b.u1Write ? 'W' : 'R',
3250	Pde.b.u1User ? 'U' : 'S',
3251	Pde.b.u1Accessed ? 'A' : '-',
3252	Pde.b.u1Dirty ? 'D' : '-',
3253	Pde.b.u1Global ? 'G' : '-',
3254	Pde.b.u1WriteThru ? "WT" : "--",
3255	Pde.b.u1CacheDisable? "CD" : "--",
3256	Pde.b.u1PAT ? "AT" : "--",
3257	Pde.u & RT_BIT_64(9) ? '1' : '0',
3258	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3259	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3260	Pde.u & X86_PDE4M_PG_MASK);
3261	else
3262	{
3263	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3264	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3265	u32Address,
3266	Pde.n.u1Write ? 'W' : 'R',
3267	Pde.n.u1User ? 'U' : 'S',
3268	Pde.n.u1Accessed ? 'A' : '-',
3269	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3270	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3271	Pde.n.u1WriteThru ? "WT" : "--",
3272	Pde.n.u1CacheDisable? "CD" : "--",
3273	Pde.u & RT_BIT_64(9) ? '1' : '0',
3274	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3275	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3276	Pde.u & X86_PDE_PG_MASK);
3277	if (cMaxDepth >= 1)
3278	{
3279	/** @todo what about using the page pool for mapping PTs? */
3280	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3281	PX86PT pPT = NULL;
3282	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3283	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3284	else
3285	{
3286	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3287	if (u32Address - pMap->GCPtr < pMap->cb)
3288	{
3289	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3290	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3291	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3292	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3293	pPT = pMap->aPTs[iPDE].pPTR3;
3294	}
3295	}
3296	int rc2 = VERR_INVALID_PARAMETER;
3297	if (pPT)
3298	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3299	else
3300	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3301	if (rc2 < rc && VBOX_SUCCESS(rc))
3302	rc = rc2;
3303	}
3304	}
3305	}
3306	}
3307
3308	return rc;
3309	}
3310
3311
3312	/**
3313	* Dumps a 32-bit shadow page table.
3314	*
3315	* @returns VBox status code (VINF_SUCCESS).
3316	* @param pVM The VM handle.
3317	* @param pPT Pointer to the page table.
3318	* @param u32Address The virtual address this table starts at.
3319	* @param PhysSearch Address to search for.
3320	*/
3321	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3322	{
3323	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3324	{
3325	X86PTE Pte = pPT->a[i];
3326	if (Pte.n.u1Present)
3327	{
3328	Log(( /P R S A D G WT CD AT NX 4M a m d /
3329	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3330	u32Address + (i << X86_PT_SHIFT),
3331	Pte.n.u1Write ? 'W' : 'R',
3332	Pte.n.u1User ? 'U' : 'S',
3333	Pte.n.u1Accessed ? 'A' : '-',
3334	Pte.n.u1Dirty ? 'D' : '-',
3335	Pte.n.u1Global ? 'G' : '-',
3336	Pte.n.u1WriteThru ? "WT" : "--",
3337	Pte.n.u1CacheDisable? "CD" : "--",
3338	Pte.n.u1PAT ? "AT" : "--",
3339	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3340	Pte.u & RT_BIT(10) ? '1' : '0',
3341	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3342	Pte.u & X86_PDE_PG_MASK));
3343
3344	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3345	{
3346	uint64_t fPageShw = 0;
3347	RTHCPHYS pPhysHC = 0;
3348
3349	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3350	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3351	}
3352	}
3353	}
3354	return VINF_SUCCESS;
3355	}
3356
3357
3358	/**
3359	* Dumps a 32-bit guest page directory and page tables.
3360	*
3361	* @returns VBox status code (VINF_SUCCESS).
3362	* @param pVM The VM handle.
3363	* @param cr3 The root of the hierarchy.
3364	* @param cr4 The CR4, PSE is currently used.
3365	* @param PhysSearch Address to search for.
3366	*/
3367	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCPHYS PhysSearch)
3368	{
3369	bool fLongMode = false;
3370	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3371	PX86PD pPD = 0;
3372
3373	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3374	if (VBOX_FAILURE(rc) \|\| !pPD)
3375	{
3376	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3377	return VERR_INVALID_PARAMETER;
3378	}
3379
3380	Log(("cr3=%08x cr4=%08x%s\n"
3381	"%-*s P - Present\n"
3382	"%-*s \| R/W - Read (0) / Write (1)\n"
3383	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3384	"%-*s \| \| \| A - Accessed\n"
3385	"%-*s \| \| \| \| D - Dirty\n"
3386	"%-*s \| \| \| \| \| G - Global\n"
3387	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3388	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3389	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3390	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3391	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3392	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3393	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3394	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3395	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3396	- W U - - - -- -- -- -- -- 010 */
3397	, cr3, cr4, fLongMode ? " Long Mode" : "",
3398	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3399	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3400
3401	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3402	{
3403	X86PDE Pde = pPD->a[i];
3404	if (Pde.n.u1Present)
3405	{
3406	const uint32_t u32Address = i << X86_PD_SHIFT;
3407
3408	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3409	Log(( /P R S A D G WT CD AT NX 4M a m d /
3410	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3411	u32Address,
3412	Pde.b.u1Write ? 'W' : 'R',
3413	Pde.b.u1User ? 'U' : 'S',
3414	Pde.b.u1Accessed ? 'A' : '-',
3415	Pde.b.u1Dirty ? 'D' : '-',
3416	Pde.b.u1Global ? 'G' : '-',
3417	Pde.b.u1WriteThru ? "WT" : "--",
3418	Pde.b.u1CacheDisable? "CD" : "--",
3419	Pde.b.u1PAT ? "AT" : "--",
3420	Pde.u & RT_BIT(9) ? '1' : '0',
3421	Pde.u & RT_BIT(10) ? '1' : '0',
3422	Pde.u & RT_BIT(11) ? '1' : '0',
3423	Pde.u & X86_PDE4M_PG_MASK));
3424	/** @todo PhysSearch */
3425	else
3426	{
3427	Log(( /P R S A D G WT CD AT NX 4M a m d /
3428	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3429	u32Address,
3430	Pde.n.u1Write ? 'W' : 'R',
3431	Pde.n.u1User ? 'U' : 'S',
3432	Pde.n.u1Accessed ? 'A' : '-',
3433	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3434	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3435	Pde.n.u1WriteThru ? "WT" : "--",
3436	Pde.n.u1CacheDisable? "CD" : "--",
3437	Pde.u & RT_BIT(9) ? '1' : '0',
3438	Pde.u & RT_BIT(10) ? '1' : '0',
3439	Pde.u & RT_BIT(11) ? '1' : '0',
3440	Pde.u & X86_PDE_PG_MASK));
3441	////if (cMaxDepth >= 1)
3442	{
3443	/** @todo what about using the page pool for mapping PTs? */
3444	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3445	PX86PT pPT = NULL;
3446
3447	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3448
3449	int rc2 = VERR_INVALID_PARAMETER;
3450	if (pPT)
3451	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3452	else
3453	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3454	if (rc2 < rc && VBOX_SUCCESS(rc))
3455	rc = rc2;
3456	}
3457	}
3458	}
3459	}
3460
3461	return rc;
3462	}
3463
3464
3465	/**
3466	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3467	*
3468	* @returns VBox status code (VINF_SUCCESS).
3469	* @param pVM The VM handle.
3470	* @param cr3 The root of the hierarchy.
3471	* @param cr4 The cr4, only PAE and PSE is currently used.
3472	* @param fLongMode Set if long mode, false if not long mode.
3473	* @param cMaxDepth Number of levels to dump.
3474	* @param pHlp Pointer to the output functions.
3475	*/
3476	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3477	{
3478	if (!pHlp)
3479	pHlp = DBGFR3InfoLogHlp();
3480	if (!cMaxDepth)
3481	return VINF_SUCCESS;
3482	const unsigned cch = fLongMode ? 16 : 8;
3483	pHlp->pfnPrintf(pHlp,
3484	"cr3=%08x cr4=%08x%s\n"
3485	"%-*s P - Present\n"
3486	"%-*s \| R/W - Read (0) / Write (1)\n"
3487	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3488	"%-*s \| \| \| A - Accessed\n"
3489	"%-*s \| \| \| \| D - Dirty\n"
3490	"%-*s \| \| \| \| \| G - Global\n"
3491	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3492	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3493	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3494	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3495	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3496	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3497	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3498	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3499	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3500	- W U - - - -- -- -- -- -- 010 */
3501	, cr3, cr4, fLongMode ? " Long Mode" : "",
3502	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3503	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3504	if (cr4 & X86_CR4_PAE)
3505	{
3506	if (fLongMode)
3507	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3508	return pgmR3DumpHierarchyHCPaePDPTR(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3509	}
3510	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3511	}
3512
3513
3514
3515	#ifdef VBOX_WITH_DEBUGGER
3516	/**
3517	* The '.pgmram' command.
3518	*
3519	* @returns VBox status.
3520	* @param pCmd Pointer to the command descriptor (as registered).
3521	* @param pCmdHlp Pointer to command helper functions.
3522	* @param pVM Pointer to the current VM (if any).
3523	* @param paArgs Pointer to (readonly) array of arguments.
3524	* @param cArgs Number of arguments in the array.
3525	*/
3526	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3527	{
3528	/*
3529	* Validate input.
3530	*/
3531	if (!pVM)
3532	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3533	if (!pVM->pgm.s.pRamRangesGC)
3534	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3535
3536	/*
3537	* Dump the ranges.
3538	*/
3539	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3540	PPGMRAMRANGE pRam;
3541	for (pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
3542	{
3543	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3544	"%VGp - %VGp %p\n",
3545	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3546	if (VBOX_FAILURE(rc))
3547	return rc;
3548	}
3549
3550	return VINF_SUCCESS;
3551	}
3552
3553
3554	/**
3555	* The '.pgmmap' command.
3556	*
3557	* @returns VBox status.
3558	* @param pCmd Pointer to the command descriptor (as registered).
3559	* @param pCmdHlp Pointer to command helper functions.
3560	* @param pVM Pointer to the current VM (if any).
3561	* @param paArgs Pointer to (readonly) array of arguments.
3562	* @param cArgs Number of arguments in the array.
3563	*/
3564	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3565	{
3566	/*
3567	* Validate input.
3568	*/
3569	if (!pVM)
3570	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3571	if (!pVM->pgm.s.pMappingsR3)
3572	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3573
3574	/*
3575	* Print message about the fixedness of the mappings.
3576	*/
3577	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3578	if (VBOX_FAILURE(rc))
3579	return rc;
3580
3581	/*
3582	* Dump the ranges.
3583	*/
3584	PPGMMAPPING pCur;
3585	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
3586	{
3587	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3588	"%08x - %08x %s\n",
3589	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3590	if (VBOX_FAILURE(rc))
3591	return rc;
3592	}
3593
3594	return VINF_SUCCESS;
3595	}
3596
3597
3598	/**
3599	* The '.pgmsync' command.
3600	*
3601	* @returns VBox status.
3602	* @param pCmd Pointer to the command descriptor (as registered).
3603	* @param pCmdHlp Pointer to command helper functions.
3604	* @param pVM Pointer to the current VM (if any).
3605	* @param paArgs Pointer to (readonly) array of arguments.
3606	* @param cArgs Number of arguments in the array.
3607	*/
3608	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3609	{
3610	/*
3611	* Validate input.
3612	*/
3613	if (!pVM)
3614	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3615
3616	/*
3617	* Force page directory sync.
3618	*/
3619	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3620
3621	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3622	if (VBOX_FAILURE(rc))
3623	return rc;
3624
3625	return VINF_SUCCESS;
3626	}
3627
3628
3629	/**
3630	* The '.pgmsyncalways' command.
3631	*
3632	* @returns VBox status.
3633	* @param pCmd Pointer to the command descriptor (as registered).
3634	* @param pCmdHlp Pointer to command helper functions.
3635	* @param pVM Pointer to the current VM (if any).
3636	* @param paArgs Pointer to (readonly) array of arguments.
3637	* @param cArgs Number of arguments in the array.
3638	*/
3639	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3640	{
3641	/*
3642	* Validate input.
3643	*/
3644	if (!pVM)
3645	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3646
3647	/*
3648	* Force page directory sync.
3649	*/
3650	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3651	{
3652	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3653	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3654	}
3655	else
3656	{
3657	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3658	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3659	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3660	}
3661	}
3662
3663	#endif
3664
3665	/**
3666	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3667	*/
3668	typedef struct PGMCHECKINTARGS
3669	{
3670	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3671	PPGMPHYSHANDLER pPrevPhys;
3672	PPGMVIRTHANDLER pPrevVirt;
3673	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3674	PVM pVM;
3675	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3676
3677	/**
3678	* Validate a node in the physical handler tree.
3679	*
3680	* @returns 0 on if ok, other wise 1.
3681	* @param pNode The handler node.
3682	* @param pvUser pVM.
3683	*/
3684	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3685	{
3686	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3687	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3688	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3689	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3690	AssertReleaseMsg( !pArgs->pPrevPhys
3691	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3692	("pPrevPhys=%p %VGp-%VGp %s\n"
3693	" pCur=%p %VGp-%VGp %s\n",
3694	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3695	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3696	pArgs->pPrevPhys = pCur;
3697	return 0;
3698	}
3699
3700
3701	/**
3702	* Validate a node in the virtual handler tree.
3703	*
3704	* @returns 0 on if ok, other wise 1.
3705	* @param pNode The handler node.
3706	* @param pvUser pVM.
3707	*/
3708	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
3709	{
3710	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3711	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
3712	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3713	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3714	AssertReleaseMsg( !pArgs->pPrevVirt
3715	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
3716	("pPrevVirt=%p %VGv-%VGv %s\n"
3717	" pCur=%p %VGv-%VGv %s\n",
3718	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
3719	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3720	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
3721	{
3722	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
3723	("pCur=%p %VGv-%VGv %s\n"
3724	"iPage=%d offVirtHandle=%#x expected %#x\n",
3725	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
3726	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
3727	}
3728	pArgs->pPrevVirt = pCur;
3729	return 0;
3730	}
3731
3732
3733	/**
3734	* Validate a node in the virtual handler tree.
3735	*
3736	* @returns 0 on if ok, other wise 1.
3737	* @param pNode The handler node.
3738	* @param pvUser pVM.
3739	*/
3740	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3741	{
3742	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3743	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
3744	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
3745	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
3746	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
3747	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3748	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3749	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3750	" pCur=%p %VGp-%VGp\n",
3751	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3752	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3753	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3754	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3755	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3756	" pCur=%p %VGp-%VGp\n",
3757	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3758	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3759	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
3760	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3761	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3762	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3763	{
3764	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
3765	for (;;)
3766	{
3767	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3768	AssertReleaseMsg(pCur2 != pCur,
3769	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3770	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3771	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
3772	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3773	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3774	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3775	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3776	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
3777	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3778	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3779	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3780	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3781	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
3782	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3783	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3784	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3785	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3786	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3787	break;
3788	}
3789	}
3790
3791	pArgs->pPrevPhys2Virt = pCur;
3792	return 0;
3793	}
3794
3795
3796	/**
3797	* Perform an integrity check on the PGM component.
3798	*
3799	* @returns VINF_SUCCESS if everything is fine.
3800	* @returns VBox error status after asserting on integrity breach.
3801	* @param pVM The VM handle.
3802	*/
3803	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
3804	{
3805	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
3806
3807	/*
3808	* Check the trees.
3809	*/
3810	int cErrors = 0;
3811	PGMCHECKINTARGS Args = { true, NULL, NULL, NULL, pVM };
3812	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3813	Args.fLeftToRight = false;
3814	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3815	Args.fLeftToRight = true;
3816	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3817	Args.fLeftToRight = false;
3818	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3819	Args.fLeftToRight = true;
3820	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3821	Args.fLeftToRight = false;
3822	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3823
3824	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
3825	}
3826
3827
3828	/**
3829	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
3830	*
3831	* @returns VBox status code.
3832	* @param pVM VM handle.
3833	* @param fEnable Enable or disable shadow mappings
3834	*/
3835	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
3836	{
3837	pVM->pgm.s.fDisableMappings = !fEnable;
3838
3839	size_t cb;
3840	int rc = PGMR3MappingsSize(pVM, &cb);
3841	AssertRCReturn(rc, rc);
3842
3843	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
3844	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
3845	AssertRCReturn(rc, rc);
3846
3847	return VINF_SUCCESS;
3848	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 5605

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