VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 9453

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1/* $Id: HWACCMInternal.h 9453 2008-06-06 09:28:02Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <iprt/memobj.h>
33#include <iprt/cpuset.h>
34#include <iprt/mp.h>
35
36/* Uncomment to enable experimental nested paging. */
37//#define VBOX_WITH_NESTED_PAGING
38/* Uncomment to enable 64 bits guest support. */
39//#define VBOX_ENABLE_64_BITS_GUESTS
40
41__BEGIN_DECLS
42
43
44/** @defgroup grp_hwaccm_int Internal
45 * @ingroup grp_hwaccm
46 * @internal
47 * @{
48 */
49
50
51/**
52 * Converts a HWACCM pointer into a VM pointer.
53 * @returns Pointer to the VM structure the EM is part of.
54 * @param pHWACCM Pointer to HWACCM instance data.
55 */
56#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
57
58/** Maximum number of exit reason statistics counters. */
59#define MAX_EXITREASON_STAT 0x100
60#define MASK_EXITREASON_STAT 0xff
61
62/** @name Changed flags
63 * These flags are used to keep track of which important registers that
64 * have been changed since last they were reset.
65 * @{
66 */
67#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
68#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
69#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
70#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
71#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
72#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
73#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
74#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
75#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
76#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
77#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
78#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
79
80#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
81 | HWACCM_CHANGED_GUEST_CR0 \
82 | HWACCM_CHANGED_GUEST_CR3 \
83 | HWACCM_CHANGED_GUEST_CR4 \
84 | HWACCM_CHANGED_GUEST_GDTR \
85 | HWACCM_CHANGED_GUEST_IDTR \
86 | HWACCM_CHANGED_GUEST_LDTR \
87 | HWACCM_CHANGED_GUEST_TR \
88 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
89 | HWACCM_CHANGED_GUEST_FPU \
90 | HWACCM_CHANGED_GUEST_DEBUG \
91 | HWACCM_CHANGED_HOST_CONTEXT)
92
93#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
94 | HWACCM_CHANGED_GUEST_CR0 \
95 | HWACCM_CHANGED_GUEST_CR3 \
96 | HWACCM_CHANGED_GUEST_CR4 \
97 | HWACCM_CHANGED_GUEST_GDTR \
98 | HWACCM_CHANGED_GUEST_IDTR \
99 | HWACCM_CHANGED_GUEST_LDTR \
100 | HWACCM_CHANGED_GUEST_TR \
101 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
102 | HWACCM_CHANGED_GUEST_DEBUG \
103 | HWACCM_CHANGED_GUEST_FPU)
104
105/** @} */
106
107/** @name Intercepted traps
108 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
109 * Currently #NM and #PF only
110 */
111#ifdef VBOX_STRICT
112#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
113#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
114#else
115#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
116#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
117#endif
118/** @} */
119
120
121/** Maxium resume loops allowed in ring 0 (safety precaution) */
122#define HWACCM_MAX_RESUME_LOOPS 1024
123
124/** HWACCM SSM version
125 */
126#define HWACCM_SSM_VERSION 3
127
128/* Per-cpu information. */
129typedef struct
130{
131 RTCPUID idCpu;
132
133 RTR0MEMOBJ pMemObj;
134 /* Current ASID (AMD-V only) */
135 uint32_t uCurrentASID;
136 /* TLB flush count */
137 uint32_t cTLBFlushes;
138
139 bool fConfigured;
140} HWACCM_CPUINFO;
141typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
142
143/**
144 * HWACCM VM Instance data.
145 * Changes to this must checked against the padding of the cfgm union in VM!
146 */
147typedef struct HWACCM
148{
149 /** Offset to the VM structure.
150 * See HWACCM2VM(). */
151 RTUINT offVM;
152
153 /** Set when we've initialized VMX or SVM. */
154 bool fInitialized;
155 /** Set when we're using VMX/SVN at that moment. */
156 bool fActive;
157
158 /** Set when hardware acceleration is allowed. */
159 bool fAllowed;
160
161 /** Set if nested paging is enabled. */
162 bool fNestedPaging;
163
164 /** HWACCM_CHANGED_* flags. */
165 uint32_t fContextUseFlags;
166
167 /** Old style FPU reporting trap mask override performed (optimization) */
168 uint32_t fFPUOldStyleOverride;
169
170 /** And mask for copying register contents. */
171 uint64_t u64RegisterMask;
172 struct
173 {
174 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
175 bool fSupported;
176
177 /** Set when we've enabled VMX. */
178 bool fEnabled;
179
180 /** Set if we can use VMXResume to execute guest code. */
181 bool fResumeVM;
182
183 /** R0 memory object for the VM control structure (VMCS). */
184 RTR0MEMOBJ pMemObjVMCS;
185 /** Physical address of the VM control structure (VMCS). */
186 RTHCPHYS pVMCSPhys;
187 /** Virtual address of the VM control structure (VMCS). */
188 R0PTRTYPE(void *) pVMCS;
189
190 /** R0 memory object for the TSS page used for real mode emulation. */
191 RTR0MEMOBJ pMemObjRealModeTSS;
192 /** Physical address of the TSS page used for real mode emulation. */
193 RTHCPHYS pRealModeTSSPhys;
194 /** Virtual address of the TSS page used for real mode emulation. */
195 R0PTRTYPE(PVBOXTSS) pRealModeTSS;
196
197 /** Host CR4 value (set by ring-0 VMX init) */
198 uint64_t hostCR4;
199
200 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
201 uint64_t proc_ctls;
202
203 /** Current CR0 mask. */
204 uint64_t cr0_mask;
205 /** Current CR4 mask. */
206 uint64_t cr4_mask;
207
208 /** VMX MSR values */
209 struct
210 {
211 uint64_t feature_ctrl;
212 uint64_t vmx_basic_info;
213 uint64_t vmx_pin_ctls;
214 uint64_t vmx_proc_ctls;
215 uint64_t vmx_exit;
216 uint64_t vmx_entry;
217 uint64_t vmx_misc;
218 uint64_t vmx_cr0_fixed0;
219 uint64_t vmx_cr0_fixed1;
220 uint64_t vmx_cr4_fixed0;
221 uint64_t vmx_cr4_fixed1;
222 uint64_t vmx_vmcs_enum;
223 } msr;
224
225 /* Last instruction error */
226 uint32_t ulLastInstrError;
227 } vmx;
228
229 struct
230 {
231 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
232 bool fSupported;
233 /** Set when we've enabled SVM. */
234 bool fEnabled;
235 /** Set if we don't have to flush the TLB on VM entry. */
236 bool fResumeVM;
237 /** Set if erratum 170 affects the AMD cpu. */
238 bool fAlwaysFlushTLB;
239 /** Set if we need to flush the TLB during the world switch. */
240 bool fForceTLBFlush;
241
242 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
243 RTCPUID idLastCpu;
244
245 /* TLB flush count */
246 uint32_t cTLBFlushes;
247
248 /** R0 memory object for the VM control block (VMCB). */
249 RTR0MEMOBJ pMemObjVMCB;
250 /** Physical address of the VM control block (VMCB). */
251 RTHCPHYS pVMCBPhys;
252 /** Virtual address of the VM control block (VMCB). */
253 R0PTRTYPE(void *) pVMCB;
254
255 /** R0 memory object for the host VM control block (VMCB). */
256 RTR0MEMOBJ pMemObjVMCBHost;
257 /** Physical address of the host VM control block (VMCB). */
258 RTHCPHYS pVMCBHostPhys;
259 /** Virtual address of the host VM control block (VMCB). */
260 R0PTRTYPE(void *) pVMCBHost;
261
262 /** R0 memory object for the IO bitmap (12kb). */
263 RTR0MEMOBJ pMemObjIOBitmap;
264 /** Physical address of the IO bitmap (12kb). */
265 RTHCPHYS pIOBitmapPhys;
266 /** Virtual address of the IO bitmap. */
267 R0PTRTYPE(void *) pIOBitmap;
268
269 /** R0 memory object for the MSR bitmap (8kb). */
270 RTR0MEMOBJ pMemObjMSRBitmap;
271 /** Physical address of the MSR bitmap (8kb). */
272 RTHCPHYS pMSRBitmapPhys;
273 /** Virtual address of the MSR bitmap. */
274 R0PTRTYPE(void *) pMSRBitmap;
275
276 /** SVM revision. */
277 uint32_t u32Rev;
278
279 /** Maximum ASID allowed. */
280 uint32_t u32MaxASID;
281
282 /** SVM feature bits from cpuid 0x8000000a */
283 uint32_t u32Features;
284 } svm;
285
286 struct
287 {
288 uint32_t u32AMDFeatureECX;
289 uint32_t u32AMDFeatureEDX;
290 } cpuid;
291
292 /* Event injection state. */
293 struct
294 {
295 uint32_t fPending;
296 uint32_t errCode;
297 uint64_t intInfo;
298 } Event;
299
300 /** Saved error from detection */
301 int32_t lLastError;
302
303 /** HWACCMR0Init was run */
304 bool fHWACCMR0Init;
305
306 /** Currenty shadow paging mode. */
307 PGMMODE enmShadowMode;
308
309 STAMPROFILEADV StatEntry;
310 STAMPROFILEADV StatExit;
311 STAMPROFILEADV StatInGC;
312
313 STAMCOUNTER StatIntInject;
314
315 STAMCOUNTER StatExitShadowNM;
316 STAMCOUNTER StatExitGuestNM;
317 STAMCOUNTER StatExitShadowPF;
318 STAMCOUNTER StatExitGuestPF;
319 STAMCOUNTER StatExitGuestUD;
320 STAMCOUNTER StatExitGuestSS;
321 STAMCOUNTER StatExitGuestNP;
322 STAMCOUNTER StatExitGuestGP;
323 STAMCOUNTER StatExitGuestDE;
324 STAMCOUNTER StatExitGuestMF;
325 STAMCOUNTER StatExitInvpg;
326 STAMCOUNTER StatExitInvd;
327 STAMCOUNTER StatExitCpuid;
328 STAMCOUNTER StatExitRdtsc;
329 STAMCOUNTER StatExitCRxWrite;
330 STAMCOUNTER StatExitCRxRead;
331 STAMCOUNTER StatExitDRxWrite;
332 STAMCOUNTER StatExitDRxRead;
333 STAMCOUNTER StatExitCLTS;
334 STAMCOUNTER StatExitLMSW;
335 STAMCOUNTER StatExitIOWrite;
336 STAMCOUNTER StatExitIORead;
337 STAMCOUNTER StatExitIOStringWrite;
338 STAMCOUNTER StatExitIOStringRead;
339 STAMCOUNTER StatExitIrqWindow;
340 STAMCOUNTER StatExitMaxResume;
341 STAMCOUNTER StatIntReinject;
342 STAMCOUNTER StatPendingHostIrq;
343
344 STAMCOUNTER StatFlushPageManual;
345 STAMCOUNTER StatFlushPhysPageManual;
346 STAMCOUNTER StatFlushTLBManual;
347 STAMCOUNTER StatFlushPageInvlpg;
348 STAMCOUNTER StatFlushTLBWorldSwitch;
349 STAMCOUNTER StatNoFlushTLBWorldSwitch;
350 STAMCOUNTER StatFlushTLBCRxChange;
351 STAMCOUNTER StatFlushASID;
352
353 STAMCOUNTER StatSwitchGuestIrq;
354 STAMCOUNTER StatSwitchToR3;
355
356 STAMCOUNTER StatTSCOffset;
357 STAMCOUNTER StatTSCIntercept;
358
359 STAMCOUNTER StatExitReasonNPF;
360 R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
361 R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
362} HWACCM;
363/** Pointer to HWACCM VM instance data. */
364typedef HWACCM *PHWACCM;
365
366#ifdef IN_RING0
367
368#ifdef VBOX_STRICT
369HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
370HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
371#else
372#define HWACCMDumpRegs(a) do { } while (0)
373#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
374#endif
375
376/* Dummy callback handlers. */
377HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
378HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM);
379HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
380HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
381HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
382HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
383HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
384HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu);
385HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
386HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
387
388#endif
389
390/** @} */
391
392__END_DECLS
393
394#endif
395
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