VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 7392

Last change on this file since 7392 was 5999, checked in by vboxsync, 17 years ago

The Giant CDDL Dual-License Header Change.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 11.7 KB
Line 
1/* $Id: HWACCMInternal.h 5999 2007-12-07 15:05:06Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HWACCMInternal_h
19#define ___HWACCMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/em.h>
24#include <VBox/stam.h>
25#include <VBox/dis.h>
26#include <VBox/hwaccm.h>
27#include <VBox/pgm.h>
28
29__BEGIN_DECLS
30
31
32/** @defgroup grp_hwaccm_int Internal
33 * @ingroup grp_hwaccm
34 * @internal
35 * @{
36 */
37
38
39/**
40 * Converts a HWACCM pointer into a VM pointer.
41 * @returns Pointer to the VM structure the EM is part of.
42 * @param pHWACCM Pointer to HWACCM instance data.
43 */
44#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
45
46/** Maximum number of exit reason statistics counters. */
47#define MAX_EXITREASON_STAT 0x100
48#define MASK_EXITREASON_STAT 0xff
49
50/** @name Changed flags
51 * These flags are used to keep track of which important registers that
52 * have been changed since last they were reset.
53 * @{
54 */
55#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
56#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
57#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
58#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
59#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
60#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
61#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
62#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
63#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
64#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
65#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
66#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
67
68#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
69 | HWACCM_CHANGED_GUEST_CR0 \
70 | HWACCM_CHANGED_GUEST_CR3 \
71 | HWACCM_CHANGED_GUEST_CR4 \
72 | HWACCM_CHANGED_GUEST_GDTR \
73 | HWACCM_CHANGED_GUEST_IDTR \
74 | HWACCM_CHANGED_GUEST_LDTR \
75 | HWACCM_CHANGED_GUEST_TR \
76 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
77 | HWACCM_CHANGED_GUEST_FPU \
78 | HWACCM_CHANGED_GUEST_DEBUG \
79 | HWACCM_CHANGED_HOST_CONTEXT)
80
81#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
82 | HWACCM_CHANGED_GUEST_CR0 \
83 | HWACCM_CHANGED_GUEST_CR3 \
84 | HWACCM_CHANGED_GUEST_CR4 \
85 | HWACCM_CHANGED_GUEST_GDTR \
86 | HWACCM_CHANGED_GUEST_IDTR \
87 | HWACCM_CHANGED_GUEST_LDTR \
88 | HWACCM_CHANGED_GUEST_TR \
89 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
90 | HWACCM_CHANGED_GUEST_DEBUG \
91 | HWACCM_CHANGED_GUEST_FPU)
92
93/** @} */
94
95/** @name Intercepted traps
96 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
97 * Currently #NM and #PF only
98 */
99#ifdef VBOX_STRICT
100#define HWACCM_VMX_TRAP_MASK RT_BIT(0) | RT_BIT(7) | RT_BIT(14) | RT_BIT(6) | RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(16)
101#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
102#else
103#define HWACCM_VMX_TRAP_MASK RT_BIT(7) | RT_BIT(14)
104#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
105#endif
106/** @} */
107
108
109/** Maxium resume loops allowed in ring 0 (safety precaution) */
110#define HWACCM_MAX_RESUME_LOOPS 1024
111
112/** HWACCM SSM version
113 */
114#define HWACCM_SSM_VERSION 3
115
116/**
117 * HWACCM VM Instance data.
118 * Changes to this must checked against the padding of the cfgm union in VM!
119 */
120typedef struct HWACCM
121{
122 /** Offset to the VM structure.
123 * See HWACCM2VM(). */
124 RTUINT offVM;
125
126 /** Set when we've initialized VMX or SVM. */
127 bool fInitialized;
128 /** Set when we're using VMX/SVN at that moment. */
129 bool fActive;
130
131 /** Set when hardware acceleration is allowed. */
132 bool fAllowed;
133
134 /** HWACCM_CHANGED_* flags. */
135 uint32_t fContextUseFlags;
136
137 /** Old style FPU reporting trap mask override performed (optimization) */
138 uint32_t fFPUOldStyleOverride;
139
140 struct
141 {
142 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
143 bool fSupported;
144
145 /** Set when we've enabled VMX. */
146 bool fEnabled;
147
148 /** Set if we can use VMXResume to execute guest code. */
149 bool fResumeVM;
150
151 /** Physical address of the VM control structure (VMCS). */
152 RTHCPHYS pVMCSPhys;
153 /** Virtual address of the VM control structure (VMCS). */
154 void *pVMCS;
155
156 /** Physical address of the VMXON page. */
157 RTHCPHYS pVMXONPhys;
158 /** Virtual address of the VMXON page. */
159 void *pVMXON;
160
161 /** Physical address of the TSS page used for real mode emulation. */
162 RTHCPHYS pRealModeTSSPhys;
163 /** Virtual address of the TSS page used for real mode emulation. */
164 PVBOXTSS pRealModeTSS;
165
166 /** Host CR4 value (set by ring-0 VMX init) */
167 uint32_t hostCR4;
168
169 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
170 uint64_t proc_ctls;
171
172 /** Current CR0 mask. */
173 uint64_t cr0_mask;
174 /** Current CR4 mask. */
175 uint64_t cr4_mask;
176
177 /** VMX MSR values */
178 struct
179 {
180 uint64_t feature_ctrl;
181 uint64_t vmx_basic_info;
182 uint64_t vmx_pin_ctls;
183 uint64_t vmx_proc_ctls;
184 uint64_t vmx_exit;
185 uint64_t vmx_entry;
186 uint64_t vmx_misc;
187 uint64_t vmx_cr0_fixed0;
188 uint64_t vmx_cr0_fixed1;
189 uint64_t vmx_cr4_fixed0;
190 uint64_t vmx_cr4_fixed1;
191 uint64_t vmx_vmcs_enum;
192 } msr;
193
194 /* Last instruction error */
195 uint32_t ulLastInstrError;
196 } vmx;
197
198 struct
199 {
200 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
201 bool fSupported;
202
203 /** Set when we've enabled SVM. */
204 bool fEnabled;
205
206 /** Set if we don't have to flush the TLB on VM entry. */
207 bool fResumeVM;
208
209 /** Physical address of the VM control block (VMCB). */
210 RTHCPHYS pVMCBPhys;
211 /** Virtual address of the VM control block (VMCB). */
212 void *pVMCB;
213
214 /** Physical address of the host VM control block (VMCB). */
215 RTHCPHYS pVMCBHostPhys;
216 /** Virtual address of the host VM control block (VMCB). */
217 void *pVMCBHost;
218
219 /** Physical address of the Host State page. */
220 RTHCPHYS pHStatePhys;
221 /** Virtual address of the Host State page. */
222 void *pHState;
223
224 /** Physical address of the IO bitmap (12kb). */
225 RTHCPHYS pIOBitmapPhys;
226 /** Virtual address of the IO bitmap. */
227 void *pIOBitmap;
228
229 /** Physical address of the MSR bitmap (8kb). */
230 RTHCPHYS pMSRBitmapPhys;
231 /** Virtual address of the MSR bitmap. */
232 void *pMSRBitmap;
233
234 /** SVM revision. */
235 uint32_t u32Rev;
236
237 /** Maximum ASID allowed. */
238 uint32_t u32MaxASID;
239 } svm;
240
241 struct
242 {
243 uint32_t u32AMDFeatureECX;
244 uint32_t u32AMDFeatureEDX;
245 } cpuid;
246
247 /* Event injection state. */
248 struct
249 {
250 uint32_t fPending;
251 uint32_t errCode;
252 uint64_t intInfo;
253 } Event;
254
255 /** Saved error from detection */
256 int32_t lLastError;
257
258 /** HWACCMR0Init was run */
259 bool fHWACCMR0Init;
260
261 /** Currenty shadow paging mode. */
262 PGMMODE enmShadowMode;
263
264 STAMPROFILEADV StatEntry;
265 STAMPROFILEADV StatExit;
266 STAMPROFILEADV StatInGC;
267
268 STAMCOUNTER StatIntInject;
269
270 STAMCOUNTER StatExitShadowNM;
271 STAMCOUNTER StatExitGuestNM;
272 STAMCOUNTER StatExitShadowPF;
273 STAMCOUNTER StatExitGuestPF;
274 STAMCOUNTER StatExitGuestUD;
275 STAMCOUNTER StatExitGuestSS;
276 STAMCOUNTER StatExitGuestNP;
277 STAMCOUNTER StatExitGuestGP;
278 STAMCOUNTER StatExitGuestDE;
279 STAMCOUNTER StatExitGuestMF;
280 STAMCOUNTER StatExitInvpg;
281 STAMCOUNTER StatExitInvd;
282 STAMCOUNTER StatExitCpuid;
283 STAMCOUNTER StatExitRdtsc;
284 STAMCOUNTER StatExitCRxWrite;
285 STAMCOUNTER StatExitCRxRead;
286 STAMCOUNTER StatExitDRxWrite;
287 STAMCOUNTER StatExitDRxRead;
288 STAMCOUNTER StatExitCLTS;
289 STAMCOUNTER StatExitLMSW;
290 STAMCOUNTER StatExitIOWrite;
291 STAMCOUNTER StatExitIORead;
292 STAMCOUNTER StatExitIOStringWrite;
293 STAMCOUNTER StatExitIOStringRead;
294 STAMCOUNTER StatExitIrqWindow;
295 STAMCOUNTER StatExitMaxResume;
296 STAMCOUNTER StatIntReinject;
297 STAMCOUNTER StatPendingHostIrq;
298
299 STAMCOUNTER StatSwitchGuestIrq;
300 STAMCOUNTER StatSwitchToR3;
301
302 R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
303 R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
304} HWACCM;
305/** Pointer to HWACCM VM instance data. */
306typedef HWACCM *PHWACCM;
307
308
309#ifdef IN_RING0
310
311#ifdef VBOX_STRICT
312HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
313HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
314#else
315#define HWACCMDumpRegs(a) do { } while (0)
316#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
317#endif
318
319#endif
320
321/** @} */
322
323__END_DECLS
324
325#endif
326
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette