HWACCMInternal.h@ 20961

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1	/* $Id: HWACCMInternal.h 20838 2009-06-23 14:15:46Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define VMX_USE_CACHED_VMCS_ACCESSES
43	#define HWACCM_VMX_EMULATE_REALMODE
44	#define HWACCM_VTX_WITH_EPT
45	#define HWACCM_VTX_WITH_VPID
46
47	RT_C_DECLS_BEGIN
48
49
50	/** @defgroup grp_hwaccm_int Internal
51	* @ingroup grp_hwaccm
52	* @internal
53	* @{
54	*/
55
56
57	/** Maximum number of exit reason statistics counters. */
58	#define MAX_EXITREASON_STAT 0x100
59	#define MASK_EXITREASON_STAT 0xff
60	#define MASK_INJECT_IRQ_STAT 0xff
61
62	/** @name Changed flags
63	* These flags are used to keep track of which important registers that
64	* have been changed since last they were reset.
65	* @{
66	*/
67	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
68	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
69	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
70	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
71	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
72	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
73	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
74	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
75	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
76	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
77	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
78	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
79
80	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
81	\| HWACCM_CHANGED_GUEST_CR0 \
82	\| HWACCM_CHANGED_GUEST_CR3 \
83	\| HWACCM_CHANGED_GUEST_CR4 \
84	\| HWACCM_CHANGED_GUEST_GDTR \
85	\| HWACCM_CHANGED_GUEST_IDTR \
86	\| HWACCM_CHANGED_GUEST_LDTR \
87	\| HWACCM_CHANGED_GUEST_TR \
88	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
89	\| HWACCM_CHANGED_GUEST_FPU \
90	\| HWACCM_CHANGED_GUEST_DEBUG \
91	\| HWACCM_CHANGED_HOST_CONTEXT)
92
93	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
94	\| HWACCM_CHANGED_GUEST_CR0 \
95	\| HWACCM_CHANGED_GUEST_CR3 \
96	\| HWACCM_CHANGED_GUEST_CR4 \
97	\| HWACCM_CHANGED_GUEST_GDTR \
98	\| HWACCM_CHANGED_GUEST_IDTR \
99	\| HWACCM_CHANGED_GUEST_LDTR \
100	\| HWACCM_CHANGED_GUEST_TR \
101	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
102	\| HWACCM_CHANGED_GUEST_DEBUG \
103	\| HWACCM_CHANGED_GUEST_FPU)
104
105	/** @} */
106
107	/** @name Intercepted traps
108	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
109	* Currently #NM and #PF only
110	*/
111	#ifdef VBOX_STRICT
112	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
113	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
114	#else
115	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
117	#endif
118	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
119	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
120	/** @} */
121
122
123	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
124	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
125
126	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
127	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
128	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
129	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
130	/** Total guest mapped memory needed. */
131	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
132
133	/** HWACCM SSM version
134	*/
135	#define HWACCM_SSM_VERSION 4
136	#define HWACCM_SSM_VERSION_2_0_X 3
137
138	/* Per-cpu information. (host) */
139	typedef struct
140	{
141	RTCPUID idCpu;
142
143	RTR0MEMOBJ pMemObj;
144	/* Current ASID (AMD-V)/VPID (Intel) */
145	uint32_t uCurrentASID;
146	/* TLB flush count */
147	uint32_t cTLBFlushes;
148
149	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
150	bool fFlushTLB;
151
152	/** Configured for VT-x or AMD-V. */
153	bool fConfigured;
154
155	/** In use by our code. (for power suspend) */
156	volatile bool fInUse;
157	} HWACCM_CPUINFO;
158	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
159
160	/* VT-x capability qword. */
161	typedef union
162	{
163	struct
164	{
165	uint32_t disallowed0;
166	uint32_t allowed1;
167	} n;
168	uint64_t u;
169	} VMX_CAPABILITY;
170
171	/**
172	* Switcher function, HC to RC.
173	*
174	* @param pVM The VM handle.
175	* @returns Return code indicating the action to take.
176	*/
177	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
178	/** Pointer to switcher function. */
179	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
180
181	/**
182	* HWACCM VM Instance data.
183	* Changes to this must checked against the padding of the cfgm union in VM!
184	*/
185	typedef struct HWACCM
186	{
187	/** Set when we've initialized VMX or SVM. */
188	bool fInitialized;
189
190	/** Set when hardware acceleration is allowed. */
191	bool fAllowed;
192
193	/** Set if nested paging is enabled. */
194	bool fNestedPaging;
195
196	/** Set if nested paging is allowed. */
197	bool fAllowNestedPaging;
198
199	/** Set if we can support 64-bit guests or not. */
200	bool fAllow64BitGuests;
201
202	/** Set if an IO-APIC is configured for this VM. */
203	bool fHasIoApic;
204
205	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
206	* naturally. */
207	bool padding[2];
208
209	/** And mask for copying register contents. */
210	uint64_t u64RegisterMask;
211
212	/** Maximum ASID allowed. */
213	RTUINT uMaxASID;
214
215	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
216	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
217	uint32_t cMaxResumeLoops;
218
219	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
220	/** 32 to 64 bits switcher entrypoint. */
221	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
222
223	/* AMD-V 64 bits vmrun handler */
224	RTRCPTR pfnSVMGCVMRun64;
225
226	/* VT-x 64 bits vmlaunch handler */
227	RTRCPTR pfnVMXGCStartVM64;
228
229	/* RC handler to setup the 64 bits FPU state. */
230	RTRCPTR pfnSaveGuestFPU64;
231
232	/* RC handler to setup the 64 bits debug state. */
233	RTRCPTR pfnSaveGuestDebug64;
234
235	/* Test handler */
236	RTRCPTR pfnTest64;
237
238	RTRCPTR uAlignment[2];
239	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
240	uint32_t u32Alignment[1]; */
241	#endif
242
243	struct
244	{
245	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
246	bool fSupported;
247
248	/** Set when we've enabled VMX. */
249	bool fEnabled;
250
251	/** Set if VPID is supported. */
252	bool fVPID;
253
254	/** Set if VT-x VPID is allowed. */
255	bool fAllowVPID;
256
257	/** Virtual address of the TSS page used for real mode emulation. */
258	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
259
260	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
261	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
262
263	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
264	RTR0MEMOBJ pMemObjAPIC;
265	/** Physical address of the APIC physical page (serves for filtering accesses). */
266	RTHCPHYS pAPICPhys;
267	/** Virtual address of the APIC physical page (serves for filtering accesses). */
268	R0PTRTYPE(uint8_t *) pAPIC;
269
270	/** R0 memory object for the MSR bitmap (1 page). */
271	RTR0MEMOBJ pMemObjMSRBitmap;
272	/** Physical address of the MSR bitmap (1 page). */
273	RTHCPHYS pMSRBitmapPhys;
274	/** Virtual address of the MSR bitmap (1 page). */
275	R0PTRTYPE(uint8_t *) pMSRBitmap;
276
277	/** R0 memory object for the MSR entry load page (guest MSRs). */
278	RTR0MEMOBJ pMemObjMSREntryLoad;
279	/** Physical address of the MSR entry load page (guest MSRs). */
280	RTHCPHYS pMSREntryLoadPhys;
281	/** Virtual address of the MSR entry load page (guest MSRs). */
282	R0PTRTYPE(uint8_t *) pMSREntryLoad;
283
284	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
285	RTR0MEMOBJ pMemObjScratch;
286	RTHCPHYS pScratchPhys;
287	R0PTRTYPE(uint8_t *) pScratch;
288	#endif
289	/** R0 memory object for the MSR exit store page (guest MSRs). */
290	RTR0MEMOBJ pMemObjMSRExitStore;
291	/** Physical address of the MSR exit store page (guest MSRs). */
292	RTHCPHYS pMSRExitStorePhys;
293	/** Virtual address of the MSR exit store page (guest MSRs). */
294	R0PTRTYPE(uint8_t *) pMSRExitStore;
295
296	/** R0 memory object for the MSR exit load page (host MSRs). */
297	RTR0MEMOBJ pMemObjMSRExitLoad;
298	/** Physical address of the MSR exit load page (host MSRs). */
299	RTHCPHYS pMSRExitLoadPhys;
300	/** Virtual address of the MSR exit load page (host MSRs). */
301	R0PTRTYPE(uint8_t *) pMSRExitLoad;
302
303	/** Ring 0 handlers for VT-x. */
304	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
305
306	/** Host CR4 value (set by ring-0 VMX init) */
307	uint64_t hostCR4;
308
309	/** VMX MSR values */
310	struct
311	{
312	uint64_t feature_ctrl;
313	uint64_t vmx_basic_info;
314	VMX_CAPABILITY vmx_pin_ctls;
315	VMX_CAPABILITY vmx_proc_ctls;
316	VMX_CAPABILITY vmx_proc_ctls2;
317	VMX_CAPABILITY vmx_exit;
318	VMX_CAPABILITY vmx_entry;
319	uint64_t vmx_misc;
320	uint64_t vmx_cr0_fixed0;
321	uint64_t vmx_cr0_fixed1;
322	uint64_t vmx_cr4_fixed0;
323	uint64_t vmx_cr4_fixed1;
324	uint64_t vmx_vmcs_enum;
325	uint64_t vmx_eptcaps;
326	} msr;
327
328	/** Flush types for invept & invvpid; they depend on capabilities. */
329	VMX_FLUSH enmFlushPage;
330	VMX_FLUSH enmFlushContext;
331	} vmx;
332
333	struct
334	{
335	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
336	bool fSupported;
337	/** Set when we've enabled SVM. */
338	bool fEnabled;
339	/** Set if erratum 170 affects the AMD cpu. */
340	bool fAlwaysFlushTLB;
341	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
342	* naturally. */
343	bool padding[1];
344
345	/** R0 memory object for the IO bitmap (12kb). */
346	RTR0MEMOBJ pMemObjIOBitmap;
347	/** Physical address of the IO bitmap (12kb). */
348	RTHCPHYS pIOBitmapPhys;
349	/** Virtual address of the IO bitmap. */
350	R0PTRTYPE(void *) pIOBitmap;
351
352	/** R0 memory object for the MSR bitmap (8kb). */
353	RTR0MEMOBJ pMemObjMSRBitmap;
354	/** Physical address of the MSR bitmap (8kb). */
355	RTHCPHYS pMSRBitmapPhys;
356	/** Virtual address of the MSR bitmap. */
357	R0PTRTYPE(void *) pMSRBitmap;
358
359	/** SVM revision. */
360	uint32_t u32Rev;
361
362	/** SVM feature bits from cpuid 0x8000000a */
363	uint32_t u32Features;
364	} svm;
365
366	struct
367	{
368	uint32_t u32AMDFeatureECX;
369	uint32_t u32AMDFeatureEDX;
370	} cpuid;
371
372	/** Saved error from detection */
373	int32_t lLastError;
374
375	/** HWACCMR0Init was run */
376	bool fHWACCMR0Init;
377	} HWACCM;
378	/** Pointer to HWACCM VM instance data. */
379	typedef HWACCM *PHWACCM;
380
381	/* Maximum number of cached entries. */
382	#define VMCSCACHE_MAX_ENTRY 128
383
384	/* Structure for storing read and write VMCS actions. */
385	typedef struct VMCSCACHE
386	{
387	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
388	/* Magic marker for searching in crash dumps. */
389	uint8_t aMagic[16];
390	uint64_t uMagic;
391	uint64_t u64TimeEntry;
392	uint64_t u64TimeSwitch;
393	uint64_t cResume;
394	uint64_t interPD;
395	uint64_t pSwitcher;
396	uint32_t uPos;
397	uint32_t idCpu;
398	#endif
399	/* CR2 is saved here for EPT syncing. */
400	uint64_t cr2;
401	struct
402	{
403	uint32_t cValidEntries;
404	uint32_t uAlignment;
405	uint32_t aField[VMCSCACHE_MAX_ENTRY];
406	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
407	} Write;
408	struct
409	{
410	uint32_t cValidEntries;
411	uint32_t uAlignment;
412	uint32_t aField[VMCSCACHE_MAX_ENTRY];
413	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
414	} Read;
415	#ifdef DEBUG
416	struct
417	{
418	RTHCPHYS pPageCpuPhys;
419	RTHCPHYS pVMCSPhys;
420	RTGCPTR pCache;
421	RTGCPTR pCtx;
422	} TestIn;
423	struct
424	{
425	RTHCPHYS pVMCSPhys;
426	RTGCPTR pCache;
427	RTGCPTR pCtx;
428	uint64_t eflags;
429	uint64_t cr8;
430	} TestOut;
431	struct
432	{
433	uint64_t param1;
434	uint64_t param2;
435	uint64_t param3;
436	uint64_t param4;
437	} ScratchPad;
438	#endif
439	} VMCSCACHE;
440	/** Pointer to VMCSCACHE. */
441	typedef VMCSCACHE *PVMCSCACHE;
442
443	/**
444	* HWACCM VMCPU Instance data.
445	*/
446	typedef struct HWACCMCPU
447	{
448	/** Old style FPU reporting trap mask override performed (optimization) */
449	bool fFPUOldStyleOverride;
450
451	/** Set if we don't have to flush the TLB on VM entry. */
452	bool fResumeVM;
453
454	/** Set if we need to flush the TLB during the world switch. */
455	bool fForceTLBFlush;
456
457	/** Set when we're using VT-x or AMD-V at that moment. */
458	bool fActive;
459
460	/** HWACCM_CHANGED_* flags. */
461	RTUINT fContextUseFlags;
462
463	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
464	RTCPUID idLastCpu;
465
466	/* TLB flush count */
467	RTUINT cTLBFlushes;
468
469	/* Current ASID in use by the VM */
470	RTUINT uCurrentASID;
471
472	struct
473	{
474	/** R0 memory object for the VM control structure (VMCS). */
475	RTR0MEMOBJ pMemObjVMCS;
476	/** Physical address of the VM control structure (VMCS). */
477	RTHCPHYS pVMCSPhys;
478	/** Virtual address of the VM control structure (VMCS). */
479	R0PTRTYPE(void *) pVMCS;
480
481	/** Ring 0 handlers for VT-x. */
482	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu));
483
484	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
485	uint64_t proc_ctls;
486
487	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
488	uint64_t proc_ctls2;
489
490	/** R0 memory object for the virtual APIC page for TPR caching. */
491	RTR0MEMOBJ pMemObjVAPIC;
492	/** Physical address of the virtual APIC page for TPR caching. */
493	RTHCPHYS pVAPICPhys;
494	/** Virtual address of the virtual APIC page for TPR caching. */
495	R0PTRTYPE(uint8_t *) pVAPIC;
496
497	/** Current CR0 mask. */
498	uint64_t cr0_mask;
499	/** Current CR4 mask. */
500	uint64_t cr4_mask;
501
502	/** Current EPTP. */
503	RTHCPHYS GCPhysEPTP;
504
505	/** VMCS cache. */
506	VMCSCACHE VMCSCache;
507
508	/** Real-mode emulation state. */
509	struct
510	{
511	X86EFLAGS eflags;
512	uint32_t fValid;
513	} RealMode;
514
515	struct
516	{
517	uint64_t u64VMCSPhys;
518	uint32_t ulVMCSRevision;
519	uint32_t ulInstrError;
520	uint32_t ulExitReason;
521	RTCPUID idEnteredCpu;
522	RTCPUID idCurrentCpu;
523	uint32_t padding;
524	} lasterror;
525
526	/** The last seen guest paging mode (by VT-x). */
527	PGMMODE enmLastSeenGuestMode;
528	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
529	PGMMODE enmCurrGuestMode;
530	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
531	PGMMODE enmPrevGuestMode;
532	} vmx;
533
534	struct
535	{
536	/** R0 memory object for the host VM control block (VMCB). */
537	RTR0MEMOBJ pMemObjVMCBHost;
538	/** Physical address of the host VM control block (VMCB). */
539	RTHCPHYS pVMCBHostPhys;
540	/** Virtual address of the host VM control block (VMCB). */
541	R0PTRTYPE(void *) pVMCBHost;
542
543	/** R0 memory object for the VM control block (VMCB). */
544	RTR0MEMOBJ pMemObjVMCB;
545	/** Physical address of the VM control block (VMCB). */
546	RTHCPHYS pVMCBPhys;
547	/** Virtual address of the VM control block (VMCB). */
548	R0PTRTYPE(void *) pVMCB;
549
550	/** Ring 0 handlers for VT-x. */
551	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
552
553	} svm;
554
555	/** Event injection state. */
556	struct
557	{
558	uint32_t fPending;
559	uint32_t errCode;
560	uint64_t intInfo;
561	} Event;
562
563	/** IO Block emulation state. */
564	struct
565	{
566	bool fEnabled;
567	uint8_t u8Align[7];
568
569	/** RIP at the start of the io code we wish to emulate in the recompiler. */
570	RTGCPTR GCPtrFunctionEip;
571
572	uint64_t cr0;
573	} EmulateIoBlock;
574
575	/** Currenty shadow paging mode. */
576	PGMMODE enmShadowMode;
577
578	/** The CPU ID of the CPU currently owning the VMCS. Set in
579	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
580	RTCPUID idEnteredCpu;
581
582	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
583	struct
584	{
585	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
586	unsigned cPages;
587	} TlbShootdown;
588
589	/** For saving stack space, the disassembler state is allocated here instead of
590	* on the stack.
591	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
592	union
593	{
594	/** The disassembler scratch space. */
595	DISCPUSTATE DisState;
596	/** Padding. */
597	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
598	};
599
600	RTUINT padding2[1];
601
602	STAMPROFILEADV StatEntry;
603	STAMPROFILEADV StatExit1;
604	STAMPROFILEADV StatExit2;
605	#if 1 /* temporary for tracking down darwin issues. */
606	STAMPROFILEADV StatExit2Sub1;
607	STAMPROFILEADV StatExit2Sub2;
608	STAMPROFILEADV StatExit2Sub3;
609	#endif
610	STAMPROFILEADV StatInGC;
611
612	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
613	STAMPROFILEADV StatWorldSwitch3264;
614	#endif
615
616	STAMCOUNTER StatIntInject;
617
618	STAMCOUNTER StatExitShadowNM;
619	STAMCOUNTER StatExitGuestNM;
620	STAMCOUNTER StatExitShadowPF;
621	STAMCOUNTER StatExitGuestPF;
622	STAMCOUNTER StatExitGuestUD;
623	STAMCOUNTER StatExitGuestSS;
624	STAMCOUNTER StatExitGuestNP;
625	STAMCOUNTER StatExitGuestGP;
626	STAMCOUNTER StatExitGuestDE;
627	STAMCOUNTER StatExitGuestDB;
628	STAMCOUNTER StatExitGuestMF;
629	STAMCOUNTER StatExitInvpg;
630	STAMCOUNTER StatExitInvd;
631	STAMCOUNTER StatExitCpuid;
632	STAMCOUNTER StatExitRdtsc;
633	STAMCOUNTER StatExitRdpmc;
634	STAMCOUNTER StatExitCli;
635	STAMCOUNTER StatExitSti;
636	STAMCOUNTER StatExitPushf;
637	STAMCOUNTER StatExitPopf;
638	STAMCOUNTER StatExitIret;
639	STAMCOUNTER StatExitInt;
640	STAMCOUNTER StatExitCRxWrite[16];
641	STAMCOUNTER StatExitCRxRead[16];
642	STAMCOUNTER StatExitDRxWrite;
643	STAMCOUNTER StatExitDRxRead;
644	STAMCOUNTER StatExitRdmsr;
645	STAMCOUNTER StatExitWrmsr;
646	STAMCOUNTER StatExitCLTS;
647	STAMCOUNTER StatExitHlt;
648	STAMCOUNTER StatExitMwait;
649	STAMCOUNTER StatExitLMSW;
650	STAMCOUNTER StatExitIOWrite;
651	STAMCOUNTER StatExitIORead;
652	STAMCOUNTER StatExitIOStringWrite;
653	STAMCOUNTER StatExitIOStringRead;
654	STAMCOUNTER StatExitIrqWindow;
655	STAMCOUNTER StatExitMaxResume;
656	STAMCOUNTER StatExitPreemptPending;
657	STAMCOUNTER StatIntReinject;
658	STAMCOUNTER StatPendingHostIrq;
659
660	STAMCOUNTER StatFlushPageManual;
661	STAMCOUNTER StatFlushPhysPageManual;
662	STAMCOUNTER StatFlushTLBManual;
663	STAMCOUNTER StatFlushPageInvlpg;
664	STAMCOUNTER StatFlushTLBWorldSwitch;
665	STAMCOUNTER StatNoFlushTLBWorldSwitch;
666	STAMCOUNTER StatFlushTLBCRxChange;
667	STAMCOUNTER StatFlushASID;
668	STAMCOUNTER StatFlushTLBInvlpga;
669	STAMCOUNTER StatTlbShootdown;
670	STAMCOUNTER StatTlbShootdownFlush;
671
672	STAMCOUNTER StatSwitchGuestIrq;
673	STAMCOUNTER StatSwitchToR3;
674
675	STAMCOUNTER StatTSCOffset;
676	STAMCOUNTER StatTSCIntercept;
677
678	STAMCOUNTER StatExitReasonNPF;
679	STAMCOUNTER StatDRxArmed;
680	STAMCOUNTER StatDRxContextSwitch;
681	STAMCOUNTER StatDRxIOCheck;
682
683
684	#ifdef VBOX_WITH_STATISTICS
685	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
686	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
687	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
688	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
689	#endif
690	} HWACCMCPU;
691	/** Pointer to HWACCM VM instance data. */
692	typedef HWACCMCPU *PHWACCMCPU;
693
694
695	#ifdef IN_RING0
696
697	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
698	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
699
700
701	#ifdef VBOX_STRICT
702	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
703	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
704	#else
705	#define HWACCMDumpRegs(a, b ,c) do { } while (0)
706	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
707	#endif
708
709	/* Dummy callback handlers. */
710	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
711	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
712	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
713	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
714	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
715	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
716	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
717	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
718	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
719	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
720
721
722	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
723	/**
724	* Gets 64-bit GDTR and IDTR on darwin.
725	* @param pGdtr Where to store the 64-bit GDTR.
726	* @param pIdtr Where to store the 64-bit IDTR.
727	*/
728	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
729
730	/**
731	* Gets 64-bit CR3 on darwin.
732	* @returns CR3
733	*/
734	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
735	# endif
736
737	#endif /* IN_RING0 */
738
739	/** @} */
740
741	RT_C_DECLS_END
742
743	#endif
744

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 20961

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