HWACCMInternal.h@ 15540

Last change on this file since 15540 was 15507, checked in by vboxsync, 16 years ago
VT-x: keep track of missed paging mode changes
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1	/* $Id: HWACCMInternal.h 15507 2008-12-15 14:51:45Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define VMX_USE_CACHED_VMCS_ACCESSES
43	#define HWACCM_VMX_EMULATE_REALMODE
44	#define HWACCM_VTX_WITH_EPT
45	#define HWACCM_VTX_WITH_VPID
46
47	__BEGIN_DECLS
48
49
50	/** @defgroup grp_hwaccm_int Internal
51	* @ingroup grp_hwaccm
52	* @internal
53	* @{
54	*/
55
56
57	/** Maximum number of exit reason statistics counters. */
58	#define MAX_EXITREASON_STAT 0x100
59	#define MASK_EXITREASON_STAT 0xff
60
61	/** @name Changed flags
62	* These flags are used to keep track of which important registers that
63	* have been changed since last they were reset.
64	* @{
65	*/
66	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
67	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
68	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
69	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
70	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
71	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
72	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
73	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
74	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
75	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
76	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
77	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
78
79	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
80	\| HWACCM_CHANGED_GUEST_CR0 \
81	\| HWACCM_CHANGED_GUEST_CR3 \
82	\| HWACCM_CHANGED_GUEST_CR4 \
83	\| HWACCM_CHANGED_GUEST_GDTR \
84	\| HWACCM_CHANGED_GUEST_IDTR \
85	\| HWACCM_CHANGED_GUEST_LDTR \
86	\| HWACCM_CHANGED_GUEST_TR \
87	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
88	\| HWACCM_CHANGED_GUEST_FPU \
89	\| HWACCM_CHANGED_GUEST_DEBUG \
90	\| HWACCM_CHANGED_HOST_CONTEXT)
91
92	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93	\| HWACCM_CHANGED_GUEST_CR0 \
94	\| HWACCM_CHANGED_GUEST_CR3 \
95	\| HWACCM_CHANGED_GUEST_CR4 \
96	\| HWACCM_CHANGED_GUEST_GDTR \
97	\| HWACCM_CHANGED_GUEST_IDTR \
98	\| HWACCM_CHANGED_GUEST_LDTR \
99	\| HWACCM_CHANGED_GUEST_TR \
100	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101	\| HWACCM_CHANGED_GUEST_DEBUG \
102	\| HWACCM_CHANGED_GUEST_FPU)
103
104	/** @} */
105
106	/** @name Intercepted traps
107	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
108	* Currently #NM and #PF only
109	*/
110	#ifdef VBOX_STRICT
111	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
112	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
113	#else
114	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
115	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#endif
117	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
118	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
119	/** @} */
120
121
122	/** Maxium resume loops allowed in ring 0 (safety precaution) */
123	#define HWACCM_MAX_RESUME_LOOPS 1024
124
125	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
126	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
127	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
128	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
129	/** Total guest mapped memory needed. */
130	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
131
132	/** HWACCM SSM version
133	*/
134	#define HWACCM_SSM_VERSION 4
135	#define HWACCM_SSM_VERSION_2_0_X 3
136
137	/* Per-cpu information. (host) */
138	typedef struct
139	{
140	RTCPUID idCpu;
141
142	RTR0MEMOBJ pMemObj;
143	/* Current ASID (AMD-V)/VPID (Intel) */
144	uint32_t uCurrentASID;
145	/* TLB flush count */
146	uint32_t cTLBFlushes;
147
148	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
149	bool fFlushTLB;
150
151	/** Configured for VT-x or AMD-V. */
152	bool fConfigured;
153
154	/** In use by our code. (for power suspend) */
155	volatile bool fInUse;
156	} HWACCM_CPUINFO;
157	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
158
159	/* VT-x capability qword. */
160	typedef union
161	{
162	struct
163	{
164	uint32_t disallowed0;
165	uint32_t allowed1;
166	} n;
167	uint64_t u;
168	} VMX_CAPABILITY;
169
170	/**
171	* Switcher function, HC to RC.
172	*
173	* @param pVM The VM handle.
174	* @returns Return code indicating the action to take.
175	*/
176	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
177	/** Pointer to switcher function. */
178	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
179
180	/**
181	* HWACCM VM Instance data.
182	* Changes to this must checked against the padding of the cfgm union in VM!
183	*/
184	typedef struct HWACCM
185	{
186	/** Set when we've initialized VMX or SVM. */
187	bool fInitialized;
188
189	/** Set when we're using VMX/SVN at that moment. */
190	bool fActive;
191
192	/** Set when hardware acceleration is allowed. */
193	bool fAllowed;
194
195	/** Set if nested paging is enabled. */
196	bool fNestedPaging;
197
198	/** Set if nested paging is allowed. */
199	bool fAllowNestedPaging;
200
201	/** Set if we're supposed to inject an NMI. */
202	bool fInjectNMI;
203
204	/** Set if we can support 64-bit guests or not. */
205	bool fAllow64BitGuests;
206
207	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
208	* naturally. */
209	bool padding[1];
210
211	/** And mask for copying register contents. */
212	uint64_t u64RegisterMask;
213
214	/** Maximum ASID allowed. */
215	RTUINT uMaxASID;
216
217	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
218	/** 32 to 64 bits switcher entrypoint. */
219	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
220
221	/* AMD-V 64 bits vmrun handler */
222	RTRCPTR pfnSVMGCVMRun64;
223
224	/* VT-x 64 bits vmlaunch handler */
225	RTRCPTR pfnVMXGCStartVM64;
226
227	/* RC handler to setup the 64 bits FPU state. */
228	RTRCPTR pfnSaveGuestFPU64;
229
230	/* RC handler to setup the 64 bits debug state. */
231	RTRCPTR pfnSaveGuestDebug64;
232
233	# ifdef DEBUG
234	/* Test handler */
235	RTRCPTR pfnTest64;
236
237	RTRCPTR uAlignment[1];
238	# endif
239	#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
240	uint32_t u32Alignment[1];
241	#endif
242
243	struct
244	{
245	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
246	bool fSupported;
247
248	/** Set when we've enabled VMX. */
249	bool fEnabled;
250
251	/** Set if VPID is supported. */
252	bool fVPID;
253
254	/** Set if VT-x VPID is allowed. */
255	bool fAllowVPID;
256
257	/** Virtual address of the TSS page used for real mode emulation. */
258	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
259
260	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
261	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
262
263	/** R0 memory object for the virtual APIC mmio cache. */
264	RTR0MEMOBJ pMemObjAPIC;
265	/** Physical address of the virtual APIC mmio cache. */
266	RTHCPHYS pAPICPhys;
267	/** Virtual address of the virtual APIC mmio cache. */
268	R0PTRTYPE(uint8_t *) pAPIC;
269
270	/** R0 memory object for the MSR bitmap (1 page). */
271	RTR0MEMOBJ pMemObjMSRBitmap;
272	/** Physical address of the MSR bitmap (1 page). */
273	RTHCPHYS pMSRBitmapPhys;
274	/** Virtual address of the MSR bitmap (1 page). */
275	R0PTRTYPE(uint8_t *) pMSRBitmap;
276
277	/** R0 memory object for the MSR entry load page (guest MSRs). */
278	RTR0MEMOBJ pMemObjMSREntryLoad;
279	/** Physical address of the MSR entry load page (guest MSRs). */
280	RTHCPHYS pMSREntryLoadPhys;
281	/** Virtual address of the MSR entry load page (guest MSRs). */
282	R0PTRTYPE(uint8_t *) pMSREntryLoad;
283
284	/** R0 memory object for the MSR exit store page (guest MSRs). */
285	RTR0MEMOBJ pMemObjMSRExitStore;
286	/** Physical address of the MSR exit store page (guest MSRs). */
287	RTHCPHYS pMSRExitStorePhys;
288	/** Virtual address of the MSR exit store page (guest MSRs). */
289	R0PTRTYPE(uint8_t *) pMSRExitStore;
290
291	/** R0 memory object for the MSR exit load page (host MSRs). */
292	RTR0MEMOBJ pMemObjMSRExitLoad;
293	/** Physical address of the MSR exit load page (host MSRs). */
294	RTHCPHYS pMSRExitLoadPhys;
295	/** Virtual address of the MSR exit load page (host MSRs). */
296	R0PTRTYPE(uint8_t *) pMSRExitLoad;
297
298	/** Ring 0 handlers for VT-x. */
299	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
300
301	/** Host CR4 value (set by ring-0 VMX init) */
302	uint64_t hostCR4;
303
304	/** VMX MSR values */
305	struct
306	{
307	uint64_t feature_ctrl;
308	uint64_t vmx_basic_info;
309	VMX_CAPABILITY vmx_pin_ctls;
310	VMX_CAPABILITY vmx_proc_ctls;
311	VMX_CAPABILITY vmx_proc_ctls2;
312	VMX_CAPABILITY vmx_exit;
313	VMX_CAPABILITY vmx_entry;
314	uint64_t vmx_misc;
315	uint64_t vmx_cr0_fixed0;
316	uint64_t vmx_cr0_fixed1;
317	uint64_t vmx_cr4_fixed0;
318	uint64_t vmx_cr4_fixed1;
319	uint64_t vmx_vmcs_enum;
320	uint64_t vmx_eptcaps;
321	} msr;
322
323	/** Flush types for invept & invvpid; they depend on capabilities. */
324	VMX_FLUSH enmFlushPage;
325	VMX_FLUSH enmFlushContext;
326	} vmx;
327
328	struct
329	{
330	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
331	bool fSupported;
332	/** Set when we've enabled SVM. */
333	bool fEnabled;
334	/** Set if erratum 170 affects the AMD cpu. */
335	bool fAlwaysFlushTLB;
336	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
337	* naturally. */
338	bool padding[1];
339
340	/** R0 memory object for the host VM control block (VMCB). */
341	RTR0MEMOBJ pMemObjVMCBHost;
342	/** Physical address of the host VM control block (VMCB). */
343	RTHCPHYS pVMCBHostPhys;
344	/** Virtual address of the host VM control block (VMCB). */
345	R0PTRTYPE(void *) pVMCBHost;
346
347	/** R0 memory object for the IO bitmap (12kb). */
348	RTR0MEMOBJ pMemObjIOBitmap;
349	/** Physical address of the IO bitmap (12kb). */
350	RTHCPHYS pIOBitmapPhys;
351	/** Virtual address of the IO bitmap. */
352	R0PTRTYPE(void *) pIOBitmap;
353
354	/** R0 memory object for the MSR bitmap (8kb). */
355	RTR0MEMOBJ pMemObjMSRBitmap;
356	/** Physical address of the MSR bitmap (8kb). */
357	RTHCPHYS pMSRBitmapPhys;
358	/** Virtual address of the MSR bitmap. */
359	R0PTRTYPE(void *) pMSRBitmap;
360
361	/** SVM revision. */
362	uint32_t u32Rev;
363
364	/** SVM feature bits from cpuid 0x8000000a */
365	uint32_t u32Features;
366	} svm;
367
368	struct
369	{
370	uint32_t u32AMDFeatureECX;
371	uint32_t u32AMDFeatureEDX;
372	} cpuid;
373
374	/** Saved error from detection */
375	int32_t lLastError;
376
377	/** HWACCMR0Init was run */
378	bool fHWACCMR0Init;
379	} HWACCM;
380	/** Pointer to HWACCM VM instance data. */
381	typedef HWACCM *PHWACCM;
382
383	/* Maximum number of cached entries. */
384	#define VMCSCACHE_MAX_ENTRY 256
385
386	/* Structure for storing read and write VMCS actions. */
387	typedef struct VMCSCACHE
388	{
389	/* CR2 is saved here for EPT syncing. */
390	uint64_t cr2;
391	struct
392	{
393	uint32_t cValidEntries;
394	uint32_t uAlignment;
395	uint32_t aField[VMCSCACHE_MAX_ENTRY];
396	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
397	} Write;
398	struct
399	{
400	uint32_t cValidEntries;
401	uint32_t uAlignment;
402	uint32_t aField[VMCSCACHE_MAX_ENTRY];
403	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
404	} Read;
405	#ifdef DEBUG
406	struct
407	{
408	RTHCPHYS pPageCpuPhys;
409	RTHCPHYS pVMCSPhys;
410	RTGCPTR pCache;
411	RTGCPTR pCtx;
412	} TestIn;
413	struct
414	{
415	RTHCPHYS pVMCSPhys;
416	RTGCPTR pCache;
417	RTGCPTR pCtx;
418	} TestOut;
419	struct
420	{
421	uint64_t param1;
422	uint64_t param2;
423	uint64_t param3;
424	uint64_t param4;
425	} ScratchPad;
426	#endif
427	} VMCSCACHE;
428	/** Pointer to VMCSCACHE. */
429	typedef VMCSCACHE *PVMCSCACHE;
430
431	/**
432	* HWACCM VMCPU Instance data.
433	*/
434	typedef struct HWACCMCPU
435	{
436	/** Old style FPU reporting trap mask override performed (optimization) */
437	bool fFPUOldStyleOverride;
438
439	/** Set if we don't have to flush the TLB on VM entry. */
440	bool fResumeVM;
441
442	/** Set if we need to flush the TLB during the world switch. */
443	bool fForceTLBFlush;
444
445	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
446	* naturally. */
447	bool padding[1];
448
449	/** HWACCM_CHANGED_* flags. */
450	RTUINT fContextUseFlags;
451
452	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
453	RTCPUID idLastCpu;
454
455	/* TLB flush count */
456	RTUINT cTLBFlushes;
457
458	/* Current ASID in use by the VM */
459	RTUINT uCurrentASID;
460
461	struct
462	{
463	/** R0 memory object for the VM control structure (VMCS). */
464	RTR0MEMOBJ pMemObjVMCS;
465	/** Physical address of the VM control structure (VMCS). */
466	RTHCPHYS pVMCSPhys;
467	/** Virtual address of the VM control structure (VMCS). */
468	R0PTRTYPE(void *) pVMCS;
469
470	/** Ring 0 handlers for VT-x. */
471	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu));
472
473	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
474	uint64_t proc_ctls;
475
476	/** Current CR0 mask. */
477	uint64_t cr0_mask;
478	/** Current CR4 mask. */
479	uint64_t cr4_mask;
480
481	/** Current EPTP. */
482	RTHCPHYS GCPhysEPTP;
483
484	/** VMCS cache. */
485	VMCSCACHE VMCSCache;
486
487	/** Real-mode emulation state. */
488	struct
489	{
490	X86EFLAGS eflags;
491	uint32_t fValid;
492	} RealMode;
493
494	struct
495	{
496	uint64_t u64VMCSPhys;
497	uint32_t ulVMCSRevision;
498	uint32_t ulInstrError;
499	uint32_t ulExitReason;
500	RTCPUID idEnteredCpu;
501	RTCPUID idCurrentCpu;
502	uint32_t padding;
503	} lasterror;
504
505	/** The last seen guest paging mode (by VT-x). */
506	PGMMODE enmLastSeenGuestMode;
507	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
508	PGMMODE enmCurrGuestMode;
509	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
510	PGMMODE enmPrevGuestMode;
511	} vmx;
512
513	struct
514	{
515	/** R0 memory object for the VM control block (VMCB). */
516	RTR0MEMOBJ pMemObjVMCB;
517	/** Physical address of the VM control block (VMCB). */
518	RTHCPHYS pVMCBPhys;
519	/** Virtual address of the VM control block (VMCB). */
520	R0PTRTYPE(void *) pVMCB;
521
522	/** Ring 0 handlers for VT-x. */
523	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
524
525	} svm;
526
527	/** Event injection state. */
528	struct
529	{
530	uint32_t fPending;
531	uint32_t errCode;
532	uint64_t intInfo;
533	} Event;
534
535	/** Currenty shadow paging mode. */
536	PGMMODE enmShadowMode;
537
538	/** The CPU ID of the CPU currently owning the VMCS. Set in
539	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
540	RTCPUID idEnteredCpu;
541
542	STAMPROFILEADV StatEntry;
543	STAMPROFILEADV StatExit1;
544	STAMPROFILEADV StatExit2;
545	#if 1 /* temporary for tracking down darwin issues. */
546	STAMPROFILEADV StatExit2Sub1;
547	STAMPROFILEADV StatExit2Sub2;
548	STAMPROFILEADV StatExit2Sub3;
549	#endif
550	STAMPROFILEADV StatInGC;
551
552	STAMCOUNTER StatIntInject;
553
554	STAMCOUNTER StatExitShadowNM;
555	STAMCOUNTER StatExitGuestNM;
556	STAMCOUNTER StatExitShadowPF;
557	STAMCOUNTER StatExitGuestPF;
558	STAMCOUNTER StatExitGuestUD;
559	STAMCOUNTER StatExitGuestSS;
560	STAMCOUNTER StatExitGuestNP;
561	STAMCOUNTER StatExitGuestGP;
562	STAMCOUNTER StatExitGuestDE;
563	STAMCOUNTER StatExitGuestDB;
564	STAMCOUNTER StatExitGuestMF;
565	STAMCOUNTER StatExitInvpg;
566	STAMCOUNTER StatExitInvd;
567	STAMCOUNTER StatExitCpuid;
568	STAMCOUNTER StatExitRdtsc;
569	STAMCOUNTER StatExitCRxWrite[8];
570	STAMCOUNTER StatExitCRxRead[8];
571	STAMCOUNTER StatExitDRxWrite;
572	STAMCOUNTER StatExitDRxRead;
573	STAMCOUNTER StatExitCLTS;
574	STAMCOUNTER StatExitLMSW;
575	STAMCOUNTER StatExitIOWrite;
576	STAMCOUNTER StatExitIORead;
577	STAMCOUNTER StatExitIOStringWrite;
578	STAMCOUNTER StatExitIOStringRead;
579	STAMCOUNTER StatExitIrqWindow;
580	STAMCOUNTER StatExitMaxResume;
581	STAMCOUNTER StatIntReinject;
582	STAMCOUNTER StatPendingHostIrq;
583
584	STAMCOUNTER StatFlushPageManual;
585	STAMCOUNTER StatFlushPhysPageManual;
586	STAMCOUNTER StatFlushTLBManual;
587	STAMCOUNTER StatFlushPageInvlpg;
588	STAMCOUNTER StatFlushTLBWorldSwitch;
589	STAMCOUNTER StatNoFlushTLBWorldSwitch;
590	STAMCOUNTER StatFlushTLBCRxChange;
591	STAMCOUNTER StatFlushASID;
592	STAMCOUNTER StatFlushTLBInvlpga;
593
594	STAMCOUNTER StatSwitchGuestIrq;
595	STAMCOUNTER StatSwitchToR3;
596
597	STAMCOUNTER StatTSCOffset;
598	STAMCOUNTER StatTSCIntercept;
599
600	STAMCOUNTER StatExitReasonNPF;
601	STAMCOUNTER StatDRxArmed;
602	STAMCOUNTER StatDRxContextSwitch;
603	STAMCOUNTER StatDRxIOCheck;
604
605
606	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
607	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
608	} HWACCMCPU;
609	/** Pointer to HWACCM VM instance data. */
610	typedef HWACCMCPU *PHWACCMCPU;
611
612
613	#ifdef IN_RING0
614
615	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
616	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
617
618
619	#ifdef VBOX_STRICT
620	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
621	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
622	#else
623	#define HWACCMDumpRegs(a, b) do { } while (0)
624	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
625	#endif
626
627	/* Dummy callback handlers. */
628	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
629	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
630	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
631	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
632	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
633	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
634	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
635	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
636	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
637	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
638
639
640	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
641	/**
642	* Gets 64-bit GDTR and IDTR on darwin.
643	* @param pGdtr Where to store the 64-bit GDTR.
644	* @param pIdtr Where to store the 64-bit IDTR.
645	*/
646	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
647
648	/**
649	* Gets 64-bit CR3 on darwin.
650	* @returns CR3
651	*/
652	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
653	# endif
654
655	#endif /* IN_RING0 */
656
657	/** @} */
658
659	__END_DECLS
660
661	#endif
662

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 15540

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