VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 12566

Last change on this file since 12566 was 12566, checked in by vboxsync, 16 years ago

Backed out 36722, 36764 & 36770; no need for per-cpu mmio registations anymore.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 18.6 KB
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1/* $Id: HWACCMInternal.h 12566 2008-09-18 12:42:54Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <iprt/memobj.h>
33#include <iprt/cpuset.h>
34#include <iprt/mp.h>
35
36#define VBOX_WITH_HWACCM_DEBUG_REGISTER_SUPPORT
37
38#if HC_ARCH_BITS == 64
39/* Enable 64 bits guest support. */
40# define VBOX_ENABLE_64_BITS_GUESTS
41#endif
42
43__BEGIN_DECLS
44
45
46/** @defgroup grp_hwaccm_int Internal
47 * @ingroup grp_hwaccm
48 * @internal
49 * @{
50 */
51
52
53/**
54 * Converts a HWACCM pointer into a VM pointer.
55 * @returns Pointer to the VM structure the EM is part of.
56 * @param pHWACCM Pointer to HWACCM instance data.
57 */
58#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
59
60/** Maximum number of exit reason statistics counters. */
61#define MAX_EXITREASON_STAT 0x100
62#define MASK_EXITREASON_STAT 0xff
63
64/** @name Changed flags
65 * These flags are used to keep track of which important registers that
66 * have been changed since last they were reset.
67 * @{
68 */
69#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
70#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
71#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
72#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
73#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
74#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
75#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
76#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
77#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
78#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
79#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
80#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
81
82#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
83 | HWACCM_CHANGED_GUEST_CR0 \
84 | HWACCM_CHANGED_GUEST_CR3 \
85 | HWACCM_CHANGED_GUEST_CR4 \
86 | HWACCM_CHANGED_GUEST_GDTR \
87 | HWACCM_CHANGED_GUEST_IDTR \
88 | HWACCM_CHANGED_GUEST_LDTR \
89 | HWACCM_CHANGED_GUEST_TR \
90 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
91 | HWACCM_CHANGED_GUEST_FPU \
92 | HWACCM_CHANGED_GUEST_DEBUG \
93 | HWACCM_CHANGED_HOST_CONTEXT)
94
95#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
96 | HWACCM_CHANGED_GUEST_CR0 \
97 | HWACCM_CHANGED_GUEST_CR3 \
98 | HWACCM_CHANGED_GUEST_CR4 \
99 | HWACCM_CHANGED_GUEST_GDTR \
100 | HWACCM_CHANGED_GUEST_IDTR \
101 | HWACCM_CHANGED_GUEST_LDTR \
102 | HWACCM_CHANGED_GUEST_TR \
103 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
104 | HWACCM_CHANGED_GUEST_DEBUG \
105 | HWACCM_CHANGED_GUEST_FPU)
106
107/** @} */
108
109/** @name Intercepted traps
110 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
111 * Currently #NM and #PF only
112 */
113#ifdef VBOX_STRICT
114#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
115#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
116#else
117#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
118#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
119#endif
120/** @} */
121
122
123/** Maxium resume loops allowed in ring 0 (safety precaution) */
124#define HWACCM_MAX_RESUME_LOOPS 1024
125
126/** HWACCM SSM version
127 */
128#define HWACCM_SSM_VERSION 3
129
130/* Per-cpu information. */
131typedef struct
132{
133 RTCPUID idCpu;
134
135 RTR0MEMOBJ pMemObj;
136 /* Current ASID (AMD-V only) */
137 uint32_t uCurrentASID;
138 /* TLB flush count */
139 uint32_t cTLBFlushes;
140
141 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
142 bool fFlushTLB;
143
144 bool fConfigured;
145} HWACCM_CPUINFO;
146typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
147
148/* VT-x capability qword. */
149typedef union
150{
151 struct
152 {
153 uint32_t disallowed0;
154 uint32_t allowed1;
155 } n;
156 uint64_t u;
157} VMX_CAPABILITY;
158
159/**
160 * HWACCM VM Instance data.
161 * Changes to this must checked against the padding of the cfgm union in VM!
162 */
163typedef struct HWACCM
164{
165 /** Offset to the VM structure.
166 * See HWACCM2VM(). */
167 RTUINT offVM;
168
169 /** Set when we've initialized VMX or SVM. */
170 bool fInitialized;
171 /** Set when we're using VMX/SVN at that moment. */
172 bool fActive;
173
174 /** Set when hardware acceleration is allowed. */
175 bool fAllowed;
176
177 /** Set if nested paging is enabled. */
178 bool fNestedPaging;
179
180 /** Set if nested paging is allowed. */
181 bool fAllowNestedPaging;
182
183 /** HWACCM_CHANGED_* flags. */
184 uint32_t fContextUseFlags;
185
186 /** Old style FPU reporting trap mask override performed (optimization) */
187 uint32_t fFPUOldStyleOverride;
188
189 /** And mask for copying register contents. */
190 uint64_t u64RegisterMask;
191 struct
192 {
193 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
194 bool fSupported;
195
196 /** Set when we've enabled VMX. */
197 bool fEnabled;
198
199 /** Set if we can use VMXResume to execute guest code. */
200 bool fResumeVM;
201
202 /** R0 memory object for the VM control structure (VMCS). */
203 RTR0MEMOBJ pMemObjVMCS;
204 /** Physical address of the VM control structure (VMCS). */
205 RTHCPHYS pVMCSPhys;
206 /** Virtual address of the VM control structure (VMCS). */
207 R0PTRTYPE(void *) pVMCS;
208
209 /** R0 memory object for the TSS page used for real mode emulation. */
210 RTR0MEMOBJ pMemObjRealModeTSS;
211 /** Physical address of the TSS page used for real mode emulation. */
212 RTHCPHYS pRealModeTSSPhys;
213 /** Virtual address of the TSS page used for real mode emulation. */
214 R0PTRTYPE(PVBOXTSS) pRealModeTSS;
215
216 /** R0 memory object for the virtual APIC mmio cache. */
217 RTR0MEMOBJ pMemObjAPIC;
218 /** Physical address of the virtual APIC mmio cache. */
219 RTHCPHYS pAPICPhys;
220 /** Virtual address of the virtual APIC mmio cache. */
221 R0PTRTYPE(uint8_t *) pAPIC;
222
223 /** R0 memory object for the MSR bitmap (1 page). */
224 RTR0MEMOBJ pMemObjMSRBitmap;
225 /** Physical address of the MSR bitmap (1 page). */
226 RTHCPHYS pMSRBitmapPhys;
227 /** Virtual address of the MSR bitmap (1 page). */
228 R0PTRTYPE(uint8_t *) pMSRBitmap;
229
230 /** R0 memory object for the MSR entry load page (guest MSRs). */
231 RTR0MEMOBJ pMemObjMSREntryLoad;
232 /** Physical address of the MSR entry load page (guest MSRs). */
233 RTHCPHYS pMSREntryLoadPhys;
234 /** Virtual address of the MSR entry load page (guest MSRs). */
235 R0PTRTYPE(uint8_t *) pMSREntryLoad;
236
237 /** R0 memory object for the MSR exit store page (guest MSRs). */
238 RTR0MEMOBJ pMemObjMSRExitStore;
239 /** Physical address of the MSR exit store page (guest MSRs). */
240 RTHCPHYS pMSRExitStorePhys;
241 /** Virtual address of the MSR exit store page (guest MSRs). */
242 R0PTRTYPE(uint8_t *) pMSRExitStore;
243
244 /** R0 memory object for the MSR exit load page (host MSRs). */
245 RTR0MEMOBJ pMemObjMSRExitLoad;
246 /** Physical address of the MSR exit load page (host MSRs). */
247 RTHCPHYS pMSRExitLoadPhys;
248 /** Virtual address of the MSR exit load page (host MSRs). */
249 R0PTRTYPE(uint8_t *) pMSRExitLoad;
250
251 /** Ring 0 handlers for VT-x. */
252 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
253
254 /** Host CR4 value (set by ring-0 VMX init) */
255 uint64_t hostCR4;
256
257 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
258 uint64_t proc_ctls;
259
260 /** Current CR0 mask. */
261 uint64_t cr0_mask;
262 /** Current CR4 mask. */
263 uint64_t cr4_mask;
264
265 /** VMX MSR values */
266 struct
267 {
268 uint64_t feature_ctrl;
269 uint64_t vmx_basic_info;
270 VMX_CAPABILITY vmx_pin_ctls;
271 VMX_CAPABILITY vmx_proc_ctls;
272 VMX_CAPABILITY vmx_proc_ctls2;
273 VMX_CAPABILITY vmx_exit;
274 VMX_CAPABILITY vmx_entry;
275 uint64_t vmx_misc;
276 uint64_t vmx_cr0_fixed0;
277 uint64_t vmx_cr0_fixed1;
278 uint64_t vmx_cr4_fixed0;
279 uint64_t vmx_cr4_fixed1;
280 uint64_t vmx_vmcs_enum;
281 uint64_t vmx_eptcaps;
282 } msr;
283
284 /* Last instruction error */
285 uint32_t ulLastInstrError;
286
287 struct
288 {
289 uint64_t u64VMCSPhys;
290 uint32_t ulVMCSRevision;
291 } lasterror;
292 } vmx;
293
294 struct
295 {
296 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
297 bool fSupported;
298 /** Set when we've enabled SVM. */
299 bool fEnabled;
300 /** Set if we don't have to flush the TLB on VM entry. */
301 bool fResumeVM;
302 /** Set if erratum 170 affects the AMD cpu. */
303 bool fAlwaysFlushTLB;
304 /** Set if we need to flush the TLB during the world switch. */
305 bool fForceTLBFlush;
306
307 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
308 RTCPUID idLastCpu;
309
310 /* TLB flush count */
311 uint32_t cTLBFlushes;
312
313 /* Current ASID in use by the VM */
314 uint32_t uCurrentASID;
315
316 /** R0 memory object for the VM control block (VMCB). */
317 RTR0MEMOBJ pMemObjVMCB;
318 /** Physical address of the VM control block (VMCB). */
319 RTHCPHYS pVMCBPhys;
320 /** Virtual address of the VM control block (VMCB). */
321 R0PTRTYPE(void *) pVMCB;
322
323 /** R0 memory object for the host VM control block (VMCB). */
324 RTR0MEMOBJ pMemObjVMCBHost;
325 /** Physical address of the host VM control block (VMCB). */
326 RTHCPHYS pVMCBHostPhys;
327 /** Virtual address of the host VM control block (VMCB). */
328 R0PTRTYPE(void *) pVMCBHost;
329
330 /** R0 memory object for the IO bitmap (12kb). */
331 RTR0MEMOBJ pMemObjIOBitmap;
332 /** Physical address of the IO bitmap (12kb). */
333 RTHCPHYS pIOBitmapPhys;
334 /** Virtual address of the IO bitmap. */
335 R0PTRTYPE(void *) pIOBitmap;
336
337 /** R0 memory object for the MSR bitmap (8kb). */
338 RTR0MEMOBJ pMemObjMSRBitmap;
339 /** Physical address of the MSR bitmap (8kb). */
340 RTHCPHYS pMSRBitmapPhys;
341 /** Virtual address of the MSR bitmap. */
342 R0PTRTYPE(void *) pMSRBitmap;
343
344 /** Ring 0 handlers for VT-x. */
345 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
346
347 /** SVM revision. */
348 uint32_t u32Rev;
349
350 /** Maximum ASID allowed. */
351 uint32_t u32MaxASID;
352
353 /** SVM feature bits from cpuid 0x8000000a */
354 uint32_t u32Features;
355 } svm;
356
357 struct
358 {
359 uint32_t u32AMDFeatureECX;
360 uint32_t u32AMDFeatureEDX;
361 } cpuid;
362
363 /* Event injection state. */
364 struct
365 {
366 uint32_t fPending;
367 uint32_t errCode;
368 uint64_t intInfo;
369 } Event;
370
371 /** Saved error from detection */
372 int32_t lLastError;
373
374 /** HWACCMR0Init was run */
375 bool fHWACCMR0Init;
376
377 /** Currenty shadow paging mode. */
378 PGMMODE enmShadowMode;
379
380
381#ifdef VBOX_WITH_HWACCM_DEBUG_REGISTER_SUPPORT
382 struct
383 {
384 /* Saved host debug registers. */
385 uint64_t dr0, dr1, dr2, dr3, dr6, dr7;
386 bool fHostDR7Saved;
387 bool fHostDebugRegsSaved;
388 } savedhoststate;
389#endif
390
391#ifdef VBOX_STRICT
392 /** The CPU ID of the CPU currently owning the VMCS. Set in
393 * HWACCMR0Enter and cleared in HWACCMR0Leave. */
394 RTCPUID idEnteredCpu;
395# if HC_ARCH_BITS == 32
396 RTCPUID Alignment0;
397# endif
398#endif
399
400 STAMPROFILEADV StatEntry;
401 STAMPROFILEADV StatExit;
402 STAMPROFILEADV StatInGC;
403
404 STAMCOUNTER StatIntInject;
405
406 STAMCOUNTER StatExitShadowNM;
407 STAMCOUNTER StatExitGuestNM;
408 STAMCOUNTER StatExitShadowPF;
409 STAMCOUNTER StatExitGuestPF;
410 STAMCOUNTER StatExitGuestUD;
411 STAMCOUNTER StatExitGuestSS;
412 STAMCOUNTER StatExitGuestNP;
413 STAMCOUNTER StatExitGuestGP;
414 STAMCOUNTER StatExitGuestDE;
415 STAMCOUNTER StatExitGuestDB;
416 STAMCOUNTER StatExitGuestMF;
417 STAMCOUNTER StatExitInvpg;
418 STAMCOUNTER StatExitInvd;
419 STAMCOUNTER StatExitCpuid;
420 STAMCOUNTER StatExitRdtsc;
421 STAMCOUNTER StatExitCRxWrite;
422 STAMCOUNTER StatExitCRxRead;
423 STAMCOUNTER StatExitDRxWrite;
424 STAMCOUNTER StatExitDRxRead;
425 STAMCOUNTER StatExitCLTS;
426 STAMCOUNTER StatExitLMSW;
427 STAMCOUNTER StatExitIOWrite;
428 STAMCOUNTER StatExitIORead;
429 STAMCOUNTER StatExitIOStringWrite;
430 STAMCOUNTER StatExitIOStringRead;
431 STAMCOUNTER StatExitIrqWindow;
432 STAMCOUNTER StatExitMaxResume;
433 STAMCOUNTER StatIntReinject;
434 STAMCOUNTER StatPendingHostIrq;
435
436 STAMCOUNTER StatFlushPageManual;
437 STAMCOUNTER StatFlushPhysPageManual;
438 STAMCOUNTER StatFlushTLBManual;
439 STAMCOUNTER StatFlushPageInvlpg;
440 STAMCOUNTER StatFlushTLBWorldSwitch;
441 STAMCOUNTER StatNoFlushTLBWorldSwitch;
442 STAMCOUNTER StatFlushTLBCRxChange;
443 STAMCOUNTER StatFlushASID;
444
445 STAMCOUNTER StatSwitchGuestIrq;
446 STAMCOUNTER StatSwitchToR3;
447
448 STAMCOUNTER StatTSCOffset;
449 STAMCOUNTER StatTSCIntercept;
450
451 STAMCOUNTER StatExitReasonNPF;
452 STAMCOUNTER StatDR0Armed;
453 STAMCOUNTER StatDR1Armed;
454 STAMCOUNTER StatDR2Armed;
455 STAMCOUNTER StatDR3Armed;
456 STAMCOUNTER StatDRxContextSwitch;
457
458
459 R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
460 R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
461} HWACCM;
462/** Pointer to HWACCM VM instance data. */
463typedef HWACCM *PHWACCM;
464
465#ifdef IN_RING0
466
467/**
468 * Returns the cpu structure for the current cpu.
469 * Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
470 *
471 * @returns cpu structure pointer
472 * @param pVM The VM to operate on.
473 */
474HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
475
476#ifdef VBOX_STRICT
477HWACCMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
478HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
479#else
480#define HWACCMDumpRegs(a, b) do { } while (0)
481#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
482#endif
483
484/* Dummy callback handlers. */
485HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
486HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM);
487HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
488HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
489HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
490HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
491HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
492HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
493HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
494HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
495
496#endif
497
498/** @} */
499
500__END_DECLS
501
502#endif
503
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