HWACCMInternal.h@ 25776

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1	/* $Id: HWACCMInternal.h 25387 2009-12-15 10:48:35Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36	#include <iprt/avl.h>
37
38	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
39	/* Enable 64 bits guest support. */
40	# define VBOX_ENABLE_64_BITS_GUESTS
41	#endif
42
43	#define VMX_USE_CACHED_VMCS_ACCESSES
44	#define HWACCM_VMX_EMULATE_REALMODE
45	#define HWACCM_VTX_WITH_EPT
46	#define HWACCM_VTX_WITH_VPID
47
48
49	#if 0
50	/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
51	* for some strange reason the CPU doesn't save the MSRs during the VM-exit.
52	* Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
53	*
54	* Note: change the assembly files when enabling this! (remove the manual auto load/save)
55	*/
56	#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
57	#endif
58
59	RT_C_DECLS_BEGIN
60
61
62	/** @defgroup grp_hwaccm_int Internal
63	* @ingroup grp_hwaccm
64	* @internal
65	* @{
66	*/
67
68
69	/** Maximum number of exit reason statistics counters. */
70	#define MAX_EXITREASON_STAT 0x100
71	#define MASK_EXITREASON_STAT 0xff
72	#define MASK_INJECT_IRQ_STAT 0xff
73
74	/** @name Changed flags
75	* These flags are used to keep track of which important registers that
76	* have been changed since last they were reset.
77	* @{
78	*/
79	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
80	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
81	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
82	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
83	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
84	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
85	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
86	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
87	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
88	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
89	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
90	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
91
92	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93	\| HWACCM_CHANGED_GUEST_CR0 \
94	\| HWACCM_CHANGED_GUEST_CR3 \
95	\| HWACCM_CHANGED_GUEST_CR4 \
96	\| HWACCM_CHANGED_GUEST_GDTR \
97	\| HWACCM_CHANGED_GUEST_IDTR \
98	\| HWACCM_CHANGED_GUEST_LDTR \
99	\| HWACCM_CHANGED_GUEST_TR \
100	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101	\| HWACCM_CHANGED_GUEST_FPU \
102	\| HWACCM_CHANGED_GUEST_DEBUG \
103	\| HWACCM_CHANGED_HOST_CONTEXT)
104
105	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
106	\| HWACCM_CHANGED_GUEST_CR0 \
107	\| HWACCM_CHANGED_GUEST_CR3 \
108	\| HWACCM_CHANGED_GUEST_CR4 \
109	\| HWACCM_CHANGED_GUEST_GDTR \
110	\| HWACCM_CHANGED_GUEST_IDTR \
111	\| HWACCM_CHANGED_GUEST_LDTR \
112	\| HWACCM_CHANGED_GUEST_TR \
113	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
114	\| HWACCM_CHANGED_GUEST_DEBUG \
115	\| HWACCM_CHANGED_GUEST_FPU)
116
117	/** @} */
118
119	/** @name Intercepted traps
120	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
121	* Currently #NM and #PF only
122	*/
123	#ifdef VBOX_STRICT
124	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
125	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
126	#else
127	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
128	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
129	#endif
130	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
131	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
132	/** @} */
133
134
135	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
136	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
137
138	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
139	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
140	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
141	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
142	/** Total guest mapped memory needed. */
143	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
144
145	/* Enable for TPR guest patching. */
146	#define VBOX_HWACCM_WITH_GUEST_PATCHING
147
148	/** HWACCM SSM version
149	*/
150	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
151	#define HWACCM_SSM_VERSION 5
152	#define HWACCM_SSM_VERSION_NO_PATCHING 4
153	#else
154	#define HWACCM_SSM_VERSION 4
155	#define HWACCM_SSM_VERSION_NO_PATCHING 4
156	#endif
157	#define HWACCM_SSM_VERSION_2_0_X 3
158
159	/* Per-cpu information. (host) */
160	typedef struct
161	{
162	RTCPUID idCpu;
163
164	RTR0MEMOBJ pMemObj;
165	/* Current ASID (AMD-V)/VPID (Intel) */
166	uint32_t uCurrentASID;
167	/* TLB flush count */
168	uint32_t cTLBFlushes;
169
170	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
171	bool fFlushTLB;
172
173	/** Configured for VT-x or AMD-V. */
174	bool fConfigured;
175
176	/** In use by our code. (for power suspend) */
177	volatile bool fInUse;
178	} HWACCM_CPUINFO;
179	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
180
181	typedef enum
182	{
183	HWACCMPENDINGIO_INVALID = 0,
184	HWACCMPENDINGIO_PORT_READ,
185	HWACCMPENDINGIO_PORT_WRITE,
186	HWACCMPENDINGIO_STRING_READ,
187	HWACCMPENDINGIO_STRING_WRITE,
188	/** The usual 32-bit paranoia. */
189	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
190	} HWACCMPENDINGIO;
191
192
193	typedef enum
194	{
195	HWACCMTPRINSTR_INVALID,
196	HWACCMTPRINSTR_READ,
197	HWACCMTPRINSTR_READ_SHR4,
198	HWACCMTPRINSTR_WRITE_REG,
199	HWACCMTPRINSTR_WRITE_IMM,
200	HWACCMTPRINSTR_JUMP_REPLACEMENT,
201	/** The usual 32-bit paranoia. */
202	HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
203	} HWACCMTPRINSTR;
204
205	typedef struct
206	{
207	/** The key is the address of patched instruction. (32 bits GC ptr) */
208	AVLOU32NODECORE Core;
209	/** Original opcode. */
210	uint8_t aOpcode[16];
211	/** Instruction size. */
212	uint32_t cbOp;
213	/** Replacement opcode. */
214	uint8_t aNewOpcode[16];
215	/** Replacement instruction size. */
216	uint32_t cbNewOp;
217	/** Instruction type. */
218	HWACCMTPRINSTR enmType;
219	/** Source operand. */
220	uint32_t uSrcOperand;
221	/** Destination operand. */
222	uint32_t uDstOperand;
223	/** Number of times the instruction caused a fault. */
224	uint32_t cFaults;
225	/** Patch address of the jump replacement. */
226	RTGCPTR32 pJumpTarget;
227	} HWACCMTPRPATCH;
228	/** Pointer to HWACCMTPRPATCH. */
229	typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
230
231	/**
232	* Switcher function, HC to RC.
233	*
234	* @param pVM The VM handle.
235	* @returns Return code indicating the action to take.
236	*/
237	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
238	/** Pointer to switcher function. */
239	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
240
241	/**
242	* HWACCM VM Instance data.
243	* Changes to this must checked against the padding of the cfgm union in VM!
244	*/
245	typedef struct HWACCM
246	{
247	/** Set when we've initialized VMX or SVM. */
248	bool fInitialized;
249
250	/** Set when hardware acceleration is allowed. */
251	bool fAllowed;
252
253	/** Set if nested paging is enabled. */
254	bool fNestedPaging;
255
256	/** Set if nested paging is allowed. */
257	bool fAllowNestedPaging;
258
259	/** Set if we can support 64-bit guests or not. */
260	bool fAllow64BitGuests;
261
262	/** Set if an IO-APIC is configured for this VM. */
263	bool fHasIoApic;
264
265	/** Set when TPR patching is allowed. */
266	bool fTRPPatchingAllowed;
267
268	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
269	bool fGlobalInit;
270
271	/** Set when TPR patching is active. */
272	bool fTPRPatchingActive;
273	bool u8Alignment[7];
274
275	/** And mask for copying register contents. */
276	uint64_t u64RegisterMask;
277
278	/** Maximum ASID allowed. */
279	RTUINT uMaxASID;
280
281	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
282	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
283	uint32_t cMaxResumeLoops;
284
285	/** Guest allocated memory for patching purposes. */
286	RTGCPTR pGuestPatchMem;
287	/** Current free pointer inside the patch block. */
288	RTGCPTR pFreeGuestPatchMem;
289	/** Size of the guest patch memory block. */
290	uint32_t cbGuestPatchMem;
291	uint32_t uPadding1;
292
293	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
294	/** 32 to 64 bits switcher entrypoint. */
295	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
296
297	/* AMD-V 64 bits vmrun handler */
298	RTRCPTR pfnSVMGCVMRun64;
299
300	/* VT-x 64 bits vmlaunch handler */
301	RTRCPTR pfnVMXGCStartVM64;
302
303	/* RC handler to setup the 64 bits FPU state. */
304	RTRCPTR pfnSaveGuestFPU64;
305
306	/* RC handler to setup the 64 bits debug state. */
307	RTRCPTR pfnSaveGuestDebug64;
308
309	/* Test handler */
310	RTRCPTR pfnTest64;
311
312	RTRCPTR uAlignment[2];
313	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
314	uint32_t u32Alignment[1]; */
315	#endif
316
317	struct
318	{
319	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
320	bool fSupported;
321
322	/** Set when we've enabled VMX. */
323	bool fEnabled;
324
325	/** Set if VPID is supported. */
326	bool fVPID;
327
328	/** Set if VT-x VPID is allowed. */
329	bool fAllowVPID;
330
331	/** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
332	bool fUnrestrictedGuest;
333	bool uAlignment[3];
334
335	/** Virtual address of the TSS page used for real mode emulation. */
336	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
337
338	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
339	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
340
341	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
342	RTR0MEMOBJ pMemObjAPIC;
343	/** Physical address of the APIC physical page (serves for filtering accesses). */
344	RTHCPHYS pAPICPhys;
345	/** Virtual address of the APIC physical page (serves for filtering accesses). */
346	R0PTRTYPE(uint8_t *) pAPIC;
347
348	/** R0 memory object for the MSR entry load page (guest MSRs). */
349	RTR0MEMOBJ pMemObjMSREntryLoad;
350	/** Physical address of the MSR entry load page (guest MSRs). */
351	RTHCPHYS pMSREntryLoadPhys;
352	/** Virtual address of the MSR entry load page (guest MSRs). */
353	R0PTRTYPE(uint8_t *) pMSREntryLoad;
354
355	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
356	RTR0MEMOBJ pMemObjScratch;
357	RTHCPHYS pScratchPhys;
358	R0PTRTYPE(uint8_t *) pScratch;
359	#endif
360	/** R0 memory object for the MSR exit store page (guest MSRs). */
361	RTR0MEMOBJ pMemObjMSRExitStore;
362	/** Physical address of the MSR exit store page (guest MSRs). */
363	RTHCPHYS pMSRExitStorePhys;
364	/** Virtual address of the MSR exit store page (guest MSRs). */
365	R0PTRTYPE(uint8_t *) pMSRExitStore;
366
367	/** R0 memory object for the MSR exit load page (host MSRs). */
368	RTR0MEMOBJ pMemObjMSRExitLoad;
369	/** Physical address of the MSR exit load page (host MSRs). */
370	RTHCPHYS pMSRExitLoadPhys;
371	/** Virtual address of the MSR exit load page (host MSRs). */
372	R0PTRTYPE(uint8_t *) pMSRExitLoad;
373
374	/** Ring 0 handlers for VT-x. */
375	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
376
377	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
378	uint32_t u32Alignment;
379	#endif
380	/** Host CR4 value (set by ring-0 VMX init) */
381	uint64_t hostCR4;
382
383	/** VMX MSR values */
384	struct
385	{
386	uint64_t feature_ctrl;
387	uint64_t vmx_basic_info;
388	VMX_CAPABILITY vmx_pin_ctls;
389	VMX_CAPABILITY vmx_proc_ctls;
390	VMX_CAPABILITY vmx_proc_ctls2;
391	VMX_CAPABILITY vmx_exit;
392	VMX_CAPABILITY vmx_entry;
393	uint64_t vmx_misc;
394	uint64_t vmx_cr0_fixed0;
395	uint64_t vmx_cr0_fixed1;
396	uint64_t vmx_cr4_fixed0;
397	uint64_t vmx_cr4_fixed1;
398	uint64_t vmx_vmcs_enum;
399	uint64_t vmx_eptcaps;
400	} msr;
401
402	/** Flush types for invept & invvpid; they depend on capabilities. */
403	VMX_FLUSH enmFlushPage;
404	VMX_FLUSH enmFlushContext;
405	} vmx;
406
407	struct
408	{
409	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
410	bool fSupported;
411	/** Set when we've enabled SVM. */
412	bool fEnabled;
413	/** Set if erratum 170 affects the AMD cpu. */
414	bool fAlwaysFlushTLB;
415	bool u8Alignment;
416
417	/** R0 memory object for the IO bitmap (12kb). */
418	RTR0MEMOBJ pMemObjIOBitmap;
419	/** Physical address of the IO bitmap (12kb). */
420	RTHCPHYS pIOBitmapPhys;
421	/** Virtual address of the IO bitmap. */
422	R0PTRTYPE(void *) pIOBitmap;
423
424	/* HWCR msr (for diagnostics) */
425	uint64_t msrHWCR;
426
427	/** SVM revision. */
428	uint32_t u32Rev;
429
430	/** SVM feature bits from cpuid 0x8000000a */
431	uint32_t u32Features;
432	} svm;
433
434	/**
435	* AVL tree with all patches (active or disabled) sorted by guest instruction address
436	*/
437	AVLOU32TREE PatchTree;
438	uint32_t cPatches;
439	HWACCMTPRPATCH aPatches[64];
440
441	struct
442	{
443	uint32_t u32AMDFeatureECX;
444	uint32_t u32AMDFeatureEDX;
445	} cpuid;
446
447	/** Saved error from detection */
448	int32_t lLastError;
449
450	/** HWACCMR0Init was run */
451	bool fHWACCMR0Init;
452	bool u8Alignment1[7];
453
454	STAMCOUNTER StatTPRPatchSuccess;
455	STAMCOUNTER StatTPRPatchFailure;
456	STAMCOUNTER StatTPRReplaceSuccess;
457	STAMCOUNTER StatTPRReplaceFailure;
458	} HWACCM;
459	/** Pointer to HWACCM VM instance data. */
460	typedef HWACCM *PHWACCM;
461
462	/* Maximum number of cached entries. */
463	#define VMCSCACHE_MAX_ENTRY 128
464
465	/* Structure for storing read and write VMCS actions. */
466	typedef struct VMCSCACHE
467	{
468	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
469	/* Magic marker for searching in crash dumps. */
470	uint8_t aMagic[16];
471	uint64_t uMagic;
472	uint64_t u64TimeEntry;
473	uint64_t u64TimeSwitch;
474	uint64_t cResume;
475	uint64_t interPD;
476	uint64_t pSwitcher;
477	uint32_t uPos;
478	uint32_t idCpu;
479	#endif
480	/* CR2 is saved here for EPT syncing. */
481	uint64_t cr2;
482	struct
483	{
484	uint32_t cValidEntries;
485	uint32_t uAlignment;
486	uint32_t aField[VMCSCACHE_MAX_ENTRY];
487	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
488	} Write;
489	struct
490	{
491	uint32_t cValidEntries;
492	uint32_t uAlignment;
493	uint32_t aField[VMCSCACHE_MAX_ENTRY];
494	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
495	} Read;
496	#ifdef DEBUG
497	struct
498	{
499	RTHCPHYS pPageCpuPhys;
500	RTHCPHYS pVMCSPhys;
501	RTGCPTR pCache;
502	RTGCPTR pCtx;
503	} TestIn;
504	struct
505	{
506	RTHCPHYS pVMCSPhys;
507	RTGCPTR pCache;
508	RTGCPTR pCtx;
509	uint64_t eflags;
510	uint64_t cr8;
511	} TestOut;
512	struct
513	{
514	uint64_t param1;
515	uint64_t param2;
516	uint64_t param3;
517	uint64_t param4;
518	} ScratchPad;
519	#endif
520	} VMCSCACHE;
521	/** Pointer to VMCSCACHE. */
522	typedef VMCSCACHE *PVMCSCACHE;
523
524	/** VMX StartVM function. */
525	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
526	/** Pointer to a VMX StartVM function. */
527	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
528
529	/** SVM VMRun function. */
530	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
531	/** Pointer to a SVM VMRun function. */
532	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
533
534	/**
535	* HWACCM VMCPU Instance data.
536	*/
537	typedef struct HWACCMCPU
538	{
539	/** Old style FPU reporting trap mask override performed (optimization) */
540	bool fFPUOldStyleOverride;
541
542	/** Set if we don't have to flush the TLB on VM entry. */
543	bool fResumeVM;
544
545	/** Set if we need to flush the TLB during the world switch. */
546	bool fForceTLBFlush;
547
548	/** Set when we're using VT-x or AMD-V at that moment. */
549	bool fActive;
550
551	/** Set when the TLB has been checked until we return from the world switch. */
552	volatile uint8_t fCheckedTLBFlush;
553	uint8_t bAlignment[3];
554
555	/** HWACCM_CHANGED_* flags. */
556	RTUINT fContextUseFlags;
557
558	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
559	RTCPUID idLastCpu;
560
561	/** TLB flush count */
562	RTUINT cTLBFlushes;
563
564	/** Current ASID in use by the VM */
565	RTUINT uCurrentASID;
566
567	/** World switch exit counter. */
568	volatile uint32_t cWorldSwitchExit;
569	uint32_t u32Alignment;
570
571	struct
572	{
573	/** Physical address of the VM control structure (VMCS). */
574	RTHCPHYS pVMCSPhys;
575	/** R0 memory object for the VM control structure (VMCS). */
576	RTR0MEMOBJ pMemObjVMCS;
577	/** Virtual address of the VM control structure (VMCS). */
578	R0PTRTYPE(void *) pVMCS;
579
580	/** Ring 0 handlers for VT-x. */
581	PFNHWACCMVMXSTARTVM pfnStartVM;
582
583	#if HC_ARCH_BITS == 32
584	uint32_t u32Alignment;
585	#endif
586
587	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
588	uint64_t proc_ctls;
589
590	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
591	uint64_t proc_ctls2;
592
593	/** Physical address of the virtual APIC page for TPR caching. */
594	RTHCPHYS pVAPICPhys;
595	/** R0 memory object for the virtual APIC page for TPR caching. */
596	RTR0MEMOBJ pMemObjVAPIC;
597	/** Virtual address of the virtual APIC page for TPR caching. */
598	R0PTRTYPE(uint8_t *) pVAPIC;
599
600	/** Current CR0 mask. */
601	uint64_t cr0_mask;
602	/** Current CR4 mask. */
603	uint64_t cr4_mask;
604
605	/** Current EPTP. */
606	RTHCPHYS GCPhysEPTP;
607
608	/** Physical address of the MSR bitmap (1 page). */
609	RTHCPHYS pMSRBitmapPhys;
610	/** R0 memory object for the MSR bitmap (1 page). */
611	RTR0MEMOBJ pMemObjMSRBitmap;
612	/** Virtual address of the MSR bitmap (1 page). */
613	R0PTRTYPE(uint8_t *) pMSRBitmap;
614
615	#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
616	/** Physical address of the guest MSR load area (1 page). */
617	RTHCPHYS pGuestMSRPhys;
618	/** R0 memory object for the guest MSR load area (1 page). */
619	RTR0MEMOBJ pMemObjGuestMSR;
620	/** Virtual address of the guest MSR load area (1 page). */
621	R0PTRTYPE(uint8_t *) pGuestMSR;
622
623	/** Physical address of the MSR load area (1 page). */
624	RTHCPHYS pHostMSRPhys;
625	/** R0 memory object for the MSR load area (1 page). */
626	RTR0MEMOBJ pMemObjHostMSR;
627	/** Virtual address of the MSR load area (1 page). */
628	R0PTRTYPE(uint8_t *) pHostMSR;
629	#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
630
631	/* Number of automatically loaded/restored MSRs. */
632	uint32_t cCachedMSRs;
633	uint32_t uAlignement;
634
635	/* Last use TSC offset value. (cached) */
636	uint64_t u64TSCOffset;
637
638	/** VMCS cache. */
639	VMCSCACHE VMCSCache;
640
641	/** Real-mode emulation state. */
642	struct
643	{
644	X86EFLAGS eflags;
645	uint32_t fValid;
646	} RealMode;
647
648	struct
649	{
650	uint64_t u64VMCSPhys;
651	uint32_t ulVMCSRevision;
652	uint32_t ulInstrError;
653	uint32_t ulExitReason;
654	RTCPUID idEnteredCpu;
655	RTCPUID idCurrentCpu;
656	uint32_t padding;
657	} lasterror;
658
659	/** The last seen guest paging mode (by VT-x). */
660	PGMMODE enmLastSeenGuestMode;
661	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
662	PGMMODE enmCurrGuestMode;
663	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
664	PGMMODE enmPrevGuestMode;
665	} vmx;
666
667	struct
668	{
669	/** R0 memory object for the host VM control block (VMCB). */
670	RTR0MEMOBJ pMemObjVMCBHost;
671	/** Physical address of the host VM control block (VMCB). */
672	RTHCPHYS pVMCBHostPhys;
673	/** Virtual address of the host VM control block (VMCB). */
674	R0PTRTYPE(void *) pVMCBHost;
675
676	/** R0 memory object for the VM control block (VMCB). */
677	RTR0MEMOBJ pMemObjVMCB;
678	/** Physical address of the VM control block (VMCB). */
679	RTHCPHYS pVMCBPhys;
680	/** Virtual address of the VM control block (VMCB). */
681	R0PTRTYPE(void *) pVMCB;
682
683	/** Ring 0 handlers for VT-x. */
684	PFNHWACCMSVMVMRUN pfnVMRun;
685
686	/** R0 memory object for the MSR bitmap (8kb). */
687	RTR0MEMOBJ pMemObjMSRBitmap;
688	/** Physical address of the MSR bitmap (8kb). */
689	RTHCPHYS pMSRBitmapPhys;
690	/** Virtual address of the MSR bitmap. */
691	R0PTRTYPE(void *) pMSRBitmap;
692	} svm;
693
694	/** Event injection state. */
695	struct
696	{
697	uint32_t fPending;
698	uint32_t errCode;
699	uint64_t intInfo;
700	} Event;
701
702	/** IO Block emulation state. */
703	struct
704	{
705	bool fEnabled;
706	uint8_t u8Align[7];
707
708	/** RIP at the start of the io code we wish to emulate in the recompiler. */
709	RTGCPTR GCPtrFunctionEip;
710
711	uint64_t cr0;
712	} EmulateIoBlock;
713
714	struct
715	{
716	/* Pending IO operation type. */
717	HWACCMPENDINGIO enmType;
718	uint32_t uPadding;
719	RTGCPTR GCPtrRip;
720	RTGCPTR GCPtrRipNext;
721	union
722	{
723	struct
724	{
725	unsigned uPort;
726	unsigned uAndVal;
727	unsigned cbSize;
728	} Port;
729	uint64_t aRaw[2];
730	} s;
731	} PendingIO;
732
733	/** Currenty shadow paging mode. */
734	PGMMODE enmShadowMode;
735
736	/** The CPU ID of the CPU currently owning the VMCS. Set in
737	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
738	RTCPUID idEnteredCpu;
739
740	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
741	struct
742	{
743	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
744	unsigned cPages;
745	} TlbShootdown;
746
747	/** For saving stack space, the disassembler state is allocated here instead of
748	* on the stack.
749	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
750	union
751	{
752	/** The disassembler scratch space. */
753	DISCPUSTATE DisState;
754	/** Padding. */
755	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
756	};
757
758	RTUINT padding2[1];
759
760	STAMPROFILEADV StatEntry;
761	STAMPROFILEADV StatExit1;
762	STAMPROFILEADV StatExit2;
763	#if 1 /* temporary for tracking down darwin issues. */
764	STAMPROFILEADV StatExit2Sub1;
765	STAMPROFILEADV StatExit2Sub2;
766	STAMPROFILEADV StatExit2Sub3;
767	#endif
768	STAMPROFILEADV StatInGC;
769
770	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
771	STAMPROFILEADV StatWorldSwitch3264;
772	#endif
773	STAMPROFILEADV StatPoke;
774	STAMPROFILEADV StatSpinPoke;
775	STAMPROFILEADV StatSpinPokeFailed;
776
777	STAMCOUNTER StatIntInject;
778
779	STAMCOUNTER StatExitShadowNM;
780	STAMCOUNTER StatExitGuestNM;
781	STAMCOUNTER StatExitShadowPF;
782	STAMCOUNTER StatExitGuestPF;
783	STAMCOUNTER StatExitGuestUD;
784	STAMCOUNTER StatExitGuestSS;
785	STAMCOUNTER StatExitGuestNP;
786	STAMCOUNTER StatExitGuestGP;
787	STAMCOUNTER StatExitGuestDE;
788	STAMCOUNTER StatExitGuestDB;
789	STAMCOUNTER StatExitGuestMF;
790	STAMCOUNTER StatExitInvpg;
791	STAMCOUNTER StatExitInvd;
792	STAMCOUNTER StatExitCpuid;
793	STAMCOUNTER StatExitRdtsc;
794	STAMCOUNTER StatExitRdpmc;
795	STAMCOUNTER StatExitCli;
796	STAMCOUNTER StatExitSti;
797	STAMCOUNTER StatExitPushf;
798	STAMCOUNTER StatExitPopf;
799	STAMCOUNTER StatExitIret;
800	STAMCOUNTER StatExitInt;
801	STAMCOUNTER StatExitCRxWrite[16];
802	STAMCOUNTER StatExitCRxRead[16];
803	STAMCOUNTER StatExitDRxWrite;
804	STAMCOUNTER StatExitDRxRead;
805	STAMCOUNTER StatExitRdmsr;
806	STAMCOUNTER StatExitWrmsr;
807	STAMCOUNTER StatExitCLTS;
808	STAMCOUNTER StatExitHlt;
809	STAMCOUNTER StatExitMwait;
810	STAMCOUNTER StatExitLMSW;
811	STAMCOUNTER StatExitIOWrite;
812	STAMCOUNTER StatExitIORead;
813	STAMCOUNTER StatExitIOStringWrite;
814	STAMCOUNTER StatExitIOStringRead;
815	STAMCOUNTER StatExitIrqWindow;
816	STAMCOUNTER StatExitMaxResume;
817	STAMCOUNTER StatExitPreemptPending;
818	STAMCOUNTER StatIntReinject;
819	STAMCOUNTER StatPendingHostIrq;
820
821	STAMCOUNTER StatFlushPage;
822	STAMCOUNTER StatFlushPageManual;
823	STAMCOUNTER StatFlushPhysPageManual;
824	STAMCOUNTER StatFlushTLB;
825	STAMCOUNTER StatFlushTLBManual;
826	STAMCOUNTER StatFlushPageInvlpg;
827	STAMCOUNTER StatFlushTLBWorldSwitch;
828	STAMCOUNTER StatNoFlushTLBWorldSwitch;
829	STAMCOUNTER StatFlushTLBCRxChange;
830	STAMCOUNTER StatFlushASID;
831	STAMCOUNTER StatFlushTLBInvlpga;
832	STAMCOUNTER StatTlbShootdown;
833	STAMCOUNTER StatTlbShootdownFlush;
834
835	STAMCOUNTER StatSwitchGuestIrq;
836	STAMCOUNTER StatSwitchToR3;
837
838	STAMCOUNTER StatTSCOffset;
839	STAMCOUNTER StatTSCIntercept;
840	STAMCOUNTER StatTSCInterceptOverFlow;
841
842	STAMCOUNTER StatExitReasonNPF;
843	STAMCOUNTER StatDRxArmed;
844	STAMCOUNTER StatDRxContextSwitch;
845	STAMCOUNTER StatDRxIOCheck;
846
847
848	#ifdef VBOX_WITH_STATISTICS
849	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
850	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
851	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
852	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
853	#endif
854	} HWACCMCPU;
855	/** Pointer to HWACCM VM instance data. */
856	typedef HWACCMCPU *PHWACCMCPU;
857
858
859	#ifdef IN_RING0
860
861	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
862	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
863
864
865	#ifdef VBOX_STRICT
866	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
867	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
868	#else
869	# define HWACCMDumpRegs(a, b ,c) do { } while (0)
870	# define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
871	#endif
872
873	/* Dummy callback handlers. */
874	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
875	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
876	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
877	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
878	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
879	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
880	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
881	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
882	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
883	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
884
885	# ifdef VBOX_WITH_KERNEL_USING_XMM
886	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
887	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
888	# endif
889
890	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
891	/**
892	* Gets 64-bit GDTR and IDTR on darwin.
893	* @param pGdtr Where to store the 64-bit GDTR.
894	* @param pIdtr Where to store the 64-bit IDTR.
895	*/
896	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
897
898	/**
899	* Gets 64-bit CR3 on darwin.
900	* @returns CR3
901	*/
902	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
903	# endif
904
905	#endif /* IN_RING0 */
906
907	/** @} */
908
909	RT_C_DECLS_END
910
911	#endif
912

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 25776

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