HWACCMInternal.h@ 21990

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1	/* $Id: HWACCMInternal.h 21989 2009-08-05 12:22:13Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36	#include <iprt/avl.h>
37
38	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
39	/* Enable 64 bits guest support. */
40	# define VBOX_ENABLE_64_BITS_GUESTS
41	#endif
42
43	#define VMX_USE_CACHED_VMCS_ACCESSES
44	#define HWACCM_VMX_EMULATE_REALMODE
45	#define HWACCM_VTX_WITH_EPT
46	#define HWACCM_VTX_WITH_VPID
47
48	RT_C_DECLS_BEGIN
49
50
51	/** @defgroup grp_hwaccm_int Internal
52	* @ingroup grp_hwaccm
53	* @internal
54	* @{
55	*/
56
57
58	/** Maximum number of exit reason statistics counters. */
59	#define MAX_EXITREASON_STAT 0x100
60	#define MASK_EXITREASON_STAT 0xff
61	#define MASK_INJECT_IRQ_STAT 0xff
62
63	/** @name Changed flags
64	* These flags are used to keep track of which important registers that
65	* have been changed since last they were reset.
66	* @{
67	*/
68	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
69	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
70	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
71	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
72	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
73	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
74	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
75	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
76	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
77	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
78	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
79	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
80
81	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
82	\| HWACCM_CHANGED_GUEST_CR0 \
83	\| HWACCM_CHANGED_GUEST_CR3 \
84	\| HWACCM_CHANGED_GUEST_CR4 \
85	\| HWACCM_CHANGED_GUEST_GDTR \
86	\| HWACCM_CHANGED_GUEST_IDTR \
87	\| HWACCM_CHANGED_GUEST_LDTR \
88	\| HWACCM_CHANGED_GUEST_TR \
89	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
90	\| HWACCM_CHANGED_GUEST_FPU \
91	\| HWACCM_CHANGED_GUEST_DEBUG \
92	\| HWACCM_CHANGED_HOST_CONTEXT)
93
94	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
95	\| HWACCM_CHANGED_GUEST_CR0 \
96	\| HWACCM_CHANGED_GUEST_CR3 \
97	\| HWACCM_CHANGED_GUEST_CR4 \
98	\| HWACCM_CHANGED_GUEST_GDTR \
99	\| HWACCM_CHANGED_GUEST_IDTR \
100	\| HWACCM_CHANGED_GUEST_LDTR \
101	\| HWACCM_CHANGED_GUEST_TR \
102	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
103	\| HWACCM_CHANGED_GUEST_DEBUG \
104	\| HWACCM_CHANGED_GUEST_FPU)
105
106	/** @} */
107
108	/** @name Intercepted traps
109	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
110	* Currently #NM and #PF only
111	*/
112	#ifdef VBOX_STRICT
113	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
114	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
115	#else
116	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
117	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
118	#endif
119	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
120	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
121	/** @} */
122
123
124	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
125	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
126
127	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
128	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
129	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
130	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
131	/** Total guest mapped memory needed. */
132	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
133
134	/* Enable for TPR guest patching. */
135	//#define VBOX_HWACCM_WITH_GUEST_PATCHING
136
137	/** HWACCM SSM version
138	*/
139	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
140	#define HWACCM_SSM_VERSION 5
141	#define HWACCM_SSM_VERSION_NO_PATCHING 4
142	#else
143	#define HWACCM_SSM_VERSION 4
144	#define HWACCM_SSM_VERSION_NO_PATCHING 4
145	#endif
146	#define HWACCM_SSM_VERSION_2_0_X 3
147
148	/* Per-cpu information. (host) */
149	typedef struct
150	{
151	RTCPUID idCpu;
152
153	RTR0MEMOBJ pMemObj;
154	/* Current ASID (AMD-V)/VPID (Intel) */
155	uint32_t uCurrentASID;
156	/* TLB flush count */
157	uint32_t cTLBFlushes;
158
159	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
160	bool fFlushTLB;
161
162	/** Configured for VT-x or AMD-V. */
163	bool fConfigured;
164
165	/** In use by our code. (for power suspend) */
166	volatile bool fInUse;
167	} HWACCM_CPUINFO;
168	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
169
170	/* VT-x capability qword. */
171	typedef union
172	{
173	struct
174	{
175	uint32_t disallowed0;
176	uint32_t allowed1;
177	} n;
178	uint64_t u;
179	} VMX_CAPABILITY;
180
181	typedef enum
182	{
183	HWACCMPENDINGIO_INVALID = 0,
184	HWACCMPENDINGIO_PORT_READ,
185	HWACCMPENDINGIO_PORT_WRITE,
186	HWACCMPENDINGIO_STRING_READ,
187	HWACCMPENDINGIO_STRING_WRITE,
188	/** The usual 32-bit paranoia. */
189	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
190	} HWACCMPENDINGIO;
191
192
193	typedef enum
194	{
195	HWACCMTPRINSTR_INVALID,
196	HWACCMTPRINSTR_READ,
197	HWACCMTPRINSTR_READ_SHR4,
198	HWACCMTPRINSTR_WRITE_REG,
199	HWACCMTPRINSTR_WRITE_IMM,
200	HWACCMTPRINSTR_JUMP_REPLACEMENT,
201	/** The usual 32-bit paranoia. */
202	HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
203	} HWACCMTPRINSTR;
204
205	typedef struct
206	{
207	/** The key is the address of patched instruction. (32 bits GC ptr) */
208	AVLOU32NODECORE Core;
209	/** Original opcode. */
210	uint8_t aOpcode[16];
211	/** Instruction size. */
212	uint32_t cbOp;
213	/** Replacement opcode. */
214	uint8_t aNewOpcode[16];
215	/** Replacement instruction size. */
216	uint32_t cbNewOp;
217	/** Instruction type. */
218	HWACCMTPRINSTR enmType;
219	/** Source operand. */
220	uint32_t uSrcOperand;
221	/** Destination operand. */
222	uint32_t uDstOperand;
223	/** Number of times the instruction caused a fault. */
224	uint32_t cFaults;
225	/** Patch address of the jump replacement. */
226	RTGCPTR32 pJumpTarget;
227	} HWACCMTPRPATCH;
228	/** Pointer to HWACCMTPRPATCH. */
229	typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
230
231	/**
232	* Switcher function, HC to RC.
233	*
234	* @param pVM The VM handle.
235	* @returns Return code indicating the action to take.
236	*/
237	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
238	/** Pointer to switcher function. */
239	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
240
241	/**
242	* HWACCM VM Instance data.
243	* Changes to this must checked against the padding of the cfgm union in VM!
244	*/
245	typedef struct HWACCM
246	{
247	/** Set when we've initialized VMX or SVM. */
248	bool fInitialized;
249
250	/** Set when hardware acceleration is allowed. */
251	bool fAllowed;
252
253	/** Set if nested paging is enabled. */
254	bool fNestedPaging;
255
256	/** Set if nested paging is allowed. */
257	bool fAllowNestedPaging;
258
259	/** Set if we can support 64-bit guests or not. */
260	bool fAllow64BitGuests;
261
262	/** Set if an IO-APIC is configured for this VM. */
263	bool fHasIoApic;
264
265	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
266	* naturally. */
267	bool padding[2];
268
269	/** And mask for copying register contents. */
270	uint64_t u64RegisterMask;
271
272	/** Maximum ASID allowed. */
273	RTUINT uMaxASID;
274
275	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
276	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
277	uint32_t cMaxResumeLoops;
278
279	/** Guest allocated memory for patching purposes. */
280	RTGCPTR pGuestPatchMem;
281	/** Current free pointer inside the patch block. */
282	RTGCPTR pFreeGuestPatchMem;
283	/** Size of the guest patch memory block. */
284	uint32_t cbGuestPatchMem;
285	uint32_t uPadding1;
286
287	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
288	/** 32 to 64 bits switcher entrypoint. */
289	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
290
291	/* AMD-V 64 bits vmrun handler */
292	RTRCPTR pfnSVMGCVMRun64;
293
294	/* VT-x 64 bits vmlaunch handler */
295	RTRCPTR pfnVMXGCStartVM64;
296
297	/* RC handler to setup the 64 bits FPU state. */
298	RTRCPTR pfnSaveGuestFPU64;
299
300	/* RC handler to setup the 64 bits debug state. */
301	RTRCPTR pfnSaveGuestDebug64;
302
303	/* Test handler */
304	RTRCPTR pfnTest64;
305
306	RTRCPTR uAlignment[2];
307	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
308	uint32_t u32Alignment[1]; */
309	#endif
310
311	struct
312	{
313	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
314	bool fSupported;
315
316	/** Set when we've enabled VMX. */
317	bool fEnabled;
318
319	/** Set if VPID is supported. */
320	bool fVPID;
321
322	/** Set if VT-x VPID is allowed. */
323	bool fAllowVPID;
324
325	/** Virtual address of the TSS page used for real mode emulation. */
326	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
327
328	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
329	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
330
331	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
332	RTR0MEMOBJ pMemObjAPIC;
333	/** Physical address of the APIC physical page (serves for filtering accesses). */
334	RTHCPHYS pAPICPhys;
335	/** Virtual address of the APIC physical page (serves for filtering accesses). */
336	R0PTRTYPE(uint8_t *) pAPIC;
337
338	/** R0 memory object for the MSR bitmap (1 page). */
339	RTR0MEMOBJ pMemObjMSRBitmap;
340	/** Physical address of the MSR bitmap (1 page). */
341	RTHCPHYS pMSRBitmapPhys;
342	/** Virtual address of the MSR bitmap (1 page). */
343	R0PTRTYPE(uint8_t *) pMSRBitmap;
344
345	/** R0 memory object for the MSR entry load page (guest MSRs). */
346	RTR0MEMOBJ pMemObjMSREntryLoad;
347	/** Physical address of the MSR entry load page (guest MSRs). */
348	RTHCPHYS pMSREntryLoadPhys;
349	/** Virtual address of the MSR entry load page (guest MSRs). */
350	R0PTRTYPE(uint8_t *) pMSREntryLoad;
351
352	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
353	RTR0MEMOBJ pMemObjScratch;
354	RTHCPHYS pScratchPhys;
355	R0PTRTYPE(uint8_t *) pScratch;
356	#endif
357	/** R0 memory object for the MSR exit store page (guest MSRs). */
358	RTR0MEMOBJ pMemObjMSRExitStore;
359	/** Physical address of the MSR exit store page (guest MSRs). */
360	RTHCPHYS pMSRExitStorePhys;
361	/** Virtual address of the MSR exit store page (guest MSRs). */
362	R0PTRTYPE(uint8_t *) pMSRExitStore;
363
364	/** R0 memory object for the MSR exit load page (host MSRs). */
365	RTR0MEMOBJ pMemObjMSRExitLoad;
366	/** Physical address of the MSR exit load page (host MSRs). */
367	RTHCPHYS pMSRExitLoadPhys;
368	/** Virtual address of the MSR exit load page (host MSRs). */
369	R0PTRTYPE(uint8_t *) pMSRExitLoad;
370
371	/** Ring 0 handlers for VT-x. */
372	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
373
374	/** Host CR4 value (set by ring-0 VMX init) */
375	uint64_t hostCR4;
376
377	/** VMX MSR values */
378	struct
379	{
380	uint64_t feature_ctrl;
381	uint64_t vmx_basic_info;
382	VMX_CAPABILITY vmx_pin_ctls;
383	VMX_CAPABILITY vmx_proc_ctls;
384	VMX_CAPABILITY vmx_proc_ctls2;
385	VMX_CAPABILITY vmx_exit;
386	VMX_CAPABILITY vmx_entry;
387	uint64_t vmx_misc;
388	uint64_t vmx_cr0_fixed0;
389	uint64_t vmx_cr0_fixed1;
390	uint64_t vmx_cr4_fixed0;
391	uint64_t vmx_cr4_fixed1;
392	uint64_t vmx_vmcs_enum;
393	uint64_t vmx_eptcaps;
394	} msr;
395
396	/** Flush types for invept & invvpid; they depend on capabilities. */
397	VMX_FLUSH enmFlushPage;
398	VMX_FLUSH enmFlushContext;
399	} vmx;
400
401	struct
402	{
403	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
404	bool fSupported;
405	/** Set when we've enabled SVM. */
406	bool fEnabled;
407	/** Set if erratum 170 affects the AMD cpu. */
408	bool fAlwaysFlushTLB;
409	/** Set when TPR patching is active. */
410	bool fTPRPatchingActive;
411
412	/** R0 memory object for the IO bitmap (12kb). */
413	RTR0MEMOBJ pMemObjIOBitmap;
414	/** Physical address of the IO bitmap (12kb). */
415	RTHCPHYS pIOBitmapPhys;
416	/** Virtual address of the IO bitmap. */
417	R0PTRTYPE(void *) pIOBitmap;
418
419	/** R0 memory object for the MSR bitmap (8kb). */
420	RTR0MEMOBJ pMemObjMSRBitmap;
421	/** Physical address of the MSR bitmap (8kb). */
422	RTHCPHYS pMSRBitmapPhys;
423	/** Virtual address of the MSR bitmap. */
424	R0PTRTYPE(void *) pMSRBitmap;
425
426	/** SVM revision. */
427	uint32_t u32Rev;
428
429	/** SVM feature bits from cpuid 0x8000000a */
430	uint32_t u32Features;
431
432	/**
433	* AVL tree with all patches (active or disabled) sorted by guest instruction address
434	*/
435	AVLOU32TREE PatchTree;
436	uint32_t cPatches;
437	HWACCMTPRPATCH aPatches[64];
438	} svm;
439
440	struct
441	{
442	uint32_t u32AMDFeatureECX;
443	uint32_t u32AMDFeatureEDX;
444	} cpuid;
445
446	/** Saved error from detection */
447	int32_t lLastError;
448
449	/** HWACCMR0Init was run */
450	bool fHWACCMR0Init;
451	bool u8Alignment[7];
452
453	STAMCOUNTER StatTPRPatchSuccess;
454	STAMCOUNTER StatTPRPatchFailure;
455	STAMCOUNTER StatTPRReplaceSuccess;
456	STAMCOUNTER StatTPRReplaceFailure;
457	} HWACCM;
458	/** Pointer to HWACCM VM instance data. */
459	typedef HWACCM *PHWACCM;
460
461	/* Maximum number of cached entries. */
462	#define VMCSCACHE_MAX_ENTRY 128
463
464	/* Structure for storing read and write VMCS actions. */
465	typedef struct VMCSCACHE
466	{
467	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
468	/* Magic marker for searching in crash dumps. */
469	uint8_t aMagic[16];
470	uint64_t uMagic;
471	uint64_t u64TimeEntry;
472	uint64_t u64TimeSwitch;
473	uint64_t cResume;
474	uint64_t interPD;
475	uint64_t pSwitcher;
476	uint32_t uPos;
477	uint32_t idCpu;
478	#endif
479	/* CR2 is saved here for EPT syncing. */
480	uint64_t cr2;
481	struct
482	{
483	uint32_t cValidEntries;
484	uint32_t uAlignment;
485	uint32_t aField[VMCSCACHE_MAX_ENTRY];
486	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
487	} Write;
488	struct
489	{
490	uint32_t cValidEntries;
491	uint32_t uAlignment;
492	uint32_t aField[VMCSCACHE_MAX_ENTRY];
493	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
494	} Read;
495	#ifdef DEBUG
496	struct
497	{
498	RTHCPHYS pPageCpuPhys;
499	RTHCPHYS pVMCSPhys;
500	RTGCPTR pCache;
501	RTGCPTR pCtx;
502	} TestIn;
503	struct
504	{
505	RTHCPHYS pVMCSPhys;
506	RTGCPTR pCache;
507	RTGCPTR pCtx;
508	uint64_t eflags;
509	uint64_t cr8;
510	} TestOut;
511	struct
512	{
513	uint64_t param1;
514	uint64_t param2;
515	uint64_t param3;
516	uint64_t param4;
517	} ScratchPad;
518	#endif
519	} VMCSCACHE;
520	/** Pointer to VMCSCACHE. */
521	typedef VMCSCACHE *PVMCSCACHE;
522
523	/** VMX StartVM function. */
524	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
525	/** Pointer to a VMX StartVM function. */
526	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
527
528	/** SVM VMRun function. */
529	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
530	/** Pointer to a SVM VMRun function. */
531	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
532
533	/**
534	* HWACCM VMCPU Instance data.
535	*/
536	typedef struct HWACCMCPU
537	{
538	/** Old style FPU reporting trap mask override performed (optimization) */
539	bool fFPUOldStyleOverride;
540
541	/** Set if we don't have to flush the TLB on VM entry. */
542	bool fResumeVM;
543
544	/** Set if we need to flush the TLB during the world switch. */
545	bool fForceTLBFlush;
546
547	/** Set when we're using VT-x or AMD-V at that moment. */
548	bool fActive;
549
550	/** HWACCM_CHANGED_* flags. */
551	RTUINT fContextUseFlags;
552
553	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
554	RTCPUID idLastCpu;
555
556	/* TLB flush count */
557	RTUINT cTLBFlushes;
558
559	/* Current ASID in use by the VM */
560	RTUINT uCurrentASID;
561
562	struct
563	{
564	/** R0 memory object for the VM control structure (VMCS). */
565	RTR0MEMOBJ pMemObjVMCS;
566	/** Physical address of the VM control structure (VMCS). */
567	RTHCPHYS pVMCSPhys;
568	/** Virtual address of the VM control structure (VMCS). */
569	R0PTRTYPE(void *) pVMCS;
570
571	/** Ring 0 handlers for VT-x. */
572	PFNHWACCMVMXSTARTVM pfnStartVM;
573
574	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
575	uint64_t proc_ctls;
576
577	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
578	uint64_t proc_ctls2;
579
580	/** R0 memory object for the virtual APIC page for TPR caching. */
581	RTR0MEMOBJ pMemObjVAPIC;
582	/** Physical address of the virtual APIC page for TPR caching. */
583	RTHCPHYS pVAPICPhys;
584	/** Virtual address of the virtual APIC page for TPR caching. */
585	R0PTRTYPE(uint8_t *) pVAPIC;
586
587	/** Current CR0 mask. */
588	uint64_t cr0_mask;
589	/** Current CR4 mask. */
590	uint64_t cr4_mask;
591
592	/** Current EPTP. */
593	RTHCPHYS GCPhysEPTP;
594
595	/** VMCS cache. */
596	VMCSCACHE VMCSCache;
597
598	/** Real-mode emulation state. */
599	struct
600	{
601	X86EFLAGS eflags;
602	uint32_t fValid;
603	} RealMode;
604
605	struct
606	{
607	uint64_t u64VMCSPhys;
608	uint32_t ulVMCSRevision;
609	uint32_t ulInstrError;
610	uint32_t ulExitReason;
611	RTCPUID idEnteredCpu;
612	RTCPUID idCurrentCpu;
613	uint32_t padding;
614	} lasterror;
615
616	/** The last seen guest paging mode (by VT-x). */
617	PGMMODE enmLastSeenGuestMode;
618	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
619	PGMMODE enmCurrGuestMode;
620	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
621	PGMMODE enmPrevGuestMode;
622	} vmx;
623
624	struct
625	{
626	/** R0 memory object for the host VM control block (VMCB). */
627	RTR0MEMOBJ pMemObjVMCBHost;
628	/** Physical address of the host VM control block (VMCB). */
629	RTHCPHYS pVMCBHostPhys;
630	/** Virtual address of the host VM control block (VMCB). */
631	R0PTRTYPE(void *) pVMCBHost;
632
633	/** R0 memory object for the VM control block (VMCB). */
634	RTR0MEMOBJ pMemObjVMCB;
635	/** Physical address of the VM control block (VMCB). */
636	RTHCPHYS pVMCBPhys;
637	/** Virtual address of the VM control block (VMCB). */
638	R0PTRTYPE(void *) pVMCB;
639
640	/** Ring 0 handlers for VT-x. */
641	PFNHWACCMSVMVMRUN pfnVMRun;
642
643	} svm;
644
645	/** Event injection state. */
646	struct
647	{
648	uint32_t fPending;
649	uint32_t errCode;
650	uint64_t intInfo;
651	} Event;
652
653	/** IO Block emulation state. */
654	struct
655	{
656	bool fEnabled;
657	uint8_t u8Align[7];
658
659	/** RIP at the start of the io code we wish to emulate in the recompiler. */
660	RTGCPTR GCPtrFunctionEip;
661
662	uint64_t cr0;
663	} EmulateIoBlock;
664
665	struct
666	{
667	/* Pending IO operation type. */
668	HWACCMPENDINGIO enmType;
669	uint32_t uPadding;
670	RTGCPTR GCPtrRip;
671	RTGCPTR GCPtrRipNext;
672	union
673	{
674	struct
675	{
676	unsigned uPort;
677	unsigned uAndVal;
678	unsigned cbSize;
679	} Port;
680	uint64_t aRaw[2];
681	} s;
682	} PendingIO;
683
684	/** Currenty shadow paging mode. */
685	PGMMODE enmShadowMode;
686
687	/** The CPU ID of the CPU currently owning the VMCS. Set in
688	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
689	RTCPUID idEnteredCpu;
690
691	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
692	struct
693	{
694	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
695	unsigned cPages;
696	} TlbShootdown;
697
698	/** For saving stack space, the disassembler state is allocated here instead of
699	* on the stack.
700	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
701	union
702	{
703	/** The disassembler scratch space. */
704	DISCPUSTATE DisState;
705	/** Padding. */
706	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
707	};
708
709	RTUINT padding2[1];
710
711	STAMPROFILEADV StatEntry;
712	STAMPROFILEADV StatExit1;
713	STAMPROFILEADV StatExit2;
714	#if 1 /* temporary for tracking down darwin issues. */
715	STAMPROFILEADV StatExit2Sub1;
716	STAMPROFILEADV StatExit2Sub2;
717	STAMPROFILEADV StatExit2Sub3;
718	#endif
719	STAMPROFILEADV StatInGC;
720
721	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
722	STAMPROFILEADV StatWorldSwitch3264;
723	#endif
724
725	STAMCOUNTER StatIntInject;
726
727	STAMCOUNTER StatExitShadowNM;
728	STAMCOUNTER StatExitGuestNM;
729	STAMCOUNTER StatExitShadowPF;
730	STAMCOUNTER StatExitGuestPF;
731	STAMCOUNTER StatExitGuestUD;
732	STAMCOUNTER StatExitGuestSS;
733	STAMCOUNTER StatExitGuestNP;
734	STAMCOUNTER StatExitGuestGP;
735	STAMCOUNTER StatExitGuestDE;
736	STAMCOUNTER StatExitGuestDB;
737	STAMCOUNTER StatExitGuestMF;
738	STAMCOUNTER StatExitInvpg;
739	STAMCOUNTER StatExitInvd;
740	STAMCOUNTER StatExitCpuid;
741	STAMCOUNTER StatExitRdtsc;
742	STAMCOUNTER StatExitRdpmc;
743	STAMCOUNTER StatExitCli;
744	STAMCOUNTER StatExitSti;
745	STAMCOUNTER StatExitPushf;
746	STAMCOUNTER StatExitPopf;
747	STAMCOUNTER StatExitIret;
748	STAMCOUNTER StatExitInt;
749	STAMCOUNTER StatExitCRxWrite[16];
750	STAMCOUNTER StatExitCRxRead[16];
751	STAMCOUNTER StatExitDRxWrite;
752	STAMCOUNTER StatExitDRxRead;
753	STAMCOUNTER StatExitRdmsr;
754	STAMCOUNTER StatExitWrmsr;
755	STAMCOUNTER StatExitCLTS;
756	STAMCOUNTER StatExitHlt;
757	STAMCOUNTER StatExitMwait;
758	STAMCOUNTER StatExitLMSW;
759	STAMCOUNTER StatExitIOWrite;
760	STAMCOUNTER StatExitIORead;
761	STAMCOUNTER StatExitIOStringWrite;
762	STAMCOUNTER StatExitIOStringRead;
763	STAMCOUNTER StatExitIrqWindow;
764	STAMCOUNTER StatExitMaxResume;
765	STAMCOUNTER StatExitPreemptPending;
766	STAMCOUNTER StatIntReinject;
767	STAMCOUNTER StatPendingHostIrq;
768
769	STAMCOUNTER StatFlushPageManual;
770	STAMCOUNTER StatFlushPhysPageManual;
771	STAMCOUNTER StatFlushTLBManual;
772	STAMCOUNTER StatFlushPageInvlpg;
773	STAMCOUNTER StatFlushTLBWorldSwitch;
774	STAMCOUNTER StatNoFlushTLBWorldSwitch;
775	STAMCOUNTER StatFlushTLBCRxChange;
776	STAMCOUNTER StatFlushASID;
777	STAMCOUNTER StatFlushTLBInvlpga;
778	STAMCOUNTER StatTlbShootdown;
779	STAMCOUNTER StatTlbShootdownFlush;
780
781	STAMCOUNTER StatSwitchGuestIrq;
782	STAMCOUNTER StatSwitchToR3;
783
784	STAMCOUNTER StatTSCOffset;
785	STAMCOUNTER StatTSCIntercept;
786
787	STAMCOUNTER StatExitReasonNPF;
788	STAMCOUNTER StatDRxArmed;
789	STAMCOUNTER StatDRxContextSwitch;
790	STAMCOUNTER StatDRxIOCheck;
791
792
793	#ifdef VBOX_WITH_STATISTICS
794	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
795	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
796	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
797	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
798	#endif
799	} HWACCMCPU;
800	/** Pointer to HWACCM VM instance data. */
801	typedef HWACCMCPU *PHWACCMCPU;
802
803
804	#ifdef IN_RING0
805
806	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
807	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
808
809
810	#ifdef VBOX_STRICT
811	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
812	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
813	#else
814	#define HWACCMDumpRegs(a, b ,c) do { } while (0)
815	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
816	#endif
817
818	/* Dummy callback handlers. */
819	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
820	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
821	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
822	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
823	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
824	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
825	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
826	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
827	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
828	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
829
830	# ifdef VBOX_WITH_KERNEL_USING_XMM
831	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
832	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
833	# endif
834
835	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
836	/**
837	* Gets 64-bit GDTR and IDTR on darwin.
838	* @param pGdtr Where to store the 64-bit GDTR.
839	* @param pIdtr Where to store the 64-bit IDTR.
840	*/
841	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
842
843	/**
844	* Gets 64-bit CR3 on darwin.
845	* @returns CR3
846	*/
847	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
848	# endif
849
850	#endif /* IN_RING0 */
851
852	/** @} */
853
854	RT_C_DECLS_END
855
856	#endif
857

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 21990

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