HWACCMInternal.h@ 21780

Last change on this file since 21780 was 21709, checked in by vboxsync, 16 years ago
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1	/* $Id: HWACCMInternal.h 21709 2009-07-17 16:07:35Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36	#include <iprt/avl.h>
37
38	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
39	/* Enable 64 bits guest support. */
40	# define VBOX_ENABLE_64_BITS_GUESTS
41	#endif
42
43	#define VMX_USE_CACHED_VMCS_ACCESSES
44	#define HWACCM_VMX_EMULATE_REALMODE
45	#define HWACCM_VTX_WITH_EPT
46	#define HWACCM_VTX_WITH_VPID
47
48	RT_C_DECLS_BEGIN
49
50
51	/** @defgroup grp_hwaccm_int Internal
52	* @ingroup grp_hwaccm
53	* @internal
54	* @{
55	*/
56
57
58	/** Maximum number of exit reason statistics counters. */
59	#define MAX_EXITREASON_STAT 0x100
60	#define MASK_EXITREASON_STAT 0xff
61	#define MASK_INJECT_IRQ_STAT 0xff
62
63	/** @name Changed flags
64	* These flags are used to keep track of which important registers that
65	* have been changed since last they were reset.
66	* @{
67	*/
68	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
69	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
70	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
71	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
72	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
73	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
74	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
75	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
76	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
77	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
78	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
79	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
80
81	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
82	\| HWACCM_CHANGED_GUEST_CR0 \
83	\| HWACCM_CHANGED_GUEST_CR3 \
84	\| HWACCM_CHANGED_GUEST_CR4 \
85	\| HWACCM_CHANGED_GUEST_GDTR \
86	\| HWACCM_CHANGED_GUEST_IDTR \
87	\| HWACCM_CHANGED_GUEST_LDTR \
88	\| HWACCM_CHANGED_GUEST_TR \
89	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
90	\| HWACCM_CHANGED_GUEST_FPU \
91	\| HWACCM_CHANGED_GUEST_DEBUG \
92	\| HWACCM_CHANGED_HOST_CONTEXT)
93
94	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
95	\| HWACCM_CHANGED_GUEST_CR0 \
96	\| HWACCM_CHANGED_GUEST_CR3 \
97	\| HWACCM_CHANGED_GUEST_CR4 \
98	\| HWACCM_CHANGED_GUEST_GDTR \
99	\| HWACCM_CHANGED_GUEST_IDTR \
100	\| HWACCM_CHANGED_GUEST_LDTR \
101	\| HWACCM_CHANGED_GUEST_TR \
102	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
103	\| HWACCM_CHANGED_GUEST_DEBUG \
104	\| HWACCM_CHANGED_GUEST_FPU)
105
106	/** @} */
107
108	/** @name Intercepted traps
109	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
110	* Currently #NM and #PF only
111	*/
112	#ifdef VBOX_STRICT
113	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
114	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
115	#else
116	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
117	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
118	#endif
119	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
120	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
121	/** @} */
122
123
124	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
125	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
126
127	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
128	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
129	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
130	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
131	/** Total guest mapped memory needed. */
132	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
133
134	/* Enable for TPR guest patching. */
135	//#define VBOX_HWACCM_WITH_GUEST_PATCHING
136
137	/** HWACCM SSM version
138	*/
139	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
140	#define HWACCM_SSM_VERSION 5
141	#define HWACCM_SSM_VERSION_NO_PATCHING 4
142	#else
143	#define HWACCM_SSM_VERSION 4
144	#define HWACCM_SSM_VERSION_NO_PATCHING 4
145	#endif
146	#define HWACCM_SSM_VERSION_2_0_X 3
147
148	/* Per-cpu information. (host) */
149	typedef struct
150	{
151	RTCPUID idCpu;
152
153	RTR0MEMOBJ pMemObj;
154	/* Current ASID (AMD-V)/VPID (Intel) */
155	uint32_t uCurrentASID;
156	/* TLB flush count */
157	uint32_t cTLBFlushes;
158
159	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
160	bool fFlushTLB;
161
162	/** Configured for VT-x or AMD-V. */
163	bool fConfigured;
164
165	/** In use by our code. (for power suspend) */
166	volatile bool fInUse;
167	} HWACCM_CPUINFO;
168	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
169
170	/* VT-x capability qword. */
171	typedef union
172	{
173	struct
174	{
175	uint32_t disallowed0;
176	uint32_t allowed1;
177	} n;
178	uint64_t u;
179	} VMX_CAPABILITY;
180
181	typedef enum
182	{
183	HWACCMPENDINGIO_INVALID = 0,
184	HWACCMPENDINGIO_PORT_READ,
185	HWACCMPENDINGIO_PORT_WRITE,
186	HWACCMPENDINGIO_STRING_READ,
187	HWACCMPENDINGIO_STRING_WRITE,
188	/** The usual 32-bit paranoia. */
189	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
190	} HWACCMPENDINGIO;
191
192
193	typedef enum
194	{
195	HWACCMTPRINSTR_READ,
196	HWACCMTPRINSTR_READ_SHR4,
197	HWACCMTPRINSTR_WRITE_REG,
198	HWACCMTPRINSTR_WRITE_IMM,
199	HWACCMTPRINSTR_JUMP_REPLACEMENT,
200	/** The usual 32-bit paranoia. */
201	HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
202	} HWACCMTPRINSTR;
203
204	typedef struct
205	{
206	/** The key is the address of patched instruction. (32 bits GC ptr) */
207	AVLOU32NODECORE Core;
208	/** Original opcode. */
209	uint8_t aOpcode[16];
210	/** Instruction size. */
211	uint32_t cbOp;
212	/** Replacement opcode. */
213	uint8_t aNewOpcode[16];
214	/** Replacement instruction size. */
215	uint32_t cbNewOp;
216	/** Instruction type. */
217	HWACCMTPRINSTR enmType;
218	/** Source operand. */
219	uint32_t uSrcOperand;
220	/** Destination operand. */
221	uint32_t uDstOperand;
222	/** Number of times the instruction caused a fault. */
223	uint32_t cFaults;
224	/** Patch address of the jump replacement. */
225	RTGCPTR32 pJumpTarget;
226	} HWACCMTPRPATCH;
227	/** Pointer to HWACCMTPRPATCH. */
228	typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
229
230	/**
231	* Switcher function, HC to RC.
232	*
233	* @param pVM The VM handle.
234	* @returns Return code indicating the action to take.
235	*/
236	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
237	/** Pointer to switcher function. */
238	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
239
240	/**
241	* HWACCM VM Instance data.
242	* Changes to this must checked against the padding of the cfgm union in VM!
243	*/
244	typedef struct HWACCM
245	{
246	/** Set when we've initialized VMX or SVM. */
247	bool fInitialized;
248
249	/** Set when hardware acceleration is allowed. */
250	bool fAllowed;
251
252	/** Set if nested paging is enabled. */
253	bool fNestedPaging;
254
255	/** Set if nested paging is allowed. */
256	bool fAllowNestedPaging;
257
258	/** Set if we can support 64-bit guests or not. */
259	bool fAllow64BitGuests;
260
261	/** Set if an IO-APIC is configured for this VM. */
262	bool fHasIoApic;
263
264	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
265	* naturally. */
266	bool padding[2];
267
268	/** And mask for copying register contents. */
269	uint64_t u64RegisterMask;
270
271	/** Maximum ASID allowed. */
272	RTUINT uMaxASID;
273
274	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
275	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
276	uint32_t cMaxResumeLoops;
277
278	/** Guest allocated memory for patching purposes. */
279	RTGCPTR pGuestPatchMem;
280	/** Current free pointer inside the patch block. */
281	RTGCPTR pFreeGuestPatchMem;
282	/** Size of the guest patch memory block. */
283	uint32_t cbGuestPatchMem;
284	uint32_t uPadding1;
285
286	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
287	/** 32 to 64 bits switcher entrypoint. */
288	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
289
290	/* AMD-V 64 bits vmrun handler */
291	RTRCPTR pfnSVMGCVMRun64;
292
293	/* VT-x 64 bits vmlaunch handler */
294	RTRCPTR pfnVMXGCStartVM64;
295
296	/* RC handler to setup the 64 bits FPU state. */
297	RTRCPTR pfnSaveGuestFPU64;
298
299	/* RC handler to setup the 64 bits debug state. */
300	RTRCPTR pfnSaveGuestDebug64;
301
302	/* Test handler */
303	RTRCPTR pfnTest64;
304
305	RTRCPTR uAlignment[2];
306	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
307	uint32_t u32Alignment[1]; */
308	#endif
309
310	struct
311	{
312	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
313	bool fSupported;
314
315	/** Set when we've enabled VMX. */
316	bool fEnabled;
317
318	/** Set if VPID is supported. */
319	bool fVPID;
320
321	/** Set if VT-x VPID is allowed. */
322	bool fAllowVPID;
323
324	/** Virtual address of the TSS page used for real mode emulation. */
325	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
326
327	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
328	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
329
330	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
331	RTR0MEMOBJ pMemObjAPIC;
332	/** Physical address of the APIC physical page (serves for filtering accesses). */
333	RTHCPHYS pAPICPhys;
334	/** Virtual address of the APIC physical page (serves for filtering accesses). */
335	R0PTRTYPE(uint8_t *) pAPIC;
336
337	/** R0 memory object for the MSR bitmap (1 page). */
338	RTR0MEMOBJ pMemObjMSRBitmap;
339	/** Physical address of the MSR bitmap (1 page). */
340	RTHCPHYS pMSRBitmapPhys;
341	/** Virtual address of the MSR bitmap (1 page). */
342	R0PTRTYPE(uint8_t *) pMSRBitmap;
343
344	/** R0 memory object for the MSR entry load page (guest MSRs). */
345	RTR0MEMOBJ pMemObjMSREntryLoad;
346	/** Physical address of the MSR entry load page (guest MSRs). */
347	RTHCPHYS pMSREntryLoadPhys;
348	/** Virtual address of the MSR entry load page (guest MSRs). */
349	R0PTRTYPE(uint8_t *) pMSREntryLoad;
350
351	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
352	RTR0MEMOBJ pMemObjScratch;
353	RTHCPHYS pScratchPhys;
354	R0PTRTYPE(uint8_t *) pScratch;
355	#endif
356	/** R0 memory object for the MSR exit store page (guest MSRs). */
357	RTR0MEMOBJ pMemObjMSRExitStore;
358	/** Physical address of the MSR exit store page (guest MSRs). */
359	RTHCPHYS pMSRExitStorePhys;
360	/** Virtual address of the MSR exit store page (guest MSRs). */
361	R0PTRTYPE(uint8_t *) pMSRExitStore;
362
363	/** R0 memory object for the MSR exit load page (host MSRs). */
364	RTR0MEMOBJ pMemObjMSRExitLoad;
365	/** Physical address of the MSR exit load page (host MSRs). */
366	RTHCPHYS pMSRExitLoadPhys;
367	/** Virtual address of the MSR exit load page (host MSRs). */
368	R0PTRTYPE(uint8_t *) pMSRExitLoad;
369
370	/** Ring 0 handlers for VT-x. */
371	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
372
373	/** Host CR4 value (set by ring-0 VMX init) */
374	uint64_t hostCR4;
375
376	/** VMX MSR values */
377	struct
378	{
379	uint64_t feature_ctrl;
380	uint64_t vmx_basic_info;
381	VMX_CAPABILITY vmx_pin_ctls;
382	VMX_CAPABILITY vmx_proc_ctls;
383	VMX_CAPABILITY vmx_proc_ctls2;
384	VMX_CAPABILITY vmx_exit;
385	VMX_CAPABILITY vmx_entry;
386	uint64_t vmx_misc;
387	uint64_t vmx_cr0_fixed0;
388	uint64_t vmx_cr0_fixed1;
389	uint64_t vmx_cr4_fixed0;
390	uint64_t vmx_cr4_fixed1;
391	uint64_t vmx_vmcs_enum;
392	uint64_t vmx_eptcaps;
393	} msr;
394
395	/** Flush types for invept & invvpid; they depend on capabilities. */
396	VMX_FLUSH enmFlushPage;
397	VMX_FLUSH enmFlushContext;
398	} vmx;
399
400	struct
401	{
402	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
403	bool fSupported;
404	/** Set when we've enabled SVM. */
405	bool fEnabled;
406	/** Set if erratum 170 affects the AMD cpu. */
407	bool fAlwaysFlushTLB;
408	/** Set when TPR patching is active. */
409	bool fTPRPatchingActive;
410
411	/** R0 memory object for the IO bitmap (12kb). */
412	RTR0MEMOBJ pMemObjIOBitmap;
413	/** Physical address of the IO bitmap (12kb). */
414	RTHCPHYS pIOBitmapPhys;
415	/** Virtual address of the IO bitmap. */
416	R0PTRTYPE(void *) pIOBitmap;
417
418	/** R0 memory object for the MSR bitmap (8kb). */
419	RTR0MEMOBJ pMemObjMSRBitmap;
420	/** Physical address of the MSR bitmap (8kb). */
421	RTHCPHYS pMSRBitmapPhys;
422	/** Virtual address of the MSR bitmap. */
423	R0PTRTYPE(void *) pMSRBitmap;
424
425	/** SVM revision. */
426	uint32_t u32Rev;
427
428	/** SVM feature bits from cpuid 0x8000000a */
429	uint32_t u32Features;
430
431	/**
432	* AVL tree with all patches (active or disabled) sorted by guest instruction address
433	*/
434	AVLOU32TREE PatchTree;
435	uint32_t cPatches;
436	HWACCMTPRPATCH aPatches[64];
437	} svm;
438
439	struct
440	{
441	uint32_t u32AMDFeatureECX;
442	uint32_t u32AMDFeatureEDX;
443	} cpuid;
444
445	/** Saved error from detection */
446	int32_t lLastError;
447
448	/** HWACCMR0Init was run */
449	bool fHWACCMR0Init;
450	} HWACCM;
451	/** Pointer to HWACCM VM instance data. */
452	typedef HWACCM *PHWACCM;
453
454	/* Maximum number of cached entries. */
455	#define VMCSCACHE_MAX_ENTRY 128
456
457	/* Structure for storing read and write VMCS actions. */
458	typedef struct VMCSCACHE
459	{
460	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
461	/* Magic marker for searching in crash dumps. */
462	uint8_t aMagic[16];
463	uint64_t uMagic;
464	uint64_t u64TimeEntry;
465	uint64_t u64TimeSwitch;
466	uint64_t cResume;
467	uint64_t interPD;
468	uint64_t pSwitcher;
469	uint32_t uPos;
470	uint32_t idCpu;
471	#endif
472	/* CR2 is saved here for EPT syncing. */
473	uint64_t cr2;
474	struct
475	{
476	uint32_t cValidEntries;
477	uint32_t uAlignment;
478	uint32_t aField[VMCSCACHE_MAX_ENTRY];
479	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
480	} Write;
481	struct
482	{
483	uint32_t cValidEntries;
484	uint32_t uAlignment;
485	uint32_t aField[VMCSCACHE_MAX_ENTRY];
486	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
487	} Read;
488	#ifdef DEBUG
489	struct
490	{
491	RTHCPHYS pPageCpuPhys;
492	RTHCPHYS pVMCSPhys;
493	RTGCPTR pCache;
494	RTGCPTR pCtx;
495	} TestIn;
496	struct
497	{
498	RTHCPHYS pVMCSPhys;
499	RTGCPTR pCache;
500	RTGCPTR pCtx;
501	uint64_t eflags;
502	uint64_t cr8;
503	} TestOut;
504	struct
505	{
506	uint64_t param1;
507	uint64_t param2;
508	uint64_t param3;
509	uint64_t param4;
510	} ScratchPad;
511	#endif
512	} VMCSCACHE;
513	/** Pointer to VMCSCACHE. */
514	typedef VMCSCACHE *PVMCSCACHE;
515
516	/** VMX StartVM function. */
517	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
518	/** Pointer to a VMX StartVM function. */
519	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
520
521	/** SVM VMRun function. */
522	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
523	/** Pointer to a SVM VMRun function. */
524	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
525
526	/**
527	* HWACCM VMCPU Instance data.
528	*/
529	typedef struct HWACCMCPU
530	{
531	/** Old style FPU reporting trap mask override performed (optimization) */
532	bool fFPUOldStyleOverride;
533
534	/** Set if we don't have to flush the TLB on VM entry. */
535	bool fResumeVM;
536
537	/** Set if we need to flush the TLB during the world switch. */
538	bool fForceTLBFlush;
539
540	/** Set when we're using VT-x or AMD-V at that moment. */
541	bool fActive;
542
543	/** HWACCM_CHANGED_* flags. */
544	RTUINT fContextUseFlags;
545
546	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
547	RTCPUID idLastCpu;
548
549	/* TLB flush count */
550	RTUINT cTLBFlushes;
551
552	/* Current ASID in use by the VM */
553	RTUINT uCurrentASID;
554
555	struct
556	{
557	/** R0 memory object for the VM control structure (VMCS). */
558	RTR0MEMOBJ pMemObjVMCS;
559	/** Physical address of the VM control structure (VMCS). */
560	RTHCPHYS pVMCSPhys;
561	/** Virtual address of the VM control structure (VMCS). */
562	R0PTRTYPE(void *) pVMCS;
563
564	/** Ring 0 handlers for VT-x. */
565	PFNHWACCMVMXSTARTVM pfnStartVM;
566
567	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
568	uint64_t proc_ctls;
569
570	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
571	uint64_t proc_ctls2;
572
573	/** R0 memory object for the virtual APIC page for TPR caching. */
574	RTR0MEMOBJ pMemObjVAPIC;
575	/** Physical address of the virtual APIC page for TPR caching. */
576	RTHCPHYS pVAPICPhys;
577	/** Virtual address of the virtual APIC page for TPR caching. */
578	R0PTRTYPE(uint8_t *) pVAPIC;
579
580	/** Current CR0 mask. */
581	uint64_t cr0_mask;
582	/** Current CR4 mask. */
583	uint64_t cr4_mask;
584
585	/** Current EPTP. */
586	RTHCPHYS GCPhysEPTP;
587
588	/** VMCS cache. */
589	VMCSCACHE VMCSCache;
590
591	/** Real-mode emulation state. */
592	struct
593	{
594	X86EFLAGS eflags;
595	uint32_t fValid;
596	} RealMode;
597
598	struct
599	{
600	uint64_t u64VMCSPhys;
601	uint32_t ulVMCSRevision;
602	uint32_t ulInstrError;
603	uint32_t ulExitReason;
604	RTCPUID idEnteredCpu;
605	RTCPUID idCurrentCpu;
606	uint32_t padding;
607	} lasterror;
608
609	/** The last seen guest paging mode (by VT-x). */
610	PGMMODE enmLastSeenGuestMode;
611	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
612	PGMMODE enmCurrGuestMode;
613	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
614	PGMMODE enmPrevGuestMode;
615	} vmx;
616
617	struct
618	{
619	/** R0 memory object for the host VM control block (VMCB). */
620	RTR0MEMOBJ pMemObjVMCBHost;
621	/** Physical address of the host VM control block (VMCB). */
622	RTHCPHYS pVMCBHostPhys;
623	/** Virtual address of the host VM control block (VMCB). */
624	R0PTRTYPE(void *) pVMCBHost;
625
626	/** R0 memory object for the VM control block (VMCB). */
627	RTR0MEMOBJ pMemObjVMCB;
628	/** Physical address of the VM control block (VMCB). */
629	RTHCPHYS pVMCBPhys;
630	/** Virtual address of the VM control block (VMCB). */
631	R0PTRTYPE(void *) pVMCB;
632
633	/** Ring 0 handlers for VT-x. */
634	PFNHWACCMSVMVMRUN pfnVMRun;
635
636	} svm;
637
638	/** Event injection state. */
639	struct
640	{
641	uint32_t fPending;
642	uint32_t errCode;
643	uint64_t intInfo;
644	} Event;
645
646	/** IO Block emulation state. */
647	struct
648	{
649	bool fEnabled;
650	uint8_t u8Align[7];
651
652	/** RIP at the start of the io code we wish to emulate in the recompiler. */
653	RTGCPTR GCPtrFunctionEip;
654
655	uint64_t cr0;
656	} EmulateIoBlock;
657
658	struct
659	{
660	/* Pending IO operation type. */
661	HWACCMPENDINGIO enmType;
662	uint32_t uPadding;
663	RTGCPTR GCPtrRip;
664	RTGCPTR GCPtrRipNext;
665	union
666	{
667	struct
668	{
669	unsigned uPort;
670	unsigned uAndVal;
671	unsigned cbSize;
672	} Port;
673	uint64_t aRaw[2];
674	} s;
675	} PendingIO;
676
677	/** Currenty shadow paging mode. */
678	PGMMODE enmShadowMode;
679
680	/** The CPU ID of the CPU currently owning the VMCS. Set in
681	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
682	RTCPUID idEnteredCpu;
683
684	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
685	struct
686	{
687	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
688	unsigned cPages;
689	} TlbShootdown;
690
691	/** For saving stack space, the disassembler state is allocated here instead of
692	* on the stack.
693	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
694	union
695	{
696	/** The disassembler scratch space. */
697	DISCPUSTATE DisState;
698	/** Padding. */
699	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
700	};
701
702	RTUINT padding2[1];
703
704	STAMPROFILEADV StatEntry;
705	STAMPROFILEADV StatExit1;
706	STAMPROFILEADV StatExit2;
707	#if 1 /* temporary for tracking down darwin issues. */
708	STAMPROFILEADV StatExit2Sub1;
709	STAMPROFILEADV StatExit2Sub2;
710	STAMPROFILEADV StatExit2Sub3;
711	#endif
712	STAMPROFILEADV StatInGC;
713
714	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
715	STAMPROFILEADV StatWorldSwitch3264;
716	#endif
717
718	STAMCOUNTER StatIntInject;
719
720	STAMCOUNTER StatExitShadowNM;
721	STAMCOUNTER StatExitGuestNM;
722	STAMCOUNTER StatExitShadowPF;
723	STAMCOUNTER StatExitGuestPF;
724	STAMCOUNTER StatExitGuestUD;
725	STAMCOUNTER StatExitGuestSS;
726	STAMCOUNTER StatExitGuestNP;
727	STAMCOUNTER StatExitGuestGP;
728	STAMCOUNTER StatExitGuestDE;
729	STAMCOUNTER StatExitGuestDB;
730	STAMCOUNTER StatExitGuestMF;
731	STAMCOUNTER StatExitInvpg;
732	STAMCOUNTER StatExitInvd;
733	STAMCOUNTER StatExitCpuid;
734	STAMCOUNTER StatExitRdtsc;
735	STAMCOUNTER StatExitRdpmc;
736	STAMCOUNTER StatExitCli;
737	STAMCOUNTER StatExitSti;
738	STAMCOUNTER StatExitPushf;
739	STAMCOUNTER StatExitPopf;
740	STAMCOUNTER StatExitIret;
741	STAMCOUNTER StatExitInt;
742	STAMCOUNTER StatExitCRxWrite[16];
743	STAMCOUNTER StatExitCRxRead[16];
744	STAMCOUNTER StatExitDRxWrite;
745	STAMCOUNTER StatExitDRxRead;
746	STAMCOUNTER StatExitRdmsr;
747	STAMCOUNTER StatExitWrmsr;
748	STAMCOUNTER StatExitCLTS;
749	STAMCOUNTER StatExitHlt;
750	STAMCOUNTER StatExitMwait;
751	STAMCOUNTER StatExitLMSW;
752	STAMCOUNTER StatExitIOWrite;
753	STAMCOUNTER StatExitIORead;
754	STAMCOUNTER StatExitIOStringWrite;
755	STAMCOUNTER StatExitIOStringRead;
756	STAMCOUNTER StatExitIrqWindow;
757	STAMCOUNTER StatExitMaxResume;
758	STAMCOUNTER StatExitPreemptPending;
759	STAMCOUNTER StatIntReinject;
760	STAMCOUNTER StatPendingHostIrq;
761
762	STAMCOUNTER StatFlushPageManual;
763	STAMCOUNTER StatFlushPhysPageManual;
764	STAMCOUNTER StatFlushTLBManual;
765	STAMCOUNTER StatFlushPageInvlpg;
766	STAMCOUNTER StatFlushTLBWorldSwitch;
767	STAMCOUNTER StatNoFlushTLBWorldSwitch;
768	STAMCOUNTER StatFlushTLBCRxChange;
769	STAMCOUNTER StatFlushASID;
770	STAMCOUNTER StatFlushTLBInvlpga;
771	STAMCOUNTER StatTlbShootdown;
772	STAMCOUNTER StatTlbShootdownFlush;
773
774	STAMCOUNTER StatSwitchGuestIrq;
775	STAMCOUNTER StatSwitchToR3;
776
777	STAMCOUNTER StatTSCOffset;
778	STAMCOUNTER StatTSCIntercept;
779
780	STAMCOUNTER StatExitReasonNPF;
781	STAMCOUNTER StatDRxArmed;
782	STAMCOUNTER StatDRxContextSwitch;
783	STAMCOUNTER StatDRxIOCheck;
784
785
786	#ifdef VBOX_WITH_STATISTICS
787	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
788	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
789	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
790	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
791	#endif
792	} HWACCMCPU;
793	/** Pointer to HWACCM VM instance data. */
794	typedef HWACCMCPU *PHWACCMCPU;
795
796
797	#ifdef IN_RING0
798
799	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
800	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
801
802
803	#ifdef VBOX_STRICT
804	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
805	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
806	#else
807	#define HWACCMDumpRegs(a, b ,c) do { } while (0)
808	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
809	#endif
810
811	/* Dummy callback handlers. */
812	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
813	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
814	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
815	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
816	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
817	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
818	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
819	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
820	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
821	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
822
823	# ifdef VBOX_WITH_KERNEL_USING_XMM
824	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
825	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
826	# endif
827
828	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
829	/**
830	* Gets 64-bit GDTR and IDTR on darwin.
831	* @param pGdtr Where to store the 64-bit GDTR.
832	* @param pIdtr Where to store the 64-bit IDTR.
833	*/
834	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
835
836	/**
837	* Gets 64-bit CR3 on darwin.
838	* @returns CR3
839	*/
840	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
841	# endif
842
843	#endif /* IN_RING0 */
844
845	/** @} */
846
847	RT_C_DECLS_END
848
849	#endif
850

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 21780

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