HWACCM.cpp@ 9354

Last change on this file since 9354 was 9354, checked in by vboxsync, 16 years ago

Added CPUMGetCPUVendor.
Added CPUMCPUIDFEATURE_NXE, CPUMCPUIDFEATURE_LONG_MODE, CPUMCPUIDFEATURE_LAHF & CPUMCPUIDFEATURE_SYSCALL cpuid feature bits.

Enable the required cpuid feature bits in 64 bits mode.

Property svn:eol-style set to native
Property svn:keywords set to Id

File size: 38.0 KB

Line
1	/* $Id: HWACCM.cpp 9354 2008-06-03 13:45:14Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/hwacc_vmx.h>
34	#include <VBox/hwacc_svm.h>
35	#include "HWACCMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/err.h>
38	#include <VBox/param.h>
39	#include <VBox/patm.h>
40	#include <VBox/csam.h>
41	#include <VBox/selm.h>
42
43	#include <iprt/assert.h>
44	#include <VBox/log.h>
45	#include <iprt/asm.h>
46	#include <iprt/string.h>
47	#include <iprt/thread.h>
48
49	/* Uncomment to enable experimental nested paging. */
50	//#define VBOX_WITH_NESTED_PAGING
51
52	/*******************************************************************************
53	* Internal Functions *
54	*******************************************************************************/
55	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
56	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
57
58
59	/**
60	* Initializes the HWACCM.
61	*
62	* @returns VBox status code.
63	* @param pVM The VM to operate on.
64	*/
65	HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
66	{
67	LogFlow(("HWACCMR3Init\n"));
68
69	/*
70	* Assert alignment and sizes.
71	*/
72	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
73	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
74
75	/* Some structure checks. */
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
77	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
78	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
79	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
80
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
84	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
85	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
86	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
87	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
88
89
90	/*
91	* Register the saved state data unit.
92	*/
93	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
94	NULL, hwaccmR3Save, NULL,
95	NULL, hwaccmR3Load, NULL);
96	if (VBOX_FAILURE(rc))
97	return rc;
98
99	/* Misc initialisation. */
100	pVM->hwaccm.s.vmx.fSupported = false;
101	pVM->hwaccm.s.svm.fSupported = false;
102	pVM->hwaccm.s.vmx.fEnabled = false;
103	pVM->hwaccm.s.svm.fEnabled = false;
104
105	pVM->hwaccm.s.fActive = false;
106	pVM->hwaccm.s.fNestedPaging = false;
107
108	/* On first entry we'll sync everything. */
109	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
110
111	pVM->hwaccm.s.vmx.cr0_mask = 0;
112	pVM->hwaccm.s.vmx.cr4_mask = 0;
113
114	/*
115	* Statistics.
116	*/
117	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
118	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
119	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
120
121	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
122	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
123	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
124	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
125	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
126	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
127	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
128	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
129	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
130	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
131	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
132	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
133	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
134	STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
135	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
136	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
137	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
138	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
139	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
140	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
141	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
142	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
143	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
144	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
145	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
146	STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
147
148	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
149	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
150
151	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
152	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
153	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
154
155	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Virt/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
156	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPhysPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Phys/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
157	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
158	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
159	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
160	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
161	STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
162	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
163
164	STAM_REG(pVM, &pVM->hwaccm.s.StatTSCOffset, STAMTYPE_COUNTER, "/HWACCM/TSC/Offset", STAMUNIT_OCCURENCES, "Nr of occurances");
165	STAM_REG(pVM, &pVM->hwaccm.s.StatTSCIntercept, STAMTYPE_COUNTER, "/HWACCM/TSC/Intercept", STAMUNIT_OCCURENCES, "Nr of occurances");
166
167	pVM->hwaccm.s.pStatExitReason = 0;
168
169	#ifdef VBOX_WITH_STATISTICS
170	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
171	AssertRC(rc);
172	if (VBOX_SUCCESS(rc))
173	{
174	for (int i=0;i<MAX_EXITREASON_STAT;i++)
175	{
176	char szName[64];
177	RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
178	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
179	AssertRC(rc);
180	}
181	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, "/HWACCM/Exit/Reason/#NPF", STAMUNIT_OCCURENCES, "Exit reason");
182	AssertRC(rc);
183	}
184	pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
185	Assert(pVM->hwaccm.s.pStatExitReasonR0);
186	#endif
187
188	/* Disabled by default. */
189	pVM->fHWACCMEnabled = false;
190
191	/* HWACCM support must be explicitely enabled in the configuration file. */
192	pVM->hwaccm.s.fAllowed = false;
193	CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
194
195	return VINF_SUCCESS;
196	}
197
198
199	/**
200	* Turns off normal raw mode features
201	*
202	* @param pVM The VM to operate on.
203	*/
204	static void hwaccmr3DisableRawMode(PVM pVM)
205	{
206	/* Disable PATM & CSAM. */
207	PATMR3AllowPatching(pVM, false);
208	CSAMDisableScanning(pVM);
209
210	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
211	SELMR3DisableMonitoring(pVM);
212	TRPMR3DisableMonitoring(pVM);
213
214	/* The hidden selector registers are now valid. */
215	CPUMSetHiddenSelRegsValid(pVM, true);
216
217	/* Disable the switcher code (safety precaution). */
218	VMMR3DisableSwitcher(pVM);
219
220	/* Disable mapping of the hypervisor into the shadow page table. */
221	PGMR3ChangeShwPDMappings(pVM, false);
222
223	/* Disable the switcher */
224	VMMR3DisableSwitcher(pVM);
225
226	if (pVM->hwaccm.s.fNestedPaging)
227	{
228	/* Reinit the paging mode to force the new shadow mode. */
229	PGMR3ChangeMode(pVM, PGMMODE_REAL);
230	}
231	}
232
233	/**
234	* Initialize VT-x or AMD-V.
235	*
236	* @returns VBox status code.
237	* @param pVM The VM handle.
238	*/
239	HWACCMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
240	{
241	int rc;
242
243	if ( !pVM->hwaccm.s.vmx.fSupported
244	&& !pVM->hwaccm.s.svm.fSupported)
245	{
246	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
247	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
248	return VINF_SUCCESS;
249	}
250
251	/*
252	* Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
253	* because it turns off paging, which is not allowed in VMX root mode.
254	*
255	* To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
256	*
257	*/
258	/* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
259	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
260	if (VBOX_FAILURE(rc))
261	{
262	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
263	LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
264	/* Invert the selection */
265	pVM->hwaccm.s.fAllowed ^= 1;
266	LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
267
268	if (pVM->hwaccm.s.fAllowed)
269	{
270	if (pVM->hwaccm.s.vmx.fSupported)
271	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
272	else
273	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
274	}
275	else
276	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
277	}
278
279	if (pVM->hwaccm.s.fAllowed == false)
280	return VINF_SUCCESS; /* disabled */
281
282	Assert(!pVM->fHWACCMEnabled);
283
284	if (pVM->hwaccm.s.vmx.fSupported)
285	{
286	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
287
288	if ( pVM->hwaccm.s.fInitialized == false
289	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
290	{
291	uint64_t val;
292
293	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
294	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
295	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
296	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
297	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
298	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
299	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
300	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
301
302	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
303	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
304	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
305	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
306	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
307	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
308	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
309	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
310	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
311	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
312	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
313
314	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
315	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
316	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
317	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
318	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
319	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
320	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
321	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
322	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
323	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
324	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
325	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
326	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
327	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
328	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
329	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
330	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
331	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
332	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
333	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
334	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
335	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
336	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
337	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
338	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
339	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
340	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
341	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
342	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
343	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
344	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
345	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
346	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
347	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
348	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
349	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
350	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
351	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
352	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
353	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
354	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
355	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
356	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
357	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
358	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
359	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
360	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
361	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
362	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
363	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
364	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
365	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
366	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
367	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
368	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
369	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
370	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
371	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
372	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
373	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
374	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
375	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
376	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
377	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
378	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
379	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
380	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
381
382	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
383	val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
384	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
385	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
386	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
387	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
388	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
389	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
390	val = pVM->hwaccm.s.vmx.msr.vmx_entry;
391	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
392	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
393	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
394	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
395	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
396	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
397
398	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
399	val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
400	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
401	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
402	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
403	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
404	val = pVM->hwaccm.s.vmx.msr.vmx_exit;
405	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
406	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
407	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
408	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
409
410	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
411	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
412	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
413	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
414	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
415
416	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
417	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
418	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
419	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
420	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
421
422	/* Only try once. */
423	pVM->hwaccm.s.fInitialized = true;
424
425	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
426	AssertRC(rc);
427	if (rc == VINF_SUCCESS)
428	{
429	pVM->fHWACCMEnabled = true;
430	pVM->hwaccm.s.vmx.fEnabled = true;
431	hwaccmr3DisableRawMode(pVM);
432
433	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
434	#ifdef VBOX_WITH_64_BITS_GUESTS
435	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
436	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
437	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
438	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
439	#endif
440	LogRel(("HWACCM: VMX enabled!\n"));
441	}
442	else
443	{
444	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
445	LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
446	pVM->fHWACCMEnabled = false;
447	}
448	}
449	}
450	else
451	if (pVM->hwaccm.s.svm.fSupported)
452	{
453	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
454
455	if (pVM->hwaccm.s.fInitialized == false)
456	{
457	/* Erratum 170 which requires a forced TLB flush for each world switch:
458	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
459	*
460	* All BH-G1/2 and DH-G1/2 models include a fix:
461	* Athlon X2: 0x6b 1/2
462	* 0x68 1/2
463	* Athlon 64: 0x7f 1
464	* 0x6f 2
465	* Sempron: 0x7f 1/2
466	* 0x6f 2
467	* 0x6c 2
468	* 0x7c 2
469	* Turion 64: 0x68 2
470	*
471	*/
472	uint32_t u32Dummy;
473	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
474	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
475	u32BaseFamily= (u32Version >> 8) & 0xf;
476	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
477	u32Model = ((u32Version >> 4) & 0xf);
478	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
479	u32Stepping = u32Version & 0xf;
480	if ( u32Family == 0xf
481	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
482	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
483	{
484	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
485	}
486
487	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
488	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
489	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
490	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
491	LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
492
493	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
494	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
495	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
496	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
497	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
498	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
499	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
500	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
501	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
502	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
503
504	/* Only try once. */
505	pVM->hwaccm.s.fInitialized = true;
506
507	#ifdef VBOX_WITH_NESTED_PAGING
508	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
509	pVM->hwaccm.s.fNestedPaging = true;
510	#endif
511
512	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
513	AssertRC(rc);
514	if (rc == VINF_SUCCESS)
515	{
516	pVM->fHWACCMEnabled = true;
517	pVM->hwaccm.s.svm.fEnabled = true;
518
519	hwaccmr3DisableRawMode(pVM);
520	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
521	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
522	#ifdef VBOX_WITH_64_BITS_GUESTS
523	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
524	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
525	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
526	#endif
527	}
528	else
529	{
530	pVM->fHWACCMEnabled = false;
531	}
532	}
533	}
534	return VINF_SUCCESS;
535	}
536
537	/**
538	* Applies relocations to data and code managed by this
539	* component. This function will be called at init and
540	* whenever the VMM need to relocate it self inside the GC.
541	*
542	* @param pVM The VM.
543	*/
544	HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
545	{
546	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
547	return;
548	}
549
550
551	/**
552	* Checks hardware accelerated raw mode is allowed.
553	*
554	* @returns boolean
555	* @param pVM The VM to operate on.
556	*/
557	HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
558	{
559	return pVM->hwaccm.s.fAllowed;
560	}
561
562
563	/**
564	* Notification callback which is called whenever there is a chance that a CR3
565	* value might have changed.
566	* This is called by PGM.
567	*
568	* @param pVM The VM to operate on.
569	* @param enmShadowMode New paging mode.
570	*/
571	HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
572	{
573	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
574	}
575
576	/**
577	* Terminates the HWACCM.
578	*
579	* Termination means cleaning up and freeing all resources,
580	* the VM it self is at this point powered off or suspended.
581	*
582	* @returns VBox status code.
583	* @param pVM The VM to operate on.
584	*/
585	HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
586	{
587	if (pVM->hwaccm.s.pStatExitReason)
588	{
589	MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
590	pVM->hwaccm.s.pStatExitReason = 0;
591	}
592	return 0;
593	}
594
595
596	/**
597	* The VM is being reset.
598	*
599	* For the HWACCM component this means that any GDT/LDT/TSS monitors
600	* needs to be removed.
601	*
602	* @param pVM VM handle.
603	*/
604	HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
605	{
606	LogFlow(("HWACCMR3Reset:\n"));
607
608	if (pVM->fHWACCMEnabled)
609	hwaccmr3DisableRawMode(pVM);
610
611	/* On first entry we'll sync everything. */
612	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
613
614	pVM->hwaccm.s.vmx.cr0_mask = 0;
615	pVM->hwaccm.s.vmx.cr4_mask = 0;
616
617	pVM->hwaccm.s.Event.fPending = false;
618	}
619
620	/**
621	* Checks if we can currently use hardware accelerated raw mode.
622	*
623	* @returns boolean
624	* @param pVM The VM to operate on.
625	* @param pCtx Partial VM execution context
626	*/
627	HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
628	{
629	Assert(pVM->fHWACCMEnabled);
630
631	/* AMD SVM supports real & protected mode with or without paging. */
632	if (pVM->hwaccm.s.svm.fEnabled)
633	{
634	pVM->hwaccm.s.fActive = true;
635	return true;
636	}
637
638	/* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
639	* (but do we really care?)
640	*/
641
642	pVM->hwaccm.s.fActive = false;
643
644	/** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
645
646	#ifndef HWACCM_VMX_EMULATE_ALL
647	/* Too early for VMX. */
648	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
649	return false;
650
651	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
652	if (pCtx->csHid.Attr.n.u1Present == 0)
653	return false;
654	if (pCtx->ssHid.Attr.n.u1Present == 0)
655	return false;
656	#endif
657
658	if (pVM->hwaccm.s.vmx.fEnabled)
659	{
660	uint32_t mask;
661
662	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
663	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
664	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
665	mask &= ~X86_CR0_NE;
666	#ifdef HWACCM_VMX_EMULATE_ALL
667	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
668	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
669	#endif
670	if ((pCtx->cr0 & mask) != mask)
671	return false;
672
673	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
674	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
675	if ((pCtx->cr0 & mask) != 0)
676	return false;
677
678	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
679	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
680	mask &= ~X86_CR4_VMXE;
681	if ((pCtx->cr4 & mask) != mask)
682	return false;
683
684	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
685	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
686	if ((pCtx->cr4 & mask) != 0)
687	return false;
688
689	pVM->hwaccm.s.fActive = true;
690	return true;
691	}
692
693	return false;
694	}
695
696	/**
697	* Checks if we are currently using hardware accelerated raw mode.
698	*
699	* @returns boolean
700	* @param pVM The VM to operate on.
701	*/
702	HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
703	{
704	return pVM->hwaccm.s.fActive;
705	}
706
707	/**
708	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
709	*
710	* @returns boolean
711	* @param pVM The VM to operate on.
712	*/
713	HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
714	{
715	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
716	}
717
718	/**
719	* Execute state save operation.
720	*
721	* @returns VBox status code.
722	* @param pVM VM Handle.
723	* @param pSSM SSM operation handle.
724	*/
725	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
726	{
727	int rc;
728
729	Log(("hwaccmR3Save:\n"));
730
731	/*
732	* Save the basic bits - fortunately all the other things can be resynced on load.
733	*/
734	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
735	AssertRCReturn(rc, rc);
736	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
737	AssertRCReturn(rc, rc);
738	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
739	AssertRCReturn(rc, rc);
740
741	return VINF_SUCCESS;
742	}
743
744
745	/**
746	* Execute state load operation.
747	*
748	* @returns VBox status code.
749	* @param pVM VM Handle.
750	* @param pSSM SSM operation handle.
751	* @param u32Version Data layout version.
752	*/
753	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
754	{
755	int rc;
756
757	Log(("hwaccmR3Load:\n"));
758
759	/*
760	* Validate version.
761	*/
762	if (u32Version != HWACCM_SSM_VERSION)
763	{
764	Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
765	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
766	}
767	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
768	AssertRCReturn(rc, rc);
769	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
770	AssertRCReturn(rc, rc);
771	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
772	AssertRCReturn(rc, rc);
773
774	return VINF_SUCCESS;
775	}
776
777
778
779

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 9354

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