VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 9082

Last change on this file since 9082 was 9082, checked in by vboxsync, 16 years ago

More statistics
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 37.1 KB
Line 
1/* $Id: HWACCM.cpp 9082 2008-05-23 13:14:15Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/hwacc_vmx.h>
34#include <VBox/hwacc_svm.h>
35#include "HWACCMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/err.h>
38#include <VBox/param.h>
39#include <VBox/patm.h>
40#include <VBox/csam.h>
41#include <VBox/selm.h>
42
43#include <iprt/assert.h>
44#include <VBox/log.h>
45#include <iprt/asm.h>
46#include <iprt/string.h>
47#include <iprt/thread.h>
48
49/* Uncomment to enable experimental nested paging. */
50//#define VBOX_WITH_NESTED_PAGING
51
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
56static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
57
58
59/**
60 * Initializes the HWACCM.
61 *
62 * @returns VBox status code.
63 * @param pVM The VM to operate on.
64 */
65HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
66{
67 LogFlow(("HWACCMR3Init\n"));
68
69 /*
70 * Assert alignment and sizes.
71 */
72 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
73 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
74
75 /* Some structure checks. */
76 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
77 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
78 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
79 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
80
81 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
82 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
83 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
84 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
85 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
86 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
87 AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
88
89
90 /*
91 * Register the saved state data unit.
92 */
93 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
94 NULL, hwaccmR3Save, NULL,
95 NULL, hwaccmR3Load, NULL);
96 if (VBOX_FAILURE(rc))
97 return rc;
98
99 /* Misc initialisation. */
100 pVM->hwaccm.s.vmx.fSupported = false;
101 pVM->hwaccm.s.svm.fSupported = false;
102 pVM->hwaccm.s.vmx.fEnabled = false;
103 pVM->hwaccm.s.svm.fEnabled = false;
104
105 pVM->hwaccm.s.fActive = false;
106 pVM->hwaccm.s.fNestedPaging = false;
107
108 /* On first entry we'll sync everything. */
109 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
110
111 pVM->hwaccm.s.vmx.cr0_mask = 0;
112 pVM->hwaccm.s.vmx.cr4_mask = 0;
113
114 /*
115 * Statistics.
116 */
117 STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
118 STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
119 STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
120
121 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
122 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
123 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
124 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
125 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
126 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
127 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
128 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
129 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
130 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
131 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
132 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
133 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
134 STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
135 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
136 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
137 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
138 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
139 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
140 STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
141 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
142 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
143 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
144 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
145 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
146 STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
147
148 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
149 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
150
151 STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
152 STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
153 STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
154
155 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
156 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
157 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
158 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
159 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
160 STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
161 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
162
163 STAM_REG(pVM, &pVM->hwaccm.s.StatTSCOffset, STAMTYPE_COUNTER, "/HWACCM/TSC/Offset", STAMUNIT_OCCURENCES, "Nr of occurances");
164 STAM_REG(pVM, &pVM->hwaccm.s.StatTSCIntercept, STAMTYPE_COUNTER, "/HWACCM/TSC/Intercept", STAMUNIT_OCCURENCES, "Nr of occurances");
165
166 pVM->hwaccm.s.pStatExitReason = 0;
167
168#ifdef VBOX_WITH_STATISTICS
169 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
170 AssertRC(rc);
171 if (VBOX_SUCCESS(rc))
172 {
173 for (int i=0;i<MAX_EXITREASON_STAT;i++)
174 {
175 char szName[64];
176 RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
177 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
178 AssertRC(rc);
179 }
180 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, "/HWACCM/Exit/Reason/#NPF", STAMUNIT_OCCURENCES, "Exit reason");
181 AssertRC(rc);
182 }
183 pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
184 Assert(pVM->hwaccm.s.pStatExitReasonR0);
185#endif
186
187 /* Disabled by default. */
188 pVM->fHWACCMEnabled = false;
189
190 /* HWACCM support must be explicitely enabled in the configuration file. */
191 pVM->hwaccm.s.fAllowed = false;
192 CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
193
194 return VINF_SUCCESS;
195}
196
197
198/**
199 * Turns off normal raw mode features
200 *
201 * @param pVM The VM to operate on.
202 */
203static void hwaccmr3DisableRawMode(PVM pVM)
204{
205 /* Disable PATM & CSAM. */
206 PATMR3AllowPatching(pVM, false);
207 CSAMDisableScanning(pVM);
208
209 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
210 SELMR3DisableMonitoring(pVM);
211 TRPMR3DisableMonitoring(pVM);
212
213 /* The hidden selector registers are now valid. */
214 CPUMSetHiddenSelRegsValid(pVM, true);
215
216 /* Disable the switcher code (safety precaution). */
217 VMMR3DisableSwitcher(pVM);
218
219 /* Disable mapping of the hypervisor into the shadow page table. */
220 PGMR3ChangeShwPDMappings(pVM, false);
221
222 /* Disable the switcher */
223 VMMR3DisableSwitcher(pVM);
224
225 if (pVM->hwaccm.s.fNestedPaging)
226 {
227 /* Reinit the paging mode to force the new shadow mode. */
228 PGMR3ChangeMode(pVM, PGMMODE_REAL);
229 }
230}
231
232/**
233 * Initialize VT-x or AMD-V.
234 *
235 * @returns VBox status code.
236 * @param pVM The VM handle.
237 */
238HWACCMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
239{
240 int rc;
241
242 if ( !pVM->hwaccm.s.vmx.fSupported
243 && !pVM->hwaccm.s.svm.fSupported)
244 {
245 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
246 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
247 return VINF_SUCCESS;
248 }
249
250 /*
251 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
252 * because it turns off paging, which is not allowed in VMX root mode.
253 *
254 * To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
255 *
256 */
257 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
258 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
259 if (VBOX_FAILURE(rc))
260 {
261 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
262 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
263 /* Invert the selection */
264 pVM->hwaccm.s.fAllowed ^= 1;
265 LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
266
267 if (pVM->hwaccm.s.fAllowed)
268 {
269 if (pVM->hwaccm.s.vmx.fSupported)
270 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
271 else
272 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
273 }
274 else
275 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
276 }
277
278 if (pVM->hwaccm.s.fAllowed == false)
279 return VINF_SUCCESS; /* disabled */
280
281 Assert(!pVM->fHWACCMEnabled);
282
283 if (pVM->hwaccm.s.vmx.fSupported)
284 {
285 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
286
287 if ( pVM->hwaccm.s.fInitialized == false
288 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
289 {
290 uint64_t val;
291
292 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
293 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
294 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
295 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
296 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
297 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
298 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
299 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
300
301 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
302 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
303 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
304 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
305 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
306 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
307 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
308 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
309 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
310 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
311 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
312
313 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
314 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
315 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
316 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
317 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
318 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
319 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
320 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
321 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
322 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
323 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
324 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
325 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
326 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
327 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
328 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
329 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
330 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
331 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
332 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
333 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
334 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
335 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
336 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
337 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
338 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
339 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
340 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
341 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
342 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
343 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
344 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
345 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
346 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
347 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
348 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
349 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
350 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
351 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
352 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
353 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
354 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
355 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
356 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
357 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
358 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
359 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
360 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
361 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
362 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
363 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
364 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
365 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
366 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
367 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
368 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
369 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
370 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
371 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
372 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
373 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
374 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
375 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
376 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
377 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
378 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
379 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
380
381 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
382 val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
383 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
384 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
385 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
386 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
387 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
388 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
389 val = pVM->hwaccm.s.vmx.msr.vmx_entry;
390 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
391 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
392 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
393 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
394 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
395 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
396
397 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
398 val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
399 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
400 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
401 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
402 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
403 val = pVM->hwaccm.s.vmx.msr.vmx_exit;
404 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
405 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
406 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
407 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
408
409 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
410 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
411 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
412 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
413 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
414
415 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
416 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
417 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
418 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
419 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
420
421 /* Only try once. */
422 pVM->hwaccm.s.fInitialized = true;
423
424 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
425 AssertRC(rc);
426 if (rc == VINF_SUCCESS)
427 {
428 pVM->fHWACCMEnabled = true;
429 pVM->hwaccm.s.vmx.fEnabled = true;
430 hwaccmr3DisableRawMode(pVM);
431
432 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
433 LogRel(("HWACCM: VMX enabled!\n"));
434 }
435 else
436 {
437 LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
438 LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
439 pVM->fHWACCMEnabled = false;
440 }
441 }
442 }
443 else
444 if (pVM->hwaccm.s.svm.fSupported)
445 {
446 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
447
448 if (pVM->hwaccm.s.fInitialized == false)
449 {
450 /* Erratum 170 which requires a forced TLB flush for each world switch:
451 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
452 *
453 * All BH-G1/2 and DH-G1/2 models include a fix:
454 * Athlon X2: 0x6b 1/2
455 * 0x68 1/2
456 * Athlon 64: 0x7f 1
457 * 0x6f 2
458 * Sempron: 0x7f 1/2
459 * 0x6f 2
460 * 0x6c 2
461 * 0x7c 2
462 * Turion 64: 0x68 2
463 *
464 */
465 uint32_t u32Dummy;
466 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
467 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
468 u32BaseFamily= (u32Version >> 8) & 0xf;
469 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
470 u32Model = ((u32Version >> 4) & 0xf);
471 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
472 u32Stepping = u32Version & 0xf;
473 if ( u32Family == 0xf
474 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
475 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
476 {
477 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
478 }
479
480 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
481 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
482 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
483 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
484 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
485
486 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
487 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
488 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
489 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
490 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
491 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
492 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
493 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
494 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
495 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
496
497 /* Only try once. */
498 pVM->hwaccm.s.fInitialized = true;
499
500#ifdef VBOX_WITH_NESTED_PAGING
501 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
502 pVM->hwaccm.s.fNestedPaging = true;
503#endif
504
505 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
506 AssertRC(rc);
507 if (rc == VINF_SUCCESS)
508 {
509 pVM->fHWACCMEnabled = true;
510 pVM->hwaccm.s.svm.fEnabled = true;
511
512 hwaccmr3DisableRawMode(pVM);
513 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
514 }
515 else
516 {
517 pVM->fHWACCMEnabled = false;
518 }
519 }
520 }
521 return VINF_SUCCESS;
522}
523
524/**
525 * Applies relocations to data and code managed by this
526 * component. This function will be called at init and
527 * whenever the VMM need to relocate it self inside the GC.
528 *
529 * @param pVM The VM.
530 */
531HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
532{
533 Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
534 return;
535}
536
537
538/**
539 * Checks hardware accelerated raw mode is allowed.
540 *
541 * @returns boolean
542 * @param pVM The VM to operate on.
543 */
544HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
545{
546 return pVM->hwaccm.s.fAllowed;
547}
548
549
550/**
551 * Notification callback which is called whenever there is a chance that a CR3
552 * value might have changed.
553 * This is called by PGM.
554 *
555 * @param pVM The VM to operate on.
556 * @param enmShadowMode New paging mode.
557 */
558HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
559{
560 pVM->hwaccm.s.enmShadowMode = enmShadowMode;
561}
562
563/**
564 * Terminates the HWACCM.
565 *
566 * Termination means cleaning up and freeing all resources,
567 * the VM it self is at this point powered off or suspended.
568 *
569 * @returns VBox status code.
570 * @param pVM The VM to operate on.
571 */
572HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
573{
574 if (pVM->hwaccm.s.pStatExitReason)
575 {
576 MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
577 pVM->hwaccm.s.pStatExitReason = 0;
578 }
579 return 0;
580}
581
582
583/**
584 * The VM is being reset.
585 *
586 * For the HWACCM component this means that any GDT/LDT/TSS monitors
587 * needs to be removed.
588 *
589 * @param pVM VM handle.
590 */
591HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
592{
593 LogFlow(("HWACCMR3Reset:\n"));
594
595 if (pVM->fHWACCMEnabled)
596 hwaccmr3DisableRawMode(pVM);
597
598 /* On first entry we'll sync everything. */
599 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
600
601 pVM->hwaccm.s.vmx.cr0_mask = 0;
602 pVM->hwaccm.s.vmx.cr4_mask = 0;
603
604 pVM->hwaccm.s.Event.fPending = false;
605}
606
607/**
608 * Checks if we can currently use hardware accelerated raw mode.
609 *
610 * @returns boolean
611 * @param pVM The VM to operate on.
612 * @param pCtx Partial VM execution context
613 */
614HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
615{
616 Assert(pVM->fHWACCMEnabled);
617
618 /* AMD SVM supports real & protected mode with or without paging. */
619 if (pVM->hwaccm.s.svm.fEnabled)
620 {
621 pVM->hwaccm.s.fActive = true;
622 return true;
623 }
624
625 /* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
626 * (but do we really care?)
627 */
628
629 pVM->hwaccm.s.fActive = false;
630
631 /** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
632
633#ifndef HWACCM_VMX_EMULATE_ALL
634 /* Too early for VMX. */
635 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
636 return false;
637
638 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
639 if (pCtx->csHid.Attr.n.u1Present == 0)
640 return false;
641 if (pCtx->ssHid.Attr.n.u1Present == 0)
642 return false;
643#endif
644
645 if (pVM->hwaccm.s.vmx.fEnabled)
646 {
647 uint32_t mask;
648
649 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
650 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
651 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
652 mask &= ~X86_CR0_NE;
653#ifdef HWACCM_VMX_EMULATE_ALL
654 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
655 mask &= ~(X86_CR0_PG|X86_CR0_PE);
656#endif
657 if ((pCtx->cr0 & mask) != mask)
658 return false;
659
660 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
661 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
662 if ((pCtx->cr0 & mask) != 0)
663 return false;
664
665 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
666 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
667 mask &= ~X86_CR4_VMXE;
668 if ((pCtx->cr4 & mask) != mask)
669 return false;
670
671 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
672 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
673 if ((pCtx->cr4 & mask) != 0)
674 return false;
675
676 pVM->hwaccm.s.fActive = true;
677 return true;
678 }
679
680 return false;
681}
682
683/**
684 * Checks if we are currently using hardware accelerated raw mode.
685 *
686 * @returns boolean
687 * @param pVM The VM to operate on.
688 */
689HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
690{
691 return pVM->hwaccm.s.fActive;
692}
693
694/**
695 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
696 *
697 * @returns boolean
698 * @param pVM The VM to operate on.
699 */
700HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
701{
702 return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
703}
704
705/**
706 * Execute state save operation.
707 *
708 * @returns VBox status code.
709 * @param pVM VM Handle.
710 * @param pSSM SSM operation handle.
711 */
712static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
713{
714 int rc;
715
716 Log(("hwaccmR3Save:\n"));
717
718 /*
719 * Save the basic bits - fortunately all the other things can be resynced on load.
720 */
721 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
722 AssertRCReturn(rc, rc);
723 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
724 AssertRCReturn(rc, rc);
725 rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
726 AssertRCReturn(rc, rc);
727
728 return VINF_SUCCESS;
729}
730
731
732/**
733 * Execute state load operation.
734 *
735 * @returns VBox status code.
736 * @param pVM VM Handle.
737 * @param pSSM SSM operation handle.
738 * @param u32Version Data layout version.
739 */
740static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
741{
742 int rc;
743
744 Log(("hwaccmR3Load:\n"));
745
746 /*
747 * Validate version.
748 */
749 if (u32Version != HWACCM_SSM_VERSION)
750 {
751 Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
752 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
753 }
754 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
755 AssertRCReturn(rc, rc);
756 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
757 AssertRCReturn(rc, rc);
758 rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
759 AssertRCReturn(rc, rc);
760
761 return VINF_SUCCESS;
762}
763
764
765
766
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette